SYS`l`EMASTER User Manual Sacramento, C~lifornla, USA
Contents
1. TS 06 RTS oT RTS 4 AL 05 05 5 9 HEAD 1 04 04 2 36 5 CIS 5 9 5 5 3 2 es LOAD ce 5 one 2NI j DI 6 OSR 5 TE DSR 6 INDEX 1 z L 1 DCD 50 5 8 sh AB 8 10 KE 100 UF amp OTR 9 3 M DTR 20 zd 1 NC SAER OET u4 o INT i 17980 4 04 TXC JE 40 22 N C 13 SELECT ia oe 26 AB o8 pu 2 E25 12 2 5 2 N C 13GNO 7 SELECT 2 4 36 RO i TORQ 5 4 23 Se 4 UATA 4 2 n L 3 Maux 7 7 6 TRACK RITE PROT READ 46 Q 4 DATA Phase Locked MOTOR 50 Loop Flexible Disk Controller Serial Ports 15 Data Separator C omawm JP d ant GET SYSTE MASTER flr Je EOE REVISION 2 TELETEK M 13319 ON 10009 05 23 417 016 515 518 013 012 ult 210 7 15 4 3 934 32 9 42 4i 95 86 8 53 87 3 34 ts cil 2 51 3 2 4 ed lg 1 05 6 114 EN ne Ul 03 2 a4 7 02 giiia _ 01 rd2. Y 16 DL Open 17 WP intact 18 NP pen 19 52 irace intact 20 1 3 21 051 4 Select appropriate drive address 22 DJs 2 3 4 Open instail 2 resistor terminator modules into the last drive in the daisy chain cach drive requires 24 volts at U YA and 5 volts at 1 14 Required Pre write Compensation 12
3. Array 9 RA 13 RAG RAS 4 11211 5 RAZ 4 24 RAI U 5 4 RAS 5 4 ue AWR 14 6 15 pe e v M 064 WoT RD 06 05 0403 02 DO e mc Mad Lass lt gt 19 _ Im 419 3 B ROM 13 Als 4 16 i JMP 5 4 E 46 s 4 S gt 4 7 Ar n uu U26 L9 pinsTRT Pi AG AS ROM 1 DECODE 1 0 Select OR 10099 CLEATPRINT Parallel Parts 2 o0 p RESET P4 Io 6 5 PIO 5 15 ii 37 CTC at 6 e 5 29 p2 30 9 0 485 IE lt 9 86 1 0 1 Adjacent to J 3 Contro Register 5 er a 5 0 Et SYSTEMASTER o a c REVISION 2 p RESET 2 4 15 nt 2 4576M a 1 0 ROM Select RAM PIO CTC Control Register OnAwM REVISED Flexible Disk Control UPD 765 AC EIA Serial Port B SIO Seria Port A 4 z i 3 77 Pin 4 2 f 12 6 4 n 58 RES 557 RESET 2 DIN 30 4450 RXDB MNS 2 2 TT 5 20 S Y QA CK fs N C ject T 4 TC P2 3 5 6 ABOVE 256 P2 3DOUT 5090 lt 59 5 43 SYNCB DUAL T K f 13 22
4. U 42 and U 43 to select the upper 8 bits of the memory address When the positive pulse in the delay line reaches the 49 tap it clocks the remaining section of U 54 which generates a CAS signal to complete the RAM access After the RAM access time has elapsed data lines are stable at the RAM outputs When the positive pulse in the delay line reaches the 1003 tap the first section of U 19 is cleared which resets the RAS signal This allows the RAM RAS circuit to pre charge in preparation for the next memory access As long as CAS is low the RAM outputs are stable When the CPU terminates the memory request 1 resets U 54 which returns the address multiplexers to the low order address lines and resets the CAS signal A memory write operation does not begin until WR from the CPU is active This ensures that the R WR line to the RAM ICs is active when the RAM ICs are accessed This precaution allows the DATA IN and DATA OUT lines of the RAM ICs to be connected together simplifying the memory circuitry A refresh operation begins when RFSH and MREQ from the CPU are both active low A normal memory cycle is started but the address multiplexer and CAS circuits are held idle The CPU outputs a refresh address during this time to refresh one of 128 consecutive locations in the RAM necessary to retain data Because the CPU supplies the refresh address the only RAM devices that can be used are those that are compatible with a 128
5. 16 8 50mA 16v 8 5 mA Workmanship conforms to the requirements of MIL STD 454 Forced air cooling is required OY Un wN S 100 BUS Connections Function 81 16V XRDY NMI SDSB CDSB GND ADSB DODSB pSTVAL pHLDA A5 4 15 12 001 A10 DO4 DO5 DO6 DI2 DI3 DI7 5 1 SOUT SINP SMEMR SHLTA CLOCK GND Pin 51 52 53 54 55 56 57 58 Function 8V 16V GND SLAVE CLR SXTRQ PHANTOM optional MWET GND RDY INT HOLD RESET SYNC pWR AQ A2 7 A13 A14 All DO2 DO3 007 014 DIS DI DIO SINP swo POC GND INSTALLATION Upon receipt of SYSTEMASTER check the shipping package for signs of abuse which may indicate possible damage Check the board physically to look for any parts which may have been damaged during shipping any diskettes were shipped with SYSTEMASTER check the diskettes for signs of damage which might be any bending or signs of a sharp object placed against the diskettes Diskettes are quite fragile and any warping of the surface of the diskette will render it inoperative Notify the shipper of any damage SYSTEMASTER is ready for immediate use upon receipt requires only that the peripherals which will be used with it be connected to the appropriate female connector which will then plug into the headers
6. 424 0 eT d 24 a rp 14 9 4 16 iB 2 A 3 5 STRIC T 5226 44 sHLTA 48 sXTRQ amp 58 pDBIN 78 pSYNC 76 pSTVAL 25 4 pHLDA 6 0 gt d 3 pwRH 77 sOUT 45 ti 12 3 2 MWRT 68 0078 z 24 Ta E ADSB 22 5 100 BUS 3 66 4 RFSH RI 1 S I00 BUS RN 5 XROY 3 WAIT m 72 5 NM 12 Oc 7 NT S RN 6 _ BUSRO P 8 HOLD N INT SLAVE CLR R 43 R 42 ICOK c 26 lt e 8 41 R 47 2K t5 GNO 100 50 CLOCK 49 9 18 16 i6 GND GNO DRAWN EY JP SYSTEMASTER REVISION 2 4 SYSTEMASTER DRIVE INTERFACING controlling a disk drive from SYSTEMASTER proper connections must be made to the disk drive in order for it to be operational The drive options must be configured as outlined in the appropriate manufacturer s section following this introduction Particularly important is the fact that the uPD 765 continuously polls ail drives in the system to keep track of their status With some drives this will interfere with their seek function positioning of the head Thus most drives will have a stepper motor enable option or simultanious seek option that powers the stepper motor
7. drive select 3 for 5 25 drives but is the READY signal for Micropolis drives 4 Pad 2 to 4 8 drive select 3 connected to 5 25 pin 34 This pin is drive select 3 for Micropolis drives or READY for Pertec drives 5 Pad 5 to 3 8 READY connected to 5 25 pin 6 This pin is the READY pin for Micropolis drives 6 Pad 5 to 6 8 READY connected to GROUND Since most 5 25 drives do not provide a READY signal it is neccessary to ground this line 7 Pad 7 to 8 8 drive select 0 connected to 5 25 drive select 9 8 Pad 9 to 8 8 drive select 2 connected to 5 25 drive select g Electrical 1 Multi Drop Bus Multiple drives may be connected to the same host controller as shown in Figure 1 Only one drive is logically connected to the interface at a time 2 Voltage Levels as measured at the driver Logical true Active low 6 to 0 4 Logical false Active high 2 4 to 5 5V 3 Termination Signal lines shall be terminated by one of two resistive networks Either the signal line will pull up resistor of 150 ohms or it will have a pull up resistor of 220 ohms in addition to a 330 ohm resistor connecting the signal to ground 4 Signal Drivers The signal drivers should have open collector output stages capable of sinking a minimum of 40mA at logical true low level with maximum voltage of 0 4 as measured at the driver output 5 Signal Receivers The signal receivers should not unduly load the m
8. pulling inactive the printer will stop the flow of data from the SIO When it is ready to receive more data it reactivates DTR Similarly if Auto Enables is enabled the SIO will not accept information until RTS is active This function is labelled DCD on the SIO chip This is primarily used with a communications link where if signal conditions deteriorate the data may be garbled In summary the handshake lines provide a convenient means of controlling the flow of information in a setial channel Lf any line is pulled inactive transfer ceases RS 232 C Voltage Levels _ logic high a binary ONE or marking condition is any voltage less than 3 volts to minimum of 25 volts logic low a binary ZERO or spacing condition is any voltage greater than 3 volts to a maximum of 25 volts level between 3 and 3 volts is undefined This is called the transition region The maximum transition time between bit cells is four per cent of the basic clock period The maximum voltage rate of change slew rate is 30 volts uSec Thus the maximum RS 232 C transmission speed based on voltage swings of 12 to 12 volts is 50 000 baud 9 Serial Data Timing Prior to transmitting data the signal line is held high or marking It goes low spacing to indicate the start of a character The bits representing the character are then sent Least Significant Bit first then a parity bit if used and finally 2 stop bits T
9. routine must immediately issue a terminal count to the 765 by doing an input from port 14H The DMA controller accesses port 18H to transfer data to or from the 765 This port connects to the DACK DMA acknowledge pin of the 765 The DMA controller is a single channel device which can execute only one series of operations at a time Although it is connected to the uPD765 flexible disk controller when the uPD765 is idle the DMA controller can perform block moves of data between memory and I O devices This is done by reprogramming the control registers of the DMA controller with the appropriate information and forcing the transfer through the use of a special software command 21 Dynamic RAM Control Logic Array LA 1 U15 controls the access to the on board dynamic RAM RAM cycle is started by M1 going low or by MREQ active low in conjunction with RD WR RFSH the RAM select options match RAMEN and the option address jumpers MSTRT goes low Both sections of U 19 a dual J K flip flop are clocked active by the action of MSTRT One section of 019 activates the RAS line of the dynamic RAM ICs RAS clocks the lower 8 bits of the memory address into the RAM ICs The second section of 019 sends a positive pulse into the delay line U 47 The 20 tap of the delay line resets this section of U 19 to terminate the positive pulse and in addition clocks one section of U 54 The output of U 54 causes the address multiplexers
10. to operate at a higher temperature than is necessary 32 TELETEK SYSTEMASTER poara Layout Ex Oe pen e i Som 0 U48 EN am 0 qr ERES LS eu ella 351 U c E18 iU mcam ioi de m M de 0 is 9 u27 EN 016 ji tn 00 oO v ec S pop nn EMIL 5 gs az 9 Ws xis 2 jam I _ zip 22 220 03 21 LEl 640 c2 U i Fs dips UM g 23 RNT 66 9 uts i CO 244 1244 LA4 0 6 448 925 AB RESET 4 ON ROY E8 1 4 5 B 2 Jumpers shown are ES tor 2716 2316 ROM SELECT R WR 73 3 44 4 9 3 AJ 2 4 9 4171 AIl 4 9 0 510 9 8 3 Y ssuwper 58507 saoer TP TEST PONT 580 2 Adjacent tous WAIT STATE 4M 42 ALL MEMORY Select Delete ail jumpers pd fot States CPU Dynamic RAM Control EY ROM P2 Note All resistor values are in ohms SYSTEMASTER REVISION 2 Dynamic
11. 0H FFFFH 1 2 3 Connected 8k EQ00H FFFFH AJ 1 Open AJ 2 Connected AJ 3 Connected 4 2 1 Connected 2 Connected AJ 3 Connected The selectable block of RAM occupies the memory space from 9000H up to the fixed block of RAM The selectable block is enabled when RAMEN islow RAMEN is bit 7 of the control register When disabled the selectable block of RAM is not affected by memory accesses in its memory space NOTE The on board RAM cannot be accessed by off board temporary bus masters IV THEORY OF OPERATION SYSTEMASTER is a single board computer for the S 100 bus It contains 2k 8k bytes of ROM 64k bytes of RAM a flexible disk controller two parallel ports two serial ports a DMA controller a CTC and a CPU With appropriate software SYSTEMASTER comprises a complete stand alone single user computer The following discussion details the operation of the various functional areas SYSTEMASTER Please refer to Appendix A for the board layout and schematics when reading the following information Central Processor Operations The heart of SYSTEMASTER is 4 MHz Z80A CPU It provides the intelligence to operate the on board support chips and to provide the information interchange to the 5 10 bus Connections to the bus are made through tri state buffers and control logic to provide the correct timing signals and status Signals to operate other boards within th
12. ASTER provides one more if the P3 jumper is in place the compensation for tracks 0 42 will be one step less than that in the above table At track 43 and higher write compensation will be equal to the table value This option is provided because most drives require more compensation on the inner tracks where the recording density is higher For 5 1 4 drives which do not have more than 42 tracks select compensation one step greater than that required 14 For example assume an 8 drive which requires 258 nSec compensation and 5 1 4 drive with 46 tracks which requires 250 nSec compensation Option jumper P3 is in place Select 1 Pl 0 P2 0 At Tracks 0 42 5 1 4 compensation is 250 nSec and 8 compensation is 125 nSec For tracks 43 and above the 8 drive will have 250 nSec compensated data Extended Head Load The uPD 765AC floppy disk controller has a maximum head unload time of 240 mSec In some applications this will cause undue amount of head loading and unloading To increase this head unload time and reduce the number of head load actions a 74LS123 monostable can be wired into the head drive circuit With the addition of a 6 volt capacitor the head unload time is extended This increases the life of the media and the heads where there would normally be a great deal of head load activity The following table gives the effective head load time for several different capacitor values Capacitor uF Head Load T
13. H The CPU is interrupted every second and the time is updated The date is also updated if necessary but leap years and turn of the century occurances are not accounted for 11 of the values are kept in binary The user may set or read the time and date by accessing these six bytes of data The following code in a user program will return the address of SEC in the HL register LD C412 select function 12 CALL 48H call BIOS function handler Note that the clock is not initialized on reset is up to the user s software to set the time and date and until they are set they should be considered invalid EPROM RAM Options The on board ROM socket 041 can accommodate 24 or 28 5 or ROMS occupying 2k 4k or 8k bytes of memory space This ROM can originate at 0000H EV00H FOOBH or F800H depending on the setting of the option jumpers on LA 5 ROM Memory Space Options ROM Origin End Space Jumpers 2316 2716 2008H 07FFH 2k E14 to E16 E15 to E17 2332 2732 0000H QFFFH 4k 14 to E16 to E17 2364 2764 IFFFH 8k to E16 to E17 24316 2716 F800H FFFFH 2k E14 to E16 E15 to E17 2332 2732 F000H FFFFH 4k 14 to El6 E13 to E17 2364 2764 E000H FFFFH 8k to 16 to 17 17 The type of ROM used determines the socket and jumpers used at the socket ROM Size Socket Jumpers 2316 2k 24 pin E5 to E8 to E19 E7 to E12 2332 4k 24 ES to Ell E6 to Elg E7 to E12 2364 8
14. Open Juniper Jumper Open Jumper 27 LOADS Jumper Jumper Open pen Jumper Open Open Jumper Open OPEN JESE WE SUGGEST BENDING THE PINS ON THE SHUNT BLOCK AT 4E TO OPEN THEM INSTEAD OF CUTTING THE SHUNT THROUGH install tne termination network I 2f in the last drive only Each drive requires 24 volts at 1 0A and 5 volts at 1 1 Required Pre write Compensation 22 250 ns Snugart 800 801 Disk Drive Required pai PN AM A p 14 16 17 18 19 20 drive configuration Demat OO O DS 1 4 TL 3 4 5 D T2 HL DS RI RR Y 809 801 Jumper Trace intact Trace intact Trace intact Select appropriate drive address Jumper on last drive in system Jumper Open Open Trace intact Trace intact Open Jumper Jumper Open Jumper Open Each drive requires 24 volts at 1 7A 5 volts at 1 0 and 5 volts at 0 07 Note Many not have the drives power supplies for floppy drives do required current capability for 2 or more Shugart Required Pre write compensation 250 ns 13 01 8 Disk Driv Required drive configuration 1 Jumper Open 3 X Jumper 4 7 Jumper 5 HL 5 Jumper 1 Jumper 8 RI Trace intact 9 RR Trace intact i9 Jumper il D Open 12 DC Open 13 25 Jumper 14 DS Open
15. Physically doubie density disk drives do not differ significantly from their single density counterparts Improvements in double density record and playback heads and changes in mechanics often provide less expensive and more durable drives These changes are minor compared to the differences in reading and writing functions Figure 1 reviews encoding methods used in single and double density The standard recording formats are FM for frequency modulation MFM for modified frequency modulation double density and for mcdified modified frequency modulation which is a refinement of MFM Line 1 of Figure 1 indicates the basic clock frequency which designates the bit cell in which information will be passed The next line illustrates a sample of information the line following shows the pulses which generate that information in a single density FM format Notice that information actually sent to and received from the drive is a combination of the basic clock frequency and data pulses Refer to the next line which is Here only the data pulses will be sent to the drive and their orientation within the bit cell determines the value of that particular data pulse a 1 Every is represented by a data pulse that coincides with the basic clock frequency Every l is represented by a pulse that occurs midway between two clock pulses Thus when the data pulse occurs in the middle of bit ceil it is a 1 when it occurs
16. SYSTEMASTER User Manual Copyright c 1982 Teletek Enterprises Inc Sacramento California USA Revision 3 July 1982 III IV V Table of Contents PRODUCT DESCRIPTION SPECIFICATIONS INSTALLATION 3 1 Peripheral Connections Serial Ports Parallel Ports Floppy Disk Drive 3 2 Options Write Compensation Extended Head Load Wait State Generator CTC Timing EPROM RAM Options THEORY OF OPERATION IN CASE OF TROUBLE Appendix A Board Layout Schematics Appendix Disk Drive Interfacing Appendix NEC uPD765 Manual I PRODUCT DESCRIPTION The SYSTEMASTER is microcomputer on a board It incorporates most of the features required in a small computing system including a CPU 64k bytes of RAM serial and parallel I O and a floppy disk controller On board is a Z80A CPU which operates at 4 MHz for high speed efficient processing of information The 280A provides the capability to support many sophisticated applications The interrupt structure of the Z80A is particularly important for systems which perform multiple tasks concurrently The SYSTEMASTER utilizes the structured interrupt system of the 288 in all of its I O capabilities The on board memory of SYSTEMASTER can provide up to 8k bytes of storage in EPROM ROM and 64k bytes of RAM The standard SYSTEMASTER is set up for 2k bytes of EPROM to be used for on board initialization routines and 64k bytes of RAM Options are available a
17. Side one select 16 15 In use control 18 17 Head load 20 19 Index 22 21 Drive ready 24 23 Sector 26 25 Drive select 0 28 27 Drive select 1 30 29 Drive select 2 32 31 Drive select 3 34 33 Direction select 36 35 Step 38 37 Composite write data 40 39 Write gate 42 41 Track Q0 44 43 Write protected 46 45 Composite read d ta 48 47 Separated read data 50 49 Separated read clock Tandon TM100 Disk Drive Required configuration 1 MX Open 2 HS Jumper 3 HM Open 3 NDSO NDS3 Select appropriate drive address Install the termination network 2F in the last drive only Each drive requires 12 volts at 0 9A and 5 volts at 0 6 Required Pre write Compensation none 23 Shugart 850 851 Disk Drive configuration Shunts with next to them are on shunt block at IC location 4E 7 28 29 30 31 32 7333 34 35 36 37 38 24 DC D C I R 5 051 4 HL 05 RI RR Gum Y Z 850 851 A x 1B 2B 3B 4B 25 WP D NPS 51 394 va s DL M TS FS Wr RS RM HLL IT HI Fm Aft ny RF Snunt intact Open Open Jumper Snunt intact Snunt intact Snunt intact Select appropriate drive address Shunt open Open Trace intact Trace intact Open Snunt intact Jumper Open Shunt intact Snunt open Open Jumper Trace intact Open Open Jumper
18. along the top of the board For the particular connections required see the section entitled Peripheral Connections SYSTEMASTER need only be plugged into a standard S 190 bus for power and it will be functional able to utilize the peripherals connected to it with the memory on board The SYSTEMASTER needs to be in a well ventilated area due to the high density of IC s on board Ideally the board should be mounted vertically in a stream of air which will 5e moving across the face of the board Whatever the mounting position cooling is mandatory Bring peripheral cables neatly away from the board with enough slack to prevent any tension being applied to the cable as this may cause the cable to separate from its crimp connection causing intermittent problems For serial console devices SIO B is the primary port With the standard software SIO B can determine the baud rate of a carriage return and thus set the appropriate speed automatically after a reset The serial speed must be standard value between 110 and 19200 baud Note Up to eight carraige returns are required for a terminal operating at 110 baud Also SIO B requires the handshake lines of the RS 232 C interface before it will function See Serial Ports for further information Once the system has been brought up the console port speed may as an option be statically set to allow the system to boot fully on RESET This can be done by running the utili
19. are used with port A Normally port is configured as an output for such parallel items as a printer Under software control port A can be configured as an input or as a bidirectional port where input data and output data well as direction are controlled by the four handshaking lines Port B of the PIO is used in a bit control mode This port is normally used to provide individual control lines for interfacing to parallel devices such as hard disk drives Serial Ports The 280A SIO is used to generate two entirely independent serial ports Both serial ports incorporate all the handshaking lines required by an RS232C data interconnection device Each channel of the SIO is driven by an independent section of the This means that baud rates for the twe channels can be independently selected In fact the baud rates may range anywhere from 45 baud up to 19200 baud These frequencies determined during initialization of the CTC The data lines to and from the SIO channels are buffered by RS 232 C level translators These buffers are also inherently protected from Short circuits on the external lines Both serial ports will interconnect with terminal equipment printer CRT terminal etc using standard insulation displacement connectors Connection to a MODEM requires transposition of all six serial lines as required by the MODEM see Peripheral Connections When connecting to a synchronous MODEM which provides the receiv
20. continuously rather than just when the drive is selected If the drive won t read initially check for this option Drive interfacing deals with the proper connection of functional signals and the satisfying of electrical and mechanical requirements To help ease the shock of transition from the interchanging of vario s disk drives to other host controllers a standard known as ANSI was developed which standardized the means of intercommunication between disk drive and host controller by specifying power requirements and voltage levels edge connector and cable specifications and specific pin numbers of the connector to particular functional signals ANSI Standards Functional signals assigned to specific pin numbers of the connector are shown on the next page for a 5 25 inch disk drive and an 8 inch disk drive Mini Floppy Drives Use of mini floppy drives requires the use of a special 59 to 34 pin adapter board The following is a diagram of this board and its options Eight inch to five and a quarter inch drive p c adaptor board 8 051 9 o 5 25 051 1 o 8 DS3 2 o 4 5 25 DS3 RDY 5 25 DS3 RDY 3 8 RDY 5 o GND 6 o 8 DSB 7 o o 9 8 DS2 8 5 25 DS Options 1 Pad 2 to 1 8 drive select 1 connected to 5 25 drive select 1 2 Pad 1 to 2 8 drive select 2 connected to 5 25 drive select la 3 Pad 2 to 3 8 drive select 3 connected to 5 25 pin 6 Normally this pin is
21. cycle refresh NOTE An extended RESET or Wait State condition will cause a loss of refresh in the on board dynamic RAM Wait State Generator The wait state generator functions by holding the CPU wait input low until one clock cycle after MREQ from the CPU is active U 53 a J K flip flop has its K input connected to MREQ from the CPU The inverted state of MREQ connects to the J input Initially prior to a memory cycle MREQ is high causing U 53 to clock its 0 output low The 0 output of U53 is gated with the desired condition active 1 ROM or all memory accesses The resulting signal is gated with MREQ and connected to the wait input of the CPU If the current CPU cycle meets the desired conditions the wait input of the CPU is held low On the next negative edge of the CPU clock because MREQ is low and the J input of U 53 is now high the 0 output of U 53 will go high This in turn releases the wait input of the CPU allowing completion of the cycle U 53 resets itself at the end of the memory cycle when MREQ again goes inactive ROM I O Decoder U 26 a logic array LA 5 provides the logic necessary to access the on board ROM select I O and control the RAM data buffer When the CPU accesses memory LA 5 decodes the address and option lines to determine if the on board ROM is being accessed If the CPU is accessing ROM the RAM data buffer is held inactive otherwise it is enabled if LA 1 has determ
22. e and transmit clocks the clock inputs to SIO must be connected to the MODEM IO A clocks Jumper Internal CTC E22 to E21 E25 to E24 From MODEM E22 to E23 E25 to E26 The transmit and receive clocks for SIO A are provided by channel Those for SIO are provided by channel 1 25 Floppy Disk Controller Operation The heart of the flexible disk controller is the NEC uPD765AC Capable of single and double density single and double sided 5 1 4 and 8 data recording the 765 provides a flexible reliable disk controller for SYSTEMASTER Circuitry on board SYSTEMASTER supports the 765 in stabilizing the read data from the disk drive compensating data written to the disk drive and buffering status signals to and from the disk drive The following discussion details the circuitry surrounding the 765 To reduce the number of its pins the 765 multiplexes dual Signals on four of its control lines Pin 39 of the 765 selects the seek mode when high and the data read write mode when low One section of U 56 an inverting buffer inverts the signal from pin 39 to enable the appropriate drivers when the 765 is in its seek mode When in the seek mode the 765 positions the disk drive head over the desired track on the diskette this mode the 765 looks at the dual sided and track 9 signals and outputs drive control signals to the direction and step lines In the read write mode these four function lines become write pr
23. e microcomputer The 4MHz clock for the CPU is derived from a 16 2 oscillator Ul6 and a counter IC U39 This circuit also provides clock signals to the disk controller section and a 2MHz Signal for the 5 100 bus The SYSTEMASTER CPU is configured in interrupt mode 2 In this mode a requesting device generates an interrupt and when that interrupt is acknowledged the CPU expects the device to place 8 bit address vector on the data lines The CPU then adds this 8 bit vector with another 8 bit register internal to the CPU to form a 16 bit absolute memory address This address points to a 2 byte location in memory which contains the absolute address of the desired subroutine to service the interrupt In the case of the Z80A DMA SIO PIO and CTC the necessary interrupt vectors are loaded to internal registers during initialization For the case of the floppy controller IC the interrupt vector is simply composed of that vector formed by the pull up resistors on the data lines an FE The Z80 support IC s normally begin on an even memory location because bit is always low during their interrupt response 20 when a device external to the CPU requests an interrupt the external device must provide an interrupt vector on the data bus when interrupt acknowledge status line goes active high The 280A support IC s are series connected to provide priority interrupts The last device in the chain namely the PIO provides an interrupt e
24. he stop bits indicate the end of the character and are always logic ONEs The standard SYSTEMASTER is Set up for 8 data bits no parity and 2 stop bits The value of each character bit is held for the entire length of each bit cell The length in time of each bit cell is the basic clock period equal to the reciprocal of the baud rate Thus for 9600 baud each bit cell is 104 uSec long 0001041 5 1 9690 MODEM Connections If connection to a MODEM is desired then the following connections must be made SYSTEMASTER EIA Direction Function Pin Pin 5 2 OUT Data to MODEM 3 3 IN Data to SYSTEMASTER 11 4 OUT RTS Request To Send 14 CTS Clear To Send 7 6 IN DSR Data Set Ready 13 7 Signal Ground 9 28 OUT DTR Data Terminal Ready IN refers to data sent to SYSTEMASTER and OUT refers to data sent to the MODEM 18 Parallel Ports PIO A 2 4 6 8 18 12 14 16 RESET 5 GND STB B RDY A STB RDY 1 3 5 7 9 11 13 15 D7 D6 D5 D4 D3 D2 01 2 4 6 8 19 GND 01 D2 1 3 5 7 9 D3 D4 07 06 05 These are the connections into the ch p The chip has two parallel ports A and B configured PIO A may be used as an input output bidirectional or control port with four handshake lines PIO B is the same except that it does not have bidirectional capabilties or handshake lines The signals are D D7 8 data lines A STB Strobe input pulse from a device Depending the mode
25. icrocomputer board or as the basis for a high performance multi user multi processing system II SPECIFICATIONS Central processor 280A CPU 4 MH2 operation Memory 64k bytes dynamic RAM bank selectable Uses eight 64k 1 devices 2 5 or faster 128 cycle refresh Serial 280A SIO 2 RS 232C independent operation Speeds from 110 to 19200 baud Timer 280 4 channels 2 used for serial ports 2 used for real time clock Parallel 280A PIO 1 bidirectional port with 4 handshake lines 1 port with 8 independent input or output lines Floppy disk controller NEC uPD 765AC single or double density and single or double sided operation mini or maxi drives ANSI Standard 50 pin connector IBM compatible format DMA 280A DMA controller handles floppy disk transfers Disk data transfer rates Single density 5 1 4 125k bits sec 8 250k bits sec Double density 5 1 4 250k bits sec 8 5Q0k bits sec EPROM ROM 2716 2732 2764 2316 2332 2364 up to 8k bytes total S 100 Bus Bus pins used by tbe SYSTEMASTER are shown on the next page Note the definition of pin 66 as the RFSH signal from the 280 CPU Also note that PHANTOM is an option and requires modification to the standard board Note SYSTEMASTER does not provide 8080 type I O addressing only the lower 8 address lines contain the I O address Dimensions 5 05 x 10 0 excluding edge connector Power requirements 8v 8 2 0 amp
26. ime sec 19 0 5 30 1 4 50 2 3 70 3 2 90 4 1 110 5 0 138 5 9 150 6 8 176 7 7 199 8 6 218 9 5 238 10 4 250 11 3 The time values are approximate normally resistor values are 10 and capacitor values 20 and are derived from the following equation HLT 45 C 1E03 where C is in microFarads To enable the head load option jumper option pin E 19 to E 20 and install the desired capacitor value at location C 12 If this option is not desired then pin E 19 should be connected to E 18 15 Wait State Generator The wait state generator can generate a wait state during all memory accesses Ml accesses or only when the on board ROM is accessed The choice of wait state generation is dictated by the requirements of the system For the standard SYSTEMASTER one wait state is generated for every access to the on board ROM With a faster ROM less than 368 nSec access time the wait State is not needed The following wait state options are available Option Jumper No wait state El open On board ROM only E to 4 All memory El to E3 All memory 1 to B2 NOTE if the RDY or XRDY input ot the S 100 bus is low this will be gated into the CPU wait input causing the CPU to wait until RDY and XRDY are released to an inactive high state CAUTION An extended wait state will cause a loss of refresh to the dynamic RAMs on the SYSTEMASTER CTC Timing The trigger inputs to channels 0 through 2 co
27. in the beginning of a bit cell it is a 0 Look at the next line which represents MMFM This is slight refinement of MFM this instance tke data pulses once again represent I s and O s via their placement within the bit cell However the rules change slightly the preceding data pulse was 9 and the present datum is a then the data pulse will occur the 1355 data pulse was a 1 and the present datum is a the present data pulse does not appear the last data pulse was a 1 the present datum is al that data pulse appears Every time there is a l a data pulse will appear in the middle of a bit cell But whether or not a 6 data pulse occurs depends on the preceding datum Note that the density of data pulses for MFM is almost exactly one half the density of data pulses for FM Thus for the same density of pulses on the diskette MFM will record twice as much information as FM has slightly less dense data pulses than MFM but its complexity of encoding and decoding outweighs the slight advantage it might enjoy due to slightly less density The basic clock frequency for FM encoding is 250 KHz for an 8 inch diskette Wher we delete the clock and leave only the Gata pulses in MFM that clock rate changes to 500 KHz The MFM data transfer rate 15 twice as fast as FM The defisity and the speed are both doubled which means that twice as much information can be stored in the same physical space and manipula
28. ined that on board memory is to be accessed During an I O operation if the CPU address is less than 20H the on board I O decoder is selected If Ml is active at the same time as IORQ an interrupt acknowledge cycle is in process and neither ROM RAM nor I O is selected On board Control Register 0 13 octal D type flip flop provides control for several areas of SYSTEMASTER The output lines of U 13 are Bit Name Function 7 RAMEN When low enables the selectable block of on board RAM 6 ROMEN With JMP controls the on board ROM 5 JMP With ROMEN controls the on board ROM 4 MOT When low turns on the flexible disk drive Spindle motor 3 FL8 When low allows 8 flexible disk data transfers When high 5 1 4 flexible disk data transfers are enabled 0 2 E Not presently used 23 All these bits are reset low when a reset pulse occurs The control register bits are set simultaneously by a CPU output to port 1 The outputs follow the inputs directly Reset Jump After a reset operation SYSTEMASTER begins execution of the instructions in the ROM to initialize the system Because the ROM may reside at 0000H or a higher memory address special circuitry enables the ROM independent of its actual location The outputs of U 13 the on board control register are cleared by a reset pulse Therefore outputs JMP and ROMEN are low This combination causes LA 5 the ROM I O decoder to enable the ROM for any CPU
29. k 24 E5 tO E9 E6 to EL12 E7 to Ell 2716 2k 24 E5 to E8 E6 to E10 E7 to E12 2732 4k 24 5 to Ell to E10 7 to E12 2764 28 to Ell E6 to E7 to El2 The chip select options for the 2316 and 2332 must be specified as follows for the above jumper connections 2316 Pin 18 active low Pin 20 active low Pin 21 active high 2332 Pin 18 active low Pin 20 active low NOTE when the 24 pin 2364 is used underlying RAM cannot be written when the ROM is enabled Except for the 24 pin 2364 when the ROM is enabled either during reset jump or otherwise the underlying RAM can be written to but not read Memory other than that occupied by the ROM can be accessed normally Thus on reset the ROM monitor could copy itself into RAM then disable the ROM and continue execution RAM RAM Select SYSTEMASTER contains 64k bytes of RAM This RAM is partitioned into a fixed and a seiectable block The selectable block can be disabled allowing CPU access to additional external memory The fixed block is always resident in the CPU memory space This combination of fixed and selectable memory accommodates such multi user operating systems as MP M from Digital Research which requires a fixed block of RAM for the operating system 18 size of the fixed block of RAM varied by option jumpers AJ 1 2 and 3 Fixed Block Size Range Jumpers 32k 8000H FFFFH 1 2 3 l6k CO09
30. le that will interface this type of printer SYSTEMASTER Printer Pin Function Pin Function 1 07 1 DATA STB 15 2 D1 13 01 3 D2 11 02 4 D3 9 D3 5 D4 7 D4 6 05 5 5 7 06 3 D6 8 D7 14 ASTB 10 The SYSTEMASTER provides a software strobe to the printer using data bit 7 from PIOA Therefore data bit 8 on the printer is not connected On most printers this bit controls special print modes and should be jumpered to ground to enable normal printing Also remember that there are no drivers on the PIO signal lines therefore the cable length must be kept short less than five feet depending upon your printer termination Floppy Disk Drive Ground Signal Input I Pin Pin Output O Description l 2 Above track 43 3 4 Not used 5 6 Not used 7 8 Above track 43 9 10 i Dual sided 11 12 Not used 13 14 1 15 16 Not used 17 18 Head load 19 20 I Index 21 22 I Ready 23 2 Not used 25 26 O Drive select 60 7 28 Drive select 1 29 30 Q Drive select 2 31 32 Drive select 3 33 34 Direction 35 36 Step pulse 37 38 0 Write data 39 48 Write gate 41 42 I Track 08 43 44 I Write protected 45 46 1 Read data composite 47 48 Not used 49 50 i Motor control Input Output are referenced to SYSTEMASTER Input is a signal from the disk drive to SYSTEMASTER and output is a signal to the disk drive More detailed information regarding floppy disk drive interfacing is a
31. llowing the RAM to be bank switched Providing two independent serial ports the Z80A SIO provides RS232C compatible serial ports which can be operated under interrupt control Both serial ports include full handshaking for connection to external devices as a printer CRT terminal or MODEM Also on board is a counter timer chip which provides software settable clocks for both serial ports and a real time clock The real time clock is used by the software to provide timekeeping functions It normally functions under interrupt control requiring a minimum of overhead This real time clock can be used by software for any time related functions such as time dating of files a stop watch or timing loops for external operations The 280 PIO provides two parallel ports of these two ports is bidirectional with 8 data and 4 handshake lines Normally this port is configured as a printer output but because it is under software control it can be reconfigured by the user to be a device input or a truly bidirectional port The second parallel port has 8 data lines available which can be set independently to be input or output lines Using the NEC 765AC FDC and Zilog 280 DMA ICs SYSTEMASTER provides single and double density data storage on both mini and maxi floppy disk drives providing capabilities which minimize the overhead burden on the software Use of the DMA controller allows the CPU to be available at all times f
32. memory access If the ROM options are set for a ROM location at E090H FOOOH or F800H the first instruction in the ROM should be an absolute jump to the ROM location plus three For example a SYSTEMASTER set up for a 2716 has the ROM options set for an address F8 H first instruction in the ROM is a jump to F803H This sets the CPU program counter to the actual ROM address space While JMP and ROMEN are both active RAM cannot be accessed After the CPU begins executing the ROM in the correct address space RAM can be enabled by setting JMP high if the ROM occupies high address space F000H or higher or setting ROMEN high if the ROM occupies memory starting at 0000H If the RAMEN signal is active low then both ROM and RAM can be accessed at this time In order to disable ROM both signals JMP and ROMEN should be inactive If is addressed at 00 is high and JMP is low then RAMEN must be low to enable ROM To summarize RAMEN JMP Result ROM enabled RAM disabled 2008 ROM enabled RAM enabled 0000 ROM enabled RAM enabled ROM disabled RAM enabled 2008 ROM enabled RAM disabled ROM and RAM disabled He CQ C Ua X e Qe SR pm bY 0 low 1 high X don t care 24 Paraliel Ports The parallel ports consist primarily of the 280 A is used as an 8 bit input output or bidirectional port The four handshaking lines of the PIO
33. nable signal for external devices When this line is high interrupts are enabled for external requests When this line is low external devices must be prevented from generating a response to an interrupt acknowledge signal The vector that external devices place on the bus when combined with the internal high order vector of the CPU must point to a location in memory which provides the absolute address of the subroutine used for servicing that particular interrupt Following is the on board interrupt daisy chain in order of priority 1 2 510 4 PIO DMA Controller SYSTEMASTER incorporateS DMA controller to provide efficient transparent flexible disk data transfer without requiring CPU intervention Interrupts can be enabled during DMA operations Prior to a series of DMA data transfers the DMA controller must be set up as necessary for the particular operation desired No CPU intervention is required during a DMA transfer process At the completion of the series of data transfers the DMA controller will interrupt the CPU At thes time the CPU performs any operations necessary to terminate the data transfer The sequence of operations should be set up the DMA controller for the of bytes to transfer the sector size and the starting memory address for tne transfer and finally send the read or write command to the 765 When the DMA controller interrupts the CPU at the end of the data transfer the interrupt
34. nnect to a 1 2288 MHz source Thus all standard baud rates from 150 to 76 800 can be generated by programming the CTC for the counter mode with a time constant between 1 and 256 0 SIO divider is set for 16 or 32 as necessary For baud rates that are non standard or below 150 use the CTC in the timer mode with a divide by 16 prescaler and the SIO divider set for 16 or 32 To summarize Baud rate 300 to 76 800 510 divider set to 16 in the counter mode time constant set from 1 to 256 Baud rate 150 SIO divider set to 32 CTC in the counter mode time constant set to 256 Baud rates less than 150 CTC in the timer mode prescaler set to 16 Baud Rate SIO divider Time Constant Error 45 32 174 0 228 60 32 130 0 16 75 16 288 0 16 116 16 142 0 043 Real Time Clock Channels 2 and 3 of the CTC are chained together to provide l second interrupt real time clock Channel 2 is programmed in the timer mode pre scaler set to 256 and time constant set to 125 Channel 3 is set to the counter mode time constant set to 125 and interrupt enabled For a multi user operating system which requires a fast clock interrupt enable the interrupt for channel 2 also The interrupt routine for channel 2 can count down to provide periods which are integral multiples of the 8 millisecond interrupt The standard system software stores the time and date in System RAM in six consecutive bytes SEC MIN HOUR YEAR DAY and MONT
35. nnected relax Due to its complexity there are many areas that may have inadvertently been overlooked Take time to read the Peripheral Connections section The following trouble shooting guide lists the major functional areas of the SYSTEMASTER and some typical problems associated with each Suggested solutions are offered for each But remember it is highly recommended that the entire manual be read TROUBLESHOOTING GUIDE Once the SYSTEMASTER board has been plugged into your mainframe a disk drive cable attached to the 50 pin connector on board and the system console cable connected then the typical boot procedure should be as follows a Insert the SYSTEMASTER CP M disk supplied by Teietek into drive A and RESET the system b disk access should take place C The system will then wait for you to enter a series of carraige returns up to eight may be required so that the baud rate of your console device can be determined This procedure can be bypassed by choosing the static option for SIOB when running the CONSYS COM utility d Once the console port speed has been Successfully determined a sign on message will appear on your console followed by a CP M prompt SYMPTOM There is no disk access on RESET Disk access occurs but nothing appears on the terminal upon entering many carraige returns List device does not function Board dies after a Short period of operatioin POSSIBLE CAUSES 1 Missing p
36. of operation it means 1 Output mode Positive edge of this strobe is issued by the device to acknowledge the receipt of data made available by PIO A 2 Input mode The strobe is issued by the device to load data from the device into PIO A 3 Bidirectional mode Same as 1 except output data are present only while A STB is low 4 Control mode The strobe is inhibited internally A RDY Ready output to a device Depending on the mode of operation it means 1 Output mode Indicates that the data bus is Stable for transfer to the device 2 Input mode When active it indicates that PIO A is ready to accept data from the device 3 Bidirectional mode Same as 1 4 Control mode Always in a low state 11 The active low reset line the SYSTEMASTER This can be used to reset a hard disk connected to PIO A STB Used when PIO A is in the bidirectional mode strobes data from the device into A RDY Used when is in the bidirectional mode it goes high to indicate that PIO A is ready for data from the device The software supplied by Teletek allows PIO A to be set up as an input port or an output port PIO B is set up in the control mode with all eight data lines available individually as input or output lines Parallel Printer Connection A Centronics type parallel printer may be connected to PIOA on the SYSTEMASTER board The following table lists the pin connections required to make a cab
37. or interrupts a very important feature when the board is used in a multi user or real time enviroment Some additional capabilities are single and double density data transfer under software control performance of simuitaneous Seek operations on all drives connected to the system IBM compatible formatting for ease of information exchange with controllers using Similar operating system software compatibility with both single and double sided drives ANSI standard 58 pin disk drive connector automatic reading of sequential sectors diskette automatic reading of both tracks of a two sided diskette automatic error checking detected via CRC under software control possible selection of Sector size to 128 256 512 or 1 824 bytes The floppy disk control section of SYSTEMASTER also incorporates a field proven phase locked oscillator PLO which is used to stabilize the separated information and clock for precise data recovery A reset jump circuit on SYSTEMASTER makes the CPU jump to the EPROM software on board whenever the system reset button is activated This is useful for systems which do not have a front panel For systems with a front panel reset jump will override the functions of the front panel Also incorporated as part of the reset jump circuit power on clear function is included which automatically generates a reset when power is first applied SYSTEMASTER can be used as cost effective stand alone m
38. otect write fault low current track greater than 42 and write fault reset The 765 also has two drive select outputs U 49 a dual decoder decodes 056 and 051 from the 765 to develop four drive select signals The 765 generates an interrupt request to the CPU when it detects an error or completes an operation The 765 interrupt output on pin 18 is active high thus it is inverted by U 57 afid activates the output of U 7 a tri state buffer U 7 pullis down the CPU interrupt request line When the CPU acknowledges the interrupt LA 4 will pull down data line 6 if no other interrupts are active on SYSTEMASTER Because the other data lines to the CPU have resistor pull ups to 5 volts the CPU sees FEH on its data bus and will execute the absolute address stored at FEH in the interrupt table data input buffer from the 5 100 bus is held inactive by LA 4 during the interrupt acknowledge operation when the 765 interrupt line is active The read data from the disk drive may vary in frequency due to disk drive rotation speed variations To maintain reliable read data a phase locked loop oscillator follows the frequency of the read data and provides a stabilized read clock for the 765 The action of the phase lock loop is such that the read data pulses will occur in the center of the high or low portion of the read data clock sent to the 765 This provides the maximum margin for error in disk read operations 26 Disk Data Encoding
39. ower and ground check 5V supply Make sure your mainframe provides ground on pins 29 and 70 of the 5 10 0 bus 2 Check that the 5 pin drive cable is connected correctly 3 Verify that the drives are configured as recommended in the drive appendix of this manual 1 Make sure the terminal is connected to SIOB the port next to the disk drive cable 2 Verify that the terminal cable is connected correctly and that the terminal provides hardware not then follow the suggestions given in the Peripheral Connections section for the serial ports 3 Check the and 12V supply 1 Verify that the BIOS has been configured correctly for your list device by running the CONSYS COM utility Make sure the correct protocols and port speeds are selected for your printer Remember that the system must be reboott amp d before any changes that are made will take effect 2 For a parallel printer verify the cable connection to see Peripheral Connections Also remenber that the is a MOS device and is not capable of driving long cables without adding an external driver adapter 1 Check the cooling ability of your mainframe If the temperature of the 5V regulator is high enough it will shut down Forced airflow across the face of the board is required Also verify that the supply voltages are not more than are required by the 5 10 standard Any excess voltage will cause the regulator
40. s which must be at 12V for the SIO channel to function if the Auto Enables option is activated through software This option is normally enabled in the standard SYSTEMASTER software Either channel can be crimp connected to a 25 pin RS 232 connector by aligning pin l of the cable from the SYSTEMASTER connector with pin 1 of the 25 pin RS 232 connector In this configuration the channel connects directly to a terminal or printer If the terminal or printer does not provide the necessary handshake lines pins 4 5 and 28 should be jumpered together This ensures that the required handshake signals to the SIO port are provided The connections can be made on the serial cable or at the SIO connector on the SYSTEMASTER At the SIO connector this requires that pins7 9 and 14 be jumpered An alternative to providing a hardware handshake is to disable the Auto Enables Option on the SIO This can be accomplished by altering the initialization software EIA Serial Data Transfer Protocol Prior to sending or receiving data the four handshake lines should be active However the SIO will allow control of its receive transmit functions independently If the Auto Enables function of the SIO channel is enabled standard the SIO will not send data until is active This function is labelled CTS on the SIO chip This is handy for buffered printers which need to stop receiving data until the buffer is printed
41. ted twice as fast FIGURE FLOPPY DISK DATA ENCODING BASE CLOCK DATA D 2 PULE ____ _ AUU well dL dL 100 Bus Interface The signals generated by SYSTEMASTER are compatible with the proposed IEEE 696 standard U 14 logic array LA 4 transforms the 2 80 family status signals to those of the S 186 bus In addition U 14 controls the data input bus driver U 12 to prevent conflicts with on board I O and memory devices conflict could occur SYSTEMASTER ignores the off board device SYSTEMASTER generates the S 100 standard memory write strobe by the logical equation MWRT pWR AND SOUT In addition to the standard S 100 signals SYSTEMASTER brings the 2 80 CPU refresh signal to pin 66 of the bus for those memory boards which need this signal U 5 a dual monostable generates the pSYNC and pSTVAL Signals Whenever the CPU activates a status line Ml MREQ IORQ U 14 outputs an active low signal to trigger U 5A The output of U 5A appears on the bus as pSYNC and also triggers U 5B U 5B generates pSTVAL signal whose active edge occurs after status is valid and during the pSYNC puise Power On Clear SYSTEMASTER generates a reset pulse when power is applied to automatically initialize the system Thus during the start up operation operator intervention is not required To develop the power on reset pulse circui
42. try on board SYSTEMASTER detects the first application of power Capacitor C 26 is initially discharged C 26 holds the plus input of U 17 a dual comparator low which causes the output of U 17 to be low The output of U 17 enables two drivers of U 6 a hex inverting bus driver which pull RESET and SLAVE CLR low on the 5 100 bus In addition the output of U 17 is buffered by U 18 to drive POC low When C 26 charges above the level on the minus input pin of U 17 the output of U 17 goes high RESET and SLAVE CLR are released and pulled high by resistors connected to 5 volts and POC goes high At this time the CPU on board SYSTEMASTER begins execution of the instructions in the on board ROM When power is turned off diode D 1 discharges C 26 quickly to provide a reset action if power is shortly reapplied Such a sequence can occur during a temporary power outage 29 SYSTEMASTER Port Assignments Device SIO Function A Data A Control B Data B Control A Data A Control B Data B Control Channel 510 baud rate Channel 1 SIO B baud rate Channel 2 Real time clock Channel 3 Real time clock connects to the output of Channel 2 Status register Data Not used DMA acknowledge to 765 Not used Terminal count to 765 Not used DMA processor control registers Not used On board control register Not used V CASE OF TROUBLE If the SYSTEMASTER does not respond the first time it s co
43. ty CONSYS COM on the system disk Some versions of SYSTEMASTER upon request do not have RAM on board If no RAM is provided it must be supplied by the user before the SYSTEMASTER will function Care must be exercised in choosing the right RAM device for use on the board See the SYSTEMASTER specifications for further information 3 1 Peripheral Connections Serial Ports SIO SIO B 15 17 20 2 4 6 8 19 12 14 16 TxC RxC DTR SIOA SIOA IN 2 3 4 5 6 7 8 3 2 y 9 11 13 15 DATA DATA RTS CTS DSR GND DCD IN OUT IN OUT OUT OUT EIA pins are shown in parentheses These are the connections going into channels A and B of the SIO chip this configuration each channel appears as a data communication device and will connect to a terminal or a printer IN and OUT refer to data direction with respect to the SYSTEMASTER Data from an external device is IN to SYSTEMASTER and data to an external device is OUT The signals TxC and RxC are clock inputs for synchronous communications They are provided on serial port A only these inputs are to be used then jumper E22 to E23 and E25 to E26 These modifications connect the clock inputs of the SIO to the externally supplied clock on the EIA connector CTS Clear To Send and DSR Data Set Ready are outputs to the external device and are at 12V when the SIO channel is ready to function RTS Request To Send and DTR Data Terminal Ready are input
44. ulti drop bus and should not require more than 4 uA current from the driver at input high 2 4V nor supply more than 1 6mA to a current sink at input low 0 4V level Interconnecting Cable Conductor Size Copper AWG 30 or larger for solid conductor AWG 28 or larger for stranded conductor Non copper Sufficient size as to yield a dc resistance not to exceed 110 Ohms per 1000 ft per conductor Stray capacitance Capacitance between tne wire in a cable and all others in the cable with all others connected to ground shall not exceed 4 pF ft and the value shall be reasonably uniform over the length of the cable Mutual pair capacitance Capacitance between one wire of the pair to the other shall not exceed 20pF ft and the value should be reasonably uniform over the length of the cable ANSI Standard for 5 25 Inch Drive Signal Ground Pin No Pin No Signal 2 1 Not assigned Head load 4 3 In use control 6 5 Drive select 3 Ready 8 7 Index sector 10 9 Drive select 0 12 11 Drive select 1 14 2213 Drive select 2 16 15 Motor on 18 17 Direction select 20 19 Step 22 21 Composite write data 24 23 Write gate 26 29 Track 0 28 27 Write protected 30 29 Composite read data 32 31 Side one select 34 33 Disk change Drive select 3 ANSI Standard for 8 Inch Drive Signal Ground Pin No Pin No Signal 2 i Head current switch 4 3 Not assigned 6 5 Not assigned 8 7 Drive busy 9 10 Two sided 12 11 Disk change 14 13
45. vailable in appendix B Please refer to that section of the manual when installing disk drives on the SYSTEMASTER ya Uu 3 2 Options Write Compensation To help compensate for the shifting of data bits during the read process of the floppy disk drive the write data bits are compensated This is particularly critical for double density operation Different drives require different amounts of write compensation The symptoms of too much or not enough write compensation are as follows 1 Too much write compensation Shows up as read errors usually CRC in the outer tracks 0 42 2 Not enough write compensation shows up as read errors in the inner tracks 43 76 SYSTEMASTER provides selectable compensation for both 5 1 4 and 8 drives in the following combinations Jumper Compensation PO Pl 2 5 1 4 8 1 1 1 None None 0 1 1 125 1 0 1 None 250 nSec 0 0 1 250 nSec 125 1 1 0 250 258 0 1 0 500 nSec 125 nSec 1 0 8 586 nSec 250 0 Illegal write data output 1 indicates the jumper is in place while a indicates the option pins are open Compensation is automatically switched as the on board drive size control is switched from 5 1 4 to 8 dr ves Compensation depends on the recommendations of the drive manufacturer Both 5 1 4 and 8 drives usually require 250 nSec compensation Track 43 Selectable Compensation In addition to the above options SYSTEM
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