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TM8723 User`s Manual (Ver 1.0) (*)

1. 20 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual XTOUT External Resistor 2 2 2 2 RC OSCILLATOR WITH INTERNAL RESISTOR CF CLOCK Two kinds of the frequencies could be selected in this mode of oscillator the one is 250KHz and the other is 500KHz When this oscillator is used leave CFOUT and CFIN two pins opened This kind of oscillator could be used in FAST only or DUAL clock options MASK OPTION table Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY amp USE INTERNAL RESISTOR or 4 DUAL For 250KHz output frequency Mask Option name Selected item FAST CLOCK OSC TYPE FOR FAST ONLY OR DUAL 1 INTERNAL RESISTOR FOR 250KHz For 500KHz output frequency Mask Option name Selected item FAST CLOCK OSC TYPE FOR FAST ONLY OR DUAL 2 INTERNAL RESISTOR FOR 500KHz XTOUT N C XTIN N C Intema RC FREQUENCY RANGE OF INTERNAL RC OSCILLATOR Option Mode BAK Min Typ Max 250KHz 1 5V 200KHz 300KHz 400KHz 3 0V 200KHz 250KHz 300KHz 500KHz 1 5V 450KHz 600KHz 750KHz 3 0V 400KHz 500KHz 600KHz 21 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 2 3 COMBINATION OF THE CLOCK SOURCES There are three types of combination of the clock sources that can be selected by mask option 2 2 3 1 DUAL CLOCK MASK OPTION table Mask Option name Selected item CLOCK SOURC
2. 120 2 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Chapter 1 General Description 1 1 GENERAL DESCRIPTION The TM8723 is an embedded high performance 4 bit microcomputer with LCD LED driver It contains all the necessary functions such as 4 bit parallel processing ALU ROM RAM I O ports timer clock generator dual clock operation EL panel driver LCD driver look up table watchdog timer and key matrix scanning circuitry in a signal chip 1 2 FEATURES 1 2 Low power dissipation Powerful instruction set 135 instructions Binary addition subtraction BCD adjust logical operation in direct and index addressing mode Single bit manipulation set reset decision for branch Various conditional branch 16 working registers and manipulation Table look up LCD driver data transfer LCD LED driver output 5 common outputs and 27 segment outputs up to drive 135 LCD LED segments e 1 2 Duty 1 3 Duty 1 4 Duty or 1 5 Duty for both LCD LED drivers is selected by MASK option e 1 2 Bias or 1 3 Bias for LCD driver is selected by MASK option e Single instruction to turn off all segments Segment outputs SEG1 12 21 35 could be defined as CMOS or P open drain type output by mask option Memory capacity capacity 1536 x 16 bits RAM capacity 96 x 4 bits Input output ports Port IOA 4 pins with internal pull low muxed with SEG24 27 Port IOB 4 pi
3. cepere cde etude Eee cede diee t ted 29 2 7 Data Memory RAM nee nen Ake Ae Ae Code RRR 30 2 8 Working Register 31 2 9 Accumulator s week ec ee 31 2 10 ALU Arithmetic and Logic Unit a s s 31 2 11 Hexadecimal Convert to Decimal HCD 32 2 12 Timer FC TI tise Geiss uum ns 33 2 oltalus Iegisler STS scott EE EEE 36 2 14 Control Register 40 2 15 ua eee eene e Het tbe 44 2 16 Heavy Load Function reete 44 Lourdes 45 2 18 Back Up Function ON CIE NR ad a e RAO CERA MERE Qni REI QUE UTI 46 CHAPTER 3 Control Function 49 3 1 auzinjeduUigieio 49 1 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual S2 Reset PUC O u m Su a 53 3 3 Clock Generator Frequency Generator and Predivider 57 du Buzzer DuipubPiltissiasnec cen oar u us eee ere
4. 3 3 8 V Volle 100 1 0 2 V Output L Voltage Vol2e jlol 10uA 2 0 2 V Vol3e olz10uA 23 0 2 V 1 2 Bias Display Mode Output H Voltage Voh12f jloh 1uA 1 2 2 2 V Voh3f 1 3 SEG n 3 8 V Output L Voltage VoM2f jlol 1uA 1 2 0 2 V Vol3f flol 1uA 3 0 2 V Output H Voltage Voh12g 10 81 82 2 2 V Voh3g loh 10uUA 3 COM n 3 8 V Output M Voltage Vom12g _ lol hn 10uUA 1 2 1 0 1 4 V Vom3g _ lol h 10uUA 3 1 8 2 2 V Output L Voltage Voli2g lol 10uA 1 2 0 2 V Vol3g 10 3 0 2 V 1 3 Bias display Mode Output H Voltage Voh12i loh 1uA 1 2 3 4 V Voh3i loh 1uA 3 5 8 V Output M1 Voltage Vom12i lol h2 10u0A 71 722 1 0 1 4 V Vom13i lol n 10uA 3 SEG n 1 8 2 2 V Output M2 Voltage Vom22i lol h 10uA 1 2 2 2 2 6 V Vom23i lol h2 10u0A 3 3 8 4 2 V Output L Voltage Vol12i jlol 1uA 1 2 0 2 V Voli lol 1uA 3 0 2 V Output H Voltage Voh12j 10 41 82 3 4 V Voh3j 100 3 5 8 V Output M1 Voltage Vom12j lol h 10uA 1 2 1 0 1 4 V Vom13j 101 100 3 1 8 2 2 V Output M2 Voltage Vom22j lol h2 10u0A 71 722 2 2 2 6 V 23 101 100 3 3 8 4 2 V Output L Voltage Vol12j 101 100 1 2 0 2 V Vol3j lol210uA 23 0 2 V 10 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 1 8 TYPICAL APPLICATION CIRCUIT This application circuit is simply a
5. The carry flag CF will be affected D 0H FH AC Rx Ry D D represents an immediate data The contents of Ry and D are binary ADDed the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC Ry D B 1 D represents an immediate data 106 tenx technology inc Rev 1 0 2003 11 13 SUBI Ry D Function Description ADNI Ry D Function Description ADNI Ry D Function Description ANDI Ry D Function Description ANDI Ry D Function Description EORI Ry D Function Description TM8723 User s Manual The immediate data D is binary subtracted from working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH AC Rx Ry D B 1 D represents an immediate data The immediate data D is binary subtracted from working register Ry the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC Ry D D represents an immediate data The contents of Ry and D are binary ADDed the result is loaded to AC The result will not affect the carry flag CF D 0H FH AC Rx Ry D D represents an immediate data The contents of Ry and D are binary ADDed the result is loaded to AC and working register Ry The result will not affect the carry flag CF D 0H FH AC Ry amp D D represents an immediate data The
6. Carry flag CF will be affected AC R HL AC CF The contents of data memory specified by QHL AC and CF are binary added the result is loaded to AC Carry flag CF will be affected AC Rx Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC and data memory Rx Carry flag CF will be affected AC R HL R HL AC CF The contents of data memory specified by HL AC and CF are binary added the result is loaded to AC and data memory specified by HL Carry flag CF will be affected AC Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected AC R HL AC B CF The contents of AC and CF are binary subtracted from content of data memory specified by HL the result is loaded to AC Carry flag CF will be affected AC Rx Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC and data memory Rx Carry flag CF will be affected 102 tenx technology inc Rev 1 0 2003 11 13 SBC HL Function Description ADD Rx Function Description ADD HL Function Description ADD Rx Function Description ADD HL Function Description SUB Rx Function Description SUB HL Function Description SUB Rx Function Description TM8723 User s Manual AC R HL R HL
7. CLOCKS This figure shows the System Clock Switches from Slow to Fast After executing SLOW instruction the system clock generator will hold 2 XT clocks and then switches XT clock to BCLK CF Fast clock stops operating clock XT clock SLOW BCLK This figure shows the System Clock Switches from Fast to Slow 2 2 3 2 SINGLE CLOCK MASK OPTION table For Fast clock oscillator only Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY amp USE INTERANL RESISTOR or 2 FAST ONLY amp USE EXTERANL RESISTOR For slow clock oscillator only Mask Option name Selected item CLOCK SOURCE 3 SLOW ONLY The operation of the single clock option is shown in the following figure Either XT or CF clock may be selected by mask option in this mode The FAST and SLOW instructions will perform as the NOP instruction in this option The backup flag BCF will be set to 1 automatically before the program enters the stop mode This could ensure the Crystal oscillator would start up in a better condition 23 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Halt Normal mode Halt Halt mode OSC active released OSC active Reset Reset release Stop Stop Release Stop mode OSC stop Reset mode
8. DAS Function AC BCD AC Description Converts the content of AC to decimal format and then restores to AC When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected DAS Rx Function AC Rx BCD AC Description Converts the content of AC to decimal format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected DAS HL 113 tenx technology inc Rev 1 0 2003 11 13 Function Description TM8723 User s Manual AC HL BCD AC Converts the content of AC to decimal format and then restores to AC and data memory HL When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution 0 lt lt 9 6 lt AC lt F AC 5 8 JUMP INSTRUCTIONS JBO X Function Description JB1 X Function Description JB2 X Function Description JB3 X Function Description JNZ X Function Description JNC X Program counter jumps to X if ACO 1 If bitO of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 5FFH Program counter jumps to X if AC1 1 If bit of AC is
9. SCC AC1 AC0 FRQ D Rx Rx3 RxO SCC instruction may specify the clock source selection for the frequency generator The frequency generator outputs the clock with different frequencies and duty cycles corresponding to the presetting data of FRQ related instructions The FRQ related instructions preset a letter N into the programming divider and letter D into the duty cycle generator The frequency generator will then output the clock using the following formula FREQ clock source N 1 X Hz 1 2 3 4 for 1 1 1 2 1 3 1 4 duty This letter N is a combination of data memory and accumulator AC or the table ROM data or operand data specified in the FRQX instruction The following table shows the bit pattern of the combination The following table shows the bit pattern of the preset letter N 57 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual The bit pattern of preset letter N Notes 1 TO T7 represents the data of table ROM 2 X0 X7 represents the data specified operand X The following table shows the bit pattern of the preset letter D Preset Letter D Duty Cycle 1 4 duty The following diagram shows the output waveform for different duty cycles clock source N 1 Hz ET eT md oj 1 4 duty carrier out 1 3 duty carrier out 1 2 duty carrier out 1 1 duty carrier out 3 3 2 Melody Output The frequency generator may generat
10. TM8723 User s Manual Once the program enter back up mode BCF 1 32 768KHz Crystal oscillator will operate in a large driver condition and internal logic function operates with higher supply voltage TM8723 will get more power supply noise margin while back up mode is active but also increases more power consumption The back up flag BCF indicated the status of back up function BCF flag could be set or reset by executing SF or RF instruction respectively The back up function has different performance corresponding to different power mode option shown in the following table 1 5V battery mode TM8723 status BCF flag status Initial reset cycle BCF 1 hardware controlled After initial reset cycle BCF 1 hardware controlled Executing SF 2h instruction 1 Executing RF 2h instruction 0 HALT mode Previous state STOP mode BCF 1 hardware controlled TM8723 status 0 1 32 768KHz Crystal Oscillator Small driver Large driver Voltage on BAK pin VDD1 VDD1 Internal operating voltage VDD1 VDD1 3V battery or higher mode Initial reset cycle BCF 1 hardware controlled After initial reset cycle BCF 1 hardware controlled Executing SF 2h instruction 1 Executing RF 2h instruction 0 HALT mode Previous state STOP mode BCF 1 hardware controlled Boo BCF 1 32 768 2 Crystal Oscillator Small driver Large driver Voltage on BAK pin VDD1 VDD2
11. bit3 bit2 bit1 bitO The following table shows the clock source setting for TMR1 Notes 1 When the 1 clock is PH3 TMR set time Set value error 8 1 fosc KHz ms 2 When the TMR1 clock is PH9 TMR1 set time Set value error 512 1 fosc KHz ms 3 When the TMR1 clock is PH15 TMR set time Set value error 32768 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 lt error 1 fosc Input of the predivider PH3 3rd stage output of the predivider PH9 9th stage output of the predivider PH15 The 15th stage output of the predivider 8 When the TMR1 clock is FREQ TMRI set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 2 12 2 RE LOAD OPERATION TMR1 provides the re load function which can extend any time interval greater than 3Fh The SF 80h instruction enables the re load function and RF 80h instruction disables it When the re load function is enabled the TMR1 will not stop counting until the re load function is disabled and TMR1 underflows again During this operation the program must use the halt release request flag or interrupt to check the wanted counting value t is necessary to execute the TMS or instruction to set the down count value before the re load function is enabled because TMR1 will automatically count down with an unknown value once the re load function is enabled e
12. uode mW DE Eu 6 BITS PRESET 8 LEVELS INSTRUCTION PREDWIDER TIMER 1 STACK DECODER CONTROL db 11 BITS PROGRAM PROGRAM ROM OSCILLATOR CIRCUIT y COUNTER 128N X 16 BITS CUP1 2 XTIN OUT RESET INT 1 gt 12 Je 1 FREQUENCY GENERATOR 4 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 1 4 PAD DIAGRAM The substrate of chip should be connected to GND Die sizez 1680um x 1480um LILILILILILILILILILI 0000000 1 5 PAD COORDINATE XOUT GND SEG12 K12 VDD1 5 21 VDD2 SEG22 VDD3 SEG23 CUP1 SEG24 IOA1 CUP2 SEG25 IOA2 1 5 26 2 5 27 4 I SEG28 IOB1 ELC COM4 SEG29 IOB2 ELP COM5 SEG30 IOB3 BZB SEG31 IOBA BZ SEG32 IOC1 KI1 SEG33 IOC2 KI2 SEG34 IOC3 KI3 5 5 4 RESET INT TEST 5 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 1 6 PIN DESCRIPTION Name u Power Back up pin At Li Mode ey a 0 1u capacitor to GND LCD supply voltage and positive supply pins In Ag power mode connect positive power to VDD1 In Lior ExtV power mode connect positive power to VDD2 Input pin for external reset request signal built in internal pull down resistor Reset cycle time can be defined as PH15 2 or PH12 2 by mask option Reset Type can be defined as Le
13. Internal operating voltage VDD1 VDD2 Ext V power mode TM8723 status BCF flag status Initial reset cycle BCF 0 hardware controlled After initial reset cycle BCF 0 hardware controlled Executing SF 2h instruction 1 Executing RF 2h instruction 0 HALT mode Previous state STOP mode BCF 1 hardware controlled Bcr 0 1 32 768KHz Crystal Oscillator Large driver Large driver 47 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Voltage on BAK pin VDD2 VDD2 Internal operating voltage VDD2 VDD2 Note For power saving reason it is recommend to reset BCF flag to 0 when back up mode is not used 48 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual CHAPTER 3 CONTROL FUNCTION 3 1 INTERRUPT FUNCTION There are 5 interrupt resources 3 external interrupt factors and 2 internal interrupt factors When an interrupt is accepted the program in execution is suspended temporarily and the corresponding interrupt service routine specified by a fix address in the program memory ROM is called The following table shows the flag and service of each interrupt Table 3 5 Interrupt information Interrupt INT pin IOC port TMR1 Pre source underflow divider i overflow Scanning ERE vector Interrupt IEF2 audi Band enable flag Interrupt priority Interrupt Interrupt
14. SCA intruction Note The default prevention clock is PH10 This chattering prevention function works when the signal at the applicable pin ex IOC1 is changed from L level to H level or from H level to L level and the remaining pins ex 2 to IOC4 are held at L level When the signal changes at the input pins of IOC port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF1 At that time the chattering prevention clock will stop due to the delivery of SCF1 The SCF1 will be reset to O by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF1 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOC interrupt enable mode IEFO is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOC1 to IOCA the input data at the port IOC must be read into the RAM immediately after the halt mode is released 68 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 3 6 EL PANEL DRIVER TM8723 provides an EL panel driver for the backlight of the LCD panel The user can choose different voltage pumping frequencies duty cycle and ON OFF frequency to operate with few external components This circuit
15. SPC Ofh Disable all the pull down device on internal IOC port Set all of the IOC pins as output mode SPK 10h Generate HALT released request when key depressed Scanning all columns simultaneous in each cycle PLC 20h Clear HRF5 SHE 20h Set HEF5 HALT for the halt release caused by key matrix MCX 10h Check SCF8 SKI JBO ski_release ski_release IPC 10h read KI1 4 input latch state JBO ki1_release JB1 ki2_release JB2 ki3 release JB3 ki4 release ki1 release SPK 40h Check key depressed on K1 column PLC 20h Clear HRF5 to avoid the false HALT released CALL wait scan again Waiting for the next key matrix scanning cycle The waiting period must longer than key matrix scanning Cycle IPC 10h Read KI1 input latch state JBO ki seg1 SPK 4fh Only enable SEG 16 scanning output PLC 20h Clear HRF5 to avoid the false HALT released CALL wait scan again Wait for time over halt LCD clock cycle to sure scan again IPC 10h Read KI1 input latch state JBO kil seg16 wait scan again HALT PLC 20h RTS 74 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual CHAPTER 4 LCD LED DRIVER OUTPUT 4 1 LCD DRIVER OUTPUT When the LED mode option is not selected in the mask option the entire segment pins and common pins will be used for LCD driver or DC output port The number of the LCD driver outputs in TM8723 is 27 segment pins with 5 common pins All of these output pins could also be used as DC output
16. interrupt 3 address 01CH interrupt 5 address 024H and interrupt 6 address 028H in the program memory This figure shows the Organization of ROM Address address 000h Initial reset 000H 010h Interrupt 2 014h Interrupt 0 018h Interrupt 1 zo 01Ch Interrupt 3 2 High Low Nibble Nibble 024h Interrupt 5 579 2048 128 N 0 XFFH 8 Bits 2 12 1 gt 12 Instruction ROM PROM organization T bl ROM TR M organization This figure shows the Organization of ROM 2 4 2 TABLE ROM TROM The table ROM is organized with 256 12 N x 8 bits that shared the memory space with instruction ROM as shown in the figure above This memory space stores the constant data or look up table for the usage of main program All of the table ROM addresses are specified by the index address register HL The data width could be 8 bits 256 12 N x 8 bits or 4 bits 512 12 N x 4 bits which depends on the different usage Refer to the explanation of instruction chapter 28 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 5 INDEX ADDRESS REGISTER HL This is a versatile address pointer for the data memory RAM and table ROM TROM The index address register HL is a 12 bit register and the contents of the register can be modified by executing MVH and MVL instructions Executed MVL instruction will load the content of specified data memory to the lower nibble o
17. 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 5FFH Program counter jumps to X if AC2 1 If bit2 of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 5FFH Program counter jumps to X if AC3 1 If bit3 of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 5FFH Program counter jumps to X if AC 0 If the content of AC is not 0 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 5FFH 114 tenx technology inc Rev 1 0 2003 11 13 Function Program counter jumps to X if CF 0 Description If the content of CF is 0 jump occurs If 1 the PC increases by 1 The range of X is from 000H to 5FFH 2 X Function Program counter jumps to X if AC 0 Description If the content of AC is 0 jump occurs If 1 the PC increases by 1 The range of X is from 000H to 5FFH JC X Function Program counter jumps to X if CF 1 Description If the content of CF is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 5FFH JMP X Function Program counter jumps to X Description Unconditional jump The range of X is from 000H to 5FFH CALL X Function STACK PC 1 Program counter jumps to X Description A subroutine is called The range of X is from 000H to 5FFH RTS Function PC STACK Description A return from a subroutine occurs 5 9 MISCELLANEOUS INSTRUCTIONS TM8723 User s M
18. 11 13 TM8723 User s Manual Once the subroutine call or interrupt causes the stack register STACK overflow the stack pointer will return to 0 and the content of the level 0 stack will be overwritten by the PC value The contents of the stack register STACK are returned sequentially to the program counter PC during execution of the RTS instruction Once the RTS instruction causes the stack register STACK underflow the stack pointer will return to level 7 and the content of the level 7 stack will be restored to the program counter The following figure shows the diagram of the stack Stack pointer CALL instruction Interrupt accepted RTS instruction function STACK ring with first in last out 2 7 The static RAM is organized with 96 addresses x 4 bits and is used to store data The address range of data memory is from 00h to 7Fh but addresses between 50h to 6Fh are not reachable The data memory may be accessed using two methods 1 Direct addressing mode The address of the data memory is specified by the instruction and the addressing range is from 00H to 7FH Addresses between 50h to 6Fh are not reachable 2 Index addressing mode The index address register HL specifies the address of the data memory and all address space from 00H to 1FFH can be accessed Addresses between 50h to 6Fh are not reachable 30 tenx technology inc Rev 1 0 2003 11 13 TM8723 Use
19. AC B CF The contents of AC and CF are binary subtracted from content of data memory specified by HL the result is loaded to AC and data memory specified by HL Carry flag CF will be affected AC Rx AC The contents of Rx and AC are binary added the result is loaded to AC Carry flag CF will be affected AC R HL AC The contents of data memory specified by HL and AC are binary added the result is loaded to AC Carry flag CF will be affected AC Rx Rx AC The contents of Rx and AC are binary added the result is loaded to AC and data memory Rx Carry flag CF will be affected AC R HL R HL AC The contents of data memory specified by HL and AC are binary added the result is loaded to AC and data memory specified by HL Carry flag CF will be affected AC lt Rx AC B 1 The content of AC is binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected AC R HL AC B 1 The content of AC is binary subtracted from content of data memory specified by HL the result is loaded to AC Carry flag CF will be affected AC Rx Rx AC B 1 The content of AC is binary subtracted from content of Rx the result is loaded to AC and Rx 103 tenx technology inc Rev 1 0 2003 11 13 SUB HL Function Description ADN Rx Function Description ADN HL Function Description ADN Rx Function Descr
20. CF AC Rx CF The content of CF is loaded to AC and Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 CF Bit 2 AC 0 zero flag Bit 1 No Use Bit 0 No Use 5 3 OPERATION INSTRUCTIONS INC Rx Function Description INC HL Function Description DEC Rx Function Description Rx AC Rx 1 Add 1 to the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected R HL AC R HL 1 Add 1 to the content of data memory specified by HL the result is loaded to data memory specified by QHL and AC Carry flag CF will be affected Rx AC Rx 1 Substrate 1 from the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected 101 tenx technology inc Rev 1 0 2003 11 13 DEC HL Function Description ADC Rx Function Description ADC HL Function Description ADC Rx Function Description ADC HL Function Description SBC Rx Function Description SBC QHL Function Description SBC Rx Function Description TM8723 User s Manual R HL AC R HL 1 Substrate 1 from the content of data memory specified by HL the result is loaded to data memory specified by HL and AC Carry flag CF will be affected AC Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC
21. Cch PH10 X2 1 0 010 Cch PH8 X2 1 0 100 Cch PH6 SCA X 1101 1010 000X 0000 X4 Enable SEF4 C1 4 SPA x 1101 1100 000X XXXX 4 Set IOA4 1 Pull Low X3 0 Set IOA4 1 I O SPB X 1101 1101 000X XXXX 4 Set IOB4 1 Pull Low X3 0 Set IOBA4 1 I O SPC X 1101 1110 000X XXXX X4 Set IOC4 1 Pull Low Low Level Hold X3 0 Set 1OC4 1 I O TMS Rx 1110 0000 XXXX Timer1 lt Rx amp TMS HL 1110 0001 0000 0000 Timer1 lt TQHL TMSX x 1110 0010 XXXX XXXX 7 6 11 Ctm FREQ X7 6 10 Ctm PH15 X7 6 01 Ctm PH3 X7 6 00 Ctm PH9 X5 0 Set Timer1 Value SPK X 1110 0011 XXXX XXXX X671 KEY S release by scanning cycle 6 0 5 release by normal key scanning 7 5 4 000 Set one of KO1 12 1 by lOC normal X3 0 SCAN X7 5 4 001 Set all 1 SCAN X7 5 4 010 Set all Hi z X7 5 4 10X Set eight of KO1 12 1 by X3 X3 0 gt KO1 8 X3 1 gt KO9 12 X7 5 4 110 Set four of KO1 12 1 by X3 2 X3 2 00 gt KO1 4 X3 2 01 gt KO5 8 X3 2 10 gt KO9 12 X7 5 4 111 Set two of KO1 12 1 by X3 2 1 X3 1 000 gt KO1 2 X3 1 001 gt KO3 4 X3 1 010 gt KO5 6 X3 1 011 gt KO7 8 X3 1 100 gt KO9 10 122 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Instruction Machine Code Function Flag Remark X3 1 101 gt KO11 12 SHE x 1110 1000 00X0 XXX0 X5 Enable HEF5 KEY S X3 Enable HE
22. EXT V Li Mode 2 4 5 25 V Input Voltage Vihl Ag Battery Mode VDD1 0 7 VDD1 0 7 V Input L Voltage Vil1 0 7 0 7 V Input Voltage Vih2 Li Battery Mode VDD2 0 7 VDD2 0 7 V Input L Voltage Vil2 0 7 0 7 V Input H Voltage Vih3 OSCIN at Ag Battery Mode 0 8xVDD1 VDD1 V Input L Voltage Vil3 0 0 2xXVDD1 V Input Voltage Vih4 OSCIN at Li Battery Mode 0 8xVDD2 VDD2 V Input L Voltage Vil4 0 0 2xVDD2 V Input Voltage Vih5 CFIN at Li Battery or EXT V 0 8xVDD2 VDD2 V Input L Voltage Vil5 Mode 0 0 2xVDD2 V Input Voltage RC Mode 0 8xVDDO VDDO V Input L Voltage Vil6 0 0 2 xVDDO V Operating Freq Fopg1 Crystal Mode 32 kHz Fopg2 RC Mode 10 1000 kHz tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual ELECTRICAL CHARACTERISTICS at 1 VDD1 1 2V Ag at 2 VDD2 2 4V Li at 3 VDD2 4V Ext V Input Resistance Name Symb Condition Min Max Unit L Level Hold Rilh1 Vi 0 2VDD1 21 10 40 100 Kohm Tr IOC Rilh2 Vi 0 2VDD2 22 10 40 100 Kohm Rilh3 Viz0 2VDD2 23 5 20 50 Kohm IOC Pull Down Tr Vi VDD1 1 200 500 1000 Kohm 2 Vi VDD2 2 200 500 1000 Kohm Rmad3 Vi VDD3 3 100 250 500 Kohm INT Pull up Tr Rintu1 Vi VDD1 1 200 500 1000 Kohm Rintu2 Vi VDD2 2 200 500 1000 Kohm Rintu3 Vi VDD3 3 100 250 500 Kohm INT Pull Down Tr R
23. HL lt HL 1 LDL Rx HL 0110 0010 OXXX XXXX lt L TQHL LDL Rx HL 0110 0011 XXXX L TQHL HL lt QHL 1 STA Rx 0110 1000 XXXX lt AC STA HL 0110 1000 1000 0000 R HL lt LDA Rx 0110 1100 0XXX XXXX lt Rx 121 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Instruction Machine Code Function Flag Remark LDA HL 0110 1100 1000 0000 AC lt R HL MRA Rx 0110 1101 XXXX lt Rx 3 MRW HL Rx 0110 1110 XXXX ACRQHL Rx MWR Rx HL 0110 1111 XXXX lt R HL MRW Ry Rx 0111 OYYY YXXX XXXX AC Ry lt Rx MWR Rx Ry 0111 1YYY YXXX XXXX lt Ry JBO X 1000 XXXX PC X if AC O 1 JB1 X 1000 1XXX XXXX PC X if AC 1 JB2 X 1001 OXXX XXXX PC X if AC 2 1 JB3 X 1001 1XXX XXXX PC X if AC 3 1 JNZ X 1010 OXXX XXXX XXXX PC X if AC 0 JNC X 1010 1XXX XXXX XXXX PC X if CF 0 JZ X 1011 OXXX XXXX XXXX X if AC 0 JC X 1011 1XXX XXXX XXXX PC X if CF 1 CALL X 1100 XXXX XXXX STACK PC 1 PC lt X JMP X 1101 OXXX XXXX X RTS 1101 1000 0000 0000 PC lt STACK CALL Return SCC X 1101 1001 0X00 X671 Cfq BCLK X670 Cfq PHO X2 1 0 001
24. Interrupt Interrupt Interrupt Interrupt request 2 0 1 3 5 flag 49 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual The following figure shows the Interrupt Control Circuit Specified signal change at IOC port Timer TM underflow Specified signal change at INT pin Predivider overflow Specified signal enable at Key matrix Scanning Interrupt 0 Priority control circuit Interrupt 1 Interrupt Interrupt 2 request signal Interrupt vector address generator Interrupt 3 Interrupt 5 Interrupt accept signal SIE instruction Initial clear tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 3 1 1 INTERRUPT REQUEST AND SERVICE ADDRESS 3 1 1 1 External interrupt factor The external interrupt factor involves the use of the INT pin IOC ports or Key matrix Scanning 1 External INT pin interrupt request By using mask option either a rise or fall of the signal at the INT pin can be selected for applying an interrupt If the interrupt enable flag 2 IEF2 is set and the signal on the INT pin change that matches the mask option will issue the HRF2 interrupt 2 is accepted and the instruction at address10H is executed automatically It is necessary to apply level L before the signal rises and level H after the signal rises to the INT pin for at least 1 machine cycle 2 port IOC interrupt
25. LCD pattern of this option is shown below DBUSA DBUSA in n DBUSF DBUSB DBUSF DBUSB DBUSG DBUSG DBUSC DpBUSE DBUSC l DBUSD DBUSH DBUSD DBUSH DBUSF 0 DBUSF 1 The following table shows the option table for displaying digit 7 pattern MASK OPTION table Mask Option name Selected item F SEGMENT FOR DISPLAY 7 1 ON F SEGMENT FOR DISPLAY 7 2 OFF Both LCT and LCB instructions use the data decoder table to decode the content of data memory that specified When the content of data memory that specified by LCB instruction is 0 the decoded output of DBUSA DBUSH are all 0 this is used for blanking the leading digit 0 on LCD panel The LCP instruction transferred the data of the RAM Rx and accumulator AC directly from DBUSA to DBUSH without passing through the data decoder 78 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual The LCD instruction transfers the table ROM data T HL directly from DBUSA to DBUSH without passing through the data decoder Table 2 2 The mapping table of LCP and LCD instructions _ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH There are 8 data decoder outputs of DBUSA to DBUSH and 32 LO to L4 decoder outputs of PSTB Oh to PSTB 1Fh The input data and clock signal of the latch circuit are DBUSA to DBUSH and PSTB Oh to PSTB 1Fh respectively Eac
26. Never disable the re load function before the last expected halt release or interrupt occurs If TMS related instructions are not executed after each halt release or interrupt occurs the TMR1 will stop operating immediately after the re load function is disabled For example if the expected count down value is 500 it may be divided as 52 7 64 First set the initiate count down value of TMR1 to 52 and start counting then enable the 34 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual TMR1 halt release or interrupt function Before the first time underflow occurs enable the re load function The TMR1 will continue operating even though TMR1 underflow occurs When halt release or interrupt occurs clear the HRF1 flag by PLC instruction After halt release or interrupt occurs 8 times disable the re load function and the counting is completed TMS ay 4th pA 6th 7th lt u count u count Hon u count n E lt coa count HRF1 PLC x Yo T Re load In the following example S W enters the halt mode to wait for the underflow of TMR1 RE_LOAD subroutine END_TM1 LDS 0 0 PLC 2 SHE 2 TMSX 34h SF 80h HALT INC 0 PLC 2 JB3 1 JMP RE LOAD RF 80 initiate the underflow counting register enable the HALT release caused by TMR1 initiate the TMR1 value 52 and clock source is 9 enable the re load function increa
27. OR ed output of K1 4 latch signals can cause the stop mode to be released 2 14 3 CONTROL REGISTER 3 CTL3 Control register 3 CTL3 is organized with 7 bits of interrupt enable flags IEF to enable disable interrupts The interrupt enable flag IEF is set reset by SIE instruction The bit pattern of control register 3 CTL3 is shown below Interrupt enable IEF5 IEF3 IEF2 flag Enable the interrupt request Enable the interrupt request Enable the interrupt request Interrupt request e fla caused by Key Scanning caused by pre divider caused by INT pin HRF2 HRF5 overflow HRF3 Interrupt flag Interrupt 4 Interrupt 3 Interrupt 2 Interrupt enable IEF1 IEFO flag Interrupt request Enable the interrupt request Enable the interrupt request flag caused by TM1 underflow caused by IOC port signal tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual si HRF1 tobechanged HRFO Interrupt flag Interrupt 1 Interrupt 0 When any of the lt are accepted the corresponding HRFx and the interrupt enable flag IEF will be reset to 0 automatically Therefore the desirable interrupt enable flag IEFx must be set again before exiting from the interrupt routine 2 14 4 CONTROL REGISTER 4 CTL4 Control register 4 CTL4 being a 3 bit register is set reset by SRE instruction The following table shows the Bit Pattern of Control Register 4 CTL4 si SRF7 SRF4 S
28. USE FOR KEY RESET 1 USE IOCA KI4 FOR KEY RESET 1 USE IOC or KI pins aren t used as key reset Mask Option name Selected item IOC1 KI1 FOR KEY RESET 2 NO USE IOC2 KI2 FOR KEY RESET 2 NO USE FOR KEY RESET 2 NO USE 4 FOR KEY RESET 2 NO USE 55 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual The following figure shows the key reset organization ocak 14 edes VDD e reset IOC eS 1 l mu ass VDD 3 2 4 WATCHDOG RESET The timer is used to detect unexpected execution sequence caused by software run away The watchdog timer consists of a 9 bit binary counter The timer input PH10 is the 10th stage output of the pre divider When the watchdog timer overflows it generates a reset signal to reset TM8723 and most of the functions in TM8723 will be initiated except for the watchdog timer which is still active WDF flag will not be affected and PHO PH10 of the pre divider will not be reset The following figure shows the watchdog timer organization 9 bit counter WDF Edge detector WDRST to reset TM8706 Reset pin POR RF 10H During initial reset power on reset POR or reset pin the timer is inactive and the watchdog flag WDF is reset Instruction SF 10h will enable the watchdog timer and set the watchdog fl
29. X3 1 HEF3 is set so that the halt mode is released by predivider overflow X5 1 The HEF5 is set so that the halt mode is released by the signal is H L LED LCD on 1 4 in scanning interval XT 6 4 is reserved SRE X Function Set Reset stop release enable flag Description X4 1 The SRF4 is set so that the stop mode is released by the signal changed on port SRF5 is set so that the stop mode is released by the signal 7 1 i i changed on INT pin 7 1 The SRF6 is set so that the stop mode is released by the signa 110 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Jis Hl L LED LCD on 1 4 in scanning interval FAST Function Description SLOW Function Description MSB Rx Function Description X6 X3 0 is reserved Switches the system clock to CFOSC clock Starts up the CFOSC high speed osc and then switches the system clock to high speed clock Switches the system clock to XTOSC clock low speed osc Switches the system clock to low speed clock and then stops the CFOSC AC Rx SCF1 BCF2 BCF The SCF1 SCF2 and BCF flag contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 2 Bit 1 Bit 0 Start condition Start condition Backup flag flag 2 flag 1 BCF SCF2 SCF1 Halt release caused Halt The backup by SCF4 5 7 8 caused b
30. address is executed automatically Refer to Table 3 1 In this case the CPU performs the following services automatically 1 As for the return address of the interrupt service routine the addresses of the program counter PC installed before interrupt servicing began are saved in the stack register STACK 2 The corresponding interrupt service routine address is loaded in the program counter PC The interrupt request flag corresponding to the interrupt accepted is reset and the interrupt enable flags are all reset When the interrupt occurs the TM8723 will follow the procedure below Instruction 1 In this instruction interrupt is accepted NOP 1M8723 stores the program counter data into the STACK At this time no instruction will be executed as with NOP instruction 52 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Instruction A The program jumps to the interrupt service routine Instruction B Instruction C RTS Finishes the interrupt service routine Instruction 1 re executes the instruction which was interrupted Instruction 2 Note If instruction 1 is halt instruction the CPU will return to halt after interrupt When an interrupt is accepted all interrupt enable flags are reset to 0 and the corresponding HRF flag will be cleared the interrupt enable flags IEF must be set again in the interrupt service routine as required 3 2 RESET FUNCTION TM8723 contains four reset source
31. and data memory specified by Rx D 0H FH AC lt Rx The content of Rx is loaded to AC AC R HL The content of data memory specified by HL is loaded to AC 108 tenx technology inc Rev 1 0 2003 11 13 LDH Rx HL Function Description LDH Rx HL Function Description LDL Rx HL Function Description LDL Rx HL Function Description TM8723 User s Manual Rx AC H T HL The higher nibble data of Table ROM specified by QHL is loaded to data memory specified by Rx Rx AC H T HL HL lt HL 1 The higher nibble data of Table ROM specified by HL is loaded to data memory specified by Rx and then is increased in HL Rx AC L T HL The lower nibble data of Table ROM specified by HL is loaded to the data memory specified by Rx Rx AC L T HL HL HL 1 The lower nibble data of Table ROM specified by HL is loaded to the data memory specified by Rx and then incremented the content of HL 5 5 CPU CONTROL INSTRUCTIONS NOP Function Description HALT Function Description STOP Function Description no operation no operation Enters halt mode The following 3 conditions cause the halt mode to be released 1 An interrupt is accepted 2 The signal change specified by the SCA instruction is applied to IOC 3 The halt release condition specified by SHE instruction is met When an interrupt is accepted to release the halt mode the halt mode ret
32. configuring the mask option of LCD PLA the cfg file provides the necessary format for editing the LCD LED configuration The syntax in cfg file is as follows SEG COM PSTB DBUS SEG Specifies the segment pin COM Specifies the corresponding latch in each segment pin Only O 1 2 3 4 5 and 9 can be entered into this field 0 is for CMOS type DC output option and 9 is for P open drain DC output option PSTB Specifies the strobe data for the latch DBUS Specifies the DBUS data for the latch 81 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 4 2 LED DRIVER OUTPUT When the LED mode is selected by the mask option all of the segments and common pins will be used for LED display The number of the LED driver outputs is 27 segment pins with 5 common pins COM For LED driver outputs COM mask option can be used to select active low LED display or active high LED display and there are static 1 2 duty 1 3 duty 1 4duty or 1 5 duty lighting systems could be used There is no bias issue in LED mode so please select the 1 2 bias or No bias as the bias system In LED mode all of the segment output pins SEG work only in low active mode MASK OPTION table When COM pins have been used to drive high active LED panel Mask Option name Selected item LCD LED ACTIVE TYPE 2 LED HIGH ACTIVE When COM pins have been used to drive low active LED panel Mask Option name Selected item
33. loaded to the LCD latch specified by Lz Defines the input output mode of each pin for IOA port and enables disables the pull low device Sets the mode and turns on off the pull low device The input pull low device will be enabled when the I O pin was set as input mode The meaning of each bit of X X2 X1 is shown below Enable IOA pull low R Disable IOA pull low R IOA4 as output mode IOA4 as input mode IOA3 as output mode as input mode 2 as output mode 2 as input mode IOA1 as output mode 1 as input mode OPA Rx Function OA Rx 96 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Description The content of Rx is outputted to I OA port OPAS Rx D Function 1 2 Rx D 4 lt pulse Description Content of Rx is outputted to IOA port D is outputted to IOA3 pulse is outputted to 4 D Oor1 IPA Rx Function Rx AC IOA Description The data of I OA port is loaded to AC and data memory Rx SPB X Function Defines the input output mode of each for IOB port and enables disables the pull low device Description Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O pin was set as input mode The meaning of each bit of X X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting Enable IOB pull low R Disable IOB pull low R IOB4 as
34. lt IOA IPB Rx 0100 0100 XXXX lt IOB IPC Rx 0100 0111 XXXX lt IOC MAF Rx 0100 1010 OXXX XXXX lt STS1 CF B2 ZERO B1 No use BO No use MSB Rx 0100 1011 XXXX lt STS2 B3 No use B2 SCF2 HRx B1 SCF1 CPT BO BCF MSC Rx 0100 1100 XXXX lt STS3 B3 SCF7 PDV B2 PH15 B1 SCF5 TM1 BO SCF4 INT MCX Rx 0100 1101 XXXX lt STS3X B3 No use B2 No use B1 No use BO SCF8 SKI MSD Rx 0100 1110 OXXX XXXX lt STS4 B3 No use B2 No use B1 WDF BO CSF SRO Rx 0101 0000 XXXX AC ROn lt Rx n 1 AC 3 Rx 3 lt 0 SR1 Rx 0101 0001 XXXX AC Rx n lt Rx n 1 AC 3 R29 1 SLO Rx 0101 0010 XXXX AC n Rn lt Rx n 1 0 REO 0 511 Rx 0101 0011 XXXX AC n Rx n lt 1 0 RE9 O 1 DAA 0101 0100 0000 0000 AC lt BCD AC CF DAA Rx 0101 0101 XXXX lt BCD AC CF DAA HL 0101 0101 1000 0000 AC R HL BCD AC CF DAS 0101 0110 0000 0000 AC lt BCD AC CF DAS Rx 0101 0111 XXXX lt BCD AC CF DAS HL 0101 0111 1000 0000 AC R HL lt BCD AC CF LDS Rx D 0101 1DDD DXXX XXXX D LDH Rx HL 0110 0000 0XXX XXXX H T HL LDH Rx HL 0110 0001 OXXX XXXX lt H T HL
35. mode the backup flag BCF is set When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in driver size At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD2 at the off state of SW1 is used as an intermediate voltage level for the LCD driver 2 1 2 3 1 3 BIAS AT LI BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup flag BCF BCF 0 BCF 1 15 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual CUP1 MJ 0 1U cup T VDD3 VDD2 h i sw2 m ent VDD1 SW1 3 0V BAK 0 1U Internal 0 10 logic GND T MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER LCD BIAS 1 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in inverter size At the backup flag set mode the operating current is increased Therefore the backup flag must be r
36. must be executed to output the data to those output latches This will prevent the chattering signal when the IOC pins change to output mode IOC port had built in pull down resistor by mask option and executing SPC instruction to enable disable this device MASK OPTION table Mask Option name Selected item IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE The pull down resistor and low level hold device in each IOC pin can t exist in the same time When the pull down resistor is enabled the low level hold device will be disable vise versa Executing SPC 10h instruction to enable the pull low device and disable the low level hold device executing SPC Oh to disable the pull low device and enable the low level hold device When the low level hold device is enabled by mask option the initial reset will enable the pull low device and disable the low level hold device 66 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual bit0 D lt Q CLK lociL g 2 Nono bit0 M O bit1 D lt Q CLK IOC2 a a gt on L M O Initial clear o d er edge dectect amp TR Pu zi q 2 Bus bit2 A Qv CLK C IOC3 DOLI gt o pit2 5 M O m 5 bit3 lt e zmr IOC4 D gt on gt o bit3 Control 2 Note
37. output mode 4 as input mode IOB3 as output mode IOB3 as input mode 2 as output mode 2 as input mode 1 as output mode 1 as input mode OPB Rx Function lt Rx Description The contents of Rx are outputted to I OB port IPB Rx Function Rx AC IOB Description The data of I OB port is loaded to AC and data memory Rx SPC X Function Defines the input output mode of each pin for IOC port and enables disables the pull low device or low level hold device Description Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O pin was set as input mode The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Enables all of the pull low and Disables all of the pull X471 disables the low level hold X4 0 low and enables the low devices level hold devices IOC4 as output mode IOC4 as input mode IOC3 as output mode IOC3 as input mode IOC2 as output mode IOC2 as input mode 97 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual X0 1 IOC1 as output mode X0 0 IOC1 as input mode OPC Rx Function lt Rx Description The content of Rx is outputted to I OC port IPC Rx Function Rx AC IOC Description The data of I OC port is loaded to AC and data memory Rx SPK X Function Sets Key Matrix scanning output state Description When any of SEG1 12 is used for LCD LED by mask option the outp
38. ports mask option If more than one of LCD driver output pin was defined as DC output the following mask option must be selected MASK OPTION table When all of SEG and COM pins have been used to drive LCD panel Mask Option name Selected item LCD LED ACTIVE TYPE 1 LCD When more than one of SEG or COM pins had been used for DC output port Mask Option name Selected item LCD ACTIVE TYPE 4 O P During the initial reset cycle all of LCD s lighting system may be lighted or unlighted by mask option All of the LCD output will keep the initial setting until the LCD relative instructions are executed to change the output data MASK OPTION table Mask Option name Selected item LCD DISPLAY IN RESET CYCLE 4 ON LCD DISPLAY IN RESET CYCLE 2 OFF 4 1 1 LCD LIGHTING SYSTEM IN TM8723 There are several LCD lighting systems could be selected by mask option in TM8723 they are e 1 2bias 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 4 duty 1 2bias 1 5duty e 1 3 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias 1 5duty All of these lighting systems are combined with 2 kinds of mask options the one is LCD DUTY CYCLE and the other is LCD BIAS MASK OPTION table LCD duty cycle option Mask Option Name Selected Item LCD LED DUTY CYCLE 1 O P LCD LED DUTY CYCLE 2 DUPLEX 1 2 duty LCD LED DUTY CYCLE 3 1 3 DUTY 4 S LCD LED DUTY CYCLE 4 1 4 DUTY LCD LE
39. section operates when the instructions are executed gt Latch circuit 135 ii DBUSA DBUSH memory Multiplexer amp LCD AC amp RAM data Data bus Strobe data VIS strobe LO to L4 related instruction egments Hriver circuit Segment PLA Figure 5 3 Principal Drawing of LCD Driver Section The LCD driver section consists of the following units e Data decoder to decode data supplied from RAM or table ROM Latch circuit to store LCD lighting information LO to L4 decoder to decode the Lz specified data in the LCD related instructions which specifies the strobe of the latch circuit e Multiplexer to select 1 2duty 1 3duty 1 4duty 1 5duty 77 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual e LCD driver circuitry Segment PLA circuit connected between data decoder LO to L4 decoder and latch circuit The data decoder is used for decoding the content of the working register specified in LCD related instructions as 7 segment pattern on LCD panel The decoding table is shown below Content Output of data decoder DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH 1 1 1 1 0 1 1 1 EE ee EE 1 1 2 i T Note The DBUSF of decoded output be selected as 0 or 1 by mask option The
40. will output L level In this mode TM8723 does not dissipate any power in the stop mode Because the stop mode will set the BCF flag to 1 automatically it is recommended to reset the BCF flag after releasing the stop mode in order to reduce power consumption Before the stop instruction is executed all of the signals on the pins defined as input mode of IOC port must be in the L state and no stop release signal SRFn should be delivered The CPU will then enter the stop mode 45 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual The following conditions cause the stop mode to be released One of the signals on the input mode pin of IOC port is in H state and holds long enough to cause the CPU to be released from halt mode signal change in the INT pin The stop release condition specified by the SRE instruction is met INT pin is exclusive When the TM8723 is released from the stop mode the TM8723 enters the halt mode immediately and will process the halt release procedure If the H signal on the IOC port does not hold long enough to set the SCF1 once the signal on the IOC port returns to L the TM8702 will enter the stop mode immediately The backup flag BCF will be set to 1 The following diagram shows the stop release procedure automatically after the program enters the stop mode STOP HALT normal MODE STOP Yes released mode release Figure 3 16 The stop release state machine Before
41. 003 11 13 TM8723 User s Manual MCX 12h Check the signal change at 1 4 pins that causes the stop mode to be released 2 15 HALT FUNCTION The halt function is provided to minimize the current dissipation of the TM8723 when LCD is operating During the halt mode the program memory ROM is not in operation and only the oscillator circuit pre divider circuit sound circuit I O port chattering prevention circuit and LCD driver output circuit are in operation If the timer has started operating the timer counter still operates in the halt mode After the HALT instruction is executed and no halt release signal SCF1 SCF3 HRF1 6 is delivered the CPU enters the halt mode The following 3 conditions are available to release the halt mode 1 An interrupt is accepted When an interrupt is accepted the halt mode is released automatically and the program will enter halt mode again by executing the RTS instruction after completion of the interrupt service When the halt mode is released and an interrupt is accepted the halt release signal is reset automatically 2 The signal change specified by the SCA instruction is applied to port IOC SCF1 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When the halt mode is released in either 2 or 3 it is necessary that the MSB MSC or MCX instruction is executed in order to test the halt release signal and that the PLC instruction is then exe
42. 111 0000 0000 Stop Operation 123 tenx technology inc Rev 1 0 2003 11 13 Symbol Description Content of Register TM8723 User s Manual Immediate Data Accumulator Complement of Immediate Data Content of Accumulator bit n Program Counter Complement of content of Accumulator Address of program or control data Address X of data RAM Watch Dog Timer Enable Flag Bit n content of Rx 7 segment decoder for LCD Address Y of working register System clock for instruction Address of data RAM specified by HL Interrupt Enable Flag Back up Flag HALT Release Flag Generic Index address register HALT Release Enable Flag Content of generic Index address register Address of LCD PLA Latch Content of lowest nibble Index register STOP Release Enable Flag Content of highest amp middle nibble Index register Start Condition Flag Address of Table ROM Clock Source of Chattering prevention ckt High Nibble content of Table ROM Clock Source of Frequency Generator Low Nibble content of Table ROM Switch Enable Flag Timer 1 Frequency Generator setting Value Timer Overflow Release Flag Clock Source Flag Clock Source of Timer Content of stack Pre Divider 124 tenx technology inc Rev 1 0 2003 11 13
43. 8 are set to 1 SCF2 will also be set to 1 simultaneously When all of the flags in SCF4 5 7 8 are clear start condition flag 2 SCF2 is reset to O Note If start condition flag is set to 1 the program will not be able to enter halt mode Backup flag BCF This flag could be set reset by executing the SF 2h RF 2h instruction 37 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 13 3 STATUS REGISTER 3 STS3 When the halt mode is released by start condition flag 2 SCF2 status register 3 STS3 will store the status of the factor in the release of the halt mode Status register 3 STS3 consists of 4 flags 1 Start condition flag 4 SCF4 Start condition flag 4 SCF4 is set to 1 when the signal change at the INT pin causes the halt release request flag 2 HRF2 to be outputted and the halt release enable flag 2 HEF2 is set beforehand To reset start condition flag 4 SCF4 the PLC instruction must be used to reset the halt release request flag 2 HRF2 or the SHE instruction must be used to reset the halt release enable flag 2 HEF2 2 Start condition flag 5 SCF5 Start condition flag 5 SCF5 is set when an underflow signal from Timer 1 TMR1 causes the halt release request flag 1 HRF1 to be outputted and the halt release enable flag 1 HEF1 is set beforehand To reset start condition flag 5 SCF5 the PLC instruction must be used to reset the halt release request flag 1 HRF1 or the SHE i
44. A ake Ee BE to FS BR x el Er Sa tenx technology inc 8723 4 Bit Micro Controller with LCD Driver User s Manual tenx technology inc tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual CONTENTS CHAPTER 1 General Description 3 1 1 General Description Da a v Este ice ie 3 ju CS 3 1 9 Block Diagram zo 4 tA Pad Diagrami eee Ce 5 1 5 Pagd COoOrdinale iieii ae e a e E Ta 5 120 Pin D SerIBU6nS un i sma pa oido EEEE s Dr ers 6 4 7 Characterizati n s oar rendo ed aco ante aon ea cap eate tanta a 7 1 8 Typical Application Circuitry ea desee a dd a aaa a pneus cau pua 11 CHAPTER 2 TM8723 Internal System Architecture 12 2 1 Power SUPPLY doi dote sana a ed apud HU oem t alat a tet 12 2 2 5ystem r i tetro daa Hat eto aod p ae EIL Ua Ee e CR UR 18 2 3 Program 26 2 4 Program Table Memory 5 2 55 552 lt 55 lt 552 lt 555 lt 26 27 2 5 Index Address Register HL 29 2 6 Slack
45. AC R HL lt RQHL AC B CF CF ADD Rx 00100100 XXXX lt Rx AC CF ADD HL 0010 0100 1000 0000 AC lt R HL CF ADD Rx 0010 0101 lt Rx AC CF ADD HL 0010 0101 1000 0000 AC R HL R HL AC CF SUB Rx 0010 0110 OXXX XXXX lt Rx AC B 1 CF SUB HL 0010 0110 1000 0000 AC lt R HL AC B 1 CF SUB Rx 0010 0111 OXXX lt Rx 1 CF SUB HL 0010 0111 1000 0000 AC R HL lt R HL 1 CF ADN Rx 0010 1000 OXXX XXXX AC lt Rx AC ADN HL 0010 1000 1000 0000 AC lt R HL AC ADN Rx 0010 1001 OXXX XXXX Rx AC ADN HL 0010 1001 1000 0000 AC R HL R HL AC AND Rx 0010 1010 OXXX XXXX AC lt Rx AND AC AND HL 0010 1010 1000 0000 AC R HL AND AC AND Rx 0010 1011 0XXX XXXX lt Rx AND AC AND HL 0010 1011 1000 0000 AC R HL R HL AND AC EOR Rx 0010 1100 OXXX XXXX lt Rx EOR AC EOR HL 0010 1100 1000 0000 AC lt R HL EOR AC EOR Rx 0010 1101 XXXX lt Rx EOR EOR HL 0010 1101 1000 0000 AC R HL R HL EOR AC OR Rx 0010 1110 OXXX lt Rx OR AC OR HL 0010 1110 1000 0000 AC lt R HL OR AC OR Rx 0010 1111 lt Rx OR AC OR HL 0010 1111 1000 0000 AC R HL R HL OR AC ADCI Ry
46. C and data memory Rx 104 tenx technology inc Rev 1 0 2003 11 13 Function Description EOR Rx Function Description EOR HL Function Description EOR Rx Function Description EOR HL Function Description OR Rx Function Description HL Function Description OR Rx Function Description OR HL Function Description ADCI Ry D Function Description TM8723 User s Manual AC R HL R HL amp AC The contents of data memory specified by HL and AC are binary ANDed the result is loaded to AC and data memory specified by HL AC Rx AC The contents of Rx and AC are exclusive Ored the result is loaded to AC AC R HL AC The contents of data memory specified by HL and AC are exclusive Ored the result is loaded to AC AC Rx Rx AC The contents of Rx and AC are exclusive Ored the result is loaded to AC and data memory Rx R HL AC contents of data memory specified by HL exclusive Ored the result is loaded to AC and data memory data memory specified by HL AC Rx AC The contents of Rx and AC binary Ored the result is loaded to AC R HL AC The contents of HL and are binary Ored the result is loaded to AC HL indicates an index address of data memory AC Rx Rx AC The contents of Rx and AC are binary Ored the result is load
47. CLK 4 2 setting value for the frequency generator is and duty cycle is 1 2 ALM 1COh signal is outputted This instruction must be executed after the FRQ related instructions HALT Wait for the halt release caused by timer 1 asas Halt released ALM 0 Stop the buzzer output 3 5 INPUT OUTPUT PORTS Three ports are available in TM8723 IOA IOB and IOC Each I O port is composed of 4 bits and has the same basic function When the pins are defined as non IO function by mask option the input output function of the pins will be disabled 61 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 3 5 1 IOA PORT IOA1 IOA4 pins are MUX with CX SEG24 RR SEG25 RT SEG26 and RH SEG27 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG24 IOA1 CX 2 IOA1 SEG25 IOA2 RR 2 10A2 5 26 2 SEG27 IOA4 RH 2 IOA4 In initial reset cycle the IOA port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPA instructions Executing OPA instructions may output the content of specified data memory to the pins defined as output mode the pins defined as the input mode will still remain the input mode Executing IPA instructions may store the signals applied to the IO pins into the specified data memory When the IO pins are defin
48. D 0011 0000 DDDD YYYY Ry D CF CF ADCI RyD 0011 0001 YYYY AC Ry lt Ry D CF CF SBCI RyD 0011 0010 DDDD YYYY AC lt Ry DB CF CF SBCI RyD 0011 0011 DDDD YYYY AC Ry lt Ry DB CF CF ADDI RyD 0011 0100 DDDD YYYY AC Ry D CF 120 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Instruction Machine Code Function Flag Remark ADDI RyD 0011 0101 YYYY AC Ry Ry D CF SUBI RyD 0011 0110 DDDD YYYY lt 1 SUBI RyD 0011 0111 YYYY lt Ry 1 ADNI Ry D 0011 1000 DDDD YYYY lt Ry ADNI RyD 0011 1001 YYYY AC Ry lt Ry ANDI RyD 0011 1010 DDDD YYYY AC lt Ry AND D ANDI Ry D 0011 1011 DDDD YYYY Ry D EORI Ry D 0011 1100 DDDD YYYY lt Ry EOR D EORI Ry D 0011 1101 DDDD YYYY AC Ry lt Ry EOR D ORI RyD 0011 1110 DDDD YYYY AC lt Ry ORD ORI Ry D 0011 1111 DDDD YYYY __ AC Ry lt Ry ORD INC Rx 0100 0000 OXXX XXXX lt Rx 1 CF INC HL 0100 0000 1000 0000 AC R HL lt RQHL 1 CF DEC Rx 0100 0001 OXXX XXXX lt Rx CF DEC HL 0100 0001 1000 0000 AC R HL lt R HL CF IPA Rx 0100 0010 OXXX XXXX
49. D DUTY CYCLE 5 1 5 DUTY LCD bias option Mask Option name Selected item LCD BIAS 3 NO BIAS LCD BIAS 2 1 2 BIAS LCD BIAS 1 1 3 BIAS 75 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual The frame frequency for each lighting system is shown below these frequencies could be selected by mask option All of the LCD frame frequencies in the following tables based on the clock source frequency of the pre divider PH0 is 32768Hz The LCD alternating frequency in duplex 1 2 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 16Hz LCD frame frequency 2 TYPICAL 32Hz LCD frame frequency 2 FAST 64Hz LCD frame frequency 2 O P OHz LCD not used The LCD alternating frequency in 1 3 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 21Hz LCD frame frequency 2 TYPICAL 42Hz LCD frame frequency 2 FAST 85Hz LCD frame frequency 2 O P OHz LCD not used The LCD alternating frequency in 1 4 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 16Hz LCD frame frequency 2 TYPICAL 32Hz LCD frame frequency 2 FAST e4Hz LCD frame frequency 2 OHz LCD not used The LCD alternating frequency in 1 5 duty type Mask Option name Selected item Remark alterna
50. DD2 0 3 to 5 5 V VDD3 0 3 to 8 5 V Maximum Input Voltage Vin 0 3 to VDD1 2 0 3 V Maximum output Voltage Vout1 0 3 to VDD1 2 0 3 V Vout2 0 3 to VDD3 0 3 V Maximum Operating Temperature Topg 20 to 70 C Maximum Storage Temperature Tstg 25 to 125 C POWER CONSUMPTION at Ta 20 C to 70 C GND 0V Name Sym Condition Min Typ Max Unit HALT mode IlAtri Only 32 768KHz Crystal oscillator 2 uA operating without loading Ag mode VDD1 1 5V BCF 0 IHALT2 Only 32 768KHz Crystal oscillator 2 uA operating without loading Li mode VDD2 3 0V BCF 0 STOP mode STOP 1 uA Note When RC oscillator function is operating the current consumption will depend on the frequency of oscillation INTERNAL RC FREQUENCY RANGE Option Mode BAK Min Typ Max 250KHz 1 5V 200KHz 300KH 400KHz 3 0V 200KHz 250KHz 300KHz 500KHz 1 5V 450KHz 600KHz 750KHz 3 0V 400KHz 500KHz 600KHz 7 tenx technology inc Rev 1 0 2003 11 13 ALLOWABLE OPERATING CONDITIONS at Ta 20 C to 70 C GND OV TM8723 User s Manual Name Symb Condition Min Max Unit VDD1 1 2 5 25 V Supply Voltage VDD2 2 4 5 25 V VDD3 2 4 8 0 V Oscillator Start Up Voltage VDDB Crystal Mode 1 3 V Oscillator Sustain Voltage VDDB Crystal Mode 1 2 V Supply Voltage VDD1 Ag Mode 1 2 1 65 V Supply Voltage VDD2
51. E 4 DUAL The operation of the dual clock option is shown in the following figure When this option is selected by mask option the clock source BCLK of system clock generator will switch between XT clock and CF clock according to the user s program When the halt and stop instructions are executed the clock source BCLK will switch to XT clock automatically The XT clock provides the clock to the pre divider timer port chattering prevention and LCD circuitry in this option Halt Halt Halt mode Slow mode Slow Fast mode XTOSC active XTOSC active 4 XTOSC active CFOSC stop HALT CFOSC stop Fest CFOSC active released Stop Sto released Reset p release Reset Reset state Reset Stop mode XTOSC active d XTOSC stop Power on reset CFOSC sto Reset pin reset Watchdog timer reset Key reset CFOSC stop State Diagram of Dual Clock Option was shown on above figure After executing FAST instruction the system clock generator will hold 12 CF clocks after the CF clock oscillator starts up and then switches CF clock to BCLK This will prevent the incorrect clock from delivering to the system clock in the start up duration of the fast clock oscillator 22 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual CF E clock FAST BCLK w HOLD 12
52. F3 PDV X2 Enable HEF2 INT X1 Enable HEF1 TMR1 SIE X 1110 1001 00X0 XXXX 5 Enable IEF5 KEY S X3 Enable PDV X2 Enable IEF2 INT X1 Enable IEF1 TMR1 X0 Enable IEFO CPT PLC X 1110 101X 00X0 XXXX 8 Reset PH15 11 X5 3 0 Reset HRF5 3 0 SRE X 1110 1101 0000 X7 Enable SRF7 SRF7 KEY_S X5 Enable SRF5 SRF5 INT X4 Enable SRF4 SRF4 C Port FAST 1110 1110 0000 0000 SCLK High Speed Clock SLOW 1110 1111 0000 0000 SCLK Low Speed Clock SF x 1111 0000 X00X XXXX 7 Reload 1 Set RL1 X4 WDT Enable WDF X3 HALT after EL X2 ELLIGHT On X1 BCF Set BCF X0 CF Set CF RF x 1111 0100 X00X0XXX X7 Reload 1 Reset RL1 X4 WDT Reset WDF X2 ELLIGHT Off X1 BCF Reset BCF X0 CF Reset CF SF2 X 1111 1000 0000 XX00 X3 Enable INT powerful Pull INTPL low X2 Close all Segments RSOFF RF2 x 1111 1001 0000 XX00 X3 Disable INT powerful Pull INTPL low X2 Release Segments RSOFF ALM x 1111 101X XXXX XXXX 8 7 6 111 FREQ 8 7 6 100 DC1 X8 7 6 011 PH3 X8 7 6 010 PH4 X8 7 6 001 PHS X8 7 6 000 DC0 5 0 lt 15 10 ELC X 1111 110X XXXX XXXX X871 BCLKX ELP CLK 8 0 7 6 11 BCLK 8 BCLKX X7 6 10 BCLK 4 X7 6 01 BCLK 2 X7 6 00 BCLK X5 4 11 1 1 ELP DUTY 5 4 10 1 2 5 4 01 2 3 5 4 00 3 4 3 2 11 5 ELC CLK X3 2 10 PH6 X3 2 01 PH7 X3 2 00 PH8 X1 0 11 1 1 ELC DUTY X1 0 10 1 2 X1 0 01 1 3 X1 0 00 1 4 HALT 1111 1110 0000 0000 Halt Operation STOP 1111 1
53. For input triggered type Mask Option name Selected item INT PIN TRIGGER MODE 1 RISING EDGE INT PIN TRIGGER MODE 2 FALLING EDGE IEF2 Interrupt request SCF2 Halt release request Mask option HRF 2 PLC 4h nitial clear pulse Mask option Interrupt 2 receive signal Open type Note For Ag battery power supply positive power is connected to VDD1 for anything other than Ag battery power supply it is connected to VDD2 This figure shows the INT Pin Configuration 3 8 Key Matrix Scanning TM8723 shared the timing of LCD LED waveform to scan the key matrix circuitry and these scanning output pins are SEG1 12 for easy to understand named these pins as 1 K12 The time sharing of LCD LED waveform will not affect the display of LCD LED panel The input port of key matrix circuitry is composed by KI1 4 pins these pins are muxed with SEG32 SEG35 pins and selected by mask option MASK OPTION table Mask Option name Selected item SEG32 IOC1 KI1 3 KI1 2 2 3 2 SEG34 IOC3 KI3 3 KI3 SEGS35 IOCA KIA 3 4 The typical application circuit of key matrix scanning is shown below tenx technology inc Rev 1 0 2003 11 13 71 TM8723 User s Manual Executing SPK X instruction could set the scanning type of key matrix The bit pattern of this instruction is shown
54. K8 For ELC setting Discharge pulse X3 X2 X1 X0 Duty cycle DPH 100 14 00 1 3 duty The default setting after the initial reset is ELP PHO clock of pre divider and 3 4 duty cycle ELC 8 clock of pre divider and 1 4 duty cycle The timing of the duty cycle is shown below PH0 PH8 1 4 duty 1 3 duty owe 1 2 duty eee p ag E NT E 1 1 duty Example ELC 110 ELP outputs BCLK clock with 1 3 duty cycle and ELC outputs 8 clock with 1 4 duty cycle SF 4h Enables the light control signal LIT and turns on the EL light driver RF 4h Disables the light control signal and turns off the EL light driver 3 7 EXTERNAL INT PIN The INT pin can be selected as pull up or pull down or open type by mask option The signal change either rising edge or falling edge by mask option sets the interrupt flag delivering the halt release request flag 2 HRF2 In this case if the halt release enable flag HEF2 is provided the start condition flag 2 is delivered If the INT pin interrupt enable mode IEF2 is provided the interrupt is accepted MASK OPTION table 70 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual For internal resistor type Mask Option name Selected item INT PIN INTERNAL RESISTOR 1 PULL HIGH INT PIN INTERNAL RESISTOR 2 PULL LOW INT PIN INTERNAL RESISTOR 3 OPEN TYPE
55. LCD LED ACTIVE TYPE 3 LED LOW ACTIVE The following schema will illustrate the application difference between high active mode and low active mode 1 High Active Mode SEG1 52 S3 S4 S5 S6 S7 S8 ames 82 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 Low Active Mode a E SEG1 S355 S 52 S4 5658 Note Due to the sink current capability if all segment more than 8 turn on at Low Active Mode the same time the IC may be burn down if one segment has 5mA then eight segments 40m4A Mask option can also be used to select the alternating frequency All of the LED alternating frequencies based on the clock source frequency of the pre divider are 32768Hz The LED alternating frequency in 1 2 duty mode LED duty cycle 1 2 duty frequency The LED alternating frequency in 1 3 duty mode LED duty cycle 1 3 duty frequency The LED alternating frequency in 1 4 duty mode LED duty cycle 1 4 duty Mask option frequency The LED alternating frequency in 1 5 mode LED duty cycle 1 5 duty Mask option LED alternating 102Hz 205Hz 83 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual frequency Mask option permits LED driver output pins SEG to be used for CMOS type DC output or P open drain DC output ports In this case it is possible to u
56. M Preset Letter D Duty Cycle x D p 0 1 4 duty 0 11 1 Ny xa 1 20 12 1 1 duty FRQX D X Function Frequency generator D X Description Loads the data X X7 and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting b The bit pattern of preset letter N 116 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Programming divider Bite Bits Bit4 Bit2 bit 1 bito FRQX DX Note X7 represents the data specified in operand X TMS Rx Function Description TMS HL Function Description Preset Letter D Duty Cycle xr D D P j po O duy umm p A 1 x 1 0 1 duy 1 1 duty 1 FRQ D Rx The content of Rx and AC as preset data N 2 FRQ D QHL The content of tables TOM specified by index address buffer as preset data N 3 FRQX D X The data of operand in the instruction assigned as preset data N Select timer 1 clock source and preset timer 1 The content of data memory specified by Rx and AC are loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Select clock Setting value The clock source option for timer 1 49 Select timer 1 clock source and preset timer 1 The content of table ROM specified by HL is loaded to timer 1 to start the t
57. M O is mask option IPC OPC This figure shows the organization of IOC port Note If the input level is in the floating state a large current straight through current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state 67 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual When the IOC pin has been defined as the output mode both the pull low and low level hold devices will be disabled Low level hold function option Mask Option name Selected item C PORT LOW LEVEL HOLD 1 USE C PORT LOW LEVEL HOLD 2 NO USE 3 5 3 1 Chattering Prevention Function and Halt Release The port IOC is capable of preventing high low chattering of the switch signal applied on IOC1 to IOC4 pins The chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing SCC instruction and the default selection is PH10 after the reset cycle When the pins of the IOC port are defined as output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry SPC 1 Interrupt HRF0 SPC 4 Edge s Q request SPC 8 detect R IOC1 IOC2 edge dectect amp SCF1 yHALT released chattering s Q re C 1 Interrupt accept SCC s Q R
58. Note 1 The input output ports operate between GND and VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 12 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 1 1 2 MASK OPTION table VDD1 Internal E BA logic 1 2 BIAS AT AG BATTERY POWER SUPPLY Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY LCD BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 2 1 1 3 1 3 BIAS AT AG BATTERY POWER SUPPLY MASK OPTION table CUP1 Internal logic Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY LCD BIAS 1 1 3 BIAS 13 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Note 1 The input output p
59. OM and table ROM TROM shares this memory space together The partition formula for PROM and TROM is shown below Instruction ROM memory space 128 N words Table ROM memory space 256 16 N bytes N 1 12 Note The data width of table ROM is 8 bit The partition of memory space is defined by mask option the table is shown below MASK OPTION table Mask Option name Selected item Instruction ROM Table ROM memory space memory space Words Bytes INSTRUCTION ROM lt gt TABLE ROM 1 N 1 128 2816 INSTRUCTION ROM lt gt TABLE ROM 2 N 2 256 2560 INSTRUCTION ROM lt gt TABLE ROM 3 N 3 384 2304 INSTRUCTION ROM lt gt TABLE ROM 4 N 4 512 2048 INSTRUCTION ROM lt gt TABLE ROM 5 5 640 1792 INSTRUCTION ROM lt gt TABLE ROM 6 N 6 768 1536 INSTRUCTION ROM lt gt TABLE ROM 7 7 896 1280 INSTRUCTION ROM lt gt TABLE ROM 8 N 8 1024 1024 INSTRUCTION ROM lt gt TABLE ROM 9 N 9 1152 768 INSTRUCTION ROM lt gt TABLE ROM A N 10 1280 512 INSTRUCTION ROM lt gt TABLE ROM B N 11 1408 256 INSTRUCTION ROM lt gt TABLE ROM C 12 1536 0 27 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 4 1 INSTRUCTION ROM PROM There are some special locations that serve as the interrupt service routines such as reset address 000H interrupt 0 address 014H interrupt 1 address 018H interrupt 2 address 010H
60. POWER SUPPLY MASK OPTION table CUP1 CUP2 VDD3 VDD2 VDD1 BAK Internal GND logic rl EXT V Mask Option name Selected item POWER SOURCE 1 EXT V LCD BIAS 1 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required 2 2 SYSTEM CLOCK XT clock slow clock oscillator and CF clock fast clock oscillator compose the clock oscillation circuitry and the block diagram is shown below The system clock generator provided the necessary clocks for execution of instruction The pre divider generated several clocks with different frequencies for the usage of LCD driver frequency generator etc The following table shows the clock sources of system clock generator and pre divider in different conditions ES C O PHO Slow clock only option XT clock fast clock only option CF clock Initial state dual clock option Halt mode dual clock option Slow mode dual clock option Fast mode dual clock option BCLK XT clock CF clock XT clock XT clock XT clock CF clock tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 2 1 CONNECTION DIAGRAM OF SLOW CLOCK OSCILLATOR
61. Power onreset OSC active Reset Reset pin reset Watchdog timer reset Key reset This figure shows the State Diagram of Single Clock Option 2 2 4 PREDIVIDER The pre divider is a 15 stage counter that receives the clock from the output of clock switch circuitry PH0 as input When PH0 is changed from H level to L level the content of this counter changes The PH11 to PH15 of the pre divider are reset to 0 when the PLC 100H instruction is executed or at the initial reset mode The pre divider delivers the signal to the halver tripler circuit alternating frequency for LCD display system clock sound generator and halt release request signal 1 port chattering prevention clock Frequency epa Hinterrupt request Generator mode BCLK Initial EET FAST instruction T1 T2 T3 T4 Sclk PLC 8H R FAST instruction Interrupt 4 Q HALT release Clock System Fall edge S HRF3 request flag Switch clock detector XTOSC n f circuit generator MSC instruction Data bus 2 mu Clock switch circuit o timer circuit PLC 100H initial CFOSC Single clock option Dual clock option To sound circuit tribler circuit 24 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual This figure shows the Pre divider and its Peripherals The PH14 delivers the
62. RF3 enable flag Enable the stop release Enable the stop release Enable the stop release Stop release request caused by signal request caused by signal request caused by signal request flag change on 1 4 SKI change on INT pin change on IOC HRF2 When the stop release enable flag 7 SRF7 is set to 1 the input signal change at the KI1 4 pins causes the stop mode to be released In the same manner when SRF4 SRF3 and SRF5 are set to 1 the input signal change at the input mode pins of IOC port and the signal changed on INT pin causes the stop mode to be released respectively Example This example illustrates the stop mode released by port IOC KI1 4 and INT pin Assume all of the pins in IOD and IOC have been defined as input mode PLC 25h Reset the HRFO HRF2 and HRF5 SHE 24h HEF2 and HEF5 is set so that the signal change at INT or 1 4 causes start condition flag 4 8 to be set SCA 10h SEF4 is set so that the signal changes at port IOC cause the start conditions SCF1 to be set SRE ObOh SRF7 5 4 are set so that the signal changes at Kl1 4 pins port IOC and INT pin cause the stop mode to be released STOP Enter the stop mode Ama a aut ike STOP release MSC 10h Check the signal change at INT pin that causes the stop mode to be released MSB 11h Check the signal change at port IOC that causes the stop mode to be released 43 tenx technology inc Rev 1 0 2
63. The mapping table is shown below Table 2 4 The mapping table of LCP and LCD instructions __ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH LCD TQHLO TOHL1 TOHL2 TOHL3 T HL4 TOHL5 TOHL6 T HL7 5 SF2 4h Turns off the LCD display 6 RF2 4h Turns on the LCD display 4 1 3 3 CONCRETE EXPLANATION Each LCD driver output corresponds to the LCD 1 5 duty panel and has 5 latches refer to Figure Sample Organization of Segment PLA Option Since the latch input and the signal to be applied to the clock strobe are selected with the segment PLA the combination of the segments in the LCD driver outputs is flexible In other words one of the data decoder outputs DBUSA to DBUSH is applied to the latch input L and one of the PSTBO to PSTB1Fh outputs are applied to clock CLK Refer to Chapter 5 for detail description of these instructions 80 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual n gt Mask option L Q Mask option CLK Mask option L m dal E Mask option CLK a n 1 9 2 Mask option L gt i Mask opion Mask option CLK Multiplexen LOD Driver Mask option L Q LA Mask option CLK Mask option Q Mask option CLK 5 ka Figure Sample Organization of Segment PLA Option 4 1 3 4 THE CONFIGURATION FILE FOR MASK OPTION When
64. XT CLOCK This clock oscillation circuitry provides the lower speed clock to the system clock generator pre divider timer chattering prevention of IO port and LCD circuitry This oscillator will be disabled when the fast clock only option is selected by mask option or it will be active all the time after the initial reset In stop mode this oscillator will be stopped There are 2 type oscillators can be used in slow clock oscillator selected by mask option 2 2 1 1 External 32 768KHz Crystal oscillator XT CLOCK MASK OPTION table Mask Option name Selected item SLOW CLOCK TYPE FOR SLOW ONLY OR DUAL 1 X tal When backup flag BCF is set to 1 the oscillator operates with an extra buffer in parallel in order to shorten the oscillator start up time but this will increase the power consumption Therefore the backup flag should be reset unless required otherwise The following table shows the power consumption of Crystal oscillator in different conditions Ag power option Li power option EXT V option BCF 1 BCF 0 reset reset 19 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 2 1 2 External RC oscillator XT CLOCK MASK OPTION table Mask Option name Selected item SLOW CLOCK TYPE FOR SLOW ONLY OR DUAL 2 RC XIN 540 2 2 2 2 CONNECTION DIAGRAM OF FAST CLOCK OSCILLATOR CF CLOCK The CF clock
65. active in Low active COMS3 in Low active COM4 in Low active COMS Low active COM High active CON2 in High active in High active in High active COMS5 in High active segnments on 1 2 3 4 5 with unlighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on lighted sides segnments on COM1 2 3 4 5 COM 1 with COM with with with 5 with COM1 2 with 1 3 with COM1 4 with 1 5 with COM2 3 with COM2 4 with COM2 5 with COM3 4 with COM3 5 with COM4 5 with with lighted sides 93 f period TM8723 User s Manual tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual iii Display Turn Off VDD COM1 2 3 4 5 uM in low active _ GND VDD COM1 2 3 4 5 high active GND VDD All LED driver outputs GND iv Stop mode VDD COM1 2 3 4 5 in low active VDD COM1 2 3 4 5 in high active GND VDD All LED driver outputs GND Figure 2 43 1 5 du
66. ag WDF to 1 At the same time the content of the timer will be cleared 56 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Once the watchdog timer is enabled the timer will be paused when the program enters the halt mode or stop mode When the TM8723 wakes up from the halt or stop mode the timer operates continuously It is recommended to execute SF 10h instruction before the program enters the halt or stop mode in order to initialize the watchdog timer Once the watchdog timer is enabled the program must execute SF 10h instruction periodically to prevent the timer overflowed The overflow time interval of watchdog timer is selected by mask option MASK OPTION table Mask Option name Selected item WATCHDOG TIMER OVERFLOW TIME INTERVAL 1 8 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 2 64 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 3 512 x PH10 Note timer overflow time interval is about 16 seconds when PHO 32 768KHz 3 3 CLOCK GENERATOR 3 3 1 FREQUENCY GENERATOR The Frequency Generator is a versatile programmable divider that is capable of delivering a clock with wide frequency range and different duty cycles The output of the frequency generator may be the clock source for the alarm function timer1 timer2 and RFC counter The following shows the organization of the frequency generator BCLK p opt PE a Pen E I Frequency output FREQ PH0 FRQ D Rx
67. anual SCC X Function Setting the clock source for IOA IOC chattering prevention PWM output and frequency generator Description The following table shows the meaning of each bit for this instruction Bit pattern Clock source setting Bit pattern Clock source setting X6 1 The clock source comes X6 0 The clock source comes from the system clock from the 0 Refer to BCLK section 3 3 4 for 0 X2 X1 X0 001 Chattering prevention 2 1 0 010 Chattering prevention clock 10 clock 8 2 1 0 100 46 115 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual XT 5 4 3 is reserved FRQ D Rx Function Frequency generator D Rx AC Description Loads the content of AC and data memory specified by Rx and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting x Thebit pattern of presetletterN _ Programming divider Preset Letter D Duty Cycle D x O O day L0 11 uty 1 ty FRQ HL Function Frequency generator D T HL Description Loads the content of Table ROM specified by HL and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting kw The bit pattern of preset letter N Programming divider FRQ D HL Note TO T7 represents the data of table RO
68. below Instruction Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO SPK X XT X6 X5 X4 X3 X2 X1 X0 Bit Patten Setting Halt Release by 6 0 Normal Key Scanning Scanning Cycle The bit pattern of X for Key Matrix scanning output to SEG1 12 K1 1 Hi z i Hi z Hi z Hi z HzHez 1 zzzi 2 Hi Hz Hz Hz Hz Hcr iz Htz Htz H Hi z Hi z ahaha Macer Hcr Hz z Hz Hiz Hz Biz T Hz Hz Hz H Hi TTE IE TIENE i Hi i KAKAK Em Hi z Hi z Hi z Hi z Hi T Hi z Hi LAS se Hi I T N N N N N IN I I N Hi z Hi z Hi z 1 KERN Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z ice i geez a 1 Hi z Hi z Hi z Hi z 1 1 IHi z Hi z Hi z Hi z Hi z Hi z 72 tenx technology inc Rev 1 0 2003 11 13 S s E N N TM8723 User s Manual Hi z T i 1 Notes 1 1 H L LED LCD 2 K1 12 SEG1 12 output in scanning interval When Kl1 4 is defined for Key matrix scanning input by mask option it is necessary to execute SPC instruction to set the internal unused IOC port as output mode before the key matrix scanning function is active The organization of Key matrix scanning input port is shown in next page Once one of 1 4 pin detected the sig
69. by the stop release enable flags SRFx and these flags should be clear before the chip enters the stop mode All of the pins in IOC port had to be defined as the input mode and keep in 0 state before the chip enters the STOP mode or the program can not enter the STOP mode Instruction SRE is used to set or reset the stop release enable flags SRF4 5 7 The following table shows the stop release request flags The OR ed The OR ed input The rising or latched signals for mode pins of IOC falling edge on INT 1 4 port pin Stop release request flag HRF2 Stop release enable flag SRF7 SRF4 SRF5 2 14 CONTROL REGISTER CTL The control register CTL comes in 4 types control register 1 CTL1 to control register 4 CTLA 2 14 1 CONTROL REGISTER 1 CTL1 The control register 1 CTL 1 being a 1 bit register 1 Switch enable flag 4 SEF4 Stores the status of the input signal change at pins of IOC defined as input mode that causes the halt mode or stop mode to be released Executed SCA instruction may set or reset these flags The following table shows Bit Pattern of Control Register 1 CTL1 Bit 4 Switch enable flag 4 40 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual SEF4 Enables the halt release caused by the signal change on IOC port Write only The following figure shows the organization of control register 1 CTL1 HALT Released Request Edge detector loc In
70. contents of Ry and D binary ANDed the result is loaded to AC D 0H FH AC Rx Ry amp D D represents an immediate data The contents of Ry and D are binary ANDed the result is loaded to AC and working register Ry D 0H FH AC Ry D D represents an immediate data The contents of Ry and D are exclusive OREd the result is loaded to AC 107 tenx technology inc Rev 1 0 2003 11 13 EORI Ry D Function Description ORI Ry D Function Description ORI D Function Description TM8723 User s Manual D 0H FH AC Rx lt Ry D represents an immediate data The contents of Ry D are exclusive OREd the result is loaded to AC and working register Ry D 0H FH AC Ry D D represents an immediate data The contents of Ry and D are binary OREd the result is loaded to AC D 0H FH AC Rx lt Ry D D represents an immediate data The contents of D are binary OREd the result is loaded to AC and working register Ry D 0H FH 5 4 LOAD STORE INSTRUCTIONS STA Rx Function Description STA HL Function Description LDS Rx D Function Description LDA Rx Function Description LDA HL Function Description Rx AC The content of AC is loaded to data memory specified by Rx R HL AC The content of AC is loaded to data memory specified by HL AC Rx D Immediate data D is loaded to the AC
71. cription RF2 X Function Description PLC Function Description TM8723 User s Manual Sets flag Description of each flag X3 1 Enable INT powerful pull low X2 1 Disables the LCD LED segment output 7 4 1 0 is reserved Resets flag Description of each flag 1 Disable INT powerful pull low X2 1 Enables the LCD LED segment output X7 4 1 0 is reserved Pulse control The pulse corresponding to the data specified by X is generated 1 Halt release request flag HRFO caused by the signal at I O port C is reset X1 1 Halt release request flag HRF1 caused by underflow from the timer 1 is reset and stops the operating of timer 1 TM1 X2 1 Halt or stop release request flag HRF2 caused by the signal change at the INT pin is reset 1 Halt release request flag HRF3 caused by overflow from the predivider be reset X5 1 Halt release request flag HRF5 caused by the signal change to H L LED LCD on 1 4 in scanning interval is reset X8 1 The last 5 bits of the predivider 15 bits are reset When executing this instruction X3 must be set to 1 X4 X8 are reserved 119 tenx technology inc Rev 1 0 2003 11 13 Appendix A TM8723 Instruction Table TM8723 User s Manual Inst
72. ctive es GND VDD Unlighted LCD driver outputs Uc GND v VDD Lighted LCD driver outputs eee GND iii Display Turn Off VDD COM1 in Z ClLLeeLLLLlLL 0 00 ti Ovalle 0 r r GND E VDD COMI in high active __ 0 0 0 0 0 0 00000000 o GND DEM VDD All LED driver 0 007 outputs nnns GND iv STOP Mode VDD COMA i ti 54 GND VDD 4 Abp m lllIl LLL LlL e ea us high active 0 0 o oOo GND VDD All LED driver outputs GND Figure 2 39 Static LED Waveform 85 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 4 2 2 1 2 DUTY LIGHTING SYSTEM FOR LED DRIVER i Initial clear mode ee VDD COM1 COM2 p in ti In low active 7 0 0 0 0 GND ied VDD 1 2 in high active GND gt VDD All LED driver ae outputs C C LLelleeeeoeoer r e C C GND ii Normal operation mode alternating frquency COM1 VDD mode GND COM2 VDD in low active mode GND COM1 VDD in high Sele EBNENMENRE mode GND COM2 VDD in high active mode GND LED driver outputs VDD for LED segments J on COM1 with lighted sides TT TTT GND LED driver outputs for LED segments COM2with j p p pv lighted sides _ GND LCD driver outputs VDD for LCD segments on COM1 COM2 with light
73. cuted to reset the halt release signal Even when the halt instruction is executed in the state where the halt release signal is delivered the CPU does not enter the halt mode 2 16 HEAVY LOAD FUNCTION When heavy loading lamp light up motor start etc causes a temporary voltage drop on supply voltage the heavy loading function set BCF 1 prevents TM8723 from malfunctioning especially where a battery with high internal impedance such as Li battery or alkali battery is used During back up mode the 32 768KHz Crystal oscillator will add an extra buffer in parallel and switch the internal power BAK from VDD1 to VDD2 Li power option only In this condition all of the functions in TM8723 will work under VDD voltage range this will cause 8723 to get better noise immunity For shorten the start up time of 32 768KHz Crystal oscillator TM8723 will set the BCF to 1 during reset cycle and reset BCF to 0 after reset cycle automatically in Ag and Li power mode option In EXT V power mode option however BCF is set to 1 by default setting and can not be reset to 0 and BCF will be reset to 0 by default setting during normal operation Table 3 1 The back up flag status in different conditions 1 Agoption Lioption EXT V option Reset cycle BCF 1 BCF 1 BCF 0 44 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual After reset cycle BCF 1 BCF 1 BCF 0 large current SF 2 executed BCF 1 BCF 1 BCF 1 RF 2 ex
74. d item SEG28 IOB1 ELC 2 IOB1 SEG29 IOB2 ELP 2 2 5 2 2 IOB3 SEG31 IOBA BZ 2 IOB4 64 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Initial clear SPB 1 i lt Q L CLK IOB1 9 gt bit0 M O Initial clear SPB 2 bit1 Q s il IOB2 gt Initial clear 9 4 bit2 lt Q L CLK h IOB3 4 gt i M O Initial clear LI M SPB 8 TE M O Mb OBB OPBS OPB Note M O is mask option The following figure shows the organization of IOB port Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state After the reset cycle the IOB port is set as input and each bit of port can be defined as input or output individually by executing SPB instructions Executing OPB instructions may output the content of specified data memory to the pins defined as output mode the other pins which are defined as the input will still be input Executed IPB instructions may store the signals applied on the IOB pins into the specified data memory When the IOB pins are defined as the output executing IPB instruction will save the data stored in the output latch into the specified data memory Before executing SPB instruction to define the pins as output the OPB instruction must be executed t
75. e the frequency for melody usage When the frequency generator is used to generate the melody output the tone table is shown below 1 The clock source is PHO i e 32 768 Hz 2 The duty cycle is 1 2 Duty D 2 3 FREQ is the output frequency 4 ideal is the ideal tone frequency 5 96 is the frequency deviation The following table shows the note table for melody application FREQ Ideal Tone FREQ Ideal C2 249 65 5360 65 4064 0 19 C4 62 260 063 261 626 0 60 293 665 309 132 58 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual E2 198 82 3317 82 4069 0 09 E4 49 327 680 329 628 0 59 0 18 0 07 165 495 164 814 0 41 184 090 184 997 0 49 F5 4A3 69 234 057 233 082 0 42 5 17 910 222 932 328 2 37 Note 1 Above variation does not include X tal variation 2 If PHO 65536Hz C3 B5 may have more accurate frequency During the application of melody output sound effect output or carrier output of remote control the frequency generator needs to combine with the alarm function BZB BZ For detailed information about this application refer to section 3 4 3 3 3 Halver Doubler Tripler The halver doubler tripler circuits are used to generate the bias voltage for LCD and are composed of a combination of PH2 PH3 PH4 PH5 When the Li battery application is used the 1 2 VDD voltage ge
76. ecuted BCF 0 BCF 0 BCF 0 For low power consumption application reset BCF to 0 is necessary the 32 768KHz Crystal oscillator operates with a normal buffer only so switch the internal power BAK to VDD1 Li power option only In this condition only peripheral circuitry operates under VDD voltage range the other functions will operate under 1 2 VDD voltage range In Ag and EXT V power options the internal power BAK will not be affected by the setting of BCF With Li power option it is necessary to connect a 0 1uf capacitor from BAK power pin to GND for the backup mode application When the heavy load function is performed the current dissipation will increase Table 3 2 Ag gr Open amic ius Internal logic VDD VDD VDD VD VD logic Table 3 3 Li power Initial reset After reset Stop mode RE2 BCF ee logic Table 3 4 EXT V power option Initial reset After reset Stop mode 58 2 RF2 SSK a ode lp ul plos sasi BCF logic Note When the program enters the stop mode the BCF will set to 1 automatically to insure that the low speed oscillator will start up in a proper condition while stop release occurs 2 17 STOP FUNCTION STOP The stop function is another solution to minimize the current dissipation for TM8723 In stop mode all of functions in TM8723 are held including oscillators All of the LCD corresponding signals COM and Segment
77. ed as the output mode executing IPA instruction will store the content that stored in the latch of the output pin into the specified data memory Before executing SPA instruction to define the I O pins as the output mode the OPA instruction must be executed to output the data to those output latches beforehand This will prevent the chattering signal on the I O pin when the I O mode changed IOA port had built in pull down resistor by mask option and executing SPA instruction to enable disable this device MASK OPTION table Mask Option name Selected item IOA PULL LOW RESISTOR 1 USE IOA PULL LOW RESISTOR 2 NO USE 62 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Initial clear IOA1 B y gt bitO M O Initial clear 40 SPA 2 bit1 Q L gt bit1 od Data Initial clear D 4 bit2 Bus L s bit2 Initial clear SCLK SPA 8 bit3 bit3 SPA 10 dc of OPA OPAS 0 IBA 24 Note M O is mask option This figure shows the organization of IOA port Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state 3 5 1 1 Pseudo Serial Output IOA port may operate as a pseudo serial output port by executing OPAS instruction IOA port must be defined as the output mode before executing OPAS instructi
78. ed sides TI K s aGND LCD driver outputs gt VDD for LCD segments on COM1 COM2 with unlighted sides lt GND 86 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual iii Display Turn Off cd VDD 1 COM2 Er d in low active 0 0 00 0 GND VDD COM1 COM2 gt L lcoOIGC I I C D b 9 0x in high active GND VDD All LED driver outputs GND iv STOP Mode n VDD COM1 COM2 in ti in low active VDD COM1 COM2 in high active VDD ALL LED driver outputs GND Figure 2 40 Duplex 1 2 duty LED Waveform 4 2 3 1 3 DUTY LIGHTING SYSTEM FOR LED DRIVER i Initial clear mode COM1 COM2 7 VDD COM3 in low active GND COM1 COM2 YDB COM3inhigh active 086 GND VDD All LED driver outputs GND 87 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual ii Normal operation mode alternating frquency gt COM1 VDD in low active ECC Y Ag mode GND COM2 VDD in low active mode GND COM3 VDD in low active mode GND COM1 VDD in high active mode GND COM2 VDD in high active mode GND COM3 VDD in high active mode GND segments on VDD COM1 with lighted sides GND segments on VDD COM2 with lighted sides GND segments on VDD COM1 2 with lighted sides GND segments on VDD COM3 with lighted sides GND segments on VDD COM1 3 with lighted sides GND se
79. ed to AC data memory Rx AC R HL R HL The contents of data memory specified by HL and AC are binary Ored the result is loaded to AC and data memory specified by HL AC Ry D CF D represents an immediate data 105 tenx technology inc Rev 1 0 2003 11 13 ADCI Ry D Function Description SBCI Ry D Function Description SBCI Ry D Function Description ADDI Ry D Function Description ADDI Ry D Function Description SUBI Ry D Function Description TM8723 User s Manual The contents of Ry D and CF are binary ADDed the result is loaded to AC The carry flag CF will be affected D 0H FH AC Rx Ry D CF D represents an immediate data The contents of Ry D and CF are binary ADDed the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH lt Rx D B CF D represents an immediate data The CF and immediate data D are binary subtracted from working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH AC Rx Ry D B CF D represents an immediate data The CF and immediate data D are binary subtracted from working register Ry the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC Ry D D represents an immediate data The contents of Ry and D are binary ADDed the result is loaded to AC
80. ere erae ere aysa du qaspay 59 3 l put O tp utiPorlS u u uu usu a aaa aa DR 61 3 0 EL Panel DrIiVer u uu uu od 0o E be oan 69 SoC Extemal INT TID a o Ga GU S I I ae a uhay QA 70 3 8 Key Matrix 71 CHAPTER 4 LCD Driver Output 75 4 1 LCD driver output 75 82 CHAPTER 5 Detail Explanation of TM8723 Instructions 95 5 1 Input Output Inst GtlOFs odo Drei rst era oca cu en ed eor ere tae 95 5 2 Accumulator Manipulation Instructions and Memory Manipulation iS EPUCHOFIS acd REFERRI QC De REACHES a ay RED RES 100 5 3 Operatiom Instruetlorjs s reote cose anu eee ite Mp 101 5 4 Load Store Rcgi een Mt n 108 5 5 CRU ControlInstractionis uuu onde tds nU rentes a us a bd Mad 109 5 6 Index Address Instructions 113 5 7 Decimal Arithmetic 113 5 0 Jump INSWUCHONS u l ee eel mau D ced pu xe peo que ada 114 5 9 Miscellaneous 116 APPNDIX A 8723 Instruction Table
81. eset unless otherwise required For the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD at the off state of SW1 is used as an intermediate voltage level for LCD driver 2 1 3 EXTV POWER SUPPLY Operating voltage range 3 6V 5 4V For different LCD bias application the connection diagrams are shown below 16 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 1 3 1 NO BIAS AT EXT V BATTERY POWER SUPPLY MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V LCD BIAS 3 NO BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Application OG g 2 2 l L4 PAESE E m C c AN 8 6 d d TM8723 2 1 3 2 1 2 BIAS AT EXT V POWER SUPPLY MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V LCD BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required logic ok GN 17 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 1 3 3 1 3 BIAS AT EXT V
82. f the index register L In the same manner executed MVH instructions may load the contents of the data RAM Rx and AC into the higher nibble of the register H L is a 4 bit register and H is an 8 bit register H register H register L register Bit7 Bit Bits Bit4 Bits Bit2 Bit1 BitO Bits Bit2 Bit1 IDBF11 IDBF10 IDBF9IIDBF8 IDBF7 IDBF6 IDBF5IDBFA IDBFS3 IDBF2 IDBF 1 IDBFO The index address register can specify the full range addresses of the table ROM and data memory bit3 addressing MVH I DATA RAM bit3 Rx bit0 it TABLE ROM Rx index it HL addressing This figure shows the diagram of the index address register 2 6 STACK REGISTER STACK Stack is a special design register following the first in last out rule It is used to save the contents of the program counter sequentially during subroutine call or execution of the interrupt service routine The contents of stack register are returned sequentially to the program counter PC while executing return instructions RTS The stack register is organized using 11 bits by 8 levels but with no overflow flag hence only 8 levels of subroutine call or interrupt are allowed If the stacks are full and either interrupt occurs or subroutine call executes the first level will be overwritten 29 tenx technology inc Rev 1 0 2003
83. f the modulation output Note 1 The high frequency clock source should only be one of PH3 PH4 PH5 or FREQ the lower frequency may be any all of the combinations from PH10 PH15 2 The frequencies in corresponding to the input clock of the pre divider PHO is 32768Hz 3 The BZ and BZB pins will output DCO after the initial reset Example Buzzer output generates a waveform with 1KHz carrier and PH15 PH14 envelope LDS 20h ALM 70h Output the waveform 60 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual In this example the BZ and BZB pins will generate the waveform as shown in the following figure PH15 1HZ m L j l f 1 jJ 1 PHS 1KH2 lt emen LLLP BZ f 3 4 2 THE CARRIER FOR REMOTE CONTROL If buzzer output combines with the timer and frequency generator the output of the BZ pin may deliver the waveform for the IR remote controller For remote control usage the setting value of the frequency generator must be greater than or equal to 3 and the ALM instruction must be executed immediately after the FRQ related instructions in order to deliver the FREQ signal to the BZ pin as the carrier for IR remote controller Example SHE 2 Enable timer 1 halt release enable flag TMSX 3Fh Set value for timer 1 is 3Fh and the clock source is PHY SCC 40h Setthe clock source of the frequency generator as BCLK FRQX 2 3 FREQ B
84. gments on VDD COM2 3 with lighted sides GND segments on VDD 1 2 3 with lighted sides GND segments on VDD 1 2 3 with unlighted sides GND 88 tenx technology inc Rev 1 0 2003 11 13 iii Display Turn Off 1 2 OX in low active COM1 COM2 COM3 in high active All LED driver outputs iv STOP mode 1 2 7 7 7 sw COM3 in low active 1 2 in high active All LED driver outputs Figure 2 41 1 3duty LED Waveform 4 2 4 1 4 DUTY LIGHTING SYSTEM FOR LED DRIVER i Initial clear mode lighting COM1 2 3 4 in low active COM1 2 3 4 in high active All LED driver outputs 89 TM8723 User s Manual tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual ii Normal operation mode VDD COM1 in Low active GND VDD in Low active GND CONG in wee Low active GND VDD in Low active GND VDD COMI in high active GND VDD COM2 in high active GND CONG in VER high active GND VDD in high active M GND segments on T c VDD 1 4 with unlighted sides GND segments on VDD COM1 with lighted sides GND 90 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual segments on COM2 with lighted sides seg
85. h segment pin has 5 latches corresponding to 1 5 The segment PLA performs the function of combining DBUSA to DBUSH inputs to each latch and strobe PSTB Oh to PSTB 1Fh is selected freely by mask option Of 256 signals obtainable by combining DBUSA to DBUSH PSTB Oh to PSTB 1Fh any 175 corresponding to the number of latch circuits incorporated in the hardware signals can be selected by programming and the above mentioned segment PLA Table 2 7 shows the PSTB Oh to PSTB 1Fh signals concretely Table 2 3 Strobe Signal for LCD Latch in Segment PLA and Strobe in LCT Instruction strobe signal for Strobe in LCT LCB LCP LCD LCD latch instructions The values of Lz in LCT Lz Q fe OH ENTE _ TAN 1AH Note The values of Q are the addresses of the working register in the data memory RAM In the LCD instruction Q is the index address in the table ROM The LCD outputs could be turned off without changing the segment data Executed SF2 4h instruction could turn off the display simultaneously and executed RF2 4h could turn on the display with the patterns before turned off These two instructions will not affect the content stored in the latch circuitry When the LCD is turned off by executing RF2 4h instruction the program could still execute LCT LCB LCP and LCD instructions to update the content in the latch circuitry and the new content will be outputted to the LCD while the display is turned on again In s
86. halt mode release request signal setting the halt mode release request flag HRF3 In this case if the pre divider interrupt enable mode IEF3 is provided the interrupt is accepted and if the halt release enable mode HEF3 is provided the halt release request signal is delivered setting the start condition flag 7 SCF7 in status register 3 STS3 The clock source of pre divider is PH0 and 4 kinds of frequency of PH0 could be selected by mask option MASK OPTION table Mask Option name Selected item PH0 lt gt BCLK FOR FAST ONLY 1 PH0 BCLK PH0 lt gt BCLK FOR FAST ONLY 2 PH0 BCLK 4 PH0 lt gt BCLK FOR FAST ONLY 3 PH0 BCLK 8 4 PH0 lt gt BCLK FOR FAST ONLY 4 PH0 BCLK 16 2 2 5 SYSTEM CLOCK GENERATOR For the system clock the clock switch circuit permits the different clock input from XTOSC and CFOSC to be selected The FAST and SLOW instructions can switch the clock input of the system clock generator SGC The basic system clock is shown below SCLK T1 T2 T3 T4 Machine Cycle Instruction N Cycle 25 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 3 PROGRAM COUNTER PC This is an 11 bit counter which addresses the program memory ROM up to 1536 addresses The program cou
87. iate data 1 to data memory address 11H and AC RF 1h Reset CF to O ADD 10h Contents of the data memory address 10H and AC are binary added the result loads to AC amp data memory address 10H R10 AC Ar CF 0 DAA 10h Convert the content of AC to decimal format The result in the data memory address 10H is O and the CF is 1 This represents the decimal number 10 Instructions DAS DAS DAS HL can convert the data from hexadecimal format to decimal format after any subtraction operation The conversion rules are shown in the following table and illustrated in Example 2 AC data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution 0x AC 9 6 lt AC lt F AC A 32 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Example 2 LDS 10h 1 Load immediate data 1 to the data memory address 10H LDS 11h 2 Load immediate data 2 to the data memory address 11H AC SF 1h Set CF to 1 which means no borrowing has occurred SUB 10h Content of data memory address 10H is binary subtracted the result loads to data memory address 10H Rio AC Fu CF 0 DAS 10h Convert the content of the data memory address 10H to decimal format The result in the data memory address 10H is 9 and the CF is 0 This represents the decimal number 1 2 12 TIMER 1 TMR1 Re
88. imer The following table shows the bit pattern for this instruction Select clock Setting value The clock source option for timer 1 117 tenx technology inc Rev 1 0 2003 11 13 TMSX X Function Description SF X Function Description RF X Function Description TM8723 User s Manual Bit7 Bit6 Clock source Selects timer 1 clock source and preset timer 1 The data specified by X X7 is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Select clock Setting value The clock source option for timer 1 Sets flag Description of each flag 1 The CF is set to 1 X1 1 The chip enters backup mode and BCF is set to 1 X2 1 The EL light driver output pin is active 1 For X271 when the SF instruction is executed at X371 the EL light driver is active and the halt request signal is outputted then the chip enters halt mode X4 1 The watchdog timer is initiated and active XT 1 Enables the re load function of timer 1 X6 5 is reserved Resets flag Description of each flag 1 The CF is reset to 0 X1 1 The chip is out of backup mode and BCF is reset to 0 X2 1 The EL light driver is inactive X4 1 The watchdog timer is inactive XT 1 Disables the re load function of timer 1 X6 5 3 is reserved 118 tenx technology inc Rev 1 0 2003 11 13 SF2 X Function Des
89. indicates the operating status of the watchdog timer The MSD instruction can be used to transfer the contents of status register 4 STS4 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 4 STS4 Bit 3 Bit 2 Bit 1 Bit 0 NA NA Watchdog timer System clock Enable flag WDF selection flag CSF Read only Read only 2 13 6 START CONDITION FLAG 11 SCF11 Start condition flag 11 SCF11 will be set to 1 in STOP mode when the following conditions are met A high level signal comes from the OR ed output of the pins defined as input mode in port which causes the stop release flag of IOC port CSR to output and stop release enable flag 4 SRF4 is set beforehand 39 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual A high level signal comes from the OR ed output of the signals latch for 1 4 which causes the stop release flag of Key Scanning SKI to output and stop release enable flag 4 SRF7 is set beforehand The signal change from the INT pin causes the halt release flag 2 HRF2 to output and the stop release enable flag 5 SRF5 is set beforehand The following figure shows the organization of start condition flag 11 SCF 11 HRF2 SRF5 KI2 SKI Stop SCF11 KIS DA release request SRF7 IOC1 IOC2 CSR IOC3 IOC4 SRF4 The stop release flags SKI CSR HRF2 were specified
90. intd1 Vi GND 1 200 500 1000 Kohm Rintd2 Vi GND 2 200 500 1000 Kohm Rintd3 Vi GND 3 100 250 500 Kohm RES Pull Down R Rres1 Vi GND or 50 80 100 Kohm VDD1 1 Rres2 Vi GND or 50 80 100 Kohm VDD2 2 Rres3 Vi GND or 50 80 100 Kohm VDD2 3 DC Output Characteristics Name Symb Condition Port Min Typ Max Unit Vohic 2000 1 0 8 0 9 1 0 V Output H Voltage Voh2c loh 1mA 2 32530 3581 22 1 V Voh3c 3 SEG1 12 25 3 0 3 5 V Vollc 101 4000 1 SEG21 35 02 0 3 0 4 V Output L Voltage Vol2c lol 2mA 2 0 3 0 6 0 9 V Vol3c lol 6mA 3 0 5 10 1 5 V 9 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Segment Driver Output Characteristics Name Symb Condition For Min Typ Max Unit Static Display Mode Voh d loh 1uA 1 1 0 V Output H Voltage Voh2d loh 1uA 2 2 2 V Voh3d _ loh 1uA 3 SEG n 3 8 V Volid olz1uA 71 0 2 V Output L Voltage Vol2d lol 1uA 2 0 2 V Vol3d lolz1uA 73 0 2 V Voh e 100 1 1 0 V Output H Voltage Voh2e oh 10uA 72 2 2 V Voh3e 10
91. iption ADN Function Description AND Rx Function Description AND HL Function Description AND Rx Function Description AND TM8723 User s Manual Carry flag CF will be affected AC R HL R HL AC B 1 The content of AC is binary subtracted from content of data memory specified by HL the result is loaded to AC and data memory specified by HL Carry flag CF will be affected AC Rx AC The contents of Rx and AC are binary added the result is loaded to AC The result will not affect the carry flag CF AC R HL AC The contents of data memory specified by HL and AC are binary added the result is loaded to AC The result will not affect the carry flag CF AC Rx Rx AC The contents of Rx and AC are binary added the result is loaded to AC and data memory Rx The result will not affect the carry flag CF AC R HL R HL AC The contents of data memory specified by HL and AC are binary added the result is loaded to AC and data memory specified by HL The result will not affect the carry flag CF AC lt Rx amp AC The contents of Rx and AC are binary ANDed the result is loaded to AC AC R HL amp AC The contents of data memory specified by HL and AC are binary ANDed the result is loaded to AC AC Rx Rx amp AC The contents of Rx and are binary ANDed the result is loaded to A
92. is a multiple type oscillator mask option which provide a faster clock source to system In single clock operation fast only this oscillator will provide the clock to the system clock generator pre divider timer I O port chattering prevention clock and LCD circuitry In dual clock operation CF clock provides the clock to system clock generator only When the dual clock option is selected by mask option this oscillator will be inactive most of the time except when the FAST instruction is executed After the FAST instruction is executed the clock source BCLK of the system clock generator will be switched to CF clock and the clock source for other functions will still come from XT clock Halt mode stop mode or SLOW instruction execution will stop this oscillator and the system clock BCLK will be switched to XT clock There are 3 type oscillators can be used in slow clock oscillator selected by mask option 2 2 2 1 RC OSCILLATOR WITH EXTERNAL RESISTOR CF CLOCK This kind of oscillator could only be used in FAST only option the fast clock source of dual clock mode can t use this oscillator When this oscillator is used the frequency option of the RC oscillator with internal RC is not cared MASK OPTION table Mask Option name Selected item CLOCK SOURCE 2 FAST ONLY amp USE EXTERNAL RESISTOR MASK OPTION table Mask Option name Selected item FAST CLOCK OSC TYPE FOR FAST ONLY OR DUAL 1 or 2 don t care
93. ister contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder LCB 12 95 tenx technology inc Rev 1 0 2003 11 13 Function Description LCP Lz Ry Function Description LCD Lz HL Function Description LCT Lz HL Function Description LCB Lz HL Function Description LCP Lz HL Function Description SPA X Function Description TM8723 User s Manual LCD latch Lz data decoder Ry The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder If the content of Ry is 0 the outputs of the data decoder are all 0 LCD latch Lz Ry AC The working register contents specified by Ry and the contents of AC are loaded to the LCD latch specified by Lz LCD latch Lz T HL HL indicates an index address of table ROM The contents of table ROM specified by HL is loaded to the LCD latch specified by Lz directly LCD latch Lz data decoder R HL The contents of index RAM specified by HL is loaded to the LCD latch specified by Lz through the data decoder LCD latch Lz data decoder R HL The contents of index RAM specified by HL is loaded to the LCD latch specified by Lz through the data decoder If the content of HL is 0 the outputs of the data decoder are all 0 LCD latch Lz R HL AC The contents of index RAM specified by HL and the contents of AC are
94. itiated all of the interrupt enable flags IEFO IEF6 are cleared and should be set with the next execution of the SIE instruction Refer to Table 3 1 51 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Example Assume all interrupts are requested simultaneously when all interrupts are enabled and all of the the pins of IOC have been defined as input mode PLC 7Fh Clear all of the HRF flags SCA 10h enable the interrupt request of IOC SIE 3Fh enable all interrupt requests Lm all interrupts are requested simultaneously Interrupt caused by the predivider overflow occurs and interrupt service is concluded SIE 27h Enable the interrupt request except the predivider Interrupt caused by the 1 underflow occurs and interrupt service is concluded SIE 25h Enable the interrupt request except the predivider and TMR1 Interrupt caused by the IOC port and interrupt service is concluded SIE 24h Enable the interrupt request except the predivider TMR1 and IOC port Interrupt caused by the INT pin and interrupt service is concluded SIE 20h Enable the interrupt request except the predivider TMR1 IOC port and INT Interrupt caused by the Key matrix Scanning and interrupt service is concluded All interrupt requests have been processed 3 1 3 INTERRUPT SERVICING When an interrupt is enabled the program in execution is suspended and the instruction at the interrupt service
95. load RL1 s TMS instruction IEF1 Q Initial reset TMR1 Interrupt FREQ 6 bit binary down PH3 __ counter Set ug 5 HRF1 PH9 SCF5 PH15 HEF1 data 5 0 TMS instruction Interrupt accept signal ku PLC 2 instruction TMS instruction Initial reset This figure shows the TMR1 organization lB Halt release Reset 2 12 1 NORMAL OPERATION TMR1 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TMS or TMSX instruction Once the TMR1 counts down to 3Fh it generates an underflow signal to set the halt release request flag1 HRF1 to 1 and then stop to count down When HRF1 1 and the TMR1 interrupt enable flag IEF1 1 the interrupt is generated When HRF1 1 if the IEF1 0 and the TMR1 halt release enable HEF1 1 program will escapes from halt mode if CPU is in halt mode and then set the start condition flag 5 SCF5 to 1 in the status register 3 STS3 After power on reset the default clock source of TMR1 is PH3 If watchdog reset occurred the clock source of TMR1 will still keep the previous selection 33 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual The following table shows the definition of each bit in TMR1 instructions OPCODE Select clock Initiate value of timer TMSX X X7 X6 X5 X4 X3 X2 X1 XO TMS HL bit7 bit6 bit5
96. lt release request flag HRF 0 6 1 Ag Li version 0 EXTV version 54 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Halt release enable flags 1 HEF1 6 to 3 Interrupt enable flags Oto 3 IEF0 6 Alarm output ALARM DC 0 Pull down flags in I OC port 1 with pull down resistor Input output ports PORT I OA OC port chattering clock Cch PH10 EL panel driver pumping clock Celp PHO duty cycle is 3 4 source and duty cycle i EL panel driver clearing clock Celc PH8 duty cycle is 1 4 source and duty cycle Inactive RR RT RH output Input mode Resistor frequency converter RFC LCD driver output All lighted mask option Timer 1 Inactive Watchdog timer WDT Reset mode WDF 0 XT clock slow speed Clock source BCLK clock in dual clock option Notes PH3 the 3rd output of predivider PH10 the 10th output of predivider Mask option can unlighted all of the LCD output 3 2 3 IOC Port Key Matrix RESET Key reset function is selected by mask option When port or key matrix scanning input 1 4 is in used the 0 signal applied to all these pins that had be set as input mode in the same time KI1 4 pins need to wait scanning time reset signal is delivered MASK OPTION table IOC or KI pins are used as key reset Mask Option name Selected item IOC1 KI1 FOR KEY RESET 1 USE 2 2 FOR KEY RESET 1
97. ments on with lighted sides segments on COM4 with lighted sides segments on 1 2 with lighted sides segments on COM1 3 with lighted sides segments on COM1 4 with lighted sides segments on COM2 3 with lighted sides segments on 2 4 with lighted sides segments on COM3 4 with lighted sides segments on COM1 4 with lighted sides iii Display Turn Off tos VDD 1 1 GND VDD od ee GND GND VDD hk d Lb eee GND VDD e IE TE ESTE E GND i GND u GND a GND oe VDD UP Fo od RM GND 5 VDD GND VDD 1 234 00 00 0000 00 00 000 00000 f in I ti IN low active M OQ Q L LIIIOQBL GND VDD COM1 2 3 4 0 in high active o oOo GND VDD All LED driver outputs GND 91 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual iv Stop mode E VDD COM1 2 3 4 L LL ALLY in low active 00 7 0 0 GND VDD COM1 2 3 9h in high active o 25 GND VDD All LED driver outputs GND Figure 2 42 1 4 duty LED Waveform 4 2 5 1 5 DUTY LIGHTING SYSTEM FOR LED DRIVER i Initial clear mode lighting VDD COM1 2 3 4 5 in low active _ GND VDD COM1 2 3 4 5 e in high active GND VDD All LED driver outputs GND 92 tenx technology inc Rev 1 0 2003 11 13 ii Normal operation mode COM1 in Low
98. n Description MVL Rx Function Description H Rx AC Loads content of Rx to higher nibble of index address buffer H H7 AC3 H6 AC2 H5 AC1 H4 ACO H3 Rx3 H2 Rx2 H1 Rx1 H0 Rx0 L Rx Loads content of Rx to lower nibble of index address buffer L L3 Rx3 L2 Rx2 L1 Rx1 L0 Rx0 112 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 5 7 DECIMAL ARITHMETIC INSTRUCTIONS DAA Function AC BCD AC Description Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected DAA Rx Function AC Rx BCD AC Description Converts the content of AC to binary format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected DAA HL Function BCD AC Description Converts the content of AC to decimal format and then restores to AC and data memory specified by HL When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 lt lt 9 lt lt AC AC 6 0 lt lt 3 AC 6
99. n example and is not guaranteed to work LCD COM1 5 SEG1 12 SEG21 35 15 B XIN 1 32 768KHz 0 CUP2 S XOUT en l VDD2 VDD1 o 15 GND e e m TM8723 L 4 jJ x a M i ELP PN RESET C7 EL Plat Extemd INT ee INT ELC I O Port IOAJOB OC Choke Buzzer BZ BZB ww K1 12 1 4 Key Scaning Key Marix Ag power mode 1 3 Bias 1 5 Duty 11 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Chapter 2 TM8723 Internal System Architecture 2 1 Power Supply TM8723 could operate at Ag Li and EXTV 3 types supply voltage all of these operating types are defined by mask option The power supply circuitry also generated the necessary voltage level to drive the LCD panel with different bias Shown below are the connection diagrams for 1 2 bias 1 3 bias and no bias application 2 1 1 Ag BATTERY POWER SUPPLY Operating voltage range 1 2V 1 8V For different LCD bias application the connection diagrams are shown below 2 1 1 1 NO LCD BIAS NEED AT Ag BATTERY POWER SUPPLY Application drait g 9 z 2 NE HHHH Epa TM8723 MASK OPTION table Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY LCD BIAS 3 NO BIAS
100. nal change from Hi z to 1 TM8723 will set HRF5 to 1 If HEF5 had been set to 1 beforehand this will cause SCF7 to be set and release the HALT mode After the key scanning cycle finished the states of KI1 4 will be latched into the IOC port Executing the IPC instruction could store these states into data RAM Executing PLC 20h instruction could clear HRF5 flag Since the key matrix scanning function shared the timing of LCD LED waveform so the scanning frequency is corresponding to LCD frame frequency and LCD duty cycle The formula for key matrix scanning frequency is shown below key matrix scanning frequency Hz LCD frame frequency x LCD duty cycle x 2 Note 2 is a factor For example if the LCD frame frequency is 32Hz and duty cycle is 1 5 duty the scanning frequency for key matrix is 320Hz 32 x 5 x 2 KI1 H key scanning SKI1 input amp latch gt bitO key scanning SKI2 K2 input amp latch bit1 KSI INI SKI Data Bus key scanning SKI3 KIs input amp latch x6 gt gt key scanning SKI4 1 input amp latch key scanning enable signal IPC bit3 PLC 20h Initial Reset Interrupt 5 request This figure shows the organization of Key matrix scanning input 73 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Example
101. nerated by the halver operation is supplied to the circuits which are not related to input output operation 3 3 4 Alternating Frequency for LCD The alternating frequency for LCD is a frequency used to make the LCD waveform 3 4 BUZZER OUTPUT PINS There are two output pins BZB and BZ Each are MUXed with IOB3 and 4 by mask option respectively BZB and BZ pins are versatile output pins with complementary output polarity When buzzer output function combined with the clock source comes from the frequency generator this output function may generate melody sound effect or carrier output of remote control 59 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual MASK OPTION table Mask Option name Selected item SEG30 IOB3 BZB 3 BZB SEG31 IOB4 BZ 3 BZ MUX 05 MUX This figure shows the organization of the buzzer output 3 4 1 BASIC BUZZER OUTPUT The buzzer output BZ BZB is suitable for driving a transistor for the buzzer with one output pin or driving a buzzer with BZ and BZB pins directly It is capable of delivering a modulation output in any combination of one signal of FREQ PH3 4096Hz PH4 2048Hz PH5 1024Hz and multiple signals of PH10 32Hz PH11 16Hz PH12 8Hz 13 4 2 PH14 2Hz PH15 1Hz The ALM instruction is used to specify the combination The higher frequency clock is the carrier of modulation output and the lower frequency clock is the envelope o
102. ns with internal pull low muxed with SEG28 31 Port IOC 4 pins with internal pull low low level hold muxed with SEG32 SEG35 IOC port had built in input signal chattering prevention circuitry 8 level subroutine nesting Interrupt function External factors 3 INT pin Port IOC amp KI input Internal factors 2 Pre Divider Timer1 Built in EL panel driver ELC ELP Muxed with SEG28 SEG29 Built in Alarm clock or single tone melody generator e BZB BZ Muxed with SEG30 SEG31 3 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 10 Built in key matrix scanning function e K1 K12 Shared with SEG1 SEG12 e Kl1 Kl4 Muxed with SEG32 SEG35 11 One 6 bit programmable timer with programmable clock source 12 Watch dog timer 13 Built in Voltage doubler halver tripler charge pump circuit 14 Dual clock operation slow clock oscillation be defined as X tal or external RC type oscillator by mask option efast clock oscillation can be defined as internal R or external R type oscillator by mask option 15 HALT function 16 STOP function 1 3 BLOCK DIAGRAM B1 4 ELC ELP A1 4 Ee p 35 BZ BZB COMI 19 7 HOW s LCD DRIVER B PORT C PORT EL DRIVER KEY IN ALARM A PORT SEGMENT PLA 4 BITS DATA BUS xe X TABLE ROM ALU DATA RAM 56 12 N X 8 BITS 96 X 4 BITS
103. nstruction must be used to reset the halt release enable flag 1 HEF1 3 Start condition flag 7 SCF7 Start condition flag 7 SCF7 is set when an overflow signal from the pre divider causes the halt release request flag 3 HRF3 to be outputted and the halt release enable flag 3 HEF3 is set beforehand To reset start condition flag 7 SCF7 the PLC instruction must be used to reset the halt release request flag 3 HRF3 or the SHE instruction must be used to reset the halt release enable flag 3 HEF3 4 The 15th stage s content of the pre divider The MSC instruction is used to transfer the contents of status register 3 STS3 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3 STS3 Bit 3 Bit 2 Bit 1 Bit 0 Start condition 15th stage of the Start condition Start condition flag 7 pre divider flag 5 flag 4 SCF7 SCF5 SCF4 Halt release Halt release Halt release caused by pre caused by TMR1 caused by INT divider overflow underflow pin Read only Read only Read only Read only 2 13 4 STATUS REGISTER 3X STS3X When the halt mode is released with start condition flag 2 SCF2 status register 3X STS3X will store the status of the factor in the release of the halt mode Status register 3X STS3X consists of 3 flags 1 Start condition flag 8 SCF8 SCF8 is set to 1 when any one of KI1 4 21 0 KI1 4 1 LED mode 1 4 0 in LCD mode causes the halt
104. nter PC is normally increased by one 1 with every instruction execution PC PC 1 When executing JMP instruction subroutine call instruction CALL interrupt service routine or reset occurs the program counter PC loads the specified address corresponding to table 2 1 PC specified address shows in Table 2 1 When executing a jump instruction except JMP and CALL the program counter PC loads the specified address in the operand of instruction PC specified address in operand e Return instruction RTS PC content of stack specified by the stack pointer Stack pointer stack pointer 1 Table 2 1 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO 1 0 0 0 0 INT pin amono 2 EAE input port C mer timer 1 interrupt BED Up Interrupt 5 Key Scanning interrupt Jump instruction P10 Subroutine call P10 to PO Low order 11 bits of instruction operand ETEA Interrupt 3 pre divider interrupt P9 P8 P9 P8 When executing the subroutine call instruction or interrupt service routine the contents of the program counter PC are automatically saved to the stack register STACK 26 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 4 PROGRAWTABLE MEMORY The built in mask ROM is organized with 1536 x 16 bits 16 bits 000h SFFh Both instruction ROM PR
105. o output the data to the output latches This will prevent the chattering signal on the pin when the mode changed IOB port had built in pull down resistor by mask option and executing SPB instruction to enable disable this device 65 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual MASK OPTION table Mask Option name Selected item IOB PULL LOW RESISTOR 1 USE IOB PULL LOW RESISTOR 2 NO USE 3 5 3 IOC PORT IOC1 IOC4 pins MUXed with KI1 SEG32 KI2 SEG33 SEG34 and KIA SEG35 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG32 IOC1 KI1 2 IOC1 SEG33 IOC2 KI2 2 IOC2 SEG34 IOC3 KI3 2 IOC3 SEG35 IOCA KIA 2 IOC4 After the reset cycle the IOC port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPC instruction Executed OPC instruction may output the content of specified data memory to the pins defined as output the other pins which are defined as the input will still remain the input mode Executed IPC instructions may store the signals applied to the IOC pins in the specified data memory When the IOC pins are defined as the output executing IPC instruction will save the data stored in the output latches in the specified data memory Before executing SPC instruction to define the IOC pins as output the OPC instruction
106. on 1 BITO and BIT1 of the port deliver RAM data 2 BIT2 of the port delivers the constant value of the OPAS 3 BIT3 of the port delivers pulses Shown below is a sample program using the OPAS instruction 1 LDS OAH 0 2 OAH SPA LDS 1 5 3 5 1 1 Bit 0 output shift gate open 4 SRO 1 Shifts bit 1 to bit 0 5 5 1 1 Bit 1 output 6 SRO 1 Shifts bit2 to bit 0 63 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 7 OPAS1 1 Bit 2 output g SRO 1 Shifts bit 3 to bit 0 9 OPAS1 1 Bit3 output 10 1 1 Lastdata 11 OPAS1 0 Shiftgate closes The timing chart below illustrates the above program 1 2 3 4 5 6 7 8 9 10 11 0 5 2 1 IOA1 for Rx 5 Bit1 for Rx 5 Bit2 for Rx 5 Bit3 for 5 M M gt gt lt t BCLK 2 If IOA1 is used as the CX pin for function and the other pins IOA2 IOA3 are used for normal IO pins 1 pin must always be defined as the output mode to avoid the influence from the CX when the input chattering prevention function is active On the other hand the counter can receive the signal changes on 1 when the counter is enabled 3 5 2 IOB PORT IOB1 IOB4 pins are MUXed with ELC SEG28 ELP SEG29 BZB SEG30 BZ SEG31 pins respectively by mask option MASK OPTION table Mask Option name Selecte
107. on is selected connected a capacitor between VDD and GND is necessary 3 2 2 RESET PIN RESET When H level is applied to the reset pin the reset signal will issue Built in a pull down resistor on this pin Two types of reset method for RESET pin and the type could be mask option the one is level reset and other is pulse reset It is recommended to connect a capacitor 0 1uf between RESET pin and VDD This connection will prevent the bounce signal on RESET pin 3 2 2 1 Level Reset Once a 1 signal applied on the RESET pin TM8723 will not release the reset cycle until the signal on RESET pin returned to 0 After the signal on reset pin is cleared to 0 8723 begins the internal reset cycle and then release the reset status automatically MASK OPTION table Mask Option name Selected item RESET PIN TYPE 1 LEVEL 3 2 2 2 Pulse Reset Once a 1 signal applied on the RESET pin TM8723 will escape from reset state and begin the normal operation after internal reset cycle automatically no matter what the signal on RESET pin returned to 0 or not MASK OPTION table Mask Option name Selected item RESET PIN TYPE 2 PULSE The following table shows the initial condition of TM8723 in reset cycle Program counter PC Address 000H Start condition flags 1 to 7 SCF 1 7 Backup flag BCF Stop release enable flags SRF3 4 5 7 4 5 7 Switch enable flags 4 SEF3 4 Ha
108. orts operate between GND and VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 2 1 2 LI BATTERY POWER SUPPLY Operating voltage range 2 4V 3 6V For different LCD bias application the connection diagrams are shown below 2 1 2 1 NO BIAS AT LI BATTERY POWER SUPPLY Application loal H HHHH Bia il CN rd N Q Q Q a a amp 8 SN TM8723 MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER LCD BIAS 3 NO BIAS Note 1 The input output ports operate between GND and VDD2 14 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 1 2 2 1 2 BIAS AT LI BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin BAK logic GND MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER LCD BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear
109. r s Manual The 16 specified addresses 70H to 7FH in the direct addressing memory are also used as 16 working registers The function of working register will be described in detail in section 2 6 00H 89 DATA 8 lt o 58 58 a H Working Register 4 Bits gt This figure shows the Data Memory RAM Working Register Organization 2 8 WORKING REGISTER WR The locations 70H to 7FH of the data memory RAM are not only used as general purpose data memory but also as the working register WR The following will introduce the general usage of working registers 1 Be used to perform operations on the contents of the working register and immediate data Such as ADCI ADCI SBCI SBCI ADDI ADDI SUBI SUBI ADNI ADNI ANDI ANDI EORI EORI ORI ORI 2 Be transferred the data between the working register and any address in the direct addressing data memory RAM Such as MWR Rx Ry MRW Ry Rx 3 Decode or directly transfer the contents of the working register and output to the LCD PLA circuit Such as LCT LCB LCP 2 9 ACCUMULATOR AC The accumulator AC is a register that plays the most important role in operations and controls By using it in conjunction with the ALU Arithmetic and Logic Unit data transfer between the accumulator and other registers or data memory can be performed 2 10 ALU Arithmetic and Logic Unit This is a ci
110. rcuitry that performs arithmetic and logic operation The ALU provides the following functions Binary addition subtraction INC DEC ADC SBC ADD SUB ADN ADCI SBUI ADNI Logic operation AND EOR OR ANDI EORI ORI Shift SRO SR1 SLO SL 1 31 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Decision JB0 JB1 JB2 JB3 JC JNC JZ and JNZ BCD operation DAA DAS 2 11 HEXADECIMAL CONVERT TO DECIMAL HCD Decimal format is another number format for TM8723 When the content of the data memory has been assigned as decimal format it is necessary to convert the results to decimal format after the execution of ALU instructions When the decimal converting operation is processing all of the operand data including the contents of the data memory RAM accumulator AC immediate data and look up table should be in the decimal format or the results of conversion will be incorrect Instructions DAA DAA DAA HL can convert the data from hexadecimal to decimal format after any addition operation The conversion rules are shown in the following table and illustrated in example 1 AC data before CF data before AC data after CF data after DAA execution execution execution execution 0 lt AC lt 9 CF 0 no change no change lt lt 6 0 lt lt 3 AC 6 Example 1 LDS 10h 9 Load immediate data 9 to data memory address 10H LDS 11h 1 Load immed
111. release request flag 5 HRF5 to be outputted and the halt release enable flag 5 HEF5 is set beforehand To reset the start condition flag 8 SCF8 the PLC instruction must be used to reset the halt release request flag 5 HRF5 or the SHE instruction must be used to reset the halt release enable flag 5 HEF5 38 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual The MCX instruction can be used to transfer the contents of status register 3X STS3X to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3X STS3X Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag 8 SCF8 Halt release caused by SKI underflow Read only 2 13 5 STATUS REGISTER 4 STS4 Status register 4 STS4 consists of 3 flags 1 System clock selection flag CSF The system clock selection flag CSF indicates which clock source of the system clock generator SCG is used Executing SLOW instruction will change the clock source BCLK of the system clock generator SCG to the slow speed oscillator XT clock and the system clock selection flag CSF is reset to 0 Executing FAST instruction will change the clock source BCLK of the system clock generator SCG to the fast speed oscillator CF clock and the system clock selection flag CSF is set to 1 For the operation of the system clock generator refer to 3 3 2 Watchdog timer enable flag WTEF The watchdog timer enable flag WDF
112. request An interrupt request signal HRFO is delivered when the input signal changes at I O port specified by the SCA instruction In this case if the interrupt enabled by flag 0 IEFO is set to 1 interrupt O is accepted and the instruction at address 14H is executed automatically 3 Key matrix Scanning interrupt request An interrupt request signal HRF5 is delivered when the input signal generated in scanning interval If the interrupt enable flag 5 IEF5 is set to 1 and interrupt 5 is accepted the instruction at address 24H will be executed automatically 3 1 1 2 Internal interrupt factor The internal interrupt factor involves the use of timer 1 TMR1 and the pre divider 1 Timer1 TMR1 interrupt request An interrupt request signal HRF1 is delivered when timer1 TMR1 underflows In this case if the interrupt enable flag 1 IEF1 is set interrupt 1 is accepted and the instruction at address 18H is executed automatically 2 Pre divider interrupt request An interrupt request signal HRF3 is delivered when the pre divider overflows In this case if the interrupt enable flag3 IEF3 is set interrupt 3 is accepted and the instruction at address 1CH is executed automatically 3 1 2 INTERRUPT PRIORITY If all interrupts are requested simultaneously during a state when all interrupts are enabled the pre divider interrupt is given the first priority and other interrupts are held When the interrupt service routine is in
113. reset to 0 3 The MAF instruction can be used to transfer data in status register 1 STS1 to the accumulator AC and the data memory RAM 4 The MRA instruction can be used to transfer data of the data memory RAM to the status register 1 STS1 The bit pattern of status register 1 STS1 is shown below Bit 3 Bit 2 Bit 1 Bit 0 Carry flag AC Zero flag Z NA NA Read write Read only Read only Read only 2 13 2 STATUS REGISTER 2 STS2 Status register 2 STS2 consists of start condition flag 1 2 SCF1 SCF2 and the backup flag The MSB instruction can be used to transfer data of status register 2 STS2 to the accumulator AC and the data memory RAM but it is impossible to transfer data of the data memory RAM to status register 2 STS2 The following table shows the bit pattern of each flag in status register 2 STS2 Bit 3 Bit 2 Bit 1 Bit 0 NA Start condition Start condition Backup flag flag 2 flag 1 BCF SCF2 SCF1 NA Halt release Halt release The back up caused by caused by the mode status SCF4 5 7 8 IOC port Start condition flag 1 SCF1 When the SCA instruction specified signal change occurs at port IOC to release the halt mode SCF1 will be set Executing the SCA instruction will cause SCF1 to be reset to 0 Start condition flag 2 SCF2 When a factor other than port IOC causes the halt mode to be released SCF2 will be set to1 In this case if one or more start condition flags SCF4 5 7
114. rogram 41 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual If the interrupt 0 is accepted by SEF4 and IEF0 the interrupt 0 request to the next signal change at IOC will be inhibited To release this mode SCA instruction must be executed again Refer to 2 16 1 1 2 14 2 CONTROL REGISTER 2 CTL2 Control register 2 CTL2 consists of halt release enable flags 1 2 3 5 HEF1 2 3 5 and is set by SHE instruction The bit pattern of the control register CTL2 is shown below Halt release enable flag Enable the halt Halt release release caused by condition Key Scanning HRF5 F MEFS HEB enable flag Enable the halt Enable the halt Enable the halt Halt release release caused by release caused by release caused by condition pre divider overflow HRF2 TM1 underflow HRF3 HRF1 When the halt release enable flag 1 HEF1 is set an underflow signal from TMR1 causes the halt mode to be released In the same manner the following conditions will cause the halt mode to be released respectively when HEF2 3 5 are set to 1 the signal change at the INT pin an overflow signal from the pre divider and a H signal from OR ed output of KI1 4 latch signals When the stop release enable flag 5 SRF5 and the HEF2 are set the signal change at the INT pin can cause the stop mode to be released When the stop release enable flag 7 and the HEF5 are set the H signal from
115. ruction Machine Code Function Flag Remark NOP 0000 0000 0000 0000 No Operation LCT Lz Ry 0000 001Z ZZZZ YYYY 2 lt 7SEG Ry LCB Lz Ry 0000 0107 ZZZZ YYYY 2 7SEG Ry Blank Zero LCP Lz Ry 0000 0112 ZZZZ YYYY __ Lz Ry AC LCD Lz HL 0000 100Z ZZZZ 0000 Lz R HL LCT Lz HL 0000 100Z ZZZZ 0001 Lz lt 7SEG R HL LCB Lz HL 0000 100Z ZZZZ 0010 Lz lt 7SEG RQHL Blank Zero LCP Lz HL 0000 100Z ZZZZ 0011 Lz RQHL OPA Rx 0000 1010 XXXX IOA lt Rx OPAS Rx D 0000 1011 XXXX IOA1 2 3 4 lt Rx 0 Rx 1 D Pulse OPB Rx 0000 1100 XXXX lt Rx OPC Rx 0000 1101 XXXX lt Rx FRQ D Rx 0001 00DD XXXX FREQ D 00 1 4 Duty D 01 1 3 Duty D 10 1 2 Duty D 11 1 1 Duty FRQ D HL 0001 01DD 0000 0000 FREQ lt T HL FRQX D X 0001 10DD XXXX XXXX FREQ X MVL Rx 0001 1100 XXXX Ql lt Rx MVH Rx 0001 1101 XXXX QH lt Rx AC ADC Rx 0010 0000 OXXX XXXX AC lt Rx AC CF CF ADC HL 0010 0000 1000 0000 AC R HL AC CF CF ADC Rx 0010 0001 OXXX XXXX lt Rx AC CF CF ADC HL 0010 0001 1000 0000 AC R HL R HL AC CF CF SBC Rx 0010 0010 OXXX XXXX lt Rx AC B CF CF SBC HL 0010 0010 1000 0000 AC lt R HL AC B CF CF SBC Rx 0010 0011 XXXX lt Rx AC B CF CF SBC HL 0010 0011 1000 0000
116. ry could generate output voltage up to AC 150V or above for driving the EL plant the ELC and ELP output is MUXed with IOB1 SEG28 and IOB2 SEG29 and is selected by mask option MASK OPTION table Mask Option name Selected item SEG28 IOB1 ELC 3 ELC SEG29 IOB2 ELP 3 ELP The ELP pin will output clocks to pump voltage to the EL plant the ELC pin will output the pulse to discharge the EL plant The EL plant driver will not operate until the light control signal LIT is enabled Once the light control signal LIT is enabled the ELC pin will output a pulse to discharge the capacitor before the pumping clocks output to ELP pin This will insure that there is no residual voltage that may cause damage while the first pumping clock is applied When the light control signal LIT is disabled the ELC pin will output a pulse to discharge the EL plant after the last pumping clock This figure shows the application circuit of EL plant EL plant LIT ne fee ELP ELC This figure shows the output waveform of EL plant driver 69 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual The ELP ELC pulse frequency and duty cycle could be defined by executing ELC instruction When ELC pin outputs the discharge pulse the clock on ELP pin will be inhibited For ELP setting Pumping clock X8 X7 X6 X5 X4 Duty cycle 00 Pho 00 3 4duty 2 3 duty BCLK 2 1 2 duty BCLK 4 1 1 duty BCL
117. s power on reset RESET pin reset IOC port reset and watchdog timer reset When reset signal is accepted TM8723 will generate a time period for internal reset cycle and there are two types of internal reset cycle time could be selected by mask option the one is PH15 2 and the other is PH12 2 idi IHH Jugduuluu du dul CJ UU UU UU UL Hold 16384 clocks for pla Normal operation gt internal reset cycle Internal reset cycle time is PH15 2 MASK OPTION table Mask Option name Selected item RESET TIME 1 PH15 2 In this option the reset cycle time will be extended 16384 clocks clock source comes form pre divider long at least Internal reset cycle time is PH12 2 MASK OPTION table Mask Option name Selected item RESET TIME 2 PH12 2 In this option the reset cycle time will be extended 2048 clocks clock source comes form pre divider long at least 53 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 3 2 1 POWER ON RESET TM8723 provides a power on reset function If the power VDD is turned on or power supply drops below 0 6V it will generate a power on reset signal Power on reset function can be disabled by mask option MASK OPTION table Mask Option name Selected item POWER ON RESET 1 USE POWER ON RESET 2 NO USE Note When the power on reset opti
118. se some LED driver output pins for DC output ports and the remaining LED driver output pins for LED driver outputs In the LCD configuration file cfg with the O data listed in the COM column the segment pin will be defined as the CMOS type output port When the 9 data is listed in the COM column the segment pin will be defined as the P open drain type output port SEG1 SEG12 SEG21 SEG35 of LED driver outputs can be selected as CMOS type or P open drain type output by mask option When the LED driver output pin SEG has been defined as the DC output port the output data will not be affected when the STOP mode or LED turn off mode is active During reset mode all of LED s outputs will be unlighted by default setting as this setting may prevent large power consumption during the initial clear cycle All of the LED output data will keep the initial setting until the LED related instructions are executed in the program The output waveform of the common output and LED driver output for each LED lighting system are shown below 4 2 1 STATIC LIGHTING SYSTEM FOR LED DRIVER i Initial clear mode e VDD OM in LJ b Q low active aes GND VDD COMTin J c I LIL ZJ UU C 0 0000s high active 0 0 o oOo GND VDD All LED driver outputs GND 84 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual ii Normal operation mode Uc VDD COM1 in low active EE GND pues VDD COM1 in high a
119. se the underflow counter clear HRF 1 iif the TMR1 underflow counter is equal to 8 exit disable the re load function 35 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 2 13 STATUS REGISTER STS The status register STS is organized with 4 bits and comes in 4 types status register 1 STS1 to status register 4 STS4 The following figure shows the configuration of the start IEF0 d PLCO SIE Tib a prevention UN SCF1 PLC 1h BES J TE Initial reset Interrupt accept 3 Halt release request Timer1 underflow HRF1 X SCF5 Interrupt 1 HEF1 SHE 2h SEF4 SCA 10h IEF2 Signal SIE 4h Interrupt 2 changed HRF 2 on INT pin N SCF 4 HEF 2 SHE 4h ES HRF3 SIE ab Interrupt 3 Predivid D N uou HEF 3 IPC e SHE 8h IEF5 SIE 20h Interrupt 5 Key Scanning HRF5 overflow WEE N SCF8 SHE 20h 2 condition flags for TM8723 2 13 1 STATUS REGISTER 1 STS1 Status register 1 STS1 consists of 2 flags 1 Carry flag CF The carry flag is used to save the result of the carry or borrow during the arithmetic operation 2 Zero flag Z Indicates the accumulator AC status When the content of the accumulator is 0 the Zero flag is set to 1 36 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual If the content of the accumulator is not 0 the zero flag is
120. terrupt 0 request SEF4 SCA 10h PLC 1 Interrupt accept 2 14 1 1 The Setting for Halt Mode If the SEF4 is set to 1 the signal changed on IOC port will cause the halt mode to be released and set SCF1 to 1 Because the input signal of IOC port were ORed so it is necessary to keep the unchanged input signals at 0 state and only one of the input signal could change state 2 14 1 2 The Setting for Stop Mode If SRF4 and SEF4 are set the stop mode will be released to set the SCF1 when a high level signal is applied to one of the input mode pins of IOC port and the other pins stay in 0 state After the stop mode is released TM8723 enters the halt condition The high level signal must hold for a while to cause the chattering prevention circuitry of IOC port to detect this signal and then set SCF 1 to release the halt mode or the chip will return to the stop mode again 2 14 1 3 Interrupt for CTL1 The control register 1 CTL 1 performs the following function in the execution of the SIE instruction to enable the interrupt function The input signal changes at the input pins in IOC port will deliver the SCF1 when SEF4 has been set to 1 by executing SCA instruction Once the SCF1 is delivered the halt release request flag HRFO will be set to 1 In this case if the interrupt enable flag 0 IEFO is set to 1 by executing SIE instruction the interrupt request flag O interrupt O will be delivered to interrupt the p
121. the stop instruction is executed the following operations must be completed Specify the stop release conditions by the SRE instruction Specify the halt release conditions corresponding to the stop release conditions if needed Specify the interrupt conditions corresponding to the stop release conditions if needed HALT released decision When the stop mode is released by an interrupt request the TM8723 will enter the halt mode immediately While the interrupt is accepted the halt mode will be released by the interrupt request The stop mode returns by executing the RTS instruction after completion of interrupt service After the stop release it is necessary that the MSB MSC or MCX instruction be executed to test the halt release signal and that the PLC instruction then be executed to reset the halt release signal Even when the stop instruction is executed in the state where the stop release signal SRF is delivered the CPU does not enter the stop mode but the halt mode When the stop mode is released and an interrupt is accepted the halt release signal HRF is reset automatically 2 18 BACK UP FUNCTION TM8723 provide a back up mode to avoid system malfunction when heavy loading occurred such as buzzer is active LED is lighting etc Since the heavy loading will cause a large voltage drop on the supply voltage and the system will be malfunction in this condition 46 tenx technology inc Rev 1 0 2003 11 13
122. ting frequency LCD frame frequency 1 SLOW 25Hz LCD frame frequency 2 TYPICAL 51Hz LCD frame frequency 2 FAST 102Hz LCD frame frequency 2 OHz LCD not used The following table shows the relationship between the LCD lighting system and the maximum number of driving LCD segments System Driving LCD Segments 13 bias 1 3 duty 856 1 3 bias 1 4 duty 18 Q 3bias 1 5 duy 15 j When choosing the LCD frame frequency it is recommended to choice the frequency that higher than 24Hz If the frame frequency is lower than 24Hz the pattern on the LCD panel will start to flash 76 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 4 1 2 DC OUTPUT TM8723 permits LCD driver output pins SEG1 SEG27 to be defined as CMOS type DC output or P open drain DC output ports by mask option In this case it is possible to use some LCD driver output pins for DC output and the rest LCD driver output pins for LCD driver Refer to 4 3 4 The configurations of CMOS output type and P open drain type are shown below When the LCD driver output pins SEG are defined as DC output the output data on this port will not be affected while the program entered stop mode or LCD turn off mode VDD SEG Figure 5 1 CMOS Output Type Figure 5 2 P Open Drain Output Type 4 1 3 SEGMENT PLA CIRCUIT FOR LCD DISPLAY 4 1 3 1 PRINCIPLE OF OPERATION OF LCD DRIVER SECTION Explained below is how the LCD driver
123. tion in the following table The bit pattern of X for higher frequency clock source 79 90 1 0 1 1 34KHz L0 1 o eKH x O O 1 aki O o 0 The bit pattern of X for lower frequency clock source clock source lower frequency 15 1Hz 14 2Hz 13 4Hz 12 8Hz 11 16Hz 10 32Hz Notes 1 FREQ is the output of frequency generator 2 When the buzzer output does not need the envelope waveform X5 X0 should be set to 0 3 The frequency inside the bases on the 00 is 32768Hz ELC X Function The bit control of EL light driver Description The meaning of each bit specified by X X8 X0 is shown below For ELP pin setting X8 X7 X6 Pumping clock X5 X4 Duty cycle frequency 00 40 BCLK 2 1 2 duty BCLK 4 1 1 duty original BCLKB For ELC pin setting 99 tenx technology inc Rev 1 0 2003 11 13 X3 X2 Discharge pulse X1 X0 frequency TM8723 User s Manual Duty cycle O 00 f duy 7 1 3 01 _ 196 10 J 1l2qty ff 45 1 1 duty original 5 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY MANIPULATION INSTRUCTIONS MRW Ry Rx Function Description MRW Rx Function Description MWR Rx Ry Function Description MWR Rx Function Description SRO Rx Function Description SR1 Rx Function Description SLO R
124. top state all COM and SEG outputs of LCD driver will automatically switch to the GND state to avoid the DC voltage bias on the LCD panel 79 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 4 1 3 2 Relative Instructions 1 LCT Lz Ry Decodes the content specified Ry with the data decoder and transfers the DBUSA H to LCD latch specified by Lz 2 LCB Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to LCD latch specified by Lz The DBUSA to DBUSH are all 0 when the input data of the data decoder is O 3 LCD Lz HL Transfers the table ROM data specified by HL directly to DBUSA to DBUSH without passing through the data decoder The mapping table is shown in table 2 32 4 LCP Lz Ry The data of the RAM and accumulator AC are transferred directly to DBUSA to DBUSH without passing through the data decoder The mapping table is shown below 5 LCT Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to LCD latch specified by Lz 6 LCB Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to LCD latch specified by Lz The DBUSA to DBUSH are all 0 when the input data of the data decoder is 0 7 LCP Lz HL The data of the index RAM and accumulator AC are transferred directly to DBUSA to DBUSH without passing through the data decoder
125. ty LED Waveform 94 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual Chapter 5 Detail Explanation of TM8723 Instructions Before using the data memory it is necessary to initiate the content of data memory because the initial value is unknown The working registers are part of the data memory RAM and the relationship between them can be shown as follows The absolute address of working register Rx Ry 70H Note Ry Address of working register the range of addresses specified by Rx is from 00H to 7FH Rx Address of data memory the range of addresses specified by Ry is from OH to FH Address of working registers specified by Ry Absolute address of data memory Rx e HL is an 8 bit index address buffer This buffer may address all data memory and table ROM The contents of the index address buffer may be specified by two instructions MVH and MVL MVH transfers the contents of data memory Rx to the higher nibble 4 bits and MVL to the lower nibble 4 bits O N O The organization of the index address buffer HL is shown below Index Address Buffer Higher nibble H Lower nibble L H7 0 L3 LO Transferred by MVH Transferred by MVL Lz represents the address of the latch of LCD PLA the address range specified by Lz is from 00H to 1FH 5 1 INPUT OUTPUT INSTRUCTIONS LCT 12 Function LCD latch Lz data decoder Ry Description The working reg
126. urns by executing the RTS instruction after completion of interrupt service Enters stop mode and stops all oscillators Before executing this instruction all signals on IOC port must be set to low The following 3 conditions cause the stop mode to be released 1 One of the signal on KI1 4 is H L LED LCD in scanning interval 2 A signal change in the INT pin 3 One of the signals on IOC port is H 109 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual SCA X Function The data specified by X causes the halt mode to be released Description The signal change at ports IOA IOC is specified The bit meaning of X X4 is shown below Bit pattern Description Halt mode is released when signal applied to IOC 7 5 3 0 is reserved SIE X Function Set Reset interrupt enable flag Description The IEF0 is set so that interrupt 0 Signal change at port IOC specified by SCA is accepted X1 1 The IEF1 is set so that interrupt 1 underflow from timer 1 is accepted 2 1 IEF2 is set so that interrupt 2 the signal change at the INT is accepted X3 1 The IEF3 is set so that interrupt 3 overflow from the predivider is accepted X5 1 The IEF5 is set so that interrupt 5 key scanning is accepted X7 6 4 is reserved SHE X Function Set Reset halt release enables flag Description The HEF 1 is set so that the halt mode is released by TMR1 underflow INT pin X3 1
127. ut state in scanning interval is set by 7 0 Bit Patten Setting Halt Release by X670 Normal Key Scanning Scanning Cycle The bit pattern of X for Key Matrix scanning output to SEG1 12 K1 K10 K11 K1 1 Hi z aie Hip 1 Hie HrzIHee Hz Hz Hiz i z Hi z Hi Hiz 1 Hiz Hz Hiz Hoz Hi Hi z lt Hz Hiz H z 1 Hiz Hiz Hz Hiz Hz Hz Hoz Hiz Hiz Hiz Hiz 1 HezHrz ea Hiz Hiz Hr Hiz U Hz HE HE Hz 1 Hcr Hi IH Hr iil ra GE 1 1 Ez Hz Hz e Hz Rez Rz Rz c c Rez Re He 1 RE LELE LT Dr Lr paper Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 1 1 1 1 HezHc ez HezIHez Hz H eld ez B H z Hi z Hiz Hi z Hiz Hez ez Hiz 1 1 1 Hi z a Az a 1 KNEES 2 2 1 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 98 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual X Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi Z 1 LT T L L be X Bz a ea He Hor He Notes 1 1 H L LED LCD 2 1 12 SEG1 12 output in scanning interval ALM X Function Sets buzzer output frequency Description The waveform specified by X X8 X0 is delivered to the BZ and BZB pins The output frequency could be any combina
128. vel reset or Pulse reset by mask option Input pin for external interrupt request signal Falling edge or rising edge triggered is defined by mask option Internal pull down or pull up resistor is defined by mask option Switching pins for supply the LCD driving voltage to the VDD1 2 3 pins Connect the CUP1 and CUP2 pins with non polarized electrolytic capacitor when chip operated in 1 2 or 1 3 bias mode Inno BIAS mode application leave these pins opened Time base counter frequency clock specified LCD alternating frequency Alarm signal frequency or system clock oscillation 32KHz Crystal oscillator In FAST ONLY mode option connect an external resistor could compose a RC oscillator COM1 5 O Output pins for driving the common pins of the LCD or LED panel SEG1 12 Output pins for driving the LCD or LED panel segment SEG21 35 ELC ELP O Output port for EL driver O BZB BZ O Output port for alarm clock or single tone melody generator IK1 12 Output port for key matrix scanning Shared with SEG1 SEG12 4 1 Input port for key matrix GND Negative supply voltage j 6 tenx technology inc Rev 1 0 2003 11 13 TM8723 User s Manual 1 7 CHARACTERISTICS ABSOLOUTE MAXIMUM RATINGS GND 0V Name Symbol Range Unit VDD1 0 3 to 5 5 V Maximum Supply Voltage V
129. x Function AC Rx Rx The content of Rx is loaded to AC and the working register specified by Ry AC R HL Rx The content of data memory specified by Rx is loaded to AC and data memory specified by HL AC Rx Ry The content of working register specified by Ry is loaded to AC and data memory specified by Rx AC Rx RQHL The content of data memory specified by HL is loaded to AC and data memory specified by Rx Rxn Rx n 1 AC n 1 Rx3 AC3 0 The Rx content is shifted right and 0 is loaded to the MSB The result is loaded to the AC 0 gt Rx3 gt Rx2 5 Rx1 gt Rx0 gt Rxn ACn Rx n 1 AC n 1 Rx3 AC3 1 The Rx content is shifted right and 1 is loaded to the MSB The result is loaded to the AC 1 Rx3 gt Rx2 gt Rx1 gt Rx0 gt Rxn ACn Rx n 1 AC n 1 100 tenx technology inc Rev 1 0 2003 11 13 Description SL1 Rx Function Description MRA Rx Function Description MAF Rx Function Description TM8723 User s Manual Rx0 AC0 0 The Rx content is shifted left and 0 is loaded to the LSB The results are loaded to the AC lt Rx3 lt Rx2 lt Rx1 Rx0 lt 0 Rxn ACn Rx n 1 AC n 1 Rx0 ACO 1 The Rx content is shifted left and 1 is loaded to the LSB The results are loaded to the AC lt Rx3 lt Rx2 lt Rx1 Rx0 lt 1 CF Rx 3 Bit3 of the content of Rx is loaded to carry flag
130. y the mode status in IOC port TM8723 MSC Rx Function Description Bit 3 AC Rx SCF4 7 The SCF4 to SCF7 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 2 Bit 1 Bit 0 Start condition flag The content of 15th Start condition flag Start condition flag 7 stage of the 5 4 SCF7 predivider SCF5 SCF4 Halt release Halt release Halt release caused by caused by TM1 caused by INT pin predivider overflow underflow MCX Rx Function AC Rx SCF8 111 tenx technology inc Rev 1 0 2003 11 13 Description TM8723 User s Manual The SCF8 content is loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as MSD Rx Function Description follows Bit 2 Bit 1 Bit 0 Start condition flag 8 SCF8 Halt release caused by the signal change to H PL LED LCD 1 4 in scanning interval Rx AC WDF CSF RFOVF The watchdog flag system clock status and overflow flag of RFC counter are loaded to data memory specified by Rx and AC The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit2 Bit 1 Bit 0 Reserved Reserved Watchdog timer System clock enable flag WDF selection flag CSF 5 6 INDEX ADDRESS INSTRUCTIONS MVH Rx Functio

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