NAMC-ECAT_manual
Contents
1. Technical Reference Manual FPGA Version R pister casais nn ee Res ra RR tt ee FPGA ID 1 Register es FPGA ID 2 Register FPGA BOARD ID Register FPGA Reset Register AS SPI interface register to FPGA PROM riiin Ne ann a SPI miterfac register to A a a e eae aE A R EEn EEAS AA AE EEA SNA aA eN ERA A RS ESC Register rr an nn a A A EEN 6 KNOWN BUGS RESTRICTIONS ssmsemenenennennnnnnnnnnnennnnennennensnenesenennensenenneeenenses 31 APPENDIX A REFERENCE DOCUMENTATION sese sees sees sees reeeo reroror 32 APPENDIX B DOCUMENTS HISTORY cssssssssssssssessssessessssessersesessessesessesseseesessesessessesesessesessesseseseens 33 Version 1 0 NAT GmbH 5 NAMC ECAT Technical Reference Manual List of Tables Tablet bisto used abbreviati Gis misina naan aana aa 7 Table2 NAME EC ALT ES Sii il 11 Table AMC Port Definition iii i 20 Table ls LED Functional pd dt 21 Lable 22 AME Conector JL assa seda ln 23 Table 1 Amel Programming POR sss sese 0 v a 25 Table 1 Lattice programming Portada nas osv 25 Table 2 Pin Assignment of the Front panel Connectors S1 Ethernet 26 Table 3 Pin Assignment of the Front panel Connectors S2 Ethernet 26 Table 4 Pin Assignment of the Front panel Connectors S3 Ethernet 27 Table 1 FPGA Memory Maps nina inerte 28 Tablet PEB Version Register ES TA 4884 88 84 282. 20 unassigned Version 1 0 N A T GmbH 20 NAMC ECAT Technical Reference Manual 3 8 Front Panel and LEDs The NAMC ECAT module is eguipped with 4 or 6 LEDs depending on the number of available ports on the NAMC ECAT They are integrated in the RJ45 interface jacks Additionally the module contains the standard AMC LEDs and a status indicator LED for the EtherCAT bus Figure 7 Front Panel 3 Port X3 Out Figure 8 Front Panel 2 Port The function of the LEDs is described in the following table Table 1 LED Functionality LED Function RUN Status of the EtherCAT State Machine ERR AMC Error LED HS AMC Hotswap LED 1 Link Activity LED on port 1 2 port receive error LED on port 1 3 Link Activity LED on port 2 4 port receive error LED on port 2 5 Link Activity LED on port 2 6 port receive error LED on port 2 Version 1 0 N A T GmbH 21 NAMC ECAT Technical Reference Manual 4 Connectors 4 1 Connector Overview Figure 9 Connectors of the NAMC ECAT Top View Please refer to the following tables to look up the connector pin assignment of the NAMC ECAT Version 1 0 N A T GmbH 22 NAMC ECAT Technical Reference Manual 4 2 AMC Connector J1 Table 2 AMC Connector J1 RD AMC Signal 3 168 4 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 14
3. 3 3 PCI Express Interface The NAMC ECAT includes a 1 lane PCI Express interface This is implemented in a PEX8112 PCI to PCIe bridge PLX The PCIe bridge may receive its reference clock either from the Clock 3 port of the AMC backplane connector or from a local 100 MHz oscillator circuitry default The clock source is programmable 3 4 AMC Clock Interface AMC backplane clock port Clock 1 is connected to the FPGA in order to be used as a Telecom standard clock Clock 1 is only received AMC backplane clock port Clock 2 is connected to the FPGA in order to be used as a Telecom standard reference Clock 2 may be received from or transmitted to the backplane in order to become the reference clock for the entire system AMC backplane clock port Clock 3 is connected to the PCI gt PCIe bridge in order to be used as a reference clock for PCI Express Clock 3 is only received Clock 3 is routed to a multiplexer which allows programming the clock source of the PCIe line to be either Clock 3 or an internal differential 100 MHz reference clock In case clock 3 is to be used for a different functionality 1t also feeds the FPGA and may be used there for any suitable purpose 3 5 IPMB Interface The NAMC ECAT implements an IPMB interface consisting of an ATmegal6 16AC microcontroller and a couple of DC devices such as a temperature sensor The IPMB controller manages also the hot swap functionality and the geographical address as requested b
4. N A T to provide all products fully compliant to the RoHS directive as soon as possible For this purpose since January 31st 2005 N A T 1s requesting RoHS compliant deliveries from its suppliers Special attention and care has been paid to the production cycle so that wherever and whenever possible RoHS components are used with N A T hardware products already Compliance to WEEE Directive Directive 2002 95 EC of the European Commission on Waste Electrical and Electronic Equipment WEEE predicts that every manufacturer of electrical and electronical equipment which is put on the European market has to contribute to the reuse recycling and other forms of recovery of such waste so as to reduce disposal Moreover this directive refers to the Directive 2002 95 EC of the European Commission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS Having its main focus on private persons and households using such electrical and electronic equipment the directive also affects business to business relationships The directive is quite restrictive on how such waste of private persons and households has to be handled by the supplier manufacturer however it allows a greater flexibility in business to business relationships This pays tribute to the fact with industrial use electrical and electronical products are commonly integrated into larger and more complex environments or systems that cannot e
5. PCI X to PCIe bridge PLX The PCI Express interface connects to Port 4 of the Fat Pipe Region of the AMC backplane connector The implementation of PCle conforms to the AMC 1 specification IPMB The NAMC ECAT implements an IPMB interface which conforms to the AMC O specification Version 1 0 O N A T GmbH 10 NAMC ECAT Technical Reference Manual 1 1 Board Specification AMC Module Front I O RAM Power consumption Environmental conditions Standards compliance Version 1 0 Table 2 NAMC ECAT Features standard Advanced Mezzanine Card single width double height 3 2 x RJ45 connectors 8 KByte RAM 3 3V MP 0 1A max 12V 0 7A max Temperature operating 0 C to 50 C with forced cooling Temperature storage 40 C to 85 C Humidity 10 to 90 rh noncondensing PICMG AMCO Rev 2 0 PICMG AMC 1 Rev 1 0 PCI Express Base Specification Rev 1 1 PICMG SFP 0 Rev 1 0 System Fabric Plane Format IPMI Specification v2 0 Rev 1 0 PICMG uTCA 0 Rev 1 0 ETG 1300 Indicator and Labeling Specification O N A T GmbH 11 NAMC ECAT Technical Reference Manual 2 Installation 2 1 Safety Note To ensure proper functioning of the NAMC ECAT during its usual lifetime take the following precautions before handling the board CAUTION Electrostatic discharge and incorrect board installation and uninstallation can damage circuits or shorten their lifetime Version 1 0 Before installing or uninstalling the N
6. Supplies PCI to PCle Bridge PLX Power Supplies Top View OS b FPGA Lattice DOAOMZZOO OZ b ET 1100 C O N N E C T O R Bottom View Version 1 0 N A T GmbH 16 NAMC ECAT Technical Reference Manual 3 Functional Blocks The NAMC ECAT can be divided into a number of functional blocks which are described in the following paragraphs 3 1 EtherCAT Slave Controller ESC The ESC ET1100 is an ASIC from Beckhoff Automation that process the EtherCAT protocol in the hardware It offers various possibilities for the configuration and utilization of the available hardware recourses In figure 3 you can see the block diagram of the ESC and its configuration Figure 4 EtherCAT Slave Controller Block Diagram Ports 16 8 bit synchrounes 0 1 2 HController Auto Forwarder PHY MI Loopback EtherCAT Interface Process Data Interface PHY Management ma Sync Manager EtherCAT Processing Unit ESC address space Sync Latch ISC EEPROM Leds Reset Distributed Clocks Version 1 0 N A T GmbH 17 NAMC ECAT Technical Reference Manual For more details regarding the EtherCAT Slave Controller its function features properties and the allocation of the ESC address space please consider the ET1100 data sheet 3 2 FPGA The FPGA implements the following functional blocks e PCI interface for management e 16 8 bit uController interface
7. 2 141 140 139 138 137 136 135 134 Version 1 0 O N A T GmbH 23 NAMC ECAT Technical Reference Manual Version 1 0 Od AMC Signal 60 INC TDMO 11 joo INC O NC O os 68 NC NC o O 6 NC NC O qo 72 PWR_ NC 9 73 GND_ GND 98 75 CLK IN NC N A T GmbH 24 NAMC ECAT Technical Reference Manual AMC Signal AMC Signal 80 CIK3P PETOPP8 91 81 CIK3N PETONP8 90 82 GND__ GND s9 85 GND___ GND___ 86 4 3 Connector JP1 IPMI uC Programming Port Connector JP1 connects the programming port of the Atmel uC device Table 1 Atmel Programming Port Pin No Signal 6 JoND 4 4 Connector JP2 Lattice FPGA programming port Connector JP2 connects the JTAG or programming port of the Lattice FPGA device Version 1 0 Table 1 Lattice programming port 2 3 TDI PROGRAM 4 2 Es 5 ln TMS J 7 OND TCK dS 9 DONELAT INITLAT 10 O N A T GmbH 25 NAMC ECAT Technical Reference Manual 4 5 Hot Swap Switch SW1 Switch SW 1 is used to support hot swapping of the module It conforms to PICMG AMC 0 4 6 The Front Panel Connectors S1 S3 4 6 1 The Ethernet Connector S1 Table 2 100BaseT signals of the EtherCAT interface Table 2 Pin Assignment of the Front panel Connectors S1 Ethernet 5 er RO 7 e GND dS 9 IEDLA LEDIK io 4 6 2 The Ethernet Connector S2 Table 2 100BaseT sig
8. AMC ECAT read this installation section Before installing or uninstalling the NAMC ECAT read the Installation Guide and the User s Manual of the carrier board used or of the uTCA system the board will be plugged into Before installing or uninstalling the NAMC ECAT on a carrier board or both in a rack Check all installed boards and modules for steps that you have to take before turning on or off the power Take those steps Finally turn on or off the power if necessary Make sure the part to be installed removed is hot swap capable if you don t switch off the power Before touching integrated circuits ensure to take all require precautions for handling electrostatic devices Ensure that the NAMC ECAT is connected to the carrier board or to the uTCA backplane with the connector completely inserted When operating the board in areas of strong electromagnetic radiation ensure that the module 1s bolted the front panel or rack and shielded by closed housing O N A T GmbH 12 NAMC ECAT Technical Reference Manual 2 2 Installation Prereguisites and Reguirements IMPORTANT Before powering up e check this section for installation prerequisites and requirements 2 2 1 Requirements The installation requires only e an ATCA carrier board or a uTCA backplane for connecting the NAMC ECAT e power supply e cooling devices 2 2 2 Power supply The power supply for the NAMC ECAT must meet the followi
9. C EtherCAT Slave A PCI to PCle m T Controller FPGA gt Bridge gt PHY i Leds SPI AMC plug in Figure 2 shows a detailed block diagram of the NAMC ECAT 2 Ports Figure 2 NAMC ECAT Block Diagram 2 Ports EEPROM EEPROM MESSI PHY 0 IT EtherCAT Slave as PCI to PCle FPGA 22 ES Controller ete gt Bridge L Connector Leds MMC Leds SPI AMC plug in Version 1 0 N A T GmbH NAMC ECAT Technical Reference Manual Board Features e EtherCAT Ports There are 2 or 3 EtherCAT interfaces available on the NAMC ECAT They are realized by the Ethernet connectors and the PHYs which are connected to the EtherCAT Slave Controller ESC For the connection to the AMC based EtherCAT slave card a standard Ethernet patch cable 1s reguired e EtherCAT Slave Controller ESC The central component on the NAMC ECAT is the EtherCAT slave controller ET1100 The ESC is responsible for the EtherCAT communication between the EtherCAT fieldbus and the slave application The ESC contains the necessary components e g EtherCAT Processing Unit EPU FMMU SyncManager RAM etc for the data transfer between the fieldbus and the FPGA Thereby a 16 or 8 bit synchronous uController interface is used depending on the number of available ports on the NAMC ECAT e Backplane Interface PCIe The NAMC ECAT includes a x1 PCI Express interface This is implemented in a PEX8112
10. D Register This read only register can be used by the device driver to probe register access It holds the N A T internal board id of the NAMC ECAT Table 4 FPGA BOARD ID Register FPGA BOARD ID Address 0x08 Default value 0x0B0f Bit 15 0 Access R Func BOARD ID Version 1 0 N A T GmbH 29 NAMC ECAT Technical Reference Manual 5 1 1 6 FPGA Reset Register The Reset Register is used to trigger a reset to the whole FPGA logic FPGA blocks or external devices Writing a 1 to a bit triggers the reset After reset the bit is self cleared to 0 Table 5 FPGA Reset Register Reset Address Offset 0x100 Default value 0x0000 Bit 15 6 5 4 3 2 1 0 Access R W R W R W R W R W R W R W R W Func ESC 5 1 1 7 SPI interface register to FPGA PROM This chapter will be completed in a later version of the User s Manual For the time being contact N A T for further information 5 1 1 8 SPI interface register to Atmel This chapter will be completed in a later version of the User s Manual For the time being contact N A T for further information 5 1 1 9 ESC Register The ESC registers are divided into registers for configuration and control and registers for process data exchange The start address for the access on the ESC register is 0x10000 The table below shows the memory map For more information regarding read and write ac
11. NAMC ECAT Technical Reference Manual NAMC ECAT AMC EtherCAT Slave Module Technical Reference Manual V1 0 HW Revision 1 1 NAMC ECAT Technical Reference Manual The NAMC ECAT has been designed by N A T GmbH Kamillenweg 22 D 53757 Sankt Augustin Phone 49 2241 3989 0 Fax 49 2241 3989 10 E Mail support nateurope com Internet http www nateurope com Version 1 0 N A T GmbH 2 NAMC ECAT Technical Reference Manual Disclaimer The following documentation compiled by N A T GmbH henceforth called N A T repre sents the current status of the product s development The documentation 1s updated on a regular basis Any changes which might ensue including those necessitated by updated speci fications are considered in the latest version of this documentation N A T is under no obli gation to notify any person organization or institution of such changes or to make these changes public in any other way We must caution you that this publication could include technical inaccuracies or typographi cal errors N A T offers no warranty either expressed or implied for the contents of this documentation or for the product described therein including but not limited to the warranties of merchant ability or the fitness of the product for any specific purpose In no event will N A T be liable for any loss of data or for errors in data utilization or processing resulting from the use of this
12. Table FPGA Version Regresa 29 Table 2 FPGA ID 1 Register zisk salsa anal tda ad 29 Tabl 3 VEPGCA IE 2 Rent e ie pel de tl ed ette enr 29 Table4 FPGA BOARD ID Registr a it 29 Tables FPGA Reset Registr A TR Aes a ees 30 Tabled ESC Regina 30 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Version 1 0 NAMC ECAT Block Diagram 3 Ports 9 NAMC ECAT Block Diagram 2 Ports 9 Location diagram of the NAMC ECAT rena 16 EtherCAT Slave Controller Block Diagram sss sees 17 PC Structure of the NAMC ECAT a 19 PC Structure of the NAMC ECAT bb 19 Front Panel 3 Potasio 21 Front Panel O ST yaa id 21 Connectors of the NAME BCA Ti Re en 22 O N A T GmbH 6 NAMC ECAT Technical Reference Manual Conventions If not otherwise specified addresses and memory maps are written in hexadecimal notation identified by Ox Table 1 gives a list of the abbreviations used in this document Table 1 List of used abbreviations CA E B Ye S O AMC CPU EPU ESC PDI RAM ROM Version 1 0 N A T GmbH 7 NAMC ECAT Technical Reference Manual 1 Introduction The NAMC ECAT is an EtherCAT Ethernet for Control Automation Technology interface card in AMC Advanced Mezzanine Card form factor The slave card has the task to connect a flexible scalable and powerful Micro Telecommunications Computing Architecture UTCA Sy
13. asily be split up again when it comes to their disposal at the end of their life cycles Version 1 0 O N A T GmbH 14 NAMC ECAT Technical Reference Manual As N A T products are solely sold to industrial customers by special arrangement at time of purchase the customer agreed to take the responsibility for a WEEE compliant disposal of the used N A T product Moreover all N A T products are marked according to the directive with a crossed out bin to indicate that these products within the European Community must not be disposed with regular waste If you have any guestions on the policy of N A T regarding the Directive 2002 95 EC of the European Commission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS or the Directive 2002 95 EC of the European Commission on Waste Electrical and Electronic Equipment WEEE please contact N A T by phone or e mail 2 3 3 Compliance to CE Directive Compliance to the CE directive is declared A CE sign can be found on the PCB 2 3 4 Product Safety The board complies with EN60950 and UL1950 Version 1 0 O N A T GmbH 15 NAMC ECAT Technical Reference Manual 2 4 Location Overview Figure 3 and figrure 4 show the position of important components Depending on the board type it might be that the board does not include all components named in the location diagram Figure 3 Location diagram of the NAMC ECAT Power
14. cesses on these registers please consider the ESC data sheet 1 Table 1 ESC Register Address Offset Logical Block 0x 10000 Register for ESC configuration and control 0x11000 Register for ESC process data exchange Version 1 0 O N A T GmbH 30 NAMC ECAT Technical Reference Manual 6 Known Bugs Restrictions none Version 1 0 N A T GmbH 31 NAMC ECAT Technical Reference Manual Appendix A Reference Documentation 1 Beckhoff ET1100 Hardware Data Sheet Rev 1 5 2 Broadcom BCM5241 Data Sheet Document 5241 DS12 R 3 Atmel AT24C128 256 Data Sheet Rev 0670J SEEPR 4 1 03 4 Atmel Atmega16 16L Product Data Rev 2466C 03 02 5 Lattice ECP2 M Handbook Version 04 2 6 PLX Technology PEX8112 A A PCI Express to PCI Bridge Data Book Version 1 2 Version 1 0 N A T GmbH 32 NAMC ECAT Technical Reference Manual Appendix B Documen s History a FE i Version 1 0 N A T GmbH 33
15. ess the EtherCAT slave controller registers for configuration and process data exchange 5 1 1 FPGA GP Registers Status This chapter describes the basic board control registers implemented within the FPGA Further register description will follow up in future versions of this manual 5 1 1 1 PCB Version Register The Version Register holds the PCB Revision encoded in two nibbles Table 1 PCB Version Register PCB Version Address 0x00 Default value 0x0011 Bit 15 8 7 4 3 0 Access R R R Func reserved Version Major Version Minor Version 1 0 N A T GmbH 28 NAMC ECAT Technical Reference Manual 5 1 1 2 FPGA Version Register The Version Register holds the FPGA Revision encoded in two nibbles Table 1 FPGA Version Register FPGA Version Address 0x02 Default value 0x0010 Bit 15 8 7 4 3 0 Access R R R Func reserved Version Major Version Minor 5 1 1 3 FPGAID 1 Register This read only register can be used by the device driver to probe register access Table 2 FPGA ID 1 Register FPGA ID 1 Address 0x04 Default value 0xA A 55 Bit 15 0 Access R Func ID_1 5 1 1 4 FPGA ID_2 Register This read only register can be used by the device driver to probe register access Table 3 FPGA ID_2 Register FPGA ID_2 Address 0x06 Default value 0xDEAD Bit 15 0 Access R Func ID 2 5 1 1 5 FPGA BOARD I
16. nals of the EtherCAT interface Table 3 Pin Assignment of the Front panel Connectors S2 Ethernet Version 1 0 5 Jer po JO poi CONDE ale gt 3 9 LEDIA LEDI K 10 O N A T GmbH shows the pin assignment of RJ45 connector S1 This connector carries the shows the pin assignment of RJ45 connector S2 This connector carries the 26 NAMC ECAT Technical Reference Manual 4 6 3 The Ethernet Connector S3 Table 2 100BaseT signals of the EtherCAT interface Table 4 Pin Assignment of the Front panel Connectors S3 Ethernet Version 1 0 ne aa LEDI K 11 LED2A LED2K 12 1 3 Soler RX2 O Io e 7 LEDI K 1 3 5 7 11 O N A T GmbH shows the pin assignment of RJ45 connector S3 This connector carries the 24 NAMC ECAT Technical Reference Manual 5 NAMC ECAT Programming Notes The table below shows the memory map for the logical sub blocks of the design Refer to the following sub chapters for detailed information Table 1 FPGA Memory Map Address Offset 0x00000 General Purpose Status read only 0x00100 General Purpose Registers 0x01000 SPI interface to FPGA PROM 0x02000 SPI interface to MMC Atmel 0x10000 uC interface to EtherCAT Slave Controller The FPGA Design consists of two main blocks e Misc board control and status registers and a register interface to access the FPGA s PROM and the MMC e Controller interface to acc
17. ng specifica tions e required for the module 12V 0 7A max 2 2 3 Automatic Power Up In the following situations the NAMC ECAT will automatically be reset and proceed with a normal power up Voltage sensors The voltage sensor generates a reset e when 12V voltage level drops below 8V e when 3 3V voltage level drops below 3 08V or when the carrier board backplane signals a PCle Reset Version 1 0 N A T GmbH 13 NAMC ECAT Technical Reference Manual 2 3 Statement on Environmental Protection 2 3 1 2 3 2 Compliance to RoHS Directive Directive 2002 95 EC of the European Commission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS predicts that all electrical and electronic equipment being put on the European market after June 30th 2006 must contain lead mercury hexavalent chromium polybrominated biphenyls PBB and polybrominated diphenyl ethers PBDE and cadmium in maximum concentration values of 0 1 respective 0 01 by weight in homogenous materials only As these hazardous substances are currently used with semiconductors plastics i e semiconductor packages connectors and soldering tin any hardware product is affected by the RoHS directive if it does not belong to one of the groups of products exempted from the RoHS directive Although many of hardware products of N A T are exempted from the RoHS directive it is a declared policy of
18. nte serre ere de em dent ds ta sense 17 3 1 ETHERCAT SLAVE CONTROLLER ESC iii 17 312 lA ARE ne Inn crie D Ar 7 A T N Ab o in 18 3 3 PCLEXPRESS INTEREFAC Beis ais rito tete nn 18 34 AMGCLOCKINIERFACE eme Men meet er 18 353 IEMB INTERFACE Los 22 tattoo ot A BASS col tea lr 326 DR e et ee me et nn no 18 3 06 w ACS DEVICES ee o ce LO es er a on o el der na LAD o e ne a 18 3 7 AMC PORT DEFINITION ccococcnonononononononononononononononononononononononononononononononononononononononononononononononnnnononnnnnnnnnons 20 3 8 FRONT PANEL ANDLEDS oooooccconononononononononononononononononononononononononononononononononononononononononononononononononononononos 21 4 ANNO incdecsssbecscesdessseteebaseeas seas ssbeed oasuscsesssetaebasenss aa 22 4 1 GONNECTOR OVER VIEW a tthe Sistas ceeds coeds 22 42 AMG CONNECT its 23 4 3 CONNECTOR JP1 IPMI 4C PROGRAMMING PORT 25 4 4 CONNECTOR JP2 LATTICE FPGA PROGRAMMING PORT 25 AS HOTSWAPSWITCH SW a a nae EE N to 26 4 6 THE FRONT PANEL CONNECTORS S1 S3 ono novo nn on nn 26 4 6 1 THEE therner Connector SEEN ER NAN ii 26 4 6 2 The ektherner Connector S Zas RER E EE AS A ee 26 4 6 3 The Ethernet Connector S Ians nran ER EA IE Se a n 27 5 NAMC ECAT PROGRAMMING NOTE G ccssssccsssssccsssssccssssccccssseccscssccccsssaccccssssccssssseccsssaccccsssseces 28 Dido ZPPGA GP Reglsters S TOUS a A Nan 28 Slot PCB Version Regist can NA 28 Version 1 0 N A T GmbH 4 NAMC ECAT
19. on 1 0 O N A T GmbH 3 NAMC ECAT Technical Reference Manual Table of Contents LIST OF TABLES siviscsscssicscecscssesssiccssdessuienssodesceseedeveedsviedsosebadesdseteessductsesscsededesessesensecsescscesivessssdsceasoededeedscbessoes 6 EIST OF FIGURES zku vao das ovi 6 CONVENTIONS wistsssssisssccccccsssscsscovsscsscbuessoscsvecssbscessduceceessbessessncessessubobsvessicssevesscnsescedesdescoscuieassdcovecssbusdesssieseeesses 7 1 INTRODUCTION 6s isessscscsscscessosssiciesesiessssvsees saseiavesssvdeceictecsoesdvssscesesesdsncoessscbiesestensevssusecesesieeiasvbeed adusaeesseys 8 BOARD FEA TURES aio 10 1 1 BOARD SPECIBIGA TION aiii 11 2 INSTALLATION 6 sscsccsssssscescosescossvusssossctussobentasssssecesssdessesevsesesesdensesssesdesessossuveasesdescedsubsssssssducsodesvasesseetese 12 E SAFETY NOTE U en 12 2 2 INSTALLATION PREREQUISITES AND REQUIREMENTS eee 13 2 21 O 71 RA A ANA E a nu GUN Cedar Aonde sde tendent es 13 2 22 PoweriSUpply onini AR O A a R En nn ns eee relient is 13 2 23 Automatic Power Ubicacion id iia 13 2 3 STATEMENT ON ENVIRONMENTAL PROTECTION 14 2 3 1 Compliance to ROHS Directive sense li teca e a songs aan sn aaa decirles lies 14 2 3 2 Compliance to WEEE Directive oriak ninie eaeoe nena A aeee non naar ana cnn E SEa 14 2 3 3 Compliance to CE DirecVenininaci n varna 15 2 3 4 Product Sali ds iia 15 24 LOCATION OVERVIEW 1002 16 3 FUNCTIONAL BLOCKS 55 nadia dents sudok rece
20. product or the documentation In particular N A T will not be responsible for any direct or indirect damages including lost profits lost savings delays or interruptions in the flow of business activities including but not limited to special incidental consequential or other similar damages arising out of the use of or inability to use this product or the associated documentation even if N A T or any authorized N A T representative has been advised of the possibility of such damages The use of registered names trademarks etc in this publication does not imply even in the absence of a specific statement that such names are exempt from the relevant protective laws and regulations patent laws trade mark laws etc and therefore free for general use In no case does N A T guarantee that the information given in this documentation is free of such third party rights Neither this documentation nor any part thereof may be copied translated or reduced to any electronic medium or machine form without the prior written consent from N A T GmbH This product and the associated documentation is governed by the N A T General Conditions and Terms of Delivery and Payment Note The release of the Hardware Manual is related to a certain HW board revision given in the document title For HW revisions earlier than the one given in the document title please contact N A T for the corresponding older Hardware Manual release Versi
21. stem to the high speed EtherCAT fieldbus Using uTCA as dedicated slave nodes in an EtherCAT network adds a new dimension of intelligent and scalable nodes to this industrial automation network This requires the utilization of the EtherCAT interface card NAMC ECAT Key component of the EtherCAT slave card NAMC ECAT 1s the ESC EtherCAT Slave Controller as Interface between the EtherCAT bus and the user application within the uTCA system As ESC the EtherCAT ASIC ET1100 from Beckhoff Automation is used The ESC has an 8kByte Dual Port RAM to exchange data between the EtherCAT network and the application The NAMC ECAT 1s available as a single mid or a single full size module Form the point of view of the EtherCAT fieldbus there are two different versions regarding the EtherCAT interfaces The slave card is available in a two or three port version The NAMC ECAT has the following major features implemented on board e Ports 3 2 x RJ45 EtherCAT interfaces e RAM KByte 8 e Fieldbus Memory Management Unit FMMU 8 e SyncManagers 8 e Distributed Clocks 64 bit e Process Data Interface PDI 16 8 bit synchronous u Controller e Lane PCI Express Interface Rev 1 1 e Configuration Control via PCle or via EtherCAT Version 1 0 O N A T GmbH 8 NAMC ECAT Technical Reference Manual Figure 1 shows a detailed block diagram of the NAMC ECAT 3 Ports Figure 1 NAMC ECAT Block Diagram 3 Ports EEPROM EEPROM Y DE PHY
22. y the AMC specification 3 6 IC Devices Two PC busses connect to the IPMI controller an ATmegal6 16AC microcontroller The first one is the IPMB bus of the AMC connector The second PC bus connects the IPMI controller the Hot Swap Controller and a temperature sensor These devices are all powered by IPMB power Version 1 0 O N A T GmbH 18 NAMC ECAT Technical Reference Manual Figure 5 PC Structure of the NAMC ECAT a Hot Swap Controller ATmegal6 16AC uC IPMB L Temp Sensor A third PC bus connects the FPGA and the EEPROM which is necessary for the ESC The EEPROM can also be accessed via ESC Figure 6 PC Structure of the NAMC ECAT b EtherCAT Slave Controller Version 1 0 N A T GmbH 19 NAMC ECAT Technical Reference Manual 3 7 AMC Port Definition Table 3 AMC Port Definition CLKI Reference Clock 1 CLK2 Clocks Reference Clock 2 7 CLK3 Reference Clock 3 2 0 Common unassigned E 1 Options unassigned 8 2 Region unassigned 3 unassigned 3 4 PCI Express Lane 0 default Fa 5 unassigned 6 Fat unassigned 7 Pipes unassigned 8 Region unassigned 9 unassigned 10 unassigned 3 11 unassigned 3 12 unassigned 5 13 unassigned S 14 unassigned T 15 Extended unassigned 3 CLK4 5 Options Reference Clock 4 5 S 17 Region unassigned 18 unassigned 19 unassigned
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