User`s Manual
Contents
1. RTE VR4100 PC Board Top View 3 1 RESET SWITCH SWRESET SWRESET is a reset switch Pressing this switch causes the CPU to be reset 3 2 POWER SUPPLY CONNECTOR JPOWER When this board is to be used as a standalone that is without being inserted in an ISA bus slot the board should be supplied with power from an external power supply by connecting it to the JPOWER connector The external power should be one rated as listed below Voltage 5V Current Maximum of 2 5 A excluding the current supplied to the JEXT connector Mating connector Type A 5 5 mm in diameter Polarity Caution When attaching an external power supply to the board be careful about its connector polarity When inserting the board into the ISA bus slot do not attach the JPOWER connector to an external power supply RTE VR4100 PC USER S MANUAL 3 8 CLOCK SOCKET OSC1 OSC1 is an 8 pin socket for an oscillator to generate clock pulses supplied to the CPU The socket is factory equipped with a 10 MHz oscillator When exchanging it be careful about its polarity Caution When you have to cut an oscillator pin for convenience be careful not to cut it too short or otherwise the frame housing of the oscillator may touch a tine in the socket resulting in a short circuit occurring2. 3 4 CPU SWITCH SW1 SW1 is a switch for determining the operation mode of the VR4100 Itis set as listed below W1 contact 1 ON BIGENDIAN 0 Low Little endian OFF BIGENDIAN 1 High default Big endian ON HIZPARITY 0 Low OFF HIZPARITY 1 High default ON DIV2 0 Low OFF DIV2 1 High default 4 5 6 7 Not used fixed at OFF ON 64 bit monitor OFF 32 bit monitor default SW1 Setting 3 5 CONFIG SWITCH SW2 SW2 is a switch for general purpose input ports When a switch contact is open it corresponds to 1 When it is closed it corresponds to 0 See Section 5 2 2 for details 3 6 ISA PORT SWITCH SW3 SW3 is a switch for selecting the I O address of the ISA bus Switch contacts 1 to 8 corresponds to ISA addresses A4 to A11 respectively A12 to A15 are fixed at 0 This means that the I O address that can be selected ranges between 000xH and OFFxH When a switch contact is open it corresponds to 1 When it is closed it corresponds to 0 SW3contact 1 2 3 4 5 6 7 8 SVV3 to ISA Address Correspondence 3 7 LED POWER AND LED8 TO LED1 LED POWER lights when power is supplied LED8 to LED1 can be turned on and off from general purpose output ports See Section 5 2 3 for details RTE VR4100 PC USER S MANUAL 3 8 ROMEMU JUMPER JP3 JP3 is a set of jumper pins which are set to use mainly the ROM in circuit debugger It enables a reset and an interrupt from the ROM in
3. 33 RTE VR4100 PC USER S MANUAL e SW3 syve contaci 1 2 3 4 5 6 7 8 VO address ON 020xH OFF 1 factory set ISA to I O Address Correspondence 8 2 JUMPERS e JP3 ROMEMU Function Function RESET input active low INTO input active low 47 kQ pull up resistor 47 kQ pull up resistor NMI input active low INT1 input active low 47 kQ pull up resistor 47 kQ pull up resistor 47 kQ pull up resistor 47 kQ pull up resistor poses Not used NC INT4 nput active low 47 kQ pull up resistor o a GND JP3 Functions JP4 ROMSEL ROM type Pin connection with a bank Pin connection with no bank 271024 64Kx16Bit 9 10 11 12 factory set 1 2 3 4 76 J 272048 128Kx16Bit 1 11 11 1 1 2 34 56 274096 256Kx 6Bi 1 2 3 4 5 6 7 8 JP4 Pin Connection 34 RTE VR4100 PC USER S MANUAL Memo RTE VR4100 PC User s Manual M643MNL04 Created on October 15 1996 Rev1 0 Revice on Junuary 9 1998 Rev1 1 Midas lab 35
4. PREQ EREQ MasterCLOCK 17 ev INT O INT 1 INT 3 ColdRESET BIGENDIAN SW1 1 30 DIV2 SW1 3 HIZPARITY SW1 2 32 sw1 4 GND AAA TT J2 Pin Arrangement RTE VR4100 PC USER S MANUAL 3 13 DRAM SIMM SOCKETS The RTE VR4100 PC has two DRAM SIMM sockets used to install 4 Mbytes standard of SIMM Each socket can hold a 72 pin 4 8 or 16 Mbyte SIMM known as a module for DOS V machines so it is easy to expand the capacity of DRAM The capacity of installed SIMMs can be detected using a PIO port See Section 5 2 2 3 14 ROM SOCKETS The RTE VR4100 PC has ROM sockets Of these sockets two are used to hold 40 pin ROM chips to provide standard 128 Kbytes 64K x16 bits The access time of the ROM chips used here should be 150 ns or less The ROM has four banks that can be selected using switches to allow for selection of endian and operation mode See Section 3 9 for bank setting RTE VR4100 PC USER S MANUAL 4 INSTALLATION AND USE The RTE VR4100 PC board is designed to be installed in the ISA bus slot of a PC AT or compatible hereafter called the PC However it can also be used as a standalone if it is powered from an external power supply When the board is used for testing purposes or with the Multi debugger communication software called RTE for Windows must be installed in the PC Refer to the RTE for Windows Installation Manual for installation and test methods 4 1 BOARD SETTING
5. The RTE VR4100 PC board has DIP switches The DIP switches can be used to set up the evaluation board The switch layout is shown below O o POWER JPOWER b ROM D15 00 DRAM SIMM x2 VR4100 b ROM D32 16 Switches on the RTE VR4100 PC Board SW1 is used to set the CPU operation mode endian and internal clock W1 contact 1 ON BIGENDIAN 0 Low Little endian OFF BIGENDIAN 1 High Big endian ON HIZPARITY 0 Low OFF HIZPARITY 1 High default 3 ON DIV2 0 Low OFF DIV2 1 High default ON 64 bit monitor OFF 32 bit monitor default SW1 Setting SW2 is a switch for general purpose input ports For the Multi monitor in the factory installed ROM SW2 is used to set the RS 232C baud rate profiler timer period and VR4100 data rate RTE VR4100 PC USER S MANUAL SW contact Setting Not used 38400 baud 19200 baud 9600 baud factory set Baud Rate Setting SW2 contact Profiler period Setting Timer interrupt is not used 200Hz 5ms 100Hz 10ms 60Hz 16 67ms factory set Profiler Period Setting SW2 contact 5 6 Datare Setting
6. circuit debugger RESET input active low INTO input active low 47 kQ pull up resistor 47 kQ pull up resistor NMI input active low INT1 input active low 47 kQ pull up resistor 47 kQ pull up resistor Not used NC INT2 input active low 47 kQ pull up resistor Not used NC INT3 input active low 47 kQ pull up resistor INT4 input active low 47 kQ pull up resistor 132 Le JP3 Functions 3 9 ROMSEL JUMPER JP4 JP4 is a set of jumper pins for specifying the type of ROM to be installed in the ROM socket Its pins correspond to ROM addresses as shown below The ROM has four banks that can be selected by switching the upper address bits so that the system endians are supported CPU address 16 bit ROM address 4 5 271024 6 272048 7 274096 Monitor selection Endian JP4 Connection The table below lists the relationships between the ROM types and jumper pins to be strapped ROM type Pin connection with a bank Pin connection with no bank 271024 64K x 16Bit 9 10 11 12 factory set 1 2 3 4 272048 128Kx16Bi 11 1 1 2 34 56 274096 256Kx16Bi 1 2 34 5 6 7 8 JP4 Pin Connection RTE VR4100 PC USER S MANUAL 3 10 SERIAL CONNECTOR JSIO JSIO is a connector for the RS 232C interface controlled by the serial controller SCC2691 It is a 9 pin D SUB connector D SUB9 generally used with the PC AT All signals at this connector are at R
7. switch setting Turn off the power to the PC open its housing and confirm the ISA bus slot to be used If the slot is equipped with a rear panel remove the rear panel Insert the board into the ISA bus slot Make sure that the board does not touch any adjacent board Fasten the rear panel of the board to the housing of the PC with screws Turn on the power to the PC and check that the POWER LED on the board lights If the LED does not light turn off the PC power immediately and check the connection If the system does not start normally for example if an error occurs during installation of a device driver it is likely that the set I O address is the same as one already in use Reconfirm the l O address of the board by referring to the applicable manual of the PC or the board When the system turns out to be normal turn off the PC power again and put back its housing 4 3 STANDALONE USE OF THE BOARD When the RTE VR4100 PC is used as a standalone rather than being installed in the PC it requires an external power supply In addition communication with the debugger is supported only by the RS 232C interface This configuration is useful when the host debugger used with the board is not one in the PC AT or compatible as well as when the board is used for hardware confirmation and expansion The RTE VR4100 PC can be used as a standalone according to the following procedure 1 c2 3 Get an RS 232C cable for conn
8. way each port bit is used RTE VR4100 PC USER S MANUAL un ERN PP fixed fixed fixed fixed Out sai B RE ace ad td a Fors rar Por TOM T Esr Out e CLR fixed MIA Init PIO Bit Map The following paragraphs explain the meaning of each port bit Lwid 1 0 The minimum number of cycles is specified for local bus access The number of cycles is based on the LBCLK pulse generated by dividing the frequency of the TCLOCK by 2 See Section 5 3 3 for detailed timing descriptions Lwid 1 Lwid 0 Number of cycles ae o ee Mc E A eee EA ERES SAA Lwid 1 0 Setting Swait 1 0 The number of wait states is specified for the SRAM read cycle See Section 5 3 1 for detailed timing descriptions Swait 1 Swait 0 Ewik Sl gl P HE a EN ma Swait 1 0 Setting Dwid 1 0 The RAS CAS width is specified for the DRAM access cycle See Section 5 3 2 for detailed timing descriptions Dwid 1 Dwid 0 RAS precharge RAS Min CAS Read CAS Write 3 Dwid 1 0 Setting RTE VR4100 PC USER S MANUAL NOILV This bit specifies whether to select the interleave mode for DRAM access When 0O it selects the interleave mode When 1 it deselects the interleave mode NOHIT This bit specifies whether to enable a page hit for DRAM access When 0 it enables a page hit When 1 it disables a page hit TOVF This bit becomes 0 when the local bus cycle is 8 us or longer an
9. 00 0200H LED LED LED LED LED LED LED LED 0 2 ON output 8 7 6 5 4 3 2 1 1 OFF SWITCH LED Port Bit Map 20 RTE VR4100 PC 5 3 BUS CYCLE USER S MANUAL The RTE VR4100 PC controls the bus cycle according to the type of device used such as SRAM DRAM ROM or I O This section describes the timing of each access cycle 5 3 1 SRAM Access SRAM access involves 0 to 3 wait states according to the setting of the PIO See Section 5 2 2 Note that wait states can be inserted only in the read cycle TCLOCK SYSAD SYSCMD PMASTER PVALID ERDY EVALID Ws 0 3 Ws Ws Ws Ws Aia Ka PM KoK Kok a X KaK k Kok KoK KoK OA X SRAM Read Cycle Swait 1 On the write cycle latched data is written to SRAM always at the CPU data rate TCLOCK SYSAD SYSCMD PMASTER PVALID ERDY EVALID tren sg p dep cbe rapa KuKoKo Ko KeoX KuKoK K Keok SRAM Write Cycle 21 RTE VR4100 PC USER S MANUAL 5 3 2 DRAM Access The RAS CAS width and interleave page hit can be controlled for DRAM according to the setting of the PIO See Section 5 2 2 On a read cycle data is latched on the positive going edge of CAS and EVALID is returned on the next cycle TCLOCK SYSAD SYSCMD PMASTER PVALID ERDY EVALID RAS Bank0 CAS Interleave mode Bank1 CAS SYSAD SYSCMD PMASTER P
10. CK and LBCLK The number of bus cycles involved is listed below Local bus device SYSTEM I O EXT BUS TIMEOUT Number of Local Bus Cycles 26 RTE VR4100 PC USER S MANUAL 5 4 RESET The factors listed below trigger a CPU reset These factors cold reset the CPU They also system reset the board control circuit Power on reset Occurs when the power to the board is switched on JP3 ROMEM 1 Input at the RESET pin of JP3 See Section 3 8 Reset switch Generated by the reset switch SWRESET on the rear panel of the board Reset from the host Sent via the ISA bus at the request of the host PC 5 5 INTERRUPT The interrupt sources outside the CPU are listed below Interrupt Interrupt source JP3 3 INTO JP3 2 SCC2691 serial timer ISA communication TIMEOVER External Interrupts Among the above interrupts INTO can be masked by hardware See description about IRQMASK in Section 5 2 2 for how to mask interrupts INTO is handled according to the following procedure 1 Set the IRQMASK of the PIO to 1 to mask the interrupt by hardware 2 Check which has requested the interrupt the ISR of the SCC2691 the TOVF of the PIO or any other lt 3 gt Handle the interrupt for the requester and clear the request 4 Reset the IRQMASK of the PIO to 0 and unmask the interrupt 5b Exit the interrupt handling routine 27 RTE VR4100 PC USER S MANUAL 5 6 EXT BUS SPECIFICATION The
11. EXT BUS is used to expand memory and l O units The local bus on this board is connected to the JEXT connector The following tables list the pin arrangement of the JEXT connector and the functions of each signal The timing relationships between the signals are also shown below Number Signal name A8 WR A7 JEXT Connector Pin Arrangement name output 5v Supply voltage of 15 V GND Ground A 0 19 Output Address bus signal Byte high enable signal which is active when bits D 8 15 are enabled Data bus signal which is originally the CPU data bus signal received at al output buffer It is pulled up with a 47 kQ resistor on the board hd boa mm space is accessed NM Po po po tr fafa joa ja fa WR Output Write cycle timing signal which becomes active only when the EXT BUS space is accessed READY Input Signal indicating the end of a cycle It is valid only for the EXT BUS space To have the CPU recognize READY securely it is necessary to keep READY active until RD or WR becomes inactive It is pulled up with al 10 kQ resistor on the board INT Input Active low interrupt request signal which is connected to the INT2 pin of the CPU via a buffer lt is pulled up with a 10 KQ resistor on the board RESET Output Active low system reset signal LBCLK Output Clock signal generated by dividing the frequency of the TCLOCK of the VR4100 by 2 JEXT Connector Signals 28 RTE VR4100 PC U
12. RTE VR4100 PC User s Manual Midas lab RTE VR4100 PC USER S MANUAL REVISION HISTORY Explanation of revision October 15 1996 1 0 First edition The previously edited manual has been modified according to the change of the circuit board Junuary 9 1998 E 1 Changed the figure of JP4 at 3 9ROMSEL JUMPER JP4 page 9 PES the figure of External Interrupts at 5 5INTERRUPT page 27 RTE VR4100 PC USER S MANUAL CONTENTS 1 INTRODUCTIONS ti iin BUR ARR RBA RA RRS ee ey 5 1 1 NUMERIC NOTATION aaa aaa nana a eee eee tere te nn nn rra nnns tete rete nnns nnn nnnr nennt E 5 FEATURES AND FUNCTIONS nc rede dk Pee 6 BOARD GONFIGURATION ick ened eR Re Ree qi de ee 7 3 1 RESET SWITCH SVYR E SE Te ie erion poide nes nene e nese tete re tete ee ee tete rete te rere nente rete te rere e zere e te 7 3 2 POWER SUPPLY CONNECTOR JPOWER aa aaaa aaaa aaa nan ane a nene eee ennemis 7 3 3 CLOCK SOGKET OSG 1 evista evi tet ture d 8 3 4 CPU SWITGHN SW sc e e pete ue 8 3 5 CONFIG SWITGH SWO2 teet tete ate te ode ftatu tete atur te te Meter sant 8 3 6 ISA PORT SWITCH SW3 cauen runnu a eene nnm tete rere tete aN 8 3 7 LED POWER AND LEDS8 TO LEDI ende be cfc t tL c e abu dogs 8 3 8 ROMEMU JUMPER JP3 i e Uie e ten edi lent es dE ase Aa ines d 9 3 9 ROMSEL JUMPER IPA ede donit tae ead eq Suet side eek etal pedo de eod ede e ied 9 3 10 SERIAL CONNECTOR IS D aaa aaa nana aaa nanen e e r
13. S a E REM 30 6 3 INIT SP SETTING ana to etie eed eect ledge te eot e lend ee sd e edd 30 6 4 REMOTE CONNEGCTION tte dec n Ee oen edocet tees aes 30 7 RTE COMMANDS 3 cereti t tete e a hank hand dit dd th etd ea 31 RTE VR4100 PC USER S MANUAL 7 1 7 2 7 3 7 4 7 5 7 6 FT 8 1 8 2 EC E 81 E sida a ate Mane ae u e peat ar 31 Ess Ore AP MC Moraine eee lees DP E oa T Ema ue 81 CACHE US d enfe un e d acit n uf Too a E un auf T ad 32 SHOWTEB e D M 32 A ovs a 32 NONEM euet ace pc ead P LUE MM EN UMS M E LEE Ld 32 APPENDIX test irc vedi eh Pneus Me te Maa Me dine dt E dl lA dae kt at EE 33 SWITCHES casa 33 RR IE EE 34 RTE VR4100 PC USER S MANUAL 1 INTRODUCTION This manual describes the RTE VR4100 PC which is an evaluation board for the VR4100 NEC s CPU With the RTE VR4100 PC it is possible to develop and debug programs and evaluate the CPU performance using the GreenHills Multi debugger Communication with this debugger is carried out using the IBM PC AT ISA bus or RS 232C serial interface It is also possible to expand memory and I O units using local bus connectors provided on the evaluation board 1 1 NUMERIC NOTATION This manual represents numbers according to the notation described in the following table Hexadecimal and binary numbers are hyphenated at every four digits if they are difficult to read because of many digits being in each number Letter x is used
14. S 232C level Its pin arrangement and signal assignment are shown and listed below For connection signals connected to the host computer the table gives the wirings for both the D SUB9 pins and D SUB25 pins on the host side These are general cross cable wirings 09000 60090 JSIO Pin Arrangement JSIO Signal name Input Connector pin number on pin output the host side D SUB D SUB25 1 NC RxD RD input NC RxD RD DTR DR O 9 pU DTRDR Output 1 6 68 ECON COS REA 7 RTS RS Output 8 5 NG E JSIO Connector Signals 3 11 JEXT CONNECTOR JEXT is a connector mating with the EXT BUS connector for a user installed expansion unit See Section 5 6 for details of the EXT BUS 3 12 CPU TEST PINS J1 AND J2 J1 and J2 are connectors for CPU signals They are used to extend signals lines for testing or circuit expansion purposes Memo The mating connector for the J1 and J2 is FX4B1 40S 1 27SV HIROSE which is a 1 27 mm pitch surface mount connector RTE VR4100 PC USER S MANUAL SYSAD 0 SYSAD 1 SYSADI2 SYSADC 0 YSADI8 SYSAD 9 YSAD 10 SYSAD 1 SYSAD 12 min YSADI 16 SYSAD 18 YSAD 20 30 YSAD 24 SYSAD 26 SYSAD 28 SYSAD 30 40 J1 Pin Arrangement n t U min U min oo lt lt lt lt 02 02 min lt gt gt gt gt 2 g JU N O ne kari a P SYSCMDJIOJ SYSCMD 2 SYSCMDIAJ 9 PMASTER PVALID EVALID
15. SER S MANUAL A 0 19 BHE D O 15 READY A O 19 BHE D O 15 T16 K READY Read cycle VVrite cycle EXT BUS Cycle symbol Deseription MiNns MAX ns TY RDaddresssetuptime o T2 RDaddresshold uptime o RD cycle time RD data hold time T7 RDREADYWAITsetuptime o T8 RDREADYsetuptime o T9 RDREADYhold me o T10 WhRaddresssetuptime o WR data delay time EXT BUS AC Specifications 29 RTE VR4100 PC USER S MANUAL 6 Multi MONITOR The ROM chip on the board is incorporated with the Multi monitor The following cautions should be observed when the board is connected to the Multi server as the host 6 1 MONITOR WORK RAM The monitor uses the SRAM area between the start address and 10000H 64 KB as work RAM In other words user programs are not allowed to use logical addresses 8000 0000H to 8000 FFFFH and A000 0000H to A000 FFFFH 6 2 INTERRUPTS When running on the Multi motor user programs cannot use interrupts at present 6 3 INIT SP SETTING INIT SP stack pointer initial value is set to 8007 FFFCH highest SRAM address by the monitor INIT SP can be changed in the Multi environment 6 4 REMOTE CONNECTION Either serial or ISA bus connection can be selected for operation with the Multi server To Switch from serial connection to ISA bus connection or vice versa it is necessary to reset the mon
16. See Section 5 6 for details of the EXT BUS It can be accessed only as a noncache space in halfword 16 bit units SYSTEM I O 1C00 0000H to 1CFF FFFFH This space is assigned to I O devices for controlling each function on the board It acts as memory mapped I O units See Section 5 2 for details It can be accessed as a noncache space ROM 1F00 0000H to 1FFF FFFFH This space is provided in ROM on the board lts storage capacity is 256 Kbytes Its access time is 150 ns or less It can be accessed as either a cache or noncache space The standard ROM chip that is factory set contains the Multi monitor 5 2 SYSTEM 1 0 SYSTEM I O is an I O device mapped in a memory space The I O devices include the UART TIMER PIO and ISA bus interface The SYSTEM I O is designed to be accessed as a kernel noncache space So the following explanation uses logical addresses In addition data bus D 7 0 is connected and it is necessary to take endians into account during byte access When byte access is carried out with a big endian 3 is added as a byte offset Logical address I O device BC00 00xxH UART TIMER SCC2691 BC00 01xxH PIO wPD71055 BC00 02xxH LED SWITCH BC00 03xxH ISA BUS I F SYSTEM I O Device Map RTE VR4100 PC USER S MANUAL 5 2 1 5 2 2 Basically the board is used on a dedicated monitor program So the explanation of the ISA bus interface is left out The user program is prohibited from accessing the ISA bus int
17. VALID ERDY EVALID RAS Bank0 CAS NOT Interleave Bank1 CAS DRAM Read Cycle Dwid 1 22 RTE VR4100 PC USER S MANUAL On the write cycle ERDY is made negative and the write data received from the CPU is saved in a register then written to DRAM After all data is written ERDY is made positive again tecock LL LU UU UU UU UU UU UU UU UU e svsan Kakokokoioi syscmp _ who oKokeoK PMASTER PVALID ERDY EVALID RAS Bank0 CAS Interleave mode Bank1 CAS SYSAD SYSCMD PMASTER PVALID ERDY EVALID RAS Bank0 CAS NOT Interleave Bank1 CAS DRAM Write Cycle Dwid 1 Data Rate D 23 RTE VR4100 PC USER S MANUAL On the write cycle CAS may be kept waiting if the data rate is not D for example if it is Dxx TCLOCK SYSAD SYSCMD PMASTER PVALID ERDY EVALID RAS Bank0 CAS Bank1 CAS DRAM Write Cycle Dwid 1 Data Rate Dxx When the page hit mode is used RAS is put on hold after DRAM access If the row address matches hit at the next access the CAS cycle is executed immediately So the number of access cycles used is reduced If a mismatch occurs unhit however access is carried out
18. contents of the TLB in the CPU 7 6 IOREAD Format IOREAD BYTE SHORT LONG address The IOREAD command reads memory at the specified address according to the specified size and displays the data Select BYTE SHORT or LONG to specify 8 16 or 32 bits Use this command to access memory mapped l O Example IOREAD BYTE BC000100 BC000100 1A 7 7 IOWRITE Format IOWRITE BYTE SHORT LONG data address The IOWRITE command writes the specified data to memory at the specified address according to the specified size Select BYTE SHORT or LONG to specify 8 16 or 32 bits Use this command to access memory mapped l O Example IOWRITE SHORT 30F0 BCOOF000 32 RTE VR4100 PC USER S MANUAL 8 APPENDIX 8 1 SWITCHES SW1 D EE ws ON BIGENDIAN 0 Low Little endian OFF BIGENDIAN 1 High default Big endian B ON HIZPARITY 0 Low OFF HIZPARITY 1 High default EE ON DIV2 0 Low OFF DIV2 1 High default Not used fixed at OFF EDEN ON 64 bit monitor OFF 32 bit monitor default SW1 Setting SW2 Setting Not used 38400 baud 19200 baud 9600 baud factory set Baud Rate Setting Setting Timer interrupt is not used 200Hz 5ms 100Hz 10ms 60Hz 16 67ms factory set Profiler Period Setting Swaconad 5 6 __ Datarate Setting factory set Data Rate Setting Config AD bit OFF AD 0 Compact factory set Config AD Bit Setting
19. d a time out occurs The flag is cleared 1 using bit 1 TOVFCLR of port 2 TOVFCLR This bit clears 1 bit 5 of port 2 It should be initialized to 1 and usually kept to be 1 When TOVF is to be cleared the bit should be reset to 0 then set back to 1 IRQMASK This bit controls the mask of interrupts INTO to INT2 to the CPU When setto 1 it masks interrupts using a gate It is initialized to 1 After interrupts become acceptable it should be reset to 0 DTR This bit controls the DTR signal output from the JSIO connector The inverted state of this bit is converted to the RS 232C level and output to the JSIO connector DSR This bit indicates the state of the DSR signal input from the JSIO connector The state of this bit represents the inverted state of the DSR signal at the JSIO connector PD 2 1 PD 2 1 of the DRAM 72 pin SIMM on the board can be accessed The states of these bits indicate the size of the DRAM area on the board The table below lists the relationships between PD 2 1 and the DRAM capacity po o 4Mbyes 1 po Reevd ps po t6Mbytes PD 2 1 and DRAM Capacity 5 2 8 SWITCH LED General Purpose Input Output Ports The SWITCH LED port is an 8 bit input output port provided on the board It is used to read the state of the SW2 CONFIG DIP switch and turn on the LEDs LEDI8 11 BC00 0200H SW2 SW2 SW2 SW2 SW2 SW2 SW2 SW2 0 ON input 8 7 6 5 4 3 2 1 1 OFF BC
20. ection with the host and an external power supply 5 V 2 5 A on hand Especially for the power supply watch for its voltage and connector polarity In addition attach spacers to the four corners of the board so it will not pose any problem wherever it is installed See Sections 3 10 and 3 2 for RS 232C cable connection and the power supply connector respectively Set the RS 232C baud rate using a DIP switch on the board See Section 4 1 for switch setting Connect the board to the host via an RS 232C cable Also connect an external power supply to the JPOWER connector then check that the POWER LED on the board lights If the LED does not light turn off the power immediately and check the connection RTE VR4100 PC USER S MANUAL 5 HARDWARE REFERENCES This chapter describes the hardware of the RTE VR4100 PC 5 1 MEMORY MAP The memory assignment of the board is shown below Logical address Physical address 32 bit mode 32 bits FFE FFFF FFFF FFFF FFFF FFFF 1F00 0000 Kernel 1E00 0000 E000 0000 DFFF FFFF Supervisor Not used C000 0000 BFFF FFFF BUS ERR Noncache A000 0000 1400 0000 9FFF FFFF 1200 0000 8000 0000 8000 0000 1000 0000 7FFF FFFF 7FFF FFFF 6000 0000 Not used BUS ERR 4000 0000 0800 0000 2000 0000 0400 0000 1FFF FFFF 0000 0000 0000 0000 0000 0000 Memory Map The VR4100 has a memory management feature It converts logical addresses to physical addresses When the Multi monitor
21. erface UART TIMER SCC2691 The SCC2691 UART receiver transmitter LSI chip produced by PHILIPS Signetics is used as the UART TIMER Because the SCC2691 has a 3 character buffer in the receiver section it is possible to minimize chances of an overrun error occurring during reception Moreover a 3 6864 MHz oscillator is connected across the X1 and X2 pins It in conjunction with a 16 bit counter in the SCC2691 enables measurement of about 271 ns to 17 8 ms Each register in the SCC2691 is assigned as listed below Refer to the applicable SCC2691 manual for the function of each register Logical address BC00 0000H MR1 MR2 MR1 MR2 BC00 0008H BC00 0010H SCC2691 Register Map The general purpose output pin MPO and input pin MPI are used as RTS RS and CTS CS respectively DTR DR and DSR ER are controlled by the PIO See Section 5 2 2 for details PIO uPD71055 The uPD71055 produced by NEC is installed as a PIO The uPD71055 is compatible with the i8255 produced by Intel It has three parallel ports These ports are used for various types of control Each register of the PIO is assigned as listed below Logical address BC00 0100H PORTO PORTO BC00 0108H PORT1 PORT1 BC00 0110H PORT2 PORT2 BC00 0118H CMD REG PIO Register Map At a reset all PIO ports are set as input so the signal state of bits used for output is set to a high level using a pull up resistor The following table lists the
22. ete a zeze te tete EE eee tere z ene tetit 10 341 JEXTGONNEGTOR cout 10 3427 SGPUTESTIPINSI J AN DAI2 tu scite acer arrire ear peat c ee edits 10 3 19 DRAM SIMM SOGKELS iid eee die dadas 12 344 ROM SOCKERS a e UU e ieu 12 4 INSTALLATION AND USE mes te t de Pe E e de e d Pe diene 13 4 1 BOARD SETTING 2 n iE ae ee eB dh 13 4 2 INSTALLATION ON THE ISA BUS aaa aa nanen nanes eee eee teze e eee rene eee tete rere teze ree tete rere zeze rei te 15 4 3 STANDALONE USE OF THE BOARD aaa aaa nane nan enes eee ere tete re rete te tere t ene eee e eee rere rete 15 5 HARDWARE REFERENCES fee i test dd dd dd 16 5 1 MEMORY MAP etm he Late ate atl a I cin 16 5 2 SYSTEM Ove sa ret t varen e a te a fe dete boa ire ed ios 17 5 2 1 UART TIMER SCC2691 sss nennen nennen nnn 18 5 2 2 PIO WPD71055 23 00 inest dd 18 5 2 3 SWITCH LED General Purpose Input Output Ports aaa aaa aneve enen neve eee 20 5 3 BUS GYGL E 3g done ete eee eda elc oi do e pere tud e kada ar kat ea 21 5 3 1 SRAM ACCESS ees t uM 21 5 3 2 DRAM ACCESS o dada 22 5 3 3 A omo Se Sp ee peso er MM 26 5 4 RESET ESSERE aie 27 5 5 INTERRUPT 5 uer cic Mee dd sl ate dii 27 5 6 EXT BUS SPECIFICATION eret ta He HER IH Re TREE TOR E TRE E TR E d E nace 28 6 MULT MONITOR Sti xe Ride HR i s di I t ES EUM 30 6 1 MONITOR WORK RAM aaa nana ana ae ene eee sete tere nennen nnnm tete rere tete nnns n i teres ete rere tete eee nnns 30 6 2 INTERB BRT
23. factory set Data Rate Setting Config AD bit OFF AD 0 Compact factory set Config AD Bit Setting Contact 8 of SW2 is not used for the Multi monitor they are fixed at OFF SW3 is a switch for selecting the I O address of the ISA bus Switch contacts 1 to 8 correspond to ISA addresses A4 to A11 respectively A12 to A15 are fixed at 0 This means that the I O address that can be selected ranges between 000xH and OFFxH When a switch contact is open it corresponds to 1 When it is closed it corresponds to 0 Generally SW3 is set to any value between 20xH and 3FxH pSWsconaet 1 12 3 4 Ss 06 7 l VO address E E OFF 1 factory set SVV3 to ISA VO Address Correspondence Caution Allocate the I O address of the ISA bus to an address not in use referring to the manual of the used PC or other installed adapter boards RTE VR4100 PC USER S MANUAL 4 2 INSTALLATION ON THE ISA BUS When the RTE VR4100 PC is installed in the ISA bus slot of the PC power 5V is supplied from the ISA bus to the board In addition the ISA bus can be used for communication with the debugger so programs are down loaded at high speed Ihe RTE VR4100 PC can be installed in the ISA bus slot according to the following procedure 1 c2 3 d 5 Set the I O address of the PC using a DIP switch on the board Be careful not to specify the same I O address as used for any other I O unit See Section 4 1 for
24. is used programs are executed in the kernel space 8000 0000H to BFFF FFFFH where a TLB map is not used When a cache is used 8000 0000H is added to physical addresses to determine logical addresses When a cache is not used A000 0000H is added BUS ERR 0800 0000H to OFFF FFFFH 8000 0000H to FFFF FFFFH not used If this space is accessed a bus error occurs TIME OUT 1000 0000H to 15FF FFFFH not used If this space is accessed a time out about 8 us interrupt occurs 16 RTE VR4100 PC USER S MANUAL Reserved space 1 1600 0000H to 17FF FFFFH Reserved space 2 1800 0000H to 19FF FFFFH These spaces are reserved for future use Do not try to access them SRAM space 0000 0000H to 0007 FFFFH This space is provided in SRAM on the board Its capacity is 512 Kbytes SRAM can be accessed with no wait state as either a cache or noncache space DRAM space 0400 0000H to 07FF FFFFH This space is provided in the 72 pin SIMMs on the board Two 4M byte SIMM chips are already installed So the total capacity is 8 Mbytes Memory can be expanded by replacing the 4 Mbyte SIMM chips with 8 or 16 Mbyte SIMM chips This space can be accessed as either a cache or noncache space This space can be subject to parity check To use parity check enable it with SW1 2 assuming that SIMM has a parity bit EXT BUS 1A00 0000H to 1AFF FFFFH This space is used for a hardware expansion board connected to the JEXT connector on the RTE VR4100 PC
25. itor by pressing the reset switch on the rear panel and run the Check RTE utility of RTE for Windows 30 RTE VR4100 PC USER S MANUAL 7 RTE COMMANDS When the monitor and MIDAS server RTESERV are connected with the Multi debugger the TARGET window is opened The RTE commands can be issued in this window The following table lists the RTE commands HELP Displays help messages INIT Displays the version number RTE Commands Some commands require parameters All numeric parameters such as addresses and data are assumed to be hexadecimal numbers The following numeric representations are invalid 0x1234 1234H 1234 7 1 HELP 2 lt Format gt HELP command name The HELP command displays a list of RTE commands and their formats A question mark 7 can also be used in place of the character string HELP If no command name is specified in the parameter part the HELP command lists all usable commands Example HELP INIT Displays help messages for the INIT command 7 2 INIT Format INIT The INIT command initializes the RTE environment Usually this command should not be used 7 3 VER Format VER The VER command displays the version number of the current RTE environment 31 RTE VR4100 PC USER S MANUAL 7 4 CACHEFLUSH Format CACHEFLUSH The CACHEFLUSH command flushes the contents of the cache in the CPU 7 5 SHOWTLB lt Format gt SHOWTLB The SHOWTLB command lists the
26. on a usual RAS CAS cycle after RAS precharge So overhead increases TCLOCK SYSAD SYSCMD PMASTER PVALID ERDY EVALID Hit RAS CAS LY I 9 O DRAM Page Hit Unhit Cycle Dwid 1 24 RTE VR4100 PC USER S MANUAL CAS before RAS refresh is carried out for DRAM every 13 us TCLOCK RAS CAS REFRESH REFREQ 13 us DRAM Refresh Cycle Dwid 1 25 RTE VR4100 PC USER S MANUAL 5 3 3 Local Bus Access The local bus operates on a bus clock generated by dividing the frequency of the TCLOCK output from the CPU by 2 It is used in accessing the ROM I O and EXT BUS units The minimum number of clock pulses for each cycle can be specified according to the PIO setting See Section 5 2 2 On a read cycle data is latched on the positive going edge of RD and EVALID is returned on the next cycle On the write cycle ERDY is made negative and the CPU write data is saved in a register then written to the local bus After all data is written ERDY is made active again TCLOCK SYSAD SYSCMD PMASTER PVALID ERDY EVALID uox Read Local BUS Cycles Dwid 1 The hatching at LBCLK RD and WR indicates a timing deviation due to the synchronization relationship between the TCLO
27. to represent an arbitrary numeral in a number like 1FxxH Notation rule Only numerals are indicated 10 represents number 10 in decimal number Hexa A number is suffixed with letter H 10H represents number 16 in decimal decimal number A number is suffixed with letter B 10B represents number 2 in decimal number Number Notation Rules RTE VR4100 PC USER S MANUAL 2 FEATURES AND FUNCTIONS The overview of each function block of the RTE VR4100 PC is shown below Internal Control RS 232C CONNECTOR RTE VR4100 PC Block Diagram Features ROM 256 Kbytes 64K x 16 bits x 2 SRAM 512 Kbytes 64K x 16 bits x 4 DRAM 8 16 or 32 Mbytes standard of 8 Mbytes installed in 72 pin SIMM sockets RS 232C port 9 pin D SUB connector Communication function supported using the ISA bus of a PC AT or compatible Local bus connector for user installed expansion equipment Processor pin connector enabling measurement of all CPU signals External reset switch provided on the rear panel Connection pins for ROM in circuit debugger RTE VR4100 PC USER S MANUAL 3 BOARD CONFIGURATION The physical layout of the major components on the RTE VR4100 PC board is shown below This chapter explains each component o O POWER JPOWER ROM D15 00 o o DRAM SIMM x2 PLD f ROM D32 16
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