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Intro to ARM Cortex-M3 processor and LPC1768

1. Cortex M3 Pipeline e The Cortex M3 Uses the 3 stage pipeline for instruction executions Fetch Decode gt Execute Pipeline design allows effective throughput to increase to one instruction per clock cycle Allows the next instruction to be fetched while still decoding or executing the previous instructions Instruction Prefetch amp Execution Unaligned 32 bit Thumb 2 instruction in memory Executing i Decoding Fetching nstructions which can 3e misaligned in word Branch speculation buffer a Inst C1 Pipeline stage Instruction Execute fetch E Inst C2 amp D Inet A Processor Modes The ARM has seven basic operating modes Each mode has access to Its own stack space and a different subset of registers Some operations can only be carried out in a privileged mode Mode Description Supervisor Entered on reset and when a Software Interrupt SVC instruction SWI is executed Entered when a high priority fast interrupt is raised Entered when a low priority normal interrupt is raised Privileged modes Exception modes Used to handle memory access violations Undef Used to handle undefined instructions System ee mode using the same registers as User nee under which most Applications OS tasks Unprivileged mode Operating Modes User mode Exception modes Normal program execution mode Entered System resources unavailable upon exception Full acces
2. Load Store multiple register Can be extended to execute conditionally by adding the appropriate suffix Affect the CPSR status flags by adding the S suffix to the instruction Thumb 2 Instruction Set Thumb 2 instruction set is a superset of the previous 16 bit Thumb instruction set Provides A set of 16 bit instructions enabling 2 instructions per memory etc A small set of 32 bit instructions to support more complex operations Specific details of this ISA not our focus we ll mostly program in C Thumb 2 Instruction Set 32 bit and 16 bit Cortex M3 Thumb Instructions yf S 16 bit j 12 16bit Thumb 2 e Some of the changes used to reduce the length of the instructions from 32 bits to 16 bits reduce the number of bits used to identify the register e less number of registers can be used reduce the number of bits used for the immediate value e smaller number range remove options such as S e make it default for some instructions remove conditional fields N Z V C no conditional executions except branch remove the optional shift and no barrel shifter operation e introduce dedicated shift instructions remove some of the instructions e more restricted coding Thumb 2 Implementation The 32 bit ARM Thumb 2 instructions are added through the space occupied by the Thumb BL and BLX instructions 31 Hw Hw2 32 bit Thumb 2 Instruction format The first Halfword
3. FIOCLRO FIOCLR1 FIOCLR2 FIOCLR3 FIODIR2 Jy FIODIR3 LPC_GPIO_TypeDef __I0 uint32_t FIOSET uint32_t RESERVEDO 3 struct union __I0 uintl6 t FIOSETL __ IO uint32_t FIOMASK __ 10 uintl6 t FIOSETH struct uintl6 t FIOMASKL uintl6 t FIOMASKH uint8 t FIOSETO uint8 t FIOSET1 uint8 t FIOSET2 FIOMASKO _t FIOSET3 FIOMASK1 FIOMASK2 FIOMASK3 LPC1 768 e The register addresses of the various ports are defined in the library see lpc17xx h define LPC APBO BASE 0x40000000UL tdefine LPC_UART1_ BASE LPC_APBO BASE 0x10000 tdefine LPC SPI BASE LPC_APBO BASE 0x20000 tdefine LPC _GPIOINT BASE LPC_APBO BASE 0x28080 tdefine LPC ADC BASE LPC_APBO BASE 0x34000 define LPC _GPIO1L LPC_GPIO TypeDef LPC_GPIO1 BASE e For example to turn on LED P1 29 on the development board the following code can be used LPC _GPIO1 gt FIOSET 1 lt lt 29 Memory e On chip flash memory system Up to 512 kB of on chip flash memory Flash memory accelerator maximizes performance for use with the two fast AHB Lite buses Can be used for both code and data storage e On chip Static RAM Up to 64 kB of on chip static RAM memory Up to 32 kB of SRAM accessible by the CPU and all three DMA controllers are on a higher speed bus Devices with more than 32 kB SRAM have two additional 16 kB SRAM blocks LPC17xx system memory map 0x4010
4. Hw1 determines the instruction length and functionality If the processor decodes the instruction as 32 bit long the processor fetches the second halfword hw2 of the instruction from the instruction address plus two 13 32bit Instruction Encoding Example ADD instruction format e ARM 32 bit encoding for ADD with immediate field 31 28 27 26 25 24 2120 19 16 15 12 11 8 7 0 8 bit immediate number f t T Condition Minor Destination flags opcode register Major Set 4 bit opcode status rotate field Immediate flag First flag operand Typical settings register Major opcode 00 this indicates data operation instructions Minor opcode 0100 specifically 100 ADD instruction Immediate flag 1 immediate field in operand 2 Set status flag 1 set carry flag after operation ARM and 16 bit Instruction Encoding ARM 32 bit encoding ADDS r1 r1 2 31 26 2726 25 24 2120 19 16 15 12 11 8 T 0 15 13 12 11 10 8 7 0 e Equivalent 16 bit Thumb instruction ADD r1 2 No condition flag No rotate field for the immediate number Use 3 bit encoding for the register Shorter opcode with implicit flag settings e g the set status flag is always set Thumb Instruction Set a ee a 4 0 0 Offset11 EEEE e 10 9 8 7 6 5 4 3 2 1 0 See 4 THUMB _Instr_Set_pt3 pdf included in lab1_files zip Move shifted register Add subtract Move compare add subtract immediate AL
5. 0000 APB1 peripherals 4GB LPC1768 memory space hatten 0x400F C000 aF 7 0x400C 0000 B 0xE010 0000 AHB peripherals 0x5020 0000 oet00e 2000 14 motor control PWM private peripheral bus 000 0000 memme e USB controller 0x400B 4000 j USB controler oxs000 cooo ox4008 0000 0x5020 0000 ped ji aaja mesened i 0x400A C000 11 AHB periherals 0x5000 0000 GPDMA controler 0x5000 4000 ooa sooo O S _ A Ethernet controll reserved 70x4400 0000 controller 0x5000 0000 ox400a 4000 2 0x400A 0000 i peripheral bit band alias addressing 0x4200 0000 Oxso00 cooo Z VARTS i reserved z owen sooo S wane oan E ee 0xaoo8 0000 y ae 0x4008 0000 z APBO peripherals onan anon 0x4006 0000 ox4o0g0000 4 Timer2 Z i 0x4005 C000 J0x2400 0000 ox4004 C000 i 13 CAN2 0x4004 8000 0x4004 4000 hie CANcommon 9 4004 000 0x200 C000 15 CANAF registers ox4003 cooo vy i Jx2008 4000 1 0x4003 8000 MW owsooscooo 3 __ amp ere 0x4008 0000 gt 5 2 FF alg 3 S 8 f 05GB AHB SRAM 2 blocks of 16 kB 0x2007 C000 i 0x4003 4000 a 7 ax1FFF 2000 i 0x4003 0000 8 kB boot ROM OxtFFF 0000 EE 0x4002 C000 P A 4 2x1000 8000 0x1000 0000 32 kB local static RAM Heode D code memory space 0x4002 0000 0x4001 C000 0x4001 8000 OOO 4758 words a 0x4001 4000 0000 0000 7 fet uarTs 512
6. control the NVIC are defined to reside at address OxEOQOOEOOO and are defined by the Cortex M3 specification These registers are accessed with the system bus Outline e ARM Cortex M3 processor e NXP LPC17xx microcontroller unit MCU Basic Processor Based System Address bus data bus and bus control signals Cortex M3 processor vs CM3 based Microcontroller Units Developed by ARM Developed by chip manufacturers Cortex M3 35 While there is significant overlap between the families and their peripherals there are also important differences In the lab of this course we focus on the NXP s LPC17xx family ecte fy AIMEL i POWER MATTERS 2 eA SZED CYPRESS V EDUST PERFORM INSTRUMENTS LPC17xx LPC17xx of NXP is an ARM Cortex M3 based microcontroller The Cortex M3 is also the basis for microcontrollers from other manufacturers including Tl ST Toshiba Atmel etc LPC1768 operates at up to a 100 MHz CPU frequency Sophisticated clock system Peripherals include up to 512 kB of flash memory up to 64 kB of data memory Ethernet MAC a USB interface that can be configured as either Host Device or OTG 8 channel general purpose DMA controller 4 UARTs 2 CAN channels 2 SSP controllers SPI interface 3 12C interfaces 2 input plus 2 output 12S interface 8 channel 12 bit ADC 10 bit DAC motor control PWM Quadrature Encoder interface 4 general purpose timers 6 output general purpose PWM ultra lo
7. EE 379 Embedded Systems and Applications Intro to ARM Cortex M3 CM3 and LPC17xx MCU Cristinel Ababei Department of Electrical Engineering University at Buffalo Spring 2013 Note This course is offered as EE 459 500 in Spring 2013 Outline e ARM Cortex M3 processor e NXP LPC17xx microcontroller unit MCU Cortex M3 Processor RISC general purpose 32 bit microprocessor released 2006 Cortex M3 differs from previous generations of ARM processors by defining a number of key peripherals as part of the core interrupt controller system timer debug and trace hardware including external interfaces This enables for real time operating systems and hardware development tools such as debugger interfaces be common across the family of processors Various Cortex M3 based microcontroller families differ significantly in terms of hardware peripherals and memory Cortex M3 Processor Greater performance efficiency more work to be done without increasing the frequency or power requirements Implements the new Thumb 2 instruction set architecture e 70 more efficient per MHz than an ARM7TDMI S processor executing Thumb instructions e 35 more efficient than the ARM7TDMI S processor executing ARM instructions for Dhrystone benchmark Low power consumption longer battery life especially critical in portable products including wireless networking applications Improved code density code fits in even the smallest memor
8. SR which is implicitly accessed by many instructions Processor Register Set a rl r13 SP r14 LR r15 PC 9 i r r r z rT T r m z T Program Memory Model e RAM for an executing program is divided into three regions Data in RAM are allocated during the link process and initialized by startup code at reset The optional heap is managed at runtime by library code implementing functions such as the malloc and free which are part of the standard C library The stack is managed at runtime by compiler generated code which generates per procedure call stack frames containing local variables and saved registers RAM End high Main Stack Heap End Heap Start RAM Start low Cortex M3 Memory Address Space e ARM Cortex M3 processor has a single 4 GB address space The SRAM and Peripheral areas are accessed through the System bus The Code region is accessed through the ICode instructions and DCode constant data buses Ox41FFFFFF 0x40100000 Peripheral 0 5GB 0x60000000 OxSFFFFFFF 0x40000000 OXSFFFFFFF 0x20000000 0x1FFFFFFF 0x00000000 Instruction Set Architecture ISA e Instruction set Addressing modes Word size Data formats Operating modes Condition codes ys v8 NSl gt N on w N R13 SP R14 LR R15 PC xPSR Endianess Major Elements of ISA mov r 1 ld ri
9. U operations Hi register operations branch exchange PC relative load Load store with register offset Load store sign extended byte halfword Load store with immediate offset Load store halfword SP relative load store Load address Add offset to stack pointer Push pop registers Multiple load store Conditional branch Software Interrupt Unconditional branch Long branch with link Application Program Status Register APSR 31 30 29 28 27 26 APSR bit fields are in the following two categories Reserved bits are allocated to system features or are available for future expansion Further information on currently allocated reserved bits is available in The special purpose program status registers xPSR on page B1 8 Application level software must ignore values read from reserved bits and preserve their value on a write The bits are defined as UNK SBZP Flags that can be set by many instructions N bit 31 Negative condition code flag Set to bit 31 of the result of the instruction If the result is regarded as a two s complement signed integer then N 1 if the result is negative and N 0 if it 1s positive or zero Z bit 30 Zero condition code flag Set to 1 if the result of the instruction is zero and to 0 otherwise A result of zero often indicates an equal result from a comparison C bit 29 Carry condition code flag Set to 1 if the instruction results in a carry condition for example an un
10. base addresses for several peripherals see page 14 of the LPC17xx user manual 0x40010000 UART1 0x40020000 SPI 0x40028000 GPIO interrupts 0x40034000 ADC No real need for a programmer to look up all these values as they are defined in the library file lpc17xx h as LPC_UART1_BASE LPC_SPI_BASE LPC_GPIOINT_BASE LPC_ADC_BASE LPC1 768 e Typically each peripheral has e control registers to configure the peripheral e status registers to determine the current peripheral status e data registers to read data from and write data to the peripheral 38 LPC1768 e In addition to providing the addresses of the peripherals lpc17xx h also provides C language level structures that can be used to access each peripheral e For example the SPI and GPIO ports are defined by the following register structures typedef struct IO uint32_t SPCR I uint32_t SPSR IO uint32_t SPDR IO uint32_t SPCCR uint32_t RESERVEDO 3 __I0 uint32_t SPINT LPC _SPI_ TypeDef LPC1 68 typedef struct union __IO uint32_t FIODIR struct __I0 __I0 uint16 _t FIODIRL uint16_t FIODIRH FIODIRO FIODIR1 union __I0 uint32_t FIOPIN struct __I0 uintl6 t FIOPINL __I0 uintl6 t FIOPINH uint8 t FIOPINO uint8 t FIOPINI1 uint8 t FIOPIN2 FIOPIN3 union _O uint32_t FIOCLR struct i struct uint16 t FIOCLRL uint16 _t FIOCLRH uint8 t uint8 t uint8 t uint8s t
11. coding T2 All versions of the Thumb ISA MS Rds cR SEPPE Not permitted inside IT block 15 14 13 12 11109 8 7645 432 d UInt Rd m UInt Rm setflags TRUE if InITBlock then UNPREDICTABLE There are similar entries for move immediate move shifted which actually maps to different Encoding T3 ARMvi M instructions etc MOV S lt c gt W lt Rd gt lt Rm gt 15 14 13 12 11 10 9 7 654 32310 151153121109 amp 7 65435221 0D o ajo afoot ojs aoje oo r oo oo me d itl m UInt Rm setflags tee ean eee j UNPREDICTABLE MOVT Move Top writes an immediate value to the top halfword of the destination register It does not affect the contents of the bottom halfword_ Encoding T1 ARMyv M MOWT lt c gt lt Rd gt lt inmlb gt 15 14 13 12 11 10 9 8 Ff 65 43532321085M4i3LP W109 6 7 6 5 4 3 d UInt Rd i inml6 m iiim ims d IN 13 15 then UNPREDICTABLE Assembler syntax WOWT lt co lt g gt A lt inmli gt where lt C gt lt gt See Standard assembler syntax fields on page A6 7 lt Rd gt Specifies the destination register lt immlG gt Specifies the immediate value to be written to lt Rd gt It must be m the range 0 65535 Operation if ConditionPassed then EncodingSpeci fi cOperations R d lt 31 16 gt imi f f Ri dj lt 15 8 gt unchanged 29 Example 2 int counter int Counter Inc void return counter Resulting annotated assembly language with correspond
12. d How does a mixed C Assembly program get turned into a executable program image C files c Binary program file bin ld linker Assembly Object image File C A files s files EN image file L A gcc gt compile il as link assembler Memory layout x Disassembled Code 1st Library object Linker files 0 script 1d Nested Vector Interrupt Controller NVIC e A programmable device that sits between the CM3 core and the microcontroller CM3 uses a prioritized vectored interrupt model the vector table is defined to reside starting at memory location 0 First 16 entries in this table are defined for all Cortex M3 implementations while the remainder up to 240 are implementation specific NVIC supports dynamic redefinition of priorities with up to 256 priority levels Two entries in the vector table are especially important address 0 contains the address of the initial stack pointer address 4 contains the address of the reset handler to be executed at boot time 33 Nested Vector Interrupt Controller NVIC Provides key system control registers including the System Timer SysTick that provides a regular timer interrupt Provision for a built in timer across the Cortex M3 family has the significant advantage of making operating system code highly portable all operating systems need at least one core timer for time slicing Registers used to
13. ed before next instruction is executed Instruction synchronization barrier flushes the pipeline and ensures that all previous instructions are completed before executing new instructions 27 Unified Assembly Language e UAL supports generation of either Thumb 2 or ARM instructions from the same source code same syntax for both the Thumb code and ARM code enable portability of code for different ARM processor families e Interpretation of code type is based on the directive listed in the assembly file e Example For GNU Assembler the directive for UAL is syntax unified For ARM assembler the directive for UAL is THUMB Example 1 byte 0x12 20 0x20 1 mov r0 mov r4 MOvw movt ldrb add add cmp bne 0 0 EL ril r2 r4 ro 4 lower16 data upper16 data r1 1 r2 1 28 AG 76 MOV register Ab6 7 78 Move register copies a value from a register to the destination register It can optionally update the condition flags based on the value Encoding T1 ARMv6 M ARMv 7 M Tf lt Rd gt and lt fm both from RO R7 otherwise all versions of the Thumb ISA MVec gt Rds Rime If lt Rd gt 1s the PC must be outside or last in IT block 15 14 13 12 11 10 9 76543521 0 oroo oii op m m From ARM d Unt D Rd m UInt Rm setflags FALSE Arch Itectu re if d 15 amp InITBlock amp amp LastInITBlock then UNPREDICTABLE Refe rence Manu al En
14. information does the disassembled file provide arm none eabi as mcpu cortex m3 mthumb example1 s o examplel1 o arm none eabi ld Ttext x o examplel1 out example1 o arm none eabi objcopy Obinary example1 out example1 bin arm none eabi objdump S examplel out gt example1 1st equ STACK_TOP 0x20000800 example1 out file format elf32 littlearm text syntax unified thumb Disassembly of section text global _start type start function 00000000 lt _start gt 0 20000800 word Q x20000800 4 00000009 word 0x00000009 word STACK_TOP start 00000008 lt start gt movs rO 10 8 200a rO 10 movs r1 0 a 2100 r1 0 adds ri rO 0000000c lt loop gt subs rO 1 C 1809 Pi ri re bne loop e 3801 rO 1 deadloop 10 difc c lt loop gt b deadloop end 00000012 lt deadloop gt 12 e7fe 12 lt deadloop gt Elements of an assembly program equ STACK_TOP 9 x20000800 Equates symbol to value text Tells AS to assemble region Syntax unified Means language is ARM UAL thumb Means ARM ISA is Thumb global _start global exposes symbol _start label is the beginning of the program region type start function Specifies start is a function start label is reset handler word STACK_TOP start Inserts word 0x20000800 Inserts word start movs r 10 movs r1 0 adds r1 re subs rO 1 bne loop deadloop b deadloop en
15. ing OS calls 25 Branching Instructions Branch B jumps forwards backwards up to 32 MB Branch link BL same saves PC 4 in LR Suitable for function call return Condition codes for conditional branches Branching Instructions Table A4 1 Branch instructions Instruction Usage Range B on page A6 40 Branch to target address 1 MB CENZ CBZ on page A6 52 Compare and Branch on Nonzero 0 126 B Compare and Branch on Zero BL on page A6 49 Call a subroutine 16 MB BLY register on page A6 50 Call a subroutine optionally change Any BX on page A6 51 Branch to target address change instruction set TBB TBH on page A6 258 Table Branch byte offsets 0 510B Table Branch halfword offsets 0 131070 B 26 IF THEN Instruction Another alternative to execute conditional code is the new 16 bit IF THEN IT instruction no change in program flow no branching overhead Can use with 32 bit Thumb 2 instructions that do not support the S suffix Example CMP R1 R2 IfR1 R2 ITEQ execute next 1st instruction ADDEQ R2 R1 RO 1st instruction The conditional codes can be extended up to 4 instructions Barrier instructions Useful for multi core amp Self modifying code k a o aaan DMB Data memory barrier ensures that all memory accesses are completed before new memory access is committed DSB Data synchronization barrier ensures that all memory accesses are ISB complet
16. ing machine code Counter Inc 240 0300 lower16 counter amp counter 2c0 0300 upper16 counter 6818 r3 0 r3 1c42 ro 1 r0 1 60la r3 0 r3 r2 4740 return r0 Two 32 bit instructions movw movt are used to load the lower upper halves of the address of counter known at link time and hence 0 in the code listing Then three 16 bit instructions load Idr the value of counter increment adds the value and write back str the updated value Finally the procedure returns the original counter Key points Cortex M3 utilizes a mixture of 32 bit and 16 bit instructions mostly the latter and the core interacts with memory solely through load and store instructions While there are instructions that load store groups of registers in multiple cycles there are no instructions that directly operate on memory locations How does an assembly language program get turned into a executable program image Binary program file bin Assembly Object E tabl files s files 0 eL A image file ns gt ne gt Ja assembler N Memory layout Disassembled Linker code lst script ld An ARM assembly language program for GNU equ STACK_TOP x20000800 etext syntax unified thumb global _start type start function word STACK_TOP start movs rO 10 movs r1 0 adds r1 re subs rO 1 bne loop deadloop deadloop 31 What
17. kB on chip flash 0x4001 0000 a vaRTO ox4000 cooo 0x4000 8000 a TIMER oxs000 4000 jo wot _ ox 000 0000 ocs L References amp Credits Joseph Jiu The Definitive guide to the ARM Cortext M3 2007 LPC17xx microcontroller user manual Cortex M3 Processor Technical Reference Manual Lab manual G Brown Indiana EECS 373 UMich
18. ondition is used to execute the instruction irrespective of the value of the condition code flags By default data processing instructions do not affect the condition code flags but the flags can be optionally set by using S Ex SUBS ri r1 1 Conditional Execution improves code density and performance by reducing the number of forward branch instructions Conditional CMP 13 0 ADDNE 10 r1 r2 17 Conditional Execution and Flags ARM instructions can be made to execute conditionally by post fixing them with the appropriate condition code This can increase code density and increase performance by reducing the number of forward branches CMP ro ri r0 r1 compare r0 with r1 and set flags ADDGT r2 r2 1 if gt r2 r2 1 flags remain unchanged ADDLE r3 r3 1 if lt r3 r3 1 flags remain unchanged By default data processing instructions do not affect the condition flags but this can be achieved by post fixing the instruction and any condition code with an S loop ADD r2 r2 r3 r2 r2 r3 SUBS rl rl 0x0 decrement r1 and set flags BNE loop if Z flag clear then branch Conditional execution examples C source code ARM instructions unconditional CMP r0 0 BNE else ADD ri rl 1 B end ADDNE r2 r2 else ADD r2 r2 1 end a 5 instructions 3 instructions a 5 words 3 words 5or6 cycles 3 cycles 18 ARM Instruction Set Data Processing Instructions Arithmetic and logical opera
19. r Q 5 Vv ri mem r 5 bne loop subs r2 1 31 30 29 28 27 26 RESERVED 32 bits System Ox FFFFF FFF 0xE0100000 Private peripheral bus External 0xE0040000 Private peripheral bus Interna External device 1 0GB 0xE0000000 10xA0000000 1 0GB 10x60000000 al 0 5GB 0 5GB 10x40000000 0x 20000000 0 5GB Endianess 0x00000000 10 Addressing Big Endian vs Little Endian e Endian ness ordering of bytes within a word Little increasing numeric significance with increasing memory addresses Big The opposite most significant byte first MIPS is big endian x86 is little endian OAOBOCOD OAOBOCOD Instruction Encoding Instructions are encoded in machine language opcodes Instructions Register Value Memory Value movs rO 10 001 00 000 00001010 Oa 20 00 21 movs r1 0 001 00 001 00000000 Encoding T1 All versions of the Thumb ISA MOVS lt Rd gt lt immd gt Outside IT block MOVec gt lt Rd gt lt imma gt Inside IT block 15 14 13 12 11 10 9 amp 7 6 5 43 3 poipo s m d UInt Rd setflags InITBlock imm32 Zerokxtend imm 32 carry APSR C ARMv7 ARM Traditional ARM instructions Fixed length of 32 bits Commonly take two or three operands Process data held in registers Shift amp ALU operation in single clock cycle Access memory with load and store instructions only
20. range Addressing Modes e Offset Addressing Offset is added or subtracted from base register Result used as effective address for memory access lt Rn gt lt offset gt e Pre indexed Addressing Offset is applied to base register Result used as effective address for memory access Result written back into base register lt Rn gt lt offset gt e Post indexed Addressing The address from the base register is used as the EA The offset is applied to the base and then written back lt Rn gt lt offset gt lt offset gt options e An immediate constant 10 e An index register lt Rm gt e A shifted index register lt Rm gt LSL lt shift gt Block Transfer Instructions e Load Store Multiple instructions LDM STM e Whole register bank or a subset copied to memory or restored with single instruction Swap Instruction e Exchanges a word between registers e Two cycles but single atomic action e Support for RT semaphores 24 Modifying the Status Registers Only indirectly m MSR moves contents R1 from CPSR SPSR to MRS selected GPR R7 CPSR MSR P8 SPSR MRS moves contents from selected GPR to CPSR SPSR Only in privileged modes Software Interrupt SWI instruction Forces CPU into supervisor mode Usage SWI n 31 28 27 24 23 0 Maximum 274 calls Suitable for running privileged code and mak
21. s to system resources Mode changed by exception only Mode changed freely Exception f Pi Piped axt hander Operations Stacks ra va P privilege out of reset Main out of reset nan Exception Handler Privileged execution Main Stack Used by Y Pig S oa An exception is being processed Full contro OS and Exceptions thread exii seas of Thread Privileged Unprivileged Main Process CONTROL User thread register No exception is being processed Normal code is executing Modes Thread out of reset Exception Reset Undefined instruction Software interrupt Prefetch Abort Data Abort Interrupt Fast interrupt Exceptions Supervisor Undefined Supervisor Abort Abort IRQ FIQ 1 6 6 9 2 4 3 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000018 0x0000001C Table 1 Exception types sorted by Interrupt Vector addresses Processor Register Set e Cortex M3 core has 16 user visible registers All processing takes place in these registers e Three of these registers have dedicated functions program counter PC holds the address of the next instruction to execute link register LR holds the address from which the current procedure was called the stack pointer SP holds the address of the current stack top CM3 supports multiple execution modes each with their own private stack pointer Processor status register P
22. signed overflow on an addition V bit 28 Overflow condition code flag Set to 1 if the instruction results in an overflow condition for example a signed overflow on an addition Q bit 27 Set to 1 if an SSAT or USAT instruction changes saturates the input value for the signed or unsigned range of the result 15 Updating the APSR SUB Rx Ry Rx Rx Ry APSR unchanged SUBS Rx Rx Ry APSR N or Z bits might be set ADD Rx Ry Rx Rx Ry APSR unchanged ADDS Rx Rx Ry APSR Cor V bits might be set Overflow and Carry in APSR unsigned sum Ulnt x Ulnt y Ulnt carry_in signed _sum SInt x SInt y Ulnt carry_in result unsigned_sum lt N 1 0 gt signed_sum lt N 1 0 gt carry_out if Ulnt result unsigned_sum then 0 else 1 overflow if SInt result signed_sum then 0 else 1 16 Conditional Execution Each data processing instruction prefixed by condition code Result smooth flow of instructions through pipeline 16 condition codes ee pe Fe unsigned lower aud less unsigned signed greater AL higher or same than or equal Ea CC unsigned lower unsigned lower signed less than Nv NV special purpose purpose Conditional Execution Every ARM 32 bit instruction is conditionally executed The top four bits are ANDed with the CPSR condition codes If they do not matched the instruction is executed as NOP The AL c
23. tions 3 address format Two 32 bit operands op1 is register op2 is register or immediate 32 bit result placed in a register Barrel shifter for op2 allows full 32 bit shift within instruction cycle 19 Data Processing Instructions Arithmetic operations ADD ADDC SUB SUBC RSB RSC Bit wise logical operations AND EOR ORR BIC Register movement operations MOV MVN Comparison operations TST TEQ CMP CMN Data Processing Instructions Conditional codes Data processing instructions Barrel shifter Powerful tools for efficient coded programs 20 Data Processing Instructions e g if z 1 R1 R2 R3 4 compiles to EQADDS R1 R2 R3 LSL 2 SINGLE INSTRUCTION AJ Multiply Instructions Integer multiplication 32 bit result Long integer multiplication 64 bit result Built in Multiply Accumulate Unit MAC Multiply and accumulate instructions add product to running total 21 Multiply Instructions MUL Multiply 32 bit result MULA Multiply accumulate 32 bit result UMULL Unsigned multiply 64 bit result UMLAL Unsigned multiply accumulate 64 bit result SMULL signed multiply 64 bit result SMLAL signed multiply accumulate 64 bit result Data Transfer Instructions Load store instructions Used to move signed and unsigned Word Half Word and Byte to and from registers Can be used to load PC if target address is beyond branch instruction
24. w power RTC with separate battery supply up to 70 general purpose I O pins 36 LPC17638 SP0 PPIM 12 5it ADC GPIO Interrupt Ci 1 LPC1 68 LPC1768 microcontrollers are based on the Cortex M3 processor with a set of peripherals distributed across three buses Advanced High performance Bus AHB and its two Advanced Peripheral Bus APB sub buses APB1 and APB2 These peripherals are controlled by the CM3 core with load and store instructions that access memory mapped registers can interrupt the core to request attention through peripheral specific interrupt requests routed through the NVIC Data transfers between peripherals and memory can be automated using DMA Labs will cover among others basic peripheral configuration e g lab1 illustrates GPIO General Purpose I O peripherals how interrupts can be used to build effective software how to use DMA to improve performance and allow processing to proceed in parallel with data transfer 37 LPC1 68 Peripherals are memory mapped core interacts with the peripheral hardware by reading and writing peripheral registers using load and store instructions The various peripheral registers are documented in the user and reference manuals documentation include bit level definitions of the various registers and info on how interpret those bits actual physical addresses are also found in the reference manuals Examples of
25. y footprints Core pipeline has 3 stages Instruction Fetch Instruction Decode Instruction Execute Simplified Cortex M3 Architecture CM3 Care Interrupts Inst Data gt Code ry DCode System Cortex M3 Processor Core System Register Bank Debug System Dee Interrupts Instruction Fetch Unit Trace Interface Interrupt Controller Memory Interface Memory Instruction Bus Protection Data Bus Unit Bus Interconnect Debug Interface T Memory System Private and Peripherals Peripherals Optional Cortex M3 Processor Architecture Harvard architecture it uses separate interfaces to fetch instructions Inst and Data Processor is not memory starved it permits accessing data and instruction memories simultaneously From CM3 perspective everything looks like memory Only differentiates between instruction fetches and data accesses Interface between CM3 and manufacturer specific hardware is through three memory buses Code DCode and System for peripherals which are defined to access different regions of memory Cortex M3 Processor e Cortex M3 is a load store architecture with three basic types of instructions e register to register operations for processing data e memory operations which move data between memory and registers control flow operations enabling programming language control flow such as if and while statements and procedure calls

Intro to ARM Cortex-M3 processor and LPC1768

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