MPC8240CE:MPC8240 Integrated Processor Chip Errata
Contents
1. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 8 Read from 0xFFF00200 0xFFF00207 cannot negate an asserted MCP signal if PCI ROM is used Overview Reading from OxFFFO0200 0xFFF00207 does not negate an asserted MCP signal if PCI ROM is used Detailed Description If the processor core detects an asserted MCP and this results in a machine check interrupt the MPC8240 will issue a code fetch from OxFFFO0200 if MSR IP 1 or from 0x00000200 if MSR IP 0 Upon seeing the fetch from the MCP exception handler the MPC8240 should then negate the MCP signal However if the address 0xFFF00200 is used while ROM is located in PCI memory space RCSO 0 during reset this read operation will not negate the MCP signal Projected Impact Unable to negate MCP signal by opcode fetch from location OxFFFO0200 if PCI ROM is used Work Arounds The machine check exception handler can perform a dummy read from 0x00000200 in order to negate the MCP signal Projected Solution Document software requirement in the MPC8240 Integrated Processor User s Manual MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 9 DLL_RESET bit must be toggled by system software during initialization to ensure DLL clock functionality Overview DLL_RESET bit must be toggled by system software2. No Problem Description Impact Work Around 1 1 1 11 1 2 1 3 12 GNT 0 has double When the on chip PCI arbiter is disabled Systems using an external PCI None Y Y output valid delay GNT 0 will function as the bus request arbiter may encounter a GNT 0 from the MPC8240 to the external PCI signal output valid timing problem arbiter in order to get ownership of the output valid time gt 6 0 ns when PCI bus However due to the existence operating the PCI bus at 66 MHz of a logic error there is a double output even if PCILHOLD_DELAY 0 2 valid delay for this output signal This is 000 to minimize the output valid caused by the logic having twice as time many delay elements as required between the latch and the output pin Note these additional delay elements are controlled by the PCI_HOLD_DELAY 0 2 bits bits 6 4 of the PMC Register 2 lt 0x72 gt 13 Dual PLL bypass mode When PLL_CFG 0 4 is configured for PLL_CFG 0 4 00110 dual PLL None YIYIYIY not functioning 00110 the MPC8240 does not boot This configuration bypasses both the peripheral logic PLL and the CPU logic PLL With the CPU PLL bypassed there is no synchronization feedback mechanism to maintain the phase relationship between the MPC8240 internal peripheral logic s sys_logic_cik and the CPU internal clock The CPU bus clock is skewed with respect to the peripheral logic s sys_ ogic_clk resulting in the MPC82
3. PCMWB buffers are empty and A PCI master does a multiple beat write which starts at an address within the last 4 bytes of a 4K block and The MPC8240 claims the PCI write transaction and after the address phase the assertion of IRDY by the master occurs after the first assertion of the MPC8240 TRDY then The MPC8240 does a disconnect on the PCI bus by design due to the 4K boundary but internally because of an errata in the logic it still sends out a write request to the internal buffers causing data corruption Note that if the starting address is not within the last word of a 4K block or if IRDY asserts at the same time as TRDY or before TRDY the problem does not occur Projected Impact System hangs or data corruption can occur Work Arounds Software should not issue multiple beat PCI writes to an address that starts within the last 4 bytes of a 4K boundary Projected Solution Fixed in Rev 1 2 D MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 11 Non compliant IEEE 1149 1 boundary scan Overview The MPC8240 BSDL scan chain does not comply with IEEE 1149 1 specifications Detailed Description Twelve signals are not included on the BSDL scan chain They are MIV PCI_CLK 0 3 PCI_SYNC_OUT PCI_CLK4 DA3 SDRAM_SYNC_OUT SDRAM_CLK 0 3 In addition the LVpp and OVpp power pins are not on the
4. BSDL Projected Impact Twelve out of 220 functional pins are not supported on the BSDL scan chain therefore JTAG interface cannot interconnect test gt 5 of the pins SDRAM interface testing capability may be impacted since SDRAM_CLK pins are affected by this errata Work Arounds Add a functional test to board level testing for verification of the clock outs MIV is used as a prototype bring up feature and most likely not used for production Projected Solution IEEE 1149 1 non compliance documented in BSDL file MPC8240 RIC MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 12 GNT 0 has double output valid delay Overview GNT 0 has double output valid delay when the on chip PCI arbiter is disabled Detailed Description When the on chip PCI arbiter is disabled GNT 0 will function as the bus request from the MPC87240 to the external PCI arbiter in order to get ownership of the PCI bus However due to the existence of a logic error there is a double output valid delay for this output signal This is caused by the logic having twice as many delay elements as required between the latch and the output pin Note these additional delay elements are controlled by the PCI_LHOLD_DELAY 0 2 bits bits 6 4 of the PMC Register 2 lt 0x72 gt Projected Impact Systems using an external PCI arbiter may encounter a GNT 0 sign
5. Table 3 Summary of Silicon Errata and Applicable Revision Silicon Revision No Problem Description Impact Work Around 1 1 1 11 1 2 1 3 1 PClI streaming PCI master issues a lock write that System hangs Software should not use PCI Y crosses cache boundary see PCI Local lock writes transaction or do Bus Specification Rev 2 1 for not issue transactions to the establishing lock transaction If PCI MC8240 that cross 4K logic has already written up to the cache boundary line boundary and the MPC8240 write Fixed in Rev 1 1 C buffers are still available for the next cache line the PCI logic will attempt to stream the next cache line into memory However for lock writes the MPC8240 as the target will disconnect at the cache line boundary that is no crossing allowed effectively ending the PCI transaction Since the PCI logic has issued request to write the next cache line into memory the MPC8240 write buffers will wait forever for the write data 2 CPU instruction The TLBISYNC signal to the MPC8240 System will hang when executing a Fixed in Rev 1 1 C Ye SSS execution stops after internal processor is always asserted __ tlbsync instruction Software should use a sync execution of tlbsync which indicates that CPU instruction rather than a tlbsyne instruction execution should stop after execution of instruction a tlbsync instruction Fixed in Rev 1 1 C
6. Upon seeing the fetch from the MCP exception handler the MPC8240 should then negate the MCP signal However if the address OxFFF00200 is used while ROM is located in PCI memory space RCSO 0 during reset this read operation will not negate the MCP signal opcode fetch from location OxFFF00200 if PCI ROM is used exception handler can perform a dummy read from 0x00000200 in order to negate the MCP signal Ou A0JONPUODIWIVS B ePIS9014 W09 3 29S901j MMM 0 09 yonpojdg SI L UG UOI EWOJU BAOW 104 eyeiy diyo 10SS3901d pa ei6a uU OPZ8OdIN Table 3 Summary of Silicon Errata and Applicable Revision continued Silicon Revision No Problem Description Impact Work Around 1 1 1 11 1 2 1 3 9 DLL_RESET bit must be The DLL_RESET bit bit 5 of the Address DLL clocks not guaranteed to System software boot code Y Y Y toggled by system Map B Options Register AMBOR function unless this bit is toggled if must toggle the DLL_RESET software during OxEO must be toggled not performed DLL clocks may bit bit 5 of the Address Map B initialization to ensure logic O logic 1 logic 0 by the system intermittently not function resulting Options Register AMBOR DLL clock functionality software boot code during initialization in no clock outputs on the OxEO during reset start up before SDRAM clocks are guaranteed to SDRAM_CLK 0 3 or initialization function SD
7. as reserved MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 14 Data corruption when bursting from PCI Overview MPC8240 corrupts inbound data when bursting from PCI space Detailed Description The MPC8240 corrupts inbound data instructions when bursting into cache from PCI space Single beat transfers from PCI to processor will not be affected Projected Impact Users of the MPC8240 should not use bursting from PCI space Work Arounds Perform single beat transactions when reading from PCI space This can be accomplished by marking the PCI space as cache inhibited If 32 bit mode is used only single beat reads from PCI without crossing the word boundary is allowed Otherwise the access will result in a burst of 2 beats and the processor may get corrupt data Use DMA engine to move data to from PCI space to main memory then cache burst read the memory into the processor Projected Solution Fixed in Rev 1 2 D MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 15 DMA double write only last PCI beat Detailed Description For certain programmed values of the DMA s DAR Destination Address Register and DMA s BCR Byte Count Register the DMA controller will write the last beat of data out twice on the PCI bus whe
8. detect the assertion of PERR and does not report the parity error to the core via the internal mcp signal Potentially corrupt data may be propagated Work Arounds Use external logic to monitor the PERR signal and assert the NMI signal when a data parity error is detected on the last data transfer Projected Solution No plans to fix MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 25 MPC8240 does not detect assertion of MCP signal for a certain doorbell register case in the messaging unit Detailed Description The MPC8240 fails to detect the assertion of the MCP signal whether in host or agent mode when bit 31 of the Inbound Doorbell register IDBR is set even if the requirements for an MCP are met The requirements for an MCP in this special case include HIDO EMCP 1 PICRI MCP_EN 1 MSR ME 1 Set bit 31 of the IDBR while the IMIMR DMCM 0 Even if the above conditions are met an MCP does not occur as asserted long enough to be recognized by the processor Projected Impact The internal MCP signal is asserted for only one clock Since the processor requires the internal MCP signal to be held asserted for at least two clocks the MPC8240 fails to detect the assertion of MCP in this case Apart from not getting an MCP for the above description the MPC8240 does not take a machine check exception even if ena
9. during initialization to ensure DLL clock functionality Detailed Description The DLL_RESET bit bit 5 of the Address Map B Options Register AMBOR OxEO must be toggled logic O logic 1 logic 0 by the system software boot code during initialization before SDRAM clocks are guaranteed to function Projected Impact DLL clocks not guaranteed to function unless this bit is toggled if not performed DLL clocks may intermittently not function resulting in no clock outputs on the SDRAM_CLK 0 3 or SDRAM_SYNC_OUT signals and thus resulting in a system hang Work Arounds System software boot code must toggle the DLL_RESET bit bit 5 of the Address Map B Options Register AMBOR OxEO during reset start up initialization Projected Solution Document software requirement in the MPC8240 Integrated Processor User s Manual MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 10 PCI multiple beat write with starting address in the last 4 bytes of a 4K block can cause data corruption Overview PCI multiple beat write with starting address in the last 4 bytes of a 4K block can cause data corruption Detailed Description A PClI write to local memory that starts at an address within the last 4 bytes of a 4K block and writing across the 4K boundary multiple beat transaction can cause data corruption The scenario is as follows
10. have additional internal bits associated with them which specify the type of floating point number contained in the register These bits are properly set whenever the FPR is loaded It is possible however for the part to power up with the internal bits randomly set such that the FPR is interpreted as containing a denormalized number but with the mantissa containing all zeros If this random state is stored with an stfd instruction before the internal bits are corrected via a floating point load operation the part will hang while searching for a leading 1 in the mantissa The stfd instruction is the only instruction that causes this behavior Note that this problem was discovered when compiled code stored out FPRs in preparation for using them as scratch registers early in the boot sequence Projected Impact This affects all systems that use floating point operations Work Arounds When emerging from reset initialize all the FPRs that will be used The initialization value is not important Projected Solution Fixed in documentation MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 19 PCI input high voltage for MPC8240 not PCI 2 1 compliant Detailed Description MPC8240 devices do not meet the PCI Local Bus Specification Rev 2 1 minimum input high voltage Vip DC electrical characteristic specification the minimum
11. the MPC8240 write buffers are available for the next cache line crossing the 4K boundary then the logic will also attempt to stream the next cache line into memory The result is also a hang Projected Impact System hangs Work Arounds Software should not use PCI lock writes transaction or do not issue transactions to the MPC8240 that cross 4K boundary Projected Solution Fixed in Rev 1 1 C MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 2 CPU instruction execution stops after execution of tlbsync instruction Overview The system will hang upon executing a tlbsync instruction Detailed Description The TLBISYNC signal to the MPC8240 internal processor is always asserted which indicates that CPU instruction execution should stop after execution of a tlbsyne instruction Projected Impact System will hang when executing a tlbsync instruction Work Arounds Software should use a SYNC instruction rather than a tlbsync instruction Projected Solution Fixed in Rev 1 1 C MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 3 ROM three stated wait functionality in EDO FPM systems Overview ROM three stated wait functionality not working for EDO FPM systems Detailed Description When the ROM three state
12. will respond to any accesses from an not be asserted after the external PCI master address phase of any PCI transaction Fixed in Rev 1 3 E 17 DMA may execute For PCI transfers initiated by the System may hang or data For a PCI memory targetthat Y Y Y incorrect PCI last beat because of PCI transactions not involving the MPC8240 MPC8240 DMA if the DMA transfer has one more beat to be completed read or write and is waiting for the PCI bus and another PCI master is currently transferring data to another PCI target the DMA transfer for the last beat will not put out the correct cycle on the PCI bus the next time the MPC8240 is granted the bus corruption can occur can accept burst transfers without disconnecting at non cache line boundaries there are precautionary programming steps which can be taken for DMA transactions accessing PCI There is no work around for a PCI memory target which cannot handle burst transfers without disconnecting at non cache line boundaries Fixed in Rev 1 3 E Ou A0JONPUODIWIDS B P9S9014 W09 3 29S901j MMM 0 09 yonpojdg SI L UG UOI EWUOJU BAOW 104 eyeliy diyo 10SS3901d pa ei69 uU OPZ8OdIN Table 3 Summary of Silicon Errata and Applicable Revision continued Silicon Revision No Problem Description Impact Work Around 1 1 1 11 1 2 1 3 18 stfd of uninitialized FPR The 64 bit FPRs each have additio
13. 40 not being able to operate in the dual PLL bypass mode bypass mode is not a valid selection for the MPC8240 Ou AOJONPUODIWIDS B PIS9014 W09 3 29S901j MMM 0 09 yonpojg SI L UG UOI EWOJU BAW 104 eyeliy diyo 10SS3901d pa ei6a uU OPZ8DdIN Table 3 Summary of Silicon Errata and Applicable Revision continued No Problem Description Impact Work Around Silicon Revision 1 1 1 11 1 2 1 3 14 Data corruption when bursting from PCI The MPC8240 corrupts inbound data instructions when bursting into cache from PCI space Single beat transfers from PCI to processor will not be affected Users of the MPC8240 should not use bursting from PCI space Perform single beat transactions when reading from PCI space This can be accomplished by marking the PCI space as cache inhibited If 32 bit mode is used only single beat reads from PCI without crossing the word boundary is allowed Otherwise the access will result in a burst of 2 beats and the processor may get corrupt data Use DMA engine to move data to from PCI space to main memory then cache burst read the memory into the processor Fixed in Rev 1 2 D 15 DMA double write only last PCI beat For certain programmed values of the DMA s DAR Destination Address Register and DMA s BCR Byte Count Register the DMA controller will write the last beat of data out twice on th
14. 8240 is the initiator of the PCI bus transaction A parity error occurs in the last data transfer of the transaction for either single or multiple beat transactions assertion of PERR and does not report the parity error to the core via the internal mcp signal Potentially corrupt data may be propagated Ou AOJONPUODIWIDS jLIS W09 3 29S901j MMM 0 09 yonpojdg SI L UO UOI EWOJU 30N 104 e eg diyd 10SS3901d pa ei69 uU OPZ8OdIN Table 3 Summary of Silicon Errata and Applicable Revision continued No Problem Description Impact Work Around Silicon Revision 1 1 1 11 1 2 1 3 25 MPC8240 does not __ detect assertion of MCP signal for a certain doorbell register case in the messaging unit The MPC8240 fails to detect the assertion of the MCP signal whether in host or agent mode when bit 31 of the Inbound Doorbell register IDBR is set even if the requirements for an MCP are met The MPC8240 fails to detect an MCP in this case Use interrupts in the messaging unit to generate an MCP 26 PCI writes may not invalidate speculative read data This error may occur when an incoming PCI read has triggered a prefetch for the next cache line Potentially stale data may be returned for PCI reads Currently there are two work arounds 1 Insert a dummy PCI read from an unrelated memory location between the PCI write a
15. Freescale Semiconductor Inc Errata MPC8240CE Rev 5 1 2004 MPC8240 Integrated Processor Chip Errata This document details all known silicon errata for the MPC8240 The MPC8240 is a PowerPC integrated microprocessor Table 1 provides a revision history for this chip errata document Table 1 Document Revision History Rev No Significant Changes 0 2 8 Earlier releases of document 3 Added Errors 21 23 4 Added Errors 24 26 5 Deleted Error 24 duplicate of Error 18 and renumbered errors Added Error 26 Table 2 provides a cross reference to match the revision code in the processor version register to the revision level marked on the part Table 2 Revision Level to Part Marking Cross Reference MPC8240 n Processor Version Revision ID A Part Marking A Revision Register Register 1 1 B 0x00810101 0x11 1 11 C 0x00810101 0x11 1 2 D 0x00810101 0x12 1 3 E 0x00810101 0x13 Table 3 summarizes all known errata and lists the corresponding silicon revision level to which the erratum applies A Y entry indicates that the erratum applies to a specific revision level and a dash entry means that the erratum does not apply 2 eo 2 freescale semiconductor For More Information On This Product Go to www freescale com W09 3 29S901j MMM 0 09 yonpojdg SI L UO UOI EWUOJU BAW 104 e e113 diyd 10SS3901d pa e169 uU OPZ8OdIN
16. Ou AOJONPUODIWIIVS B P9S9014 W09 3 29S901j MMM 0 09 yonpojdg SI L UG UOI EWUOJU BAOW 104 e e113 diyo 10SS3901d pa e169 uU OPZ8OdIN Table 3 Summary of Silicon Errata and Applicable Revision continued Silicon Revision No Problem Description Impact Work Around 1 1 1 11 1 2 1 3 3 ROM three stated wait When the ROM three stated wait Three stated collisions on the For EDO FPM memory YIYIY Y functionality in EDO FPM counter is programmed to a non zero memory data bus for EDO FPM systems program ROM systems value for EDO FPM systems there memory systems with slow ROM three state wait counter in exists a cycle window between the Flash or Port X devices memory configuration control completion of a single beat ROM read registers to zero that is and the assertion of the three state wait disable it interval During this window the central control unit CCU can issue a DRAM transfer to the memory control unit MCU in violation of the programmed three state wait period Potentially this may result in a three stated collision on the memory data bus when the DRAM device subsequently tries to drive read data onto the bus before a slow ROM device relinquishes control of it 4 Write thru stores followed The sequence of the write thru stores The write thru store is completed Do not rely on dcebz to zero Y Y Y IY by dcbz followed by followed by snoop all to same line cache after the dcbz instr
17. PCI 2 1 input high voltage specification is 0 5 x OVpp where OVpp has a range of 3 0 3 6 V DC See Table 3 in the MPC8240 Integrated Processor Hardware Specifications Currently MPC8240 devices have a minimum input high voltage of 0 65 x OVpp Projected Impact Systems with PCI devices capable of only driving the PCI specified minimum Vy 0 5 x OVpp lt minimum V y lt 0 65 x OVpp cannot interface to the MPC8240 Work Arounds Ensure other PCI devices in the system with the MPC8240 are capable of driving minimum Vy 0 65 x OVpp Projected Solution None MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 20 Non PCl input high voltage for MPC8240 not TTL compatible Detailed Description MPC87240 devices do not meet standard TTL specification minimum input high voltage Vy DC electrical characteristic specification the minimum input high voltage specification is 2 0 V DC See Table 3 in the MPC8240 Integrated Processor Hardware Specifications Currently MPC8240 devices have a minimum input high voltage of 2 25 V Projected Impact Systems with devices capable of only driving the TTL minimum Vyy 2 0 V lt minimum V lt 2 25 V cannot interface to the MPC8240 Projected Solution None Work Arounds Ensure other devices in the system with the MPC8240 are capable of driving minimum Vin 2 2 25 V Projected Solutio
18. RAM_SYNC_OUT signals and thus resulting in a system hang 10 PCI multiple beat write PCI multiple beat write with starting System hangs or data corruption Software should not issue Y with starting address in the last 4 bytes of a 4K block can cause data corruption address in the last 4 bytes of a 4K block can cause data corruption can Occur multiple beat PCI writes to an address that starts within the last 4 bytes of a 4K boundary Fixed in Rev 1 2 D 11 Non compliant IEEE 1149 1 boundary scan Twelve signals are not included on the BSDL scan chain They are MIV PCI_CLK 0 3 PCILSYNC_OUT PCI_CLK4 DA3 SDRAM_SYNC_OUT SDRAM_CLK 0 3 In addition the LVpp and OVpp power pins are not on the BSDL Twelve out of 220 functional pins are not supported on the BSDL scan chain therefore JTAG interface cannot interconnect test gt 5 of the pins SDRAM interface testing capability may be impacted since SDRAM_CLK pins are affected by this errata Add a functional test to board level testing for verification of the clock outs MIV is used as a prototype bring up feature and most likely not used for production Ou AOJONPUODIWIDS o PIS9014 W09 3 29S901j MMM 0 09 yonpojdg SI L UG UOI EWUOJU BAOW 104 eyeliy diyo 10SS3901d pa ei6a u OPZ8OdIN Table 3 Summary of Silicon Errata and Applicable Revision continued Silicon Revision
19. al output valid timing problem output valid time gt 6 0 ns when operating the PCI bus at 66 MHz even if PCI_LHOLD_DELAY 0 2 000 to minimize the output valid time Work Arounds None Projected Solution Fixed in Rev 1 2 D MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 13 Dual PLL bypass mode not functioning Overview MPC8240 does not boot in the dual PLL bypass mode Detailed Description When PLL_CFG 0 4 is configured for 00110 the MPC8240 does not boot This configuration bypasses both the peripheral logic PLL and the CPU logic PLL and is supposed to result in the MPC8240 operating in a 1 1 1 ratio mode for PCI sys_logic_clk MEM CPU However with the CPU s PLL bypassed there is no synchronization feedback mechanism to maintain the phase relationship between the MPC8240 internal peripheral logic s sys_logic_clk and the CPU s internal clock Consequently the CPU bus clock is skewed with respect to the peripheral logic s sys_logic_clk resulting in the MPC8240 not being able to operate in the dual PLL bypass mode Projected Impact PLL_CFG 0 4 00110 dual PLL bypass mode is not a valid selection for the MPC8240 Work Arounds None Projected Solution Remove references to this PLL_CFG 0 4 mode of operation from the MPC8240 Integrated Processor Hardware Specifications Rev 0 3 and mark this setting
20. bled and bits 8 7 or 4 of the Inbound Message Interrupt Status register are set IMISR 8 7 4 1 Work Arounds Use interrupts in the messaging unit to generate an MCP Projected Solution No plans to fix MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 26 PCI writes may not invalidate speculative read data Detailed Description This error may occur when an incoming PCI read has triggered a prefetch for the next cache line This can occur when either a device issues a PCI read or a PCI memory read line command when PICR1 2 1 or issues a PCI memory read multiple command Typically if the current PCI read does not need the data from the speculative prefetch the speculative read transaction can be terminated while the internal logic is still trying to fetch the data from memory and put it into the internal PCMRB buffer During this period an incoming PCI write that hits to the same prefetching cache line will be accepted and normally the prefetched data will be tracked and invalidated after the physical read operation from memory is complete However due to the existence of this error if another incoming PCI read hits to this cache line while the prefetch is still in progress the MPC8240 will return the stale data from the prefetched read operation which occurs before the write data is flushed Note that usually the
21. cessor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 16 MPC8240 may misinterpret IDSEL during a PCI transaction that does not involve MPC8240 Overview When a PCI master is performing a transaction to some other PCI device the MPC8240 may interpret the transaction as a configuration cycle to the MPC8240 This will happen during any cycle when FRAME is asserted and C BE 3 0 is either b 1010 or b 1011 and IDSEL input to MPC8240 is asserted and AD 1 0 b 00 and AD 10 8 b 000 If the above conditions occur while the MPC8240 is the target of the transaction the MPC8240 will function as expected If the above conditions occur when the MPC8240 is not the target of the transaction the MPC8240 will assert SERR if bit 8 of the PCI Command Register lt 0x04 gt is set SERR will oscillate in this manner SERR will be driven low for two clocks and then three stated for two clocks The first occurrence of SERR asserting will be three clocks after the detected event Regardless of whether bit 8 of the PCI Command Register lt 0x04 gt is set two cycles after the detected event the MPC8240 will always assert DEVSEL for one cycle After the DEVSEL assertion the internal state machine may lose state and may not respond to any accesses from an external PCI master Projected Impact This is a problem when the MPC8240 is operating in peri
22. ct System may hang or data corruption can occur Work Arounds For a PCI memory target which can accept burst transfers without disconnecting at noncache line boundaries the following programming steps should be taken for DMA transactions accessing PCI 1 Do not program the DMA to perform only a single beat transfer MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 Do not program the SAR DAR registers to start at the last beat in a cache line and avoid programming the SAR DAR and BCR with values such that SAR DAR BCR mod 0x20 1 2 3 or 4 3 The MPC8240 PCI latency timer should be programmed to 0x48 or higher and set the DMA mode register s reserved bits 23 22 to b01 Note that there will be a DMA performance reduction when operating in this mode since the MPC8240 will break up the DMA transaction by transferring a single cache line at a time on the PCI bus There is no work around for a PCI memory target which cannot handle burst transfers without disconnecting at noncache line boundaries that is single beat disconnects or random disconnects Projected Solution Fixed in Rev 1 3 E MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 18 stfd of uninitialized FPR can hang part Detailed Description The 64 bit FPRs each
23. duration of the prefetched read should not take long when compared with the PCI write followed by another PCI read transaction Thus the error will not be observed However in certain cases the prefetched read may be delayed due to the memory bus being busy an extreme case is a CPU performing a burst read from an 8 bit ROM This can significantly increase the likelihood of seeing the problem Alternatively the exposure to the error is greater if the PCI write and PCI read accesses are happening very fast and are short accesses such as in memory testing algorithms where single beat writes are followed by single beat reads and then compared Projected Impact Potentially stale data may be returned for PCI reads Work Arounds Currently there are two work arounds 1 Insert a dummy PCI read from an unrelated memory location between the PCI write and the desired PCI read sequence Using this work around the prefetched read that is triggered before the PCI write will be performed before the dummy PCI read and it will be discarded immediately By the time the real PCI read comes in it will wait until the previous write has been flushed before the latest data will be returned to the PCI bus Note that the PCI write may be used to qualify the insertion of the dummy read to minimize the need for too many dummy reads 2 Turn off speculative reading by clearing PICR1 2 and prevent external PCI masters from issuing memory read multiple command
24. e PCI bus The double write may cause difficulty for FIFO like structures on the PCI bus No problem is expected for normal memory map devices on the PCI bus Software should try to avoid programming the combination of DAR and BCR if the PCI device has difficulty in receiving the double write Fixed in Rev 1 2 D Ou AOJONPUODIWIDS B eP9S9014 W09 3 29S901j MMM 0 09 yonpojdg SI L UG UOI EWUOJU BAOW 104 eyeliy diyo 10SS3901d pa ei69 uU OPZ8DdIN Table 3 Summary of Silicon Errata and Applicable Revision continued Silicon Revision No Problem Description Impact Work Around 1 1 1 11 1 2 1 3 16 MPC8240 may If certain conditions occur when the This is a problem when the In host mode we recommend Y Y Y misinterpret IDSEL during MPC8240 is not the target of a PCI MPC8240 is operating in to pulldown the IDSEL input a PCI transaction that transaction the MPC8240 will oscillate peripheral agent mode andisa on the MPC8240 In does not involve SERR Two cycles after the detected potential problem in host mode if peripheral mode external MPC8240 event the MPC8240 will always assert the IDSEL pin of the MPC8240 is logic needs to be added to DEVSEL for one cycle After the not pulled down to a logic 0 qualify the IDSEL input to the DEVSEL assertion the internal state MPC8240 in such a way machine may lose state and may not where the IDSEL input
25. e it has problem access to the PCI bus If in the last beat For DMA to PCl operations of data transfer a stop is asserted and increasing the latency value the data is transferred the MPC8240 will to a higher value 0x48 or put out the wrong address for the next more and set the DMA mode transaction The result is data corruption register s bit 23 22 to b 01 This can happen for processor to PCI Note that the DMA engine is read write or DMA read write operating with reduced PCI transactions on the PCI bus performance in this mode Fixed in Rev 1 2 D 7 Direct configuration write If Map Ais used and software tries to use Unable to perform direct method Software can use the indirect Y Y accesses to PCI device in direct configuration write to PCI devices configuration write to PCI devices method configuration write Map A the transaction will come out to the PCI in Map A access to access in Map A to bus as an I O write cycles Note that configure the PCI devices direct method configuration reads from Fixed in Rev 1 2 D PCI devices functions properly 8 Read from OxFFF00200 If the processor core detects an asserted Unable to negate MCP signal by The machine check YIYIYIY OxFFF00207 cannot negate an asserted MCP signal if PCI ROM is used MCP and this results in a machine check interrupt the MPC8240 will issue a code fetch from OxFFF00200 if MSRI IP 1 or from 0x00000200 if MSR IP 0
26. h devices capable of Ensure other devices in the YIYIYIY voltage for MPC8240 not TTL compatible TTL specification minimum input high voltage V p DC electrical characteristic specification the minimum input high voltage specification is 2 0 V DC See Table 3 in the MPC8240 Integrated Processor Hardware Specification Currently MPC8240 devices have a minimum input high voltage of 2 25 V only driving the TTL minimum Vi 2 0 V lt minimum Vip lt 2 25 V cannot interface to the MPC8240 system with the MPC8240 are capable of driving minimum V p 2 2 25 V Ou AOJONPUODIWIDS jLIS W09 3 29S901j MMM 0 09 yonpojdg SI L UG UOI EWOJU BAOW 104 eyeuy diyd 10Ss9001g pe eiba U OVZ8DdIN Table 3 Summary of Silicon Errata and Applicable Revision continued Silicon Revision No Problem Description Impact Work Around 1 1 1 11 1 2 1 3 21 Data parity errors on 60x MCP8240 fails to detect the write parity This problem occurs on the All CPU to local memory YIYIYIY bus single beat writes are errors and does not invoke a machine MPC8240 when working in ECC writes that require error not detected check error if all of the following where RMW has to be on or reporting should be burst conditions are met normal parity modes and CPU writes cacheable write back A single beat 60x write is being data gets corrupted in a single beat accesses This wo
27. hru store is completed after the dcbz instruction Work Arounds Do not rely on debz to zero cache lines in areas of memory that are marked as write thru and can be accessed via multiple logical addresses Storing of zeros could be used instead Projected Solution TBD MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 5 Broadcasting of dcbz instructions Overview The broadcasting of dcbz instructions may retry snoop accesses indefinitely Detailed Description A sequence of broadcasting debz instructions may retry snoop indefinitely Projected Impact Snoop originator may timeout and or cause the snooped transaction to never complete Work Arounds Disable the broadcasting of dcbz by marking the memory space being addressed by the dcbz instruction as not global in the BAT or PTE Projected Solution TBD MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 6 PCI latency timer expiration with target disconnect causes data corruption Overview The MPC8240 as a master is doing a read or write on the PCI bus and its latency timer expires and the MPC8240 grant is taken away the MPC8240 is forced off the PCI bus and will restart the next transaction the next time it has access to the PCI bus If in the last beat of data tra
28. n None MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 21 Data parity errors on 60x bus single beat writes are not detected Detailed Description MCP87240 fails to detect the write parity errors and does not invoke a machine check error if all of the following conditions are met e A single beat 60x write is being performed e The CPU bus has corrupted data e RMW parity mode is turned on MCCR2 RMW_Par is set e Either ECC or parity modes are enabled Projected Impact This problem occurs on the MPC8240 when working in ECC where RMW has to be on or normal parity modes and CPU data gets corrupted in a single beat 60x write transaction As a result for ECC transactions the corrupted data will be used to generate an ECC syndrome and both will be written to SDRAM without detection For normal parity mode the corrupted data is written into the SDRAM and the parity byte is recalculated for the entire line with the corrupted data and also written into SDRAM For CPU burst write transactions the problem does not occur for either ECC or parity modes Work Arounds All CPU to local memory writes that require error reporting should be burst writes cacheable write back accesses This work around cannot be implemented for transactions that involve I O devices that may not have caching capability Projected Solution N
29. n the DMA engine is programmed either in local memory to PCI memory or PCI memory to PCI memory transfer mode No data corruption occurs when this double write happens and the status register updates normally after the second beat write has completed The combination of DAR and BCR that results in the double write can be determined as follows DAR BCR mod 0x20 R where R is a number between 0x00 and Ox1F If R 0x09 0x0C 0x19 Ox1C or 0x11 0x14 then the double write occurs Example 1 DMA 42 decimal bytes from 0x0000_0000 to 0x8000_0000 R DAR BCR mod 0x20 R 0x8000_0000 0x2A mod 0x20 R 2 147 483 648d 42d mod 32d R 10d 0x0A R Ox0A which is in the range of 0x09 0x0C therefore double write of last beat to PCI will occur Example 2 DMA 50 decimal bytes from 0x0009_0000 to 0x0009_4FEO R DAR BCR mod 0x20 R 0x0009_4FEO 0x32 mod 0x20 R 610 272d 50d mod 32d R 18d 0x12 R 0x12 which is in the range of 0x11 0x14 therefore double write of last beat to PCI will occur Projected Impact The double write may cause difficulty for FIFO like structures on the PCI bus No problem is expected for normal memory map devices on the PCI bus Work Arounds Software should try to avoid programming the DAR and BCR with the combination mentioned above if the PCI device has difficulty in receiving the double write Projected Solution Fixed in Rev 1 2 D MPC8240 Integrated Pro
30. nal This affects all systems which use Upon coming out of reset Y Y Y Y can hang part internal bits associated with them which floating point operations initialize all the FPRs which specify the type of floating point number will be used the value used contained in the register These bits get for initialization is not properly set whenever the FPR is important loaded However it is possible for the Fixed in documentation part to power up with the internal bits randomly set such that storing the FPR with an stfd instruction before the internal bits are corrected via a floating point load operation will result in the device hanging 19 PCI input high voltage for MPC8240 devices do not meet PCI Systems with PCI devices capable Ensure other PCI devicesin Y Y Y Y MPC8240 not PCI Local Bus Specification Rev 2 1 of only driving the PCI specified the system with the 2 1 compliant minimum input high voltage Vip DC minimum VIH 0 5 x OVpp lt min MPC8240 are capable of electrical characteristic specification the Vi lt 0 65 x OVpp cannot driving minimum V p 2 0 65 x minimum PCI 2 1 input high voltage interface to the MPC8240 OVpp specification is 0 5 x OVpp where OVpp has a range of 3 0 3 6 V DC See Table 3 in the MPC8240 Integrated Processor Hardware Specification Currently MPC8240 devices have a minimum input high voltage of 0 65 x OVpp 20 Non PCl input high MPC8240 devices do not meet standard Systems wit
31. nd the desired PCI read sequence 2 Turn off speculative reading by clearing PICR1 2 and prevent external PCI masters from issuing memory read multiple commands uj AOJONPUODIWIIS jLIS Freescale Semiconductor Inc Error No 1 PCI streaming Overview A fix for PCI streaming write see Errata No 3 for Rev 1 0 causes PCI lock writes and writes that cross 4K boundary to hang There should be no impact for systems that do not use PCI lock write transactions to the MPC8240 or do not issue writes to the MPC8240 that cross 4K boundary Detailed Description PCI master issues a lock write that crosses cache boundary see PCI Local Bus Specification Rev 2 1 for establishing lock transaction If PCI logic has already written up to the cache line boundary and the MPC8240 write buffers are still available for the next cache line the PCI logic will attempt to stream the next cache line into memory However for lock writes the MPC8240 as the target will disconnect at the cache line boundary that is no crossing allowed effectively ending the PCI transaction Since the PCI logic has issued request to write the next cache line into memory the MPC8240 write buffers will wait forever for the write data The result is a system hang The same failure is also observed in the case of crossing 4K boundary PCI writes The MPC87240 as a target will issue disconnect at the 4K boundary that is no crossing allowed If
32. nsfer a stop is asserted and the data is transferred the MPC8240 will put out the wrong address for the next transaction The result is data corruption This can happen for processor to PCI read write or DMA read write transactions on the PCI bus Detailed Description The sequence of operation is as followed 1 The MPC8240 starts a transaction on the PCI bus and the MPC8240 s grant is taken away The MPC87240 s latency timer expires and the MPC8240 still has more data to transfer 2 The MPC8240 has to terminate the current transaction by deasserting FRAME IRDY is still asserted 3 The target asserts STOP and TRDY for the last beat Note that STOP is asserted only when FRAME is deasserted and continues for one PCI cycle Data is transferred during this time 4 The MPC8240 finishes the current transaction and waits for the arbiter to grant the bus again 5 Once grant is given to the MPC8240 the MPC8240 resumes the previously terminated transaction but the address is incorrect Projected Impact Data corruption can occur Work Arounds For processor to PCI transactions increasing the latency value to a higher value 0x48 or more will solve the data corruption problem For DMA operations involving PCI increasing the latency value to a higher value 0x48 or more and set the DMA Mode Register s bit 23 22 to b 01 Note that the DMA engine is operating with reduced PCI performance in this mode See Table 4 E
33. o plans to fix MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 22 Type 2 fast back to back transactions result in data corruption Detailed Description Type 2 fast back to back transactions are those that access multiple targets sequentially If a PCI master issues a type 2 fast back to back transaction to the MPC8240 the transaction results in data corruption This is the case for both read and write transactions Data that is read will be corrupted Write transactions will write to incorrect locations or write bad data to a specified location Projected Impact Type 2 fast back to back transactions are not supported on the MPC8240 Work Arounds Software should disable the ability to run fast back to back transactions on PCI master devices that can issue fast back to back transactions to the MPC8240 This can be done by clearing bit 9 of the PCI Command Register in the master device Projected Solution No plans to fix MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 23 Enabling the detection of PCI SERR does not work Detailed Description Enabling bit 6 of the Error Enabling Register 2 OxC4 should report SERR assertions that occur on the PCI bus at any time regardless of whether the MPC8240 is the initiator the
34. pheral agent mode and is a potential problem in host mode if the IDSEL pin of the MPC8240 is not pulled down to a logic 0 Work Arounds In host mode we recommend to pulldown the IDSEL input on the MPC8240 In general this is an acceptable solution for host mode operation as PCI configuration cycles are normally issued by the host controller In peripheral mode external logic needs to be added to qualify the IDSEL input to the MPC8240 in such a way where the IDSEL input will not be asserted after the address phase of any PCI transaction See Figure 1 This may introduce a timing problem as FRAME and IDSEL are involved in order to generate the qualified IDSEL signal to the MPC8240 during the cycle when FRAME transitions from logic 1 to logic 0 See Figure 2 Projected Solution Fixed in Rev 1 3 E MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FRAME MPC8240 D FF _IDSEL_QUALIFIED E IDSEL PCI_SYNC_IN N IDSEL From PCI Figure 1 IDSEL Qualifying Logic 15 ns for 66 MHz PCI 5 30 ns for 33 MHz PCI OVpp 2 PCI_SYNC_IN 6 ns margin for clock skew time 3 ns for of flight and logic s lt 66 MHz gate propagation PCI gt 6 ns for 66 MHz PCI IDSEL_QUALIFIED IDSEL ADx 66 MHz 12 ns margin for clock skew time 7 ns for of fligh
35. purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part e of freescale semiconductor MPC8240CE For More Information On This Product Go to www freescale com
36. rk around performed 60x write transaction cannot be implemented for The CPU bus has corrupted data transactions that involve I O e RMW parity mode is turned on devices that may not have MCCR2 RMW_Par is set caching capability e Either ECC or parity modes are enabled 22 Type 2 fast back to back If a PCI master issues a type 2 fast Type 2 fast back to back Software should disable the YIYIYIY transactions result in data back to back transaction to the transactions are not supported on ability to run fast corruption MPC8240 the transaction results in data the MPC8240 back to back transactions on corruption This is the case for both read PCI master devices that can and write transactions issue fast back to back transactions to the MPC8240 23 Enabling the detection of Setting bit 6 of the Error Enabling SERR assertions that occur by an None YIYIYIY PCI SERR does not work Register 2 0xC4 does not report SERR external PCI agent are not reported assertions that occur on the PCI bus at by the MPC8240 any time regardless of whether the MPC8240 is the initiator the target or a non participating agent 24 MPC8240 does not The MPC8240 fails to detect the The MPC8240 fails to detect the None YIYIYIY detect assertion of PERR signal for a certain case assertion of the PERR signal when the following conditions are met The memory to PCI clock ratio is 2 1 or higher for example 2 1 3 1 and 4 1 The MPC
37. roducts There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer
38. s Projected Solution No plans to fix MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 2666 8080 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor p
39. t and logic l 33 MHz gt gate propagation PCI 11 ns for 33 MHz PCI MPC8240 specifies 3 ns for PCI Input Setup therefore there are 4 ns of additional margin for logic gate propagation time IDSEL_QUALIFIED IDSEL ADx 33 MHz Figure 2 Timing Diagram for IDSEL_QUALIFIED MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 17 DMA may execute incorrect PCI last beat because of PCI transactions not involving the MPC8240 Detailed Description For PCI transfers initiated by the MPC8240 DMA if the DMA transfer has one more beat to be completed read or write and is waiting for the PCI bus and another PCI master is currently transferring data to another PCI target the DMA transfer for the last beat will not put out the correct cycle on the PCI bus the next time the MPC8240 is granted the bus The error condition is as follows 1 The MPC8240 DMA has one more beat to transfer on the PCI bus The one more beat condition can be a result of either of the following a The DMA is only performing a single beat transfer b The DMA is currently requesting transfer of more than one beat up to a cache line and the PCI target issues a disconnect to the MPC8240 such that the next time the MPC8240 is granted the PCI bus there is only one remaining beat to transfer Note that the MPC8240 may ha
40. target or a non participating agent This does not occur on the MPC8240 which results in bit 6 of the Error Detection Register 2 OxC5 not reporting any SERR assertions that occur on the PCI bus by an external PCI agent Note that the reporting of a SERR assertion when it occurs on the PCI bus two clock cycles after the address phase of transactions where the MPC8240 is the initiator works as expected Therefore if bit 7 of the Error Enabling Register 1 ErrEnR1 0xC0 is set and the case described in the previous sentence occurs the system error is reported in bit 7 of the Error Detection Register 1 ErrDR1 0xC1 Projected Impact SERR assertions that occur by an external PCI agent are not reported by the MPC8240 Work Arounds None Projected Solution No plans to fix MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 24 MPC8240 does not detect assertion of PERR signal for a certain case Detailed Description The MPC8240 fails to detect the assertion of the PERR signal when all of the following conditions are met e The memory to PCI clock ratio is 2 1 or higher for example 2 1 3 1 and 4 1 e The MPC8240 is the initiator of the PCI bus transaction e A parity error occurs in the last data transfer of the transaction for either single or multiple beat transactions Projected Impact The MPC8240 fails to
41. uction cache lines in areas of snoop This occurs when the logical address for memory that are marked as the dcbz and the write thru store are write thru and can be different but aliased to the same physical accessed via multiple logical page addresses Storing of zeros could be used instead 5 Broadcasting of dcbz A sequence of broadcasting dcbz Snoop originator may timeout Disable the broadcasting of YIYIYIY instructions instructions may retry snoop indefinitely and or cause the snooped transaction to never complete dcbz by marking the memory space being addressed by the dcbz instruction as not global in the BAT or PTE Ou AOJONPUODIWIDS jLIS J W09 3 29S901j MMM 0 09 yonpojdg SI L UG UOI EWUOJU BAOW 104 eyeliy diyo 10SS3901d pa ei69 uU OPZ8DdIN Table 3 Summary of Silicon Errata and Applicable Revision continued Silicon Revision No Problem Description Impact Work Around 1 1 1 11 1 2 1 3 6 PCI latency timer The MPC8240 as a master is doing a Data corruption can occur For processor to PCl Y Y expiration with target read or write on the PCI bus and its transactions increasing the disconnect causes data __ latency timer expires and the MPC8240 latency value to a higher corruption grant is taken away the MPC8240 is value 0x48 or more will forced off the PCI bus and will restart the solve the data corruption next transaction the next tim
42. ve more data to transfer afterward since the size of each transfer up to a cache line depends on the DMA queue and number of bytes left to read or write Also disconnecting at a cache line boundary is acceptable 2 Another PCI master currently has mastering access on the PCI bus and transfers data to a PCI target other than the MPC8240 that is currently waiting to transfer one more beat on the PCI bus Note this errata does not occur if DMA has more than one beat waiting to be transferred when the interfering cycle occurs or if the interfering cycle is targeted toward the MPC8240 which has the pending DMA transfer 3 Then if the MPC8240 is granted the bus it will try to transfer the last data beat Because of a logic error triggered by step 2 the MPC8240 will put out the wrong cycle on the PCI bus During this incorrect transaction any all of the following may occur e C BE signals can be driven to an incorrect value 0x0 or OxF during the address and data phases e Itis possible for the logic to reread the next to last beat even though it has already read it once e The DMA status register may be incorrect that is the CB bit of the DSR is prematurely terminated and the interrupt prematurely activated if the condition occurs on the very last data beat of a DMA PCI write transfer that is the DMA will finish transferring the last beat after the CB bit is prematurely cleared and the interrupt has been activated Projected Impa
43. wait counter is programmed to a non zero value for EDO FPM systems there exists a cycle window between the completion of a single beat ROM read and the assertion of the three state wait interval During this window the central control unit CCU can issue a DRAM transfer to the memory control unit MCU in violation of the programmed three state wait period Potentially this may result in a three state collision on the memory data bus when the DRAM device subsequently tries to drive read data onto the bus before a slow ROM device relinquishes control of it Projected Impact Three stated collisions on the memory data bus for EDO FPM memory systems with slow ROM Flash or Port X devices Work Arounds For EDO FPM memory systems program ROM three state wait counter in memory configuration control registers to zero that is disable it Projected Solution TBD MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 4 Write thru stores followed by dcbz followed by snoop Overview Write thru stores followed by debz followed by snoop all to same line cache may cause incoherence Detailed Description The sequence of the write thru stores followed by snoop all to same line cache This occurs when the logical address for the debz and the write thru store are different but aliased to the same physical page Projected Impact The write t
44. xample 33 MHz PCI and 100 MHz memory system Table 4 Memory PClI DMA Transfer Measurement Platform Errata No 6 Work Around Not Implemented Errata No 6 Work Around Implemented Simulation 127 MBytes s Test Card 124 MBytes s 51 MBytes s Reference System 98 MBytes s 56 MBytes s Projected Solution Fixed in Rev 1 2 D MPC8240 Integrated Processor Chip Errata For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Error No 7 Direct configuration write accesses to PCI device in Map A Overview Cannot perform direct configuration write accesses to PCI devices if MPC8240 is configured for Map A Detailed Description A subset of the MPC8240 configuration registers are accessible from the PCI bus through the use of PCI configuration cycles using either a direct or indirect access method If Map A is used and software attempts to perform a direct method configuration write to PCI devices the transaction will come out to the PCI bus as an I O write cycle Note that direct method configuration reads from PCI devices functions properly Projected Impact Unable to perform direct method configuration write to PCI devices in Map A Work Arounds Software can use the indirect method configuration write access in Map A to configure the PCI devices Projected Solution Fixed in Rev 1 2 D MPC8240 Integrated Processor Chip Errata
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