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XPLA Designer v2.1 User`s Manual

1. 151 INCR Increment a Variable with a Specified nnne 151 1 2 10 152 LIST 6 Signals with Staite A ua 152 REI Return Prom SUbEFOHUMu iei ooi eod a eh a oo oe d les as 153 5 3SBQHe IN n la 153 SDC UCU as l 154 ct Variableto N e E DL 155 51 26 P o ei ii d EM EU 155 STAB Stability ub oLa 156 LDL b a Mc 156 Su null tii a a a Da D 157 SUB Start of a S bro tne Declaration auiu i ie al l l ba b la 157 SUNS Simulate Until the NetWork is Stable idee kam b u haapa 158 IRAC tutt hat danan aba bahalan b 159 APPENDIX B DEVICE PIN OUT CONFIGURATIONS 161 127 PLE cuu m Mf 161 PZ 303 2 PZ5032 4A PIN TOF P 162 5771775 E EPIN PEE 163 P Z5061 PZ5061 21PIN IOPPD u L e ea E eE EEEa E 164 EZ 0017270007 TINDPIEC E Un utes ate DE OAA 165 pP230604 PZ500641 97 PIN PECCO u u u u u a ada 166 PZ3064 P 75064 100 PIN BOB aaa E quE Su Fate tees
2. ada 42 1000010 42 i pi MEE MM NIMM EMEN 43 pl B D emite 44 MO T T TU 45 Ci pl UL qa 47 1055003 e 47 00000 b s 49 Generating and ASS enine CLOCKS ee aan 49 CHOOSING TOCKE OOII aT PROS CUS Ond iO r o 0 00 51 TL UAT OTA eu o o 53 S D 55 T bb 60 CHAPTER 6 SIMULATING XPLA DESIGNS 64 SIL IO DFOGOSS ae OU i d ate LK 000000 64 simulator MENUS ast u e e Ue aga 67 2 i ii T 68 605k6 xc66666606566c60c6c660t60s 0 68 68 68 Ri c n 69 550500 or n 69 FAE ESUD dan a 69 b b b 69 Us MEM MEM MM MM MM M EM 70 Aa S T m b MH 70 7 20 EM O OD ME 71 Aad VI 71 z b c r a 73 DUS D b 73 T a ai TREND 74 SV OUO AEE O D E 75 6050
3. uuu u ul o ola Ab do la 226 al daban 221 THUNDERBIRD T AIEIGHT CONTROL C 231 DENVER INTERNATIONAL AIR TRAFFIC 2 0 00 233 APPENDIX D ERROR MESSAGES 235 WARNING bb 236 EFELO o UL 237 BITTER ERROR MESSAGES AL uu b b eb eb Ci 244 I gui C O OO ER 244 Fa gil iu Oy TN T natin ty 245 1000000 E 247 COMMAND AND INTERNAL ERRORS 3 52 l b Ge b D ed ci 247 APPENDIX SOFTWARE LICENSE AGREEMENIT 248 APPENDIX Z ABOUT THIS MANUAL 249 7 Chapter 1 Introduction to XPLA Designer Welcome to the Philips XPLA Designer Manual This manual provides the information you need to use XPLA Designer to successfully design with Philips CoolRunner CPLDs The overall CPLD design process consists of five steps design definition functional simulation device fitting post layout timing simulation and programming The XPLA Designer provides the
4. RON I RI ROI I ICD 00 Status Project D SS v RPLASERSAMPLESTBIRDSTBIRD HET Screen Complete Figure 18 29 To run a simulation define the simulation run time in the Simulation Length field Then select Run in the fixed menu area Move the cursor to various times in the waveform window and verify that the logical values change as expected when different times are viewed Select a time when brake is high and notice that all the bulbs outputs are lit Do the same for the turn left and turn right signals Zoom into the waveform by double clicking the mouse near the area you wish to magnify Finally enter File Print to print the waveforms The printout should look like Figure 19 EE XPLA Sim 214 ITBIRD RE51 x He Edt View Options Anchor Help Events Create Change View Simulate Until File Signals Save Run Bus Cik Bus Value Full Screen 10000000 Status Project D SS v RSPLASERSAMPLESTBIRDSTBIRD HET Completed Loading D SS wARSPLASERARPLESTBIRDSTBIRD RES Figure 19 30 Using the Programmer If a programmer and the device are available the device may typically be programmed as follows This assumes that the programmer is connected to the PC or workstation where the jedec file resides Select Device PZ3032 Load programmer RAM with tbird yed Read programmer RAM to verify patter
5. 21 CHAPTER 5 PHDL LANGUAGE OVERVIEXMW 32 General bLangudves Mcd 32 0072010111 0 0000000 000 32 33 si ROLE RA ET M E M UM 33 200177 34 a RA SA GIES 35 PID aa Siena aie ie A apa 22 TER E o 37 GIONS cine m l 37 Logic Description SCCIVON 27 UD hO 37 Creating and Editing PHDLSo urcePile o ees vse aaa 37 SAE um 38 Editing an Ey Sis DES OI n a sa 38 3 eod r CCN O isa E 00 38 On u uya b 38 i dud I E iU ME 39 ENTE PES 39 u e 000000 00 39 39 77 RET INT MTT 39 40
6. UU S a My c RS Oe C OC VS eee eee ESE ESE ETE SEE SEE eee ee eee eee eee eee eee eee Do m o a 6166 66 6 6 616 S S Status Project D 5S wv xPLASSERAMPLESCOLRNTITB NET Refreshing Complete Figure 50 Transition Check This command allows the operator to check for signal transitions during the simulation run The results of the check can be viewed in the project status display window Figure 51 one is an example of this option s output in the project status window 81 Fl 03 Time 100000005 E List of signals without transition 0 COLUNTTT Time 10006060007 COUNTIZ NI COUNTIS_NI COUNTI4 NI COLNTIS NI COLINTA Time 100000005 COUNTS LOUNTE_NI _NI COUNTS Time lt 10000000 YCC COUNTOLG GSEN COUNTIOUNT LUL MT B STB Time 100000005 10 5 1 0 80 COUNTTO 0 562 COUNTTO_G GH Time lt 100000005 COUNTIOLG GSEN 10 2 1 H3 44 216 Time 10000 LOUNTI1 COUNTITO GC
7. Ma ah rx aat aaa aaa a Loc c aaa aaa aat Paat Paat saw aat aat aaa a Paat a a aat ee aat aat 5005 Status Project D 8 wv RSPLSSERAMPLESDEMDSDEML MET Select a Signal And Event Using The Cursor Continue selecting until all points are set then click Figure 75 Click on the OK button boxed in red to end the add events function Let s change the predefined clock so that it begins 40 state instead of the 1 state Click on the Create Clk button for additional help on this function see page 74 under Add Clk The Clock Settings window will appear Click on the Start at 0 button and then on the Accept button Now move the cursor to the word clock in the signal name row and click on it Finally click on the Done button inside the Clock Settings window You should have a waveform viewer window very similar to the one shown in Figure 76 02 FEB XPLA Sim 2 1d DEHO SCL OF x Edit View Options Drop Anchor Help Create Change View Simulate Until File Signals Events Save Run Bus Cik Full_Screen 10000000 nsec 8 1000000 12000000 13000000 2000000 15000000 6000000 7000000 18000000 3000000 p a ar Maa c
8. dst dst21 amp DRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst8 amp DRAMCSn amp MPRDn 42 MPWRn c MPRSTn dst 4511 amp DRAMCSn MPRDn amp MPWRn amp MPRSTn dst dst14 amp DRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst17 amp DRAMCSn c MPRDn amp MPWRn amp MPRSTn dst 4517 amp DRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst8 amp DRAMCSn z MPRDn 6 MPWRn z MPRSTn dst dst9 amp DRAMCSn z MPRDn amp MPWRn z MPRSTn dst 45110 amp DRAMCSn z MPRDn amp MPWRn amp MPRSTn 6 dst dst11 amp IDRAMCSn z MPRDn amp MPWRn amp MPRSTn dst dst12 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst13 amp IDRAMCSn z MPRDn amp MPWRn amp MPRSTn dst dst14 amp IDRAMCSn z MPRDn amp MPWRn amp MPRSTn dst dst15 amp IDRAMCSn z MPRDn amp MPWRn amp MPRSTn dst dst16 amp DRAMCSn z MPRDn amp MPWRn amp MPRSTn dst dst17 amp DRAMCSn z MPRDn amp MPWRn amp MPRSTn dst dst18 amp DRAMCSn amp MPRDn 6 MPWRn amp MPRSTn dst dst20 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst21 amp IDRAMCSn z MPRDn amp MPWRn 6 MPRSTn dst dst9 amp DRAMCSn amp MPRDn MPWRn amp MPRSTn dst dst12 amp DRAMCSn amp MPRDn amp MPWRn amp M
9. jShitlft 2 1 Shiftright 2 Multiptication 2 l s Unsigned division A B 2 Modulus AB POR XOR 8 Figure 21 NINININININ VIA I V PHDL File Format At a Glance Figure 22 shows an example of a PHDL design file The design 15 two 16 bit loadable bi directional enabled resetable counters Bi directional pins are used for the output and the load so that each counter can still be loaded when a 32 macrocell part is targeted The file is broken into four distinct sections the header the declarations the design description and the end Below 15 a brief description of each of these sections greater detail 15 provided later in this chapter 35 MODULE cntr2_16 title 2 16 bit up down loadable enabled resetable counters NOTE reset is load amp count_enab amp dir 5 NOTE BIDIR pins are used for the load of each counter DECLARATIONS dir pin 1 10 load pin 2 count_enab pin 44 clk pin 43 15 0 pin 4 5 6 7 8 9 11 12 13 14 16 17 18 19 20 21 istype cb15 cbOpin 41 40 39 38 37 36 34 33 32 31 29 28 27 26 25 24 istype 15 cal5 ca0 cb cb15 cb0 EQUATIONS 20 ca clk clk cb clk clk ca ar load amp count_enab amp dir 25 cb ar load amp count_enab amp dir ca oe load cb oe load 30 when load 1 then ca d ca pin cb d cb pi
10. COUNTIS D ILD amp CE amp COUNTO Q amp COUNTI Q amp COUNT2 Q amp COUNT3 Q amp COUNT4 Q amp COUNT5 Q amp COUNT6 Q amp COUNT7 Q amp COUNTS Q amp COUNT9 Q amp COUNTI0 Q amp COUNT11 Q amp COUNT12 Q 6 COUNT13 Q amp COUNT14 Q amp ICOUNT15 Q LD amp amp COUNT14 Q amp COUNTI5 Q LD amp CE amp COUNT13 Q amp COUNTI5 Q LD amp amp COUNT12 Q amp COUNTI5 Q LD amp amp COUNT11 Q amp COUNTI5 Q LD amp amp COUNT10 Q amp COUNTI5 Q LD amp amp COUNT9 Q amp COUNT15 Q LD amp amp ICOUNT8 Q amp COUNTIS Q LD amp amp COUNT7 Q amp COUNTIS Q LD amp amp COUNT6 Q amp COUNT15 Q LD amp amp ICOUNTS Q amp COUNTI5 O LD amp amp COUNT4 Q amp 5 0 LD amp amp COUNT3 Q amp COUNTI5 O LD amp amp COUNT2 Q amp COUNTIS Q LD amp amp ICOUNTI Q amp COUNTIS Q LD amp amp COUNT0 Q amp COUNT15 Q LD amp CE amp 15 LD amp D15 Figure 87 Figure 88 gives the fitting report when the Activate D T Register Synthesis option is not selected 104 ET PLA Designer Viewer COUNT16 LO0G Fil Clipboard Search Options Fitting Program 1 88 Input file count1 pla Initialization Suthesize logic Place and Route gt FATAL ERROR 3236 S
11. 1 Refreshing Complete Figure 49 80 fee XPLA Sim 2 1d COUNT16 5CL OF x Edit View Optons Drop Anchor Help File Signals Events Create Change View Simulate Until Bus Clk Bus Value Full Screen 10000000 nsec EE a a a s s a s a a s s a s a X Cow xo NM pot Pop a yop CCR OR s 05 a a a s a s a a MM a a a s a s x sa a a a xL CR A IO HCC A ICR MESES EERE REE EEE EEE REE EERE ERE ERE EE ee xxx R R AE p e nu nu S uu T Tu Due M I C CD I D EE C pr a aaa s cec ce c Lc c c ce c Lc C a a c c c c ce ce ce I OC ID De ett
12. Mah aaa noat noat aom noat c noat Capat noat c e ce c Lc s 5055 r a r 56005 nx al aaa ale a et alus runun 55 Status Project D S5 wv RSPLSSERAMPLESDEMDSDEML MET Refreshing Complete Figure 76 Now click on the run button The simulator will take the binary design file combine it with the signal level and timing information contained in the SCL file and present it in graphical form to the waveform viewer window You will now have a functionally simulated design displayed in the waveform viewer window like the one in Figure 77 FEB XPLA Sim 2 1d DEHO RES 2 OF x Edt View Options Drop Anchor Help Events File Signals Create Change View Simulate Until Save ae Bus 10000000 ngec Status Project D 58 wv RSPLSSERAMPLESDEMDSDEML MET Completed Loading D sSwARKPLASERAMPLESDERMU SDEM RES Figure 77 93 To return the edit mode click the OK button located near the upper left portion of the waveform viewer window The waveform viewer window will revert to a screen similar to the one shown in Figure 78 FE XPLA Sim 2 14 DEMO SCL Edi
13. Memory mapped I O address decoder Module p9 Memory mapped I O address decoder 3 reps This is simular to Prep 9 Inputs CLK RST AS pin A15 A14 A13 A12 A11 A10 A9 A8 pin A7 A6 A5 A4 A3 A2 A1 A0 pin Outputs A B C D E F G H BE istype buffer reg d 1 1 LA2 1 A3 1 4 1 A5_1 A6_1 A7_1 AS_1 node istype buffer reg 2 1 2 A2 2 A3 2 4 2 A5 2 6 2 7 2 AS 2 node istype buffer reg DECODE 1 0 1 41 LA2 LA3 1 4 LAS LAG LAT 1 INP A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 INPI A15 A14 A13 A12 A11 A10 A9 A8 A7_1 Q A6_1 Q A5_1 Q A4_1 Q A3_1 Q A2_1 Q 1 0 1 0 INP2 15 14 13 412 11 10 9 8 7 2 6 2 5 2 4 2 2 0 2 2 0 2 0 2 0 Equations A B C D E F G H BE CLK CLK A B C D E F G H BE AR RST AO_1 A1_1 A2_1 A3_1 A4_1 A5_1 A6_1 A7_1 AS_1 CLK CLK AO_1 A1_1 A2_1 A3_1 A4_1 A5_1 A6_1 A7_1 AS_1 AR RST 0 2 1 2 2 2 2 4 2 A5_2 A6_2 A7_2 AS_2 CLK CLK 0 2 1 2 2 2 2 4 2 5 2 6 2 7 2 5 2 AR RST A0_1 D amp 15 amp A14 amp A13 amp 12 A1_1 D AS amp 15 amp 14 amp A13 4 1 12 amp All A2_1 D AS amp A15 amp A14 amp A13 1A12 amp amp AIO A3_1 D AS amp 15 amp A14 amp A13 amp AI2 amp A10 amp A9 amp AS A4_1 D AS amp 15 amp A14 amp A13 amp 1
14. Module _8bshift adder addr4b bcd7 bidirect comps cntl6_d cntr2 16 demo gcnt16 4 2 p ps Crc8s dec38 dr dram_ctl ml6_8 m41 2 pl p3 p 9 parity refresh tbird traffic 1 Electronic Directory xpla examples 8bshift xpla examples adders adder xpla examples adders adder8 xpla examples adders adder8_d xpla examples adders addr4b xpla examples bcd xpla examples bidirect xpla examples comp8 xpla examples counters cnt16_d xpla examples counters cntr2_16 xpla examples counters demo xpla examples counters gcnt_d xpla examples counters gray4 xpla examples counters p2 xpla examples counters p7 xpla examples counters p8 xpla examples crc8s xpla examples dec38 xpla examples dr8 xpla examples dram_ctl xpla examples m16_8 xpla examples m41_2 xpla examples p1 xpla examples p3 xpla examples p5 xpla examples p6 xpla examples p9 xpla examples parity xpla examples refresh xpla examples tbird xpla examples traffic 1 Module Title 8 Bit Shift Register N Bit Adder 8 Bit Adder High Level 8 Bit Adder Low Level 4 Bit Adder w Carry In and Out BCD to 7 Segment Decoder Bidirectional Os 8 Bit Equality Comparator 16 Bit Counter Low Level Dual 16 Bit Counters 3 Bit Counter 16 Bit Gray Code Counter 4 Bit Gray Code Counter Timer Counter 16 Bit Loadable Binary Counter 16 Bit Synchronous Prescaled Counter Serial CRC Generator 3 to 8 Decoder 8 Bit L
15. 1 then 1 1 else 0 0 state 1 1 out 0 if inl 0 amp in2 0 then 0 0 else 0 1 Example 118 Multiple if then else structure Module mult ite Title Example of multiple if then else structure inl 12 pin clk pin out istype 51 52 node istype equations out c clk Sl c clk s2 c clk state_diagram s1 s2 state 0 0 out 0 if inl 0 amp 102 then 0 1 else if inl 1 amp in2 0 then 1 0 else if inl 1 amp in2 1 then 1 1 else 0 0 state 0 1 out 1 if inl 0 dc 2 0 then 0 0 else if inl 1 amp in2 0 then 1 0 else if inl 1 amp in2 1 then 1 1 else 0 1 state 1 0 out 1 if inl 0 amp 102 0 then 0 0 else if inl 0 amp in2 1 then 0 1 else if inl 1 amp in2 1 then 1 1 else 1 0 state 1 1 out 0 if inl 0 amp 2 0 then 0 0 else if inl 0 amp in2 1 then 0 1 else if inl 1 amp in2 0 then 1 0 else 1 1 end Example Nested if then else structure 119 Module nested Title Example of nested if then else statement state diagram 101102 pin clk pin out pin istype 51 52 node istype equations out c clk Sl c clk s2 c clk state_diagram s1 s2 state 0 0 state 0 1 state 1 0 state 1 1 out 0 if 101 0 the
16. 18 B3 118 JF 1223 1131GND 27 CLK2 TCK CLKO aS 83 160 25 115 IN2 20 1145 2 V Pe aa S TMS CLKI C ir 1194 8 G3 0 118 CLK3 23 Ci2 1173 155 1E3 1196 87 65 2 a 24 Vm 6 FA 1197 88 V 10143 01142 25 ci 1172 57 5 18 6 21 12 an in 26 cio ri 6 1199 9 G 22 122 an 0140 C9 110 758 E7 1200 90 68 1233 1123 AO 013 27 68 1160 s ES 120 69 234 28 116 19 1202 94 610 25 14 66 1167 0 10 1203 192 26 125 A7 16 29 65 1166 14 En 24 193 12 27 Ho fca 106 162 1208 194 1238 1126 29 32 2 NC 95 G15 ps NC TDO 170 PZ3128 PZ5128 160 Pin PQFP 1 NO 0 01193 js NC m H 23 2 114 j js NC H 24 3 13 Di5 124 183 NC 12 2 25 4 04 1223 js 1H3 26 5 N 4 1 N 14 0 6 N 14 S N 15 N pf SO we j 15 13 TDI Bid 9 19 2 21 89 3 24 19 H 28 190 1813 1190 150 129 190 FA 125 H 29 12 lis 19 6 1247 131 H8 24 13 BIO 1187 52 8 0217 9217 48 H 22 189 116 153 07 26 193 F8 1249 12 1283 14 BS 15 16 15 19 20 0113 m 15 87 14 4 105 01214 194 FIO0 21 14 24 186 183 155 Y 95
17. 45 144 amp q3 amp q2 141 6140 1915 amp 1414 amp 1q13 amp 412 amp 1411 amp 1410 amp q9 amp 198 amp q7 amp 46 q5 144 82 143 amp q2 c 101 140 lq 15 c 1414 amp 413 amp 1q12 amp 1410 amp q9 amp 148 amp 47 amp 6 q5 194 1q3 q2 amp 141 amp q0 1915 c 1414 amp 413 amp q12 amp ql1 1410 amp q9 amp 148 amp 47 amp q6 188 q5 amp 194 amp q3 q2 amp q1 140 q4 1415 4 1414 amp 1413 amp 1412 61411 8 q10 amp q9 amp q8 6147 amp 146 q5 194 amp q3 amp 192 101 6140 1915 amp 1414 amp 1413 amp 912 amp q11 amp q10 amp 199 amp 148 147 amp 140 amp 145 94 amp q3 142 amp 141 140 1915 c 1414 amp 1413 amp 912 amp q11 amp 1410 amp 199 amp 148 147 amp 140 amp 145 94 amp 43 amp q2 141 140 1915 1414 amp 413 amp 912 amp q11 amp q10 amp 199 amp 148 147 amp 140 145 amp 94 amp 1943 amp q2 82 141 140 1015 1414 amp 413 amp 912 amp q11 amp q10 amp 199 amp 148 147 82 140 amp 195 amp 44 amp 143 142 101 6140 1915 1414 amp 413 amp 912 amp q11 amp 1410 amp 199 amp 148 147 amp 140 amp 49 94 143 142 amp 141 140 1915 1414 amp 413 amp 412 amp 1411 amp q10 149 198 147 amp 46 amp 45 194 82 143 192 amp 101 am
18. Example Module end ex Title Very simple example showing use of end statement out pin istype com equations out 1 end 113 endcase Description The reserved word endcase 15 used to indicate the end of a case statement Refer to case in this chapter for more information Syntax case condition state condition state condition state condition state endcase Example Module case_ex Title Example of endcase statement 10102 pin out out2 pin istype com buffer 40 node istype state diagram q0 state 0 out 1 out2 0 case inl 0 amp 2 1 1 endcase state 1 out 0 out2 1 case inl 1 0 endcase 114 equations Description The reserved word equations is used to indicate the start of one or more logic equations It is used in the logic description section of the PHDL file Syntax equations element expression element expression when then else Note that there are two different types of assignment operators When signals are specified by including attributes in the pin or node statements of the declarations section the two different assignment types are functionally equivalent When signals are not specified with attributes and are only indicated to be pins or nodes then the different types of assignments have different effects on the design When the single equal sign assignment is used the s
19. Refreshing Complete Figure 67 88 EE XPLA Sim 2 1d BESHIFT SCL File Edit View Options Help Create Change View Simulate Until File Signals Events Save Bus Cik Bus Value Full Screen 1000000 B 100000 200000 300000 400000 500000 600000 700000 800000 0 1900000 Drop Anchor Status Project D NS RPLASERSAMPLESSBSHIFTSSBSHIFT NET Screen Complete Figure 68 e Practice Design Simulation In this section we will simulate the design that ships with XPLA Designer The name of the design is DEMO PHD From the entry screen the one that comes up when you start XPLA Designer click on the word DESIGN in the menu bar located at the top of the window A new window will pop up with the EST Design Panel Project DE following selections Delian view Help 1 New Design E E 2 Open Design 3 Exit APLA Designer V2 Figure 69 Design Panel Project bese View Help Design Clean Up Exil Figure 70 89 Click on the Open Design selection of the new window The Clean Up option can be used later to delete intermediate files created by the compiler An Open Design window will appear Use this window to select Demo phd then click on the OK button Open Design ea File name Folders d swixpla exampletdemo Ex d Cancel CA aw xpla example C3 demo
20. amp 1 0 6 1 06 A5_1 Q amp 144 1 0 amp 1 0 amp A2 L Q amp A1 1 Q amp 1 0 AS 2 0 AS_1 Q amp INPI lt HE2AB AS_1 Q amp AS 20 A D 5 2 0 4 15 amp 14 amp A13 amp 12 B D AS_2 Q amp 15 amp A14 amp A13 amp AI2 amp All C D AS 2 Q amp 15 amp A14 amp A13 amp 1A12 amp 11 amp AIO D D AS_2 Q amp 15 amp A14 amp A13 AI2 amp A11 amp AIO amp A9 amp AS E D AS_2 Q amp 15 amp A14 amp A13 amp 12 amp 11 amp A10 amp A9 amp AS amp 7 2 amp A6_2 Q F D AS_2 Q amp A15 amp A14 amp A13 amp AI2 amp AIO amp A9 amp AS amp A7 2 Q amp A6_2 Q amp A5 2 Q amp 4 2 0 G D AS 2 Q amp 15 amp A14 amp A13 amp AI2 amp amp AIO amp A9 amp AS amp A7 2 0 amp 1A6 2 0 amp A5 2 0 amp 1A4 2 0 2 Q amp A2 2 0 H D AS 2 0 amp 15 amp A14 amp A13 amp 12 amp amp AIO amp A9 amp 8 amp A7 2 Q amp 2 Q amp A5 2 0 t 1A4 2 0 2 0 amp 1A2 2 0 amp Al 2 0 amp A0 2 Q end BE D AS 2 Q amp INP2 lt HE2AB 1AS 2 0 amp BE Q 225 8 Bit Fast Parity Generator Module parity bwb Title 8 bit fast parity generator D7 D0 Pin Data to check for parity Odd Pin istype com Output of generator 5 6 node istype com intermediate parity check results x1 DOS DI Exclusive or
21. b111100 if TR then s5 state transition logic else if TL then 61 else 0 70 state s5 when BRAKE 0 then out b000110 equations else out b111110 75 if TR then s6 state transition logic else if TL then 61 else 0 state 56 90 when BRAKE 0 then out b000111 equations else out b111111 if TR then sO state transition logic else if TL then 61 85 else 0 State 57 goto 50 Illegal state recovery state transition logic 90 END 59 Notice in the design how there are only three state registers used to support the seven states of the design and how the eighth state uses a simple state transition logic statement to recover should the design inadvertently get into state s7 Also note how the states are defined in binary representations and how the state transition logic must use the if then else structure while the equations in each state must use the when then else structure Truth Table Designs can also be defined using truth tables A truth table specifies design output values as functions of other signals in a tabular form The general syntax for a truth table varies depending on the type of outputs that are used in the design For designs with combinatorial outputs the general syntax is truth table inputs gt outputs input state 1 gt output state 1 input state 2 gt output state 2 input state 3 gt output state 3
22. Burst Read Burst Read Burst Read Burst Read Write Write Write unused state istype istype istype istype istype 204 4824 h05 dst25 4h07 dst26 Ah0a dst27 hOb dst28 18 dst29 19 4830 Ahla dst31 Ahlb unused state unused state unused state unused state unused state unused state unused state unused state DRCASn DRCAS3n DRCAS2n DRCAS In DRCASOn DROUTn DRRDn DRWRn DRRDLE DRRWCLn DRRDCEn DRACKn x x Don t Care z 2 High Impedance Clock u u Undefined equations dst C IMPCLK dst OE OEn dst AP ED dst AR DRRASn C IMPCLK DRRASn OE OEn DRRASn AP 0 DRRASn AR 0 DRCASn C MPCLK DRCASn OE lOEn DRCASn AP 0 DRCASn AR 0 DROUTn C MPCLK DROUTn OE OEn DROUTn AP 0 DROUTn AR 0 IDRRASn dst 4512 amp MPRSTn dst dst3 amp MPRSTn dst 9506 amp amp STARTCYCLE amp MPRDn z MPWRn amp MPRSTn dst 9516 amp amp STARTCYCLE MPRDn amp MPVVRn amp MPRSTn dst dst7 amp DRAMCSn z MPRDn amp MPWRn z MPRSTn 205 dst dst8 amp DRAMCSn 6 MPRDn amp MPWRn amp MPRSTn dst dst9 amp DRAMCSn z MPRDn 6 MPWRn z MPRSTn dst dst10 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn amp I
23. 0 00 SA 1 0 0 1 0 01 82 SA 0 0 0 0 0 1 0 0 01 04 SB 0 0 1 0 0 20 SC 0 1 0 0 0 1 40 SD 0 0 0 1 0 0 0 08 SE 0 0 1 0 1 01 II SF 0 0 1 1 0 0 01 30 STARTI 1 0 0 01 40 START2 0 0 0 1 0 01 H L C X 1 0 Equations sreg ar sreg clk CLK sregl ar RST sregl clk CLK sreg2 ar sreg2 clk CLK state diagram sregl first instance state START 215 if h3C then SA else START state START if h3C then SA else START state START2 if h3C then SA else START state SA if inp h1F then SB else if inp h2A then SC else SAT state SAT if inp h1F then SB else if inp h2A then SC else SAT state SB if hAA then SE else SF state SC goto SD state SD goto SGI state SE goto STARTI state SF goto SG state SG goto START2 state SGI goto START2 state diagram sreg2 second instance state START if h3C then SA else START 216 state START 1 if h3C then SA else START state START2 if h3C then SA else START state SA if 1 hlF then SB else if h2A then SC else SAT state SAT if inpl hlF th
24. 0 60 0 605 Time lt 100000005 Checking signal names in lt Cireno TEMPS for validity Figure 51 Auto Save SCL on Run This command allows the operator to automatically save the most recent SCL file when the simulation is run The default for this item is enabled If it is disabled the current waveforms will not be saved and the simulation will be run using the most recently loaded SCL file Drop Anchor The Drop Anchor menu item when invoked activates the waveform viewer time measurement function See Figure 52 for an example of this invocation Select the starting point of the measurement and position your cursor just to the left of that point Click and hold down the left mouse button After a short delay several things will happen A red circular anchor mark will appear on the event you have selected 1 A red vertical red line will appear bisecting the circle and spanning the entire waveform viewer window 2 The Drop Anchor menu item will change to Raise Anchor The color of the selected signal name will change from black to red 4 A box will appear above the time ruler that contains two numbers The number in blue indicates the time in nanoseconds that separates the anchor point from the new cursor position note in Figure 53 that when you first invoke the anchor function this number is zero The number in red is the actual position on the time ruler where the cursor 15 located
25. 2 14 ECD RES Edt View Options Raie Anchor Help Events Create Change View Simulate Until File Signals Bus tik Bus Value Full Screen 10000000 nsec 4011121314 51617 819 1100111121314 Status Project D S vv RSPLASERAMPLESBCDSBCD MET Updating Bus Figure 53 Raise Anchor To delete the anchor click on the Raise Anchor item in the menu bar To select a different anchor point simply repeat the steps listed above The tool bar consist of the following items File Save Run and OK e Signals 84 e Events z e Create Bus Clk e Change Bus Value e View Full Screen Zoom Back e Simulate xxxxxxxx nsec Figure 54 depicts this arrangement Figure 55 through Figure 68 show each function in greater detail Create Change View Simulate Until File Signals Events Save Bus Cik Bus Value Full Screen 10000000 nzer Figure 54 Press the File Save button to save the current SCL file File Signals Events Create us c Buz Clk CUITE CL file rA nmnmmnnn ann Figure 55 Press the File Run button to save the current waveform stimuli to the SCL file assuming you have the autosave option on and run the simulator File Signals Events Create Save low Cik Save the curr
26. 45122 amp DRAMCSn amp BEIn dst dst2 amp MPRSTn dst dst3 amp MPRSTn amp IMPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp MPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp MPRDn amp MPVVRn z amp MPRDn amp MPVVRn amp amp MPRDn amp MPWRn amp amp MPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp IMPRDn amp MPWRn amp amp MPRDn amp MPVVRn amp amp MPRDn amp MPVVRn dst dst8 amp DRAMCSn amp amp MPRDn amp MPWRn amp 207 MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn DRRDn IMPBURSTn IMPBURSTn IMPBURSTn IMPBURSTn IMPBURSTn IMPBURSTn IMPBURSTn IMPBURSTn dst 450 amp DRAMCSn amp BEOn amp MPRDn amp MPWRn amp dst 4511 amp DRAMCSn amp BEOn amp MPRDn amp MPWRn amp dst 45112 amp DRAMCSn amp BEOn amp MPRDn amp MPWRn amp dst dst14 amp DRAMCSn amp BEOn amp MPRDn amp MPWRn amp dst 4515 amp DRAMCSn amp BEOn amp MPRDn amp MPWRn amp dst 4517 amp DRAMCSn amp BEOn amp MPRDn amp MPWRn amp dst 4518 am
27. 6 6 a s CL a s 0 0 0 0 PTT COC OCR A AER MACE AC OR AR CR Status Project Ww NRPLASERSAMPLESDERMUSDEML NET Screen Complete Figure 74 The Demo design comes with some stimuli already defined let s add another reset pulse Click on the Events button Position the up arrow cursor about 3 clocks into the simulation on the RESET signal Click the left mouse button Position the cursor a millimeter to the right of the transition you have just created and click the left mouse button again The waveform should look like the following in Figure 75 91 FEB XPLA Sim 2 19 DEHO SCL 2 OF x Edit View Options Anchor Help Create Change View Simulate Until File Signals Events Save Run xj Bus 10000000 nsec B paa a a a a s a a a 5 4 a Mg a 4 4 s a mm a a a a a a s a 4 a a sa a a s a s a sa a a s Peu OR A MM M OA AA ITO OR OR OR A OR eee Soe oo Se
28. DO amp Q0 Q CI DI amp QI Q 4 DI amp CO Q1 Q amp H L CO X LO C X Equations QOUT CLK CLk QOUT AR RST Q15 T Q15 Q Q15 Q D15 C14 Q14 T Q14 Q Q14 Q D14 C134B16 Q13 T Q13 Q Q13 Q D13 C12 Q12 T Q12 Q Q12 Q D12 C11 Q11 T Q11 Q Q11 Q D11 C10 Q10 T Q10 Q Q10 Q D10 C9 Q9 T Q9 Q Q9 Q D9 C8 Q8 T Q8 Q Q8 Q D8 C7 Q7 T Q7 Q Q7 Q D7 Q6 T Q6 Q Q6 Q D6 5 221 Q5 T 05 0 05 0 D5 C4 Q4 T Q4 Q Q4 Q D4 Q3 T Q3 Q Q3 Q D3 C2 Q2 T 02 0 Q2 Q D2 CI QI T 2 QI Q QI Q DI 00 00 0 00 0 DO 12 05 04205 D5 amp Q5 Q4 D54Q5 Q0 amp DA amp Q4 Q amp D54Q5 Q amp D44Q4 Q amp D3 amp Q3 Q Q5 0 dc D4 amp 040 DS amp D4 amp Q4 Q Q5 0 dc D4 amp D3 amp Q3 Q DS amp D4 amp D3 amp Q3 Q Q5 0 dc 4 amp D3 amp Q3 Q DS amp Q4 Q amp D3 amp Q3 Q Q7 Q amp D7 Q7 Q amp D6 amp Q6 Q D7 amp D6 amp Q6 Q B14 09 0 amp D9 Q9 Q amp D8 amp 08 0 D9 amp D8 amp Q8 Q B15 Q11 Q amp DII 11 amp DIO amp 010 0 D11 amp DIO amp Q10 Q B16 Q13 Q amp D13 13 amp DI2 amp 012 0 DI3 amp DI2 amp Q12 Q B22 Q5 Q amp D4 amp D3 DS amp D4 amp D3 Q5 Q dc Q4 Q amp DS amp Q4 Q amp D3 Q5 0 dc D4 amp
29. Incorrect program name 3201 Unrecognized argument option for preassign 3202 Unable to open input file 3203 Unrecognized switch option 3204 is required for command switch 3205 Parser reading error 3238 Unable to do pin assignment 3241 Unknown clock pin found during fuse mapping 3247 Unknown zia line found 247 Appendix E Software License Agreement 1 LICENSE Philips Semiconductors Philips hereby grants you as a Customer and Licensee a single user non exclusive license to use the enclosed Philips software program Program on a single CPU at any given point in time Philips authorizes you to make archival copies of the software for the sole purpose of backing up your software and protecting yourinvestment from loss 2 TERM AND TERMINATION This agreement is effective from the date the CDROM or diskettes are received until this agreement is terminated The unauthorized reproduction or use of the Program will immediately terminate this Agreement without notice Upon termination you are to destroy both the Program and the documentation 3 COPYRIGHT AND PROPRIETARY RIGHTS The Program is protected by both United States Copyright Law and International Treaty provisions This means that you must treat the Program just like a book with the exception of making archival copies for the sole purpose of protecting your investment from loss The Program may be used by any number of people and may be move
30. Q3 0 amp 2 amp Q1 Q amp 00 0 LOAD amp Q14 Q D14 Q13 T CE amp ILOAD amp 12 amp 11 amp 10 amp 09 0 amp 08 0 amp Q7 Q amp 06 0 amp Q5 Q amp 04 0 amp Q3 0 amp 2 amp Q1 Q amp 00 0 4 LOAD amp Q13 Q D13 12 CE amp amp Q11 Q amp 10 6 09 0 amp Q8 Q amp Q7 Q amp Q6 Q amp 5 amp 040 amp Q3 0 amp 2 amp Q1 Q amp 00 0 4 LOAD amp 012 0 D12 11 amp ILOAD amp Q10 Q amp Q9 Q amp Q8 Q amp Q7 Q amp Q6 Q amp Q5 Q amp 040 amp Q3 0 amp Q2 0 amp Q1 Q amp Q0 Q LOAD amp Q11 Q D11 195 10 CE amp amp 09 0 amp 08 0 amp Q7 Q amp 06 0 amp 05 0 amp 04 0 amp Q3 0 amp 020 amp Q1 Q amp 00 0 LOAD amp Q10 Q D10 Q9 T CE amp ILOAD amp 08 0 amp 07 0 amp 06 0 6 05 0 amp 04 0 amp 03 0 amp 02 0 amp Q1 Q amp Q0 Q LOAD 6 09 0 D9 Q8 T CE amp 6 07 0 6 Q6 Q amp 05 0 amp 04 0 6 Q3 Q amp Q2 Q amp Q1 Q amp Q0 Q LOAD amp Q8 Q D8 Q7 T CE amp ILOAD amp Q6 Q amp 05 0 amp 04 0 amp Q3 Q amp Q2 0 amp Q1 Q amp 00 0 LOAD amp Q7 Q D7 Q6 T CE amp ILOAD amp 05 0 amp 04 0 amp Q3 Q amp Q2 0 amp 1 amp Q0 Q LOAD amp Q6 Q D6 Q5 T CE amp ILOAD amp 04 0 amp Q3 Q amp 02 0 amp QI Q amp Q0 Q LOAD amp Q5 Q D5 Q4 T CE amp ILOAD amp Q3 Q amp
31. You could create a reset as a product term like A amp B amp C amp D or as a sum term like A B C D By contrast sums of products and products of sums like A B C ID Or B amp C D are not directly supported Complicated reset and preset control term equations that consist of sums of product terms must use a buried node with the keep attribute The node is assigned the sum of products control term equation and then the reset or preset 15 assigned to the node Because of the keep specification the node will not be collapsed The following 4 bit counter example illustrates how to make a reset control term that is a sum of products In this example the counter is reset whenever signal rst is high or both of the most significant counter bits are high Module cntr4bit Title 4 bit counter with sum of products reset pin pin 93 92 41 40 istype reg d buffer nl node istype keep count q3 q2 q1 q0 equations count c clk 52 nl 2 q3 q amp q2 q count ar rst nl count d count q 1 end Equations Equations are used to assign logical functions of input signals and feedback signals to the design outputs Whenever equations are used to define a design the keyword equations must be included on a line by itself before the actual equations are listed PHDL supports two kinds of assignments in the equations section they are element expression elem
32. amp 148 amp 147 amp q6 q5 194 q3 q2 amp 141 amp 140 1415 6414 amp q13 amp q12 amp q11 amp q10 amp q9 amp q8 amp 147 amp q6 q5 194 q3 q2 amp 141 amp q0 1415 amp q14 1413 amp 1412 amp 1411 amp 1410 amp q9 amp q8 amp 147 q6 q5 194 q3 q2 amp 141 amp q0 415 414 q13 amp 1412 amp q11 amp 1410 amp q9 amp q8 amp 147 amp 146 45 194 amp q3 amp q2 amp amp 140 415 c q14 amp q13 amp 412 amp 1411 amp qlO amp q9 amp q8 amp 147 42 q6 amp q5 amp q4 amp q3 amp q2 amp ql amp 140 q13 1415 amp 1414 amp 1413 amp 2412 42 1411 amp 1410 amp 149 amp q8 amp 147 amp 146 amp q5 amp g4 amp 143 amp q2 amp q1 amp q0 1915 amp 1414 amp 413 641261411 amp 1410 amp q9 amp 148 amp q7 amp 146 8 q5 amp g4 amp q3 amp q2 amp q1 6140 1915 4 1414 6413 amp q12 amp 11 4 1410 amp q9 amp q8 amp q7 amp 146 amp 1q5 amp g4 amp q3 amp q2 amp q1 6140 1915 amp q14 amp q13 amp 1412 6411 amp 1410 amp q9 amp 148 amp q7 62 146 amp 1q5 amp g4 amp 143 amp q2 amp q1 amp 140 185 1415 1414 amp q13 42 1412 1411 amp q10 amp q9 48 amp 147 amp q6 amp 45 194 43 amp 1q2 amp 141 amp q0 1415 6 914 amp 913 1412 42 10
33. enclosed between DATS DATE commands is added to the existing ones If the number of values of a data string 1s fewer than the number of signals in the ST DATA command the last mentioned value is taken for the remaining signals Example DATS 011 OCT 765 11 HEX 1A 7C4 BIN 11101 10 DATE DATS 10101 73 26 0010 DATE DATS start of data lines DATV assign Data Lines to a Variable Format DATV variable list gt variable list list of variable names separated by one comma The data of the data field 1s converted to integers and assigned to the corresponding variables The data entry indicated by the data counter is assigned to the first variable of the variable list Then the data counter 1s incremented by one 146 This process is repeated until all variables of the list have been assigned a value If there are fewer data entries in the data field than variables the list the last data value 15 assigned to the remaining variables Example DATS BIN 10 111 Data field with 2 entries DATE SDCI Set data counter to 1 default DATV VARI VAR2 VAR3 VAR4 assign values to variables VARI 2 VAR2 7 7 VAR4 7 DECV Decode a Variable Format DECV lt variable gt lt signal list gt variable list signal list list of variable names separated by one comma list of signal names separated by one comma The content of the variable is decoded when
34. file The netlist specifies the logic and gate delay behavior of the circuit while the SCL file specifies the signal waveforms applied to the inputs of the circuit 138 Figure 92 shows the simulation model for one type of element often used in netlists the NAND gate When the simulation starts the stimuli description SCL file is read checked for syntax errors and converted to an intermediate format which 15 stored on the disk The network is then loaded into the memory and simulation starts During simulation the status of all signals specified in the stimuli file print list is written to the result RES file This result file is the basis for the waveform viewer display 0 1 3 Model is a truth table and a 0 1 1 1 1 1 00 2 ay IH Or Tu Figure 92 XPLA Designer Simulator The XPLA Designer logic simulator waveform entry tool automatically converts the project netlist NET or MOD into a binary format BIN file The simulation files produced by XPLA Designer are bin net Tes SCI The BIN file is the binary netlist with timing information This file specifies the behavior of the logic in the simulator Since it is in binary format it cannot be edited or read directly The SCL file contains the input waveforms that are used in the simulation for most designs it should be edited created using the Waveform editor 139 Simulati
35. q9 amp 48 amp 147 amp 140 145 194 82 q3 amp q2 amp 41 6140 1015 c 1414 amp 1q13 amp 912 amp 411 amp q10 amp q9 amp 48 amp 147 82 140 145 amp 194 amp q3 c q2 82 141 140 1915 amp 1414 amp 1q13 amp q12 amp q11 amp q10 amp q9 amp 48 amp 147 82 140 q5 amp q4 amp 43 amp q2 46140 q0 1415 amp 1414 42 q13 amp 1412 amp 1411 amp 1410 65 q9 amp 48 amp 147 42 146 q5 q4 q3 q2 amp 141 amp q0 1915 amp 1414 amp 1q13 amp q12 amp q11 amp q10 amp q9 amp 48 amp 147 82 140 q5 194 q3 q2 141 amp q 1915 c 1414 amp q13 amp q12 amp q11 amp q10 amp q9 amp 148 amp 147 82 q6 amp 145 amp 194 82 q3 amp q2 amp ql 140 1915 amp 1414 amp 1q13 amp 912 amp q11 amp q10 amp q9 amp 48 amp 147 q6 145 amp q4 amp q3 amp q2 82 40 end 190 module gray4 count ar rst count clk clk 4 Bit Gray Code Counter title 4 6 gray code counter 93 42 41 40 pin istype count 43 401 q3 143 amp q2 amp ql amp q0 q3 amp q2 amp ql amp 140 q3 c q2 42 ql amp 40 q3 amp q2 amp q0 q3 amp q2 190 q3 amp 192 dc ql amp 140 q3 amp 192 amp ql 8240 q3 192 amp ql 440 42 143 amp 1q2 amp ql amp 90 143 amp q2 a
36. s iz 1166 4 Hs 122 54 182 1167 2 GD e s mno 1 28 107 14 5 46 19 4 M s m L T 22 5 ji j 168 PZ3128 PZ5128 100 Pin PQFP 2 4 15 D 1155 68 V 01104 135 D5 1154 160 165 202 3 2 15 6 Vo 00170 176 0 203 102 7 1153 0 167 1204 4 140 j10 2 1 58 1205 5 Y 138 Jp it 169 206 6 BIS TDI 12 D 1150 2 amp o 1B4 1 139 D0 CLK2 19 Gn 1208 7 183 1130 40 GND 1 01 73 62 29 8 B2 19 4 V 174 635 290 ___ 18 142 65 Gl4 z 9 p 17 E 0166 7 GIS TDO 22 1126 3 JE 17 76 GND 19018 1125 85 7 25 B7 14 14 JF 0119 JH 1214 1123 45 GND 78 H2 25 12185 1122 6 JE 110 H3 1216 16 i d4 4 1121 7 JE 1172 0 8 28 185 10 8 8 113 1H 29 151219 9 1174 181 H7 25 BK 68 9 JEO 0175 82 8 1221 16 017 E 16 19 1222 c4 17 4 E3 1178 4 V 18 16 JE 19 124 20 V SB 186 1H3 6 CH 14 54 F 118 1 Hi4 027 21 ci 13 JF 1182 187 1H5 1228 19 1142 55 FA 1183 8 GND 22148 14 F3 1184 189 INC CLKO 2317 14 156 FA 1185 100 2 16 19 7 F 1186 Ja Ji 24 165 18 16 9 25 4 17 158 F7 1188 9 3 116 9 8 1189 194 A15 CL
37. s2 0 x x 5 0 1 1 0 82 0 5 LIE 523 O x x gt 1 1 1 OJ 55 2 dake L Li 11 s4 0 x x 5 0 0 1 OJ 154 52 1 11 9 0E 55 O x x gt 0 1 1 l SSU j 1 x x gt 1 1 1 1 1 OJ s6 x x gt 0 1 1 1 T wets X Id Lc rl END 232 Denver International Air Traffic Controller MODULE trafficl1 TITLE Denver International Air Traffic Controller The output is not that of a conventional traffic light controller clk pin sena pin senb pin rst pin ga ya ra pin istype gb yb rb pin istype reg 53 50 node istype he 1ek x 1 0 ax count 53 50 on 1 0 off 0 11 equations gb yb rb ar rst ga ya ra ar rst gb yb rb clk clk ga ya ra clk clk s3 sO ar rst s3 sO clk clk state diagram count state 0 if sena amp senb then 0 else if sena amp senb then 4 else if sena senb then 1 state 1 goto 2 state 2 goto 3 state 3 goto 4 state 4 ga off ya on goto 5 state 5 ya off ra on 233 END rb off gb on goto 8 state 6 goto 0 state 7 goto 0 state 8 if sena senb then 8 else if sena amp senb then 12 else if Sena senb then 9 state 9 goto 10 state 10 goto 11 state 11 goto 12 state 12
38. where outputs are the output signals of the design inputs are the signals that make up the logic functions of the outputs and the input and output states specify the output values for a given set of input values For example the truth table for a 3 input and gate with inputs A B and C and output OUT would look like truth table LA B C gt OUT 10 0 gt 0 0 1 gt 0 1 OJ gt 0 J 0 1 11510 1 0 OJ gt 01 1 0 11510 1 OJ gt 01 1 1 1 gt 1 gs Designs with registered outputs have a general syntax of truth table 1nputs gt outputs input state 1 gt output state 1 input state 2 output state 2 60 input state 3 gt output state 3 where the only difference from combinatorial designs 1s the gt instead of the gt in between the inputs and outputs For designs that have both combinatorial and registered outputs the syntax is truth_table inputs gt reg outputs gt comb outputs input state 1 gt reg output state 1 gt comb output state 1 input state 2 gt reg output state 2 gt comb output state 2 input state 3 gt reg output state 31 gt comb output state 3 where outputs represent the registered design outputs and comb outputs are the combinatorial design outputs Truth tables must have parenthesis around the signal names and there must be a semicolon after each line of t
39. 0 amp 05 0 amp 04 0 amp 03 0 amp 02 0 amp 01 06 00 0 LOAD amp 014 0 014 0 13 CE amp LOAD amp O12 Q amp O11 Q amp 010 0 amp 09 0 amp 08 0 amp O7 Q amp 06 0 amp 05 0 amp 04 0 amp 03 0 amp 02 0 amp 01 06 00 0 LOAD amp O13 Q Q13 Q O12 T CE amp ILOAD amp O11 Q amp 010 0 6 09 0 amp 08 0 amp O7 Q amp 6 amp O5 Q amp 04 0 amp 03 0 amp 02 0 amp 1 amp 00 0 LOAD amp 012 0 Q12 Q 11 amp amp O10 Q amp 09 0 amp 08 0 amp 7 amp 6 amp O5 Q amp 04 0 amp 03 0 amp 02 0 amp 01 06 00 0 LOAD amp O11 Q Q11 Q 10 amp 6 09 0 amp 8 199 amp 7 amp 06 0 amp 05 0 amp 04 0 amp 03 0 amp 02 0 amp 01 06 00 Q LOAD amp O10 Q Q10 Q O9 T CE amp LOAD amp O8 Q amp O7 Q amp O6 Q amp O5 Q amp O4 Q amp O3 Q amp O2 Q amp O1 Q amp O0 Q LOAD amp O9 Q Q9 Q O8 T CE amp LOAD amp O7 Q amp O6 Q amp O5 Q amp O4 Q amp O3 Q amp O2 Q amp O1 Q amp O0 Q LOAD amp O8 Q Q8 Q O7 T CE amp LOAD amp O6 Q amp O5 Q amp O4 Q amp O3 Q amp O2 Q amp O1 Q amp O0 Q LOAD 6 07 0 Q7 Q O6 T CE amp LOAD amp O5 Q amp O4 Q amp O3 Q amp O2 Q amp O1 Q amp O0 Q LOAD amp 06 0 Q6 Q O5 T CE amp LOAD amp 04 0 amp O3 Q amp 02 0 amp O1 Q amp O0 Q LOAD amp O5 Q Q5 Q O4
40. 143 192 amp ql 62140 q7 1415 amp 1414 amp 413 amp 912 42 1411 amp 1410 amp 199 amp 148 147 46 187 amp 45 194 1q3 q2 amp 141 amp 140 1915 c 1414 1413 amp q12 amp 411 1410 amp 49 amp 148 amp 47 amp 6 amp q5 amp 44 143 amp 192 62141 62140 1015 c 1414 413 amp 412 amp 411 1410 amp 49 amp 148 amp 47 amp 6 amp 45 194 amp q3 amp q2 141 amp 140 1015 1414 amp 413 412 amp 411 62 1410 42 q9 amp 148 c 47 amp 190 45 82 194 amp 143 amp q2 amp 101 6140 1015 amp 1414 amp 413 amp 412 amp 1411 1410 amp q9 amp q8 c 47 amp 190 amp 45 194 1q3 1q2 amp 141 140 1915 c 1414 amp 413 q12 amp 1411 1410 amp 49 amp 08 amp q7 amp 146 amp q5 dc 194 1q3 q2 amp 141 140 1415 amp q14 amp 1413 1412 62 1011 amp 1910 amp 9 amp q8 q7 amp 46 amp 45 194 143 q2 amp 141 140 1015 1414 amp 1413 1912 1411 amp q10 amp q9 amp 48 amp q7 amp 190 amp 145 q4 amp 143 62 q2 141 62140 q6 q15 amp 1414 42 q13 amp q12 1411 amp 410 amp 199 amp 148 amp 147 42 146 amp 45 amp 194 82 143 q2 6141 amp 140 1915 1414 amp 1q13 amp 412 amp 1411 62 1410 amp q9 amp 198 amp 147 amp 46 q5 amp 194 143 amp q2 c 101 140 1915 1414 amp 4
41. 153 When the sequence formed by the relative time slots arrives at ETC the sequence 15 repeated A sequence is canceled if IT ST or S is specified for that particular signal Example 5 10 ETC A B 5 10 15 ETC 5 10 15125 ETC D 5 5 10 F The sequences for signals form A to D are repeated The other sequences are canceled after the last change Note During simulation the number of active sequences has a maximum limit depending on the size of the sequences SDC Set Data Counter Format SDC value value may be a constant or a variable Variables can be manipulated via the SETV or the INCR command 154 This command 15 used to reinitialize the data counter The simulator starts with the value 1 for the data counter When the counter exceeds the number of available data lines the simulation 1s terminated Example SETV Set a Variable to a Value Format variable lt sign gt value variable variable name of up to 12 characters the first being a letter sign minus sign optional If no sign is given a positive value is assumed value a positive constant or variable Examples SETV VARI 10 variable VARI set ro value 10 SETV VARI 3 variable VARI set to value 3 SETV VARI VAR2 variable VARI set to value of variable VAR2 SETV VARI VAR2 variable VARI set to negative value of variable VAR2 ST Set To Format ST s
42. 167 23128 25128 84 Pin PLCC 1 ND 30 li 15 F 2 JIN L1 5l 43 0lm B 1173 3 w 3 0219 9 14 4 A15 CLK3 0 Ci 158 F0 15 4 19 Co 9 GND 5 98 12 GND 11 F 16 6 2 0199 133 D 01148 160 2 2 17 7 G X DI 147 a FI 018 196 05 1 6 4 19 8 Jao 9 134 6112 145 62 FI5 TCK 10 4 14 te 643 G0 118 IS 93 135 p 1142101 61 12 9 Jay 2 p l142 6 1183 216 19 16 s Jia 65 14 10 8 0 137 D 10 165 G4 15 x 4 119 1 6 119 6 m 1 18 707118 jG 16 12 2 7 138 V 066 08018 16 139 17 60 507 1188 2144 11 3716 0168 GG 19 13 Vp 4 D2 15 6 10 14 BIS TDO li 114 169 60 119 p 5 4 DUCLK2 13 2 ta 2 GND 159 G 3 15 15 3 r 613 0019 18112 4 19 64 15 16 Jp E 10 711 GIS TDO 16 189 lm 140 2 t 72 GD 17 188 19 13 gt jH 17 18 1817 48 6 8 1153 8 19 GND 7 GND 733 H 19 16 107 ES 1154 200 1816 16 115 74 H 120 20 4 15 8 7 16 5 H 22 18 114 19 8 7 6 1203 1892 1003 9 0158 6 H 1204 12 10 EO H 1205 2 Jp ton 10 2 1 Je 12 8 m 2 24 4 10 4 0113 0208 25 12 i 2 Es 164 79 H 29 26 Vp 153 1210 HI 1210 cu s
43. 4 3 2 1 0 gt aout2 aout1 aout0 10 1 gt 0 0 0 10 0 1 0 gt 0 0 1 10 0 1 0 gt 0 1 0 10 0 1 0 01 gt 0 1 1 10 0 1 0 gt 1 0 0 10 1 O gt 1 0 1 L0 1 0 0 0 gt 1 1 0 1 0 0 gt 1 1 1 Create three separate encoders using the macro encode a7 a6 a5 a4 a3 a2 a1 a0 aout2 aout aoutO encode b7 b6 b5 b4 b3 b2 b1 b0 bout2 bout1 bout0 encode c7 c6 c5 c4 c3 c2 c1 c0 cout2 coutl coutO end Figure 24 4 The general syntax for creating a macro is macro name macro varl var2 var3 varN macro definition where macro_name is the name you will use to refer to the macro function macro is a reserved word indicating that you are creating a macro and varl var2 var3 varN are the signals that will be included in the macro definition The macro definition is where you design the macro Notice in the above example that there must be question marks in front of the signal names in the macro definition Also note the trailing semicolon after the closing bracket of the macro Signals Signals are identifiers that represent inputs outputs and buried nodes of the design The type of signal that an identifier becomes is determined by how it is declared Lines 9 through 14 of Figure 22 illustrate how
44. 40 882 PLA P Terms 32 B B n z PLA 5 Terms 16 B ud Figure 13 25 Designer Viewer OF E4 Clipboard Search Options tpal 6 5 ns al tpla 9 8 ns tbuf 1 5 ns tclk 8 8 ns trd 5 5 ns s n 1 cc Se H not a combinatorial pin nude Tsu 6 5 ms tpal tclk 7 0 ns telk trd thuf amm Y H not a combinatorial pin node Tsu 6 5 ms tpal tclk Tco 7 B ns trd tbuf ee H not a combinatorial pin node Tsu 6 5 ns tpal tclk 4 k 1 1 Total 151 Top 31 Bytes 5329 Figure 14 Simulate the Design To verify correct operation of the design a simulation 15 performed XPLA Designer automatically generates timing models for use with its internal simulator and may also generate models for export into third party Verilog and VHDL simulators To use the Verilog or VHDL timing models for use with an external simulator select VHDL Verilog or Both on the Generate Timing model pull down menu When the Simulate button is selected a Philips simulation model 15 created and XPLA Designer invokes the Philips simulator Figure 15 The simulator provides an interactive waveform editor for providing stimuli and viewing simulation results There are fixed menu entries at the top of the simulator user interface for providing input There is als
45. 49 amp q8 amp q7 amp 146 amp q5 amp g4 amp 143 amp q2 amp q1 6140 1915 amp 1q14 8 1413 amp g12 amp q11 amp q10 amp q9 amp q8 amp q7 amp 146 186 amp 45 194 1q3 q2 amp 141 amp q0 1015 1414 413 1412 amp 411 2410 amp q9 amp 147 amp 146 amp 45 194 143 amp 192 141 140 1015 1414 amp 1413 1412 amp 411 2410 149 198 147 190 amp 45 194 143 192 141 140 1015 c 1414 413 1412 amp q11 amp q10 199 148 147 146 amp 45 194 1q3 amp 192 141 140 1015 c 1414 413 2 amp 11 amp qlO 199 148 147 146 amp 45 194 143 amp 192 141 140 1915 1414 1413 2 62411 amp 410 62 149 148 147 140 amp 145 194 amp 143 192 amp ql 62140 99 1415 1414 amp 1413 402 amp amp 1410 4 149 4 qs amp 147 140 45 194 143 amp 192 141 140 1415 1414 1413 q12 amp 1011 1410 amp 9 amp q8 147 140 45 194 143 192 141 140 1915 1414 1413 1912 1411 1410 amp q9 amp 48 amp q7 190 amp 45 194 143 amp 192 41 140 1415 1414 1413 q12 c 1011 1410 4249 148 amp 47 140 amp 195 194 1q3 amp 192 141 140 1415 1414 1413 1412 61411 1410 amp q9 14
46. 62 FEB XPLA Sim 2 19 BCD_RES 2 OF x Edit View Options Anchor Help Create Change View Simulate Until File Signals Events Save Run xj Bus Bus Value Full_Screen 10000000 2591722 T 1000000 2000000 3000000 2000000 5000000 6000000 7000000 8000000 8000000 4011121314151617 819 11011112134 Status Project D S vv Select a Signal And Event Using The Cursor Then click Figure 52 To measure the difference between the anchor point and anywhere to the right of that point position the cursor to a new location in the waveform viewer and click the left mouse button It may be necessary to expand the scale in order to measure signal transitions occurring close to one another When you click on a location to measure Several things will happen 1 A black vertical line will appear at the location you selected spanning the entire waveform viewer window 2 The blue numbers will now indicate in nanoseconds the difference between the anchor point and the new cursor position The red numbers will indicate the new location on the time ruler where the cursor lies 4 The red and blue numbers box will follow the location black vertical line as you measure different transitions within the waveform viewer window 83 Figure 53 illustrates this delay measurement FEB XPLA Sim
47. Entries in truth table do not match with header near line lt numbers Correct the truth table in the PHDL source See p 44 45 for valid truth table syntax The record should be a format of truth table inputs gt output input state n gt output state n 5035 Number of variables in truth table do not match with header near line lt numbers Correct the truth table in the PHDL source See p 44 45 for valid truth table syntax 5040 Data of truth table are not consistent Correct the truth table in the PHDL source See p 44 45 for valid truth table syntax 5045 line lt gt Syntax error Correct PHDL syntax error 5050 Espresso Some minterm s belong to both the ON SET and DC SET Correct error in PLA file 5052 Espresso Some minterm s belong to both the ON SET and OFF SET Correct error in PLA file 5054 Espresso Some minterm s belong to both the OFF SET and DC SET Correct error in PLA file 5056 Espresso There are minterms left unspecified Correct error in PLA file 5060 Line lt number gt expected Correct error in PHDL file 5065 Line numbers Single quotation mark expected Correct error in PHDL file 5070 Line number Module name expected Correct error in PHDL file 5075 Line numbers or expected Correct error in PHDL file 5080 Line numbers Pin number or istype expected Correct error in PHDL file 5085 Line number Device or istype nam
48. List files of type Drives HDL Files phd E d hzard 2 Figure 71 You will now be back to the main XPLA Designer window The Design Panel Project line at the top of the window will now read Demo Click on the Compile button located at the bottom left side of the window The design will be compiled and the result will be in a format the simulator can use M Design Panel Project DEMO Design View Help Figure 72 Figure 73 shows the completed compilation process as indicated in the status window Simulate Figure 73 Now click on the Simulate button located at the bottom center of the Design Panel window You should see a window very similar to the one depicted in Figure 74 90 FEB XPLA Sim 2 1d DEHO SCL 2 OF x Edit View Options Drop Anchor Help Create Change View Simulate Until File Signals Events Save Run Bus Cik Full_Screen 10000000 nsec 8 1000000 2000000 3000000 3000000 5000000 6000000 17000000 8000000 3000000 sas ana sas sas sas alus moat anat aom sas Tar alas ars anat sas aret ares alus Malus alat alus Paan r A 0 0 M Mc s s a sa a sa a sa s a a a s a s EL X a a a NN xoxo x c 4 a a
49. Panel Project TBIRD R Design View Help APLA Designer V2 04 Pin preassignment Try P term per equation 7 Le Le Directory AERAMPLETTBIRD Filename TBIRD PHD EDIT 16230532 6 1 44 P v Activate register synthesis Auto Node Collapse Mode Generate Timing Model VHDL Design elect to generate SHOL and or Verilog timing odel Default iz Mone 22122 12 44 pz3D534 10 PLCC44 23054 10 Compi Figure 12 Compile the Design Prior to compilation and fitting select the compilation options As seen in Figure 12 compilation options can be selected from the main interface screen via pull down menu options and check boxes The PZ3000 PZ5000 series can support from 5 to 37 P terms macrocell There is an incremental pin to pin delay for macrocells in which the number of P terms exceeds 5 Using the pull down menu next to MAX P Terms per equation change the maximum P term per equation to 5 The user can define pin assignments in the phdl file As a compilation option the user can define the level of effort that the fitter should use to maintain the pinout assignments defined in the PHDL file The options are Try Keep and Ignore The pinout retention capability of the fitter is very high so select Keep in the menu next to Pin preassignment Click on the Compile button after setting the options to compile the
50. Q3 Q DS amp D4 amp Q3 Q Q5 Q amp Q4 Q amp Q3 Q DS amp Q4 Q amp Q3 Q B23 Q7 Q amp D6 D7 amp D6 Q7 Q amp Q6 Q D7 amp Q6 Q B24 Q9 Q amp D9 amp D8 QO Q amp Q8 Q D7 amp Q7 Q D7 Q7 Q amp D6 amp Q6 Q DII amp QII QV D114011 Q amp DI0 amp QIO0 Q D13 amp Q13 Q D13 Q13 Q amp D12 amp Q12 Q D5 Q5 Q amp D4 Q4 0 amp D3 Q3 Q D7 Q7 Q amp D6 Q6 Q D9 Q9 Q amp D8 Q8 Q 222 D9 amp Q8 Q B25 Q11 Q amp D10 D11 Q11 Q amp D10 Q10 Q D11 amp DIO Q11 Q amp 010 0 DII amp 010 0 B26 Q13 Q amp D12 D13 Q13 Q amp D12 Q12 Q 013 amp D12 013 0 amp QI2 Q D13 amp 012 0 C2 Q2 Q amp D2 Q2 Q amp DI amp QI Q D2 amp DI amp QI Q Q2 Q amp DI amp 0 amp Q0 Q D2 amp DI amp DO amp Q0 Q Q2 Q amp QI Q amp D amp D2 amp amp D amp 00 0 C5 C2 amp B22 B12 C7 C2 amp B22 amp B23 BI2 amp B23 B13 C9 C2 amp B22 amp B23 amp B24 B12 4 B23 amp B24 B13 amp B24 B14 C11 C2 amp B22 amp B23 amp B24 amp B25 B12 amp B23 amp B24 amp B25 B13 amp B24 amp B25 B14 amp B25 B15 C13 C2 amp B22 amp B23 amp B24 amp B25 amp B26 4 B12 amp B23 amp B24 amp B25 amp B26 4 B13 amp B24 amp B25 amp B26 4 B14 amp B25 amp B26 4 B15 6 B26 B16 end 223
51. T CE amp LOAD amp O3 Q amp O2 Q amp O1 Q amp O0 Q LOAD amp O4 Q Q4 Q O3 T CE amp LOAD amp O2 Q amp O1 Q amp O0 Q LOAD amp O3 Q Q3 Q 2 CE amp LOAD amp O1 Q amp O0 Q LOAD amp O2 Q Q2 Q 1 CE amp LOAD amp 00 0 LOAD amp O1 Q 01 0 O0 T CE amp LOAD LOAD amp 00 0 Q0 Q end 200 Serial CRC Generator using a 16 Bit g x x16 x12 x5 1 module 85 title serial crc generator using a 16 bit lisr g x x16 x2 x5 clk pin set pin din pin x15 x0 istype reg buffer xor crc sum x15 x0 equations din x15 xl x0 Xo xs 4 31 x5 x4 amp din amp x15 x6 X5 x x6 x8 x10 x9 x11 x16 x12 x11 amp din amp x15 x x14 x13 15 x14 crc sum clk clk crc sum ap set end 201 3 to 8 Decoder MODULE dec38 TITLE 3 to 8 decoder 12 10 pin 07 00 pin 1 12 10 o 07 00 equations 07 212 amp 11 amp 10 06 212 6211 amp 10 05 212 amp 11 amp 10 o4 c 12 amp lil amp 10 03 2 amp 11 amp 10 02 12 amp 11 10 ol 12 amp 11 amp 10 o0 H2 amp lil amp 110 end 202 8 Bit Loadable Data Register MODULE dr8 TITLE 8 bit loadable data register d7 d0 pin q7 q0 pin istype le pin clk pin rst pin
52. This command allows the operator to simulate an existing compiled design instead of the one listed under Filename in the Design Panel of XPLA Designer You may also explicitly open a functional simulation by opening the mod file created for your design or an AC timing simulation by opening the net file Save This command allows the operator to save the results of the currently defined stimuli displayed in the waveform viewer to the SCL file Save As 68 This command allows the operator to save the results of the currently defined stimuli displayed in the waveform viewer under a different SCL file name One way this command can be utilized is the saving of successive design iteration simulations or to keep multiple sets of stimuli Run This command is used to start the simulation process upon the design listed in brackets at the top of the waveform viewer window Figure 36 shows the design Count2 scl in brackets A design that has been loaded but not run will carry the suffix scl After the simulator has run the suffix will be res Print This command will print the contents of the waveform viewer screen to the printer set as default under the windows printer menu Page Setup This command allows the operator to control the orientation of the printed waveform viewer window Exit This command will terminate the waveform viewer window and take the operator back to the Design Panel window of XPLA Designer T
53. When only the brake is applied all six bulbs will light If the brake and a turn signal are applied simultaneously the turn signals function as above but all three lights on the side opposite the direction of turn will light Figure 8 To begin from the Windows Program Manager double click on the XPLA Designer icon to invoke the tool The XPLA Designer Figure 9 user interface consists of a menu bar at the top design entry options on the left hand side compilation options on the right hand side and program execution options compile simulate fit at the bottom Context sensitive help for the design entry and compilation option sections is provided just below the respective sections Move the cursor over the fixed menus and read the context zl sensitive help The menu bar consists of three entries Design View and Help Left clicking on a menu bar entry causes a pull down menu to be displayed The Design pull down menu allows the user to create a new design or edit an existing design The View pull down menu allows a variety of files to be viewed If a View file has not been generated it appears in the list as dimmed Design Panel Project TBIRD Miel X Design View Help APLA Designer V2 04 Pin preassignment Try Le Le P term per equation 7 Directory D Activate DT register synthesis Filename 5 sulu Auto Node Collapse Mode Design Generate Timing Mod
54. all of the files and sub directories in the temporary directory i e c tmp_xpla may be deleted This approach requires 25Mb of free space on your hard disk Uninstalling XPLA Designer In the event that you would like to completely remove XPLA Designer from your system do the following Delete the lt DRIVE gt XPLA directory and all its contents DRIVE is the drive where you elected to install XPLA Designer Delete any design files from any directories where you have them stored Delete the file xplayer ini from the Windows root directory 14 Chapter 3 XPLA Architecture Overview This chapter gives an overview of the XPLA H architecture implemented in the Philips CoolRunner CPLD product family The CoolRunner CPLD family combines a unique power saving design technique with a next generation architecture The CoolRunner CPLD family includes devices ranging from 32 to 128 macrocells This chapter focuses on the XPLA architecture and does not discuss the unique Fast Zero Power FZPTM design technique used to implement these devices The following sections give the CoolRunner features an explanation of the XPLA H architecture and the advantages that these architectural features provide XPLA Architecture Figure 3 gives a high level block diagram of the XPLA H architecture The XPLA architecture consist of Logic Blocks which are interconnected by a Zero power Interconnect Array ZIA The ZIA is a virtual crosspoint
55. and the pig slaughter house I don t think anything else would be related to what I m doin now When asked about family Bubba said Well me and Loretta been married for near bout 15 years Her father has let on now that we been married for sooo long how that the shotgun really wasn t loaded We got us a real nice doublewide on the east side with pink flamingos and everthing What do you do when your not working Bubba we said Bubba replied I reckon my favorite hobby 15 tryin to convert them there new fangled bucky balls into funky balls so I can use em to amplify my square dance fiddle After that I reckon it would be watchin wraslin on TV I heard people a sayin that its fake but I KNOW it AINT Reno Sanchez Reno s educational background includes a BSEE an MSEE and an Executive MBA Before coming to Philips Reno worked for a large telecommunications 250 company It was rumored that Reno left his former job because climbing telephone poles was becoming too dangerous Reno s work experience related to manual writing includes reading stories to his children and a third grade Spelling Bee contest of course he bombed out after the second round because he spelled MOM backwards In his spare time Reno continues to try his luck on the pro rodeo circuit but so far it hasn t managed to knock any sense into him Reno remains hopeful that he can use his steer wrestling techniques on difficult customers Reno also e
56. are local Jumps out of or into a subroutine are not permitted At the end of a subroutine declaration the labels are checked again Therefore illegal jumps are detected only after the subroutine has been closed The same holds for the main part of the stimuli file and the Finish keyword After reading the F keyword labels and jumps of the main part are checked and errors announced Labels must be unique with one exception the same label name can appear in a subroutine and in the main part of the stimuli file 149 IF Example LABEL ST 101 A B C SUNS GT LABELI LABEL2 ST 101 A B C SUNS GT LABEL2 IF Statement Format IF TIME lt relation gt lt ntime gt lt executable SCL statement gt lt relation gt lt or or gt lt ntime gt absolute time slot can be a constant or a variable If the condition of the IF clause is true when read the SCL statement 1s executed Note Nesting of IF statements is not allowable Example IF TIME 10000 CALL SUBTEST 1 if the actual timeslot equals 100000 the subroutine SUBTESTI is called IF TIME VARI GT If the actual timeslot equals the value of variable VARI then the program jumps to label RESETI 150 IFV Condition Check on a Variable Format IFV variable relation sign value executable SCL statement gt variable variable name of up to 12 characters the first being a let
57. conditional state transitions This structure cannot be used for equations it is only used in state diagrams Syntax if condition then state else 1f condition then state else state When a condition 15 true the state diagram will transition to the corresponding state If none of the conditions are true the state diagram will transition to the state specified after the final else statement Note that both of the else structures are optional If then can be used by itself with a single else or with multiple levels of else if statements If then else structures can also be nested Refer to the examples below Example Simple if then structure Module ifthen Title Example of simple if then structure pin pin istype s node istype equations out c clk Sl c clk 117 state diagram s1 state 0 out 0 if in 1 then 1 state 1 out 1 if in 1 then 0 Example If then else structure Module iftelse Title Example of else with if statement in state diagram inl 12 pin clk pin out istype 51 52 node istype equations out c clk Sl c clk s2 c clk state_diagram s1 s2 state 0 0 out 0 if inl 0 amp in2 1 then 0 1 else 1 0 state 0 1 out 1 if inl 1 amp in2 0 then 1 0 else 1 1 state 1 0 out 1 if inl 1 amp in2
58. d d7 d0 q 147 401 equations le amp d amp q q ar rst q clk clk END 203 Module dram_ctl Title This isa DRAM controller for R3081E Microprocessor This DRAM DRAM Controller Controller can be used to access 16 MBytes of DRAM This controller is synchronized to the R3081E to guarantee fast operation This DRAM controller uses the R3081E control signals as inputs and generated synchrozied acknowledgments back to the R3081E to terminate the DRAM access cycle Signals to control for data buffers and the multiplexing of the Row and Column addresses and also provided MPCLK MPRDn MPWRn MPRSTn MPBURSTn pin BE3n BE2n 1 BEOn pin DRAMCSn STARTCYCLE RFTIMEn OEn pin DRSMST4 DRSMST3 DRSMST2 DRSMSTI DRSMSTO pin DRRASn pin DRCAS3n DRCAS2n DRCAS In DRCASOn pin DRRDn DRWRn DRRDLE DRRWCLn DRRDCEn DRACKn pin RFSTARTn pin dst DRSMST4 DRSMST3 DRSMST2 DRSMSTI DRSMSTO dst0 00 dstl 10 452 hl2 dst3 hl6 454 hl4 dst5 h04 dst6 hOc dst hld dst Nh lic dst9 Ah le dstlO Ah0e dstll hOf dstl2 Ahlf dstl3 hl7 dst14 hl5 dstl5 hl1 45016 13 45017 h03 4518 h02 4519 h06 4520 08 4521 h09 9822 hOd dst23 hOl Refresh Refresh Refresh Refresh Refresh Refresh Idle Read Read Read Read Burst Read Burst Read Burst Read Burst Read Burst Read
59. d3 d0 pin clk pin ena pin enb pin a3 a0 b b3 b0 c c3 c0 5 d d3 d0 equations C b a clk clk ena b oe enb END 179 8 bit Equality Comparator High Level Implementation MODULE comps TITLE 8 bit equality comparator high level implementation a7 a0 pin b7 b0 pin eq pin a7 a0 b b7 b0 equations eq a b END 180 16 Bit Counter Low Level module cnt16 d This is the low level implementation of a 16 bit counter Inputs pin D15 D14 D13 D12 D11 D10 D9 D8 pin D7 D6 D5 D4 D3 D2 D1 D0 pin Outputs 215 014 013 012 011 010 09 08 pin istype buffer Q7 06 05 04 03 02 01 Q0 pin istype buffer DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 001 Equations QOUT CLK CLK QOUT AR RST Q15 T Q14 amp 013 amp 012 amp Q11 amp Q10 amp 09 amp Q8 amp Q7 amp amp Q5 amp 04 amp amp Q2 amp Q1 amp Q0 14 Q13 amp QI2 amp amp Q10 amp 09 amp Q8 amp 07 amp Q6 amp Q5 6 04 6 amp 02 amp QI amp Q0 QI3 T 12 amp amp Q10 amp 09 amp Q8 amp 07 amp Q6 amp Q5 amp 04 amp amp 02 amp QI amp QO 12 amp 010 amp Q9 amp Q8 amp 07 amp amp 6 Q4 amp am
60. dst21 amp DRAMCSn amp BE3n amp MPRDn amp MPVVRn amp MPRSTn dst ds22 dc DRAMCSn amp BE3n amp MPRDn amp MPWRn amp MPRSTn IDRCAS2n 451 dst2 amp MPRSTn dst dst3 amp MPRSTn dst 4518 amp DRAMCSn amp BE2n amp MPRDn amp MPWRn amp MPRSTn dst dst9 amp IDRAMCSn amp BE2n dz MPRDn amp MPWRn amp MPRSTn 206 MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn IDRCASIn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn MPRSTn 5 MPRSTn dst dst11 amp IDRAMCSn amp BE2n dst 4512 amp IDRAMCSn amp BE2n dst 48114 amp IDRAMCSn amp BE2n dst 4515 amp IDRAMCSn amp BE2n dst dst17 amp IDRAMCSn amp BE2n dst 48118 amp IDRAMCSn amp BE2n dst dst21 amp IDRAMCSn amp BE2n dst dst22 amp IDRAMCSn amp BE2n dst 4512 amp MPRSTn dst dst3 amp MPRSTn dst dst8 amp DRAMCSn amp BEIn dst dst9 amp DRAMCSn amp BEIn dst 45111 amp DRAMCSn amp BEln dst 4512 amp IDRAMCSn amp BEIn dst 4514 amp IDRAMCSn amp BEIn dst 4515 amp IDRAMCSn amp BEIn dst 4517 amp IDRAMCSn amp BEIn dst 4518 amp IDRAMCSn amp BEIn dst dst21 amp IDRAMCSn amp BEIn dst
61. fit the user s logic into the target device s resources The file format varies depending on the part you are using A device be selected by highlighting the chosen device in the Device pull down Menu on the XPLA Designer Interface Once the sources have been compiled and the design is functioning properly the XPLA Designer fitter can be employed by selecting the Fit Button from the XPLA Designer Interface The user can control the manner in which the fitter places the design into the device by using the following options on the XPLA Designer Interface Pin Assignments Max P term per Equation Activate D T Register Synthesis Generate Timing Model A complete description on how to control the device fitting process can be found in Chapter 7 Post Layout Simulation While the design may functionally simulate the part may not function correctly due to physical limitations For example the part will not function correctly if you are using a 100 MHz clock and there is a signal path in the part layout that takes more than 10 nanoseconds for the signal to reach the end of the path To find this type of problem early in your design you can do a second simulation that uses accurate delays from the datasheet specification of the devices to check the physical timing of the part Like the functional simulation this simulation also uses a test file that stimulates device inputs and records the outputs When fitting a design in
62. five values excluding the undefined state sma Logic state is high true state is high true r MEN state is not knovvn but either lovv or high Tri state state S High impedance or floating state impedance or floating state Logic state is between low and high indicating an unstable level Figure 31 65 EE XPLA Sim 2 1d ILEYEL3 5LL OF XI Edit View Options Anchor Help Events Create Change View Simulate Until File Signals Save Bus Cik Bus Value Full Screen 10000000 nzec 1000000 2000000 3000000 4000000 5000000 5000000 7000000 8000000 3000000 re ee a s sa s a s NN s s s uu CC IC CCC op Pat i nat Status Project DS wRPLASELIST DSNSEEVELS HET Screen Hecalc Complete Figure 32 Combining the user control of input stimuli with the data files produces waveform simulations of considerable complexity in a very short time Figure 33 represents an example of the waveform viewer output 66 FEB XPLA Sim 2 1d BCD_RES 2 OF x Edt Vi
63. gb off yb on goto 13 state 13 yb off rb on ra off ga goto 0 state 14 goto 0 state 15 ra off ya off ga on rb on yb off gb off goto 0 234 Appendix D Error Messages This appendix 15 a list of the errors and warnings provided by XPLA Designer during parsing optimizing and fitting of designs The first section provides errors related to the parsing of the source file The error message is an attempt to provide you with constructive guidance in correcting a problem If you need help in solving a problem be sure to contact Philips Applications as detailed in Chapter 1 The second section provides fitter related errors Generally errors fall into two categories design errors and file I O errors File I O errors occur when the fitter either can t open a file to read or write A fit error can be due to incorrect use of the device or not enough resources in the device for the design too many inputs outputs registers product terms etc In this appendix errors are given followed by a recommended action Errors are provided in the following format lt error type gt lt number gt lt text gt The following error types are used WARNING HTH A warning may or may not be a problem LOGICAL ERROR A design error SYNTAX ERROR A language syntax error COMMAND ERROR An error in a command line option or augument DEVICE ERROR 8 An error relate
64. generates three bursts of input in three consecutive 1000 nanosecond time periods SUB STIMULI 5 0 50 100 150 200 INI 5 0 50 200 IN2 5 0 100 200 300 400 IN3 5 1 50 IN4 END IT 0 INI IN2 IN3 INA SU TIME 1000 CALL STIMULII SU TIME 1000 CALL STIMULII SU TIMR 1000 CALL STIMULII SU TIME 1000 160 Appendix B Device Pin Out Configurations The following pages list pin and node numbers for the various package and macrocell count combinations of Philips CPLDs supported by the XPLA Device Kit PZ3032 PZ5032 44 Pin PLCC T N 123 Vo 2 IN 124 3 Y 125 1814 75 4 A1 46 127 BI2 173 20 1414 59 142 GND 1 21 1415 60 43 INO CLKO 22 GND X j44 ID 161 PZ3032 PZ5032 44 Pin TQFP 1 48 123 BO n 2 4 9 124 GND 3 Jas 150 125 B 59 4 4 GND 126 188 0169 5 6 84 127 B7 0168 6 7 52 28 6 0167 9 Vi E NI 10 40 ss 132 0164 13 AI3 8 135 B 6 14 1Al4 9 136 GND 15 1A15 160 137 TNO CLK0 16 GND 138 2 17 Y 9 18 1815 176 0 INS 19 1814 175 a V 21 1812 73 143 1A 146 22 172 144 1A2 147 162 PZ3064 PZ5064 44 Pin PLCC T N 123 W 2 124 CO CLKI 7 3 Y C 0178 A 0146 C3 0180 A 18 5 018 A 19 C 183 6 8 50 28 C7 184 A 5 29 C8
65. if RFSTARTn then rflstO else rflst13 if RFSTARTn then rflstO else rflst14 if RFSTARTn then rflstO else rflst15 goto rflstO 230 Thunderbird Tailight Control Circuit MODULE tbird TITLE thunderbird tailight control Circuit BRAKE pin TL pin TR pin CLK pin L1 L3 istype reg buffer R1 R3 pin istype reg buffer Q2 QO pin istype reg buffer out L3 L2 L1 R2 sreg Q2 Q1 QO sO 0 0 0 sl 0 0 1 s2 0 1 0 s3 0 1 1 54 1 0 0 55 1 0 1 s6 1 1 0 s7 1 1 1 equations sreg clk CLK out clk CLK state diagram sreg state sO if TL then s1 else 1f TR then s4 else 50 state sl if TL then s2 else 1f TR then s4 else 50 state s2 if TL then s3 231 else if TR then s4 else 50 State s3 if TL then sO else if TR then s4 else 50 state 54 if TR then s5 else if TL then 81 else 50 state s5 if TR then s6 else if TL then 81 else 50 state 56 if TR then sO else if TL then sl else 50 state s7 goto 50 Illegal state recovery truth table sreg fb BRAKE TR TL gt L3 L2 L R2 R3 50 0 x x 5 0 0 s0 1 OJ gt 1 1 1 1 1 1 sO 1 1 gt 10 1 1 1 s0 1 1 01 101 1 1 OJ SL 0 x x gt 0 0 1 0 0 OJ 161 1 x x gt 0 0 1 1 1 1
66. list of available signals appear on the left side of the window Highlighting a signal and clicking on the add button or double clicking on the signal name will transfer that signal to the bus elements box on the right side of the window Select the bus elements you wish to include up to a maximum of 31 If a signal is inadvertently added to the bus elements box it can be deleted by clicking on the delete button inside the window You can also cancel the entire bus operation by clicking on the cancel button When all the desired signals are added to the bus element box and the bus has a name click the done button inside the adding bus window The new bus signal will immediately be displayed above the location you selected in the signal name column A bus will be automatically made an output if any of the elements are an output or an internal node A bus element may not be another bus See Figure 41 for details Adding Bus Signals Bus Elements Add Delete Done Cancel Select a signal position Far the new bus Figure 41 Change Bus This command allows the operator to edit the bus signal elements When you click the change bus option an editing bus window will appear in the waveform viewer window Click on the bus signal in the waveform viewer window you wish to edit You may add signals to the bus or delete them from this window Note that this command does not allow you to edit the value on a bus only those elemen
67. near line numbers Correct the syntax in the PHDL file Refer to chapters 5 and 8 of this manual for correct syntax of PHDL 2340 Syntax error near line numbers Extension lt string gt is not allowed in output Correct the PHDL file by deleting the extension on the output 238 2345 File lt file gt line lt number gt unknown token Correct the PHDL file Supported tokens keywords and identifiers are provided on p 5 1 and 5 2 of this manual 2350 File lt file gt Only 1 or is allowed in pterm lt string gt is found Regenerate the PLA or BLIF to change table to a valid table 2370 Node not in PXAPIN list Contact Philips Applications 2375 Pxapin not in node list of pxainfo Contact Philips Applications 2377 Pxapin not in pin table of pxainfo Contact Philips Applications 2435 Register equation can not have COM feedback Correct the dot extension in the PHDL source See table 5 4 for a list of valid dot extensions 2437 Node equations can not have PIN feedback Correct the dot extension 1n the PHDL soure See table 5 4 for a list of valid dot extensions 2440 Register equation can not have D feedback Correct the dot extension in the PHDL source See table 5 4 for a list of valid dot extensions 2445 Equation shouldn t appear at normalization Internal Error Please contact Philips Applications 2460 Number of pin node list is not the same as number list Correct the declaration section of the
68. output enable to be active low C OUT CLK CLK connects clock to all four output registers C OUT AR RST connects reset to all four output registers EQUATIONS FOR ADDER C OUT A_IN B_IN sums and b inputs into at the clock pulse END 174 MODULE adder8 TITLE 8 Bit Adder A7 A0 7 S7 S0 CO A B SUM EQUATIONS SUM END 8 Adder High Level 0 7 0 7 01 CO S7 S0 A B PIN PIN PIN PIN 175 8 Bit Adder Low Level module adder8 low level implementation of an adder a7 a0 pin b7 b0 pin c7 cl node istype com 57 50 pin istype com out pin istype com equations 50 a0 bO 1 0 amp b0 sl al bl cl c2 al amp bl al bl s2 a2 b2 c2 c3 a2 amp b2 a2 b2 amp c2 s3 a3 b3 c3 c4 a3 amp b3 3 b3 amp c3 s4 a4 b4 c4 C5 a4 amp b4 a4 amp b4 amp c4 55 a5 b5 c5 a5 amp b5 a5 b amp c5 s6 a6 b6 C7 amp b6 b6 amp 57 a7 7 c7 c out a7 amp b7 a7 b7 amp c7 end 176 4 Bit Adder with Carry in and Carry out Module addr4b Title Four bit adder with carry in and carry out clk pin a3 a0 pin b3 b0 pin sum3 sum0 pin istype reg buffer carryin pin carryout pin istype reg buffer a 0 a3 a0 b 0 b3 b0 sum carryout
69. proceeds to the absolute time slot In case 2 above simulation starts at the actual time slot and process to actual delta time slot In case 3 above simulation starts at the actual time slot and continues until there are no more internal changes in the network Example SU TIME 1600 Assuming an actual time slot of 1000 then simulation continues to time slot 1600 Example 158 SU TIME 500 Assuming an actual time slot of 1 000 then simulation continues to time slot 1000 500 1500 Note No blanks are allowed between and delta time TRAC Transition Check Format Trac During simulation signals are checked to see if they change from O to 1 and or from 1 to 0 The result is printed on special demand The netlist is checked throughout the simulation regardless of the position of TRAC in the stimuli file Generating Clocks Let s assume you wish to make two clocks CLK1 and a second clock CLK2 which 15 at 1 2 the frequency of CLK1 The period of CLKI is 30 ns and CLK2 is 60 ns We will define CLK2 as one for 15 ns and zero for 15 ns and CLK2 as zero for 30 ns and one for 30 ns Also 1 unit 1 ns for this example Figure 95 shows the timing and Figure 96 shows the corresponding SCL file etc for 5uS Figure 95 159 S 1 15 30 ETC CLKI S 0 30 60 ETC CLK2 SU time 5000 F Figure 96 Subroutine Example As an example of subroutine usage the following SCL file
70. terms are used before all of the wide product sums have been allocated the design will not fit in the device For example consider a 32 macrocell device with 16 outputs of 10 product terms each Between the two logic blocks there are 64 PLA product terms available If the P term limit were set to 10 the fitter would first create the 20 equations with the required 10 product terms each no internal nodes because they all fall under the P term limit When it started allocating the logic the fitter would use five PAL terms and five PLA terms for each output A simple calculation shows that it would require 16 5 80 PLA product terms to do the design this way This exceeds the available 64 PLA product terms and therefore the design will not fit On the other hand if the P term limit were set to 6 the fitter would build a buried node for each output that comprised 6 of the 10 required product terms The buried node would then be combined on a second pass through the array with the remaining four product terms for the final result This limit would use all 32 of the available macrocells 107 but only 16 PLA product terms The design would now fit in the device but the maximum frequency would be reduced due to the second pass through the logic array For Philips devices it is recommended that you start your design with a P term limit of 7 This 1s the best starting point for balancing logic width and speed with device utilization The number can
71. the statement is executed The non negative value of the variable is converted into a binary number These bits are assigned to the signal list The least significant bit is assigned to the rightmost signal If necessary leading zeros are inserted This statement influences the simulation in the same way as the ST command 147 Example 1 SETV VARI 6 assign value 6 to VARI binary value 110 DECV VARI D wil result in A 0 leading zero inserted B 1 ci D 0 least significant bit Example 2 SET VAR2 11 assign value 11 to VAR2 binary value 101 1 DEC VAR2 A B will result in 1 right most signal 1 least significant bit END End of a Subroutine Declaration Format END END 15 the last statement of a subroutine The program then goes to the next statement END must not be omitted Sub test 1 Sub test 1 Ret End End Both of these examples show valid subroutine declarations 148 Finish Format F The Finish command terminates the simulation and must be the last command of a stimuli file Entries after the F command are not processed GT Goto Statement Format GT lt label gt lt label gt is a string of up to 12 alphanumeric characters the first being a letter Note Labels start in column 1 The GT statement causes a jump to the statement identified by lt label gt Labels defined within a subroutine
72. the world really is He hopes to someday take the family with him on a business trip so they too can enjoy the posh life of a Philips employee Chris moved from our petroleum division to our group about a year ago He claims he has more leisure time now that he doesn t have to work anymore double shifts as a service attendant When not at work Chris works at finishing school and races cockroaches ones from Florida are the best but it takes while to get them altitude trained he claims CAUTION Track 1 on the XPLA Designer CDROM is a Data Track Do Not Attempt to play this track on a CD Audio player Damage to your audio system may result Secret Audio Tracks courtesy of Philips FAE Mike Hummel 251
73. then be adjusted up or down depending on specific design requirements Another aspect of device fitting closely related to the trade off between speed and device utilization illustrated above is the ability to make changes late in the design without having to change the existing pinout Philips devices have excellent pinout retention characteristics due to the dedicated PAL product terms plus the extra PLA product terms through which late design changes can be routed to any of the existing macrocells 108 Chapter 8 PHDL Language Reference The following chapter provides detailed syntax and usage descriptions for all PHDL commands The commands are listed alphabetical order For each command there 15 a description a general syntax listing and an example Expressions enclosed within brackets are optional case Description The case statement is used within state diagrams to resolve state transitions based on one or more conditions Syntax case condition state condition state condition state condition state endcase Condition 1s a logical expression that when true causes the state diagram to transition to the corresponding state Example Module case ex Title Example of case statement in1 1n2 1n3 pin outl out2 pin istype com buffer 41 40 node istype state diagram 91 90 state 0 0 out 6 out2 0 case inl 1 amp 102 1 0 1 in 1 a
74. to change the value of a signal at the location in the signal waveform selected by the cursor position A values window will appear in the waveform viewer window when you EE XPLA Sim 2 14 COUNT16 SCL select the location on the waveform File Edit View Options Anchor Help you wish to edit Select the value File Signals Events Create you wish the signal to be set to by Save Hun Bus Cik X clicking the value displayed in the E Values values window Continue editing signals until you are satisfied then click OK the waveform viewer window Figure 44 Clear Status List 75 This command allows the operator to clear the status project window located at the bottom of the waveform viewer window See Figure 40 for an example of the status project box Under View there are three additional items Zoom Out Use this command to incrementally compress the waveform viewer time scale Zoom In Use this command to incrementally expand the waveform viewer time scale Full Screen Use this command to view the entire waveform viewer time scale NOTE There are three ways to Zoom in or out You can 1 Position the cursor at the spot in the waveform viewer window where you want the center of the display to be Double click with the left mouse button to zoom in The display will center on the position you selected if possible You can double click the right mouse button
75. to zoom out 2 Determine the minimum and maximum time you want to display Position the cursor in the time ruler portion of the waveform viewer window Click and hold the left mouse button at the point where you want the new time to start Drag the cursor to the point where you want the time to stop The area between the start and end points will be highlighted When you release the mouse button the time you selected will be displayed See Figure 45 for an example of this process 3 You can toggle between a zoomed and non zoomed condition by clicking on the View button in the toolbar If you are currently zoomed in the button will read Full Screen Clicking on the button will take you to a non zoomed condition When you click the button it will change to Zoom Back Clicking the button will take you back to the previous zoom condition Figure 46 and Figure 47 illustrate this function 76 EE XPLA Sim 2 1d COUNT16 5CL Edit View Options Drop Anchor Help Events Create Change View Simulate Until File Signals Save Run K Bus Value Zoom Back 10000000 nsec 1720942 1000000 1200 000000 5000000 16000000 17000000 19000000 9000000 Status Project D SS WV RPLASERAMPLESCULINTTE HET Screen Complete Figure 45 EB XPLA Sim 2 19 COUNT16 5CL Edi View Optons Drop Anchor Help Events Create Change View Simulate Until File
76. use the Global Tri State GTS feature because the pin is already assigned to another signal 246 Logical Errors 3210 Design exceeds maximum number of flip flops Your design uses a total number of registers that exceeds the maximum number the targeted device will support 3229 Invalid pin specification or attribute for pin pin number You have tried to assign an attribute or a signal to a pin that cannot support that type 1 e an output assigned to a dedicated input 3230 Pin pin name gt is not a valid clock pin You have tried to assign a clock to pin pin name and that pin will not support clocking 3231 Cannot use asynchronous clock Pin is already assigned All of the pins that can support asynchronous clocks have already been assigned to other signals so you cannot use an asynchronous clock 3232 Design exceeds maximum allowable fan in for a logic block There 1s a logic block that has more signals routed to it than the device can support 3233 Design exceeds maximum number of product terms for a logic block You have specified too many logic terms for a single logic block 3234 Design exceeds maximum number of presets resets for a logic block Only two preset reset signals are allowed per logic block 3235 Design exceeds maximum number of output enable terms for a logic block You have assigned more output enable terms in one logic block than the part will support Command and Internal Errors 3200
77. whenever the logical expression condition 1s false the state or result after the else statement will be implemented Example Else used with if statement in a state diagram Module if_else Title Example of else with if statement in state diagram 111 inl 12 pin clk pin out istype 51 52 node istype equations out c clk Sl c clk 52 clk state_diagram s1 s2 state 0 0 out 0 if 101 0 amp 1n2 1 then 0 1 else 1 0 state 0 1 out 1 if 101 1 amp in2 0 then 1 0 else 1 1 state 1 0 out 1 if 101 1 amp 2 1 then 1 1 else 0 0 state 1 1 out 0 if 101 0 amp in2 0 then 0 0 else 0 1 Example Else used with when statement equations Module when_ else Title Example of else with when statement in equations 101102 pin clk pin outl out2 pin istype equations outl c clk out2 c clk 112 when inl 1 amp 102 1 then outl 1 else out 0 when inl 0 amp in2 0 then out2 0 else out2 1 end end Description The reserved word end is required to be the last word in every PHDL module It is the counter part to the module statement Syntax module header declarations logic description end The header declarations and logic description make up the PHDL design Refer to chapter 5 for more information
78. 0 nzer ll 1000000 12000000 12000000 14000000 5000000 6000000 17000000 15000000 19000000 Signal Height Enter Desired trace height pixels Drop Anchor Help View Options Cancel Must be an integer greater than 10 and less than 80 70 a aa E Fa a a a a sa a a a a a a a a a a ccn xxx a a aas ass a a ass sas sos ass aaa aaa aaa aca ala a s a ee s s RS I A a tiM LN UC a My coc e C OC OO IC OCT V S eee eee eee ESE ESE SEE See eee eee eee eee eee eee E S Status Project O 5S 4PLA E 4MPLESCOUNT16 NET Screen Complete Figure 48 79 FB XPLA Sim 2 1d COUNT16 5CL OF x Edit View Options Drop Anchor Help File Signals Events Create Change View Simulate Until Bus Clk Bus Value Full_Screen 10000000 nsec TII 111111 l III Status Project
79. 000 12 TACK PTA TCP TG b an 12 f HIGLEY ECU 0 RRR TERT 12 CHAPTER 2 INSTALLING XPLA DESIGNER 13 Swem EROR 13 b 13 From FLOPPY DOR s pu d 14 0100 EAX PLA PENO NOT qaqa 14 CHAPTER 3 ARCHITECTURE OVERVIEVW 15 XPLA Aroma RI ORE E n dde de Dc h 15 TOS BOCKA MOCIU de 16 Ma acrocell actui nte vU aa 17 PLAST TOUT n 18 SUnplistic TMINE A 19 CIONES C1 20 CHAPTER 4 GETTING STARTED WITH XPLA DESIGNER 21 TESCO TCS CHIU Cass oa 21 o s it b m 23 COPING LIC TICS TCI m 24 000 ic 24 Sulu a Gael I GAY uu A 26 ii i iQ 27 CT SUIS pn
80. 006 r Moo esM oto tute ca eas 75 Z cr TET 76 ZOON xm cc TRIN 76 aaa q g v v7v7v7k k n mrm U 70vm1kkt Xt X41 XtXty7tXt t X Xt t v7 1 7X 7 Vv77X 76 SO NAHE ON a a 76 Tran LUON AC b b bb d bb 81 Auto SAVE SC on RIK scat a aa 82 1700700006 0006 0 M 62 505 hol a 84 Simula orn Dene 88 Prachee Des om SMULAN abba 89 4 C LBIES r ee o S C S D CHAPTER 7 CONTROLLING THE FITTING PROCESS iller ODLUONS s cites sets al Pre assignments ax P terms per equation ctivate D T register synthesis uto Node Collapse Mode itter Option Examples onstraining Pins and Nodes Example T Register Synthesis Example evice Utilization CHAPTER 8 PHDL LANGUAGE REFERENCE declarations 2177 oe are ehd equations POW if then else Istype macro module NOUS maa property eran state diagram then an when then else Wil Verses Design Speed Example APPENDIX A SCL SIMULATION CONTROL LANGUAGE heory of Operation PLA Designer Simulator imulation Contro
81. 05 04 03 Q2 01 Q0 node istype buffer reg t O15 014 013 012 011 010 09 08 istype buffer reg O7 06 05 04 03 02 01 00 istype buffer reg DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Q15 014 013 012 011 010 09 08 07 06 05 04 05 Q02 01 Q0 OOUT 015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 00 C X C Equations QOUT CLK CLK QOUT AR RST OOUT CLK CLK OOUT AR RST Q15 T CE amp amp 014 0 amp Q13 Q amp 012 0 amp 11 amp 010 0 amp 09 0 amp Q8 Q amp Q7 Q amp 06 0 amp 05 0 amp 04 0 amp Q3 0 amp 2 amp 01 06 00 0 LOAD amp Q15 Q D15 14 CE amp amp 013 0 amp 012 0 amp 11 amp 010 0 amp 09 0 amp 08 0 amp Q7 Q amp 06 0 amp 5 amp 04 0 amp Q3 0 amp 2 amp Q1 Q amp 00 0 LOAD amp Q14 Q D14 Q13 T CE amp amp 12 amp 11 amp 10 amp 09 0 amp 08 0 amp Q7 Q amp 06 0 amp 05 0 amp 04 0 amp Q3 0 amp 2 amp Q1 Q amp 00 0 LOAD amp Q13 Q D13 12 CE amp amp Q11 Q amp Q10 Q 6 09 0 amp 08 0 amp Q7 Q amp 6 amp 05 0 amp 04 0 amp Q3 0 amp 2 amp 01 06 00 0 LOAD amp Q12 0 D12 Q11 T CE amp ILOAD amp Q10 Q amp 09 0 amp Q8 Q 198 amp Q7 Q amp 06 0 6 05 0 amp 04 0 amp Q3 0 amp 02 0 amp Q1 Q amp 00 0 LOAD amp Q11 Q D11
82. 103 AI 70 138 GND 6 GND 0 4 105 8 4 0173 6 6 9 8 01 74 2 7 18 A6 0 75 4 Y 10 A7 1 76 4 68 109 u Vp ju 1A 0178 6 u m 14 8 148 GND 15 42 84 9 133 a 16 GND 115 Jaa 98 si 015 1132 18 5 4 DI4 ni B4 0199 153 o 20 1B13 0198 154 D2 19 21 V 55 DI 138 22 Bi 197 D0 0 17 23 Bu 196 156 p 16 24 10 95 157 DS 125 B9 194 8 GND 26 GND 160 106 1233 B7 19 05 12 B6 191 di D4 1121 B4 90 _ 8 _ 31 Vp B 186 IN2 165 PZ3064 PZ5064 84 Pin PLCC 129 157 C 7128 2 1013 130 89 10 5 cn 19 3 JVo 131 188 10 59 GND 4 AUCLK3 85 132 GND 6 CI3 07130 5 A1 86 33 87 1108 6 4 3 6 87 4 6 1107 6 15 1 7 GND 135 5 5 1106 6 DI5 18 8 18 136 B4 01105 64 DI4 17 9 89 37 83 1104 6 DI3 1146 10 8 190 138 V 166 V 1217 19 140 BI 1102 168 DH 0114 13 Vo 41 BOCLK2 101 169 143 14 8 193 142 GND 0 19 0142 15 9 J 143 V n D 114 16 0 95 4 CU CLK11117 72 GND 17 76 145 C 68 173 D 10 18 42 197 146 C2 19 174 106 1139 19 GND 147 GND 175 05 18 20 1A13 98 148 C3 1120 6 DA 1137 21 4 79 149 454 1121 7 D 00136 2
83. 11 42 1410 amp q9 amp q8 amp 147 amp q6 amp 45 194 1q3 q2 amp 141 140 q15 414 amp 1413 c 1412 82 1411 42 1410 4 q9 amp 48 amp 147 amp 146 45 194 1q3 1q2 amp 141 140 415 q14 amp 413 amp g12 1411 amp 910 amp q9 amp 148 147 amp 196 amp 145 194 143 62 q2 42 141 62140 412 1415 1414 1413 1412 amp 411 amp 1410 4 49 amp q8 amp 147 amp 190 amp 45 194 1q3 42 82 141 140 1415 1414 amp 1413 amp q12 amp 411 amp q10 amp q9 amp q8 amp 147 amp q6 q5 194 1q3 q2 amp 141 amp 140 1015 amp q14 amp 1413 amp 124411 amp q10 amp 149 amp 48 amp q7 amp 196 q5 194 q3 q2 amp 141 amp q0 1415 amp 1414 amp 1413 amp 912 amp q11 amp q10 amp q9 amp q8 amp 147 amp 140 q5 194 q3 q2 amp 141 amp q0 1415 1414 amp 1413 amp q12 amp 1411 amp 1410 amp q9 q8 amp 147 amp q6 q5 194 q3 q2 141 amp 140 1415 amp 1414 amp 413 amp q12 amp q11 amp q10 amp q9 amp q8 amp 147 amp 140 q5 194 1q3 q2 82 141 q0 1415 amp 914 amp 413 amp q12 amp q11 amp q10 amp q9 amp q8 amp q7 amp q6 q5 194 q3 q2 amp 141 amp 140 1915 amp q14 amp q13 amp q12 amp 1411 amp 1410 amp 199 am
84. 13 412 amp 411 amp q10 amp 149 198 147 65 46 amp q5 94 143 142 amp 141 140 1915 1414 amp 413 amp 412 amp q11 62 1410 amp 149 198 147 46 amp 195 amp 44 143 192 ql 62140 1915 1414 amp 413 412 amp 1411 amp q10 42 149 198 147 amp 46 amp 195 194 143 amp 192 141 140 1915 c 1414 413 412 amp ql1 1410 199 148 amp 47 amp 6 195 194 193 amp 192 141 140 1915 c 1414 413 412 amp ql1 1410 199 amp q8 amp 7 146 amp 45 194 1q3 amp 142 141 140 1915 1414 amp 1413 amp 1412 621411 42 1410 amp 149 amp q8 amp 47 4 46 amp 145 amp 194 amp 143 amp q2 42 ql 62140 q5 1415 42 1414 42 1413 amp 912 amp amp 1410 amp 149 amp 48 amp 147 42 146 q5 amp 44 amp q3 amp q2 141 amp 140 1915 amp 1414 amp 413 amp 912 411 amp q10 amp q9 amp 48 amp 147 amp 140 amp 49 94 q3 t 142 amp 141 140 1915 amp 1414 amp 1q13 amp 912 amp q11 amp q10 amp q9 amp 48 amp 147 82 140 q5 44 amp q3 amp q2 amp 141 amp 140 1015 amp 1414 amp 1q13 amp 912 amp 411 amp q10 amp q9 amp 148 amp 147 82 140 amp q5 194 amp q3 t q2 amp 141 amp 140 1915 amp 1414 amp q13 amp q12 amp q11 amp q10 amp q9 amp 48 amp 147 82 q6
85. 185 A C js 7 8 15 0 8 9 14 ci 0188 A0 155 o 89 8 All 56 0 GND 9 Jaz 7 31 790 190 GND 4 4 59 133 015 168 12 48 10 D 1107 B4 075 135 15 Y 7 DI 104 B 17 103 Bu 17 D 1102 16 B10 1 138 1101 B9 170 3 D7 D5 B 162 2 GND 21 BUCLK2 61 43 INO CLKO 22 GND X TN 163 PZ3064 PZ5064 44 Pin TQFP A6 jn 123 jcs 1105 A 722 C 1 8 173 CoO w A9 174 CH 1108 A0 15 Joz 1109 2 4 GND GND C4 m 19 7 1015 1128 6 45 0 1 4 1127 7 Bis 196 128 02 16 B4 95 129 8 194 130 02 15 9 Y 131 DH 114 B2 193 00 113 n 19 D 12 10 B10 91 132 D 1121 19 133 D7 10 u BS 9 106 19 B 88 D 118 B6 87 17 8 86 D 16 12 4 185 134 D2 15 13 148 D 14 14 B2 83 135 D 01113 B 82 136 GND 15 2 81 37 INUCLKO 16 GND 138 N 17 r 19 1 02 18 COCLK1 197 0 IN C 98 411 V 19 C2 79 42 AUCLKS 165 20 5 10 6 ce 11 2 3 0 68 6 13 4 0169 22 4 4 as 70 164 PZ3064 PZ5064 68 Pin PLCC 135 Y 0 2 113 16 CO CLKI 101 3 Y C 0 102 4 AOCLK3 169 137 C2 1
86. 188 882 1 0 pins 16 16 198 68 P Terms 4 B B Bg P Terms 2 1 5B 882 PAL P Terms BH 48 68 B5 PLA P Terms 32 B Bg PLA 5 Terms 16 B B Bg ET 1 1 Total 80 Top 14 Bytes 3188 Figure 90 As one can see from Figure 90 the device did fit with the Activate D T Register Synthesis selected In fact only Logic Block A was used to implement this 16 bit counter Logic Block B is still available to implement other functions Device Utilization Verses Design Speed Example One of the key settings that can most affect the fitting of your design is the Max P Term per equation selection This property determines the maximum number of product terms PLEASE NOTE Some Quantum Physics Theories Suggest That When the Consumer Is Not Directly Observing This Product It May Cease to Exist or Will Exist Only in a Vague and Undetermined State 106 that may be summed for any macrocell There is a trade off between design speed and efficiency of device utilization that must be considered when setting this property When the logic equation for a macrocell has a number of product terms that exceeds the maximum count selected buried nodes will be used to break the equation into smaller parts that will then be summed in another macrocell reducing the maximum frequency at which the design can run As an example consider the equation OUT A B C DFEHFHGHH and assume that the P ter
87. 2 amp C33 amp A2 amp C44 MAC amp Q6 Q amp C34 MAC amp Q6 Q amp A3 amp B3 C34 amp A3 amp B3 S42 33 C32 Al amp B3 S43 2 S34 C33 A2 amp B3 S44 MAC amp Q6 Q C34 A3 amp B3 Q CLK CLK Q AR RST Q0 D 6 Q0 Q 0 amp BO Q1 D S12 C11 A0 amp Bl Q2 D S22 C21 A0 amp B2 Q3 D 32 C31 A0 amp B3 Q4 D S42 C41 Q5 D 543 C42 S42 amp C41 Q6 D S44 C43 C52 Q7 D MAC amp Q7 Q C44 C53 end 220 1 Bit Accumulator module p6 bit accumulator This 18 simular to Prep 6 Inputs CLK RST D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Outputs 215 014 013 012 011 010 09 08 Q7 06 05 04 03 02 01 Q0 pin pin pin pin istype buffer pin istype buffer B12 B13 B14 B15 B16 B22 B23 B24 B25 B26 node C2C5C7C0CTLCI5S node DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 001 C14 D14 amp Q14 Q DIA amp C13 B16 Q14 Q amp C13 B16 C12 DI2 amp QI2 Q D12 amp C11 Q12 Q amp CIO DIO amp Q10 Q DIO amp C9 Q10 Q amp C9 D8 amp Q8 Q D8 amp C7 Q8 0 amp D6 amp Q6 Q amp C5 8 06 0 amp C5 D3 amp Q3 Q D3 amp C2 Q3 Q amp C2 C4 D4 amp Q4 Q DA amp C3 Q4 Q amp C3 CO
88. 2 1A15 10 150 55 12 78 V 24 Bi4 115 152 C7 14 180 DI 0 13 25 14 153 V 181 D 7133 26 54 C8 1125 82 GND 27 Bi2 3 155 9 1126 183 INO CLKO 28 Bu 112 156 01127 4 M 1 166 PZ3064 PZ5064 100 Pin PQFP q NC 135 185 1120 169 DI2 114 2 N 136 Y 7 DH 10 3 6 1107 137 B2 119 DIO 1159 4 A7 1108 38 B 68 727 N FER uM 39 BO CLK2 17 173 p 18 6 jas 40 GND 4 6 44 Vp 75 08 17 8 42 COCLKI 13 76 GND 44 C2 1135 178 p 15 45 GND 7 NC 46 1136 830 N A3 14 8 5 1138 82 DA 1153 15 1 14 1115 9 co 1139 183 D3 12 16 ais 16 0 C7 1140 84 V 01 17 1815 1132 si NC 85 D2 115 18 4 1 152 NC 086 DI 19 19 1B13 10 153 Y 97 b 19 20 V 94 68 1141 88 GND 21 2 119 155 NC 9 IN CLKO 2 1128 6 c 1142 2 23 B10 1127 7 NC Ja Mm 24 NC 158 4 9 113 25 B9 1126 9 1144 93 l 26 NC 60 Ci2 45 94 AUCLKS 101 27 B8 1125 GND 195 102 28 GND 6 CI3 1146 96 2 13 29 NC 63 Cld 1147 97 GND 30 NC 64 cs 1148 198 14 31 B7 14 165 DIS 1164 199 A4 15 32 1B6 1123 166 4 113 100 AS 16 33 1B5 112 167 DI3 162 j 34 B4 l 68 02414 10 Anm EUN Eta EUN
89. 39 ISTYPE d buffer To unlock a pin in a PHDL source remove the pin number that was specified in the declarations section D T Register Synthesis Example This example show the differences between using D and T Type flip flops This is an example of a 16 bit counter targeted for a PZ5032 which is compiled first without Activate D T Register Synthesis selected and then with Activate D T Register Synthesis selected Figure 86 gives the source code for this 16 bit counter 102 MODULE count_16 TITLE 16 bit Loadable Counter D15 D0 pin COUNTI5 COUNTO pin istype LD CE CLK RST pin COUNT COUNT15 COUNTO D D15 D0 EQUATIONS when LD then COUNT D else when CE then COUNT COUNT Q 1 else COUNT COUNT Q COUNT C CLK COUNT AR RST END Figure 86 Figure 87 gives the optimized equations for the 16 bit counter without the Activate D T Register Synthesis selected Please note that only a few output equations are shown to give the reader an idea of the effect on the equation by this option Also note that in this case the number of product terms required by each output increases by one going from QO to QI5 103 COUNTO D amp amp LD amp CE COUNTO Q LD amp DO COUNTI D amp amp COUNTO Q amp CE amp COUNTO Q amp COUNTI Q LD amp CE amp COUNTI Q LD
90. 5 04 03 02 01 00 LOAD LOADO LOAD LOAD2 LOAD3 LOADB LOADO amp LOADI amp LOAD2 amp LOAD3 IL C 1 0 C X Equations LOADO O0 Q amp 0 O0 Q dc LBO Q 01 Q amp LBI Q O1 Q dc LB1 Q LOAD 1 02 Q amp LB2 Q O2 Q dc LB2 Q 103 Q dc LB3 Q O3 Q dc LB3 Q LOAD2 O4 Q amp LB4 Q O4 Q amp LB4 Q 105 0 c LB5 Q O5 Q amp LB5 Q LOAD3 06 Q amp LB6 Q O6 Q amp LB6 Q 107 Q dc LB7 Q O7 Q dc LB7 Q 193 LA CLK CLK LB CLK CLK OUT CLK CLK LA AR RST LB AR RST OUT AR RST LA D DB amp LDPRE LA Q amp LDPRE LB D amp LDCOMP 8 LB Q amp LDCOMP 0 LOAD LOADB amp SEL amp DAO 0 LOADB amp SEL amp LAO Q O0 Q 1 LOAD amp LOADB SEL amp DAI O1 Q LOADB amp SEL amp O1 Q O2 T LOAD amp 0 0 amp O1 Q LOADB amp SEL amp DA2 O2 Q LOADB amp SEL amp LA2 Q O2 Q O3 T LOAD O0 Q amp O1 Q amp O2 Q LOADB amp SEL amp DA3 O3 Q LOADB amp SEL amp LA3 Q O3 Q O4 T LOAD amp O0 Q amp O1 Q amp O2 Q amp O3 Q LOADB amp SEL amp DA4 4 LOADB amp SEL amp LA4 Q O4 Q INPUT LATCH INPUT LATCH COUNT LOAD DATA FROM PIN LOAD LATCHED DATA O5 T LOAD amp 0 c 01 0 amp O2 Q amp O3 Q amp O4 Q LOADB SEL amp 5 5 LOADB amp S
91. 52 62 50 55 60 65 70 if TL then s3 else if TR then s4 else 50 state s3 if TL then sO else if TR then s4 else 50 state 54 if TR then s5 else if TL then 51 else 50 state s5 if TR then s6 else if TL then 61 else 0 state 56 if TR then sO else if TL then 81 else 50 state s7 goto 50 Illegal state recovery truth table sreg fb BRAKE TR TL L3 L2 L1 R2 R3 sO O x x gt 0 OJ 75 80 85 90 sO a 1 20 gt 1 b 5L L 11 50 1 I gt 0 1 1 11 s0 1 1 O gt 1 1 1 l sl O x x gt 0 1 OJ s LI 1 gt 0 0 1 1 1 1 52 O x x gt 0 1 1 OF s2 1 gt 0 1 1 1 1 1 s3 0 x x 5 1 1 1 OF fides 54 x x gt 0 1 OJ 94 20 1 Lh O 0 59 O x x gt 0 1 1 0 5652 L a xt eee j L s D gt 0 0 0 1 1 1 PSO J GE Jd 21 END 63 Chapter 6 Simulating XPLA Designs The XPLA Designer simulator is a graphical interactive design analysis tool It allows the user to input test vectors directly from the waveform screen move signal edges with the touch of a mouse button measure timing delays and many other featur
92. 8 147 146 195 194 1q3 amp 192 141 140 1415 1414 1413 amp q12 amp 1011 amp q10 amp 09 148 147 140 amp 195 194 1q3 192 141 140 lq 15 c 1414 413 1412 amp q11 amp q10 199 1468 147 146 amp 195 194 82 43 192 141 140 1415 1414 1413 1412 amp q11 410 amp q9 148 147 190 amp 145 194 amp 143 62 192 141 62140 q8 415 1414 42 413 amp 1412 amp 1411 amp 1410 amp 149 amp 148 c q7 82 140 amp 45 194 143 192 141 140 1415 1414 413 1412 42 1011 41410 42 149 4 48 amp 47 140 amp 45 194 1q3 amp 142 141 140 1415 1414 1413 1412 amp 1411 42 1410 amp q9 42 q8 82 47 q6 amp 195 194 1q3 192 141 140 1015 1414 1413 1412 42 1411 amp q10 149 amp q8 147 amp q6 amp 195 194 1q3 192 141 140 1415 amp 1414 66 1413 amp 1412 621411 61410 amp 149 amp q8 42 147 amp 146 amp 195 194 1q3 192 141 140 1415 1414 1413 q12 62 1011 amp 1910 amp q9 amp q8 147 140 amp 195 194 1q3 192 141 140 1415 1414 1413 1412 amp 1011 amp q10 amp q9 146 147 140 amp 45 194 143 amp 192 141 140 1915 1414 1413 1412 42 1411 2410 amp q9 amp q8 147 amp 190 amp 145 194 amp
93. A12 amp amp amp 9 amp 8 amp 7 6 5_1 AS amp 15 amp 14 amp A13 amp 1A12 amp A I amp amp 9 amp 8 amp A6 amp 5 amp A4 A6_1 D AS amp 15 amp 14 amp A13 1A12 amp A I amp amp 9 amp 8 amp A6 amp 5 amp 4 amp 4 A2 224 A7_1 D AS amp 15 amp 14 amp A13 amp 1A12 amp 11 amp 10 amp 9 amp A8 amp A7 amp A6 amp A5 amp 4 amp 2 amp Al amp AS 1 D AS amp INP lt HE2AB AS amp AS_1 Q A0 2 D AS I Q amp A15 amp A14 amp A13 amp A12 Al 2 D AS 10 amp 15 amp A14 amp A13 amp 1A12 amp All A2 2 D AS I Q amp A15 amp A14 amp A13 amp AI2 amp amp A10 2 D AS 1 Q amp A15 amp A14 amp A13 amp 1A12 amp amp amp A9 amp AS A4 2 D AS 1 Q amp 15 amp 14 amp A13 amp A12 amp amp 1A10 amp A9 amp A8 amp 1 amp A6 1 0 A5 20 AS I Q amp A15 amp A14 amp A13 amp 1A12 amp 0 amp A9 amp AS amp A7 1 Q amp A6 1 0 amp 5 1 amp A4 1 0 2 D AS I Q amp A15 amp A14 amp A13 amp 1A12 amp amp AIO amp A9 amp AS amp 1 amp 146 1 0 amp 5 1048144 1 0 amp 1 amp A2 1 0 7 2 D 2 AS 1 Q amp AI5 amp A14 amp A13 amp 1A12 amp amp 0 amp A9 amp AS
94. BRAKE pin TL pin TR pin CLK pin L1 L3 pin istype reg buffer R1 R3 pin istupe reg buffer Q2 Q08 pin istype reg buffer out L3 L2 L1 R1 R2 R3 sreg 102 01 00 1 1 Total 110 Top 1 Figure 11 The text editor allows the user to enter new designs and or edit existing designs It provides several functions which are useful in the design flow since it isn t necessary to exit XPLA Designer when making design revisions Design revisions can be overwritten or renamed with File Save or File Save As functions The line number and column position are displayed in the lower left box This is useful for finding errors in which the error message provides the line number of the code responsible for the error Device Selection The Philips CoolRunner series consists of 32 64 and 128 macrocell devices in 3 volt and 5 volt versions in a variety of speed grades and packages View the device list by left clicking on the arrow adjacent to Devices Scroll through the device list to see all devices displayed Figure 12 The PZ3000 series devices operate from a 3 volt supply while the 25 PZ5000 series devices use a 5 volt supply The number of macrocells is the last 3 digits in the 3000 5000 number The speed grade is generally related to the pin to pin delay and is designated next followed by the package definition This design targets an 8 ns PZ3032 in a 44 pin PLCC Select the PZ3032 8 PLCC44 PE Design
95. DECV DECV lt variable gt lt signal list gt SDC SDC lt value gt SETV SETV lt variable gt lt value gt ST DATA ST DATA signal list gt Figure 80 Figure 81 and Figure 82 contain a list of timing control statements their descriptions and formats EN EN SUNS Simulate Until Network Stable SUNS Goto Statement GT lt label gt Figure 81 s CALL Subroutine Call CALL lt subname gt SUB Start Subroutine Declaration SUB lt subname gt END End Subroutine Declaration END o Figure 82 Figure 83 and Figure 84 contain a list of print control statements their descriptions and formats Print Control Support statement are not supported in this version of the SCL simulator 96 1 ae PT Print Title PT textstring P signal list Print Comment PC textstring Print Every PE n1 n2 PCO Print Changes Only PCO Print Variables PV variable list Figure 83 Start Printer LIST List Signals State or LIST lt specification gt TRAC Transition Check TRAC STAB Stability Check STAB lt n gt Figure 84 Below is the SCL listing for the design Demo phd D XPLA EXAMPLE DEMO DEMO SCL 04 23 1996 12 33 49 XPLA Sim Beta 1 69 These Are The Bus Definitions 97 DEFBUS QBUS QO 1 02 These Signals Will Be Viewable After Running The Simulator P RESET CLOCK QO Q1 Q2 QBUS These Are The Initializations
96. E adder TITLE Two four bit adders DECLARATIONS Inputs 1 4 b1 b4 PIN SYNC CLK PIN inl in2 PIN Outputs sync outl sync out4 PIN ISTYPE reg_d buffer async_outl async_out4 PIN ISTYPE reg_d buffer s out sync outl sync out4 as out async_outl async_out4 EQUATIONS s out clk SYNC as out clk inl amp 1n2 s out al a4 b1 b4 as out al a4 b1 b4 Choosing Clock Polarity Like all signals in a PHDL source a clock can be inverted by placing an exclamation point in front of the signal name when it is used For example the asynchronous clock in the above example could be inverted with the following expression las out clk 11 amp 102 Resets and Presets Output pins that are declared as registers can be reset or preset through the use of a dot extension Figure 27 lists the extensions that may be used to reset or preset any of the register types For example if the PHDL adder example above had an input pin RST output s_out could be associated with a reset signal through the following statement 5 out ar rst 51 Presets are done in a similar fashion except that a different dot extension is used see Figure 27 Resets and presets made directly from input signals and feedbacks can be either a sum term or a product term but they cannot be a sum of products For example suppose there is a design with four inputs A B C and D
97. EL amp LA5 Q O5 Q O6 T LOAD amp O0 Q amp 01 0 82 O2 Q amp 82 O4 Q amp 5 LOADB amp SEL amp DA6 O6 Q LOADB amp SEL amp LA6 Q O6 Q O7 T LOAD amp 0 42 01 0 amp O2 Q amp amp O4 Q amp O5 Q amp 06 0 LOADB amp SEL amp DA7 O7 Q LOADB amp SEL amp LA7 Q O7 Q 194 16 Bit Loadable Binary Counter 2 reps module p7 16 bit loadable binary counter 2 reps This is simular to Prep 7 Inputs CLK RST LOAD CE pin D15 D14 D13 D12 D11 D10 D9 D8 pin D7 D6 D5 D4 D3 D2 D1 D0 pin Outputs 15 014 013 012 011 010 09 08 node istype buffer reg t Q7 Q6 05 04 03 Q2 01 Q0 node istype buffer reg t O15 014 013 012 011 010 09 08 pin istype buffer reg O7 06 05 04 03 02 01 00 pin istype buffer reg DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Q15 014 015 012 011 010 Q9 08 07 06 05 04 05 02 01 Q0 OOUT 015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 00 C N Equations QOUT CLK CLk QOUT AR RST OOUT CLK CLK OOUT AR RST Q15 T CE amp ILOAD amp 014 0 amp Q13 Q amp 012 0 amp Q11 Q amp Q10 Q amp 09 0 amp Q8 Q amp Q7 Q amp 06 0 amp 05 0 amp 040 amp Q3 0 amp 02 0 amp Q1 Q amp 00 0 LOAD amp Q15 Q D15 14 CE amp ILOAD amp Q13 Q amp 012 0 amp Q11 Q amp 010 0 amp 09 0 amp 08 0 amp Q7 Q amp 06 0 amp 05 0 amp 04 0 amp
98. Enable Currently Diasabled Buried Node Equation m O Pin Node Feedback To Zia Pin Input To Zia Figure 28 When the clocks are driven asynchronously by signals generated inside the part as in Figure 29 the output buffer is turned on and the equation used for the asynchronous clock is connected to the clock network after passing through the output buffer In this case the macrocell is wholly dedicated to generating the asynchronous clock To Clock Network Output Enable Currently Enabled Asynchronous Clock Equation Node Feedback To Zia Pin Input To Zia lt Figure 29 As with other input and output signals both synchronous and asynchronous clocks can be assigned to specific pins or they can be left floating in which case the software will assign them to appropriate pins The following example shows how to use both synchronous and asynchronous clocks ina PHDL source Note that as_out is driven by an asynchronous clock created by ANDing inputs inl and 1 2 together In this example the clock pins not specified so the software will automatically assign them to appropriate pins If for example the design were targeted to a PZ3032 in the 44 pin PLCC package the synchronous clock would be assigned to the dedicated input pin 43 and the asynchronous clock would use the macrocell associated with I O pin 4 Pin 4 would be unavailable as an I O pin for this design 50 MODUL
99. Fit Eas Gat Eod Qut OO 167 pPZ3129 PZ5128 ay 168 pZ35128 PZ51258 TOO PN POEP u u 169 PZ3126 PZ5128 175 PIN OBE L y uu u 170 PASTS PIN POR 171 APPENDIX C DESIGN EXAMPLES SHIFT REGISTER a 173 PEDi NIBUS REOR Pad ap 174 BIT ADDER HIGH LEVEL Uy as Ba a 175 S DITADDER SLOV LEVEL an a M 176 4 BIT ADDER WITH CARRY IN AND CARRY OUT 11 12 2 1 16 sese se ee se 177 BCD TOS SEGMENT DECODER aa lotam bouche 178 BID RECT ONAL LO aa ep VIE 179 8 BIT EQUALITY COMPARATOR HIGH LEVEL IMPLEMENTATION 000 0 0 0 000 180 16 BIT COUNTER LOW LEVELS a d ia 181 DUAL 16 BIT UP DOVVN LOADABLE ENABLED RESETABLE COUNTERS 182 755 C0UN Ebola 184 CODECOUNTERAS a aaa 185 4 BIT G
100. GND 15 HI2 25 16 BS 2 5 1DA 213 196 Fil 22 16 26 17 GND 157 03 42 97 Fi2 4 127 18 B4 11 158 p 21 198 24 1137 5 298 13 20 D0 CLK2 F15 IN0 CLK0 TCK A peo Yo C15 E0 CLK1 G2 TMS 27 E 1226 2 655 260 14 Vm 205 4 8 128 104 AS GND 6 1263 46 412 13 Es poo fiw e7 7 2 231 1107 G8 1265 18 GND 01 232 G9 26 149 0 108 60 6 A9 1170 6453 20 46 0167 6 271 12 5 16 TDO 113 22297 22 234 235 236 Fm 2 5 5 239 240 56 241 CH 1204 65 66 203 6 202 H 201 68 F 200 69 F 19 F 198 70 F 19 71 196 F 74 N 75 N 76 N 77 N E 78 E 80 F GND 114 NC 115 NC 116 NC 117 NC 118 NC 119 NC 120 NC 171 Appendix C Design Examples This Appendix contains a wide variety of design examples The purpose of this Appendix is to give the reader reference designs which can be used as is or can be modified to meet the individual designer s needs An electronic version of all of these design files phd along with their corresponding simulation files scl are loaded automatically when the XPLA Designer software is installed This section contains the following Design Examples
101. HDL source code If the design can be fit with no pre assigned pins the fitter will assign pins which be viewed in the fitter report filename fit The user should take these pin assignments and incorporate them back into the PHDL source design file The user will be notified whether the fitting operation was successful Max P terms per equation The Max P terms per equation selection allows the user to specify the maximum number of product terms that can be used for each macrocell equation The reason for this option is to control how wide logic functions are implemented Wide logic functions can be implemented in two different manners using more PLA product terms or using more than one pass through the logic array The maximum number which can be specified ranges from 5 to 37 product terms As specified in Chapter 3 XPLA Architecture Overview each macrocell has 5 dedicated PAL product terms and has access to 32 PLA product terms Because each design 1s unique and everyone has different system timing requirements XPLA Designer allows the user control this fitting parameter Implementing 100 wide logic functions using or up to 32 of the PLA product terms will add an additional delay see individual data sheets for PLA delay time Implementing wide logic functions using multiple passes through the logic array adds a Tpd delay for every additional logic array pass If speed is the most important parameter the design should spec
102. HIS IS A 10096 MATTER PRODUCT In the Unlikely Event That This Merchandise Should Contact Antimatter in Any Form a Catastrophic Explosion Will Result 69 EE XPLA Sim 2 19 BCD_SCL File View OUptions Drop Anchor Help F Undo Events 7 Create Change View Simulate Until Add Signal Bus Cik Bus Value Full_Screen 10000000 nsec Del Signal Add Evert 0000002000000 3000000 4000000 5 6000000 8000000 9000001 Del Event DO Add Bus Change Bus D1 Add Value D2 Clear Status List Figure 36 Under Edit there are ten additional items which are Undo This command will allow the operator to delete the last entered command Add Signal This command will allow the operator to add a signal to the waveform viewer window An Add Signal window will open and a list of signals available to add will appear In the waveform viewer window click in the row of signal names at the location where you want the new signal to appear You will be prompted for a new signal name Type the name of the signal or select a name from the list provided If the name you type is not the name of an available signal it will be assumed to be an internal node and automatically set to be an output When you are finished click the Done button and the new signal name will appear above location you selected All signal names below the point you selected will be pushed down the waveform vi
103. IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPDO D1 SL_ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 D2 ID7 ID6 ID5 ID4 ID3 ID2 ID1 0E_IDO D3 Q7 06 05 04 03 02 01 Q0 SF 06 05 04 03 02 01 00 07 Equations B CLK CLK C CLK CLK R CLK CLK D3 CLK CLK RST C AR RST R AR RST D3 AR RST 51 amp 150 amp DO 151 amp SO amp DI SI amp 150 amp D2 SI amp S0 amp D3 PIN 213 C Dz SL 1015 amp B Q LOAD SL 1015 amp SC Q SHIFT R D 151 amp S0 C Q Sl SO amp DI SI amp 150 amp D2 Sl amp 50 amp D3 PIN D3 Dz ISL 1015 amp RQ LOAD SL 1015 amp SF Q SHIFT D3 OE OE IDO end 214 Small State Machine 8 inputs 8 registered outputs module p3 Small state machine 8 inputs 8 registered outputs 3 reps This is simular to Prep3 Inputs CLK RST I7 I6 I5 I4 I3 I2 I1 IO Outputs O7 06 05 04 03 02 01 00 pin istype buffer reg B7 B6 B5 B4 B3 B2 B1 BO node istype buffer reg C7 C6 C5 C4 C3 C2 C1 CO node istype buffer reg Q QB QC node istype buffer reg State Register assignment OUT 7 6 5 4 3 2 1 01 inp I7 I6 I5 I4 I3 D2 IH IO IB7 Q B6 Q B5 Q B4 Q B3 Q B2 Q B1 Q BO Q inp2 C7 Q C6 Q C5 Q C4 Q C3 Q C2 Q C1 Q C0 Q sreg O7 06 05 04 03 02 01 00 sregl B7 B6 B5 B4 B3 B2 B1 B0 QB sreg2 C7 C6 C5 C4 C3 C2 C1 C0 QC START
104. IT 01 GND VCC PCO These Are The Signal Transitions For The Simulation 5 1 91 417 449 629 638 RESET S 1 17 34 ETC CLOCK SU time 1000 F 98 Chapter 7 Controlling the Fitting Process Once the design has been compiled and functionally debugged it can be fit into the targeted device There are many options available in the XPLA Designer that allow you to control specifically how the design 1s fitted These options affect such things as design speed logic minimization the width of logic equations and pin locations As a general rule designs that use a large percentage of the available logic in the part will be affected more by the option settings For some designs it may be desirable to try different fitting options to obtain optimal results This chapter describes how to access different fitting options for Philips CPLDs and makes recommendations for settings Fitter Options Fitting options are controlled by customizing the properties of processes to be performed on the source being fitted For each source a number of properties may be set to control the compilation and logic reduction and there are additional options selectable from the XPLA Designer User Interface as shown in Figure 85 for the targeted device Design Panel Project TBIRD Miel X Design View Help Designer V2 04 Pin preassignment Try Max P term per equation 7 Le Le Directory EXAMPLE TBIRD F Activat
105. K3 116 26 02 15 19 110 A 11114 0 Fi0 1191 195 m 710 13 di GND 196 a 118 28 GND FH 2 97 GND 29 8 14 2 2 119 m Di4 01163 163 FI3 1194 198 0 jm 30 12 FId 1195 jag tt 31 DI2 16 64 FI5 TCK 196 199 as 109 Di 160 165 GO 1197 110 71477 18 32 pi 1159 65 8 A6 1107 419 118 6 JG 19 33 bs 151 55 1220 169 PZ3128 PZ5128 128 Pin LQFP 1 N 1162 65 N 96 0 a 2 N 33 0 1181 6 N H 2 3 Y 134 1015 1192 67 V 97 H 28 4 4 113 1 4 11 168 13 6 198 24 5 A3 1132 135 113 10 4 27 99 H 0245 6 A2 11 6 GND 6 1208 100 GND HH ICT 8 _ 7 fao 19 8 20 102 NC CERNI IE eI TDI 4 9 0 9 1158 4 1012 1189 173 FA 43 105 1H5 01246 10 2 1157 42 DI 1188 74 FS 214 16 u 1156 43 DIO 17 6 1215 1106 0248 12 0 1155 119 1186 75 E7 6 1107 H8S 0249 B9 114 4 108 1185 618 7 19 0 1250 13 8 1153 45 D 1184 19 1108 251 14 B7 112 6 1183 7 FI0 29 1109 Hi 1252 15 GND 146 05 1182 8 1220 10 H2 253 B6 l1 47 DA 1 9 GND li a 125 16 1150 48 1D3 1180 0 Fi2 21 4 01255 17 B4 1149 49 DA 19 SI FI3 222 12 Hs 1256
106. MPBURSTn dst 15011 amp IDRAMCSn z MPRDn amp MPWRn amp MPRSTn dst dst12 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst13 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst14 amp IDRAMCSn z MPRDn amp MPWRn amp MPRSTn dst dst15 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst16 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst17 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst18 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst20 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst21 amp IDRAMCSn amp MPRDn amp MPWRn 6 MPRSTn IDRCAS3n dst dst2 amp MPRSTn dst dst3 amp MPRSTn dst dst8 amp DRAMCSn amp BE3n amp MPRDn amp MPWRn amp MPRSTn dst 450 amp DRAMCSn amp BE3n 62 MPRDn amp MPWRn amp MPRSTn dst dst11 amp DRAMCSn BE3n amp MPRDn amp MPWRn amp MPRSTn dst 4512 amp DRAMCSn amp BE3n amp MPRDn amp MPWRn z MPRSTn dst dstl4 amp DRAMCSn amp BE3n amp MPRDn amp MPWRn amp MPRSTn dst 4815 amp DRAMCSn 62 BE3n amp MPRDn amp MPWRn 62 MPRSTn dst dst17 amp DRAMCSn amp BE3n amp MPRDn amp MPWRn 62 MPRSTn dst dst18 amp DRAMCSn amp BE3n amp MPRDn amp MPVVRn z MPRSTn dst
107. PHDL source 2465 line lt number gt Syntax a1 b1 not allowed in a declaration statement The values for al and bl are not compatible for range operator Correct the PHDL source in the declaration section 2470 Number numbers is not allowed near line numbers Only or 1 is allowed Revise the source so that either or 1 is used 2475 Size of set not compatible near line lt number gt LHS numbers RHS number Correct the PHDL source so that the expression for the right hand side is the same size as that on the left hand side 2480 Error near line number lt string gt is not supported for sets Revise the PHDL source For correct use of sets in PHDL refer to chapter 5 of this manual 239 2485 Syntax error near line number Set is not allowed in WHEN condition Revise the PHDL source so that a set is not used in a WHEN conditional statement One option may be to use discrete signals in the conditional statement 2495 Constant declaration must be one to one correspondence Revise the PHDL source so that the constant 1s defined only once 2515 Error near line lt number gt State exp must all 0 1s in this release Revise the PHDL state machine description See p 43 for an example 2520 Error near line number Size of state register is different with state esp Revise the PHDL state machine description See p 43 for an example 2530 Different set size LHS number RHS lt numbers g
108. PLA product terms 18 Programmable 113 EN T 5 d5 Dy y Figure 6 Simplistic Timing Model Figure 7 shows the CoolRunner Timing Model As one can see from this illustration the CoolRunner timing model looks very much like a 22V10 timing model in that there are three main timing parameters including Tpd Tsu and Tco In other competing architectures the user may be able to fit the design into the CPLD but 15 not sure whether system timing requirements can be met until after the design has been fit into the device This is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed sharable expanders varying number of X and Y routing channels used etc In the XPLA architecture the user knows up front whether the design will meet system timing requirements This is due to the simplicity of the timing model For example in the PZ5032 device the user knows up front that 1f a given output uses 5 product terms or less the Tpd 6ns the Tsu 4ns and the Tco 5 5ns If an output is using 6 to 37 product terms an additional 2ns is added to the Tpd and Tsu timing parameters to account for the time to propagate through the PLA array this 1s the only variation in timing that exists when using the XPLA architecture 19 Tpd_pal Combinatorial PALonly Tpd_pla Combinatorial PAL PLA Input Pin Outpu
109. PRSTn dst dst15 amp DRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst18 amp DRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst9 amp DRAMCSn MPWRn amp MPRSTn amp dst dst15 amp DRAMCSn amp MPRDn amp MPVVRn amp MPRSTn dst dst20 amp DRAMCSn MPRDn amp MPWRn c MPRSTn dst dst2 amp MPRSTn dst dst3 dc MPRSTn dst dst4 amp MPRSTn STATE DIAGRAM DRSMSTA4 DRSMST3 DRSMST2 DRSMSTI DRSMSTO0 state dstO state 4511 state dst2 if MPRSTn then 450 else 4511 goto dst2 goto dst3 209 state dst3 goto dst4 state dst4 goto dst5 state 4515 goto dst6 state 9516 if IRETIMEnD then 4511 else if STARTCYCLE amp DRAMCSn amp MPRDn amp MPWRn amp RFTIMEn then dst7 else if STARTCYCLE amp DRAMCSn amp MPRDn amp MPWRn dz RFTIMEnD then dst20 else dst6 state dst7 goto dst8 state dst8 goto dst9 state dst9 goto dst10 state dst10 state 45111 state dst12 state dst13 state 45114 state dst15 state 45116 state dst17 state dst18 state dst19 State dst20 State dst21 State 45122 end if MPBURSTn then dst11 else dst6 goto dst12 goto dst13 goto 45114 goto 9515 goto dst16 goto dst17 goto dst18 goto dst19 goto dst6 goto dst21 goto dst22 goto dst6 210 High Level Implementation of 16 to 8 Multiplexer MODULE m16_8 Hig
110. Q amp amp BO S12 MAC amp Q1 Q amp BO 513 MAC amp Q2 Q 2 amp BO S14 MAC amp Q3 Q amp BO C51 542 amp C41 A A3 A2 A1 A0 B3 B2 B1 BO Q 07 06 05 04 03 02 01 00 ILL CG X 1 00 X Equations C52 543 amp C42 543 amp C51 C42 amp C51 C53 S44 amp C43 S44 amp C52 C43 amp C52 C21 512 amp C11 S12 amp A0 amp 1 11 amp A0 amp Bl C22 513 amp CI2 S13 amp Al amp BI CI2 amp Al amp Bl C23 S14 amp CI3 514 amp A2 amp BI C13 amp A2 amp Bl C24 MAC amp Q4 Q amp C14 MAC amp Q4 Q amp amp C14 amp amp Bl S22 13 C12 Al amp 219 S23 8145 A2 amp 524 MAC amp Q4 Q C14 amp C31 522 amp C21 S22 amp A amp B2 C21 amp A0 amp B2 C32 523 amp C22 523 amp Al amp B2 C22 amp Al amp B2 C33 524 amp C23 524 amp A2 amp B2 C23 amp A2 amp B2 C34 MAC amp Q5 Q amp C24 MAC amp Q5 Q amp amp B2 C24 amp B2 S32 823 C22 Al amp B2 S33 S24 C23 A2 amp B2 S34 MAC amp Q5 Q C24 A3 amp B2 C4 532 amp C31 532 amp amp C31 amp amp B3 C42 533 amp C32 533 amp Al amp B3 C32 amp Al amp B3 C43 534 amp C33 534 amp A
111. Q10 T CE amp amp Q9 Q amp Q8 Q amp Q7 Q amp 06 0 amp 05 0 amp 04 0 amp amp 2 amp Q1 Q amp 00 0 LOAD amp Q10 Q D10 Q9 T CE amp ILOAD amp 08 0 6 07 0 amp 06 0 6 05 0 amp 040 amp 03 0 amp 02 0 amp Q1 Q amp Q0 Q LOAD 6 09 0 D9 Q8 T CE amp amp Q7 Q 6 06 0 amp 05 0 amp 04 0 amp Q3 Q amp Q2 Q amp Q1 Q amp Q0 Q LOAD amp Q8 Q D8 Q7 T CE amp ILOAD amp Q6 Q amp 05 9 amp 04 0 amp Q3 Q amp Q2 0 amp Q1 0 amp 00 0 LOAD amp Q7 Q D7 Q6 T CE amp ILOAD amp 05 0 amp 04 0 amp Q3 Q amp Q2 0 amp Q1 Q amp Q0 Q LOAD amp Q6 Q D6 Q5 T CE amp LOAD amp 04 0 amp Q3 Q amp 02 0 amp QI Q amp Q0 Q LOAD amp Q5 Q D5 Q4 T CE amp ILOAD amp 030 amp 02 06 Q1 Q amp Q0 Q LOAD 6 Q4 Q D4 Q3 T CE amp ILOAD amp 02 0 amp 1 amp Q0 Q LOAD amp Q3 Q D3 Q2 T CE amp ILOAD amp QI Q amp Q0 Q LOAD amp Q2 Q D2 1 CE amp ILOAD amp 00 0 LOAD amp Q1 Q DI QO T CE amp LOAD LOAD 6 00 0 DO 15 CE amp ILOAD amp 014 0 amp O13 Q amp O12 Q amp 11 amp 010 0 amp O9 Q amp 08 0 amp 7 amp 06 0 amp 05 0 amp 04 0 amp 03 0 amp 02 0 amp 01 06 00 0 LOAD amp O15 Q Q15 Q 14 CE amp amp 013 0 amp 012 0 amp 11 amp 010 0 amp 09 0 amp 08 0 amp 7 amp 06
112. Q2 Q amp Q1 Q amp Q0 Q LOAD amp Q4 Q D4 Q3 T amp ILOAD amp 02 0 amp 1 amp 00 0 LOAD amp Q3 Q D3 2 CE amp ILOAD amp 1 amp Q0 Q LOAD amp Q2 Q D2 1 CE amp ILOAD amp Q0 Q LOAD amp Q1 Q DI QO T CE amp LOAD LOAD 6 00 0 DO O15 T CE amp ILOAD amp 014 0 amp O13 Q amp 012 0 amp 11 amp 010 0 amp 090 amp 08 0 amp O7 Q amp 06 0 amp 05 0 amp 04 0 amp 03 0 amp 02 0 amp 1 amp 00 0 LOAD amp O15 Q Q15 Q 14 CE amp amp O13 Q amp 0120 amp 11 amp 010 0 amp O9 Q amp O8 Q amp 7 amp 6 amp O5 Q amp 04 0 amp 03 0 amp 02 0 amp 1 amp 00 0 LOAD amp 014 0 014 0 O13 T CE amp ILOAD amp 012 0 amp 011 0 amp O10 Q amp 09 0 amp O8 Q amp O7 Q amp 6 amp O5 Q amp 04 0 amp 03 0 amp 02 0 amp 1 amp 00 Q LOAD amp 13 Q13 Q O12 T CE amp amp O11 Q amp 010 0 6 09 0 amp 08 0 amp O7 Q amp 6 amp O5 Q amp 04 0 amp 03 0 amp 02 0 amp 01 0 amp 00 0 LOAD amp 012 0 Q12 Q amp amp O10 Q amp O9 Q amp O8 Q amp O7 Q amp 6 amp O5 Q amp 04 0 amp 03 0 amp 02 0 amp 1 amp O0 Q LOAD amp O11 0 Q11 Q 10 amp ILOAD 6 09 0 amp 08 0 amp O7 Q amp 6 amp O5 Q amp 04 0 amp 03 0 amp 02 0 amp OI Q
113. RAY CODE COUNTER a d ma dadi 191 TIMES COLER m amaya aa 193 16 BIT LOADABLE BINARY COUNTER 2 6 000441 1111 se sse serre nus 195 16 BIT SYNCHRONOUS PRESCALED COUNTER 2 6 2 198 SERIAL CRC GENERATOR USING A 16 BIT LFSR G X X16 X12 X5 201 2107 ECODER mu m 202 8 BIT LOADABLE DATA eere rre eer a a a amal ba i 203 DOR T CONTEROLEERC paka DN 204 HIGH LEVEL IMPLEMENTATION OF 16 TO 8 re he serere rsen nun 211 AT TO sc b 212 DATAPATH CIRCUIT 6 1 4 441 1 se se ease es te 213 SMALL STATE MACHINE 8 INPUTS REGISTERED OUTPUTS 215 6 ARITHMETIC CIRCUIT 4 X 4 MULTIPLIER 8 BIT ADDER 8 BIT REG STER 219 IPS Sd ACCUMULA TOR a a ARA daaa 221 MEMORY MAPPED I O ADDRESS DECODER scscececececececececcceccucscecscscscecececscecececeacecscscetecsesaseececesesesucecs 224
114. S ne a a ON RO IO x RD OR S OC t ACER A CRT CCRT A MER aC CE MCR A CER MC a CE ACC CRT ACER MER CCRT A MR nC seeded cde eode ee dede ede dee ede ede dede de eoe deed dee de NN S UN S NS UN NS S ON TP PPP b b b Ub bb b ub ub b bob RON e I ICD OON IE ICD COO Status Project D SS v 3PLA EX4MPLESTBIRDATBIRD NET Refreshing Complete Figure 17 The input stimulus to the TL TR and BRAKE inputs is provided by first setting the signal to a level and then defining the transitions of the signal To do this select the Change Value in the fixed menu area Select the TL waveform and a dialog box appears with options to select 0 1 Z values Select 0 for the TL signal Next select the TR waveform set it to 0 Similarly set BRAKE to Multiple waveforms can be 28 defined without returning to the Change Value menu entry When done select OK in the upper left fixed menu area Next define the transitions of the input signals The TL signal should go active high at approximately 400000 ns Select the entry in the Event entry and click the TL waveform in the 400000 ns area The waveform should transition to 1 Use this procedure to define the following transitions on the TL TR amp BRAKE signals BRAKE 0 at tim
115. Signals Save Run Bus Cik Bus Value Full Screen 10000000 nsec 4172942 2500000 3000000 3500000 4000000 Status Project D SS Ww RPLASERAMPLESCOLINTTE HET Screen Complete Figure 46 77 EH XPLA Sim 2 19 COUNT16 5CL Of xi Edit View Options Drop Anchor Help Events Create Change View Simulate Until File Signals Seve Run K Bus Cik Bus Value Zoom Back 10000000 nsec 4172942 1000000 12000000 13000000 4000000 5000000 6000000 7000000 8000000 3000000 1 Status Project D SS vw RPLASERAMPLESCULINTTE HET Refreshing Complete Figure 47 Under Options there are the three additional items which are Set Signal Height This command allows the operator to scale the signal display height Using this command you can adjust the number of signals displayed in the window When selecting this item a signal height window will appear in the waveform viewer window see Figure 48 Set the height to a value between 10 and 50 inclusive The value you select is saved in the project ini file when the program is exited and will be the start up value when the program is invoked Figure 49 and Figure 50 are examples how this command works 78 fa XPLA Sim 2 14 Edi nue Create Change View Simulate Until Save OK Bus Bus Value Full_Screen 1000000
116. Testing There are two feedback paths to the 71 one from the macrocell and one from the I O pin The ZIA feedback path before the output buffer 15 the macrocell feedback path while the ZIA feedback path after the output buffer is the I O pin ZIA path When the macrocell is used as an output the output buffer 15 enable and the macrocell feedback path can be used to feedback the logic implemented in the macrocell When the I O pin is used as an input the output buffer will be three stated and the input signal will be fed into the ZIA via the I O feedback path and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path PLA Product Term Sharing Another feature offered by the XPLA architecture which cannot be offered by other competing architectures is product term sharing In address decode circuits some state machines and other types of designs there are product terms which are common to a number of macrocells XPLA architecture allows sharing of PLA product terms between macrocells as shown in Figure 6 In this example it shows one PLA product term being shared by two macrocells In this case there is effectively 33 PLA product terms because one of them is shared between two macrocells PLA product term sharing increases the effective density of the device and allows larger designs to fit in the same macrocell count device If needed all 16 macrocells could share all 32
117. XPLA Designer Hot Tools tor Cool Silicon Philips Semiconductors 1996 Permission is hereby granted to freely distribute this document in printed and electronic formats in its entirety without modification Philips CPLD Technical Support Philips Semiconductors Programmable Products Group M S 08 9201 Pan American Freeway NE Albuquerque New Mexico 87113 Phone 1 888 COOL PLD Toll free in the USA or 1 505 858 2996 Fax 1 505 822 7804 email coolpld scs philips com World Wide Web http www coolpld com XPLATM FZP Fast Zero Power and TotalCMOSTM are trademarks of Philips Semiconductors All other trademarks are the property of their respective owners IMPORTANT NOTICE TO PURCHASERS The Entire Physical Universe Including This Product May One Day Collapse Back into an Infinitesimally Small Space Should Another Universe Subsequently Re emerge the Existence of This Product in That Universe Cannot Be Guaranteed XPLA Designer version 2 1 User s Manual CHAPTER 1 INTRODUCTION XPLA DESIGNER 8 DUDDOVIOQ DOVIGOS as E Qa a Dsi mami aww aa 8 THE Des n T TOCE 8 1005000 Pre 9 101010 TS IIL OM RENTRER EO 10 1272000200 0 0 11 Fost Layout Smula OV uuu 11 1000
118. acro functions in chapter 5 Syntax macro_name macro inputs outputs macro definition 5 Macro name 15 the name of the macro function being defined inputs and outputs are the variables passed into and out of the function and macro definition 1s where the relationship between the inputs and outputs 1s created Note in the example below how question marks are used in front of the inputs and outputs in the macro definition These question marks are required for the macro to be instantiated in the PHDL file several times each time with different inputs and outputs Example Module macro ex Title Simple macro function example a b c d e f g pin 06 01 pin istype com Create the macro called gc dsn gc dsn macro in1 in2 in3 in4 out out2 2000 amp n2 amp 73 20012 in1 in4 62 2112 NOTE reserved word equations 15 required due to equations in the macro EQUATIONS 123 Use the macro in the design lgc_dsn a b d e 06 05 lgc_dsn d e f g 01 03 lgc_dsn a c e g 02 04 end module Description The reserved word module is used to assign a name to the PHDL design Module and a name for the design are required as the first line in every PHDL source Syntax module module_name Example Module modl ex Title Example of the reserved word module in out pin istype com equations out in end node Description The reserved word node is used to dec
119. al as an output is signal_name PIN pin_number ISTYPE attr where signal_name 15 the name of the signal PIN is a reserved word pin_number 15 the optional specification of the pin the signal will be assigned to ISTYPE is a reserved word and the variables attr determine the format of the output signal Lines 13 and 14 of Figure 22 illustrate how to declare output signals with specified pin numbers Like input signals the signals can automatically be assigned to pins of an appropriate type by leaving the pin number specification blank For example changing lines 13 and 14 of Figure 22 to 15 0 istype cb15 cb0 pin istype vvill cause the softvvare to choose pin numbers for each of the signals The attr variables are really a string of attributes used with the reserved word ISTYPE to set the format of the output signal For example the attribute reg specifies that the output is registered while the attribute specifies the signal to be combinatorial The pin attributes available in PHDL are listed and described in Figure 25 ATTRIBUTE DESCRIPTION Use non inverted output Collapse this signal during logic synthesis Combinatorial output Use inverted output keep Do not collapse this signal during logic synthesis Clocked memory element 2 This attribute is ignored for all signals except those that are a detailed register type reg d reg g reg jk reg sr
120. amp 00 0 LOAD amp O10 Q Q10 Q 196 O9 T CE amp ILOAD amp 08 0 amp 07 0 amp 06 0 amp 05 0 amp 04 9 amp O3 Q amp 02 0 amp 01 0 amp O0 Q LOAD amp O9 Q Q9 Q O8 T CE amp amp 07 amp O6 Q amp 05 0 amp 04 0 amp O3 Q amp 020 amp O1 Q amp O0 Q end LOAD amp O8 Q Q8 Q O7 T CE amp ILOAD amp 6 amp O5 Q amp O4 Q amp 03 0 amp 02 0 amp 01 0 amp 0 LOAD amp 07 Q Q7 Q O6 T CE amp LOAD amp O5 Q amp 04 0 amp 03 0 amp 02 0 amp 01 0 amp 0 LOAD amp 06 0 Q6 Q O5 T CE amp ILOAD amp O4 Q amp O3 Q amp 02 0 amp O1 Q amp 00 0 LOAD amp 05 0 Q5 Q O4 T CE amp ILOAD amp O3 Q amp 02 9 amp 1 amp 00 Q LOAD amp 04 0 04 0 O3 T CE amp ILOAD amp 02 0 amp O1 Q amp 00 Q LOAD 6 03 0 03 0 O2 T CE amp amp 01 0 amp O0 Q LOAD amp 02 0 Q2 Q 1 amp ILOAD amp 00 Q LOAD amp O1 Q QI Q O0 T CE amp LOAD LOAD amp O0 Q Q0 Q 197 16 Bit Synchronous Prescaled Counter 2 reps module 16 bit Synchronous prescaled counter 2 reps This circuit can divede the clock frequency by any value up to 65536 This is simular to Prep 8 Inputs CLK RST LOAD CE pin D15 D14 D13 D12 D11 D10 D9 D8 pin D7 D6 D5 D4 D3 D2 D1 D0 pin Outputs 15 014 013 012 011 010 09 08 node istype buffer reg t Q7 Q6
121. amp 199 amp 148 147 82 140 amp 145 194 82 143 amp q2 amp ql amp 140 1915 amp 1414 amp 1413 amp 912 amp q11 amp q10 amp 199 148 147 amp 140 amp 145 1944 143 amp q2 1915 1414 amp 413 amp 9412 amp q11 amp 410 amp 199 amp 148 amp 147 amp 140 amp 145 194 amp 143 amp q2 amp 141 amp 40 1915 c 1414 amp 413 amp 9412 amp q11 82 1410 amp 199 amp 148 amp 147 82 140 amp 45 194 143 amp q2 ql 6140 1915 1414 amp 413 amp 912 amp q11 amp 1410 amp 199 amp 148 147 82 140 amp 145 amp 194 amp q3 amp q2 amp 141 140 189 1415 amp 1414 amp 1413 amp q12 61411 amp 1410 amp 09 q8 amp 147 amp 146 145 amp 94 amp q3 142 amp 141 140 1915 c 1414 amp q13 amp q12 amp 1411 amp q10 amp q9 amp 48 42 147 amp 140 amp 195 c q4 amp 43 amp q2 amp ql 4140 ql 1415 amp q14 42 q13 amp q12 1411 amp 410 amp q9 amp q8 amp 147 42 146 q5 194 q3 q2 141 amp 40 1015 amp 1414 amp 1q13 amp 9412 amp 411 amp q10 amp q9 amp 148 42 147 82 q6 145 194 amp q3 amp 142 amp 41 amp 40 1915 amp 1414 amp q13 amp q12 amp q11 amp q10 amp q9 amp 48 amp 147 82 140 q5 194 q3 q2 amp ql amp q0 1915 amp 1414 amp 1q13 amp q12 amp 411 amp q10 amp
122. cess The Philips XPLA Designer is a stand alone tool which includes all aspects of the design process including design definition functional simulation device fitting post layout timing simulation and also produces a JEDEC file which can be used to program the device Figure shows the high level CPLD design process The following sections walk the user through this design process Each section first gives a general description of the development stage and then gives the reader a brief introduction of how to use the XPLA Designer to complete each stage A detailed description of each design stage is given in subsequent chapters Design Definition FAIL Functional Fail A Simulation Device Fitting PASS Post Layout Timing Simulation Program 2 Devices Figure 1 Design Definition The design definition stage 15 where the design is actually created Starting with the knowledge of what the design must do the designer enters that information into the computer in various formats Within the limitations of the design package the designer may use various methods of design entry including schematics textual models state diagrams state machines and boolean equations To the computer all of these formats are equivalent because the software will eventually link them all together Having the ability to choose the design method gives designers a very powerful tool for their work For example
123. chronous Synchronous clocks are driven from an external pin and asynchronous clocks are driven by a logic equation created within the code of the PHDL source Both types of clocks are available to every macrocell in both the inverted and non inverted state Every Philips device has at least two clock networks All but one of the clock networks in a given device can be driven by either synchronous or asynchronous clocks the one remaining clock network clkO in all Philips devices can be driven by only synchronous clocks A review of the tables in Appendix B shows that on every Philips CPLD clkO is assigned to a dedicated input pin This is the reason that clkO can be driven only by a synchronous clock dedicated input pins cannot be connected to logic signals generated inside the part they must be driven by external signals All other clocks in the Philips devices are assigned to input output I O pins so they can be driven by an external input or by logic signals generated inside the device and fed through the output buffer Figure 28 shows a schematic of an I O pin that is configured as a clock and is being driven by a synchronous external clock When the I O pin clocks are driven by external sources the output buffer on the I O pin is turned off and the input is directly connected to the clock network In this case the macrocell can still be used as a buried node because the output buffer 15 disabled 49 To Clock Network A Output
124. cription Dot Extensions Dot extensions are short suffixes that are appended to a signal name in the logic description section of the phd file They are used to access device specific features or to specify the type of signal or feedback Figure 27 lists all the dot extensions available in PHDL and indicates whether they are directly or indirectly supported Dot extensions that are directly supported are available as a hardware feature of the device indirectly supported dot extensions are not available as a hardware feature but are emulated using logic equations and hardware features that are available 47 SUPPORTED SUPPORTED SUPPORTED AP ASET PR Asynchronous preset x 2 ACLR RE Asynchronous reset x 0 2 CE Clockenable CLK Qlockinput to register x CLR SR Synchronous reset COM Combinatorial feedback X L Eli FBQ Register feedback 2 FC Ripfopmeecmmi X 4 PDatinputtoaJKFF 2 K DatainputtoaJKFF X 2 ID 1 Register load input 2 LE Latch enableinput 2 Latch enable high 2 PN Pinfeedback 2 OE R lputtoansRFF S PmpittoanSRFF SET SP Symhronusprset XP T X Figure 27 The following example illustrates the use of dot e
125. d from one computer to another so long as there is No Possibility of its being used by two people at the same time 4 DISCLAIMER THIS PROGRAM AND DOCUMENTATION ARE LICENSED AS IS WITHOUT WARRANTY AS TO PERFORMANCE PHILIPS EXPRESSLY DISCLAIMS ALL WARRANTIES EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS OF THIS PROGRAM FOR A PARTICULAR PURPOSE 5 LIMITED WARRANTY The CDROM or diskettes on which this Program 15 recorded is guaranteed for 90 days from date of purchase If a defect occurs within 90 days contact the representative at the place of purchase to arrange for a replacement 6 LIMITATION OF REMEDIES AND LIABILITY INNO EVENT SHALL PHILIPS BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM PROGRAM USE EVEN IF PHILIPS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES PHILIPS EXCLUSIVE LIABILITY AND YOUR EXCLUSIVE REMEDY WILL BE IN THE REPLACEMENT OF ANY DEFECTIVE CDROM OR DISKETTE AS PROVIDED ABOVE IN NO EVENT SHALL PHILIPS LIABILITY HEREUNDER EXCEED THE PURCHASE PRICE OF THE SOFTWARE 7 ENTIRE AGREEMENT This agreement constitutes the sole and complete Agreement between Philips and the Customer for use of the Program Changes to this Agreement may be made only by written mutual consent 8 GOVERNING LAW This Agreement shall be governed by the laws of the State of California 248 Appendix 2 About this manual This manual was written in its ent
126. d to the device file FATAL ERROR HTH An error that causes program termination INTERNAL ERROR A program error The compiler accepts PHDL open ABEL PLA and BLIF input formats There are many tools which write netlists in BLIF and PLA format When the recommended action is to re generate the BLIF or PLA file this may involve editing a source file used the generation of the file 235 Warnings 1010 Normalizing node to active high 1020 Restoring node to active low 2355 Node with both KEEP and COLLAPSE KEEP is assumed If you want the node collapsed delete the keep directive 2357 Creating node 2360 Node collapsed 2365 Node swept 2381 The device supports maximum pterm for each node between 5 and 37 Specified as lt range gt in command line Changed to default This parameter affects the speed and density of the fitting If designs objectives are not met this number should be varied and the design re compiled and re fit 2382 The device supports maximum fanin for each node between 1 and 36 Specified as lt number gt in command line Changed to default value The default value is 36 2385 Fanin of node must between 1 and device limit Changed from lt number gt to default The fanin is changed to 36 2401 Network node does not fanout If this node is intended to be used modify the PHDL code 2403 Network node is not driven PI assumed If this node is intended to be used the design ed
127. design Fit the Design After compilation you can fit the design into the target device by clicking the Fit button During the fitting process XPLA Designer generates three files that contain information about the design The tbird fit file contains the fitter report Figure 13 which indicates 24 the CPLD utilization and pinout The tbird tim file contains timing information The tbird jed file can be used with a device programmer such as Data I O s Unisite 2900 3900 or BP Microsystems to configure the CPLD The fitter report is shown in Figure 13 Examine the report by pulling down the View menu and selecting Fitter report to see how many macrocells the design used the percentage utilization and the pinout Also take a look at the timing report a section of which is shown in Figure 14 by pulling down the View menu and selecting Timing report The timing specifications provided in this report accurately reflect the AC parameters in the data sheet ET PLA Designer Viewer TBIRD_FIT File Clipboard Search Options DESIGH DEVICE FITTER DATE tbird pz3H32 8 plcc xplafit 07 00 1006 18 10 39 SDEUICE SPIHS 13 1 11 2 pz3832 8 plcch A Fit CLK 43 L2 5 L1 6 Rolf R2 8 R1 9 08 11 01 12 02 13 RESOURCE TOTAL USED UTILIZATION Macro cells 16 9 56 25 170 pins 16 9 56 25 P Terms 4 0 008 P R P Terms 2 B z PAL P Terms BB 32
128. designing a complex state machine using only registers and logic gates can be difficult it may be easier to design it with an HDL Hardware Description Language that the computer can translate into those same registers and gates The XPLA Designer uses the PHDL Philips Hardware Description Language language to support the following design entry formats boolean equations state machines and truth tables A PHDL language overview and PHDL language reference are given in Chapters 5 and 8 respectively A design can be created or selected by choosing the Design New Design or the Design Open Design command from the Design pull down Menu on the XPLA Designer Interface shown in Figure 2 The design can be entered or modified by selecting the Edit Button on the XPLA Designer Interface Once the design has been entered the PHDL must be compiled to check for syntax errors and to minimize the user s logic In order to activate the compiler the Compile Button on the XPLA Designer Interface as illustrated in Figure 2 must be selected Design Panel Project TBIRD i IDE X Design View Help Designer V2 04 Pin preassignment Try P term per equation 7 hal Directory EXAMPLE TBIRD Activate DT register synthesis Filename TBIRD PHD EDIT Auto Hode Collapse Mode Design nz5032 6 PLCC44 Generate Timing Model VHDL open an exist design start a newe design hecki lea
129. e 1 at time 4000000 TL at time 170000 1 at time 5000000 0 at time 6500000 at time 0 1 at time 2100000 at time 3500000 1 at time 8500000 After completing definition of the stimuli select OK Figure 18 shows the waveform after TL TR and BRAKE have been defined FEB XPLA Sim 2 19 ITBIRD 5CL OF Es Edit View Options Drop Anchor Help File Signals Events Create Change View Simulate Until Save Run DK Bus Clk Bus Value Full Screen 10000000 nsec eee eee a a Da a a a Ta a ta ai a a a at a a a ta a a a a a a a rg a a a m m m m m m M o cu m m m m M m m a o m m m u M m m Au uuu uu s x si et 1 a s s a s a s a a My 5 XX 4 s a a a a a xm a a a a a sa LL a sa xoxo MMi i Mg uM to 0 6 0 0 S D CN NS ON 6 0 0 t oo S oo oe ooo ee oe eee oo oe ee S UN 2
130. e DT register synthesis Filename TBIRD PHD EDIT Auto Node Collapse Mode Design nz5032 6 PLCC44 Generate Timing Model VHDL open an exist design or start a new design hecki lear the check box r select an item elect Design open New Design in the menu he combobox to specify design options simulate it Figure 85 99 The fitting options selectable through the XPLA Designer Interface include Pin Pre assignments Max P terms per equation Activate D T register synthesis Auto Node Collapse Modes All of these options are described in the next subsections Pin Pre assignments The pin pre assignments selection gives the user three different options Try e Keep e Ignore The Try selection will attempt to fit the design with the pin assignments specified in the PHDL source code If the design cannot be fit with these pin assignments the fitter will remove the pre assigned pins and attempt to fit the design with no pre assigned pins A warning message will tell the user if the pre assigned pins have been removed The Keep selection will attempt to fit the design with the pin assignments specified in the PHDL source code If the design cannot be fit with these pin assignments the fitter will notify the user that the device could not fit It will not unlock the pins under this option The Ignore selection will attempt to fit the design and will ignore the pin assignments specified in the P
131. e expected Correct error in PHDL file 5090 Line lt numbers gt expected Correct error in PHDL file 5095 Line number Unknown dot extension Correct error in PHDL file See Chapter 5 for valid dot extensions in PHDL 241 5100 Line lt number gt expected Correct error in PHDL file 5105 Line number expected Correct error in PHDL file 5110 Line number expected Correct error in PHDL file 5115 Line number ELSE expected See p 40 41 for correct syntax of conditional statements in PHDL Correct the PHDL file 5120 Line number THEN expected Correct error in PHDL file See p 40 41 for correct syntax of conditional statements in PHDL Correct the PHDL file 5125 Line number IF CASE or GOTO statement expected See p 40 41 for correct syntax of conditional statements in PHDL Correct the PHDL file 5130 Line number Possible missing in CASE statement See p 40 41 for correct syntax of conditional statements in PHDL Correct the PHDL file 5135 Line number or WITH statement expected See p 40 41 for correct syntax of conditional statements in PHDL Correct the PHDL file 5140 Line lt number gt ENDCASE expected See p 40 41 for correct syntax of conditional statements in PHDL Correct the PHDL file 5145 Line numbers Dot extension is not allowed in output Correct error in PHDL file 5150 Line lt number gt Dot extension is not allowed in in
132. e final editing of all of the real work done by the Applications Staff Asked to comment on this he replied something about 100 monkeys given typewriters creating a work of literature In his spare time Mark continues to work out on that expensive home gym he bought as a New Years resolution Really I still use it so that his legs will transform into massive muscle rippled tree trunk like appendages that will allow him to continue kicking his friend Darryl s butt skiing the NASTAR course The recent breakthrough he made in his garage in working cold fusion is rumored to be ready for publication in a prominent scientific journal or the National Enquirer whichever will fork over the bucks first 249 The Writers Reno Sanchez V7 D Wade Baker or 0 ester Sanders B Wade Baker We asked Wade to tell us a little about himself Here in his own words is what he said My name is B Wade but I go by Bubba I think the B stands for Bubba but I aint never heard I was born in Nashville Tennessee and lived at home until the revenuers come an took my maw and paw away We asked him about college and said Yeah I reckon I heard that there is such things but I aint never bothered with em myself On the subject of work experience Bubba tells us I reckon the closest related experience would be the two weeks I worked as a salesman for Radio Shack Next would probably be the Dairy Queen
133. e page 72 under Del vent for a complete description of this function 86 File Signals Events Create Save Run Bus nal ke e a uam lete an Even n Thnnmnnnm OO nmnnnnn lifi rir Figure 61 Press the Create Bus button to add a bus signal to the waveform viewer window See page 73 under Add Bus for a complete description of this function File Signals Events Create Save Run us n TANANAN 2nnnnnn annnnnn annun Figure 62 Press the Create CIk button to add a clock signal to the waveform viewer window See page 74 under Add Clk for a complete description of this function File Signals Events Create Change Save Run OK Bus Value di E k Set Signal to a Clock n n o vnmmmmmm Figure 63 Press the Change Bus button to edit an existing bus in the waveform viewer window See page 73 under Change Bus for a complete description of this function File Signals Events Create Change Save Run Bus Value PTAA AN zsnnnnnn smmnmnmnnnm ammmmnm 12 Figure 64 Press the Change Value button to edit the value of a signal in the waveform viewer window See page 75 under Set Value f
134. e targeted device will support 3217 Clock input cannot be tied to Vpp GND You cannot connect clock inputs to power or ground 3218 Too many product terms for lt node name gt maximum is 37 Node node name has more than 37 product terms which is not supported by Philips devices 3219 Design exceeds maximum number of asynchronous clocks You are trying to generate more clocks than the device will support from the logic 3220 Output enable can be driven by only one product term The output enable signal for Philips devices can only be driven by a single product term 3221 Design exceeds maximum number of output enables You are trying to use more output enable terms than the device will support 3222 Reset preset can be driven by only one product term The reset and preset signals for Philips devices can only be driven by a single product term 245 3223 Design exceeds maximum number of resets presets You are trying to use more reset preset signals than the device will support 3225 Selected device is not supported by the fitter You have specified an incorrect Philips CPLD name or a non Philips part that 1s not supported by the Device Kit 3226 Design exceeds maximum number of pins Your design uses a total number of I O pins and dedicated inputs than the targeted device can support 3227 Design exceeds maximum number of nodes Your design uses a total number of nodes that exceeds the maximum number the targeted d
135. eated as upper case Tabs are treated as blanks An asterisk in column 1 means a comment line A comment line has no influence on the program 141 11 A number in column 1 means a continuation line The statement field starts after at least one blank and consists of a keyword usually followed by a further parameter The keyword is separated from the parameter by at least one blank The label starts in column 1 and serves as a reference for a GT go to statement It is separated from the statement by at least one blank Labels within a subroutine are local Labels signal names and variable names are composed of maximum 12 characters the first being a letter lt signal list gt is a list of signal names which are separated by commas state list is a compact string of logic states No blanks are allowed in a state list but commas may be used to separate the states Extra blanks are allowed anywhere except in names numbers and state lists General Information about Stimuli SCL statements must be in the order shown below Subroutine declarations Main part of stimuli file Printlist definition Finish command F All commands must appear either in a subroutine or after the printlist definition P command An exception to this rule is the command IDENT or IDNT It can be before the subroutine declaration Subroutines 1 Subroutines must be declared at the beginning of t
136. ed Correct the connectivity of the PHDL file 5240 Input file not found Either use the XPLA Designer GUI to navigate to the correct directory or invoke the command line interface form the project directory containing the design file 5245 Line number Operand needed for operator Table 5 2 provides the operators supported in PHDL Correct the PHDL file 5250 Line numbers Id needed for property statement Add the identifier in the PHDL file As an example of the syntax of a property statement in the header section 15 xpla property dut on 5255 Line numbers needed for macro statement Add the semicolon to macro statement in PHDL file See p 5 X for the correct syntax for using macros 5260 Line number gt syntax error within macro definition Correct the macro in the PHDL file See p 5 x for the correct syntax for using macros 5265 Line number The name of module has to be the same with its filename without extension Correct the module statement in the PHDL file 243 5270 Line number Bad istype Supported istype attributes in PHDL are listed in Table 5 3 and 5 5 The use of istyoe definition of pin and nodes is discussed on p 5 x Fitter Error Messages Below is a list of the error messages and warnings resulting from XPLA Designer s fit operation Command and Internal errors indicate that something has gone wrong with the fit program If you encounter one of these errors call the tech
137. el open an exist design or start newe design heckClear the check box or select an item elect Design open Mew Design in the menu he combobox to specify design options Simulate it Figure 9 The tbird design is created in the xpla examples directory with the software installation This tbird phd file will be used in this tutorial When either a new design file is created or an existing file 1s opened a dialog box 15 displayed which allows the user to move to the design directory See Figure 10 Open Design File name Folders d szwxplaXexamplexthird tbird phd ex d CA z xpla example List files of type Drives Files phd E 4 lizard 2 Figure 10 27 New design filenames must use a phd filename extension Existing design file extensions can use either phd tt2 or blf extensions tt2 amp blf extensions are used only when importing a design from another front end synthesis tool that supports PLA or BLIF format intermediate files If creating a new design use tbird phd for the design filename If using the source code provided the PHDL code may be viewed by opening tbird phd and then clicking the Edit button on the main screen A text editor displays the PHDL code Figure 11 Designer Editor TBIRD PHD Es File Edit Search Options Window x DULE tbird TITLE thunderbird tailight demo
138. else out2 1 end title Description The optional title statement is used as a comment at the beginning of a PHDL file to describe the function of the design 131 Syntax title what you want the title to be Example Module simple Title A very simple design with a title out pin equations out 1 end when then else Description The when then else structure is used with equations to specify conditional results This structure cannot be used for state diagrams it is only used with equations Syntax when condition then result else when condition then result else result When a condition is true the corresponding state result will be implemented If none of the conditions are true the result specified after the final else statement will be implemented Note that both of the else structures are optional When then else can be used by itself with a single else or with multiple levels of else when statements When then else structures can also be nested Refer to the examples below Example Simple when then structure 132 Module whenthen Title Example of simple when then statement in equations inl 12 pin pin pin istype outl c clk when inl 1 amp in2 1 then outl 1 when inl 0 amp in2 0 then outl 0 end Example When then else structure Module whenthen Title Example of when then else statement in e
139. en SB else if h2A then SC else SAT state SB if hA A then SE else SF state SC goto SD state SD goto SGI state SE goto STARTI state SF goto SG state SG goto START2 state SGI goto START2 state diagram sreg third instance state START if inp2 h3C then SA else START state STARTI 217 if inp2 h3C then SA else START state START2 if inp2 h3C then SA else START state SA if inp2 h1F then SB else if 1np2 h2A then SC else SAT state SAT if inp2 hlF then SB else if 1 2 h2A then SC else SAT state SB if inp2 hAA then SE else SF state SC goto SD state SD goto SGI state SE goto STARTI state SF goto SG state SG goto START2 state SGI goto START2 end 218 Arithmetic Circuit 4 x 4 multiplier 8 bit adder 8 bit register module p5 Arithmetic circuit 4 x 4 multiplier 8 bit adder 8 bit register This is simular to Prep 5 Inputs CLK RST MAC pin A3 A2 A1 A0 B3 B2 B1 BO pin Outputs Q7 Q6 05 04 03 Q2 01 Q0 pin istype buffer reg d C53 C52 C21 C22 C23 C24 node istype buffer 31 32 33 34 41 42 43 44 node istype buffer 522 523 524 532 533 534 542 543 544 node istype buffer Cll MAC amp Q0 Q amp amp BO C12 MAC t Q1 Q amp Al amp BO C13 MAC amp Q2 Q amp 2 amp BO C14 MAC amp Q3
140. ent expression Element 15 either a signal or a variable and expression 15 a logical function of inputs and feedbacks When signals are specified by including attributes 1n the pin or node statements of the declarations section the two different assignment types are functionally equivalent When signals are not specified with attributes and are only indicated to be pins or nodes then the different types of assignments have different effects on the design When the single equal sign assignment is used the signal is assumed by the compiler to be a combinatorial signal when the colon equal assignment is used the signal 1s assumed to be a registered signal It is recommended for design clarity that you specify all signals with attributes in which case the assignment operators are equivalent The following example of a four bit adder with carry in and carry out illustrates how to use equations to define a design Notice how the reserved word equations precedes the start of the equations themselves Module addr4b Title Four bit adder with carry and carry out clk pin 3 0 pin b3 b0 pin sum3 sum0 pin istype reg buffer carryin pin carryout pin istype reg buffer a 0 a3 a0 53 b 0 b3 b0 sum carryout sum3 sumQ equations sum c clk sum a b carryin end Notice the line sum a b carryin which is the defining equation for the adder design The outp
141. ent state and run it ohe simulator TANANAN ANNAN inn nn Figure 56 Press the File OK button to 1 Redraw the waveform viewer window 2 End the add delete events process 3 End the value change process File Signals Events 7 Create Change Hun ng PEN Bus Value Ri tesh the screen or end Ad Add Delete Events or Change Value 00000 3000000 13000000 5000000 160 Figure 57 85 Press the Signals button to add a signal to the waveform viewer window See page 70 under Add Signal for a complete description of this function File Signals Events Create Run NNI Bus ck B dd a Signal n 5nnhnnnn nnnnnn nnnnn Figure 5 Press the Signals button to remove a signal to the waveform viewer window See page 7 under Del Signal for a complete description of this function File Signals Events Create Save Run Bus Figure 59 Press the Events button to add a transition to a signal or signals displayed in the waveform viewer window See page 71 under Add Event for a complete description of this function File Signals Events Create Save Run OK sL Del Bus c aJJ C add an Ev ent nnnnnan n 1nnnnn Figure 60 Press the Events button to delete a transition from a signal or signals in the waveform viewer window Se
142. es available in PHDL are listed and described in Figure 26 SR type flip flop clocked memory element T type flip flop clocked memory element Do not minimize this output Preserve redundant product terms Figure 26 JK type flip flop clocked memory element Multiple attributes may be specified for a particular node as long as they do not conflict with one another For example buried NODE ISTYPE reg_d retain specifies the signal buriedl to use a D type flip flop preserve any redundant product terms that make up the node However the line buried NODE ISTYPE reg 46 is illegal because buried cannot be combinatorial and registered at the same time attributes must be separated by commas and the string of attributes must be enclosed with single tick 9 marks Because node signals are not propagated through the output buffer the input path of the I O pin is unused Thus any I O pin that is assigned to a node signal can be used as a dedicated input For example consider the following declarations up PIN 41 down PIN 40 stl NODE 61 ISTYPE reg st2 NODE 62 ISTYPE reg and assume that the design 15 targeted to PZ3032 CPLD in a 44 pin PLCC package Appendix B indicates that for this package node 61 and pin 41 share the same macrocell as do node 62 and pin 40 The above example uses the macrocells as buried nodes but at the same time can use the pins as inputs Logic Des
143. es normally found on expensive high end systems The graphical control of stimulus signals allows designs to be thoroughly simulated much less time than conventional simulators that require textual test vector entry Organization This section is comprised of four 4 parts Simulation process Description of Simulator menus Practice design simulation SCL Simulation Control Language brief Simulation process The XPLA Designer simulation engine performs functional and timing simulation of the input design using signal stimuli defined in the Simulation Control Language SCL file This file is generated when the user defines signal characteristics from the waveform window or when the information is input in text form Inputs to the simulator are the SCL file which also contains timing information and the user design file in binary form Results from the simulation can be directly displayed the waveform viewer and output to any Windows supported printer The SCL file and the binary design file are combined to produce an event list Figure 30 illustrates this process Binary Network File event list SCL File Wheel RES File Figure 30 64 The simulator utilizes five logic levels when representing waveforms Low High Unknown Tri State Undefined The SCL and Waveform viewer representation of these values are described in Figure 31 and Figure 32 The waveform viewer displays four of the
144. evice will support 3228 Design exceeds maximum number of inputs Your design uses a total number of inputs greater than what the device will allow 3236 Software unable to fit design The fitter was not able to fit your design into the device using the current fitting property settings 3237 Unable to KEEP pin assignment The pin assignment you used for the last fitting could not be reused 3239 Unable to route input signal lt signal name gt The fitter was not able to route signal lt signal name gt where it was needed in the logic 3243 Preset reset cannot both be assigned to register lt register number gt Registers in Philips devices can be reset or preset but not both at the same time 3245 Single node exceeds maximum allowable fan in There 15 a node the design that has more signals routed to it than the device can support 3246 Signal signal name gt cannot be both combinatorial and registered signal declarations must be either combinatorial or registered not both 3250 Floating node found node name The fitter found a node node name that 1s not defined 3251 Combinatorial feedback before a register is not a valid feature You cannot use the input to a register as feedback for your design 3252 Inverter after T JK SR flip flop is not synthesizable lt signal name gt T JK SR flip flops do not support inversion 3253 Cannot enable GTS Pin already assigned to lt signal name gt You cannot
145. ew Options Anchor Help Create Change View Simulate Until File Signals Events Save Run Bus Value Full_Screen 10000000 1000000 2000000 3000000 2000000 5000000 6000000 7000000 5000000 9000000 10111213141516171519 38 Status Project RSPLASERAMPLESBCDSBCD MET Completed Loading lt BCD RES gt Figure 33 Description of Simulator menus As can be seen in Figure 34 the XPLA Designer simulator operation is controlled via the waveform viewer menu and toolbar 2 14 BCD RES Edt View Options Drop Anchor Help Events Create Change View Simulate Until File Signals Save Run Bus Bus Value Full Screen 10000000 nsec Figure 34 The menu bar consist of the following items 67 File Edit View Options Drop Anchor Help FEB XPLA Sim 2 19 5 Edt View Options Anchor Help i Create Change View Simulate Until Bus Bus Value Full Screen 10000000 nsec Save Save Hun Print Exit H 1 1 PO Figure 35 Under File there are eight additional items which are New This command allows the operator to start a simulator waveform viewer window without using the SCL file generated when a particular design 1s compiled Open
146. ewer window A signal can have any valid name of eight characters or less See Figure 37 for details 70 Adding Signal Signals Enter the name of a signal to display by either 1 Selecting an existing signal name from the list ar 2 Entering a new signal name and selecting a position Far iE on the display Figure 37 Del Signal This command will allow the operator to delete a signal from the waveform window When this command 15 selected the message Click on the row which you wish to delete will appear in the project status window of the waveform viewer The signal will be deleted from view if you answer yes to the safety prompt otherwise it will remain visible The project status box 1s located at the bottom of the waveform viewer window see Figure 3 Blatuzs o Project DS ww RPLASERAMPLESBEDSBUD NET Click On The Row Which You Wish Delete Figure 38 Add Event This command will allow the operator to add signal events 1 logical highs or logical lows to a named signal Click on the signal at the time position at which you want the 71 new transition to occur If the signal was high it will go low If the signal was low it will go high If the value of the signal 15 unknown or tri state it will go low Continue adding events to the original signal or different signals until you are finished then click the OK button When selected the project status wi
147. falling or rising edges of these clocks These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity There are 2 clocks CLKO and CLKI available on the PZ3032 PZ5032 devices and 4 clocks CLKO through CLK3 available in the PZ3064 PZ5064 and PZ3128 PZ5128 devices Clock 0 in each of these devices 15 designated as the synchronous clock and must be driven by an external source Clocks 1 2 and 3 CLK1 CLK2 and CLK3 can either be used as a synchronous clock driven by an external source or as a asynchronous clock driven by a macrocell equation 17 GTS EA CEKO CT2 GND CLKO 5 odd CLK1 5 Vcc GND Figure 5 Two of the control terms CTO and are used to control the Preset Reset of the macrocell s flip flop The Preset Reset feature for each macrocell can also be disabled The other 4 control terms CT2 CT5 be used to control the Output Enable of the macrocell s Output Buffers The reason why there are so many control terms dedicated for the output enable of the macrocell is to insure that all CoolRunner devices are PCI compliant The macrocell s output buffers can also be always enabled or disabled All CoolRunner devices also provide a Global Three State GTS pin which when pulled low will three state all the outputs of the device This pin is provided to support Circuit Testing or Bed of Nails
148. first four of these five design steps and also supports the final step by producing a JEDEC file which can be used by most industry programmers to configure the device The XPLA Designer also produces Verilog and VHDL timing models which can be used in board level simulations This manual provides an overview of the XPLA Architecture and a quick tutorial on how to use XPLA Designer to assist the reader in becoming familiar with Philips CPLDs and the XPLA Designer respectively The explanations and examples used in this manual assume that the user has at least some familiarity with Microsoft Windows and CPLDs This manual is intended to be both a reference manual for experienced users and a comprehensive instruction manual for beginners Each section of this manual describes a step of the design process used when targeting Philips CPLDs Examples in each section illustrate the concepts being discussed Depending on your level of experience you may wish to read through the entire manual or to study only specific sections Supported Devices XPLA Designer software version 2 1 supports the following devices PZ3032 32 macrocell 3 3 Volt CPLD PZ5032 32 macrocell 5 Volt CPLD PZ3064 64 macrocell 3 3 Volt CPLD Preliminary Timing Model PZ5064 64 macrocell 5 Volt CPLD Preliminary Timing Model 73128 128 macrocell 3 3 Volt CPLD Preliminary Timing Model PZ5128 128 macrocell 5 Volt CPLD Preliminary Timing Model The CPLD Design Pro
149. gn The general syntax for including a title is TITLE title text where TITLE is a reserved word and title text is the string you want for the design title Property The property statement specifies information about the design to the compiler For example if you want to activate the global three state pin you would include the Statement XPLA PROPERTY dut on in the header section Declarations Section Constants Constants are identifiers that keep their value throughout the module To declare a constant type the constant name followed by the sign and then the value you want to assign Multiple constants may be assigned on one line For example 1 0 max_count hFFFF assign constant values of 1 and to identifiers and the hexadecimal value FFFF to the constant max count Variables 39 Variables are shorthand references to groups of other identifiers Lines 16 and 17 of Figure 22 show examples of variables The identifiers cal5 through 0 and cb15 through cbO declared in lines 13 and 14 represent the 16 bits of each counter and are assigned to pins The variables ca and cb are assigned to the strings of counter bits and can be used to simplify the logic description section Consider line 21 of Figure 22 Because of the variable declaration on line 16 clocks can be assigned to all the counter outputs with the single line ca clk clk If the variable ca had not been dec
150. gram Description The phrase state diagram 1s used 1n PHDL to indicate the start of a state machine design definition For more information refer to the state and if then else sections of this chapter and to the logic description section of chapter 5 Syntax state diagram q1 q0 state 0 0 state description state 0 1 state description state 1 1 state description 128 State indicates the state that is being defined and state description is where the outputs and state transition logic are created Note that state_diagrams must use sequential registers in PHDL for representation of the different states The state transition logic must use the goto or if then else structure Example Module diagram Title Example showing state diagram inl in2 pin clk pin out pin istype 51 52 53 node istype equations out c clk Sl c clk s2 c clk 53 clk state_diagram 51 52 53 state 0 0 0 out 0 if in1 1 then 0 0 1 state 0 0 1 out 1 if 101 1 then 0 1 0 state 0 1 0 out inl if 101 1 then 0 1 1 state 0 1 1 out inl if 101 1 then 1 0 0 state 1 0 0 out 1n2 if 101 1 then 1 0 1 state 1 0 1 out in2 if 101 1 then 0 0 0 state 1 1 0 goto 0 0 0 state 1 1 1 goto 0 0 0 then Description 129 The keyword then is part of both the if then else structure and the when then el
151. h level implementation of 16 to 8 multiplexer 7 0 pin b7 b0 pin y7 y0 pin sel pin a7 a0 b b7 b0 7 01 equations y sel amp a amp b end 211 MODULE m41 2 title Dual 4 to mux 13 10 bi3 b10 pin asl 50 pin bs1 bsO pin ao pin bo pin al a13 a10 bi bi3 b10 equations lasl amp 50 amp las amp asO amp ail asl amp as0 amp ai2 asl amp as 4213 bsl 42 1650 amp bi 1651 amp 650 amp bil 651 amp 1550 amp bi2 651 amp bsO 42 END Dual 4 to 1 Mux 212 Datapath Circuit Two reps module p1 Datapath circuit Two reps 4 1 8 bit mux feeds 8 bit data reg which feeds 8 bit shift register This 15 simular to Prep 1 Inputs CLK RST S1 S0 OE_IDO SL_ID15 pin IPD7 IPD6 IPD5 IPDA IPD3 IPD2 IPD1 IPDO pin ID7 ID6 ID5 IDA ID3 ID2 ID1 pin IDI4 IDI3 IDI2 ID11 ID10 IDO9 IDS pin Outputs Q7 Q6 05 04 03 Q2 01 Q0 pin istype buffer reg_d last instance shift register R7 R6 R5 R4 R3 R2 R1 RO node istype buffer reg last instance register B7 B6 B5 B4 B3 B2 B1 BO node istype buffer reg d first instance register C7 C6 C5 CA4 C3 C2 C1 CO node istype buffer reg d first instance shift register B B7 B6 B5 BA4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SC C6 C5 C4 C3 C2 C1 C0 C7 R R7 R6 R5 R4 R3 R2 R1 RO0 DO
152. he XPLA Designer will accept as input The most commonly used is the phd format which is the extension appended to files written in PHDL The other formats are tt2 and blf These formats are somewhat standard throughout the industry and are generated by many different tools In certain cases these formats can be taken from other tools and fit directly into Philips parts If you are trying to load a file in one of these formats and are having difficulty fitting it into a Philips CPLD contact the applications support group listed in chapter 1 for assistance When you first start XPLA Designer the project you last worked on is automatically loaded If you wish to start a new project or load a different project than the one that was automatically loaded follow the instructions in the sections below 37 Starting a New Design Select New Design from the Design menu in XPLA Designer as Figure 23 The New Design window will appear Navigate to the directory where you want to store the new design or create a new directory by clicking on the Create Dir button Enter the name you wish to call the design and press enter or select OK Select OK when you are prompted to create the new file for the project The XPLA Design Editor will open up with a blank file template ready for use Enter your design and save your work before exiting the Design Editor Panel Project TBIRD View Help Design Open De
153. he stimuli file 2 Subroutine declarations cannot be nested 3 Before a subroutine can be called it must be declared 4 Subroutine names must be unique 5 Subroutines can contain only local jumps Labels declared inside a subroutine are unknown at the outside After the end of a subroutine declaration all jumps are tested for correctness Jumps that are not local that 15 where the label mentioned Is unknown to the subroutine will result in an error message Subroutine call nesting depth is limited to 20 These commands belong to subroutines only SUB RET END 142 Data Fields A data field consists of data lines between the keywords DATS and DATE No other commands should be inserted the data field More than one data field can be declared The data lines are collected to form one big data field 4 Each data field starts with the default data base BIN binary 5 The data values are stored as 32 Bit values 6 These commands belong to data fields DATE DATS DATV SDC INCR Variables 1 After using the finish command all variables are checked to see that they have been UJ assigned a value If not an error message is written in design err together with their names These commands assign a value to a variable DATV SETV Variables are 32 Bits long The following commands can be used with variables DATV DECV IF IFV INCR PV SETV Jumps and Labels 1 Labels are local to a sub
154. he table To shorten truth table entries PHDL supports don t care conditions which may be entered in place of signal states This eliminates the need to specify every possible signal state when the output values will be the same for several different input states The don t care condition is entered as a X in place of the 1 or 0 that would have normally been entered The example that follows illustrates how to use don t cares The following example is a second implementation of the T Bird Tail Lights design that uses a combination of a state diagram and a truth table In this design the state diagram controls only the state transition logic and the truth table determines the output of the design by taking into account both the inputs and the current state Note the use of don t cares in the truth table 61 10 15 20 25 30 35 40 45 MODULE tbird TITLE thunderbird tailight demo BRAKE pin TL pin TR pin CLK pin L1 L3 istype R1 R3 pin istype reg q2 q0 pin istype out L3 L2 L1 R2 sreg q2 ql 0 50 0 0 0 sl 10 0 1 s2 0 1 0 s3 0 1 1 s4 11 0 0 55 1 0 1 56 1 1 0 7 1 1 1 equations sreg clk CLK out clk CLK state diagram sreg state 50 if TL then 61 else if TR then s4 else 0 state 61 if TL then s2 else if TR then s4 else 50 State
155. his case if expression 1 is true equations_1 will be evaluated but if expression is false and expression 2 is true equations 2 will be evaluated If both expression and expression 2 are false then equations 3 will be evaluated State Diagrams State diagrams are used to implement sequential state machine designs Whenever state diagrams are used they must begin with the reserved word state diagram The general syntax for a state diagram 1s state diagram x y state a b 55 equations state transition logic state c d equations state transition logic state e f equations state transition logic The state diagram uses registers x and y to keep track of the current state The states determine the design outputs for the current state and also what the next state will be based on the state transition logic Whenever there is a change in the design stimulus logic functions determine the new state of the design and the outputs are set appropriately For example if x and y were equal to a and b respectively then the current state would be state a b The outputs would be determined by the equations in state a b and the state transition logic would determine what would be the next state On the next clock edge the state registers would transition to the next state and the outputs would then take on values determined by the equations in that new state The state transition logic of the new state would determi
156. ify a larger value for the Maximum Product terms per Equation If fitting the design is perceived to be an issue density problem and speed is not as important then the user should specify a smaller value for the Maximum Product Terms per Equation Activate D T register synthesis The Activate D T register synthesis selection instructs XPLA Designer to minimize the number of product terms using either D or T Type flip flops When the selection is activated the software will implement each equation using all D or all T Type flip flops and it will pick the flip flop type that requires the minimum number of product terms If the number of product terms are the same with either implementation the XPLA Designer will default to a D Type flip flop If this selection 1s not activated the XPLA Designer will use the type of flip flop specified in the PHDL source code If the register type 15 not specified in the PHDL source code the XPLA Designer will default to a D Type flip flop Auto Node Collapse Mode The Auto Node Collapse Mode is used to minimize the number of passes through the logic array by collapsing internal nodes into other logic Collapsing the node frees a macrocell at the expense of using more PLA terms thus maximizing design performance because one pass through the PAL and PLA arrays 15 faster than multiple passes through the PAL array When the Auto Node Collapse Mode 15 used the compiler will attempt to collapse all interna
157. ignal is assumed by the compiler to be a combinatorial signal when the colon equal assignment is used the signal 15 assumed to be a registered signal It is recommended for design clarity that you specify all signals with attributes in which case the assignment operators are equivalent Example Module equat Title Example of reserved word equations a b c d pin clk pin out out2 pin istype com out3 out4 pin istype equations out3 c clk out4 c clk outl a amp b c amp d out2 last b c d 115 when a 1 then out3 d b amp else out3 d out3 q out4 outl com amp a b end goto Description The goto statement is used in a state diagram to force a state transition to a specified state Goto is often used as in the example below to transition out of unspecified states Syntax goto specified_state Specified_state 1s the specified state for the unconditional transition Example Module goto_ex Title Example of state transition with goto statement pin pin pin istype com 51 50 node istype reg equations 50 clk Sl c clk state diagram 51 50 state 0 0 out 0 if in 1 then 0 1 state 0 1 out 1 if in 1 then 1 0 state 1 0 out 1n if in 1 then 0 0 116 state 1 1 goto 0 0 if then else Description The if then structure is used state diagrams to specify
158. igns were able to route with the pins fixed after the design was changed The reason why the XPLA architecture accommodates last minute design changes is because the PAL product terms are dedicated to a given macrocell and in addition there is a free pool of 32 PLA product terms which can be used by any of the 16 macrocells If a macrocell uses less than 5 product terms and the design change requires a total of 5 product terms the design is guaranteed to fit because the 5 PAL product terms are dedicated to each macrocell There is no borrowing between macrocells Borrowing is a nice feature until the macrocell whose product terms were borrowed wants its product terms back because of a last minute design change If a design change requires more than 5 product terms unused PLA product terms are used by the macrocell In an average design less than 20 PLA product terms are used so there are typically 12 PLA product terms available to implement last minute design changes Macrocell Configuration Figure 5 shows the architecture of the macrocell used in the CoolRunner family The macrocell consists of a flip flop which can be configured as either a D or T type A D Type flip flop is generally more useful for implementing state machines and data buffering A T Type flip flop is generally more useful in implementing counters All CoolRunner family members provide both synchronous and asynchronous clocking and provide the ability to clock off either the
159. ile Included with the Philips XPLA Designer is a help menu The help menu can be activated via the Help Pull Down Menu in the XPLA Designer Interface and contains most of the information available in this manual Technical Support No documentation ever written can cover every conceivable concern a customer may have Applications Engineers are available who are dedicated to making you successful in using Philips CoolRunner CPLDs Should you have any questions regarding this product or our CoolRunner CPLDs please contact us for assistance via any of the methods listed below Philips Semiconductors Programmable Products Group Applications 9201 Pan American Freeway NE Mail Stop 08 Albuquerque New Mexico 87113 Phone 1 888 COOL PLD Toll free in the USA Or 1 505 858 2996 Fax 1 505 822 7804 email coolpld scs philips com World Wide Web http www coolpld com 12 Chapter 2 Installing XPLA Designer System Requirements It is recommended that your system have the following as a minimum for using XPLA Designer 486 PC running at 33 MHz or better o Megabytes of RAM 6 Megabytes of free disk space Microsoft Windows 3 1 or later and Win32s included on the XPLA Designer CD ROM or Microsoft Windows95 recommended see appendix Z for comments Installing From CD ROM Insert the XPLA Designer CD into your CD drive From the Windows Program Manager select File Run Enter DRIVE cdsetup exe in
160. ill result in A set to 1 B set to 1 set to 0 D set to 1 Next the data counter 15 automatically set to 5 ST DATA A B C D will result in A set to 1 B set to 1 C set to 0 D set to 1 Next the data counter 15 automatically set to 5 ST DATA A B C D will result in A set to 1 B set to 0 C set to 0 Last State is repeated D setto0 SU Simulate Until SUB Start of a Subroutine Declaration Format SUB lt subname gt This is the first statement of a subroutine The lt subname gt is a string of at most 12 alphanumeric characters starting with a letter It identifies the subroutine and must be unique 157 The subroutine facility enables the user to execute some SCL statements several times in difference parts of the file by calling them by the subroutine name A subroutine declaration is not allowed within a subroutine but one subroutine may call another Notes 1 The simulator requires that all subroutines be declared at the beginning of the program 2 If subroutine SUBI calls subroutine SUB2 then subroutine SUB2 must be declared somewhere above subroutine SUB1 SUNS Simulate Until the Network is Stable There are three possible formats 1 SU TIME stop time Stop time absolute time slot can be constant or a variable 2 SU TIME delta time Delta time number of time slots after the current time slot 3 SUNS In case 1 above simulation starts at the actual time slot and
161. ip on output pins they are available internally to only the design For example the registers used to keep track of the current state of a state machine are often required only by the internal design and external devices do not need this information Nodes can be assigned to a macrocell associated with an I O pin or to a buried macrocell Nodes assigned to I O pin macrocells do not propagate the signal through the output buffer to the output pin of the device The syntax for assigning a signal as a node 1s node name NODE node number ISTYPE attr attr 45 where node_name is the name of the signal NODE 1s a reserved word node_number is the optional specification of which macrocell you wish to assign to the node ISTYPE is a reserved word and the variables attr are attributes that specify the signal format of the node For example the line state7 state NODE ISTYPE reg keep specifies the creation of eight buried nodes that are registered and will not be collapsed during synthesis Note that the node number specification 1s left blank in this example This will cause the software to automatically assign the nodes to macrocells The nodes that the signals are assigned to can be controlled by specifying the appropriate node number associated with the macrocell where you want the node to be See appendix B for node numbers The attr variables are used with the reserved word ISTYPE to set the format of the node The node attribut
162. irety by the Philips Programmable Products Applications group Originally we planned to use a professional technical writer to produce this documentation but a number of us had suffered grievously through trying to use documentation that was written by people who had never used the product and in fact had little clue about what the product does Thus we chose to suffer grievously through the process of creating this manual instead of taking the easy way out In the hope of producing something that would be useful to real engineers This manual was written using MS Word 6 0a and most sections were created running Windows 3 11 The entire thing was compiled and final edited using MS Word 6 0a running on Windows95 The editor would like to thank Bill and his minions at Microsoft for releasing an OS that can actually open a document file that is larger than 1OMb without crashing Adobe Acrobat 2 1 was used to generate the pdf file to allow paperless distribution of this manual We thought it would be nice to let you know a little about the people that created this tome Below are what they submitted written in their own words Maybe this wasn t such a good idea after all The Editor Mark Aaldering is the Applications and Architecture Development Manager for Philips Programmable Products group He has held various positions in the Programmable Logic Field for over ten years In the creation of this manual Mark was responsible for th
163. istor If this 1s not the case the simulator produces an undefined state BUSO Switch Bus Line to Output Format BUSO signal list Only NETIO signals output of bus function are allowed The output of a bus line with a name that occurs in the signal list is changed to the output state condition In this situation the simulator checks whether a forcing external stimulus is applied to that node If this 1s the case the simulator produces an undefined state Note Atthe beginning of simulation all bus lines are treated as ordinary signals and can be forced to any state designed A check is made after the first appearance of either BUSI for BUSO It is good practice to give a BUSO command for all NETIO signals at the very beginning of the simulation CALL Subroutine Call Format CALL subname This 1s used to execute a number of SCL statements specified by the subroutine subname Subroutines must be declared before their call DATE End of data lines Data lines must appear between these two keywords and must not be interrupted by other commands Data line information starts after column 1 If several data strings occur in the same line they must be separated by a slash The data must be given in the following data bases 145 Keyword 00 It is possible to switch between these data bases If no data base is given BIN is assumed as the default data base It is possible to have several data fields Every new field
164. it the PHDL code 2405 The following signal s form a combinational loop Break the combinatorial loop in the PHDL code 2420 Preset and reset can not both be assigned to a signal Please delete either the preset or reset port attached to the signal 2430 Equation with INVERT type Normalized to equivalent active high logic Power up value has been changed Verify that polarity of the signal is correct 2490 Test vectors are not supported This section is ignored The design can be simulated using XPLA Designer 2500 Warning near line numbers Directive not supported in this release Ignored This directive is not supported in PHDL 2510 Trace statement not supported in this release Sections ignored The design can be simulated using XPLA Designer 236 2600 Control signals has lt gt pterms Converted to one Verify that the functionality of the control term is as intended 5180 line NOT operator is ignored in port connection Verify the functionality of the port is the correct polarity If not re name the signal and re write the right hand side of the equation 5190 line In hierarchial design a module cannot have a default value Remove default values 1n the interface and or functional block records in the PHDL source 5195 Output port does not have a connection Verify that the output is unused If the output is used add logic to connect the port 5202 A sub module cannot have a default val
165. k 15 set on time slot 0 Note The IT command must appear only once at the beginning of the program Otherwise it 1s treated as ST Example IT 01 AI B C D result 0 B C D l all others at unknown Note All NETIN signals primary inputs should be initialized at the beginning LIST Listing of Signals with State 7 Format LIST specification specification UNDEF OR NOTDET Writes list of all signals that are currently not determined or not defined When the LIST statement in a stimuli file 1s read all signals which have the specified state are listed in the file design err List is blank means that no signals meet the condition 152 Example SU TIME 10000 LIST UNDEF LIST NOTDET Contents of lt design gt err LIST UNDEF Undefined signals at timeslot 100000 signall signal2 signal3 signal4 signal5 signal6 LIST NODET Unknown signals at timeslot 10000 List is blank RET Return From Subroutine Format RET This is only used within a subroutine When executed control 1s passed to the next statement after the subroutine call S Sequence Format 5 initstate timel time2 lt signal list gt S initstate timel time2 ETC signal list The sequence command causes a series of signal changes dependent on the simulator clock initstate O or lt timei lt timei 1 time relative to current simulator time
166. l Language Input Format ce eneral Information about Stimuli ubroutines ata Fields ariables umps and Labels CL Keyvvord Summary CL Keyvvord Definitions BUSI Switch Bus Line to Input State BUSO Switch Bus Line to Output CALL Subroutine Call DATE End of data lines DATS start of data lines DATV assign Data Lines to a Variable DECV Decode a Variable END End of a Subroutine Declaration GT Goto Statement c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c sss 100 100 sul 101 OL tec OL 77 106 109 NIS iss s 4 vint ALO INS ilz on s s 124 s s 24 ere E25 126 our D27 m p a 2D s s l l asa 192 l 138 00 140 142 255 27 143 144 ss 144 cc 144 MA 146 LAG 148 2149 edd I I S Cate mn Cit tain E dia ahd 150 TEV Condition Check on
167. l nodes except those that have the keep attribute specified When the Auto Node Collapse Mode is not used the compiler will not attempt to collapse any internal nodes unless the collapse attribute has been specified Fitter Option Examples The following subsections give design examples of how the fitting options can be used to optimize the design to meet the user s individual needs Constraining Pins and Nodes Example One of the features of Philips CPLDs is that you can route virtually 100 of all designs with all pins locked and all of the macrocells and pins used This ensures that you can 101 lock the pins early in the design without having to worry about making changes in the logic that will affect keeping the pinouts fixed The method to fix the pinouts for a design is to assign a pin number to each input and output in the PHDL source code and specify the Keep selection on the compiler options screen To lock a pin in a PHDL source specify the desired pin number in the declarations section The following example shows how to lock the pins for a dual four bit adder Pins al through a4 will be on pin numbers 5 8 SYNC CLK will be on pin 9 and so on MODULE adder TITLE Two four bit adders DECLARATIONS Inputs 1 4 b1 b4 PIN 5 6 7 8 11 12 13 14 SYNC_CLK PIN 9 inl in2 PIN 1 2 Outputs sync_out1l sync_out4 PIN 31 32 33 34 ISTYPE reg_d buffer async_outl async_out4 PIN 36 37 38
168. lare a signal as type node Refer to the signals section in chapter 5 for more information on nodes Syntax 124 signal name node istype attributes Signal name is the name assigned to the signal and attributes are identifiers that determine the type of signal Refer to the istype description for more information Example Module node ex Title Example of node use inl in2 pin clk pin out pin istype com nl n2 node istype equations nl c clk n2 c clk state diagram nl n21 state 0 0 out 0 if in1 1 then 0 1 state 0 1 out 1n2 if 101 0 then 1 0 state 1 0 out 1 if 112 1 then 1 1 state 1 1 out inl if 102 0 then 0 0 pin Description The reserved word pin is used to declare a signal as type pin Refer to the signals section in chapter 5 for more information on pins Syntax signal name pin istype attributes 125 Signal_name is the name assigned to the signal and attributes are identifiers that determine the type of signal Refer to the istype description for more information Example Module pin_ex Title Example of pin command clk pin pin istype com pin istype equations hec cik 4 e a tb c f i a amp c bk amp Cc end property Description The property statement specifies information about the design to external programmers like the compiler Property
169. lared line 22 would have to be replaced with the following 16 lines to achieve the same result cal5 clk clk cal4 clk clk cal3 clk clk cal2 clk clk call clk clk calO clk clk ca9 clk clk clk ca7 clk clk ca6 clk clk ca5 clk clk ca4 clk clk ca3 clk clk ca2 clk clk cal clk clk 0 clk Macro Functions Macro functions are useful for including functions in a PHDL file several times without having to retype the code each time the function is used One can think of a macro as a pre defined function that can be called many times each time with different signals For example if a design used three separate eight bit to three bit encoders you would not want to have to retype the encoding definition three separate times You could instead define the encoding in a macro and then call the macro three separate times with three separate sets of signals The following example illustrates this concept 40 10 15 20 29 30 35 40 Module macrotst Title Using macro to for three separate 8b to 3b encoders DECLARATIONS Eight bit inputs to encoders 7 0 pin b7 b0 pin c7 cO pin Three bit encoded outputs aout2 aout pin istype com buffer bout2 boutO pin istype com buffer cout2 cout pin istype com buffer Create the macro encode macro a7 a6 a5 a4 a3 a2 a1 a0 aout2 aout1 aout0 truth table 7 6 5
170. lse rfust7 if RFSTARTn then rfustO else if rflst rflst15 then rfust9 else rfust8 if then rfustO else if rflst rflst15 then rfust10 else rfust9 if then rfustO else if rflst rflst15 then 1 else rfust10 if then rfustO else if rflst rflst15 then rfust12 else rfust1 1 if RFSTARTn then rfustO else if rflst rflst15 then rfust13 else rfust12 if RFSTARTn then rfustO else if rflst rflst15 then rfust14 else rfust13 if then rfustO else if rflst rflst15 then rfust15 else rfust14 if RFSTARTn then rfustO else rfust15 if RFSTARTn then rflstO 229 State rflstl State rflst2 State rflst3 State rflst4 state rflst5 State rflst6 State rflst7 state rflst amp State rflst9 state rflst10 state rflst11 state rflst12 state rflst13 state rflst14 state rflst15 end else rflst1 if RFSTARTn then rflstO else rflst2 if RFSTARTn then rflstO else rflst3 if RFSTARTn then rflstO else rflst4 if RFSTARTn then rflstO else rflst5 if RFSTARTn then rflstO else rflst6 if RFSTARTn then rflstO else rflst7 if RFSTARTn then rflstO else rflst8 if RFSTARTn then rflstO else rflst9 if RFSTARTn then rflstO else rflst10 if RFSTARTn then rflstO else rflst1 1 if then rflstO else rflst12
171. lst9 hb rflstlO Aha rflstl1 h2 rflst12 h6 221 rflst13 h4 r lst14 h5 rflst15 hd x x Don t Care z 2 High Impedance c c Clock u u Undefined equations rfust C IMPCLK rfust OE rfust AR IMPRSTn rflst C IMPCLK rflst OE OEn rflst AP MPRSTn RFTIMEn C IMPCLK RFTIMEn OE OEn RFTIMEn AP 0 IRFTIMEn rfust rfust15 amp MPRSTn STATE DIAGRAM RFUSMST3 RFUSMST2 RFUSMSTI RFUSMSTO state rfustO if RFSTARTn then rfustO else if rflst rflst15 then rfustl else rfustO state if RFSTARTn then rfustO else if rflst rflst15 then rfust2 else rfustl1 state rfust2 if RFSTARTn then rfustO else if rflst rflst15 then rfust3 else rfust2 state rfust3 if RFSTARTn then rfustO else if rflst rflst15 then rfust4 else rfust3 State rfust4 if RFSTARTn then rfustO else if rflst rflst15 then rfust5 else rfust4 228 State rfust5 state rfust6 state rfust7 state rfust8 state rfust9 state rfust10 state rfust11 state rfust12 state rfust13 state rfust14 state rfust15 STATE DIAGRAM RFLSMST3 RFLSMST2 RFLSMSTI RFLSMSTO state rflstO if RFSTARTn then rfustO else if rflst rflst15 then rfust6 else rfust5 if RFSTARTn then rfustO else if rflst rflst15 then rfust7 else rfust6 if RFSTARTn then rfustO else if rflst rflst15 then rfust8 e
172. m maximum is set to 6 Because the equation has more than 6 product terms it cannot be implemented in one macrocell After fitting the equation would be broken into two parts and implemented something like BURIED_NODE A B C D E OUT BURIED_NODE F G H which would now require two macrocells and would slow down the speed at which the design would be able to run due to the fact that resolution of signal OUT now requires two passes through the logic array For each stage of buried nodes that would need to be created to meet the P term limit set you must add a to the Tsu of the final output for timing If the P term limit were changed to 8 no internal node will be created and the design will run at a faster speed because only one pass through the logic array 15 required to resolve the signal OUT Now consider the case where a large percentage of the macrocells require large sums of product terms Because of the way the fitter allocates the product terms the P term limit setting will determine if the design will fit in the part When fitting the design the first thing the Philips fitter does 1s create sums of products logic equations based on the maximum width specified in the P term limit property The first five product terms for each output are implemented in the dedicated terms of the PAL array and the remaining terms are taken from the PLA array Each product sum is implemented by combining those PAL and PLA terms If all of the PLA
173. mp 2 0 1 1 109 endcase state 0 1 out 0 out2 1 case inl 0 1 0 endcase state 1 0 out 1 out2 0 case in2 0 0 0 11 1 amp in2 1 endcase state 1 1 0011 1 0012 1 case 112 111 0 0 endcase declarations Description The declarations statement is an optional word that may be placed near the beginning of the PHDL source file to indicate the start of the declarations section The declarations section is where constants variables macro functions and signals are declared Refer to chapter 5 for more information Syntax declarations constants variables macro functions signals The constants variables macro functions and signals are all optional but any source will have at least one of these Example Module declar Title Example of declarations declarations 110 a b c d pin out pin istype com invert equations out a amp b amp c d end else Description The keyword else is part of both the if then else structure and the when then else structure It is used to specify another result that should occur when conditions specified by the if or when statements are false For more information refer to the if then else and when then else commands this chapter Syntax if condition then state else state OR when condition then result else result For both cases
174. mp ql amp 140 143 amp q2 82 41 440 193 amp q2 amp 91 amp q 143 amp q2 amp ql amp 140 q3 amp q2 amp ql 140 q3 c q2 amp ql amp 40 q3 dc q2 amp q0 ql 143 amp 1q2 amp ql amp q0 193 192 amp ql amp q 193 amp 192 amp ql amp 140 193 amp q2 amp ql amp 140 q3 c q2 42 ql amp 40 q3 amp q2 440 q3 amp q2 amp 190 q3 amp 192 amp ql amp 1940 qO q3 amp q2 amp ql amp 190 143 amp 192 amp ql amp q0 lq3 amp q2 amp ql amp 140 143 amp q2 440 191 q3 amp q2 amp ql 140 q3 c q2 amp ql amp 40 q3 amp 142 amp 140 43 192 amp 941 8240 end gray4 192 Timer Counter module p2 Timer Counter Two 8 bit loadable registers mux counter and comparator This code is simular to Prep2 Inputs CLK RST LDPRE LDCOMP SEL DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Outputs O7 06 05 04 03 02 01 00 LOADO LOADI LOAD2 LOAD3 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LBO LA LA7 LA LA5 LA4 LA35 LA LA 1 LA l LB LB7 LB6 LB5 LB4 LB3 LB2 LB1 LBO0 pin pin pin istype buffer reg node istype buffer node istype buffer reg d node istype buffer reg DA DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO OUT 07 06 0
175. n 35 else when count_enab 1 then when dir 0 then 40 ca d ca q 1 cb d cb q 1 else when dir 1 then 45 ca d ca q 1 cb d cb q 1 50 else ca d ca q cb d cb q 55 END Figure 22 36 hi VU i Header Section The header section of a phd file contains descriptive information about the design This section must contain a name for the PHDL file and it can contain title and property statements The first three lines of Figure 22 make up the header section Declarations Section The declarations section is where constants variables signals and macro functions are declared and initialized Lines 7 through 17 of Figure 22 make up the declarations section for the dual counter design The start of the declarations section is indicated by the reserved word declarations placed by itself on one line and the declarations follow that Logic Description Section The logic description section is where the design is defined by establishing relationships between the inputs and outputs created in the declarations section The design may be defined using equations state machines and truth tables Lines 19 through 55 of Figure 22 make up the logic description for the dual 16 bit counter End Statement All PHDL files must close with the reserved word end as shown on line 56 of Figure 22 Creating and Editing PHDL Source Files There are three different file formats t
176. n if 102 0 then 1 1 else 0 1 else 1 0 out 1 if 101 0 then if 102 0 then 0 0 else 1 0 else 1 1 out 1 if 101 1 then if 102 0 then 0 1 else 1 1 else 0 0 out 0 if 101 0 then if 102 0 then 1 0 else 0 0 else 0 1 120 end istype Description The istype statement is used to attach attributes to pins and nodes PHDL design The attributes that are attached determine the format of the output signal attached to the pin or node The table below lists all available attributes associated with the istype statement and describes their function For more information refer to the section on signals in chapter 5 ATTRIBUTE DESCRIPTION Use non inverted output Collapse this signal during logic synthesis Combinatorial output Use inverted output keep Do not collapse this signal during logic synthesis Clocked memory element D type flip flop clocked memory element reg Gated D type flip flop clocked memory element JK type flip flop clocked memory element SR type flip flop clocked memory element T type flip flop clocked memory element retain Do not minimize this output Preserve redundant product terms Syntax signal name pin istype attributes OR signal name node istype attributes Signal name is the name assigned to the signal associated with the pin or node and attributes are f
177. n count_enab 1 then when dir 0 then ca d ca q 1 cb d cb q 1 182 END else else when dir 1 then ca d ca q 1 cb d cb q 1 ca d ca q cb d cb q 183 3 Bit Counter Module DEMO Title My first design 3 bit counter CLOCK RESET pin bit2 bitO pin istype count bit2 bitO equations count CLK CLOCK count AR RESET count count Q 1 end 184 16 Bit Gray Code Counter module gcntl6 title 16 bit gray code counter 415 40 pin istype clk pin rst pin count 915 90 equations count ar rst count clk clk 915 415 amp ql4 amp 1413 amp 1412 amp 1411 1410 amp q9 amp 198 amp q7 amp 190 q5 q4 q3 q2 amp 141 amp q0 415 914 c q13 amp q12 amp 411 amp 410 amp q9 amp q8 amp 147 amp 146 q5 194 q3 q2 amp 141 amp q0 q15 1414 amp q13 amp q12 amp q11 amp q10 amp q9 amp q8 amp 147 amp q6 q5 194 q3 q2 ql amp q0 415 1414 amp 1413 42 1412 amp 1411 amp 1410 amp q9 amp q8 amp 147 amp q6 amp 145 amp 144 z q3 amp 1q2 amp ql 4140 414 1415 414 amp q13 amp 1412 amp 411 amp q10 amp q9 amp q8 amp q7 amp 196 q5 194 q3 q2 amp 141 amp 140 1915 c q14 13 412621411 amp qlO amp 199
178. n is loaded correctly Program the device Record the checksum Verify the device x Your specific model programmer may operate differently than this simple example Please refer to the specific operating instructions that were included with your device programmer 31 Chapter 5 PHDL Language Overview The Philips Hardware Description Language PHDL is a high level design language used to create logic designs for Philips CPLDs Designs created using the elements of the language are synthesized by the XPLA Designer into gate level implementations that can be programmed into a CPLD The language supports equation state machine and truth table design entry formats This chapter details how to generate designs using PHDL and the various entry formats that are supported People who have never used PHDL before should read through this chapter and study the examples provided to get a feel for how to create designs using the language General Language Syntax PHDL sources are entered as text files through the XPLA Designer text editor The information provided in this section applies to all sections of the PHDL file words variables titles and syntax of the file are subject to the rules outlined here More detailed syntax descriptions and specific commands reserved words are provided in chapter 8 on language reference and more detail on the PHDL file itself is provided later in this chapter Identifiers Identifiers are the wo
179. ndow will display instructions on how to add events to signal lines and a large upward pointing arrow will appear indicating that you are in the ADD EVENT mode Figure 39 is an example of what you should see upon entering this mode EE XPLA Sim 2 19 BCD SCL JOf Edt View Options Drop Anchor Help Events Create Change View Simulate Until File Signals save Hun Bus Cik Bus Value Full Screen 10000000 nsec 1 2 4 151917 8 1 s 4 Status Project D SS wINRPLASERAMPLESBCDSBCD MHET Select a Signal 4nd Event Using The Cursor Continue selecting until all points are set then click Figure 39 Del Event This command will allow the operator to delete signal events 1 logical highs or logical lows to a named signal Click to the left of the transition you want to delete on the row of the selected signal The transition will be deleted When selected the project status window will display instructions on how to delete events from signal lines Figure 40 shows project status information for the Del Event option Status Project D SS vw RPLASERSAMPLESBEDSBED MHET Figure 40 14 Add Bus This command will allow the operator to create a bus signal from available signals and display it in the waveform viewer window Click at the position in the row of signals displayed in the waveform viewer where you want the bus signal to appear In the adding bus window a
180. ne what would become the next new state and the process would continue endlessly Only binary and decimal state representations are supported by PHDL The number of state registers declared after the state diagram key word must be able to support the number of states required for a given design For example two state registers can support a maximum of four different states and four state registers can support a maximum of sixteen different states Because the state registers consume one macrocell each you should use the minimum number of registers that will support your design In other words it is not recommended that you use five state machine registers for a three state design The state transition logic sections are created with the 17 then else structure the case statement or the goto and with statement Refer to the language reference chapter 8 for more information on each of these statements Each state must have a logical control structure that uses these statements to determine what the next state will be It is a good idea to put state transition logic in all states even those that are not used Unused states should return to a defined state in the state diagram so that the design 15 never stuck in an undefined state For example a five state design would require three state registers but would only use five of the eight possible state representations If the three unused states were left completely undefined and the state registe
181. ned which is displayed Change the cycle length from 1000000 ns to 200000 ns 27 Clock Settings Start Value Cycle Length 200000 Start At 1 Duty Cycle 50 Stark At 1 50 Done Cancel Maintain Duty Cycle Heset Using the mouse select the signal to which want to apply the parameters Figure 16 eB XPLA Sim 2 14 TEIRD SCL He Edit View Options Drop Anchor Help File Signals Events Create Change View Simulate Until Bus Cik Bus Value Full Screen 10000000 nsec 1000000 2000000 3000000 14000000 5000000 6000000 5000000 3000000 a 5 5 s a a a 5 mo wx Xxx cwm a a s a s a a s a a a a a a a a oov A a RR MC CCC CU ale al PE EE EE DX
182. nical support line for help Logical and Fatal errors as well as warnings indicate that there is a problem with your design or the way you are trying to fit the design These are generally descriptive enough that you can correct the problem and re compile and fit the design after it has been corrected Warnings 3211 Synchronous signal converted to asynchronous Indicates that you were trying to drive a synchronous clock with a signal generated in the logic These signals can only drive asynchronous clocks 3212 Power up reset signal is changed to non inverted output When inverted outputs are specified they will revert to the standard low state after power up reset 3213 Power up preset signal is changed to non inverted output When inverted outputs are specified they will revert to the standard high state after power up preset 3224 Reset Preset cannot be connected to Vpp You should not wire the reset or preset function to Vpp The devices are automatically reset preset at power up 3240 Unable to route fixed pinout Now using automatic pin assignment Indicates that the design could not be routed with the specified pinout and that the software automatically unlocked the pins and routed the design 3242 Unable to partition fixed pinout Now using automatic pin assignment Indicates that the logic could not be partitioned into the logic blocks with the specified pinout and that the software automatically unlocked the pins and ro
183. njoys deep sea diving but has had little opportunity to enjoy this activity in New Mexico Reno always notifies the local Search and Rescue Authorities before pursuing this activity in The Land of Enchantment Lester Sanders an industry veteran wrote the bulk of this manual and graciously shares credits with the parasites also in the picture After all Luc Longley also got a ring But think about it The biker looking dude is Chris Schell While his new beard isn t as permanent as Mr Gorbachev s spot he still hasn t shaven Mr Baker 15 still a fan of Philips early DOS based software called SNAP some people are easily amused Any mistakes or questions on sections which read as they were written by an amateur should be directed to Mr Sanchez Any reader managing to get help from Mr Sanchez should contact Mr Aaldering Any reader managing to get water out of a rock should contact the true author of this manual Chris Schell Barely 17 Chris is the youngest and most congenial member of our group He tells us 1 attribute my fine customer service to the unique brand of people skills I learned when I was a professional wrestler In fact I used those skills to convince Bubba that pro wrestling 1s indeed real New to the semiconductor industry Chris enjoys the travel to exotic places like Omaha and Buffalo I don t think there are any motels with magic fingers in Albuquerque he explains I had know idea how big
184. ntains device and package specific timing information that is passed to the simulator This timing information is incorporated into the signal display when the simulation is run When you use the anchor feature to measure delays they will accurately represent those you should expect the actual part to produce There are other features in the XPLA Designer Simulator that have not been mentioned in this overview Now is the time to play with the simulator and discover the many features it contains You will find the simulator to be intuitive fast powerful and every easy to use e SCL Brief Philips SCL simulation control language 1s divided into three major sections 1 Data Control Statements 94 Statements that handle signals data and variables 2 Flow Timing Statements that control the simulation flow and timing 3 Print Control Statements Statements that control the data to the output file DESIGN RES Figure 79 and Figure 80 contain a list of data control statements their descriptions and formats Initialize IT init list lt sign list gt INCR lt variable gt value IFV IFV lt var gt lt rel gt lt value gt lt SCL gt BUSI Switch Bus to Input State BUSI lt signal list gt BUSO Switch Bus to Output State BUSO signal list Figure 79 Mu DATS Start of Data Lines DATS DATE End of Data Lines DATE DATV Ass Data Lines to Variable DATV lt variable list gt
185. ntax of the pla format supported by XPLA Designer 2317 File file line numbers error names list There is an error in the BLIF source Regenerate the BLIF file 2318 File lt file gt line lt numbers error fanin number In the PLA or BLIF source the number of fanins listed 1s different than the number of fanins Regenerate the BLIF file 2320 File lt file gt line number Output can only has one digit lt number gt is found The output values in PLA or BLIF covers can have a value of 1 or 0 Regenerate the BLIF or PLA file 2321 File lt file gt line numbers Error output format must be 1 or In PLA or format outputs in the covers must be 1 or 0 Regenerate the PLA or BLIF file 2322 File lt file gt line numbers Output has been previously defined The output in the PLA or BLIF file is listed more than once Regenerate the PLA or BLIF file 2324 Input has been previously defined The input in the PLA or BLIF file is listed more than once Regenerate the PLA or BLIF file 2326 Error near line numbers Signal multiply defined The signal in the PLA file has already been defined Regenerate the PLA file 2328 Signal is not declared near line lt number gt The signal in the PLA file 1s not declared Regenerate the PLA file 2330 File lt file gt line lt number gt Module already defined The module in PHDL file has been defined Edit the PHDL file 2335 Syntax error in file
186. o a command line interface to the simulator for use with simulation vector files this is useful for designs that have more stimuli than can be conveniently entered with waveforms refer to chapter 6 for 26 zal more information The simulator 1s capable of doing both functional and timing simulation EE XPLA 5im 2 1d TBIRD_SCL depending on whether you simulate before or after you fit your design into a specific target device Since you have already fit this design to an 8nS PZ3032 you will do an AC timing simulation of your finished design Help Drop Anchor View Options File Edit Simulate Until Signals File cn a2 wo DAS WwNSRSPLSSERSASMPLESTBIRDSTBIRD NET a g e e e qum en ze E D m La 22 c Lu 2 ca 2 5 D gt m e Screen Complete Pro 15 F igure lus Generate the st Figure 16 shows the dialog box To create the clock left click on the Create Clock entry Leave the duty cycle at 50 Select Accept and select the CLK waveform on the left hand side of the waveform window Select Done in the dialog box Figure 17 shows the waveform after the clock has been defi
187. oadable Data Register DRAM Controller 16 to 8 Multiplexer Dual 4 to 1 Multiplexer Datapath Circuit Small State Machine Arithmetic Circuit 1 Bit Accumulator Address Decoder 8 Bit Fast Parity Generator DRAM Refresh Counter Thunderbird Taillight Control Circuit Denver Internatiomal Air Traffic Control 172 8 Bit Shift Register Module _ 8bshift bwb Title S bit shift register a b pin Data to shift in Clear Clock pin Shifter clock and clear signal setup qa qb qc qd qe qf qg qh pin istype reg buffer 8 shifter bits equations qa a amp b Data into first bit is the AND result of and b lqb qc qd qe qf qg qhl qa qb qc qd ge qf qg shifts data one bit at each clock qa qb qc qd ge qf qg qh clk Clock sets up clock qa qb qc qd ge qf qg qh ar Clear sets up clear end 173 N Bit Adder MODULE adder TITLE N bit Adder example bwb The number of bits added can be ajusted by setting the appropriate number of bits in b and Inputs CLK RST OENAB PIN 43 1 2 defines clock reset and output enable A 3 A 0 PIN sets four bit a input B 3 B 0 PIN sets four bit b input Outputs C 3 0 PIN ISTYPE sets four bit output A IN A_3 A_0 combines the four inputs into one variable B IN B_3 B_0 combines the four b inputs into one variable C OUT C 3 C 0 combines the four outputs into one variable Equations C OUT OE OENAB Defines
188. of first set of data bits x2 D2 D3 Exclusive or of second set of data bits x3 D4 DS Exclusive or of third set of data bits x4 D6 D7 Exclusive or of fourth set of data bits equations x5 1 x2 Exclusive or of first and second sets of data bits 3 x4 Exclusive or of third and fourth sets of data bits Odd x5 x6 Output equals exclusive or of all exclusive ors end 226 DRAM Refresh Counter Module refresh Title This isa DRAM Refresh Counter fora DRAM Controller This DRAM Refresh Counter counts up to 256 states which at 25 MHz clock frequency 40 nanosecond cycle period consists of a time period of 10 microseconds This DRAM refresh counter can be easily modified to any desired time period by adjusting the number of states in this counter MPCLK RFSTARTn MPRSTn OEn pin RFUSMST3 RFUSMST2 RFUSMST1 RFUSMSTO pin istype RFLSMST3 RFLSMST2 RFLSMST1 RFLSMSTO pin istype RFTIMEn pin istype rfust RFUSMST3 RFUSMST2 RFUSMSTI RFUSMSTO rfust rfustl hl rfust2 h3 rfust3 7 rfust4 rfustS he rfust6 hc rfust7 h rfust8 h9 rfust9 hb rfust10 ha rfust11 h2 rfust12 h6 rfust13 h4 rfust14 5 rfust15 hd rflst RFLSMST3 RFLSMST2 RFLSMST1 RFLSMSTO rflstO Ah0 rflstl 1 Mit Ah3 rflst3 7 rflst4 hf rflst5 he rflst6 hc rflst7 h rflst8 h9 rf
189. oftware unable to fit designi Fatal error found XPLAFIT terminated File ended on 7 9 96 6 46 62 PH 41 1 1 Total 18 1 Bytes 645 Figure 88 As one can see from Figure 88 the device did not fit without the Activate D T Register Synthesis selected Figure 89 gives the optimized equations for the 16 bit counter with the Activate D T Register Synthesis selected Please note that only a few output equations are shown to give the reader an idea of the effect on the equation by this option Also note that in this case the number of product terms required by each output stays constant COUNTO D amp amp LD amp CE COUNTO Q LD amp DO COUNTI T LD amp D amp COUNTI Q LD amp DI amp COUNTI Q LD amp CE amp COUNTO Q COUNT15 T LD amp D15 amp COUNTIS5 Q LD amp D15 amp ICOUNT15 Q 105 LD CE COUNTO Q amp COUNTI Q amp COUNT2 Q amp COUNT3 Q amp COUNT4 Q amp COUNTS Q amp COUNT6 Q amp COUNT7 Q amp COUNTS Q amp 9 amp COUNT10 Q amp COUNT11 Q amp COUNTI2 Q amp COUNT13 Q amp COUNT14 Q END Figure 89 Figure 90 gives the fitting report when the Activate D T Register Synthesis option is selected E Designer Viewer COUNTIB_FIT Fil Clipboard Search Options BLOCK A Resource Summary RESOURCE TOTAL USED UTILIZATION Hacro cells 16 16
190. on Control Language Inside the simulation engine SimScl control of the simulator is accomplished by means of an ASCII text file known as the SCL file As noted earlier this file can be most easily generated using the waveform editor However for designs that have a large number of vectors it can also be generated with as text editor so long as it uses the SCL format The format consists of the initial state of the input signals which signals will be displayed input and output the duration of the simulation session etc Complete detailed information 15 provided here on the internal format of the SCL file for users who wish to edit the file directly Let s look at an example of an SCL file Suppose the design to be simulated has four inputs inl 102 113 in4 and two outputs out out2 If you want to display all inputs and outputs all inputs will initially be at logical and will later transition to logical 1 see Figure 93 The first input will transition at 500 time units the second at 1000 the third at 1200 and the fourth at 2000 Supposing that the circuit will stabilize within 500 more time units we will simulate beyond the required 2000 to 2500 units 2000 2500 Figure 93 Figure 94 is an anatomy of SCL file which meets the basic format requirements and performs the task just outlined The comment lines start with an asterisk This example illustrates the S SU and F commands which are further described la
191. or a complete description of this function 87 File Signals Events Create Change View Save Run Bus Clk Bus oom Back Set the value af a Signal T 0 n Tnhnnnnmnnmn OO nmnnnnn dnnnmnnnn rnnnnnmnm cnnmnmnmnmnmm nnnmnnnrmn Figure 65 Press the View Full Screen Zoom Back button to switch between an normal or expanded view of the waveform viewer window See page 76 under View for a complete description of this function Create Change View Simulate Until Bus Bus Value Full 10000000 T _ ze Ele s xu gt li k 0 k et eet 1 1 ac mgmer last a an an nnn FI ru ru u u Ui r r7 a5 mnn ru r r r Figure 66 e Simulation Length The Simulate Until window indicates the point at which the simulation ends You can scale the waveform viewer window by adjusting this number See Figure 67 and Figure 68 for the effect of this action on the identical waveform viewer window EH XPLA Sim 2 1d BBSHIFT SCL Es Edt View Options Anchor Help Create Change View Simulate Until File Signals Events Save Run Bus Cik Bus Value Full Screen 10000000 nsec B 1000000 2000000 4000000 4000000 9000000 000000 000 Status Project 0 45 63 PLA Ex4MPLESB SHIFT VEBSHIFT
192. owever installation can be accomplished via floppy if the user can borrow access to a machine that has a CD ROM and a 1 44Mb 3 5 floppy drive In the root directory of the CD ROM there is a directory named FLOPPY In this directory there are sub directories named DISKI DISK2 DISK3 and so on currently through DISK6 Each of these floppies contains 1 44Mb or less of information in the form of an Info ZIP Pkzip compatible archive that has been split into multiple segments that will fit on the floppys The last directory also contains the Info ZIP public domain unzip utility and a batch file that will re combine the split segments Installation from a floppy only machine can be accomplished by copying all of the files in each D SK directory to separate 1 44Mb floppy disks a borrowed machine that has a CD ROM then copying the contents of all of the floppies to a single temporary directory i e c tmp_xpla onto the hard disk of the machine that has no CD ROM drive Then change directory to the temporary directory 1 e cd c tmp_xpla From a DOS command line type splice bat This will copy all of the segments into a single zip file called XPLA ZIP Delete the separate split files we re done with them del s Next unzip the files and the subdirectories contained in the zip file unzip XPLA ZIP Finally from Windows run cdsetup exe which will invoke the install program as detailed above When the install is completed
193. p 48 t 147 amp q6 amp 145 amp 194 q3 amp q2 amp ql 6140 411 1415 amp 414 amp 1413 amp 412 amp ql1 amp 410 amp q9 q8 q7 amp 190 q5 194 q3 q2 amp 141 amp 140 1015 c 1414 amp 1q13 amp 1412 amp q11 amp q10 amp q9 amp q8 dt 147 amp 146 q5 194 q3 q2 amp 141 amp 140 1415 amp q14 amp 1413 amp 1412 amp q11 amp q10 amp q9 amp 148 amp q7 amp 190 q5 194 q3 q2 82 141 amp 140 1415 c q14 amp q13 amp q12 amp 411 amp q10 amp q9 amp q8 amp q7 amp 146 q5 194 1q3 q2 141 amp q0 1415 1414 amp 413 amp 1412 amp 411 21410 amp q9 amp q8 amp q7 amp 190 q5 194 q3 q2 amp 141 amp 140 1415 c 1414 413 amp 412 amp q11 amp qlO amp q9 amp q8 amp 147 146 q5 194 q3 q2 141 amp 140 1915 1414 c q13 c q12 amp 1411 amp 1410 amp q9 amp q8 amp q7 amp q6 q5 q4 q3 q2 amp ql amp q0 1915 amp 1414 c q13 amp q12 c q11 amp 410 amp q9 amp 148 t q7 amp q6 amp 145 194 amp q3 amp q2 amp ql 62140 410 1415 amp 1414 amp 1413 amp 1412 61411 amp 1410 amp q9 amp q8 amp q7 amp 146 amp q5 amp g4 amp 143 amp q2 amp q1 amp 140 1915 amp 1414 8 1413 amp g12 amp q11 amp q10 amp
194. p DRAMCSn amp BEOn amp MPRDn amp MPWRn amp dst dst21 amp DRAMCSn amp BEOn amp MPRDn amp MPWRn amp dst dst22 amp IDRAMCSn 6 BEOn amp MPRDn amp 6 dst dst7 amp DRAMCSn c MPRDn amp MPWRn amp MPRSTn dst dst8 amp DRAMCSn z MPRDn amp MPWRn z MPRSTn dst 4519 amp DRAMCSn z MPRDn amp MPWRn z MPRSTn dst 45110 amp DRAMCSn amp MPRDn amp MPWRn amp MPRSTn dst dst11 amp IDRAMCSn amp IMPRDn amp MPWRn amp MPRSTn amp dst dst12 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn amp dst dst13 amp IDRAMCSn amp IMPRDn amp MPWRn amp MPRSTn amp dst dst14 amp IDRAMCSn amp IMPRDn amp MPWRn amp MPRSTn amp dst dst15 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn amp dst dst16 amp IDRAMCSn amp IMPRDn amp MPWRn amp MPRSTn amp dst dst17 amp IDRAMCSn z MPRDn amp MPWRn amp MPRSTn 6 dst dst18 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn amp dst 45119 amp DRAMCSn z MPRDn amp MPWRn amp MPRSTn amp IMPBURSTn DRVVRn RFTIMEn dst 9516 amp DRAMCSn amp MPRDn MPWRn amp MPRSTn amp amp STARTCYCLE dst dst20 amp IDRAMCSn amp MPRDn amp MPWRn amp MPRSTn 208 DRRDLE IDRRWCLn IMPBURSTn IDRRDCEn IDRACKn MPBURSTn IRFSTARTn
195. p 140 1915 c 1414 amp 413 412 amp q11 q10 amp 149 198 147 46 amp q5 94 143 142 41 amp 140 43 1415 4 1414 4 1413 amp 1412 61411 8 1410 amp 109 amp 148 amp 147 amp 146 45 194 1q3 amp q2 amp 101 amp 140 1015 c 1414 amp 413 amp 912 amp q11 amp 1410 amp 199 amp 148 147 amp 140 145 194 amp q3 amp q2 amp 141 140 1015 1414 amp 413 amp 912 amp q11 amp q10 amp 199 amp 148 147 amp 140 amp 145 194 amp 3 amp q2 140 1915 1414 amp 43 amp 912 amp q11 amp q10 amp 199 amp 148 147 amp 140 amp 145 amp 194 82 3 142 amp ql amp 140 1915 1414 amp 413 amp 9412 amp q11 62410 amp 199 amp 148 147 amp 140 q5 194 amp q3 192 101 46140 1915 1414 amp 413 amp 912 amp q11 amp q10 amp 199 148 147 amp 140 amp 195 amp 94 amp q3 142 amp 141 140 1415 1414 amp 1413 amp q12 62 1011 amp 1410 amp q9 148 147 146 amp q5 94 143 142 amp 141 140 1915 1414 amp 413 amp 912 amp q11 amp q10 amp 199 amp 148 147 amp 140 q5 44 amp 43 142 t ql 4140 q2 1415 4 1414 4 1413 amp 1412 61411 amp 1410 amp 109 amp 148 amp 147 amp 146 195 194 193 amp 192 amp ql 140 1915 c 1414 amp 1413 amp 912 amp q11 621410
196. p Q2 amp Q1 amp Q0 11 Q10 amp Q9 amp Q8 amp Q7 amp Q6 amp Q5 amp 046 amp Q2 amp 1 amp 00 Q10 T Q9 amp Q8 amp Q7 amp amp Q5 amp 4 amp amp Q2 amp QI amp 00 9 Q8 amp 07 amp amp Q5 amp 04 amp amp Q2 amp 1 amp QO 8 Q7 amp Q6 amp Q5 amp Q4 amp amp 02 amp 1 amp Q0 7 Q6 amp Q5 6 04 amp Q2 amp QI amp Q0 Q6 T 05 amp 04 amp amp Q2 amp QI amp 00 Q5 T 4 amp amp Q2 amp Q1 amp QO Q4 T amp Q2 amp 1 amp QO Q3 T Q2 amp Q1 amp Q0 Q2 T 1 amp 00 QI T 2 Q0 QO T 1 181 Dual 16 Bit Up Down Loadable Enabled Resetable Counters MODULE cntr2 16 title 2 16 bit up down loadable enabled resetable counters NOTE reset is load amp count enab amp dir NOTE BIDIR pins are used for the load of each counter DECLARATIONS dir pin 1 load pin 2 count_enab pin 44 clk pin 43 15 0 4 5 6 7 8 9 11 12 13 14 16 17 18 19 20 21 istype cb15 cb0 pin 41 40 39 38 37 36 34 33 32 31 29 28 27 26 25 24 istype ca cal5 ca0 cb cb15 cb0 EQUATIONS ca clk clk cb clk clk ca ar load amp count_enab amp dir cb ar load amp count_enab amp dir ca oe load cb oe when load 1 then ca d ca pin cb d cb pin else whe
197. pplied until the output enable has been turned off and the device has had sufficient time for the output buffer to be disabled Bi directional pins are not explicitly declared as input output but are created by the way in which the design is written Take the following eight bit loadable counter example in which the counter output pins are also used to load the counter Module bidi8bit Title Eight bit counter with bi directional pins pl p2 p3 p4 p5 p6 p7 ps pin load pin 44 Declare the outputs count out p1 p2 p3 p4 p5 p6 p7 p8 Declare the inputs load value count load p1 p2 p3 p4 p5 p6 p7 p8 equations Turn off the output enable when load is high count_out oe load Load when load is high count when load is low when load b1 then count_out d count_load j count out d count out q 1 j Note that the same pins are used for the counter output and for the load and they are not declared as any particular type of pin When the output enable is turned on the counter functions normally When the output enable 1s turned off the counter outputs can now be used as inputs to load the counter Even though they refer to the same pins using the variables count out and count load makes the design more clear because they draw distinction between when the pins are used as inputs to load and when the pins are used as outputs Nodes Nodes are signals that do not leave the ch
198. put Correct error in PHDL file 5155 Line numbers or z expected Add the assignment operator to the PHDL file 5160 Line numbers Identifier must begin with an alphabetic character Change the identifier in PHDL file 5165 Line number Signal is not declared in interface statement Change the interface statement in PHDL file 5170 Line lt number gt Formal and actual signal assignment do not match Correct error in PHDL file 242 5175 Line lt number gt Constant has been declared already Ensure that the constant is declared only once in PHDL file 5185 Line number Submodule has not been declared in INTERFACE statement Add the submodule to the interface statement in PHDL file 5200 Line lt number gt Instance has not been declared Add the interface and or functional block statement in top level PHDL file 5210 Line number Submodule has been declared already Correct the interface and or functional block statement in the top level PHDL file 5215 Port has not been connected Correct the PHDL file 5220 Line numbers Instance has been declared already Correct the interface and or functional block statement in the top level PHDL file 5225 Line number Dot extension is not allowed in port name Correct the name of the input output or inout in the PHDL file 5230 Line number Primary equation for exists Correct the PHDL file 5235 Line number Input port has already been connect
199. quations 101102 pin clk pin outl out2 pin istype equations outl c clk out2 c clk when inl 1 amp in2 1 then outl 1 else outl 0 when inl 0 amp in2 0 then out2 0 else out2 1 end Example Multiple when then else structure 133 Module multwhen Title Example of multiple when then else inl in2 pin clk pin outl out2 pin istype equations outl c clk out2 c clk when inl 1 amp in2 1 then out 1 out2 1 j else when inl 1 amp 2 0 then out 0 out2 1 Example Nested when then else structure Module nestwhen Title Example of nested when then else inl in2 pin clk pin outl out2 pin istype equations outl c clk out2 c clk when inl 0 then when in2 0 then out 1 out2 0 j 1 out 1 out2 1 j j else when inl 1 then when in2 0 then out 0 out2 0 j with Description The with statement is used in conjunction with if then else and case structures in state diagrams to combine output equations with state transitions It 15 also useful to make registered outputs transition with the state rather than one clock cycle after the state change Normally when state diagrams are written without using the with statement registered outputs change one clock cycle after the state For more information refe
200. quence and the other three will glow steadily as a brake light 21 10 15 20 25 30 35 40 45 MODULE tbird TITLE thunderbird tailight demo BRAKE pin TL pin TR pin CLK pin L1 L3 pin istype R1 R3 pin istype q2 q0 pin istype out L3 L2 L1 R1 R2 sreg q2 ql q0 50 0 0 0 sl 0 0 1 s2 0 1 0 53 0 1 11 s4 1 0 0 55 1 0 1 56 1 1 0 s 1 1 11 equations sreg clk CLK out clk CLK state_diagram sreg state sO when BRAKE 0 then out b000000 equations else when BRAKE 1 amp TL 1 then out b000111 else when BRAKE 1 amp TR 1 then out b1 11000 else out bl 11111 if TL then 61 state transition logic else if TR then s4 else 50 state 51 when BRAKE 0 then out 6001000 equations else out b001111 if TL then s2 state transition logic else if TR then s4 else 50 state s2 when BRAKE 0 then out b01 1000 equations else out bO11111 50 if TL then s3 state transition logic else if TR then s4 else 50 55 state 53 when BRAKE 0 then out b111000 equations else out b111111 if TL then sO state transition logic 60 else if TR then s4 else 0 state s4 when BRAKE 0 then out 6000100 equations 65 else out
201. r the check box or select an item elect Design open New Design in the menu he combobox to specify design options Simulate it Figure 2 Functional Simulation Functional simulation verifies that the design is performing as intended This 1s different from verifying that the part is performing as intended It checks only that the logical response of the design to particular input stimuli is correct but does not check any physical parameters such as speed or power For example a simple design that adds two plus two will functionally simulate correctly if the output is four even if it took hours for the output to appear When the XPLA Designer simulator is run after the design has been compiled but before the design has been fitted into the device the simulator will act as a functional simulator If the simulator 15 employed after the logic has been fit into the design the XPLA Designer simulator will act as a timing simulator and use the actual timing parameters of the target device The simulator can be activated by selecting the Simulate Button on the XPLA Designer Interface as shown in Figure 2 The simulation input stimuli is defined in a Simulation Control Language SCL file A complete description of the XPLA Designer simulator can be found in Chapter 6 10 Device Fitting Device fitting is where software translates the design into a file format that a part programmer can understand and then attempts to
202. r to the state diagram if then else and case sections in this chapter Syntax 135 if condition then state with output equations else 1f condition then state with output equations else state with output equations OR case condition state with output equations condition state with output equations i condition state with i output equations 1 endcase Example With statement in if then structure Module if with Title Example of with statement in if then structure in pin clk pin out istype 41 node istype equations 136 out c clk Sl c clk state diagram s1 state 0 if Gn 1 then 1 with out 0 state 1 if in 1 then 0 with out 1 Example With statement 1n case structure Module casewith Title Example of with statement in case structure inl in2 pin out out2 pin istype com buffer 40 node istype state diagram q0 state 0 case inl 0 amp in2 1 1 with out 1 out2 0 endcase state 1 case inl 1 0 with outl 0 out2 1 endcase 137 APPENDIX A SCL Simulation Control Language The XPLA Designer logic simulator models the operation of a logic design so that the modeled circuit can be analyzed and debugged The simulator is a vital part of the design process because is it difficult or impos
203. rds used by the designer to refer to signals module names macro names variables and the like Any word may be used for these purposes provided it meets the following restrictions e Identifiers have a maximum length of 31 characters e Identifiers cannot be reserved words see next section e Identifiers must begin with an alphabetic character or an underscore they cannot begin with a number e With the exception of the first character identifiers can contain any alphanumeric character e Identifiers cannot contain periods e Identifiers cannot contain spaces underscores should be used instead e Identifiers are case sensitive Be careful This one will get you 32 Reserved Words The following keywords are reserved for PHDL and cannot be used as identifiers For more information on the use of these words refer to Chapter 8 on language reference In contrast to identifiers these words are not case sensitive do env end notdet oct ouput until when while 8 0 Comments Comments can be used anywhere in the design file and may contain any word or character Most comments may not extend over one line There are four ways to create a comment in PHDL Begin the comment with a double quotation mark and end with the end of line This is a comment using only one quotation mark Begin the comment with a double quotation mark and end with another quota
204. reg t If you have other signals that are active low you must build the logic equations accordingly 43 reg d D type flip flop clocked memory element reg Gated D type flip flop clocked memory element reg jk JK type flip flop clocked memory element reg sr SR type flip flop clocked memory element reg t T type flip flop clocked memory element retain Do not minimize this output Preserve redundant product terms Figure 25 Multiple attributes may be specified for a particular signal as long as they do not conflict with one another For example output PIN ISTYPE reg d buffer retain specifies the signal to use a D type flip flop with no inversion after the register and to preserve any redundant product terms that make up the signal However the line output PIN ISTYPE com invert buffer is illegal because the output cannot be inverted and non inverted at the same time All attributes must be separated by commas and the string of attributes must be enclosed with single tick 9 marks Bi Directional Signals Bi directional signals are supported on all Philips CPLDs The multi function input output pins can support bi directional signals with the output enable of the output buffer When the output enable is turned on the pin is an output when the output enable 16 off the pin can be used as an input Care should be taken when using bi directional pins to ensure that input signals are not a
205. rom the list in the above table Multiple attributes may be assigned at one time if they are separated by commas Multiple attributes must not conflict with each This attribute is ignored for all signals except those that are a detailed register type reg d reg jk reg sr reg t If you have other signals that are active low you must build the logic equations accordingly 121 other i e a pin or node cannot simultaneously be assigned the attributes collapse and keep Example Module istyp ex Title Example showing istype statement usage Declare 4 inputs and a clock a b c d pin clk pin Declare 2 combinatorial outputs that are not to be collapsed out out2 istype com keep declare 2 registered outputs that are to be inverted output out3 out4 pin istype reg invert declare 2 d type registered nodes n1 n2 node istype reg_d equations out3 c clk out4 c clk nl c clk n2 c clk outl a amp b out2 c d amp nl q out3 a b outl com out4 c amp d amp a nl outl com amp out2 com n2 out3 q amp out4 q end 122 macro Description The reserved word macro is used to declare macro functions in the declarations section of the PHDL file A macro function is a set of PHDL code that can be used throughout source file multiple times without having to retype the code each time For more information refer to the section titled m
206. routine They are unknown outside subroutines 2 Jumps into a subroutine are not permitted 3 Jumps out of a subroutine are not permitted 4 Atthe end of a subroutine declaration all jumps are checked Nonlocal jumps create e an error message After the finish command F all jumps in the main part are checked Nonexistent labels create error messages Forward and backward jumps are possible There is one command related to jumps GT 143 SCL Keyword Summary Explanation switch the peripheral bus line to input state switch the peripheral bus line to output state call a subroutine end data lines start data lines assign a data line to a variable decode a variable end a subroutine declaration finish go to if statement return from a subroutine sequence set data counter set a variable Set to stability check ST DATA set to data SU simulate until SUB start of a subroutine declaration SUNS simulate until network stable TRAC transition check SCL Keyword Definitions BUSI Switch Bus Line to Input State Format BUSI lt signal list gt Only NETIO signals output of bus function are allowed The output of a bus line with a name that occurs in the signal list is changed to the input state condition 1 e a forcing external stimulus may be applied to that node In this situation the simulator checks whether the inputs of the bus line are kept on real or virtual 144 3 State pull up or pull down res
207. rs were inadvertently set to one of those undefined states the design would simply stop functioning because no logic is defined for the unused state If however these undefined states all had a simple statement 56 in them directing the state diagram to transition to a known state the design would only stop for one clock cycle and would then recover The following T Bird Tail Lights phd file example illustrates the use of state diagrams There are eight distinct states for the design represented by three registers Notice in the design how the state diagram registers are represented by a variable and how the register values associated with each state are declared beforehand This is a functionally equivalent implementation to the general syntax listed above where the registers and their values are defined within the state diagram itself The design emulates the tail lights of a late 1960 s T bird automobile The inputs are the brake and the left and right turn signals The outputs are six separate bulbs three for each tail light When either the left or right turn signal is on the three bulbs on the appropriate side light in sequence starting with the center bulb until all three are lit They then all go dark and the process repeats itself until the turn signal is turned off Whenever the brake 15 pressed all six bulbs will light unless the turn signal is also activated in that case the three bulbs indicating the direction of turn will se
208. se structure It is used to specify the result that should occur when conditions specified by the corresponding if statement are true For more information refer to the if then else and when then else commands in this chapter Syntax if condition then state else state OR when condition then result else result For both cases whenever the logical expression condition 1s true the state or result after the then statement will be implemented Example Else used with if statement in a state diagram Module if_then Title Example of then with if statement in state diagram 101102 pin clk pin out pin istype 1 52 node istype equations out c clk Sl c clk s2 c clk state_diagram s1 s2 state 0 0 out 0 if 101 0 amp in2 1 then 0 1 else 1 0 130 state 0 1 out 1 if 101 1 amp in2 0 then 1 0 else 1 1 state 1 0 out 1 if 101 1 82 in2 1 then 1 1 else 0 0 state 1 1 out 0 if Gnl 0 amp in2 0 then 0 0 else 0 1 Example Else used with when statement equations Module when_then Title Example of then with when statement in equations 101102 pin clk pin outl out2 istype equations outl c clk out2 c clk when inl 1 amp in2 1 then outl 1 else outl 0 when inl 0 amp in2 0 then out2 0
209. sible to analyze the internal operation of an integrated circuit in any other way The XPLA Designer simulator is similar in its basic operation to most commercially developed simulators The simulator runs a simulation of the logic of the design based on the binary netlist BIN file created by the simulator and the input stimulus file SCL file created using a text or waveform editor The simulator determines the values of the output signals as a function of time given the input signals in the SCL file Theory of Operation The XPLA Designer simulator is an event driven 5 State simulator Event driven means the simulator treats the clock as an ordinary event and advances time 1 expands or contracts according to activity within the circuit 1 output transitions on gates If nothing 15 happening the simulated model of time is advanced and updated to when there is some action 5 states simulated for gate outputs are logical 1 logical 0 3 State undefined and unknown see Figure 91 logic elements understood by the simulator are positive logic Symbol Low 0 Logic state is low false Logic state is high true Logic state is not known but is either low or high High impedance or floating state Undefined Logic state is between low and high indicating an unstable level Figure 91 The simulation is based on two input files a binary netlist BIN file and the Simulation Control Language SCL
210. sign Pin preassignment Try Ei Max P term per equation 7 Activate register synthesis PAD EDIT Auto Node Collapse Mode Design pz3032 8 PLCC44 M Generate Timing Model Clean Up MPLETTBIRD Exit lick the edit button edit the design file hecki lear the check box r select an item lick the combobox to select the target device he combobox to specify design options Simulate Fit Figure 23 Editing an Existing Design Select Open Design from the Design menu in XPLA Designer see Figure 23 The Open Design window will appear Navigate to the directory where the design you want to open is located Highlight the design you want to open and press enter or select OK The design you have selected will be loaded into XPLA Designer Click on the EDIT button in the XPLA Designer window The XPLA Design Editor will open up and the phd file will be displayed for editing Edit the design and save your work before exiting the Design Editor Header Section Module Statement 38 The header of all PHDL files must start with the reserved word module followed by the name you want to use to refer to this design The name must adhere to the standard eight character DOS format and should be the same as the name of the file Title Including a title for the design in the header section is optional Titles are useful because they often provide a more detailed description of the desi
211. statements are usually included at the beginning of the PHDL file The following table lists available properties and gives a brief description PROPERTY DESCRIPTION Enables global tri state function Syntax XPLA property property Example Module prop Title Example of property statement 126 XPLA property dut on in out pin istype com equations out in end state Description The reserved word state is used within a state diagram to indicate the state that is being defined For more information refer to the state diagram section of this chapter and to the logic description section of chapter 5 Syntax state diagram 91 90 state 0 0 state description state 0 1 state description state 1 1 state description Example Module stat ex Title Example showing reserved word state inl in2 pin clk pin out pin istype 51 52 53 node istype equations 127 out c clk Sl c clk s2 c clk 53 clk state_diagram s1 s2 s3 state 0 0 0 out 6 if 101 1 then 0 0 1 state 0 0 1 out 1 if 101 1 then 0 1 0 state 0 1 0 out inl if 101 1 then 0 1 1 state 0 1 1 out inl if 101 1 then 1 0 0 state 1 0 0 out 1n2 if 101 1 then 1 0 1 state 1 0 1 out 1102 if in1 1 then 0 0 0 state 1 1 0 goto 0 0 0 state 1 1 1 goto 0 0 0 state dia
212. sum3 sum0 equations sum c clk sum a b carryin end 177 BCD to 7 Segment Decoder Module BCD7 bwb Title BCD to 7 segment decoder seven segment display decoder driver with active low outputs T Segments a I fl b g el lc E D3 DO PIN A B C D E F G PIN ISTYPE COM OE PIN BCD D3 D0 LED A B C D E F G ON OFF zl LED S equations LED OE z OE BCD INPUT SEGMENT OUTPUTS OUTPUT ENABLE INVERTED SENSE FOR COMMON ANODE DEFINE OUTPUT ENABLE truth table BCD gt A B C D G end 0 1 QO ON NM di Uv t 11 12 13 14 15 gt ON ON ON ON ON ON OFF gt OFF OFF OFF OFF OFF gt ON ON OFF ON OFF ON gt ON ON ON OFF OFF ON gt OFF OFF OFF ON ON gt OFF ON OFF ON gt OFF ON ON ON ON gt ON ON OFF OFF OFF OFF gt ON ON J gt OFF OFF ON gt ON ON ON ON OFF ON gt OFF OFF ON ON ON ON gt OFF OFF ON ON ON OFF gt OFF ON ON ON ON OFF ON gt OFF OFF ON ON ON gt OFF OFF OFF ON ON 178 Bidirectional I O s MODULE bidirect TITLE Bidirectional I Os a3 aQ pin istype b3 b0 pin 3 0
213. switch Each Logic Block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells Each Logic Block also provides 32 ZIA feedback paths from the macrocells and I O pins The number of Logic Blocks contained within a device determines the macrocell count of the device For example devices containing 2 4 and 8 Logic Blocks are 32 64 and 128 macrocell devices respectively Logic Block K gt Logic Block E RENE els O O Logic Block K gt Logic Block T O elle 5 V V A A Figure 3 From this point of view this architecture looks like many other CPLD architectures What makes the CoolRunner family unique is what s inside each Logic Block and the design technique used to implement these Logic Blocks The contents of the Logic Block will be described next Logic Block Architecture Figure 4 illustrates the Logic Block Architecture Each Logic Block contains Control Terms a PAL Array a PLA Array and 16 macrocells The 6 Control Terms can individually be configured as either AND or SUM product terms and are used to control the preset reset and output enables of the 16 macrocell s flip flops The PAL Array consists of a programmable AND array with a fixed OR array while the PLA array consist of a programmable AND array with a programmable OR array The PAL array provides a high speed path through
214. t in operation lt string gt Correct the set size See Chapter 5 for the correct use of sets in PHDL 3000 PLA type not supported XPLA Designer supports only PLA formats compatible with that defined in the Open Abel Technical Specification 3002 Number of signal in ilb list doesn t match i In the PLA file the number of names in the ilb record must equal the number in the 1 record Re generate the PLA file 3004 Number of signal in ob list doesn t match o Correct the PLA file such that the number of names in the ob record 1s equal to the number in the o record 5000 Dulpicate state near line lt number gt Correct the PHDL state machine description See p43 for an example 5005 Missing parameters for macro near line line Correct the macro in the PHDL source See Chapters 5 and 8 for the correct use of macros in PHDL 5010 Parameter not declared in macro near line lt line gt Correct the macro in the PHDL source See Chapters 5 and 8 for the correct use of macros in PHDL 5015 Recursive usage of macro near line Correct the macro in the PHDL source See Chapters 5 and 8 for the correct use of macros in PHDL 5020 The number of parameters is incorrect near line numbers Correct the number of parameters in the PHDL source 5025 Syntax error near line number Extension is not supported Correct the PHDL source Valid dot extensions are listed Chapter 5 240 5030
215. t Pin Registered Registered Tsu_pal PAL only Tco Tsu_pla PAL PLA Input Pin Output Pin clock Figure 7 Closing Remarks The XPLA architecture used in the Philips CoolRunner CPLD family combines a unique power saving design technique with a next generation architecture For any questions concerning the architecture please contact Philips Programmable Products technical support via the contact information detailed in Chapter 1 20 Chapter 4 Getting Started with XPLA Designer This chapter provides a tutorial which demonstrates how to create compile and simulate a design using XPLA Designer The design uses the Philips Hardware Description Language to define a state machine Design Description This getting started chapter targets a design called T Bird Tail Lights into a Philips PZ3032 CPLD This design is a state machine that simulates the blinkers and tail lights on Ford Thunderbird automobiles of the late 1960s see Figure 8 The inputs to the state machine are clock CLK turn left TL turn right TR and brake The outputs of the design are the left blinkers L1 L2 and L3 and the right blinkers R1 R2 and R3 When turning left or right the blinkers sequence through three bulbs to indicate the direction of turn see Figure 8 Starting with the inside bulb three bulbs are sequentially lighted in the direction of the turn until all three are on then all three go dark and the sequence starts again
216. t View Options Drop Anchor Help Create Change View Simulate Until File Signals Events Save Run Bus Cik Full Screen 10000000 nsec 8 sa a a a 4 a a s a s a Mg LM 4 s s s a s a a a a a a a NR A ACC CC o TTL 60 0 0 0 Da Ps T TT 0 TT TT a a a s a a a a a a a 4 a s a a a Mg a a uu ATC ME CIC A CC A A RA AR pr a s a s a s a s a s a s a s a s a s a s a a a s a a a s a s a s a s a s ass a s a s ass ao s wv s a s a s a s a s a s a s a s a s a s a co a s a s M m o wv mv wm cw a s d TOYS Status Project wv SPLSSERAMPLESDEMDSDEML MET Refreshing Complete Figure 78 To do a timing simulation all that is required to be done is to fit the design into a particular part type and package first before running the simulation The fitter algorithm co
217. tate list signal list This has the same meaning as the IT command except that the non specified signals and the simulator clock remain unchanged Example ST 13 Al B C D result A 1 B 3 C all others are unchanged 155 STAB Stability Check Format STAB lt n gt During simulation the stability of the network is checked at the moment signals are forced by an IT ST ST DATA DECV or S command The messages are printed in alphanumeric mode lt n gt 15 an optional parameter default 15 25 giving the number of messages If lt n gt is exceeded the STAB check is canceled STAB may appear anywhere in the program ST DATA Set to DATA Format ST DATA lt signal list gt This command has the same function as the ST command The string of states identified by the current data counter is taken from the data field s These are strings of data specified between the keywords DATS and DATE The data counter is the data string number Each ST DATA command causes the data counter to be incremented by 1 If the string of states 1s not sufficient for the signal list the last state 1s repeated for the remainder of the signals Example Data field given as DATS 101 HEX 1A FC BIN 111 10 DATE Data counter set to 4 ST DATA A B C D will result A set to 1 156 B set to 1 set to 0 D set to 1 Now the data counter 15 set to 5 Next ST DATA A B C D w
218. ter 140 Simple SCL file any comment is OK here 5 0 500 inl above statement defines inl initially logic and transitions to 1 at 500 time units this will remain 1 for the remainder of the simulation 5 0 1000 in2 similarly in2 transitions from to 1 at 1000 times units S 0 1200 3 1n3 transitions from to 1 at 1200 5 0 2000 in4 finally in4 transitions at 2000 SU time 2500 Defines the simulation time as 2500 total units F Figure 94 To use SCL files that were created using a text editor with the XPLA Designer simulator you must first turn the off the autosave SCL file on run feature inside the waveform editor When the simulator waveform interface is running this 15 an checkbox item under the options menu it should be unchecked Then you can load the SCL file created with a text editor and Run a simulation The waveforms can be viewed on screen or printed Many good simulation practices could be summarized at the onset to help the designer develop good simulation practices but one single cardinal rule will minimize frustration Always initialize flip flops and registers This is important because any digital simulator will spend enormous amounts of time attempting to establish its initial state which may be impossible Input Format The input format of the stimuli file is as follows The scanning field is column to 72 inclusive Lower case characters are tr
219. ter relation lt lt sign gt minus sign optional if no sign is given a positive value is assumed lt value gt a positive constant or variable If the condition of the I F clause is true when read the SCL statement is executed Note Nesting of IF V statements is not allowed Example IFV VARI 10 CALL SUBTESTI If the value of variable VARI equals 10 the subroutine SUBTESTI is called VAR2 lt VAR3 gt If the value of variable V AR2 is greater than the value of variable VAR3 the program jumps to label RESETI INCR Increment a Variable with a Specified Value Format INCR variable lt sign gt value variable variable name up to 12 characters the first being a letter sign minus sign optional If no sign is given a positive value is assumed value a positive constant or variable Example 1 Example 2 151 SETV VARI 3 variable VARI set to 3 SETV COUNT 10 variable COUNT set to 10 INCR COUNT VARI value of variable COUNT incremented by value of variable VARI COUNT 13 IT Initialize To Format IT initstate list signal list Initializes all signals of signal list to the states given in initstate list gt All other signals are set to unknown The k th state corresponds with the k th signal When not enough states have been specified the last state is repeated The simulator cloc
220. the array while the PLA array provides increased product term density Each macrocell has 5 dedicated product terms from the PAL array If a macrocell needs more than 5 product terms it simply gets the additional product terms from the PLA array The PLA array consists of 32 product terms which are available for use by all 16 macrocells For the 5 PZ5032 the additional propagation delay incurred by a macrocell using 1 or all 32 PLA product terms is just 2ns So the total pin to pin for the PZ5032 using 6 to 37 product terms is 8ns 6ns for the PAL 2ns for the PLA Control Terms UU PAL AND Array 36 LLLI AT ELI LLL 0 811 DV VM DV VVL Hez 4 PLA AND Array iU 0000000 PLA OR Array Figure 4 16 XPLA architecture is very accommodating for implementing last minute design changes In fact 16 million worst case designs designs which used all of the I O Pins and all of the Macrocells were implemented in the PZ5032 with fixed pins amp macrocells and all but 30 designs were able to route Therefore 99 998 of these worst case des
221. the command box where DRIVE 15 the letter representing your CD Win95 users may find that the autostart feature automatically loads the install program Select OK The CD ROM Install Program will appear on screen along with instructions The install program will install any or all of the system components you specify Following the instructions on screen the CD ROM will install the following components XPLA Designer version 2 1 CPLD Design Tool Electronic documentation for the software and device datasheets Adobe Acrobat pdf format e Adobe Acrobat M Reader for Windows version 2 1 Microsoft Win32s 32bit runtime extension for Windows 3 1 or later users Windows 3 1 must either have Win32s already installed or install the version provided to run XPLA Designer This is not needed for Windows95 users Once XPLA Designer 1s installed you may run the program by following the instructions in Chapter 4 If you get an error when trying to run XPLA Designer on Windows 3 1 or later for the first time it 1s likely that you do not have a version of Win32s on your machine that is not new enough to run XPLA Designer In this case you will need to upgrade to the Win32s version included with XPLA Designer Once Win32s has been 13 upgraded try to run the program again If you still get an error contact Philips CPLD Applications for support Installing from Floppy Disk XPLA Designer is only shipped on CD ROM H
222. tion mark This is a comment using two quotation marks Begin the comment with a double forward slash and end with the end of line This is a comment using the double forward slash 33 Begin the comment with a slash star and end the comment with a star slash just like comments in programs This type of comment can extend over more than one line This is a C style comment that is recognized by XPLA Designer s parser It may extend over more than one line Number Types Numbers are represented in four different bases Figure 20 describes the format for each base note that the decimal representation can have two different formats The example column indicates how the decimal number 69 would be represented in each of the different bases BASE NAME BASE SYMBOL EXAMPLE b1000101 Octal 8 o ol0005 Decimal 10 69 Figure 20 34 Order of Operations Figure 21 defines all operators in PHDL that can be used to evaluate expressions and their order of resolution Operators with equal priority will be evaluated from left to right in the expression Be safe when writing code that has multiple operators on a line use a lot of parenthesis they are free and they will eliminate really annoying operator precedence errors that compile O K and generate logic errors in the design 1 NegateQ scomplement 1 jJ JNOT 2 amp X JAND ASB 2
223. to declare signals Input Signals Input signals are external signals that come into the design and are used to determine the value of the design outputs Input signals may be assigned to dedicated input pins or to input output 1 0 pins The syntax for assigning a signal as an input 15 signal_name pin pin_number where signal_name is the name of the signal pin is a reserved word indicating that you want to assign the signal to a pin and pin_number 15 the optional specification of the pin where the signal will enter the chip Lines 9 through 12 of Figure 22 illustrate how to declare input signals with specified pin numbers It is also possible to let the software automatically assign pin numbers to the signals by leaving the pin numbers blank For example if lines 9 through 12 were changed to 1 ADVISORY There is an Extremely Small but Nonzero Chance That Through a Process Know as Tunneling This Product May Spontaneously Disappear from Its Present Location and Reappear at Any Random Place in the Universe Including Your Neighbor s Domicile The Manufacturer Will Not Be Responsible for Any Damages or Inconvenience That May Result 42 dir pin load pin count enab clk pin then the software would automatically assign the signals to pins compatible with their defined type Output Signals Output signals must be assigned to I O pins they cannot be assigned to dedicated input pins The syntax for assigning a sign
224. to the part the XPLA Designer software generates a post layout timing file This file contains path delays for all signal routes based on real physical parameters for the selected CPLD The XPLA Designer simulation uses this timing file to verify that the design will function correctly at the required frequency once it 1s programmed into the actual part When the XPLA Designer simulator 1s employed after the design has been compiled and fitted into the device the simulator will act as a timing simulator and use the actual timing parameters of the target device The simulator can be activated by selecting the Simulate Button on the XPLA Designer Interface as shown in Figure 1 2 The simulation input stimuli is defined in a Simulation Control Language SCL file A complete description of the XPLA Designer simulator can be found in Chapter 6 11 Programming This final stage is generally done when all other steps have been completed and all design specifications have been met during the post layout simulation Designs that successfully fit into the selected CPLD are also translated into a JEDEC file for use in programming the part The JEDEC file can be loaded into a part programmer which then configures the design into a part The JEDEC format is understood by many commercially available parts programmers Refer to the users manual of the specific programmer you are using for JEDEC compatibility and programming information The XPLA Help F
225. ts that constitute a bus The individual elements of a bus must be edited to change the bus value See the section on 73 adding a bus page 73 for proper bus signal procedures Figure 42 depicts the editing bus window m Editing Bus Iof x Signals Bus Elements Add Delete Done Cancel Select the Bus you wish to edit on the screen Figure 42 Add Clk This command will allow the operator to add a clock to a signal name A clock settings window will appear in the waveform viewer window Select the start value cycle length and duty cycle you want then click the accept button in the clock settings window Select a signal name from the waveform viewer window by clicking on it The clock setting you selected will appear to the right of the selected signal name Figure 43 illustrates the procedure 74 XPLA Sim 2 14 Clock Settings E D xj Edt View Options null e Start Value 100000 i Length Simulate Until Fle Sn Start ART bur Coc Save Run OK Start At 0 s 10000000 10000000 nsec Done Cancel 1000 Maintain Duty Cycle Heset 10000 18000000 19000000 the values for the clack you desire Then press 2111 5 G G 1 Accept or Cancel Status Project D SS vw RPLASERAMPLESCULINTTB HET Set Desired Clack Attributes And Click Figure 43 Set Value This command allows the operator
226. ue Corect the interface and or functional block records in the top level PHD source and the module statement in the sub module 5205 Line numbers Default value is ignored in this module Corect the interface and or functional block records in the top level PHD source and the module statement in the sub module ERRORS 108 The command line option must be a number A string is found Replace the string with a number 118 No argument after parameter A number is required Add a number after the parameter in the command line 120 Device not supported Either select a device from the cyclic field in the XPLA Designer or verify that the correct part number is used in the command line The part number syntax is given in the data sheet 150 Cannot open file Check the location and permissions on the file and the directory being read written 200 Contact Philips Applications 1005 Unknown command line option found Use a valid command line option 2300 Error in BLIF file lt file gt at line lt number gt Unknown character Regenerate the BLIF file 2302 Unknown token in BLIF file at line lt numbers gt Regenerate the BLIF file 237 2305 Syntax error file lt file gt near line lt number gt Regenerate the BLIF file 2315 File lt file gt line lt number gt error in pla format Regenerate pla file and verify that there are no errors See p 3 1 to 3 17 of Open Abel Technical Specification for correct sy
227. uted the design 3244 lt pin name gt is a floating node It will be assigned to a pin Indicates that an unused node is an input and that it will be assigned to pin lt pin name gt 244 3248 Pin feedback for signal lt signal name gt is invalid due to output disable Indicates that you are using feedback from pin lt signal name gt that has an output enable When the output is off the logic that uses the feedback will be undefined 3249 Output enable for NODE node names is ignored Indicates that buried node node name was assigned an output enable which will do nothing because it is not an output Fatal Errors 3206 Out of memory Your system does not have enough memory to run the process requested Close other applications and try again 3207 Identifier table full There are too many identifier names Reduce the number of variable names in your design 3208 BLIF file is not supported The BLIF file you have tried to read in 1s not supported by the Device Kit 3209 Unable to open close file name gt The file you are trying to access either has a different name or does not exist 3214 Invalid device name or not a valid device You must use only device names listed in the Device Kit 3215 extension is not a valid extension Indicates that the dot extension extension is not supported 3216 Design exceeds maximum number of synchronous clocks You are trying to use more synchronous clocks than th
228. uts referred to by the variable sum are assigned with an equation to be the addition of inputs a b and carryin Equations can also be part of a when then else structure used to implement more complicated logic designs when then else structure is similar in use to the familiar if then else structure but it must be used with equations if then else is used only for state machine implementation The general syntax of the when then else structure 15 when expression then equations 1 else equations_2 k If expression is true then equations_1 are implemented if expression if false then equations_2 are implemented The following example of a 16 bit up down counter shows how to use the when then else structure In this design when the input signal dir 1s equal to 0 the counter will count up when the input dir is equal to 1 the counter will count down Module updnl xl Title Single 16 bit up down counter Detine inputs and outputs clk pin 54 dir pin c15 cOpin istype Define variables c out c15 cO equations Count up when dir 0 count down when dir 1 when dir 0 then c_out d c_out q 1 else c_out d c_out q 1 end PHDL also supports nested when then else structures The general syntax for that type of structure 15 when expression 1 then equations 1 j else when expression 2 then equations_2 else equations_3 J In t
229. xtensions in a 16 bit counter design Notice the use of the dot extensions on lines 22 and 23 to create the clock and an asynchronous reset The clock of the counter output registers c_out clk is assigned to the input signal used for the clock clk with the clk dot extension Similarly the counter reset c out ar is assigned to the input signal used for the asynchronous reset rst Also notice the use of the t and q extensions on line 27 to create the counter This equation assigns the input of the flip flop to be the output of the flip flop plus binary one Thus on the next clock pulse the output of the flip flops are incremented by one and the inputs to the flip flops now take on that new incremented value The t extension specifies that the counter will use t type flip flops and the q extension specifies internal register feedback as opposed to output pin feedback for calculating the next count value Module cntr16x1 Title Single 16 bit counter with reset Inputs Outputs c15 cO pin istype 48 Create a variable for counter outputs c out 15 0 equations Use clk and ar dot extensions to create clock and reset c out clk clk c out ar rst Use t and q dot extensions to create counter from t flip flops c out d c out q 1 end Clocking Generating and Assigning Clocks Clocks are specified in PHDL designs with dot extensions Clocks can be either synchronous or asyn

XPLA Designer v2.1 User`s Manual

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