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Datasheet - STMicroelectronics

1. millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 7 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD14952 Rev 10 83 99 Package information STM8AF6246 48 66 68 84 99 Figure 46 LQFP48 48 pin 7 x 7 mm low profile quad flat package recommended footprint F DIEN mmm LX A o y o Y ai14911d 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 47 LQFP48 marking example package top view Sec XXXXXX XXXXXX Date code Standard ST logo Revision code Pin 1 identifier MS37791V1 DocID14952 Rev 10 Ly STM8AF6246 48 66 68 Package information 11 3 LQFP32 package information Figure 48 LQFP32 32 pin 7 x 7 mm low pro
2. 1 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors The parameter maximum value must be respected for the full application range 2 This frequency of 1 MHz as a condition for Vcap parameters is given by design of internal regulator Figure 8 fcpumax Versus Vpp feru MHz Functionality SE not guaranteed in M this area 16 12 F nctioranty guaranteed Do Ta 40 to 150 C Eu 4 0 3 0 4 0 5 0 5 5 Supply voltage V MSv37798V1 52 99 DocID14952 Rev 10 Ly STM8AF6246 48 66 68 Electrical characteristics 2 Table 22 Operating conditions at power up power down hysteresis Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 20 00 top us V Vpp fall time rate 20 00 Reset release delay Vpp rising 1 1 7 ms TEMP Reset generation delay Vpp falling 3 us Power on reset Vire threshold 3 2 65 2 8 2 95 V V Brown out reset 2 58 273 2 88 dh threshold Brown out reset VHYS BOR E 70 1 e mV Guaranteed by design not tested in production If Vpp is below 3 V the code execution is guaranteed above the Vt and Vj thresholds RAM content is kept The EEPROM programming sequence must not be initiated There is inrush current into Vpp present after device power on to c
3. IH H MSv38341V1 68 99 DocID14952 Rev 10 Ly STM8AF6246 48 66 68 Electrical characteristics 10 3 8 TIM 1 2 3 and 4 timer specifications Subject to general operating conditions for Vpp fyaster and Ta unless otherwise specified Table 37 TIM 1 2 3 and 4 electrical specifications Min Typ Symbol Parameter Conditions Max Unit Timer external clock frequency 16 MHz fext 1 Not tested in production On 64 Kbyte devices the frequency is limited to 16 MHz 10 3 9 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 38 are derived from tests performed under ambient temperature fyaster frequency and Vpp supply voltage conditions tMASTER 1 MASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 38 SPI characteristics Symbol Parameter Conditions Min Max Unit Master mode 0 10 i fsck SPI clock frequency Vpp lt 4 5 V 0 e MHz Itctsck Slave mode Vpp 4 5 V to 5 5 V 0 e tusck SPI dock rise and fall time Capacitive load C 30 pF 252 t sck tsunss NSS setup time Slave mode 4 tMASTER trnss NSS hold time Slave mode 70 3 Gelee SCK high and low time Master mode tsck 2 15 tscK 2 15 w SCKL t 3 Master mode 5 S
4. Standard mode IZC Fast mode CH Symbol Parameter Unit Min Max Min Max twscLL SCL clock low time 4 7 1 3 us tw SCLH SCL clock high time 4 0 0 6 tsuspA SDA setup time 250 100 E th sDA SDA data hold time 068 o 9008 tyspay SDA and SCL rise time ns 1000 300 tScL Vpp 3 to 5 5 V SDA SDA and SCL fall time 300 300 t scL Vpp 3 to 5 5 V ty stay _ START condition hold time 4 0 0 6 tsusrA Repeated START condition setup time 4 7 0 6 tsusto STOP condition setup time 4 0 0 6 HS t STOP to START condition time 47 13 w STO STA bus free gt g gt H Cp Capacitive load for each bus line 400 400 pF 1 faster must be at least 8 MHz to achieve max fast 12C speed 400 kHz 2 Data based on standard DC protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time undefined region of the falling edge of SCL DoclD14952 Rev 10 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the 2 STM8AF6246 48 66 68 Electrical characteristics 10 3 11 10 bit ADC characteristics Subject to general operating conditions for Vppa faster and Ta unless otherwise specified Table 40 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit fapc ADC clock frequency 1
5. STM8AF6246 48 66 68 Electrical characteristics Figure 17 HSE oscillator circuit diagram Rm fuse to core gt m3 COT Re Cm E o pi USCH g Resonator 74 ejes Current control Resonator al L a Gs OSCOUT STM8 MSv37799V1 HSE oscillator critical g formula The crystal characteristics have to be checked with the following formula 9m 9merit where Gmcrit can be calculated with the crystal parameters as follows f 2 2 Imerit 2 x TI x HSE xR 2Co C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 4 Cp C Grounded external capacitance 10 3 4 Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and Ta High speed internal RC oscillator HSI Table 30 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fysi Frequency 16 MHz ky DoclD14952 Rev 10 59 99 Electrical characteristics STM8AF6246 48 66 68 Table 30 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit i icati 40 B 1 HSI oscillator user ee by a ae 1 trimming accuracy i a 0 5 1 0 5 1 ACC ue 3 0V lt Von lt 5 5 V E 5 HSI oscill
6. Table 27 Typical peripheral current consumption Vpp 5 0 V Symbol Parameter Typ fmaster TYP master Unit 2 MHz 16 MHz IDD TIM1 TIM1 supply current 0 03 0 23 IDD TIM2 TIM2 supply current 2 0 02 0 12 IDD TIM3 TIM3 supply current 0 01 04 IDD TIM4 TIM4 supply current 0 004 0 03 lppwinuart _ LINUART supply current 0 03 0 11 IDD sP1 SPI supply current 0 01 0 04 mA IDD 12C 12C supply current 0 02 0 06 IpD AWU AWU supply current 0 003 0 02 Ipp TOT DIG All digital peripherals on 0 22 1 ADC supply current when IDD ADC converting 0 93 0 95 1 Typical values not tested in production Since the peripherals are powered by an internally regulated constant digital supply voltage the values are similar in the full supply voltage range 2 Data based on a differential Ipp measurement between no peripheral clocked and a single active peripheral This measurement does not include the pad toggling consumption 3 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions Current consumption curves Figure 10 to Figure 15 show typical current consumption measured with code executing in RAM Figure 10 Typ IDD RUN HSE VS Vpp Figure 11 Typ Ipp RUN HSE vs fcpu fcpy 16 MHz peripheral on Vpp 5 0 V peripheral on 25 C 85C 25C loorun Hse mA
7. 1 All power Vpp Vppio VppA and ground Vss Vssio Vssa pins must always be connected to the external power supply 2 lingcpin must never be exceeded This is implicitly insured if Vjy maximum is respected If Vu maximum cannot be respected the injection current must be limited externally to the Iw up value A positive injection is induced by V y gt Vpp while a negative injection is induced by V y lt Vss For true open drain pads there is no positive injection current and the corresponding Vjy maximum must always be respected 2 50 99 DoclD14952 Rev 10 STM8AF6246 48 66 68 Electrical characteristics 2 Table 18 Current characteristics Unit mA Symbol Ratings Max lvppio Total current into Vppjo power lines source X23 100 lvssio Total current out of Vss jo ground lines sink 2 100 Output current sunk by any I O and control pin 20 to Output current source by any I Os and control pin 20 linue Injected current on any pin 10 liNJ TOT Sum of injected currents 50 All power Vpp Vppio VppA and ground Vss Vase Vssa pins must always be connected to the external supply The total limit applies to the sum of operation and injected currents Vppio includes the sum of the positive injection currents Vssjo includes the sum of the negative injection currents This condition is implicitly insured if V y maximum is respected If V y maximum cannot be resp
8. loo runpase mA ka Vop VI fcpu MHz 2 56 99 DoclD14952 Rev 10 STM8AF6246 48 66 68 Electrical characteristics Figure 12 Typ Ipp RUN HSI vs Vpp O fcpy 16 MHz peripheral off Figure 13 Typ Ipp wFi HsE vs Vpp O fcpy 16 MHz peripheral on N 0 A OO 3 NW P Om On IDD WFI HSE mA IDD RUN HSI mA 2 5 3 5 4 5 5 5 6 5 2 5 3 5 4 5 5 5 6 5 VDD V VDD V Figure 14 Typ DD WFI HSE VS fcpu Figure 15 Typ DD WFI HSI VS Vpp 9 Vpp 5 0 V peripheral on O fcpy 16 MHz peripheral off 2 5 2 1 5 deret 725C 85 C be 125 C DD WFI HSE mA DD WFI HSI mA fcpu MHz Vbo V 10 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and Ta Table 28 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit Kees BEE clock source bo 00 16 MHz VusEaHL Comparator hysteresis 0 1 x Vpp g Wiens See input pin high level 07 xVpp Von v Ver Ed input pin low level Wee 0 3 x Vpp ILEAK HSE br lee Vss lt Vin lt VoD 1 1 UA 1 In CSS is used the external clock must have a frequency above 500 kHz 2 DoclD14952 Rev 10 57 99 Electrical
9. I SY a ai14134c 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp Figure 38 SPI timing diagram where slave mode and CPHA 1 NSS input l tsU NSS 4 r tc SCk th NSS AE 1 1 1 x i 1 1 3 CPHA 1 y i i mi I z CPOL 0 tw SCKH 1 i m h T i B gt O CPHA 1 twscxty Ze i i de CPOL 1 T H 1 1 K 1 i T twso Pr th S0 A pa SCO ig tdis SO li ta S0 TT MISO OUTPUT we innr OUT eme OUT issour OUT tsu S1 4 th si M MOSI f ai14135b 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Mon 2 70 99 DoclD14952 Rev 10 STM8AF6246 48 66 68 Electrical characteristics Figure 39 SPI timing diagram master mode High NSS input te scKjy gt 5 cPHA 0 3 CPOL 0 k Ph M x CPHA 0 N i i O e 1 l i II N 1 l 3 CPHA 1 5 CPOL 0 h d PEE O I i 1 d 1 x CPHA 1 n i i n 9 CPOL 1 ARONA tte o I r Cer c alle tr SCK TeS tsu MI pama tw SCKL MA PIE E TEN SCK INPUT MSBIN BITS IN LBN l hm MOSI C uson ai14136c 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Mon ky DoclD14952 Rev 10 71 99 Electrical characteristics STM8AF6246 48 66 68 10 3 10 72 99 12C interface characteristics Table 39 I C characteristics
10. O Fle E vo To function remap Q z 22 27 5 aa Se ion bi L Z sl Eg el 0 uu option bit Ola 2 20 l LL g o gt TIM1_ 22 16 PBO AINO 1 O X X X O1 X X Port BO Analog input O NCC1 AFR5 23 PE7 AIN8 1 O X X O1 X X Port E7 Analog input 8 24 PE6 AIN9 VOX X X O1 X X PortE7 Analog input 9 25 17 PE5 SPIL_NSS_ I O X X X O1 X X Port E5 SPI master slave select 26 18 PC1 TIM1 CH1 I O X X X HS O3 X X Port C1 Timer 1 channel 1 27 19 PC2 TIM1_CH2 O X X X HS O3 X X Port C2 Timer 1 channel 2 28 20 PC3 TIM1_CH3 I O X X X HS O3 X X Port C3 Timer1 channel3 29 21 PC4 TIM1_CH4 l O X X X HS O3 X X PortC4 Timer1 channel4 30 22 PC5 SPILSCK l JO X X X O3 X X Port C5 SPI clock 31 Vssio 2 S IO ground 32 VVppio2 Sl 1 1 1 1 MO power supply SPI master out 33 23 PC6 SPI MOSI 1 O X X X O3 X X Port C6 h slave in 34 24 PC7 SPI_MISO OL X X X 103 X X Port C7 SPI master in slave out 35 PGO VOX X O1 X X PortGO l 36 PG1 VOX X O1 X X Port G1 l 37 PE3 TIM1_BKIN O X X X O1 X X Port E3 Timer 1 break input 38 PE2 2C SDA VvO X X O1 T O PortE2 I C data 39 PE1 C SCL VOX X O1 T O PortE1 12C clock 40 PEO CLK CCO
11. fe y life augmented STM8AF6246 STM8AF6248 STM8AF6266 STM8AF6268 Automotive 8 bit MCU with up to 32 Kbyte Flash data EEPROM 10 bit ADC timers LIN SPI I2C 3 to 5 5 V Features June 2015 Core Max fepy 16 MHz Advanced STMB8A core with Harvard architecture and 3 stage pipeline Average 1 6 cycles instruction resulting in 10 MIPS at 16 MHz fcpy for industry standard benchmark Memories Flash Program memory 16 to 32 Kbyte Flash data retention 20 years at 55 C after 1 kcycle Data memory 0 5 to 1 Kbyte true data EEPROM endurance 300 kcycle RAM 2 Kbyte Clock management Low power crystal resonator oscillator with external clock input Internal user trimmable 16 MHz RC and low power 128 kHz RC oscillators Clock security system with clock monitor Reset and supply management Wait auto wakeup Halt low power modes with user definable clock gating Low consumption power on and power down reset Interrupt management Nested interrupt controller with 32 vectors Up to 34 external interrupts on 5 vectors Timers Up to 2 general purpose 16 bit PWM timers with up to 3 CAPCOM channels each IC OC or PWM Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization 8 bit AR basic timer with 8 bit prescaler Auto wakeup timer Datasheet production data H L
12. the note about the parts marked E and ES below Figure 51 STM8AF6246 48 66 68 ordering information scheme 1 2 the standard for EMI characteristics in Table 43 EMI data Removed the references to STM8AF61xx and STM8AH61xx obsolete products Moved Section 11 4 Thermal characteristics to Section 11 Package information 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces infor
13. 125 C Parts must be ordered at least with the temperature range suffix C 2 DoclD14952 Rev 10 89 99 Ordering information STM8AF6246 48 66 68 12 90 99 Ordering information Figure 51 STM8AF6246 48 66 68 ordering information scheme 2 Example 8 bit automotive microcontroller Program memory type STM8A Product class F F Flash EEPROM P FASTROM Device family 62 Program memory size 62 Silicon rev X and rev W LIN only 6 6 4 16 Kbyte 6 32 Kbyte Pin count 6 32 pins 8 48 pins HSI accuracy Blank 5 96 1542 5 96 Package type T D xxx v T LOFP U VFQFPN Temperature range A 40 to 85 C C 40 to 125 C D 40 to 150 C Packing Y Tray U Tube X Tape and reel compliant with EIA 481 C 1 Fora list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the nearest ST Sales Office 2 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decisio
14. 2 MHz e True open drain PBC interface To decrease EMI electromagnetic interference high sink I Os have a limited maximum slew rate The rise and fall times are similar to those of standard I Os The analog inputs are equipped with a low leakage analog switch Additionally the schmitt trigger input stage on the analog I Os can be disabled in order to reduce the device standby consumption STMBA I Os are designed to withstand current injection For a negative injection current of 4 mA the resulting leakage current in the adjacent input does not exceed 1 pA Thanks to this feature external protection diodes against current injection are no longer required 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Pinouts and pin description 6 6 1 2 Pinouts and pin description Package pinouts Figure 3 VFQFPN LQFP 32 pin pinout OSCOUT PA2 L1 OO JO om E Go CH2 ADC_ETR 3 CH1 TIM2 CH3 PD5 LINUART TX HS TIM2 CH1 BEEP HS TIM3 CH2 CLK CCO TIM1 BRK HS TIM2 HS TIM HS SWIM PD6 LINUART RX PD4 PD3 PD2 PD1 NE PDO SO PD7 TLI 2 w o N N N N N o N N DB 22 1 9 10111213 141516 LAIONTO A od oo oo o ovoaaaad 5 E E E E 1 st CO QN TO 222222 fii Eet EE OO oo Qo Ou III Ig 100909 Q Lt t Gi Ce e e
15. 6 2 Alternate function remapping 31 Memory and register map 32 7 1 Memory Map EE 32 7 2 Register Map sk aces c KAKANAN KGG BAK bA dakitari SR EH UR ARRA 33 Interrupt table sii ssn a Sar APAPAP 43 Option by es Neu sac Ga eee ee ee 44 Electrical characteristics ee ee NEEN ra gg 49 10 4 Parameter conditions Nu EINEN eee eevee ed EE REN becuase 49 10 1 1 Minimum and maximum values 49 10 12 Typical values ENNER ENEE ERR IER yew RR ead 49 10 4 3 Typical curves ooo 49 10 4 4 Loading capacitor ee 49 10 1 5 Pin input voltage 11 11 1121 eee 50 10 2 Absolute maximum ratings lille 50 10 3 Operating conditions XXX xut crees KAKA RK KAG oP AE EE Lah 52 10 3 1 VCAP external capacitor lille 54 10 3 2 Supply current characteristics 54 10 3 3 External clock sources and timing characteristics 57 10 3 4 Internal clock sources and timing characteristics 59 10 3 5 Memory characteristics ee 62 10 3 6 I O port pin characteristics o oooooooooooooo ooo o 63 DoclD14952 Rev 10 3 99 Contents STM8AF6246 48 66 68 10 3 7 Reset pin characteristics 020 eee 67 10 3 8 TIM 1 2 3 and 4 timer specifications 1 1 1 2222 2222 69 10 3 9 SPI serial peripheral interface 69 10 3 10 PC interface characteristics e 72 10 3 11 10 bit ADC characteristics a 73 10 3 12 EMC characteristics e 75 11 Package informa
16. DD RUN RUN E un mode _ land EEPROM HSE fopy 4 MHz 14 200 external clock without resonator fopy 2 MHz 1 0 1 5 mA fopy 16 MHz 1 65 2 5 Supply CPU stopped all fcpu 8 MHz 1 15 1 90 Ibowrn current in peripherals off HSE Wait mode external clock fopu 4 MHz 0 90 1 62 fopy 2 MHz 0 80 1 5 fepy scaled down Ext clock 16 MHz 4 50 1 95 1 Supply all peripherals off fcpu 125 kHz ops ou current in code executed from Slow mode LSI internal RC 4 50 1 800 RAM fopy 128 kHz 1 The current due to I O utilization is not taken into account in these values 2 Values not tested in production Design guidelines only 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Electrical characteristics Table 24 Total current consumption in Halt and Active halt modes General conditions for Vpp apply Ta 40 to 55 C Conditions Main Clock source and Symbol Parameter voltage Flash specific Typ Max Unit regulator mode temperature MVR condition Clocks stopped 5 35 3 Suppl tin Halt mod Off PONES DD H upply current in Halt mode dew Clocks stopped 5 m Ta 25 C Ext clock 16 MHz 770 3 Supply current in Active halt Power fMASTER 125 kHz 900 On HA mode with regulator on down Fer TT TIT LSI clock 128 kHz 150 230 Ipp AH LSI clock 128 kHz 25 420 Supply current in Active halt Off Power mode with regulator
17. VOX x X o3 x x Ported Conigurable clock _ output TIM1_BKIN 41 25 PDO TIM3 CH2 l O x X x HS o3 X X Port DO Timer3 channel2 IP CLK CCO AFR2 42 26 PD1 SWIM 1 O X X X HS O4 X X PortD1 SWIM data interface 43 27 PD2 TIM3 CH1 1 O X X X HS O3 X X Port D2 Timer 3 channel 1 Ur 44 28 PD3 TIM2 CH2 1 O X X X HS 03 X X Port D3 Timer 2 channel 2 c 30 99 DoclD14952 Rev 10 ky STM8AF6246 48 66 68 Pinouts and pin description Table 8 STM8AF6246 48 66 68 32 Kbyte microcontroller pin description 2 continued number Input Output E e 5 Alternate T 2 2 29 Default alternate function after co amp Pin name Sl o 2 t 3r O Fl EI al 3 5 function remap 3 327983 aa s2 option bit z S SI E cl O sS p Oa 9 E o l LL g o gt PD4 TIM2_CH1 BEEP output 45 29 BEEP lO X X X HS O3 X X Port D4 Timer 2 channel 1 AFR7 46 30 PDS lO X X X 101 X X Port D5 LINUART data transmit LINUART_TX PD6 LINUART 47 31 LINUART RX lO X X X O1 X X Port D6 data receive 48 32 PD7 TLIO JO X X X O1 X X Port D7 Top level interrupt Reset state is shown in bold Refer to Table 7 for the definition of the abbreviations In Halt Active halt mode this pad behaves in the following way the input output path is disabled if t
18. e Interrupt source 1 x overflow update 2 22 99 DoclD14952 Rev 10 STM8AF6246 48 66 68 Product overview 5 8 Note 5 9 2 Analog to digital converter ADC The STM8A products described in this datasheet contain a 10 bit successive approximation ADC with up to 16 multiplexed input channels depending on the package The ADC name differs between the datasheet and STM8S series and STM8AF series 8 bit microcontrollers reference manual see Table 5 Table 5 ADC naming Peripheral name in reference manual Peripheral name in datasheet RM0016 ADC ADC1 ADC features e 10 bit resolution e Single and continuous conversion modes e Programmable prescaler fyasteR divided by 2 to 18 e Conversion trigger on timer events and external events e Interrupt generation at end of conversion e Selectable alignment of 10 bit data in 2 x 8 bit result register e Shadow registers for data consistency e ADC input range VssA Vin lt VppA e Analog watchdog e Schmitt trigger on analog inputs can be disabled to reduce power consumption e Scan mode single and continuous e Dedicated result register for each conversion channel e Buffer mode for continuous conversion An additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog Values converted from AIN12 are stored only into the ADC DRH ADC DRL registers Communication interfaces The following sections give a brief
19. output S power supply Level Input CM CMOS standard for all I Os Output HS High sink 8 mA Output speed O1 Standard up to 2 MHz Reset state Port and control Input float floating wpu weak pull up SONG Output T true open drain OD open drain PP push pull Bold X pin state after reset release Unless otherwise specified the pin state is the same during the reset phase i e under reset and after internal reset release i e at reset state 28 99 DoclD14952 Rev 10 2 STM8AF6246 48 66 68 Pinouts and pin description Table 8 STM8AF6246 48 66 68 32 Kbyte microcontroller pin description Pin iimbak Input Output E e 2 5 Alternate a Pi amp eo Default alternate function after c9 in name EI o 3 5 O Fle vo 5 function remap A zia 2 9 3 ala zz i i Liz s S E sl 06 58 option bit Oa 9 Ei o l LL gt I e x L LL gt 1 1 NRST UO X Reset 2 2 PA1 OSCIN O X X O1 X X Port A1 Resonator crystalin 3 PA2 OSCOUT VO X X X O1 X X Port A2 Resonator crystal out 4 Vssio 1 S O ground 5 4 Vss S Digital ground 6 5 VCAP S 11 8 V regulator capacitor 7 6 Von S Di
20. unwanted modification In the STM8A a memory area of up to 32 Kbyte can be protected from overwriting at user option level Other than the standard write protection the UBC protection can exclusively be modified via the debug interface the user software cannot modify the UBC protection status The UBC memory area contains the reset and interrupt vectors and its size can be adjusted in increments of 512 bytes by programming the UBC and NUBC option bytes see Section 9 Option bytes on page 44 Figure 2 Flash memory organization of STM8AF6246 48 66 68 ERA 1 Programmable UBC area area maximum Remains write protected during IAP 32 Kbyte Flash program memory Flash program memory area Write access possible for IAP Data Data memory area 1 Kbyte EEPROM memory Option bytes MS37794V1 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Product overview 5 4 4 5 5 5 5 1 2 Read out protection ROP The STM8A provides a read out protection of the code and data memory which can be activated by an option byte setting see the ROP option byte in section 10 The read out protection prevents reading and writing Flash program memory data memory and option bytes via the debug module and SWIM interface This protection is active in all device operation modes Any attempt to remove the protection by overwriting the ROP option byte triggers a global erase of the program and data mem
21. 1xx product line up SPI description in Features The typical and maximum values for treyp reset release delay in Table Operating conditions at power up power down The symbol for NRST Input not filtered pulse duration in Table NRST pin characteristics The address and comment of Reset interrupt in Table STM8A interrupt table Added the three footnotes to Figure VFQFPN 32 lead very thin fine pitch quad flat no lead package 5 x 5 Updated Table HSI oscillator characteristics Added HSI accuracy and removed temperature range B in Figure Ordering information scheme 1 12 Nov 2014 Updates in Table HSI oscillator characteristics HSI oscillator accuracy factory calibrated values and Figure Ordering information scheme 1 changed the value for DoclD14952 Rev 10 97 99 Revision history STM8AF6246 48 66 68 98 99 Table 50 Document revision history continued Date 09 Jun 2015 Revision 10 Changes Updated the product naming in the document headers and captions LIN version in Features and Section 5 9 3 Universal asynchronous receiver transmitter with LIN support LINUART Added the third table footnote to Table 22 Operating conditions at power up power down Figure 44 VFQFPN32 marking example package top view Figure 47 LQFP48 marking example package top view Figure 50 LQFP32 marking example package top view
22. 202 Load 20 pF Standard and high sink I Os 50 2 Load 20 pF Digital input pad leakage likg don purp 9 Vss lt Vin lt Vpp 1 HA Vss lt ViNS Vpp 4250 Analog input pad leakage 40 C lt TA lt 125 C E Ikg ana current Vss Mus Vias apn 40 C lt TA lt 150 C a likg inj SE lk Injection current 4 mA 1 3 UA Ippio Otal CUMETIE CN einer Including injection currents 60 mA Vppio or Vssio A Ly DoclD14952 Rev 10 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 63 99 Electrical characteristics STM8AF6246 48 66 68 2 Guaranteed by design 3 Data based on characterization results not tested in production Figure 20 Typical Vj and Vj Vs Vpp four temperatures 6 40 C 5 m 25 C 85 C 4 125 C 2 5 3 3 5 4 4 5 5 5 5 6 Vbo V Figure 21 Typical pull up resistance Rpy vs Vpp four temperatures 60 al al a o S o Pull Up resistance k ohm R al w a wo o d 64 99 DoclD14952 Rev 10 STM8AF6246 48 66 68 Electrical characteristics Figure 22 Typical pull up current l u vs Vpp four temperatures 140 120 100 E 5 80 40 C a 2 a 25 C a 40 85 C 20 125 C 04 r T T j 0
23. Class value D Unit V Electrostatic discharge voltage T 25 C conforming to 3A 4000 ESD HBM Human body model JESD22 A114 V Electrostatic discharge voltage Taz 25 C conforming to 3 500 V ESD CDM Charge device model JESD22 C101 V Electrostatic discharge voltage Taz 25 C conforming to B 200 ESD MM Machine model JESD22 A115 1 Data based on characterization results not tested in production 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Electrical characteristics 2 Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e A supply overvoltage applied to each power supply pin and e A current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the ElA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 45 Electrical sensitivities Symbol Parameter Conditions Class 1 52556 TA 85 C LU Static latch up class A Ta 125 C Ta 150 C 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard DoclD14952 Rev 10 77 99 Package information STM8AF6246 48 66 68 11 78 99 P
24. EEPROM memory General conditions Ta 40 to 150 C Table 32 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit V Operating voltage fcpu is O to 16 MHz 3 0 55 DD all modes execution write erase with O ws V V Operating voltage fcpu is 0 to 16 MHz 26 55 DD code execution with O ws i Standard programming time including erase for byte word block 6 6 6 bios 1 byte 4 bytes 128 bytes Fast programming time for 1 block 3 33 128 bytes i terase Erase time for 1 block 128 bytes 3 3 3 Table 33 Flash program memory Symbol Parameter Condition Min Max Unit Twe Temperature for writing and erasing 40 150 C Flash program memory endurance E Nwe erase write cycles Lu 1990 cycles Ta 25 C 40 tRET Data retention time Y years Ta 55 C 20 1 The physical granularity of the memory is four bytes so cycling is performed on four bytes even when a write erase operation addresses a single byte Table 34 Data memory Symbol Parameter Condition Min Max Unit Twe _ Temperature for writing and erasing 40 150 C Data memory endurance Ta 25 C 300 k S Nwe cycles erase write cycles Ta 40 C to 125 C 100 k 2 Ta 25 C 4029 trer Data retention time years Ta 55 C 20000 1 The physical granularity of the memory is four bytes so cy
25. IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF ges OS Reserved area 13 bytes 0x00 50FO AWU CSR1 AWU control status register 1 Ox00 0x00 50F1 AWU AWU APR AWU didis S l buffer Ox3F 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 DoclD14952 Rev 10 35 99 Memory and register map STM8AF6246 48 66 68 Table 11 General hardware register map continued Address Block Register label Register name Wee 0x00 50F3 BEER BEEP_CSR BEEP control status register Ox1F KSC Ge Reserved area 12 bytes 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 0x00 5204 ii SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF ene SE Reserved area 8 bytes 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 DC CR2 I2C control register 2 0x00 0x00 5212 DC FREQR I2C frequency register 0x00 0x00 5213 DC OARL I2C own address register low 0x00 0x00 5214 I2C OARH I2C own address register high 0x00 0x00 5215 Reserved area 1 byte 0x00 5216 DC DR I2C data register 0x00 0x00 5217 sin I2C_SR1 I2C status register 1 0x
26. Table I O static characteristics added new condition and new max values for rise and fall time updated the footnote 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Revision history 2 Table 50 Document revision history continued Date 18 Jul 2012 Revision 6 continued Changes Section Reset pin characteristics updated text below Figure Typical NRST pull up current Ipu vs VDD Figure Recommended reset pin protection updated unit of capacitor Table SPI characteristics updated SCK high and low time conditions and values Figure SPI timing diagram master mode replaced SCK input signals with SCK output signals Updated Table VFQFPN 32 lead very thin fine pitch quad flat no lead package mechanical data Table LQFP 48 pin low profile quad flat package mechanical data and Table LQFP 32 pin low profile quad flat package mechanical data Replaced Figure LQFP 48 pin low profile quad flat package 7 x 7 and Figure LQFP 32 pin low profile quad flat package 7 x 7 Added Figure LQFP 48 pin recommended footprint and Figure LQFP 32 pin recommended footprint Figure Ordering information scheme 1 added footnote 7 added xxx and footnote 2 updated example and device family added FASTROM Section C and assembly toolchains added www iar com 04 Apr 2014 24 Jun 2014 Updated Table Device summary Table STM8AF62xx product line up Table STM8AF H6
27. Thermal resistance junction ambient Oa LQFP 48 7 x 7 mm 3f on Thermal resistance junction ambient 5 Oa LQFP 32 7 x 7 mm P e Thermal resistance junction ambient Hu VFQFPN32 dd CIN 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Section 12 Ordering information The following example shows how to calculate the temperature range needed for a given application 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Package information Assuming the following application conditions Maximum ambient temperature Tamax 82 C measured according to JESD51 2 Ippmax 14 MA Vpp 5 V maximum 20 I Os used at the same time in output at low level with lo 8 MA Vo 2 0 4 V Pintmax 14 mA x 5 V 70 mW Piomax 20 x 8 mA x 0 4 V 64 mW This gives Pintmax 70 mW and Pjomax 64 mW Ppmax 70 mW 64 mW Thus Ppmax 134 mW Using the values obtained in Table 49 Thermal characteristics T max is calculated as follows For LQFP64 46 C W Timax 82 C 46 C W x 134 mW 82 C 6 C 88 C This is within the range of the suffix C version parts 40 lt Ty lt
28. This counter is used to cyclically wakeup the device in Active halt mode It can be clocked by the internal 128 kHz internal low frequency RC oscillator or external clock LSI clock can be internally connected to TIM3 input capture channel 1 for calibration 5 7 3 Beeper This function generates a rectangular signal in the range of 1 2 or 4 kHz which can be output on a pin This is useful when audible sounds without interference need to be generated for use in the application 5 7 4 Advanced control and general purpose timers STMBA devices described in this datasheet contain up to three 16 bit advanced control and general purpose timers providing nine CAPCOM channels in total A CAPCOM channel can be used either as input compare output compare or PWM channel These timers are named TIM1 TIM2 and TIM3 Table 3 Advanced control and general purpose timers Timer Counter Counter Prescaler Channels Inverted Repetition trigger External Break width type factor outputs counter unit trigger input TIM1 16 bit Up down 1 to 65536 4 3 Yes Yes Yes Yes 2 TIM2 16 bit Up 15 3 None No No No No 2 TIM3 16 bit Up n 0to 15 2 None No No No No 2 DoclD14952 Rev 10 21 99 Product overview STM8AF6246 48 66 68 TIM1 Advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability t
29. are guaranteed due to application scalability across a common family product architecture with compatible pinout memory map and modular peripherals Full documentation is offered with a wide choice of development tools Product longevity is ensured in the STM8A family thanks to their advanced core which is made in a state of the art technology for automotive applications with 3 3 V to 5 V operating supply All STM8A and ST7 microcontrollers are supported by the same tools including STVD STVP development environment the STice emulator and a low cost third party in circuit debugging tool 2 10 99 DoclD14952 Rev 10 STM8AF6246 48 66 68 Product line up 3 Product line up Table 1 STM8AF6246 48 66 68 product line up Medium density UO Order code Package Flash RAM Data EE 10 bit Timers Serial Wakeu 9 program byte byte A Dch IC OC PWM interfaces ins p memory p byte STM8AF P6268 32 K 1K 1x8 bit TIM4 LQFP48 10 3x16 bit TIM1 LINUART 59735 STM8AF P6248 7x7 16K 0 5K TIM2 TIM3 SPI lC 9 9 9 STM8AF P6266 32 K 1K 1x8 bit TIM4 LQFP32 3x16 bit TIM1 LIN UART 2K 7 25 23 STM8AF P6246 7x7 16K 0 5K AMG CMS SENS 8 8 8 STM8AF P6266 32 K 1K 1x8 bit TIM4 3x16 bit TIM1 LIN UART VFQFPN32 7 25 23 STM8AF P6246 16K 0 5K TIM2 TIM3 SPI FC 8 8 8 Ky DoclD14952 Rev 10 11 99 Block diagram STM8AF6246 48 66 68 4 Blo
30. detection with separate flag and interrupt source for read back checking Slave mode e Autonomous header handling one single interrupt per valid header e Mute mode to filter responses e Identifier parity error checking e LIN automatic resynchronization allowing operation with internal RC oscillator HSI clock source e Break detection at any time even during a byte reception e Header errors detection Delimiter too short Synch field error Deviation error if automatic resynchronization is enabled Framing error in synch field or identifier field Header time out DoclD14952 Rev 10 25 99 Product overview STM8AF6246 48 66 68 5 10 26 99 UART mode e Full duplex asynchronous communications NRZ standard format mark space e High precision baud rate generator Acommon programmable transmit and receive baud rates up to fysster 16 e Programmable data word length 8 or 9 bits 1 or 2 stop bits parity control e Separate enable bits for transmitter and receiver e Error detection flags e Reduced power consumption mode e Multi processor communication enter mute mode if address match does not occur e Wakeup from mute mode by idle line detection or address mark detection e Two receiver wakeup modes A Address bit MSB Idle line Input output specifications The product features four different I O types e Standard I O 2 MHz e Fastl O up to 10 MHz e High sink 8 mA
31. module USART Universal synchronous asynchronous receiver transmitter Window WDG Window watchdog DoclD14952 Rev 10 13 99 Product overview STM8AF6246 48 66 68 5 5 1 14 99 Product overview This section describes the family features that are implemented in the products covered by this datasheet For more detailed information on each feature please refer to STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 STM8A central processing unit CPU The 8 bit STM8A core is a modern CISC core and has been designed for code efficiency and performance It contains 21 internal registers six directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus with single cycle fetching for most instructions e Xand Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter with 16 Mbyte linear memory space e 16 bit stack pointer with access to a 64 Kbyte stack e 8 bit condition code register with seven condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer
32. off down LSI clock 128 kHz ze 30 Ta 25 C Wakeup time from Active On 10 308 halt mode with regulator on O ti t po perang T 40 to 150 C t ps WU AH E mode 5 d Wakeup time from Active Off 50 3 halt mode with regulator off 80 1 Configured by the REGAH bit in the CLK ICKR register 2 Configured by the AHALT bit in the FLASH CR1 register 3 Data based on characterization results Not tested in production Current consumption for on chip peripherals Table 25 Oscillator current consumption Symbol Parameter Conditions Typ Max Unit Quartz or fosc 24 MHz 1 2 06 ceramic resonator osc 16 MHz 98 CL 33 pF i f 8 MHz 0 57 HSE oscillator current Vpp 5 V o MA DD OSC R OSC consumption Quartzor fosc 24MHz 0 5 1 09 ceramic resonator fosc 16 MHz 0 25 CL 33 pF B Mee 33V fosc 8 MHz 0 18 1 During startup the oscillator current consumption may reach 6 mA 2 The supply current of the oscillator can be further optimized by selecting a high quality resonator with small Rp value Refer to crystal manufacturer for more details 3 Informative data 2 DoclD14952 Rev 10 55 99 Electrical characteristics STM8AF6246 48 66 68 Table 26 Programming current consumption Symbol Parameter Conditions Typ Max Unit Vpp 5 V 40 C to 150 C Ipp PROG Programming current erasing and programming data 1 0 1 7 mA or Flash program memory
33. relative addressing mode for efficient implementation of local variables and parameter passing Instruction set e 80 instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transfer using the X and Y registers or direct memory to memory transfers DocID14952 Rev 10 Ly STM8AF6246 48 66 68 Product overview 5 2 5 2 1 5 2 2 5 3 5 4 5 4 1 2 Single wire interface module SWIM and debug module DM SWIM The single wire interface module SWIM together with an integrated debug module permits non intrusive real time in circuit debugging and fast memory programming The interface can be activated in all device operation modes and can be connected to a running device hot plugging The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full flavored emulator Besides memory and peripheral operation CPU operation can also be monitored in real time by means of shadow registers e R W of RAM and peripheral registers in real time e R W for all resources when the application is stopped e Breakpoints on all program memory instructions software breakpoints except the interrupt vector table e
34. 0 75 8 3 0 5 0 25 0 0 5 10 15 20 25 lo mA Figure 29 Typ Vpp Von O Vpp 3 3 V standard ports 2 40 C 25 C 1 75 85 C 1 5 125 C S 1 25 5 gt 1 a gt 0 75 0 5 0 25 0 0 1 2 3 4 5 6 7 Figure 30 Typ Vpp Von O Vpp 5 0 V standard ports 2 40 C m 25 C 1 75 85 C 1 5 125 C 1 25 4 a gt 0 75 0 5 0 25 0 0 2 4 6 8 10 12 Figure 31 Typ Vpp Vou Vpp 3 3 V high sink ports 2 40 C e 25 C 1 75 85 C 1 5 125 C S 1 25 5 gt 1 8 gt 075 0 5 0 25 0 0 2 4 6 8 10 12 14 Figure 32 Typ Vpp Vou Y Vpp 5 0 V high sink ports 5 40 C 25 C 1 75 85 C 1 5 125 C 1 25 gt 014 8 2 075 0 5 0 25 0 0 5 10 15 20 25 lon mA 66 99 DoclD14952 Rev 10 2 STM8AF6246 48 66 68 Electrical characteristics 10 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 36 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vit NRsT NRST input low level voltage Vss 0 3 x Vpp Vuen NRST input high level voltage 0
35. 00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 DC SR3 I2C status register 3 0x00 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B DC CCRL I2C clock control register low 0x00 0x00 521C DC CCRH I2C clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 pe iy Reserved area 24 bytes 36 99 DoclD14952 Rev 10 2 STM8AF6246 48 66 68 Memory and register map Table 11 General hardware register map continued Address Block Register label Register name Wes 0x00 5240 UART2_SR LINUART status register OxCO 0x00 5241 UART2 DR LINUART data register OxXX 0x00 5242 UART2 BRR1 LINUART baud rate register 1 0x00 0x00 5243 UART2_BRR2 LINUART baud rate register 2 0x00 0x00 5244 UNUART UART2_CR1 LINUART control register 1 0x00 0x00 5245 UART2_CR2 LINUART control register 2 0x00 0x00 5246 UART2_CR3 LINUART control register 3 0x00 0x00 5247 UART2_CR4 LINUART control register 4 0x00 0x00 5248 Reserved 0x00 5249 UART2_CR6 LINUART control register 6 0x00 or age eserved area 6 bytes 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM
36. 00 53EC ADC _DB6RH ADC data buffer register 6 high 0x00 0x00 53ED ADC _DB6RL ADC data buffer register 6 low 0x00 0x00 53EE ADC DB7RH ADC data buffer register 7 high 0x00 0x00 53EF ADC DB7RL ADC data buffer register 7 low 0x00 0x00 53F0 ADC _DB8RH ADC data buffer register 8 high 0x00 0x00 53F 1 ADC _DB8RL ADC data buffer register 8 low 0x00 0x00 53F2 ADC _DB9RH ADC data buffer register 9 high 0x00 0x00 53F3 ADC DB9RL ADC data buffer register 9 low 0x00 uus xl Reserved area 12 bytes 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADC CR3 ADC configuration register 3 0x00 0x00 5404 ADC DRH ADC data register high OxXX 0x00 5405 ADC DRL ADC data register low OxXX 0x00 5406 ADG ADC_TDRH ADC Schmitt je disable register 0x00 0x00 5407 ADC TDRL ADC Schmitt bs disable register 0x00 0x00 5408 ADC _HTRH ADC high threshold register high OxFF 0x00 5409 ADC_HTRL ADC high threshold register low 0x03 0x00 540A ADC LTRH ADC low threshold register high 0x00 40 99 DoclD14952 Rev 10 2 STM8AF6246 48 66 68 Memory and register map Table 11 General hardware register map continued Address Block Register label Register name
37. 000 eee 15 5 4 1 Architecture EE veka he dea ev eee ba ven Nadel EN 15 5 4 2 Write protection WP 00 cece tee 16 5 4 3 Protection of user boot code UBC 0a 16 54 4 Read out protection ROP 17 5 5 Clock controller 2 0 0 0 000 cee 17 5 5 1 Ek a r AA 17 5 5 2 16 MHz high speed internal RC oscillator HSI 18 5 5 3 128 kHz low speed internal RC oscillator LS1 19 5 5 4 16 MHz high speed external crystal oscillator HSE 19 5 5 5 External clock input 19 5 5 6 Clock security system CS 19 5 6 Low power operating modes 20 5 7 TIMETS aes en ren oer EEREN E CR dew RoR apa Ce AR RRC aa ARO 20 5 7 1 Watchdog timers 0 12 244 eh 20 5 7 2 Auto wakeup counter ooo 21 5 7 3 Beeper vida A Vea ex dua 21 2 99 DoclD14952 Rev 10 Ly STM8AF6246 48 66 68 Contents 10 2 5 7 4 Advanced control and general purpose timers 21 5 7 5 Basicitlimer 422 osse pea Ade ete EE ED CAE ER NR 22 5 8 Analog to digital converter ADC 2 1 2ssk lakka aaa 23 5 9 Communication interfaces 23 5 9 1 Serial peripheral interface GP 24 5 9 2 Inter integrated circuit PC interface SEENEN eee 24 5 9 3 Universal asynchronous receiver transmitter with LIN support EINUARD EE 25 5 10 Input output specifications 26 Pinouts and pin description cece eee eee eee 27 6 1 Package pinouts ue dots k etek EE nin ala eo pic 27
38. 1 3 4 5 6 Von V Note The pull up is a pure resistor slope goes through 0 Typical output level curves Figure 23 to Figure 32 show typical output level curves measured with output on a single pin Figure 23 Typ Vo Vpp 3 3 V standard ports 1 5 40 C 25 C Vo M Figure 24 Typ Vo O Vpp 5 0 V standard ports 45 40 C m 25 C 1 25 85 C 125 C 2 0 75 a 3 0 5 0 25 0 0 2 4 6 8 10 12 lo mA Figure 25 Typ Vo Vpp 3 3 V true open drain ports Figure 26 Typ Vo O Vpp 5 0 V true open drain ports 40 C 2 40 C HH 25 C 25 C 1 75 85 C 1 75 85 C 1 5 125 C 1 5 125 C 1 25 1 25 CI 4 gt gt 0 75 0 75 0 5 0 5 0 25 0 25 0 0 0 2 4 6 8 10 12 14 0 5 10 15 20 25 lo mA lo mA ky DoclD14952 Rev 10 65 99 Electrical characteristics STM8AF6246 48 66 68 Figure 27 Typ Vo Vpp 3 3 V high sink ports 15 40 C 25 C 1 25 85 C 125 C A z 0 75 E gt 0 5 0 25 OF 0 2 4 6 8 10 12 14 lo MA Figure 28 Typ Vo 9 Vpp 5 0 V high sink ports 45 40 C m 25 C 1 25 85 C 125 C 2
39. 1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1 CCMR1 TIM1 capture compare mode register 1 0x00 0x00 5259 TIM1 CCMR2 TIM1 capture compare mode register 2 0x00 0x00 525A TIM1 CCMR3 TIM1 capture compare mode register 3 0x00 0x00 525B TIMA TIM1 CCMRA TIM1 capture compare mode register 4 0x00 0x00 525C TIM1 CCER1 TIM1 ME enable register 0x00 0x00 525D TIM1 CCER2 TIM1 a de enable register 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1_ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 er DoclD14952 Rev 10 37 99 Memory and register map STM8AF6246 48 66 68 38 99 DoclD14952 Rev 10 Table 11 General hardware register map continued Address Block Register label Register name Wem 0x00 5265 TIM1_CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low Ox00 0x00 5267 TIM1_CCR2H TIM1 capture
40. 11 kHz 4 MHz kHz MHz Vppa__ Analog supply 3 E 5 5 Vrer Positive reference voltage 2 75 Vopa Vnggr Negative reference voltage Vssa 0 5 V Vssa VppA Va Conversion voltage range Devices with external Vrer VREF VREF Vrer Pins Csamp Internal sample and hold capacitor 3 pF Sampling time fapc 2 MHz 1 5 z s 3 x 1fapc fapc 4 MHz 0 75 e fADC 2MHz 7 i tsrag Wakeup time from standby HA AAA us fADC 4MHz 3 5 Total conversion time including fapc 2 MHz 7 tconv sampling time 14 x 1 fapc fApc 4 MHz 3 5 a Rswitcn Equivalent switch resistance 7 S 30 kQ 1 During the sample time the sampling capacitance Csamp 3 PF typ can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Figure 40 Typical application with ADC Voo STM8A A o e Rswitch AIN 5 ii AINx 10 bit A D C AN NNW Ts T conversion Vr Cain N6 gv IL T MSv38342V1 1 Legend Rain external resistance Cam capacitors Csamp internal sample and hold capacitor 2 DoclD14952 Rev 10 73 99 Electrical characteristics STM8AF6246 48 66 68 74 99 Table 41 ADC accura
41. 2 capture compare reg 2 high 0x00 0x00 5312 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5313 TIM2 CCR3H TIM2 capture compare register 3 high 0x00 2 STM8AF6246 48 66 68 Memory and register map 2 Table 11 General hardware register map continued Address Block Register label Register name ra 0x00 5314 TIM2 TIM2_CCR3L TIM2 capture compare register 3 low 0x00 pe SCC Reserved area 11 bytes 0x00 5320 TIM3_CR1 TIM3 control register 1 0x00 0x00 5321 TIM3 IER TIM3 interrupt enable register 0x00 0x00 5322 TIM3 SR1 TIMS status register 1 0x00 0x00 5323 TIM3 SR2 TIMS status register 2 0x00 0x00 5324 TIM3 EGR TIM3 event generation register 0x00 0x00 5325 TIM3 CCMR1 TIM3 capture compare mode register 1 0x00 0x00 5326 TIM3 CCMR2 TIM3 capture compare mode register 2 0x00 0x00 5327 ma CCER1 TIM3 SS enable register 0x00 0x00 5328 TIM3 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIMS prescaler register 0x00 0x00 532B TIM3_ARRH TIM3 auto reload register high OxFF 0x00 532C TIM3_ARRL TIM3 auto reload register low OxFF 0x00 532D TIM3_CCR1H TIM3 capture compare register 1 high 0x00 0x00 532E TIM3_CCR1L TIM3 capture compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture compare register 2 high 0x00 0x00 5330 TI
42. 31 99 Memory and register map STM8AF6246 48 66 68 7 Memory and register map 7 1 Memory map Figure 5 Register and memory map of STM8A products 0x00 0000 RAM 2 Kbyte RAM end 0x00 4000 up to 1 Kbyte data EEPROM 0x00 4400 Option bytes Hardware registers 0x00 581D 0x00 6000 2 Kbyte of Boot ROM 0x00 6800 CPU SWIM debug ITC registers Interrupt vectors 0x00 7F00 0x00 8000 0x00 8080 Up to 32 Kbyte of Flash program memory Flash program memory end MS37795V1 2 32 99 DoclD14952 Rev 10 STM8AF6246 48 66 68 Memory and register map 7 2 2 Table 9 Memory model for the devices covered in this datasheet Flash program Flash program memory size memory end y address 32K 0x00 OFFFF 16K 0x00 OBFFF RAM size RAM end Stack roll over address address 2K 0x00 07FF 0x00 0600 Register map In this section the memory and register map of the devices covered by this datasheet is described For a detailed description of the functionality of the registers refer to STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 Table 10 I O port hardware register map Address Block Register label Register name dott 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA IDR Port A input pin value regist
43. 7 x Vpp Vpp V Voumpsen NRST output low level voltage lo 2 3 MA 2 0 6 Humpen NRST pull up resistor 30 40 60 kQ Bes NRST input filtered pulse 85 315 NRST Input not filtered pulse ns tINFP NRST quration 2 500 1 Data based on characterization results not tested in production 2 Data guaranteed by design not tested in production Figure 33 Typical NRST Vj and Vjp vs Vpp four temperatures 40 C di m 25C 5 85 C 125 C 4 s3 KEE 2 1 0 a a _ _ s 2 5 3 3 5 4 5 5 5 5 6 Vo V DoclD14952 Rev 10 67 99 2 Electrical characteristics STM8AF6246 48 66 68 Figure 34 Typical NRST pull up resistance Rpy vs Vpp 60 40 C m 25 C E 55 85 C m 125 C o 50 o c S ee LA Ed 8 45 Q 40 D e C 35 30 2 5 3 3 5 4 4 5 5 5 5 6 Vbo V 140 o o R o NRST Pull Up current uA N o 0 1 2 3 4 5 6 Voo M The reset network shown in Figure 36 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below Vi rst max see Table 36 NRST pin characteristics otherwise the reset is not taken into account internally Figure 36 Recommended reset pin protection VoD STM8A External reset NRST Upa Filter Internal reset circuit 0 1 uF R Optional
44. 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Ly STM8AF6246 48 66 68 block diagram 0 eee 12 Flash memory organization of STM8AF6246 48 66 68 16 VFQFPN LQFP 32 pin pinout o 27 LQFP 48 pin pinout 28 Register and memory map of STM8A products 020 00 e eee eee eee 32 Pin loading conditions sssr rers eerste ada eKA EEEE RI R KARNA 49 Pin input voltage a daa mm R DADA ENN a E ANEN NEEN NEE d 50 fopUmax VEFSUS Von 52 External capacitor Cer 54 Typ IDD RUN HSE vs Vpp fcpy 16 MHz peripheral Ola d a Bom ete imn 56 Typ IDD RUN HSE vs feru VDD 5 0 V peripheral et d BEE a ed Yun eis 56 Typ IDD RUN HSI vs Vpp feru 16 MHz peripheral EE eer TANG ae a E 57 Typ IDD WFNHSE vs Vpp fcPU 16 MHz peripheral TON eoe SERRE 57 Typ IDD WFDHSE vs feru Vpp 5 0 V peripheral Olarra a AA 57 Typ DD WFI HSI VS Vpp feru 16 MHz peripheral Elf Liv ae E 57 HSE external clock source 58 HSE oscillator circuit diagram 0 eee 59 Typical HSI frequency vs Ven 60 Typical LSI freque
45. Document revision history continued Date 31 Jan 2011 Revision Changes Modified references to reference manual and Flash programming manual in the whole document Added reference to AEC Q100 standard on cover page Renamed timer types as follows Auto reload timer to general purpose timer Multipurpose timer to advanced control timer System timer to basic timer Introduced concept of medium density Flash program memory Updated timer names in Figure STM8A block diagram Added TMU brief description in Section Flash program and data EEPROM and updated TMU_MAXATT description in Table Option byte description Updated clock sources in clock controller features Changed 16MHZTRIMO to HSITRIM bit in Section User trimming Added Table Peripheral clock gating bits Updated Section Low power operating modes Added calibration using TIM3 in Section Auto wakeup counter Added Table ADC naming and Table Communication peripheral naming correspondence Added Note 7 related AIN12 pin in Section Analog to digital converter ADC and Table STM8AF61xx 62xx 32 Kbyte microcontroller pin description Updated SPI data rate to 10 Mbit s or fyaster 2 in Section Serial peripheral interface SPI Added reset state in Table Legend abbreviation Table STM8AF61xx 62xx 32 Kbyte microcontroller pin description added Note 7 related to PD1 SWIM modified Note 6 corrected wpu input for PE1 and PE2 and re
46. FFE PC7 SPI_MISO PC6 SPI MOSI PC5 SPI SCK PC4 HS TIM1_CH4 PC3 HS TIM1_CH3 PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 PE5 SPI NSS 1 HS high sink capability DoclD14952 Rev 10 27 99 Pinouts and pin description STM8AF6246 48 66 68 Figure 4 LQFP 48 pin pinout NRST OSCIN PA1 OSCOUT PA2 Vssio 1 Vss VCAP Vpp Vppio 1 TIM2 CH3 PA3 PA4 PA5 DAG 2 HS high sink capability ng a H uo ua ma TEST Y X 5 55 9 Liliana ale O e cer2zzzzzod m lt IEECRE 990a _ SS 2 J NE SEET hooxoca oocqqso QAAAAAAA la ww KOO ONONO NDN Hp Ga NK HL 4847 4645 44 434241 40 39 38 10 360PG1 2 350 PGO 3 340 PC7 SPI MISO 4 330 PC6 SPI_MOSI 5 320 Vppio_2 6 310 Vssio_2 F 300 PC5 SPI_SCK 8 29H PC4 HS TIM1_CH4 9 287 PC3 HS TIM1 CH3 10 2717 PC2 HS TIM1 CH2 11 264 PC1 HS TIM1_CH1 12 25H PE5 SPI NSS 1314 15 16 17 18 192021 222324 00000000000 IK Q 10 t oC TO NG amp Am m cd ccm mc WW SLLLLLLLL AA k oO sf CO QN TO da 2222222222 L LILILIILIII A Yzzz FONT UIT 2994 m elele r222 FEE Table 7 Legend abbreviation 02 Fast up to 10 MHz O3 Fast slow programmability with slow as default state after reset OA Fast slow programmability with fast as default state after reset Type l input O
47. IM CSR SWIM control status register 0x00 Ly DoclD14952 Rev 10 41 99 Memory and register map STM8AF6246 48 66 68 Table 12 CPU SWIM debug module interrupt controller registers continued Address Block Register label Register name Reg SN Reserved area 15 bytes 0x00 7F90 DM BK1RE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM_BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register OxFF Ka Pens Reserved area 5 bytes 1 Accessible by debug module only 2 Product dependent value see Figure 5 Register and memory map of STM8A products Table 13 Temporary memory unprotection registers Address Block Register label Register name n 0x00 5800 TMU K1 Temporary memory unprotection key register 1 0x00 0x00 5801 TMU K2 Temporary memory unprotect
48. In addition STice offers in circuit debugging and programming of STM8A microcontrollers via the STMB8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers STice key features e Program and data trace recording up to 128 K records e Advanced breakpoints with up to 4 levels of conditions e Data breakpoints e Real time read write of all device resources during emulation e Occurrence and time profiling and code coverage analysis new features e In circuit debugging programming via SWIM protocol e 8 bit probe analyzer e 1 input and 2 output triggers e USB 2 0 high speed interface to host PC e Power supply follower managing application voltages between 1 62 to 5 5 V e Modularity that allows users to specify the components they need to meet their development requirements and adapt to future requirements e Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 DoclD14952 Rev 10 91 99 STM8 development tools STM8AF6246 48 66 68 13 2 13 2 1 13 2 2 92 99 Software tools STM8 development tools are supported
49. M3_CCR2L TIM3 capture compare register 2 low 0x00 KEE Reserved area 15 bytes 0x00 5340 TIM4 CR1 TIM4 control register 1 Ox00 0x00 5341 TIM4 IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 0x00 5343 TIM4 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto reload register OxFF bo Reserved area 185 bytes DoclD14952 Rev 10 39 99 Memory and register map STM8AF6246 48 66 68 Table 11 General hardware register map continued Address Block Register label Register name Wes 0x00 53E0 ADC _DBORH ADC data buffer register 0 high 0x00 0x00 53E1 ADC _DBORL ADC data buffer register 0 low 0x00 0x00 53E2 ADC _DB1RH ADC data buffer register 1 high 0x00 0x00 53E3 ADC _DB1RL ADC data buffer register 1 low 0x00 0x00 53E4 ADC _DB2RH ADC data buffer register 2 high 0x00 0x00 53E5 ADC _DB2RL ADC data buffer register 2 low 0x00 0x00 53E6 ADC _DB3RH ADC data buffer register 3 high 0x00 0x00 53E7 ADC DBSRL ADC data buffer register 3 low 0x00 0x00 53E8 ADC _DB4RH ADC data buffer register 4 high 0x00 0x00 53E9 ADC _DB4RL ADC data buffer register 4 low 0x00 0x00 53EA nu ADC DB5RH ADC data buffer register 5 high 0x00 0x00 53EB ADC DB5RL ADC data buffer register 5 low 0x00 0x
50. QFP48 LQFP32 VFQFPN32 7x7 mm 7x7 mm 5x5 mm Window and independent watchdog timers Communication interfaces LINUART LIN 2 2 compliant master slave modes with automatic resynchronization SPI interface up to 8 Mbit s or fuAsTER 2 C interface up to 400 Kbit s Analog to digital converter ADC 10 bit accuracy 2LSB TUE accuracy 2LSB TUE linearity ADC and up to 10 multiplexed channels with individual data buffer Analog watchdog scan and continuous sampling mode I Os Up to 38 user pins including 10 HS I Os Highly robust I O design immune against current injection Operating temperature up to 150 C Qualification conforms to AEC Q100 rev G DoclD14952 Rev 10 1 99 This is information on a product in full production www st com Contents STM8AF6246 48 66 68 Contents 1 IMPAQUCHON pira a a EE 9 2 Description y iii e cd a dE aa tard 10 3 Product lIn Up WEEK 11 4 Block GaGa RER 12 5 Product overview kaaa kk RA RT REA E 14 5 1 STMBA central processing unit CDU 14 5 1 1 Architecture and registers 14 5 1 2 Addressing ciem A eas ee WEEN EAR ede a 14 5 1 3 Instruction set sake ee kk eke eee eee bee 14 5 2 Single wire interface module SVIM and debug module DM 15 5 2 1 SWIM us geeiert ehr A A ie a ba baki be r AE 15 5 2 2 Debug module 277 seed eae dad nae a Oe dee ee REENEN ae 15 5 3 Interrupt controller 15 5 4 Flash program and data EEDROM 0
51. SE cycles with corresponding option byte values of 0xE1 OxD2 0xB4 and 0x00 OPT6 OPT7 OPT8 TMU 3 0 Enable temporary memory unprotection 0101 TMU disabled permanent ROP Any other value TMU enabled Reserved TMU KEY 1 7 0 Temporary unprotection key 0 Temporary unprotection key Must be different from 0x00 or OxFF OPT9 TMU KEY 2 7 0 Temporary unprotection key 1 Temporary unprotection key Must be different from 0x00 or OxFF OPT10 OPT11 2 TMU_KEY 3 7 0 Temporary unprotection key 2 Temporary unprotection key Must be different from 0x00 or OxFF TMU_KEY 4 7 0 Temporary unprotection key 3 Temporary unprotection key Must be different from 0x00 or OxFF DoclD14952 Rev 10 47 99 Option bytes STM8AF6246 48 66 68 Table 16 Option byte description continued Option byte no Description OPT12 TMU_KEY 5 7 0 Temporary unprotection key 4 Temporary unprotection key Must be different from 0x00 or OxFF OPT13 TMU_KEY 6 7 0 Temporary unprotection key 5 Temporary unprotection key Must be different from 0x00 or OxFF OPT14 TMU_KEY 7 7 0 Temporary unprotection key 6 Temporary unprotection key Must be different from 0x00 or OxFF OPT15 TMU_KEY 8 7 0 Temporary unprotection key 7 Temporary unprotection key Must be different from 0x00 or OxFF TMU_MAXATT 7 0 TMU access failure counter TMU_MAXATT can be initialized with the desired value only if TMU is di
52. TM8AF series 8 bit microcontrollers reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the STM8 Flash programming manual PM0051 e For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e For information on the STM6 core please refer to the STM8 CPU programming manual PM0044 DoclD14952 Rev 10 9 99 2 Description STM8AF6246 48 66 68 2 Description The STM8AF6246 STM8AF6248 STM8AF6266 and STM8AF6268 automotive 8 bit microcontrollers offer from 16 to 32 Kbyte of Flash program memory and integrated true data EEPROM They are referred to as medium density STM8A devices in STM8S series and STMB8AF series 8 bit microcontrollers reference manual RM0016 All devices of the STM8A product line provide the following benefits reduced system cost performance and robustness short development cycles and product longevity The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write erase cycles and a high system integration level with internal clock oscillators watchdog and brown out reset Device performance is ensured by a clock frequency of up to 16 MHz CPU and enhanced characteristics which include robust I O independent watchdogs with a separate clock source and a clock security system Short development cycles
53. Two advanced breakpoints and 23 predefined breakpoint configurations Interrupt controller e Nested interrupts with three software priority levels e 21 interrupt vectors with hardware priority e Five vectors for external interrupts up to 34 depending on the package e Trap and reset interrupts Flash program and data EEPROM e 16 Kbyte to 32 Kbyte of medium density single voltage program Flash memory e Up to 1 Kbyte true not emulated data EEPROM e Read while write writing in the data memory is possible while executing code in the Flash program memory The whole Flash program memory and data EEPROM are factory programmed with 0x00 Architecture e The memory is organized in blocks of 128 bytes each e Read granularity 1 word 4 bytes e Write erase granularity 1 word 4 bytes or 1 block 128 bytes in parallel e Writing erasing word and block management is handled automatically by the memory interface DoclD14952 Rev 10 15 99 Product overview STM8AF6246 48 66 68 5 4 2 5 4 3 16 99 Write protection WP Write protection in application mode is intended to avoid unintentional overwriting of the memory The write protection can be removed temporarily by executing a specific sequence in the user software Protection of user boot code UBC If the user chooses to update the Flash program memory using a specific boot code to perform in application programming IAP this boot code needs to be protected against
54. U Data input setup time tu s Slave mode 5 tren Master mode 7 UI Data input hold time ns tn si Slave mode 10 tasoj V Data output access time Slave mode 3 MASTER tasso YO Data output disable time Slave mode 25 Von lt 4 5 V 75 tuso Data output valid time slave mode 2R after enable edge Vpp 4 5 V to 5 5 V z 53 two Data output valid time Master mode after enable edge 30 t 3 Slave mode after enable edge 31 NSO Data output hold time tr mo Master mode after enable edge 12 B 1 fsck lt MASTER 2 2 The pad has to be configured accordingly fast mode Ly DoclD14952 Rev 10 69 99 Electrical characteristics STM8AF6246 48 66 68 3 Values based on design simulation and or characterization results and not tested in production 4 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 5 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z Figure 37 SPI timing diagram where slave mode and CPHA 0 NSS input l tSU NSS 1g yl te sck T th NSS Ap l 5 CPHA 0 1 tw SCKH 1 n i d i x i Ke all 1 CPHA 0 y tw SCKL T 1 m I I 1 1 1 i I tv so th So lap mm tr SCK tdis SO a SO tf SCk MISO Ces MSB OUT BITE Our SJ OUT OUTPUT s MsBOUT tsu SI gt MOSI WW NEUE a MSB IN i BIT1 IN usw X
55. UOUU boodbooda K 9 70 y 5V FP V2 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 50 LOFP32 marking example package top view Product identification XXXXXX EC CT II Date cod Standard ST logo ate coce Revision code Pin 1 identifier MS37789V1 DoclD14952 Rev 10 87 99 Package information STM8AF6246 48 66 68 11 4 11 4 1 11 4 2 88 99 Thermal characteristics In case the maximum chip junction temperature T max specified in Table 21 General operating conditions on page 52 is exceeded the functionality of the device cannot be guaranteed T russ IN degrees Celsius may be calculated using the following equation TJmax Tamax PDmax X Oya Where Tamax is the maximum ambient temperature in C jpis the package junction to ambient thermal resistance in C W Ppma is the sum of Pintmax and Pjjomax PDmax Pintmax Promax Pintmax is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pyomax represents the maximum power dissipation on output pins Where Pij0max Voi loi 2 Vpp Vou lon taking into account the actual Volle and Vop lop of the I Os at low and high level in the application Table 49 Thermal characteristics Symbol Parameter Value Unit
56. Wes 0x005408 ADCLTRL ADClowthresholdregisterlow 0x00 0x00 540C ADC _AWSRH ADC watchdog status register high 0x00 0x00 540D ADC ADC_AWSRL ADC watchdog status register low 0x00 0x00 540E ADC _AWCRH ADC watchdog control register high 0x00 0x00 540F ADC _AWCRL ADC watchdog control register low 0x00 yaong EE Reserved area 16 bytes 1 Depends on the previous reset source 2 Write only register Table 12 CPU SWIM debug module interrupt controller registers Address Block Register label Register name eed 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x80 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x172 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CC Condition code register 0x28 a i Reserved area 85 bytes 0x00 7F60 CPU CFG GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ge ITC_SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 ITC SPR5 Interrupt software priority register 5 OxFF Ox00 7F75 ITC_SPR6 Interrupt software priority register 6 OxFF paa i Reserved area 4 bytes 0x00 7F80 SWIM SW
57. ackage information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark VFQFPN32 package information Figure 42 VFQFPN32 32 pin 5x5 mm 0 5 mm pitch very thin profile fine pitch quad flat package outline Seating plane Bottom view 42 ME AMKOR V1 1 Drawing is not to scale 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Package information 2 Table 46 VFQFPN32 32 pin 5x5 mm 0 5 mm pitch very thin profile fine pitch quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 800 0 900 1 000 0 0315 0 0354 0 0394 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 A3 0 200 0 0079 b 0 180 0 250 0 300 0 0071 0 0098 0 0118 D 4 850 5 000 5 150 0 1909 0 1969 0 2028 D2 var A 2 900 3 100 3 200 0 1142 0 1220 0 1260 D2 var B 3 500 3 600 3 700 0 1378 0 1417 0 1457 E 4 850 5 000 5 150 0 1909 0 1969 0 2028 E2 var A 2 900 3 100 3 200 0 1142 0 1220 0 1260 E2 var B 3 500 3 600 3 700 0 1378 0 1417 0 1457 e 0 500 0 0197 L 0 300 0 400 0 500 0 0118 0 0157 0 0197 ddd 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD14952 Re
58. ator accuracy 40 C lt Ta lt 150 C factory calibrated 3 0V lt Vpp lt 5 5V 250 252 40 C x Tas 125 C HSI oscillator wakeu tsu HSI time P 26 us 1 Depending on option byte setting OPT3 and NOPT3 2 These values are guaranteed for STM8AF62x6ITx order codes only 3 Guaranteed by characterization not tested in production Figure 18 Typical HSI frequency vs Vpp 3 40 C 2 AH 25 C 85 C 1 125 C E 1 2 3 1 y 2 5 3 3 5 4 4 5 5 5 5 6 Vo V 0 HSI frequency variation Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ta Table 31 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit Ia Frequency 112 128 144 kHz tsutsi LSI oscillator wakeup time E 7 us 1 Data based on characterization results not tested in production 2 60 99 DoclD14952 Rev 10 STM8AF6246 48 66 68 Electrical characteristics 2 Figure 19 Typical LSI frequency vs Vpp LSI frequency variation 3 IT 2 1 0 1 E 25 C Va 2 3 IL O 2 5 3 3 5 4 4 5 Von V 5 5 5 DoclD14952 Rev 10 61 99 Electrical characteristics STM8AF6246 48 66 68 10 3 5 Memory characteristics Flash program memory data
59. by a complete free software package from STMicroelectronics that includes ST visual develop STVD IDE and the ST visual programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 STM8 toolset The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com This package includes ST visual develop Full featured integrated development environment from STMicroelectronics featuring e Seamless integration of C and ASM toolsets e Full featured debugger e Project management e Syntax highlighting editor e Integrated programming interface e Support of advanced emulation features for STice such as code profiling and coverage ST visual programmer STVP Easy to use unlimited graphical interface allowing read write and verification of the STM8A microcontroller Flash memory STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of the application directly from an easy to use graphical interface Available toolchains include C compiler for STM8 All compilers are available in free version with a limited code size depending on the compiler For more inf
60. ce manual RM0016 section on Flash EEPROM write protection for more details OPT2 AFR7 Alternate function remapping option 7 0 Port D4 alternate function TIM2 CH1 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 Port B5 alternate function AIN5 port B4 alternate function AIN4 1 Port B5 alternate function 12C_SDA port B4 alternate function 12C_SCL AFR5 Alternate function remapping option 5 0 Port B3 alternate function AIN3 port B2 alternate function AIN2 port B1 alternate function AIN1 port BO alternate function AINO 1 Port B3 alternate function TIM1 ETR port B2 alternate function TIM1 CHS3N port B1 alternate function TIM1 CH2N port BO alternate function TIM1_CH1N AFR4 Alternate function remapping option 4 Reserved bit must be kept at O AFR3 Alternate function remapping option 3 0 Port DO alternate function TIM3 CH2 1 Port DO alternate function TIM1 BKIN AFR2 Alternate function remapping option 2 0 Port DO alternate function TIM3_CH2 1 Port DO alternate function CLK_CCO Note AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0 Port A3 alternate function TIM2 CH3 port D2 alternate function TIM3 CH1 1 Port A3 alternate function TIM3 CH1 port D2 alternate function TIM2 CH3 AFRO Alternate function remapping option 0 0 Port D3 alternate function TIM2_CH2 1 Port D3 alt
61. ch very thin profile fine pitch quad flat package recommended footprint 80 VFQFPN32 marking example package top view 81 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline 82 LQFP48 48 pin 7 x 7 mm low profile quad flat package DoclD14952 Rev 10 7 99 List of figures STM8AF6246 48 66 68 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 8 99 recommended footprint 84 LQFP48 marking example package top view 84 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline 85 LQFP32 32 pin 7 x 7 mm low profile quad flat package recommended footprint 87 LQFP32 marking example package top view 87 STM8AF6246 48 66 68 ordering information scheme 2 cc 90 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Introduction 1 Introduction This datasheet refers to the STM8AF6246 STM8AF6248 STM8AF6266 and STM8AF6268 products with 16 to 32 Kbyte of Flash program memory In the order code the letter F refers to product versions with data EEPROM and H refers to product versions without data EEPROM The identifiers F and H do not coexist ina given order code The datasheet contains the description of family features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8A microcontroller memory registers and peripherals please refer to STM8S series and S
62. characteristics STM8AF6246 48 66 68 Figure 16 HSE external clock source External clock source JUUL MS36489V1 HSE crystal ceramic resonator oscillator The HSE clock can be supplied using a crystal ceramic resonator oscillator of up to 16 MHZ All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 29 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit Rp Feedback resistor 220 kQ C 4 C 2 Recommended load capacitance 20 pF 9m Oscillator transconductance 5 z mA V 2 Vpp is _ tsu Hse Startup time stabilized 2 8 ms 1 The oscillator needs two load capacitors C 4 and C to act as load for the crystal The total load capacitance Cjoag is Cy 1 C 2 C 4 C 2 If C 4 Cj 2 Deeg CL 2 Some oscillators have built in load capacitors C 4 and C 2 This value is the startup time measured from the moment it is enabled by software until a stabilized 16 MHz oscillation is reached lt can vary with the crystal type that is used 58 99 DoclD14952 Rev 10 2
63. ck diagram Figure 1 STM8AF6246 48 66 68 block diagram Reset block Mi XTAL 1 16 Kox Clock controller Reset Reset lt gt Wl _ RC int 16 MHz Detector POR BOR lg RC int 128 kHz DAMA Clock to peripherals and core lt p Window WDG STMBA core Independent WDG Single wire debug interface TY Debug SWIM lt gt ques Up to 32 Kbyte program Flash Master slave 4 y automatic lt LINUART KO Up to 1 Kbyte resynchronization gt data EEPROM s 2 Kbyte RAM lt Boot ROM Address and data bus 400 Kbit s K GC gt GE advanced control lt gt 10 Mbit s SPI timer TIM1 Up to CU 16 bit general purpose lt gt 9 CAPCOM 16 channels pts 10 bit ADC lt gt timers TIM2 TIM3 channels AWU timer gt gt 8 bit basic timer lt gt TIM4 MS37793V1 12 99 DocID14952 Rev 10 Ly STM8AF6246 48 66 68 Block diagram 2 1 Legend ADC Analog to digital converter beCAN Controller area network BOR Brownout reset PC Inter integrated circuit multimaster interface IWDG Independent window watchdog LINUART Local interconnect network universal asynchronous receiver transmitter POR Power on reset SPI Serial peripheral interface SWIM Single wire interface
64. cling is performed on four bytes even when a write erase operation addresses a single byte 2 More information on the relationship between data retention time and number of write erase cycles is available in a separate technical document 3 Retention time for 256B of data memory after up to 1000 cycles at 125 C 62 99 DoclD14952 Rev 10 2 STM8AF6246 48 66 68 Electrical characteristics 10 3 6 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 35 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Vu Input low level voltage 0 3 V E 0 3 x Vpp Vu Input high level voltage T 0 7 x Vpp Vpp 0 3 V 0 1x V Hysteresis hys y Mob Standard 1 0 Vpp 5 V Geer Vpp 0 5 V Vou Output high level voltage Standard 1 0 Vpp 3 V Van 0 4 V 1 1 5 mA DD V High sink and true open drain 1 0 Vpp 5 V 0 5 8 mA Vo _ Output low level voltage Standard 1 0 Vpp 5 V 7 0 6 153 mA Standard 1 0 Vpp 3 V 04 1 1 5 mA Rpu Pull up resistor Vpp 5 V Vin Vss 35 50 65 kQ od I Os 35 Load 50 pF Standard and high sink I Os 1252 a Rise and fall time Load 50 pF de RF 10 90 Fast I Os
65. compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1 TIM1 CCR3L TIM1 capture compare register 3 low Ox00 0x00 526B TIM1_CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 ee Reserved area 147 bytes 0x00 5300 TIM2 CR1 TIM2 control register 1 0x00 0x00 5301 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2 SR1 TIM2 status register 1 0x00 0x00 5303 TIM2 SR2 TIM2 status register 2 0x00 0x00 5304 TIM2 EGR TIM2 event generation register 0x00 0x00 5305 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 5306 TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 5307 TIM2 CCMR3 TIM2 capture compare mode register 3 0x00 0x00 5308 TIM2 CCER1 TIM2 SE enable register 0x00 0x00 5309 ae TIM2_CCER2 TIM2 SEH enable register 0x00 0x00 530A TIM2_CNTRH TIM2 counter high 0x00 0x00 530B TIM2_CNTRL TIM2 counter low 0x00 00 530COx TIM2 PSCR TIM2 prescaler register 0x00 0x00 530D TIM2 ARRH TIM2 auto reload register high OxFF 0x00 530E TIM2 ARRL TIM2 auto reload register low OxFF 0x00 530F TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5310 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5311 TIM2 CCR2H TIM
66. component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 42 EMS data Symbol Parameter Conditions Level class Vpp 3 3 V Taz 25 C Voltage limits to be applied on any I O pin VFESD to induce a functional disturbance fmaster 16 MHz HSI clock 3 8 Conforms to IEC 1000 4 2 Fast transient voltage burst limits to be Vpp 3 3 V Taz 25 C Verte applied through 100 pF on Vpp and Vss fyasster 16 MHz HSI clock 4 A pins to induce a fu
67. cy for Vppa 5 V Symbol Parameter Conditions Typ Max E Total unadjusted error 1 4 3 lEol Offset error 0 8 3 lEc _ Gain error fApc 2 MHz 0 1 2 Epl Differential linearity error 0 9 1 ELI Integral linearity error 0 7 1 5 E Total unadjusted error 4 9 4 40 lEol Offset error 2 1 34 40 Ec Gain error fapc 4 MHz 0 64 3 4 Epl Differential linearity error 1 54 24 EL Integral linearity error 1 20 1 50 Unit LSB Max value is based on characterization not tested in production liNj piN and Zlinypiny in Section 10 3 6 does not affect the ADC accuracy TUE 2LSB can be reached on specific sales types on the whole temperature range Target values Figure 41 ADC accuracy characteristics ADC accuracy vs injection current Any positive or negative injection current within the limits specified for A 1023 Len Ee 1022 4 iiss sioa 1021 J IDEAL 1024 gt ARA we Ce Er Lo Ls 7 a4 9 ae 6 a 54 H Y 41 2 1 P EL al EE Md 1 Y V Y Ep 27 ps gt 1J A 1 LSBipgaL H HA 01 12 3 4 5 6 7 1021102210231024 Vssa DDA 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line ET Total unadjusted error Maximum deviation between the actual and the ideal transfer curves Eo Offset error Deviation b
68. d DoclD14952 Rev 10 19 99 Product overview STM8AF6246 48 66 68 5 6 5 7 5 7 1 20 99 Low power operating modes For efficient power management the application can be put in one of four different low power modes Users can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in Active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as Active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset In all modes the CPU and peripherals remain permanently powered on the system clock is applied only to selected modules The RAM content is preserved and the brown out reset circuit remai
69. data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE CR2 Port E control register 2 0x00 0x00 5019 PF ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register Oxxx 0x00 501B Port F PF DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 0x00 501E PG ODR Port G data output latch register 0x00 0x00 501F PG IDR Port G input pin value register Gill 0x00 5020 Port G PG_DDR Port G data direction register 0x00 0x00 5021 PG CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 1 Depends on the external circuitry Table 11 General hardware register map Address Block Register label Register name sees 0x00505A FLASH CR1 Fiashcontrolregistert x00 0x00 505B FLASH CR2 Flash control register 2 0x00 0x00 505C FLASH NCR2 Flash complementary control register 2 OxFF 0x00 505D Flash FLASH_FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flesh T protection OxFF 0x00 505F FLASH_IAPSR Flash in application programming 0x40 status register gaso GER Reserved area 2 bytes 0x00 5062 Flash FLASH_PUKR Flash Program memory unprotection 0x00 register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH_DUKR Data EEPROM unprotection register 0x00 an a Reserved area 59 bytes 34 99 DoclD14952 Rev 10 er STM8AF6246 48 66 68 Memory and register map 2 Tabl
70. debug module user manual UMO470 for information on SWIM programming procedures Table 15 Option bytes Option bits Factory Addr pss seet default y 7 6 5 4 3 2 1 0 setting 0x00 Read out 4800 protection OPTO ROP 7 0 0x00 ROP SH User boot OPT1 Reserved UBC 5 0 Ox00 code Ee UBC NOPT1 Reserved NUBC 5 0 OxFF 0x00 Alternate OpT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 0x00 4803 function 0x00 remapping NAFR NAFR NAFR MAER NAFR NAFR NAFR MAER 4804 AFR NOPT2 7 6 5 4 3 2 1 0 oer 0x00 16MHZ LSI IWDG WWDG WWDG 4805 Watchdog SR SES TRIMO EN HW Hw Har 000 0x00 option N16MHZ NLSI NIWDG NWWD NWWG 4806 NOTS Reseed TRIMO EN HW GHw Har HIT 0x00 EXT CKAWU PRS PRS 4807 TS OPT4 Reserved CLK SEL C1 CO 0x00 0x00 option NEXT NCKAW NPR NPR 4808 RER Resened CLK use sc1 sco OFF 0x00 OPT5 HSECNT 7 0 0x00 4809 HSE clock startup in NOPT5 NHSECNT 7 0 OxFF 44 99 DoclD14952 Rev 10 Ky STM8AF6246 48 66 68 Option bytes Table 15 Option bytes continued Option bits Factory Addr Sec ie default Penny 7 6 5 4 3 2 1 0 setting 0x00 480B OPT6 TMU 3 0 0x00 mu TMU X 480C NOPT6 NTMU 3 0 OxFF 0x00 WAIT 4800 Ee OPT7 Reserved STATE 0x00 oxo
71. e 11 General hardware register map continued Address Block Register label Register name ea 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 we EXTI CR2 External interrupt control register 2 0x00 paano paang Reserved area 17 bytes 0x00 50B3 RST RST_SR Reset status register 0xxx ye t Reserved area 12 bytes 0x00 50C0 CLK ICKR Internal clock control register 0x01 0x00 50C1 in CLK ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register OxXX 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7 ndi CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB Reserved area 1 byte 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CD zem CLK SWIMCCR SWIM clock control register poe EE DR Reserved area 3 bytes 0x00 50D1 WB WWDG CR WWDOG control register Ox7F 0x00 50D2 WWDG WR WWDR window register Ox7F pue DE Reserved area 13 bytes 0x00 50E0 IWDG KR IWDG key register 0xxxO 0x00 50E1
72. e determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6 Figure 6 Pin loading conditions STM8A PIN 50 pF MSv37796V1 DoclD14952 Rev 10 49 99 Electrical characteristics STM8AF6246 48 66 68 10 1 5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7 Figure 7 Pin input voltage STM8A PIN MSv37797V1 10 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 17 Voltage characteristics Symbol Ratings Min Max Unit Input voltage on true open drain pins PE1 PE2 Vgg 0 3 6 5 EN Input voltage on any other pin Vss 0 3 Vpp 0 3 Vppx Vppl Variations between different power pins 50 IVssx Vssl Variations between all the different ground pins 50 ini see Absolute maximum ratings Vesp Electrostatic discharge voltage electrical sensitivity on page 76
73. ected the injection current must be limited externally to the Ij pj value A positive injection is induced by Viy gt Von while a negative injection is induced by V y lt Vas For true open drain pads there is no positive injection current allowed and the corresponding Vjy maximum must always be respected Table 19 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 Tj Maximum junction temperature 160 Table 20 Operating lifetime Symbol Ratings Value Unit 40 to 125 C Grade 1 OLF Conforming to AEC Q100 rev G 40 to 150 C Grade 0 1 For detailed mission profile analysis please contact the nearest local ST Sales Office DoclD14952 Rev 10 51 99 Electrical characteristics STM8AF6246 48 66 68 10 3 Operating conditions Table 21 General operating conditions Symbol Parameter Conditions Min Max Unit fopy Internal CPU clock frequency Ta 40 C to 150 C 0 16 MHz Vpp Vppio Standard operating voltage 3 0 5 5 V Cext capacitance of external 470 3300 nF capacitor VcAp D ESR of external capacitor 5 0 3 Q at 1 MHz ESL of external capacitor 15 nH LQFP32 85 Pp Power dissipation all VFQFPN32 200 mW temperature ranges LQFP48 88 Suffix A 85 Ta Ambient temperature Suffix C 125 Suffix D 150 40 C Suffix A 90 Ty Junction temperature range Suffix C 130 Suffix D 155
74. eee eee 57 HSE oscillator characteristics 00 0000 cece ee 58 HSI oscillator characteristics 000 0c eects 59 LSI oscillator characteristics illii 60 Flash program memory data EEPROM memory 62 Flash program Memory ces ona naka hh 62 Data MEMO ir eee AE e Ss r ee RR SEN EA 62 I O static characteristics eee aaa 63 NRST pin characteristics 67 TIM 1 2 3 and 4 electrical specifications llle 69 SPI characteristics 69 e EE 72 ADC characteristics 00020 tees 73 ADC accuracy for Vppa zbN ee 74 EMS data ies ea tenu Geta EE EE agape iar teens ee E EE 75 EMI galdandi da rt h na b kalla dlu stts aa s sa I b isse E AE RR 76 ESD absolute maximum ratings llle 76 Electrical sensitivities 77 VFQFPN32 32 pin 5x5 mm 0 5 mm pitch very thin profile fine pitch quad DoclD14952 Rev 10 5 99 List of tables STM8AF6246 48 66 68 Table 47 Table 48 Table 49 Table 50 6 99 flat package mechanical data 79 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data AANEREN end du R9 a a a a a 83 LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical dat 86 Thermal characteristics 000 cece teeta 88 Document revision history 94 DoclD14952 Rev 10 Ly STM8AF6246 48 66 68 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure
75. er oxxx 0x00 5002 Port A PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB IDR Port B input pin value register Oxxx 0x00 5007 Port B PB DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register 0xxx 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register oxxx 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 DoclD14952 Rev 10 33 99 Memory and register map STM8AF6246 48 66 68 Table 10 I O port hardware register map continued Address Block Register label Register name i 0x005014 PE ODR PortEdataoutputlatchregister 0x00 0x00 5015 PE IDR Port E input pin value register oxxx 0x00 5016 Port E PE DDR Port E
76. ernate function ADC_ETR 46 99 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Option bytes Table 16 Option byte description continued Option byte no OPT3 Description HSITRIM Trimming option for 16 MHz internal RC oscillator 0 3 bit on the fly trimming compatible with devices based on the 128K silicon 1 4 bit on the fly trimming LSI EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG HW Independent watchdog 0 IWDG independent watchdog activated by software 1 IWDG independent watchdog activated by hardware WWDG_HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG_HALT Window watchdog reset on Halt 0 No reset generated on Halt if WWDG active 1 Reset generated on Halt if WWDG active OPT4 EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for AWU PRSC 1 0 AWU clock prescaler 00 Reserved 01 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNTT 7 0 HSE crystal oscillator stabilization time This configures the stabilization time to 0 5 8 128 and 2048 H
77. etween the first actual transition and the first ideal one Eg Gain error Deviation between the last ideal transition and the last actual one Ep Differential linearity error Maximum deviation between actual steps and the ideal one E Integral linearity error Maximum deviation between any actual transition and the end point correlation line DoclD14952 Rev 10 2 STM8AF6246 48 66 68 Electrical characteristics 10 3 12 2 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at
78. file quad flat package outline SEATING PLANE E Sf OTTEN 0 25 mm GAUGE PLANE 5V_ME_V2 1 Drawing is not to scale 2 DoclD14952 Rev 10 85 99 Package information STM8AF6246 48 66 68 Table 48 LAFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data 86 99 millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 Ka 0 3 5 7 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD14952 Rev 10 2 STM8AF6246 48 66 68 Package information 2 Figure 49 LQFP32 32 pin 7 x 7 mm low profile quad flat package recommended footprint 0 80 EE VIR F D00000001 4 E L 0 30 _ C A 7 30 16 0 50 9 70 C 4 7 30 C gt VUUU
79. gital power supply 8 7 Vppio 4 S WO power supply 8 PFA AINT20 9 ro X X O1 X X Port F4 Analog input 12 9 PA3 TIM2_CH3 1 O X X X O1 X X Pont A3 Timer 2 channel 3 nm 10 PA4 lO X X X O3 X X Port A4 11 PA5 lO X X X O3 X X Port A5 12 PA6 lO X X X O3 X X Port A6 13 9 VppA S Analog power supply 14 10 VssA S Analog ground 15 PB7 AIN7 1 0 O1 X Port B7 Analog input 7 16 PB6 AIN6 1 O X X X O1 X X Port B6 Analog input 6 2 17 11 PB5 AIN5 lO X xX X O1 X X Port B5 Analog input 5 PELSDA AFR6 12C_SCL 18 12 PB4 AIN4 VOIX X X O1 X X Port B4 Analog input 4 AFR6 19 13 PB3 AIN3 lO X xX X O1 X X Port B3 Analog input 3 MEER AFR5 TIM1_ 20 14 PB2 AIN2 lO X X X O1 X X Port B2 Analog input NCC3 AFR5 TIM1_ 21 15 PB1 AIN1 lO X X X O1 X X Port B1 Analog input 1 NCC2 AFR5 Ly DoclD14952 Rev 10 29 99 Pinouts and pin description STM8AF6246 48 66 68 Table 8 STM8AF6246 48 66 68 32 Kbyte microcontroller pin description 2 continued Pin number Input Output En e 25 Alternate T 2 2 29 Default alternate function after co amp Pin name Sl o 2 lt x 3r
80. harge Cgxr capacitor This inrush energy depends from Cer capacitor value For example a Cex7 of 1yuF requires Q 1 UF x 1 8V 1 8 DoclD14952 Rev 10 HC 53 99 Electrical characteristics STM8AF6246 48 66 68 10 3 1 10 3 2 54 99 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cer to the Vcap pin Cgxr is specified in Table 21 Care should be taken to limit the series inductance to less than 15 nH Figure 9 External capacitor Cer C ESL Sen E oo ESR RLeak MSv36488V1 1 Legend ESR is the equivalent series resistance and ESL is the equivalent inductance Supply current characteristics The current consumption is measured as described in Figure 6 on page 49 and Figure 7 on page 50 If not explicitly stated general conditions of temperature and voltage apply Table 23 Total current consumption in Run Wait and Slow mode General conditions for Vpp apply Ta 40 to 150 C Symbol Parameter Conditions Typ Max Unit All peripherals fcpu 16 MHz 7 4 14 Suppl clocked code T 2 1 HN executed from Flash fcpu 8 MHz 4 0 7 4 IDD RUN Geh program memory fro 4 MHz 24 442 un TOC HSE external clock GPU without resonator fopy 2 MHz 1 5 2 5 All peripherals fopy 16 MHz 3 7 5 0 Suppl clocked code _ 2 1 aad in executed from RAM fopy 8 MHz 22 3 0
81. he HSE clock is used for wakeup the internal weak pull up is disabled if the HSE clock is off internal weak pull up setting from corresponding OR bit is used By managing the OR bit correctly it must be ensured that the pad is not left floating during Halt Active halt 5 AIN12 is not selectable in ADC scan mode or with analog watchdog On this pin a pull up resistor as specified in Table 35 I O static characteristics is enabled during the reset phase of the product In the open drain output column T defines a true open drain I O P buffer week pull up and protection diode to Vpp are not implemented The PD1 pin is in input pull up during the reset phase and after reset release If this pin is configured as interrupt pin it will trigger the TLI 6 2 2 Alternate function remapping As shown in the rightmost column of Table 8 some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 9 Option bytes on page 44 When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 DoclD14952 Rev 10
82. he field of applications is extended to motor control lighting and bridge driver e 16 bit up down and up down AR auto reload counter with 16 bit fractional prescaler D Four independent CAPCOM channels configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e Trigger module which allows the interaction of TIM1 with other on chip peripherals In the present implementation it is possible to trigger the ADC upon a timer event e External trigger to change the timer behavior depending on external signals e Break input to force the timer outputs into a defined state e Three complementary outputs with adjustable dead time e interrupt sources 4 x input capture output compare 1 x overflow update 1 x break TIM2 and TIM3 16 bit general purpose timers e 16 bit auto reload up counter e 15 bit prescaler adjustable to fixed power of two ratios 1 32768 e Timers with three or two individually configurable CAPCOM channels e Interrupt sources 2 or 3 x input capture output compare 1 x overflow update 5 7 5 Basic timer The typical usage of this timer TIM4 is the generation of a clock tick Table 4 TIM4 Timer Counter Counter Prescaler Channels Inverted Repetition trigger External Break width type factor outputs counter unit trigger input 2n e 8 bit auto reload adjustable prescaler ratio to any power of two from 1 to 128 e Clock source master clock
83. ion key register 2 0x00 0x00 5802 TMU K3 Temporary memory unprotection key register 3 0x00 0x00 5803 TMU_K4 Temporary memory unprotection key register 4 0x00 0x00 5804 TMU TMU K5 Temporary memory unprotection key register 5 0x00 0x00 5805 TMU_K6 Temporary memory unprotection key register 6 0x00 0x00 5806 TMU_K7 Temporary memory unprotection key register 7 0x00 0x00 5807 TMU_K8 Temporary memory unprotection key register 8 0x00 0x00 5808 TMU_CSR Temporary memory Se control and status 0x00 42 99 DoclD14952 Rev 10 er STM8AF6246 48 66 68 Interrupt table 8 2 Interrupt table Table 14 STM8A interrupt table Priority pios Description ME an Comments Reset Reset 0x00 8000 Yes User RESET vector TRAP SW interrupt 0x00 8004 0 TLI External top level interrupt 0x00 8008 1 AWU Auto wakeup from Halt 0x00 800C Yes 2 d Main clock controller 0x00 8010 3 MISC Ext interrupt EO 0x00 8014 Yes Port A interrupts 4 MISC Ext interrupt E1 0x00 8018 Yes Port B interrupts 5 MISC Ext interrupt E2 0x00 801C Yes Port C interrupts 6 MISC Ext interrupt E3 0x00 8020 Yes Port D interrupts 7 MISC Ext interrupt E4 0x00 8024 Yes Port E interrupts 8 Reserved 9 Reserved SS 10 ISPI End of transfer 0x00 8030 Yes 11 Timer 1 a 0x00 8034 12 Timer 1 Capture compare 0x00 8038 13 Timer 2 Update overflow 0
84. k It drives the independent watchdog or the AWU wakeup timer In systems which do not need independent clock sources for the watchdog counters the 128 kHz signal can be used as the system clock This configuration has to be enabled by setting an option byte OPT3 OPT3N bit LSI_EN 16 MHz high speed external crystal oscillator HSE The external high speed crystal oscillator can be selected to deliver the main clock in normal Run mode It operates with quartz crystals and ceramic resonators e Frequency range 1 MHz to 16 MHz e Crystal oscillation mode preferred fundamental e l Os standard I O pins multiplexed with OSCIN OSCOUT External clock input An external clock signal can be applied to the OSCIN input pin of the crystal oscillator The frequency range is 0 to 16 MHz Clock security system CSS The clock security system protects against a system stall in case of an external crystal clock failure In case of a clock failure an interrupt is generated and the high speed internal clock HSI is automatically selected with a frequency of 2 MHz 16 MHz 8 Table 2 Peripheral clock gating bit assignments in CLK_PCKENR1 2 registers AAA PE PCKEN17 TIM1 PCKEN13 LINUART PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM3 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 Ic PCKEN24 Reserved PCKEN20 Reserve
85. mation previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved 2 DoclD14952 Rev 10 99 99
86. med VE NRST tipp in Table NRST pin characteristics Added recommendations concerning NRST pin level above Figure Hecommended reset pin protection and updated external capacitor value Added Raisonance compiler in Section Software tools Moved know limitations to separate errata sheet 18 Jul 2012 Updated wildcards of document part numbers Table Device summary updated the footnotes to all STM8AF61xx part numbers Section Introduction small text change in first paragraph Table STM8AF62xx product line up added P version for all order codes updated RAM Table STM8AF H61xx product line up added P version for all order codes Figure STM8A block diagram updated POR BOR and WDG updated LINUART input added legend Section Flash program and data EEPROM removed non relevant bullet points and added a sentence about the factory programmer Table Peripheral clock gating bit assignments in CLK PCKENR1 2 registers updated ADC features updated ADC input range Table Memory model for the devices covered in this datasheet updated 16 Kbyte and 8 Kbyte information Table Option bytes updated factory default setting for NOPT17 added footnote 7 Section Minimum and maximum values Ta 40 C not 40 C Table General operating conditions updated Vcap Table Total current consumption in Run Wait and Slow mode General conditions for VDD apply TA 40 to 150 C updated conditions for Ipp RuN
87. n all the supported packages e 12C master features Clock generation Start and stop generation e l C slave features Programmable 12C address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 kHz A Fast speed up to 400 kHz e Status flags Transmitter receiver mode flag End of byte transmission flag lC busy flag e Error flags Arbitration lost condition for master mode Acknowledgment failure after address data transmission Detection of misplaced start or stop condition Overrun underrun if clock stretching is disabled 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Product overview 5 9 3 2 e Interrupt Successful address data communication Error condition Wakeup from Halt e Wakeup from Halt on address detection in slave mode Universal asynchronous receiver transmitter with LIN support LINUART The devices covered by this datasheet contain one LINUART interface The interface is available on all the supported packages The LINUART is an asynchronous serial communication interface which supports extensive LIN functions tailored for LIN slave applications In LIN mode it is compliant to the LIN standards rev 1 2 to rev 2 2 Detailed feature list LIN mode Master mode e LIN break and delimiter generation e LIN break and delimiter
88. n to use these Engineering Samples to run qualification activity 3 Customer specific FASTROM code or custom device configuration This field shows SSS if the device contains a super set silicon usually equipped with bigger memory and more I Os This silicon is supposed to be replaced later by the target silicon DoclD14952 Rev 10 Ly STM8AF6246 48 66 68 STM8 development tools 13 13 1 13 1 1 2 STM8 development tools Development tools for the STM8A microcontrollers include the e Slice emulation system offering tracing and code profiling e STVD high level language debugger including assembler and visual development environment seamless integration of third party C compilers e SIVP Flash programming software In addition the STM8A comes with starter kits evaluation boards and low cost in circuit debugging programming tools Emulation and in circuit debugging tools The STMB tool line includes the STice emulation system offering a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8A application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including tracing profiling and code coverage analysis to help detect execution bottlenecks and dead code
89. named TIMn CCx and TIMn NCCx to TIMn CHx and TIMn CHXxN respectively Section Register map Replaced tables describing register maps and reset values for non volatile memory global configuration reset status clock controller interrupt controller timers communication interfaces and ADC by Table General hardware register map Added Note 1 for Px IDR registers in Table I O port hardware register map Updated register reset values for Px IDR registers Added SWIM and debug module register map 2 DoclD14952 Rev 10 95 99 Revision history STM8AF6246 48 66 68 96 99 Table 50 Document revision history continued Date 31 Jan 2011 Revision 5 continued Changes Renamed Fast Active Halt mode to Active halt mode with regulator on and Slow Active Halt mode to Active halt mode with regulator off Updated Table Total current consumption in Halt and Active halt modes General conditions for VDD apply TA 40 to 55 in particular IDD FAH and Ipp sAH renamed Ipp AH twU FAH and twu sAH renamed tyy aH and temperature condition added Removed Ippusarr from Table Typical peripheral current consumption VDD 5 0 V Updated general conditions in Section Memory characteristics Modified Tyyg maximum value in Table Flash program memory and Table Data memory Update liq ana maximum value for TA ranging from 40 to 150 C in Table I O static characteristics Added tlEP NRST and rena
90. nctional disturbance Conforms to IEC 1000 4 4 DoclD14952 Rev 10 75 99 Electrical characteristics STM8AF6246 48 66 68 76 99 Electromagnetic interference EMI Emission tests conform to the IEC 61967 2 standard for test software board layout and pin loading Table 43 EMI data Conditions Max fepu Symbol Parameter Unit m Monitored General conditions frequency band 8 16 MHz MHz Vpp 5 V 0 4 MHz to 30 MHz 15 17 Peak level Ta 25 C 30 MHz to 130 MHz 18 22 SEMI LQFP80 package ABUV conforming to IEC 130 MHz to 1 GHz 1 3 EMI level 61967 2 2 2 5 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges 3 positive then 3 negative pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 44 ESD absolute maximum ratings Maximum Symbol Ratings Conditions
91. ncy vs Von 61 Typical Vj and Vip vs Vpp four temperatures liliis 64 Typical pull up resistance Rpy vs Vpp four temperatures 64 Typical pull up current lp vs Vpp four temperatures 65 Typ Vor O Vpp 3 3 V standard porte 65 Typ Vor O Vpp 5 0 V standard porte 65 Typ Vo O Vpp 3 3 V true open drain porte 65 Typ Vo O Vpp 5 0 V true open drain porte 65 Typ Vor Vpp 3 3 V high sink porte 66 Typ Vor Vpp 5 0 V high sink porte 66 Typ Vpp Vou O Vpp 3 3 V standard porte 66 Typ Vpp Vou O Vpp 5 0 V standard porte 66 Typ Vpp Vou O Vpp 3 3 V high sink ports 0 0000 akaun 66 Typ Vpp Vou O Vpp 5 0 V high sink ports ooo 66 Typical NRST Vj and Vip vs Vpp four temperatures 67 Typical NRST pull up resistance Rpy vs Von 68 Typical NRST pull up current lpu VS VDD xs csse hm eres 68 Recommended reset pin protection 2 68 SPI timing diagram where slave mode and CPHA 0 70 SPI timing diagram where slave mode and CPHA 1 1 2212222 cece 70 SPI timing diagram master mode ees 71 Typical application with ADC 1 1sssssas saka kaka eee 73 ADC accuracy characteristics d ss a kk ha G d m tk H a a ala D md K KK RRR RRR 74 VFQFPN32 32 pin 5x5 mm 0 5 mm pitch very thin profile fine pitch quad flat package outline 78 VFQFPN32 32 pin 5x5 mm 0 5 mm pit
92. ns activated Timers Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications The watchdog timer activity is controlled by the application program or option bytes Once the watchdog is activated it cannot be disabled by the user program without going through reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application timing perfectly The application software must refresh the counter before time out and during a limited time window If the counter is refreshed outside this time window a reset is issued 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Product overview Independent watchdog timer The independent watchdog peripheral can be used to resolve malfunctions due to hardware or software failures It is clocked by the 128 kHz LSI internal RC clock source and thus stays active even in case of a CPU clock failure If the hardware watchdog feature is enabled through the device option bits the watchdog is automatically enabled at power on and generates a reset unless the key register is written by software before the counter reaches the end of count 5 7 2 Auto wakeup counter
93. o States NWAIT 480E NOPT7 Reserved STATE OxFF 0x00 A80F Reserved 0x00 4810 OPT8 TMU_KEY 1 7 0 0x00 0x00 4841 OPT9 TMU KEY 2 7 0 0x00 0x00 4812 OPT10 TMU KEY 3 7 0 0x00 0x00 4813 OPT11 TMU_KEY 4 7 0 0x00 0x00 TMU OPT12 TMU_KEY 5 7 0 0x00 4814 0x00 4815 OPT13 TMU KEY 6 7 0 0x00 0x00 E 4816 OPT14 TMU_KEY 7 7 0 0x00 0x00 4817 OPT15 TMU KEY 8 7 0 0x00 Geier OPT16 TMU_MAXATT 7 0 OxC7 4818 Ox00 4819 Reserved to 487D 0x00 487E oe OPT17 BL 7 0 0x00 1 0x00 loader 487F NOPT17 NBL 7 0 OxFF 1 This option consists of two bytes that must have a complementary value in order to be valid If the option is invalid it has no effect on EMC reset 2 DoclD14952 Rev 10 45 99 Option bytes STM8AF6246 48 66 68 Table 16 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 5 0 User boot code area 0x00 No UBC no write protection 0x01 Page 0 to 1 defined as UBC memory write protected 0x02 Page 0 to 3 defined as UBC memory write protected 0x03 to Ox3F Pages 4 to 63 defined as UBC memory write protected Note Refer to STM8S series and STM8AF series 8 bit microcontrollers referen
94. odes the internal RC oscillator 16 MHz 8 is used for quick startup After a stabilization time the device switches to the clock source that was selected before Halt mode was entered e Clock security system CSS The CSS permits monitoring of external clock sources and automatic switching to the internal RC 16 MHz 8 in case of a clock failure e Configurable main clock output CCO This feature permits to output a clock signal for use by the application DoclD14952 Rev 10 17 99 Product overview STM8AF6246 48 66 68 5 5 2 18 99 16 MHz high speed internal RC oscillator HSI e Default clock after reset 2 MHz 16 MHz 8 e Fast wakeup time User trimming The register CLK_HSITRIMR with three trimming bits plus one additional bit for the sign permits frequency tuning by the application program The adjustment range covers all possible frequency variations versus supply voltage and temperature This trimming does not change the initial production setting For reason of compatibility with other devices from the STM8A family a special mode with only two trimming bits plus sign can be selected This selection is controlled with the HSITRIMO bit in the option byte registers OPT3 and NOPT3 DoclD14952 Rev 10 2 STM8AF6246 48 66 68 Product overview 5 5 3 5 5 4 5 5 5 5 5 6 2 128 kHz low speed internal RC oscillator LSI The frequency of this clock is 128 kHz and it is independent from the main cloc
95. ormation refer to www cosmic software com www raisonance com and www iar com STM8 assembler linker Free assembly toolchain included in the STM8 toolset which allows users to assemble and link the application source code 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 STM8 development tools 13 3 Programming tools During the development cycle STice provides in circuit programming of the STM8A Flash microcontroller on the user application board via the SWIM protocol Additional tools are used to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming the user STM8A For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family DoclD14952 Rev 10 93 99 2 Revision history STM8AF6246 48 66 68 14 94 99 Revision history Table 50 Document revision history Date 22 Aug 2008 Revision 1 Changes Initial release 10 Aug 2009 Document revised as the following Updated Features Updated Table Device summary Updated Section Product line up Changed Section Product overview Updated Section Pinouts and pin description Changed Section Register map Updated Section Interrupt table Updated Section Option bytes Updated Section Electrical characteristics Upda
96. ory The ROP circuit may provide a temporary access for debugging or failure analysis The temporary read access is protected by a user defined 8 byte keyword stored in the option bytes area This keyword must be entered via the SWIM interface to temporarily unlock the device If desired the temporary unlock mechanism can be permanently disabled by the user through OPT6 NOPT46 option bytes Clock controller The clock controller distributes the system clock coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock sources 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext e Reset After reset the microcontroller restarts by default with an internal 2 MHz clock 16 MHz 8 The clock source and speed can be changed by the application program as soon as the code execution starts e Safe clock switching Clock sources can be changed safely on the fly in Run mode through a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core or individual peripherals e Wakeup In case the device wakes up from low power m
97. overview of the communication peripheral Some peripheral names differ between the datasheet and STM8S series and STM8AF series 8 bit microcontrollers reference manual see Table 6 Table 6 Communication peripheral naming correspondence F Peripheral name in reference manual Peripheral name in datasheet RM0016 LINUART UART2 DoclD14952 Rev 10 23 99 Product overview STM8AF6246 48 66 68 5 9 1 5 9 2 24 99 Serial peripheral interface SPI The devices covered by this datasheet contain one SPI The SPI is available on all the supported packages e Maximum speed 10 Mbit s or fyasteR 2 both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on two lines with a possible bidirectional data line e Master or slave operation selectable by hardware or software e CRC calculation e 1 byte Tx and Rx buffer e Slave mode master mode management by hardware or software for both master and slave e Programmable clock polarity and phase e Programmable data order with MSB first or LSB first shifting e Dedicated transmission and reception flags with interrupt capability e SPI bus busy status flag e Hardware CRC feature for reliable communication CRC value can be transmitted as last byte in Tx mode CRC error checking for last received byte Inter integrated circuit PC interface The devices covered by this datasheet contain one 12C interface The interface is available o
98. sabled TMU 3 0 0101 in OPT6 option byte OPT16 When TMU is enabled any attempt to temporary remove the readout protection by using wrong key values increments the counter When the option byte value reaches 0x08 the Flash memory and data EEPROM are erased BL 7 0 Bootloader enable If this option byte is set to 0x55 complementary value 0xAA the OPT17 bootloader program is activated also in case of a programmed code memory for more details see the bootloader user manual UM0560 2 48 99 DoclD14952 Rev 10 STM8AF6246 48 66 68 Electrical characteristics 10 10 1 10 1 1 10 1 2 10 1 3 10 1 4 2 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 40 C Ta 25 C and TA Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 0 V They are given only as design guidelines and are not tested Typical ADC accuracy values ar
99. se timers nas sana a 21 M crm 22 ADC Naming AA 23 Communication peripheral naming correspondence 23 Legend abbreviation llis 28 STM8AF6246 48 66 68 32 Kbyte microcontroller pin description 29 Memory model for the devices covered in this datasheet 33 I O port hardware register Map 0 0020 s 33 General hardware register map 34 CPU SWIM debug module interrupt controller registers 41 Temporary memory unprotection registers 0 0 lille 42 STMBA interrupt table 43 Option DYOS EC T 44 Option byte description 46 Voltage characteristics 1 v 1 du du n d AA eee hs 50 Current characteristics snakka kaka asa akak aaa 51 Thermal characteristics sss ss sala aaa aaa aaa aaa 51 Operating lifetime A E EE an a a k Rr KAR rR KR ce AIST REPRE RO K R ae 51 General operating conditions 52 Operating conditions at power up power down 53 Total current consumption in Run Wait and Slow mode General conditions for Vpp apply Ta A0io1D0nC kaka 54 Total current consumption in Halt and Active halt modes General conditions for Vpp apply Ta 40 to 55 C ow lkk kakak aaa 55 Oscillator current consumption asas ses 55 Programming current consumption asa asa aa 56 Typical peripheral current consumption Vpp BUMN 56 HSE user external clock characteristics 00 cece eee
100. ted Section Package information Updated Section Ordering information Added Section STM8 development tools 22 Oct 2009 Adapted Table STM8AF61xx 62xx 32 Kbyte microcontroller pin description Added Section LIN header error when automatic resynchronization is enabled 08 Jul 2010 Updated title on cover page Added VFQFPN32 5x 5 mm package Added STM8AF62xx devices and modified cover page header to clarify the part numbers covered by the datasheets Updated Note 1 below Table Device summary Updated D temperature range to 40 to 150 C Content of Section Product overview reorganized Renamed Section Memory and register map and content merged with Register map section Renamed BL EN and NBL EN BL and NBL respectively in Table Option bytes Added Table Operating lifetime Added CEXT and Pp power dissipation in Table General operating conditions and Section VCAP external capacitor Suffix D maximum junction temperature Ty updated in Table General operating conditions Update tvDD in Table Operating conditions at power up power down Moved Table Typical peripheral current consumption VDD 5 0 Vto Section Current consumption for on chip peripherals and removed IDD CAN Updated Section Ordering information for the devices supported by the datasheet Updated Section STM8 development tools 2 DoclD14952 Rev 10 STM8AF6246 48 66 68 Revision history Table 50
101. tion 4 cece eee eee eee eee 78 11 1 VFQFPN32 package information skaka aa 78 11 2 LQFP48 package information 0 0 00 c eee eee 82 11 3 LQFP32 package information 500 c eee eee eee 85 11 4 Thermal characteristics 88 11 4 1 Reference document 88 11 4 2 Selecting the product temperature range 88 12 Ordering information 90 13 STM8 development tools 91 13 4 Emulation and in circuit debugging tools 91 13 1 1 STice key features 91 132 Software tools ee ee eee 92 13 2 1 STM8toolset 0 00 res 92 13 2 2 C and assembly toolchains 92 13 3 Programming tools 93 14 Revision history mara nf AA ae lr ln 94 4 99 DocID14952 Rev 10 Ky STM8AF6246 48 66 68 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Ly STM8AF6246 48 66 68 product ine up lille 11 Peripheral clock gating bit assignments in CLK PCKENR17 2 registers 19 Advanced control and general purpo
102. v 10 79 99 Package information STM8AF6246 48 66 68 Figure 43 VFQFPN32 32 pin 5x5 mm 0 5 mm pitch very thin profile fine pitch quad flat package recommended footprint F 5 30 k 3 80 l RAE AUUDUDO Loe ES L 5 30 L 3 80 LI om 1 DENM 0 75 O000008 3 80 1 Dimensions are expressed in millimeters 80 99 DoclD14952 Rev 10 Ly STM8AF6246 48 66 68 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 44 VFQFPN32 marking example package top view Product 4 identification X X X X X X Date code Y uu Standard ST logo Revision code Pin 1 identifier C MS37792V1 2 DoclD14952 Rev 10 81 99 Package information STM8AF6246 48 66 68 11 2 82 99 LQFP48 package information Figure 45 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE Cc A1 al 0 0 1l 7 3 eA NND GAUGE PLANE 5B ME V2 1 Drawing is not to scale DoclD14952 Rev 10 2 STM8AF6246 48 66 68 Package information 2 Table 47 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data
103. x00 803C 14 Timer2 Capture compare 0x00 8040 15 Timer 3 Update overflow 0x00 8044 16 Timer 3 Capture compare 0x00 8048 17 Reserved 18 Reserved 19 GC 12C interrupts 0x00 8054 Yes Ka 20 LINUART Tx complete error 0x00 8058 21 LINUART Receive data full reg 0x00 805C 22 ADC End of conversion 0x00 8060 23 Timer4 Update overflow 0x00 8064 34 Jeepen End OT Programming 0x00 8068 Write in not allowed area 1 All reserved and unused interrupts must be initialized with IRET for robust programming DoclD14952 Rev 10 43 99 Option bytes STM8AF6246 48 66 68 9 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Each option byte has to be stored twice for redundancy in a regular form OPTx and a complemented one NOPTx except for the ROP read out protection option byte and option bytes 8 to 16 Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 15 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP and UBC options that can only be toggled in ICP mode via SWIM Refer to the STM8 Flash programming manual PM0051 and STM8 SWIM communication protocol and

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