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1. 5 143 Device terminating an Ultra DMA data out burst 5 144 Pow t on Reset TIMIN nennen 5 145 tO 0 6 3 Response to hardware reset sess 6 4 Response to software reset rennen nennen 6 5 Response to diagnostic command eene 6 6 Sector Slip prOCessIDg 222 aas 6 10 Automatic alternating processing 6 11 Data buffer Structure eter enne eterne enne einen nen 6 12 Contents Tables xvi Table l 1 Specifications oreet i edes sieve Ve cine den 1 4 Table 1 2 Model names and product numbers eere 1 5 Table 1 3 Current and power dissipation seen 1 7 Table 1 4 Environmental specifications 1 8 Table 1 5 Acoustic noise Specification 1 9 Table 1 6 Shock and vibration 1 1 9 Table 3 1 Surface temperature measurement points and standard values 3 6 Table 3 2 Cable connector specifications 3 10 Table 5 1 Signal assignment on the interface 5 3 Table5 2 VO resisters cca eine diel ee PRG dee ee een Hele 5 7 Table 5 3 Command code and parameters sse 5 15 Table 5 4 Information to be read by IDENTIFY DEVICE comm
2. d Initial on track and read out of system information 9 Confirming spindle motor e speed Execute self calibration f Drive ready state command waiting state Load the head assembly Figure 4 3 Power on operation sequence C141 E195 02EN 4 5 Self calibration 4 5 Self calibration The disk drive occasionally performs self calibration in order to sense and calibrate mechanical external forces on the actuator and VCM torque This enables precise seek and read write operations 4 5 1 Self calibration contents 1 Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution The torque vary with the disk drive and the cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the drive measures and stores the force value of the actuator motor drive current that balances the torque for stopping head stably This includes the current offset in the power amplifier circuit and DAC system The forces are compensated by adding the measured value to the specified current value to the power amplifier This makes the stable servo control To compensate torque varying by the cylinder the disk is divided into 16 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibra
3. seen 5 106 Table 5 21 Command code and parameters esee 5 107 Table 5 22 Recommended series termination for Ultra 5 129 Table 5 23 Ultra DMA data burst timing requirements 5 133 Table 5 24 Ultra DMA sender and recipient timing requirements 5 135 C141 E195 02EN CHAPTER 1 Device Overview 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects Load Unload Function Advanced Power Management Overview and features are described in this chapter and specifications and power requirement are described The disk drive is 2 5 inch hard disk drive with built in disk controllers These disk drives use the AT bus hard disk interface protocol and are compact and reliable C141 E195 02EN 1 1 Device Overview 1 1 Features 1 1 1 Functions and performance The following features of the disk drive is described 1 Compact The disk drive has 1 disk or 2 disks of 65 mm 2 5 inches diameter and its height is 9 5 mm 0 374 inch 2 Large capacity The disk drive can record up to 40 GB formatted on one disk using the 60 63 RLL recording method and 30 recording zone technology The disk drive has a formatted capacity of 80 GB
4. Z Z Z Z uae u 2 2 ekekeke 2 2 2 2 2 2 2 9 of C141 E195 02EN 5 3 Host Commands Table 5 3 Command code and parameters 3 of 3 Command code Bit Parameters used Command name PPRPREBERIEEEE DEVICE CONFIGURATION DEVICE CONFIGURATION SET CONFIGURATION SET READ NATIVE MAX ADDRESS adie SUG SET ADDRESSEXT O 1 1 1 1 1 0 0 1 OE FEM ENERO EXER EE mmm mwm o o o omme o ext o powsoaowacxocove Notes 2518 z MEI Y v EE Y A Ea aE FR Features Register CY Cylinder Registers SC Sector Count Register DH Drive Head Register SN Sector Number Register R Retry at error 1 Without retry 0 With retry Y Necessary to set parameters Y Necessary to set parameters under the LBA mode N Not necessary to set parameters The parameter is ignored if it is set N May set parameters C141 E195 02EN 5 17 Interface D The device parameter is valid and the head parameter is ignored O Option customizing D The command is addressed to the master device but both the master device
5. 0 HOB 0 1 HOB 1 40 FLUSH CACHE EXT EAH Option customizing e Description This command executes the same operation as the Flush Cache command E7h but only LBA 1 can be specified e Error reporting conditions This command is issued with LBA 0 ST 51h ER 10h Aborted C141 E195 02EN 5 97 Interface 5 08 1F5 CH P 1F5 CH C 1F4 CL P 1F4 CL C 1F3 SN P 1F3 SN C 1F2 SC 1F2 SC C 1F1 FR P 1F1 FR C C Current P Previous 1F5 CH 1 1F5 CH 0 1F4 CL 1 1F4 CL 0 1F3 SN 1 1F3 SN 0 1F2 SC 1 1F2 SC 0 1F1 ER 0 HOB 0 1 HOB 1 XX XX XX XX XX XX XX Error information At command issuance I O registers setting contents imo i 1 1 0 1 9 1 0 me At command completion I O registers contents to be read mew C141 E195 02EN 5 3 Host Commands 41 WRITE DMA EXT 35H Option customizing e Description This command is the extended command of the WRITE DMA command The LBA specification is increased from 28 bits to 48 bits and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h Other command controls are the same as those of the WRITE DMA command At command issuance I O registers setting contents 1F7 CM 0 0 1 1 0 1 0 1 LE 1F5 CH P 1F5 CH C 1F4 CL P 1F4 CL C 1F3 SN P 1F3 SN C 1F2 SC P 1F2 SC C 1F1 FR P IF1 FR C
6. wO O gt v O vO Oa TO A wO Short Open a Master drive Figure 3 13 Jumper setting of master or slave drive Note Pins A and C should be open 3 12 b Slave drive C141 E195 02EN 3 4 Jumper Settings 3 4 4 CSEL setting Figure 3 14 shows the cable select CSEL setting Open 1 C Ou XX 2 D B Short Note The CSEL setting is not depended on setting between pins Band D Figure 3 14 CSEL setting Figure 3 15 and 3 16 show examples of cable selection using unique interface cables By connecting the CSEL of the master drive to the CSEL Line conducer of the cable and connecting it to ground further the CSEL is set to low level The drive 1s identified as a master drive At this time the CSEL of the slave drive does not have a conductor Thus since the slave drive is not connected to the CSEL conductor the CSEL is set to high level The drive is identified as a slave drive Figure 3 15 Example 1 of Cable Select C141 E195 02EN 3 13 Installation Conditions Master drive Host system Figure 3 16 Example 2 of Cable Select 3 4 5 Power Up in Standby setting When pin C is grounded the drive does not spin up at power on 3 14 C141 E195 02EN CHAPTER 4 Theory of Device Operation 41 4 2 4 3 44 4 5 4 6 4 7 Outl
7. Enables the Automatic Acoustic Management function From the SET FEATURES command From the SET MAX SET PASSWORD command Same definition as WORD 83 Enables the Power Up In Standby function Enables the Removable Media Status Notification function 2 Enables the Advanced Power Management function Same definition as WORD 83 Reserved Same definition as WORD 84 C141 E195 02EN 18 WORD 88 19 WORD 89 20 WORD 93 C141 E195 02EN Bit 15 8 Bit 7 0 5 3 Host Commands Currently used Ultra DMA transfer mode Bit 13 1 Mode 5 is selected Bit 12 1 Mode 4 is selected Bit 11 1 Mode 3 is selected Bit 10 1 Z Mode 2 is selected Bit 9 1 Mode 1 is selected Bit 8 1 Mode 0 is selected Supportable Ultra DMA transfer mode Bit 5 1 Supports the Mode 5 Bit 4 1 Supports the Mode 4 Bit 3 1 Supports the Mode 3 Bit 2 1 Supports the Mode 2 Bit 1 Supports the Mode 1 Bit 0 z Supports the Mode 0 MHT2080AH X28 80 minutes MHT2060AH X20 60 minutes 2040 X 14 40 minutes Bits 15 Bit 14 Bit 13 Bits 12 8 CBLID is a higher level than 80 conductor cable 0 CBLID is a lower level than VIL 40 conductor cable In the case of Device 1 slave drive a valid value is set Bit 12 Reserved Bit 11 Device asserts PDIAG Bit 10 9 Method for deciding the devic
8. 15 Time from DIOR assertion to read data avaiable Daarom 19 Data ener selection hord ume or DIORMDIOW i0 Time from DIOR DIOW assertion to IORDY low level 35 m Time from validity of read data to IORDY high level E use wiatnori0RDY Figure 5 9 PIO data transfer timing 5 130 C141 E195 02EN 5 6 Timing 5 6 2 Multiword data transfer Figure 5 10 shows the multiword DMA data transfer timing between the device and the host system CS0 ICs1 See nole DMARG See note DMACK IW DIOR DIOW DIOR DIOW Read PD 15 0 Write DD 15 0 o foam SN pmAwsiwenpon or pusu iner o pemumewpow 9 Figure 5 10 Multiword data transfer timing mode 2 C141 E195 02EN 5 131 Interface 5 6 3 Ultra DMA data transfer Figures 5 11 through 5 20 define the timings associated with all phases of Ultra DMA bursts Table 5 23 contains the values for the timings for each of the Ultra DMA Modes 5 6 3 1 Initiating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra Modes DMARQ device tu DMACK host te g tenv STOP 7 tzap host Eel coe HDMARDY 7777
9. 1 2 1F1 FR At command completion I O registers contents to be read 1F6 DH xx 1F5 CH IFACL xx IF QSN xx IF2 SC xx e SET MAX FREEZE LOCK FR 04h The Set MAX FREEZE LOCK command sets the device to SET MAX Frozen state After the device made a transition to the Set Max Freeze Lock state the following SET MAX commands are rejected then the device returns command aborted SET ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK If the Device is in the SET MAX UNLOCK state with the SET MAX FREEZE LOCK command then the device returns command aborted The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed C141 E195 02EN 5 53 Interface At command issuance I O registers setting contents 1F74 CM 1 1 1 1 0 0 1 1F5 CH 1F4 CL XX 1F2 SC 1F1 FR At command completion I O registers contents to be read 1F6 DH 1 5 1F4 CL xx 1F3 SN IF2 SC xx 17 READ NATIVE MAX ADDRESS 8 This command posts the maximum address intrinsic to the device which can be set by the SET MAX ADDRESS command Upon receipt of this command the device sets the BSY bit and indicates the maximum address in the DH CH CL and SN registers Then it clears BSY and gene
10. 7 8 9 10 11 The host shall keep DMACK in the negated state before an Ultra burst is initiated The device shall assert DMARQ to initiate an Ultra DMA burst Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP The host shall assert HSTROBE The host shall negate CSO CS1 DA2 DAI and DAO The host shall keep CSO CS1 DA2 DAI and DAO negated until after negating DMACK at the end of the burst Steps 3 4 and 5 shall have occurred at least tack before the host asserts DMACK The host shall keep DMACK asserted until the end of an Ultra DMA burst The device may negate DDMARDY tzionpy after the host has asserted DMACK Once the device has negated DDMARDY the device shall not release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst The host shall negate STOP within tgyy after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE The device shall assert DDMARDY within t after the host has negated STOP After asserting DMARQ and DDMARDY the device shall not negate either signal until after the first negation of HSTROBE by the host The host shall drive the first word of the data transfer onto DD 15 0 This step may occur any time during Ultra DMA burst initiation To transfer the first word of data the host shall negate HSTROBE no sooner than t after the de
11. Device Overview 3 A negative voltage like the bottom figure isn t to occur at 5 V when power is turned off and a thing with no ringing Permissible level 0 2 V Voltage V 0 100 200 300 400 500 600 700 800 Time ms Figure 1 1 Negative voltage at 5 V when power is turned off 1 6 C141 E195 02EN 1 3 Power Requirements 4 Current Requirements and Power Dissipation Table 1 3 lists the current and power dissipation typical Table 1 3 Current and power dissipation Typical Power 3 Energy Efficiency 4 MHT2080AH CA06377 B048 rank E 0 011W GB MHT2060AH CA06377 B046 rank E 0 014 W GB MHT2040AH CA06377 B034 rank E 0 021W GB MHT2040AH CA06377 B024 rank D 0 021 W GB Current at starting spindle motor 2 Current and power level when the operation command that accompanies a transfer of 63 sectors is executed 3 times in 100 ms 3 Power requirements reflect nominal values for 5 V power 4 Energy efficiency based on the Law concerning the Rational Use of Energy indicates the value obtained by dividing power consumption by the storage capacity Japan only 5 The seek average current is specified based on three operations per 100 msec 5 Current fluctuation Typ at 5 V when power is turned on C141 E195 02EN 1 7 Device Overview Current A 08 04 Figure 1 2 Current fluctuation at
12. Ending LBA OOh 00h Starting LBA Q0h 00h Test Span 3 Ending LBA OOh 00h Starting LBA 00h 00h Test Span 4 Ending LBA QOh 00h Test Span 5 5 Vender Unique 00h Test Span Selective self test log provides for the definition of up to five test spans If the starting and ending LBA values for a test span are both zero a test span is not defined and not tested Current LBA under test As the self test progress the device shall modify this value to contain the LBA currently being tested Current Span under test As the self test progress the device shall modify this value to contain the test span number currently being tested Feature Flags Interface Table 5 14 Selective self test feature flags o When set to one off line scan after selective test is pending When set to one off line scan after selective test is active Bit shall be written by the host and returned unmodified by the device Bit 3 4 shall be written as zeros by the host and the device shall modify them as the test progress e Selective Self test pending time min The selective self test pending time is the time in minutes from power on to the resumption of the off line testing if the pending bit is set 30 SECURITY DISABLE PASSWORD F6h This command invalidates the user password already set and releases the lock function The host transfers the 512 byte data shown in Table 5 15 to the device The device c
13. If the failure prediction function is enabled the device collects and updates data on specific items The values of items whose data is collected and updated by the device in order to predict device failures are hereinafter referred to as attribute values C141 E195 02EN 5 67 Interface Table 5 7 Features Register values subcommands and functions 1 of 3 Features Resister Function X DO SMART READ DATA A device that received this subcommand asserts the BSY bit and saves all the updated attribute values The device then clears the BSY bit and transfers 512 byte attribute value information to the host For information about the format of the attribute value information see Table 5 8 X DI SMART Read Attribute Thresholds This subcommand is used to transfer 512 byte insurance failure threshold value data to the host For information about the format of the insurance failure threshold value data see Table 5 9 XD SMART Enable Disable Attribute AutoSave Enables by setting the SC register to a value other than 00h or disables by setting the SC register to 00h a function that automatically saves device attribute values automatic attribute save function This setting is held regardless of whether the device is turned on or off If the automatic attribute save function is enabled and more than 15 minutes has elapsed since the last time that attributes were saved then the attributes are saved However if the automati
14. Operating 5 to 500 Hz 9 8m s 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s 0 peak 5G 0 peak Non operating no damage Shock half sine pulse Operating 2207 m s 0 peak 225G 0 peak 2ms duration without non recovered errors 8820 m s 0 peak 900G 0 peak lms duration Non operating 1176 m s 0 peak 120G 0 peak 11ms duration no damage C141 E195 02EN 1 9 Device Overview 1 7 Reliability 1 Mean time between failures MTBF Conditions of 300 000 h H Power on time 250H month or less 3000H years or less Operating time 20 or less of power on time Environment 5 to 55 C 8 to 90 But humidity bulb temperature 29 or less MTBF is defined as follows Total operation time in all fields MTBF H number of device failure in all fields 1 Disk drive defects refers to defects that involve repair readjustment replacement Disk drive defects do not include failures caused by external factors such as damage caused by handling inappropriate operating environments defects in the power supply host system or interface cable 2 Mean time to repair MTTR The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 W
15. nennen 3 4 Location ot breather iui eR oe RE 3 5 Surface temperature measurement points esee 3 6 3 7 Handling Cautions eiue eee esed tne eda 3 8 Connector locations et egit ete uenti 3 9 Cable cornn ctions ipee tete etie 3 10 Power supply connector pins 3 11 Jumper location nr e Ree e eren ec ie e Ra 3 11 Factory default setting i a nennen 3 12 Jumper setting of master or slave drive sss 3 12 CSEL Settings uiuere eed ee etie ee ies 3 13 Example 1 of Cable Select sse 3 13 Example 2 of Cable Select essere 3 14 Power Supply Configuration esee 4 4 Circuit Configuration nennen nennen nennen 4 5 Power on operation sequence eee 4 6 Read write circuit block diagram eere 4 9 Frequency characteristic of programmable filter 4 10 Block diagram of servo control circuit sees 4 12 Physical sector servo configuration on disk surface 4 15 Seryo frame Tormat tte e nee deeds 4 16 Interface signals he tee td ee Ree edet eee 5 2 Execution example of READ MULTIPLE command 5 21 Read Sector s command protocol sees 5 110 C141 E195 02EN
16. ATA ATAPI 6 supported 1 ATA ATAPI 5 supported 1 ATA ATAPIA supported 1 ATA 3 supported 1 ATA 2 supported Undefined Undefined Supports the NOP command Supports the READ BUFFER command 2 Supports the WRITE BUFFER command Undefined 2 Supports the Host Protected Area feature set Supports the DEVICE RESET command 2 Supports the SERVICE interrupt 2 Supports the release interrupt Supports the read cache function Supports the write cache function Supports the PACKET command feature set 2 Supports the power management feature set 2 Supports the Removable Media feature set 2 Supports the Security Mode feature set 2 Supports the SMART feature set Undefined C141 E195 02EN 14 WORD 84 15 WORD 85 C141 E195 02EN Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 3 Host Commands 1 FLUSH CACHE EXT command supported 1 FLUSH CACHE command supported Device Configuration Overlay feature set supported 2 48 bit LBA feature set 1 Automatic Acoustic Management feature set 2 Supports the SET MAX Security extending command Reserved 1 When the power is turned on spin is started by the SET FEATURES sub command 2 Supports the Power Up In Standby set 2 Supports the Removable Media Status Notification feature set 2
17. C Current P Previous LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 XX XX At command completion I O registers contents to be read ERST FGDH 1F5 CH 1 1F5 CH 0 1F4 CL 1 1F4 CL 0 1F3 SN 1 1F3 SN 0 1F2 SC 1 1F2 SC 0 1F1 ER 0 HOB 0 1 HOB 1 C141 E195 02EN LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 XX XX Error information 5 99 Interface 42 READ DMA EXT 25H Option customizing e Description This command is the extended command of the READ DMA command The LBA specification is increased from 28 bits to 48 bits and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h Other command controls are the same as those of the READ DMA command At command issuance I O registers setting contents 1F7 CM 0 0 1 0 0 1 0 1 LE 1F5 CH P 1 5 C 1F4 CL P 1F4 CL C 1F3 SN P 1F3 SN C 1F2 SC 1F2 SC C 1F1 FR P IF1 FR C C Current P Previous LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 XX XX At command completion I O registers contents to be read IFAT LE 1F5 CH 1 LBA 47 40 1F5 CH 0 LBA 23 16 1F4 CL 1 LBA 39 32 1F4 CL LBA 15 8 1F3 SN 1 LBA 31 24 1F3 SN 0 LBA 7
18. Duration of DASP assertion Duration of DASP assertion a s Figure 5 21 Power on Reset Timing C141 E195 02EN 5 145 This page is intentionally left blank CHAPTER 6 Operations 6 1 6 2 6 3 6 4 6 5 Device Response to the Reset Power Save Defect Processing Read Ahead Cache Write Cache C141 E195 02EN Operations 6 1 Device Response to the Reset This section describes how the PDIAG and DASP signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command 6 1 1 Response to power on 6 2 After the master device device 0 releases its own power on reset state the master device shall check a DASP signal for least 500 ms to confirm presence of a slave device device 1 The master device recognizes presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 500 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own power on reset state the slave device shall report its presence and the result of power on diagnostics to the master device as described below DASP signal Asserted within 450 ms PDIAG signal Negated within 1 ms and asserted within
19. LBA MSB 1 55 Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA 1F34 SN Start sector No LBA LSB 1F24 SC Transfer sector count 1F1 amp FR At command completion registers contents to be read 1F6 DH End head No LBA MSB 1F5y CH End cylinder No MSB LBA 1F4 CL End cylinder No LSB LBA 1F3y SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information Ifthe command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 4 READ VERIFY SECTOR S X 40 or X 41 This command operates similarly to the READ SECTOR S command except that the data is not transferred to the host system After all requested sectors are verified the device clears the BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain the cylinder head and sector number of the last sector verified If an unrecoverable error occurs the verify operation is terminated at the sector where the error occurred The command block registers contain the cylinder the head and the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred The Sector Count register indicates the number of sectors that have not been verified C141 E195 02EN 5 23 Interface
20. LSB Max LBA 1F34 SN Max sector Max LBA LSB e SET MAX SET PASSWORD FR Oth This command requests a transfer of 1 sector of data from the host and defines the contents of SET MAX password The password is retained by the device until the next power cycle The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed At command issuance I O registers setting contents CTT Tea IF2 SC IFIKFR 101 1F5 CH 1F4 CL xx 1F3 SN 5 50 C141 E195 02EN 5 3 Host Commands At command completion I O registers contents to be read 1F6 DH 1F5 CH 1F4 CL 1F3 SN 1 2 Password information Words Contents 0 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved e SET MAX LOCK FR 02h The SET MAX LOCK command sets the device into SET MAX LOCK state After this command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected And the device returns command aborted The device remains in the SET MAX LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the
21. MHT2080AH 60 GB MHT2060AH and 40 GB MHT2040AH respectively 3 High speed Transfer rate The disk drives have an internal data rate up to 55 4 MB s The disk drive supports an external data rate up to 100 MB s U DMA mode 5 4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 12 ms at read 1 1 2 Adaptability 1 Power save mode The power save mode feature for idle operation stand by and sleep modes makes The disk drives ideal for applications where power consumption is a factor 2 Wide temperature range The disk drives can be used over a wide temperature range 5 C to 55 3 Low noise and vibration In Ready status the noise of the disk drives is only 25 dBA measured at 0 3 m apart from the drive under the idle mode 4 High resistance against shock The Load Unload mechanism is highly resistant against non operation shock up to 8820 m s 900G 1 2 C141 E195 02EN 1 1 Features 1 1 3 Interface 1 Connection to ATA interface The disk drives have built in controllers compatible with the ATA interface 2 8 MB data buffer The disk drives use a 8 MB data buffer to transfer data between the host and the disk media In combination with the read ahead cache system described in item 3 and the write cache described in item 7 the buffer contributes to efficient I O
22. Read requested data Dust apace 1 DAP disk address pointer 4 The following cache valid data is for the read command that is executed next 1 __ gt LAST LBA i START 6 16 C141 E195 02EN 6 4 Read ahead Cache 6 4 3 3 Full hit In this situation all read requested data 15 stored in the data buffer Transfer of the read requested data is started from the location where hit data is stored For data that is a target of caching and remains before a full hit the data is retained when execution of the command is completed This is done so that a new read ahead operation is not performed If the full hit command is received during the read ahead operation a transfer of the read requested data starts while the read ahead operation is in progress 1 Anexample is the state shown below where the previous read command is executing sequential reading First HAP is set at the location where hit data is stored end location of previous read command HAP HAP It is reset to the hit data location for transfers 8 P LIT DAP DAP end location of the previous read command 2 The read requested data is transferred and a new read ahead operation is not performed HAP C141 E195 02EN 6 17 Operations 6 4 3 4 Partial hit In this situation a part of read requested data including the top sector is stored in the data buffer A transfer of the read requested data starts
23. amp HDC amp RDC Combo Figure 4 1 Power Supply Configuration 4 4 C141 E195 02EN 4 3 Circuit Configuration ATA Interface Data Buffer MCU amp HDC amp RDC SDRAM 881553x Marvell Flash ROM FROM SVC TLS2255 R W Pre Amp TLS26B624 Figure 4 2 Circuit Configuration CI4L EI95 02EN 45 Theory of Device Operation 4 4 Power on Sequence 4 6 Figure 4 3 describes the operation sequence of the disk drive at power on The outline is described below a After the power is turned on the disk drive executes the MPU bus test internal register read write test and work RAM read write test When the self diagnosis terminates successfully the disk drive starts the spindle motor b The disk drive executes self diagnosis data buffer read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the head assembly is loaded on the disk d The disk drive positions the heads onto the SA area and reads out the system information e The disk drive sets up a requirement for execution of self seek calibration This collects data for VCM torque and mechanical external forces applied to the actuator and updates the calibrating value f The drive becomes ready The host can issue commands Self diagnosis 1 MPU bus test Internal register write read test Work RAM write read test The spindle motor starts b Self diagnosis 2
24. processing 3 Read ahead cache system After the execution of a disk read command the disk drive automatically reads the subsequent data block and writes it to the data buffer read ahead operation This cache system enables fast data access The next disk read command would normally cause another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Master slave The disk drives can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device 5 Error correction and retry by ECC If a recoverable error occurs the disk drives themselves attempt error recovery The ECC has improved buffer error correction for correctable data errors 6 Self diagnosis The disk drives have a diagnostic function to check operation of the controller and disk drives Executing a diagnostic function of the smart command invokes self diagnosis 7 Write cache When the disk drives receive a write command the disk drives post the command completion at completion of transferring data to the data buffer completion of writing to the disk media This feature reduces the access time at writing C141 E195 02EN 1 3 Device Overview 1 2 Device Specifications 1 2 1 Specifications summary Table 1 1 shows the specifications of the disk drives Table 1 1 Specifications 1 2 eas a By
25. scone v I corny serpassword senmo __ v v v v_ Eumene It sermaxappressexr o wema ve v v ewm o ve v v v o v o v v y __ V Valid on this command E lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt ls 414364 lt lt lt lt lt n lt lt lt See the command descriptions 2 Valid only for Ultra DMA command O Option customizing 5 108 C141 E195 02EN 5 4 Command Protocol 5 4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command If BSY bit is 1 the host should wait for issuing a command until BSY bit is cleared to 0 Commands can be executed only when the DRDY bit of the Status register is 1 However the following commands can be executed even if DRDY bit is 0 EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS 5 4 1 PIO Data transferring commands from device to host The execution of the following commands involv
26. 1 is not present e device 0 posts only the results of its own self diagnosis device 0 clears the BSY bit of the Status register and generates an interrupt Table 5 6 lists the diagnostic code written in the Error register which is 8 bit code If the device 1 fails the self diagnosis the device 0 ORs X 80 with its own status and sets that code to the Error register C141 E195 02EN 5 55 Interface Table 5 6 Diagnostic code Result of diagnostic No error detected HDC diagnostic error Data buffer diagnostic error Memory diagnostic error Reading the system area is abnormal Calibration abnormal Failure of device 1 attention The device responds to this command with the result of power on diagnostic test At command issuance I O registers setting contents T T ient 1F54 CH 1F4 CL 1F3 SN 1F2 SC 1F1y FR At command completion I O registers contents to be read 1F6 DH SEXES Head No LBA MSB 1 5 1F44 CL XX 1F3y SN Oly 1F2y SC Oly 1F1yCER Diagnostic code 5 56 C141 E195 02EN 5 3 Host Commands 19 READ LONG 22 or X2 This command operates similarly to the READ SECTOR S command except that the device transfers the data in the requested sector and the ECC bytes to the host system The ECC error correction is not performed for this command This command is used for checking ECC function by combining with the WRITE L
27. 1F4 CL 1F3 SN 1F2 SC 1F1 FR 5 86 C141 E195 02EN 5 3 Host Commands At command completion I O register contents XX F5 CH 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information 34 SECURITY SET PASSWORD F1h This command enables a user password or master password to be set The host transfers the 512 byte data shown in Table 5 16 to the device The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data Table 5 17 Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted Command error Table 5 16 Contents of SECURITY SET PASSWORD data Wow Control word Bit 0 Identifier 0 Sets a user password 1 Sets a master password Bits 1 to 7 Reserved Bit 8 Security level 0 High 1 Maximum Bits 9 to 15 Reserved 1016 1 to 16 Password 32 bytes Master password version number C141 E195 02EN 5 87 Interface Table 5 17 Relationship between combination of Identifier and Security level and operation of the lock function User High The specified password is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password or the master password already set Master High The specified password is saved as a new master password The lock function is not enabled ximum The s
28. 3 4 2 Factory default setting eese nennen 3 12 3 4 3 Master drive slave drive setting 4 3 12 CSEL Setting nne ni e EHE 3 13 3 4 5 Power Up in Standby setting eee 3 14 Theory of Device Operation 4 1 AA Reo eq 4 2 4 2 Subasseimblies eere te ases eee aee eee 4 2 42 T Disk eR EE e ERI eR 4 2 4 227 site ite le eb Ee HERR HE 4 2 42 3 A CUUALOR nee epi e eee Eie tite Lb ERE eeu 4 2 ADA Mte e OE ee 4 3 43 Circuit Configuration ete tee tero tle deut teens 4 3 4 4 Poweron Sequence teer Eee teet Ed 4 6 4 5 cSelt calibrationx e eee et eto eius 4 7 4 5 1 Self calibration contents eese 4 7 4 5 2 Execution timing of self calibration 4 8 4 5 3 Command processing during self calibration sess 4 8 4 6 Read wrte Circuit die RE UR IRE LIRE edes 4 9 4 6 1 Read write preamplifier 4 9 C141 E195 02EN CHAPTER 5 C141 E195 02EN Contents 4 6 2 CITCUIU deo Re RE E cad ae Ee OR 4 9 4 6 3 Read Circuit Hd 4 10 4 645 Digital PEL Circuit oerte Pe ede rere 4 11 4T Seryo Control it i ite UH eere er iie e aee te 4 12 Servo control circuit im e eem eee eae oe 4 12 4 7 2 Data surface servo 4 14 4 7 3 Servo fr
29. 30 seconds The asserted PDIAG signal is negated 30 seconds after it is asserted if the command is not received C141 E195 02EN 6 1 Device Response to the Reset V Power on Master device 1 1 1 1 1 Power On Reset 1 Status Reg BSY bit Max 31 sec 1 gt gt Checks DASP for upto If presence of a slave device is 500 ms confirmed PDIAG is checked for up to 31 seconds Slave device Power On Reset BSY bit 4 gt 1 ms 1 i I PDIAG T NEUE 30 1 DASP 1 1 450 1 1 Figure 6 1 Response to power on Note Figure 6 1 has a assumption that the device is kept on the power off condition for more than 5 sec before the device power is turned on 6 1 2 Response to hardware reset Response to RESET hardware reset through the interface is similar to the power on reset Upon receipt of hardware reset the master device checks a DASP signal for up to 500 ms to confirm presence of a slave device The master device recognizes the presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the self diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is
30. 5 1F4 CL XX 1F3y SN XX 1F2y SC XX 1 15 Error information 5 62 C141 E195 02EN 5 3 Host Commands 25 STANDBY X 96 or X E2 Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt If the device has already spun down the spin down sequence is not implemented By using this command the APS Automatic Power Standby timer function is enabled and the timer starts the countdown when the device returns to the Waiting Host Command Mode If the device has not received any command during specified period then the device enters standby mode automatically Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as READ SECTOR s command is received the device processes the command after driving the spindle motor At command issuance I O registers setting contents mesi Ts x ove 1 5 1 4 1F3y SN XX 1F24 SC Period of timer 1Fly FR XX At command completion I O registers contents to be read Ts Ts IS 1 5 1F44 CL XX 1F3y SN XX 1F2y SC XX 1F1y ER Error information C141 E195 02EN 5 63 Interface 26 STANDBY IMMEDIATE X 94 or X E0 Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device
31. 5 V when power is turned 6 Power on off sequence The voltage detector circuits monitor 5 V The circuits do not allow a write signal if either voltage is abnormal These prevent data from being destroyed and eliminates the need to be concerned with the power on off sequence 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Temperature Operating 5 to 55 C ambient 5 C to 60 C disk enclosure surface Non operating 40 C to 65 Thermal Gradient 20 or less Humidity Operating 8 96 to 90 RH Non condensing Non operating 5 96 to 95 RH Non condensing Maximum Wet Bulb 29 Operating 40 Non operating Altitude relative to sea level Operating 300 to 3 000 m Non operating 300 to 12 000 m 1 8 C141 E195 02EN 1 5 Acoustic Noise 1 5 Acoustic Noise Table 1 5 lists the acoustic noise specification Table 1 5 Acoustic noise specification Item Specification typ Idle mode DRIVE READY 2 2 B MHT2040AH Sound Power 2 8 B MHT2080AH MHT2060AH MHT2040AH 1 Sound Pressure at 0 3m 25 dB A MHT2040AH 34 dB A MHT2080AH MHT2060AH MHT2040AH 1 1 Incase of model CA06377 B034 1 6 Shock and Vibration Table 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Vibration Swept sine 1 4 octave per minute
32. 6 7 processing defect 6 9 processing sector slip 6 10 processing track slip 6 10 R read ahead 6 12 cache 6 12 operation 6 12 READ DMA 6 13 READ MULTIPLE 6 13 READ SECTOR S 6 13 reset 5 145 6 2 reset response 6 20 reset timing 5 145 resistor pull up or pull down 5 129 response to diagnostic command 6 6 hardware reset 6 3 power on 6 2 software reset 6 5 response to diagnostic command 6 6 hardware reset 6 3 power on 6 2 software reset 6 5 S sector slip processing 6 10 sequential command 6 16 sequential hit 6 16 sleep mode 6 8 spare area 6 9 standby mode 6 8 status report in event of error 6 20 sustain Ultra DMA data in burst 5 136 out burst 5 141 sustained Ultra DMA data in burst 5 136 out burst 5 141 IN 2 T terminating device Ultra DMA data out burst 5 138 5 144 terminating host Ultra DMA data in burst 5 139 out burst 5 143 timing multiword DMA data transfer 5 131 timing PIO data transfer 5 130 timing power on 5 145 timing reset 5 145 timing requirement Ultra DMA data burst 5 133 U Ultra DMA data burst timing requirement 5 133 Ultra DMA data transfer 5 132 Ultra DMA recipient timing requirement 5 135 Ultra DMA sender timing requirement 5 135 using read segment buffer 6 15 using read segment buffer 6 15 write cache 6 19 WRITE SECTOR S EXT 34H 5 103 X X BI 5 91 C141 E195 02EN Comment Form We would appreciate your comments and suggestions regarding t
33. At command issuance I O registers setting contents IFPKCM 0 1 0 0 0 0 0 R 1F6 DH Start head No LBA MSB 1 5 Start cylinder No MSB LBA 1 4 Start cylinder No LSB LBA 1F34 SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fly FR XX At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1 5 End cylinder No MSB LBA 1F4 CL End cylinder No LSB LBA 1F3y SN End sector No LBA LSB 1F24 SC 00 1 1 1 Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 5 WRITE SECTOR S X 30 or X 317 5 24 This command writes data of sectors from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified from 1 to 256 sectors A sector count of 0 requests 256 sectors Data transfer begins at the sector specified in the Sector Number register For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 2 If the head is not on the track specified by the host the device performs an implied seek After the head reaches to the specified track the device writes the target sector If an error occurs when writing to the target sector retries are attempted irrespectively
34. C141 E195 02EN 5 143 Interface 5 6 3 11 Device terminating an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra Modes DMARQ device DMACK host tack STOP ME pre host trp tioRDvz DDMARDY device t t LI MLI tack HSTROBE gt host tcvs DD 15 0 z SZ SZ hos XOXOOOOOOOOOK gt tack DAO DA1 DA2 50 CS1 The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 20 Device terminating an Ultra DMA data out burst 5 144 C141 E195 02EN 5 6 Timing 5 6 4 Power on and reset Figure 5 21 shows power on and reset hardware and software reset timing 1 Only master device is present V Clear Reset 1 Power on RESET gt Software reset itN Reset means including Power on Reset Hardware Reset RESET and Software Reset 2 Master and slave devices are present 2 drives configuration V Clear Reset Master device tN BSY Slave device ZEE SS EHE dis nd Time from RESET negation to BSY set 400 ns He Time from RESET negation to DASP or DIAG negation 1 ms 10 Self diagnostics execution time Self diagnostics execution time 3 s Time from RESET negation to DASP assertion slave 400 ms ee 6
35. Mode at which the system operates The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode of which the device is capable Only the Ultra DMA Mode shall be selected at any given time timing requirements for a selected Ultra Mode shall be satisfied Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and 1 Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA Mode 0 An Ultra DMA capable device shall retain its previously selected Ultra DMA Mode after executing a Software reset sequence An Ultra DMA capable device shall clear any previously selected Ultra DMA Mode and revert to its default non Ultra DMA Modes after executing a Power on or hardware reset Both the host and device perform a CRC function during an Ultra DMA burst At the end of an Ultra DMA burst the host sends the its CRC data to the device The C141 E195 02EN 5 5 Ultra DMA Feature Set device compares its CRC data to the data sent from the host If the two values do not match the device reports an error in the error register at the end of the command If an error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred 5 5 2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts Each Ultra DMA burst has three mandatory phases of operation the in
36. Not Found IDNF This bit indicates an error except for bad sector uncorrectable error and SB not found Bit3 Unused Bit2 Aborted Command ABRT This bit indicates that the requested command was aborted due to a device status error e g Not Ready Write Fault or the command code was invalid 5 8 C141 E195 02EN 5 2 Logical Interface Bit1 Track 0 Not Found TKONF This bit indicates that track 0 was not found during RECALIBRATE command execution 0 Address Mark Not Found AMNF This bit indicates that the SB Not Found error occurred Diagnostic code No Error Detected X02 HDC Diagnostic Error X 03 Data Buffer Diagnostic Error X 04 Memory Diagnostic Error 05 Reading the system area is abnormal X 06 Calibration is abnormal 80 Device 1 slave device Failed Error register of the master device is valid under two devices master and slave configuration If the slave device fails the master device posts X 80 OR the diagnostic code with its own status X OI to X 06 However when the host system selects the slave device the diagnostic code of the slave device is posted 3 Features register X 1F1 The Features register provides specific feature to a command For instance it is used with SET FEATURES command to enable or disable caching 4 Sector Count register X 1F2 The Sector Count register indicates the number of sector
37. The host shall negate DMACK no sooner than ty after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY and no sooner than tpys after the host places the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DSTROBE within 7 after the host negates DMACK The host shall not negate STOP no assert HDMARDY until at least tacx after negating DMACK The host shall not assert DIOR CSO CS1 DA2 DAI or DAO until at least tacx after negating DMACK Host terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 6 and 5 6 3 2 for specific timing requirements 1 2 3 4 The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred The host shall initiate Ultra DMA burst termination by negating HDMARDY The host shall continue to negate HDMARDY until the Ultra DMA burst is terminated The device shall stop generating
38. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting 4 2 3 Actuator 4 2 The actuator consists of a voice coil motor and a head carriage The VCM moves the head carriage along the inner or outer edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head C141 E195 02EN 4 3 Circuit Configuration 4 2 4 Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating When disk drives are transported under conditions where the air pressure changes a lot filtered air is circulated in the DE The circulation filter cleans out dust and dirt from inside the DE The disk drive cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a blower on the rotating disk 4 3 Circuit Configuration Figure 4 1 shows the power supply configuration of the disk drive and Figure 4 2 shows the disk drive circuit configuration 1 Read write circuit The read write circuit consists of two circuits read write preamplifier PreAMP and read channel RDC The PreAMP consists of the write current switch
39. and the slave device execute it X Do not care 5 3 2 Command descriptions The contents of the I O registers to be necessary for issuing a command and the example indication of the I O registers at command completion are shown as following in this subsection Example READ SECTOR S At command issuance I O registers setting contents IFAKCM Cus Ti Tov 1 5 Start ome address MSB LBA At command completion I O registers contents to be read E 1F7 amp ST Status information 1 5 End ae address MSB LBA 5 18 C141 E195 02EN 5 3 Host Commands CM Command register FR Features register DH Device Head register ST Status register CH Cylinder High register ER Error register CL Cylinder Low register L LBA logical block address setting bit SN Sector Number register DV Device address bit SC Sector Count register x xx Do not no necessary to set Note l When the L bit is specified to 1 the lower 4 bits of the DH register and all bits of the CH CL and SN registers indicate the LBA bits bits of the DH register are the MSB most significant bit and bits of the SN register are the LSB least significant bit 2 At error occurrence the SC register indicates the remaining sector count of data transfer 3 In the table indicating I O registers contents in this subsection bit indication is omitted 1 READ SECTOR S X20 or X
40. at a time from the beginning C141 E195 02EN 5 3 Host Commands e Insurance failure threshold The limit of a varying attribute value The host compares the attribute values with the thresholds to identify a failure Table 5 10 Log Directory Data Format s SMART Logging Version Number of sectors of Address 01h 03 Reserved 04 Number of sectors of Address 02h 05 0B Reserved Number of sectors of Address 06h Number of sectors of Address 09h Address 80h 102 Address 81h 102 and 13 both the vnd 13F Address 9Fh format as 100 101 140 1 Reserved e SMART error logging If the device detects an unrecoverable error during execution of a command received from the host the device registers the error information in the SMART Summary Error Log see Table 5 11 and the SMART Comprehensive Error Log see Table 5 11 1 and saves the information on media The host issues the SMART Read Log Sector sub command FR register D5h SN register 1 SC register 011 and can read the SMART Summary Error Log The host issues the SMART Read Log Sector sub command FR register D5h SN register 02h SC register 33h and can read the SMART Comprehensive Error Log C141 E195 02EN 5 77 Interface Table 5 11 Data format of SMART Summary Error Log 1 sequence unit ms Power on time unit h 5C to 1C3 Error log data Format of each error log data structure is same as those of stru
41. beginning of each block or partial block The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined To obtain a valid error information the host should retry data transfer as an individual request C141 E195 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F6 DH Start head No LBA MSB 1 55 Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA 1F34 SN Start sector No LBA LSB 1F24 SC Transfer sector count 1F1 amp FR At command completion registers contents to be read 1F6 DH End head No LBA MSB 1 1 1 1 1 5 End cylinder No MSB LBA FA4 CL End cylinder No LSB LBA F34 SN End sector No LBA LSB F24 SC 00 F1 ER Error information 7 WRITE DMA X CA or X CB This command operates similarly to the WRITE SECTOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device The device posts a status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the
42. command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the error information is the same as the WRITE SECTOR S command C141 E195 02EN 5 27 Interface A host system can select the following transfer mode using the SET FEATURES command e Multiword DMA transfer mode 0 to 2 e Ultra DMA transfer mode 0 to 5 At command issuance I O registers setting contents 1F6 DH Start head No LBA MSB 1 55 Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA 1F3y SN Start sector No LBA LSB 1F24 SC Transfer sector count 1F1y FR XX At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1 5 End cylinder MSB LBA 1F4 CL End cylinder No LSB LBA IF34 SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8 WRITE VERIFY X 3C This command operates similarly to the WRITE SECTOR S command except that the device verifies each sector immediately after being written The verify operation is a read and check for data errors without data transfer Any error that is detected du
43. connected C141 E195 02EN 6 3 Operations After the slave device receives the hardware reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below DASP signal Asserted within 450 ms PDIAG signal Negated within 1 ms and asserted within 30 seconds The asserted PDIAG signal is negated 30 seconds after it is asserted if the command is not received Reset Master device Status Reg BSY bit Max 31 sec NYa A gt If presence of a slave device is Checks DASP for up to confirmed PDIAG is checked for 500 ms up to 31 seconds Slave device BSY bit pc 4 Max 1 ms 1 1 1 1 1 1 PDIAG Max 30 sec DASP Dee n I 1 1 gt Max 450 ms 1 Figure 6 2 Response to hardware reset Note Master Device does not check the DASP signal assertion for 2ms upon receipt of hardware reset 6 4 C141 E195 02EN 6 1 Device Response to the Reset 6 1 3 Response to software reset X 3F6 Reg The master device does not check the DASP signal for a software reset If a slave device is present the master device checks the PDIAG signal for up to 15 seconds to see if the slave device has completed the self diagnosis successfully After the slave device receives the software reset the slave device shall report its presence and the result of the self diagnostics to the master de
44. data signals to be considered stable at the host until some time after they are driven by the device Figure 5 12 Sustained Ultra DMA data in burst 5 136 C141 E195 02EN 5 6 Timing 5 6 3 4 Host pausing an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host STOP host HDMARDY host DSTROBE z device MIS XX XX XX XK OXXXXXXX device Notes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tgp after HDMARDY is negated 2 After negating HDMARDY the host may receive zero one two or three more data words from the device Figure 5 13 Host pausing an Ultra DMA data in burst C141 E195 02EN 5 137 Interface 5 6 3 5 Device terminating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra Modes DMARQ device mE DMACK host 75 STOP host n HDMARDY7c 71 N host lt tss tioRDvz DSTROBE device gt _ DD 15 0 me SOOO DAO DA1 DA2 77 CSQ C51 J Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 14 Device terminating an Ultra DMA data in burst 5 138 C141 E195 02EN 5 6 Timing 5 6 3 6 Host terminating an Ultra DMA data in burst 5 6 3 2 contains
45. eer eene diee e eere dee te 6 13 6 4 3 Using the read segment buffer ssssseeeeeeeeenn 6 15 GAS MisS hit iem Ret tete 6 15 6 4 3 2 Sequential toe Ec eC e 6 16 6 4 3 3 insectes deu 6 17 6 4 3 Partial nits oe tree ote eee eade 6 18 6 5 Write Cache ettet eiie ipee leet e ede 6 19 6 3 1 gt Cache operation eee eee ee adie pro ot eas 6 19 GOS S GL 1 Acronyms and Abbreviations enne nnne nnn AB 1 XC seva dccus ona dear dk RA RR RR IN 1 C141 E195 02EN xiii Contents Figures xiv Figure 1 1 Figure 1 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 5 1 Figure 5 2 Figure 5 3 Illustrations Negative voltage at 5 V when power is turned off 1 6 Current fluctuation Typ at 5 V when power is turned on 1 8 Disk drive OUterVIew iren Cedere ee teet eoe e dote ee teeta 2 2 1 drive system configuration 2 3 2 drives configuration ener nenne 2 4 DIMENSIONS Le ede eio m e Reb ies 3 2 Orientation i pe EP eee E ie ed eee 3 3 Mounting frame
46. function for automatically reading data blocks upon completion of the read command in order to read data from disk media and save data block on a data buffer If a subsequent command requests reading of the read ahead data data on the data buffer can be transferred without accessing the disk media As the result faster data access becomes possible for the host 6 4 1 DATA buffer structure 6 12 This device contains a data buffer 8 MB This buffer is divided into two areas one area is used for MPU work and the other 15 used as a read cache for another command See Figures 6 7 and 6 8 8192 KB 8388608 bytes Figure 6 7 Data buffer structure The read ahead operation is done by the following commands READ SECTOR s EXT READ MULTIPLE EXT READ DMA EXT e READ DMA QUEUED EXT e READ STREAM e READ STREAM DMA C141 E195 02EN 6 4 Read ahead Cache 6 4 2 Caching operation The caching operation is performed only when the commands listed below are received If any of the following data are stored on the data buffer the data is sent to the host system e All of the sector data that this command processes part of the sector data including the start sector that this command processes If part of the data to be processed is stored on the data buffer the remaining data is read from disk media and sent to the host system 1 Commands that are targets of caching The commands that are ta
47. number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count C141 E195 02EN 5 3 Host Commands If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled the device rejects the READ MULTIPLE command with an ABORTED COMMAND error Figure 5 2 shows an example of the execution of the READ MULTIPLE command e Block count specified by SET MULTIPLE MODE command 4 number of sectors in a block e READ MULTIPLE command specifies Number of requested sectors 9 Sector Count register 9 Command Issue Parameter v Write V Status read V Status read V Status read V V Sector 1 21314 5 6 718 9 tranferred lt gt gt Block Block block Figure 5 2 Execution example of READ MULTIPLE command At command issuance I O registers setting contents 1F6 DH Start head No LBA MSB 1 55 Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA 1F3y SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fly FR XX C141 E195 02EN 5 21 Interface At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1F54 CH End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB IF2 SC 00 1 15 Error information command is t
48. of the R bit setting The data stored in the buffer and CRC code and ECC bytes are written to the data field of the corresponding sector s Upon the completion of the command execution the command block registers contain the cylinder head and sector addresses of the last sector written C141 E195 02EN 5 3 Host Commands If an error occurs during multiple sector write operation the write operation is terminated at the sector where the error occurred Command block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred At command issuance I O registers setting contents DV Start head No LBA MSB 1F6 DH 1F5 CH 1F4 CL 1F3 SN 1 2 1 1 Start cylinder MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count XX At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1F5 CH 1F4 CL 1F3 SN 1 2 1F1 ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register C141 E195 02EN 5 25 Interface 6 WRITE MULTIPLE X CS 5 26 This command is similar to the WRITE SECTOR S com
49. system is completed reading of the disk continues until a certain amount of data is stored HAP stop i Read requested data Read ahead data tr DAP 4 The following cache valid data is for the read command that is executed next LAST LBA i START LBA gt C141 E195 02EN 6 15 Operations 6 4 3 2 Sequential Hit When the read command that is targeted at a sequential address is received after execution of the read commands is completed the read command transmits the Read requested data to the host system continuing read ahead without newly allocating the buffer for read 1 When the sequential read command is received HAP is set in the sequential address of the last read command and DAP is set at a present read position as it is HAP host address pointer 1 Read requested data 1 Cache valid data IEEE Free space fr DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system HAP host address pointer l 1 1 Cache valid data Read requested data Free space 1 DAP disk address pointer 3 When reading of read requested data is completed and transfer of the read requested data to the host system is completed the read ahead operation continues until a certain amount of data is stored HAP host address pointer c Read ahead Cache valid data
50. the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it at the end of the command A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra DMa burst in the same command If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred g ForREAD or WRITE DMA commands When a CRC error is detected it shall be reported by setting both ICRC and ABRT bit 7 and bit 2 in the Error register to one ICRC is defined as the Interface CRC Error bit The host shall respond to this error by re issuing the command h A host may send extra data words on the last Ultra DMA burst of a data out command If a device determines that all data has been transferred for a command the device shall terminate the burst A device may have already received more data words than were required for the command These extra words are used by both the host and the device to calculate the CRC but on an Ultra DMA data out burst the extra words shall be discarded by the device 5 128 C141 E195 02EN 5 5 Ultra DMA Feature Set i The CRC generator polynomial is G X X16 X12 X5 1 Note Since no bit clock is available the recommended approach for calculating CRC is to use a word clock derived from
51. the result of its CRC calculation see 5 5 5 If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than ty after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY and no sooner than tpys after the host places the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA burst for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DSTROBE within tiorpyz after the host negates DMACK The host shall neither negate STOP nor assert HDMARDY until at least tacx after the host has negated DMACK The host shall not assert DIOR CSO CS1 DA2 DAI or DAO until at least tacx after negating DMACK 5 123 Interface 5 5 4 Ultra DMA data out commands 5 5 4 1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 7 and 5 6 3 2 for specific timing requirements D 2 3 4 5
52. the values for the timings for each of the Ultra DMA Modes DMARQ device tu host tre STOP tack HDMARDY host t Tm tu MLI bue b dd DSTROBE SE device c tcvs XX DAO DA1 DA2 Cso CS1 Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 15 Host terminating an Ultra DMA data in burst C141 E195 02EN 5 139 Interface 5 6 3 7 Initiating an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra Modes DMARQ device DMACK host STOP hos 77777777777777 DDMARDY device HSTROBE host DD 15 0 7777 T D ST 1 Z XZ Xz Nz NZ NZ NZ MZ Xz XZ hy host DAO DA1 DA2 CSO0 CS1 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 16 Initiating an Ultra DMA data out burst 5 140 C141 E195 02EN 5 6 Timing 5 6 3 8 Sustained Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes HSTROBE at host tpvH tpvH tpvHic tpvHic DD 15 0 at host HSTROBE at device DD 15 0 SKK XXXXXXX_ XXXXXXX Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emph
53. then clears the BSY bit and generates an interrupt This command does not support the APS timer function At command issuance I O registers setting contents S x 1F5 CH 1F4 CL 1F34 SN 1F24 SC 1F1 FR At command completion I O registers contents to be read fs Ts Ts 1F54 CH 1F44 CL XX 1F3y SN XX 1F2y SC XX 1F1 CER Error information 5 64 C141 E195 02EN 5 3 Host Commands 27 SLEEP X 99 or X E6 This command is the only way to make the device enter the sleep mode Upon receipt of this command the device sets the BSY bit of the Status register and enters the sleep mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The only way to release the device from sleep mode is to execute a software or hardware reset At command issuance I O registers setting contents mes ipi x ove 1F54 CH 1F4 CL 1F3 4 SN 1 2 1F14 FR At command completion I O registers contents to be read Des Ts 1 5 1F44 CL XX 1F3y SN XX 1F24 SC XX 1 15 Error information C141 E195 02EN 5 65 Interface 28 CHECK POWER MODE X 98 or 5 The host c
54. to save the device attribute value data on a medium Alternative the device must issue the SMART Enable Disable Attribute AutoSave subcommand FR register D2h to use a feature which regularly save the device attribute value data to a medium The host can predict failures in the device by periodically issuing the SMART Return Status subcommand FR register 2 DAh to reference the CL and CH registers If an attribute value is below the insurance failure threshold value the device is about to fail or the device is nearing the end of its life In this case the host recommendis that the user quickly backs up the data At command issuance I O registers setting contents 1 5 Key C2h 1F44 CL Key 4Fh 1F34 SN XX 1F24 SC XX 1FI amp FR Subcommand 5 70 C141 E195 02EN 5 3 Host Commands At command completion I O registers setting contents 1 5 Key failure prediction status C2h 2Ch 1F44 CL Key failure prediction status 4Fh F4h 1F3y SN XX 1 2 1FIug ER Error information The attribute value information is 512 byte data the format of this data is shown the following Table 5 8 The host can access this data using the SMART READ DATA subcommand FR register DOh The insurance failure threshold value data is 512 byte data the format of this data is shown the following Table 5 9 The host can access this data using the SMART READ DATA subcommand FR register D1h C141
55. 0 1F2 SC 1 xx 1F2 SC 0 xx 1F1 ER Error information 0 HOB 0 1 HOB 1 5 100 C141 E195 02EN 5 3 Host Commands 43 WRITE MULTIPLE EXT 39H Option customizing e Description This command is the extended command of the WRITE MULTIPLE command The LBA specification is increased from 28 bits to 48 bits and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h Other command controls are the same as those of the WRITE MULTIPLE command At command issuance I O registers setting contents 1F7 CM 0 0 1 1 1 0 0 1 LE 1F5 CH P 1F5 CH C 1F4 CL P 1F4 CL C 1F3 SN P 1F3 SN C 1F2 SC P 1F2 SC C 1F1 FR P IF1 FR C C Current P Previous LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 XX XX At command completion I O registers contents to be read ERST FGDH 1F5 CH 1 1F5 CH 0 1F4 CL 1 1F4 CL 0 1F3 SN 1 1F3 SN 0 1F2 SC 1 1F2 SC 0 1F1 ER 0 HOB 0 1 HOB 1 C141 E195 02EN LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 XX XX Error information 5 101 Interface 44 READ MULTIPLE EXT 29H Option customizing e Description This command is the extended command of the READ MULTIPLE command The LBA specification is increased from 28 bits to 48 bits and the maximum number of sectors th
56. 1 HOB 1 5 104 LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 XX XX Error information C141 E195 02EN 5 3 Host Commands 47 DOWNLOAD MICRO CODE 92H EWC meom 1 1 6 9 acp WC ISO iru At command completion I O registers contents to be read 1F7 ST Status information wes i x fo wu oS This command rewrites the microcode of the device firmware When this command is accepted the device does beginning the data transfer of the microcode or the microcode rewriting according to Subcommand code Rewriting is also possible simultaneously with the data transfer Refer to Table 5 19 In the data transfer of Subcommand code 01h transfer by which data is divided into multiple times is possible Refer to Table 5 20 After the designation of rewriting by Subcommand code 07h reactivates in the device for the update of the rewriting microcode of the microcode C141 E195 02EN 5 105 Interface Table 5 19 Operation of DOWNLOAD MICRO CODE Host Command Movement of device pan Data transfer Microcode rewriting execution FR Reg SN SC m 8 Rewriting execution reservation execution reservation xxxxh execution reservation Excluding Olh and 07h 01h and 07h Abort n the cases Subcommand code 07h returns Abort as an error though
57. 21 This command reads data of sectors specified in the Sector Count register from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers Number of sectors can be specified from 1 to 256 sectors To specify 256 sectors reading 00 is specified For INTRQ and BSY protocols related to data transfer see Subsection 5 4 1 If the head is not on the track specified by the host the device performs an implied seek After the head reaches to the specified track the device reads the target sector If an error occurs retry reads are attempted to read the target sector before reporting an error irrespective of the R bit setting The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition Upon the completion of the command execution command block registers contain the cylinder head and sector addresses in the CHS mode or logical block address in the LBA mode of the last sector read If an unrecoverable error occurs in a sector the read operation is terminated at the sector where the error occurred Command block registers contain the cylinder the head and the sector addresses of the sector in the CHS mode or the logical block address in the LBA mode where the error occurred and remaining number of sectors of which data was not transferred C141 E195 02EN 5 19 Interface At command issuance I O registers setting co
58. 44 FCI supply cable 44 pin type 44 pin type IMPORTANT For the host interface cable use a ribbon cable A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines This is because the interface is designed for ribbon cables and not for cables carrying differential signals 3 3 3 Device connection Figure 3 9 shows how to connect the devices ATA cable Disk Drive 0 ATA cabl Host system Disk Drive 1 DC Power supply Power supply cable Figure 3 9 Cable connections 3 3 4 Power supply connector CN1 Figure 3 10 shows the pin assignment of the power supply connector CN1 C141 E195 02EN 3 4 Jumper Settings 5V RETURN Pin 43 Pin 1 5V DC Pin 41 42 viewed from connector side Figure 3 10 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 11 shows the location of the jumpers to select drive configuration and functions i 20 Switch viewed from connector side witc Figure 3 11 Jumper location C141 E195 02EN 3 11 Installation Conditions 3 4 2 Factory default setting Figure 3 12 shows the default setting position at the factory Figure 3 12 Factory default setting 3 4 3 Master drive slave drive setting Master drive disk drive 0 or slave drive disk drive 1 15 selected L Open Open
59. 777 S4 host gt tzionDv E DSTROBE device ipzrs me vos gt oo 050 ERX tack a DAO DA1 DA2 CS0 CS1 Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 11 Initiating an Ultra DMA data in burst 5 132 C141 E195 02EN 5 6 Timing 5 6 3 2 Ultra DMA data burst timing requirements Table 5 23 Ultra DMA data burst timing requirements 1 of 2 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 in ns in ns in ns in ns in ns in ns COMMENT oce CY aa 120 90 W sustained average two time Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge Two cycle time allowing for clock variations from rising edge to next rising edge or from falling edge to next falling edge of STROBE Data setup time at recipient from data valid until STROBE edge 2 5 Data hold time at recipient from STROBE edge until data may become invalid 2 5 Data valid setup time at sender from data valid until STROBE edge 3 Data valid hold time at sender from STROBE edge until data may become invalid 3 CRC word setup time at device 2 Jes word hold time device 2 En word valid setup time at host from CRC valid until DMACK negation 3 CRC word valid hold time at sender from DMACK
60. 9 Reserved Bit 8 48 bit Addressing feature set supported Bit 7 Host Protected Area feature set supported Bit 6 Automatic acoustic management supported Bit 5 1 READ WRITE DMA QUEUED commands supported Bit 4 1 Power up in Standby feature set supported Bit 3 1 Security feature set supported Bit 2 1 SMART error log supported Bit 1 1 SMART self test supported Bit 0 1 SMART feature set supported 8 254 X 0000 Reserved 255 XXxAS Integrity word Bits 15 8 contains the data structure checksum that is the two s complement of the sum of all byte in words 0 through 254 and the byte consisting of bits 7 0 of word 255 5 94 Ts When 48 bit LBA of the option customize is supported same number of LBA as WORD60 61 is displayed C141 E195 02EN 5 3 Host Commands 38 READ NATIVE MAX ADDRESS EXT 27H Option customizing e Description This command is used to assign the highest address that the device can initially set with the SET MAX ADDRESS EXT command The maximum address is displayed in the CH CL SN registers of the device control register with HOB bit 0 1 e Error reporting conditions This command is issued with LBA 0 ST 2 51h O4h Aborted command At command issuance I O registers setting contents uoo o 0 o 1 9 1 mem 1F5 CH P 1FS CH 1F4 CL P 1F4 CL C 1F3 SN P 1F3 SN 1F2 SC 1F2 SC C 1
61. A burst termination when the device stops generating STROBE edges If the device does not negate DMARQ in order to initiate ULTRA DMA burst termination the host shall negate HDMARDY and wait tgp before asserting STOP The device shall resume an Ultra DMA burst by generating a DSTROBE edge Host pausing an Ultra DMA data in burst 1 2 3 4 5 The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred The host shall pause an Ultra DMA burst by negating The device shall stop generating DSTROBE edges within of the host negating If the host negates HDMARDY within tsr after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates HDMARD YY greater than tsr after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two additional data words The additional data words a result of cable round trip delay and timing for the device The host shall resume an Ultra DMA burst by asserting HDMARDY 5 5 3 4 Terminating an Ultra data in burst a Device terminating an Ultra DMA data in burst C141 E195 02EN The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 5 and 5 6 3 2 for specific timing requirements 1 The device shall in
62. ATE command 4 HDD power supply cutting 1 11 Advanced Power Management The disk drive shifts to the three kinds of APM modes automatically under the Idle condition The APM mode can be chosen with a Sector Count register of the SET FEATURES EF command In APM Mode 1 which is the APM default mode the operation status shifts till it finally reaches Low Power Idle The disk drive complies with the three kinds of APM modes that a command from the host is required FR 05h Enable SC COh FEh Mode 0 Active Idle Low Power Idle SC 80h BFh Mode l Active Idle Low Power Idle Default SC 01h 7Fh Mode 2 Active Idle gt Low Power Idle Standby 85 Disable APM return to Default C141 E195 02EN Active Idle Low Power Idle 1 11 Advanced Power Management The head is in a position of extreme inner in disk medium VCM Lock The head is unloaded from disk VCM Unload The spindle motor rotates Standby The spindle motor stops Active Idle Low Power Idle Standby AEM Mode Lock VCM Unload Spin Off Mode 0 0 2 1 2 sec 15 min N A Mode 1 0 2 1 2 sec 10 0 40 0 sec N A Mode 2 0 2 1 2 sec 10 0 40 0 sec 10 0 40 0 sec When the maximum time that the HDD is waiting for commands has been exceeded C141 E195 02EN Mode 1 Mode 2 Mode 0 Mode shifts from Active condition to Active Idle in 0 2 1 2 and to Low Power Idle in 15 minutes M
63. C141 E195 02EN MHT2080AH MHT2060AH MHT2040AH DISK DRIVES PRODUCT MANUAL FUJITSU FOR SAFE OPERATION Handling of This Manual This manual contains important information for using this product Read thoroughly before using the product Use this product only after thoroughly reading and understanding especially the section Important Alert Items in this manual Keep this manual handy and keep it carefully FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property Use the product according to this manual IMPORTANT NOTE TO USERS READ THE ENTIRE MANUAL CAREFULLY BEFORE USING THIS PRODUCT INCORRECT USE OF THE PRODUCT MAY RESULT IN INJURY OR DAMAGE TO USERS BYSTANDERS OR PROPERTY While FUJITSU has sought to ensure the accuracy of all information in this manual FUJITSU assumes no liability to any party for any damage caused by any error or omission contained in this manual its updates or supplements whether such errors or omissions result from negligence accident or any other cause In addition FUJITSU assumes no liability with respect to the application or use of any product or system in accordance with the descriptions or instructions contained herein including any liability for incidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU
64. DRESS EXT READ NATIVE MAX ADDRESS EXT IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE SMART DISABLE OPERATION SMART ENABLE DISABLE AUTOSAVE SMART ENABLE OPERATION SMART EXECUTE OFFLINE IMMEDIATE SMART RETURN STATUS SECURITY ERASE PREPARE SECURITY FREEZE LOCK FLUSH CACHE EXT Figure 5 6 shows the protocol for the command execution without data transfer Parameter write W Command V Status read psy 1 DRDY EG INTRQ TB Figure 5 6 Protocol for the command execution without data transfer 5 114 C141 E195 02EN 5 4 Command Protocol 5 4 4 Other commands e READ MULTIPLE EXT e SLEEP e WRITE MULTIPLE EXT See the description of each command 5 4 5 DMA data transfer commands READ DMA EXT WRITE DMA EXT Starting the DMA transfer command is the same as the READ SECTOR S WRITE SECTOR S command except the point that the host initializes the DMA channel preceding the command issuance Interruption processing for DMA transfer does not issue interruptions in any intermediate sector when a multisector command is executed The following outlines the protocol C141 E195 02EN 5 115 Interface 5 116 The interrupt processing for the DMA transfer differs the following point a b c d e g The interrupt processing for the DMA transfer differs the following point The host writes any parameters to the Features Sector Count S
65. DSTROBE edges within ters of the host negating HDMARDY If the host negates HDMARDY within tsp after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates HDMARDY greater than tsr after the device has generated a DSTROBE edge then the host shall be C141 E195 02EN 5 7 8 9 10 11 12 13 14 15 16 C141 E195 02EN 5 5 Ultra DMA Feature Set prepared to receive zero one or two additional data words The additional data words a result of cable round trip delay and timing for the device The host shall assert STOP no sooner than tgp after negating HDMARDY The host shall not negate STOP again until after the Ultra DMA burst is terminated The device shall negate DMARQ within t after the host has asserted STOP The device shall not assert DMARQ again until after the Ultra DMA burst 15 terminated If DSTROBE is negated the device shall assert DSTROBE within tj after the host has asserted STOP No data shall be transferred during this assertion The host shall ignore this transition on DSTROBE DSTROBE shall remain asserted until the Ultra DMA burst is terminated The device shall release DD 15 0 no later than taz after negating DMARQ The host shall drive DD 15 0 no sooner than tz4j after the device has negated DMARQ For this step the host may first drive DD 15 0 with
66. E CONFIGURATION DOWNLOAD MICROCODE UNSUPPORT COMMAND INVALID COMMAND 1 2 Commands that partially invalidate caching data When data in the buffer or on media is overwritten the overwritten data is invalidated READ DMA READ MULTIPLE READ SECTOR s READ DMA EXT READ MULTIPLE EXT READ SECTOR s EXT WRITE DMA WRITE MULTIPLE WRITE SECTOR s WRITE DMA EXT WRITE MULTIPLE EXT WRITE SECTOR s EXT SMART 2 hard reset is issued or the power is turned off 3 When HOST CRC ERROR has occurred C141 E195 02EN 6 4 Read ahead Cache 6 4 3 Using the read segment buffer Methods of using the read segment buffer are explained for following situations 6 4 3 1 Miss hit In this situations the top block of read requested data is not stored at all in the data buffer As a result all of the read requested data is read from disk media 1 HAP host address pointer and DAP disk address pointer are defined in the head of the segment allocated from Buffer If pre read is executed HAP is set at the requested data reading position AP host address pointer T DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data is stored until this point HAP 1 Read requested data Free space T DAP 3 When reading of read requested data is completed and transfer of the read requested data to the host
67. E195 02EN 5 71 Interface Table 5 8 Format of device attribute value data 00 Data format version number 01 0 Attribute 1 Attribute ID 03 Status flag Current attribute value Attribute value for worst case so far 07 to 0 Raw attribute value Reserved OEto 169 Attribute 2 to The format of each attribute value is the same as attribute 30 that of bytes 02 to OD 16A Off line data collection status 16B 16C 16D Off line data collection execution time sec 16E Reserved 16F Off line data collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Self test error detection point 174 Simple self test Quick Test execution time min 175 Comprehensive self test Comprehensive Test execution time min 176 Conveyance self test execution time min 177to 181 Reserved 182 to IFE Vendor unique Check sum Table 5 9 Format of insurance failure threshold value data 01 01 Threshold 1 Attribute ID Insurance failure threshold Threshold 30 that of bytes 02 to OD Reserved 17C to IFE Vendor unique Check sum 5 72 C141 E195 02EN Attribute ID C141 E195 02EN Attribute ID p p 0 E 192 93 o 195 196 198 200 5 3 Host Commands Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds The dat
68. F1 FR P IFI FR C C Current P Previous At command completion I O registers contents to be read EST wem 1 ovj 1F5 CH 1 Native max address LBA 47 40 1F5 CH 0 Native max address LBA 23 16 1F4 CL 1 Native max address LBA 39 32 1F4 CL 0 Native max address LBA 15 8 1F3 SN 1 Native max address LBA 31 24 1F3 SN 0 Native max address LBA 7 0 1F2 SC 1 xx 1F2 SC 0 xx 1F1 ER Error information 0 HOB 0 1 HOB 1 C141 E195 02EN 5 95 Interface 39 SET MAX ADDRESS EXT 37H Option customizing 5 96 Description This command limits specifications so that the highest address that can be accessed by users can be specified only in LBA mode The address information specified with this command is set in words 1 54 57 58 60 61 and 100 to 103 of the IDENTIFY DEVICE command response If read or write processing is executed for an address that is outside of the new address space an ID Not Found error occurs If the SC register bit is O and the value volatile VV bit is 1 when this command is executed the specified values are maintained after a power on reset If the VV bit is 0 when the command is executed the specified values are invalidated during the power on sequence If the VV bit is 1 the highest address value is defined as the last value specified If the VV bit is not set to 1 the highest address is the default value After a powe
69. Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 5 11 Figure 5 12 Figure 5 13 Figure 5 14 Figure 5 15 Figure 5 16 Figure 5 17 Figure 5 18 Figure 5 19 Figure 5 20 Figure 5 21 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 C141 E195 02EN Contents Protocol for command abort sse 5 111 WRITE SECTOR S command protocol suse 5 113 Protocol for the command execution without data transfer 5 114 Normal DMA data transfer sese 5 117 Ultra DMA termination with pull up or pull down 5 129 PIO data transfer timing sese 5 130 Multiword DMA data transfer timing mode 2 5 131 Initiating an Ultra DMA data in burst eese 5 132 Sustained Ultra data in burst sse 5 136 Host pausing an Ultra DMA data in 5 137 Device terminating an Ultra DMA data in burst 5 138 Host terminating an Ultra DMA data in burst 5 139 Initiating an Ultra DMA data out 5 140 Sustained Ultra DMA data out burst esee 5 141 Device pausing an Ultra DMA data out 5 142 Host terminating an Ultra DMA data out burst
70. I transfer Trasnfers dummy data The host should receive 512 byte dummy data or release the DRQ set state by resetting C141 E195 02EN Figure 5 4 Protocol for command abort 5 111 Interface 5 4 2 PIO Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive WRITE SECTOR S EXT WRITE LONG WRITE BUFFER WRITE VERIFY SMART WRITE LOG SECTOR SECURITY DISABLE PASSWORD SECURITY ERASE UNIT SECURITY SET PASSWORD SECURITY UNCLOK The execution of these commands includes the transfer one or more sectors of data from the host to the device In the WRITE LONG command 516 bytes are transferred Following shows the protocol outline a b c d e f g h i The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers The host writes a command code in the Command register The drive sets the BSY bit of the Status register When the device is ready to receive the data of the first sector the device sets DRQ bit and clears BSY bit The host writes one sector of data through the Data register The device clears the DRQ bit and sets the BSY bit When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the DRQ bit After detecting the INTRQ si
71. I FR C C Current P Previous LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 XX XX At command completion I O registers contents to be read ERST LT 1F5 CH 1 1FS CH 0 1F4 CL 1 1F4 CL 0 1F3 SN 1 1F3 SN 0 1F2 SC 1 1F2 SC 0 1F1 ER 0 HOB 0 1 HOB 1 C141 E195 02EN LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 XX XX Error information 5 103 Interface 46 READ SECTOR S EXT 24H Option customizing e Description This command is the extended command of the READ SECTOR S command The LBA specification is increased from 28 bits to 48 bits and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h Other command controls are the same as those of the READ SECTOR S command At command issuance I O registers setting contents 1F7 CM 0 0 1 0 0 1 0 1 LE 1F5 CH P 1 5 C 1F4 CL P 1F4 CL C 1F3 SN P 1F3 SN C 1F2 SC 1F2 SC C 1F1 FR P IF1 FR C C Current P Previous LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 XX XX At command completion I O registers contents to be read IFAT LE 1F5 CH 1 1F5 CH 0 1F4 CL 1 1F4 CL 0 1F3 SN 1 1F3 SN 0 1F2 SC 1 1F2 SC 0 1F1 ER 0 HOB 0
72. II code 40 characters left 4 X 8010 Maximum number of sectors per interrupt on READ WRITE MULTIPLE command Reserved 9 Capabilities 4 0 Capabilities 5 51 PIO data transfer mode 6 2 Reserved 53 Enable disable setting of words 54 58 and 64 70 88 7 54 Number of current Cylinders 55 Number of current Head 6 Number of current sectors per track 57 58 Total number of current sectors Transfer sector count currently set by READ WRITE MULTIPLE command 8 Total number of user addressable sectors LBA mode only 2 Reserved Multiword DMA transfer mode 9 Advance PIO transfer mode support status 10 X 0078 Minimum multiword DMA transfer cycle time per word 120 ns 5 34 C141 E195 02EN 5 3 Host Commands Table 5 4 Information to be read by IDENTIFY DEVICE command 2 of 2 X 0078 Manufacturer s recommended DMA transfer cycle time 120 ns 67 X 00F0 Minimum PIO transfer cycle time without IORDY flow control 240 ns X 0078 Minimum PIO transfer cycle time with IORDY flow control 120 ns T Enhanced Security Erase Unit execution time 1 LSB 2 min 5 7 x 94 Acoustic Management level 21 100 103 Xxx Total number of sectors accessible by users in the 48 bit LBA mode 22 255 5 Check sum The 2 complement of the lower order byte resulting from summing bits 7 to 0 of word 0 to 254 and word 255 in byte units Word 0 General configuration 85 87 88 EM E
73. Interface signals 5 2 C141 E195 02EN 5 1 2 Signal assignment on the connector 5 1 Physical Interface Table 5 1 shows the signal assignment on the interface connector Table 5 1 Signal assignment on the interface connector C141 E195 02EN MSTR PUS KEY RESET 7 5 4 DATA2 DATAI DATAO GND DMARQ DIOW STOP DIOR HDMRDY HSTROBE IORDY DDMARDY DSTROBE DMACK INTRQ DAI DAO CS0 DASP 5 VDC GND MSTR ENCSEL ENCSEL KEY GND DATAS DATA9 DATA10 DATAI1 DATAI2 DATAI3 DATAI4 DATAI5 KEY GND GND GND CSEL GND reserved IOCS16 PDIAG CBLID DA2 CS1 GND 5 VDC unused 5 3 signal ENCSEL MSTR PUS RESET DATA 0 15 DIOW STOP DIOR HDMARDY HSTROBE INTRQ O Description This signal is used to set master slave using the CSEL signal pin 28 PinsBandD Open Sets master slave using the CSEL signal is disabled Sets master slave using the CSEL signal is enabled MSTR I Master slave setting Pin A B C D open Master setting Pin A B Short Slave setting When pin C is grounded the drive does not spin up at power on Short Reset signal from the host This signal is low active and is asserted for a minimum of 25 us during power on Sixteen bit bi directional data bus between the host and the device These signals are used for data transfer Signal asserted by the host to wr
74. M lt lt EM ard lt a 9 Es 9 CA Bit 15 ATA device 0 ATAPI device 1 C141 E195 02EN 5 35 Interface 5 36 Bit 14 8 Undefined Bit 7 Removable disk drive 1 Bit 6 Fixed drive 1 Bit 5 3 Undefined Bit 2 IDENTIFY DEVICE 0 Bit 1 0 Reserved 2 Word 1 3 6 60 61 Word 01 X 3FFF Word 03 x0 Word 06 Word 60 61 X 4A85300 3 Status of the Word 2 Identify information is shown as follows 37C8h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete 738Ch The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete 8C73h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete C837h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete Others Reserved 4 Word 49 Capabilities Bit 15 14 Reserved Bit 13 Standby timer value ATA spec is 1 Bit 12 Reserved Bit 11 Supported Bit 10 0 Disable inhibition Bit 7 0 Undefined Bit 8 1 ZLBA Supported Bit 9 1 Supported C141 E195 02EN 5 3 Host Commands 5 Word 50 Device capability Bit 15 0 Bit 14 1 Bit 13 to 1 Reserved Bit 0 Standby time
75. N register Next it clears the BSY bit and transmits the log sector to the host computer SN SC Log sector 00h 01h SMART log directory 01h 01h SMART summary error log 02h 33h SMART comprehensive error log 06h 01h SMART self test log 09h 01h SMART selective self test log 80h 9Fh Olh 10h Host vendor log See Table 5 11 concerning the SMART error log data format See Table 5 12 concerning the SMART self test log data format See Table 5 13 concerning the SMART selective self test log data format X D6 SMART Write Log A device which receives this sub command asserts the BSY bit and when it has prepared to receive data from the host computer it sets DRQ and clears the BSY bit Next it receives data from the host computer and writes the specified log sector in the SN register SN SC Log sector 09h 01h SMART selective self test log 80h 9Fh Olh 10h Host vendor log The host can write any desired data in the host vendor log X Dg SMART Enable Operations This subcommand enables the failure prediction feature The setting is maintained even when the device is turned off and then on When the device receives this subcommand it asserts the BSY bit enables the failure prediction feature then clears the BSY bit X D9 SMART Disable Operations This subcommand disables the failure prediction feature The setting is maintained even when the device is turned off and then on When the device receives this subcommand it as
76. O The host shall keep CSO0 CS1 DA2 DAI and DAO negated until after negating DMACK at the end of the burst 6 Steps 3 4 and 5 shall have occurred at least t4ck before the host asserts DMACK The host shall keep DMACK asserted until the end of an Ultra DMA burst 7 The host shall release DD 15 0 within t4z after asserting DMACK 5 119 Interface 8 9 10 11 12 The device may assert DSTROBE tzjorpy after the host has asserted DMACK Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK at the end of an Ultra DMA burst The host shall negate STOP and assert HDMARDY within tgyy after asserting DMACK After negating STOP and asserting HDMARDY the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device i e after the first data word has been received The device shall drive DD 15 0 no sooner than after the host has asserted DMACK negated STOP and asserted The device shall drive the first word of the data transfer onto DD 15 0 This step may occur when the device first drives DD 15 0 in step 10 To transfer the first word of data the device shall negate DSTROBE within tps after the host has negated STOP and asserted HDMARDY The device shall negate DSTROBE no sooner than tpys after driving the first word of data onto DD 15 0 5 5 3 2 T
77. O registers setting contents 1F74 CM 1F54 CH 1F4 CL 1F34 SN 1 2 1 1 C141 E195 02EN 5 3 Host Commands At command completion I O registers contents to be read Des s Ts Ts ove 1 5 1F44 CL XX 1F3y SN XX 1F2 SC XX 1 15 Error information 13 IDENTIFY DEVICE X EE When this command is not used to transfer data to the host in DMA mode this command functions in the same way as the Identify Device command At command issuance I O registers setting contents Dr S T T TT 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F14 FR At command completion I O registers contents to be read Des fs Ts Ts ove 1 5 1 4 1F34 SN XX 1 2 1F1y ER Error information C141 E195 02EN 5 33 Interface Table 5 4 Information to be read by IDENTIFY DEVICE command 1 of 2 XO05 amp General Configuration 1 Number of Logical cylinders 2 etailed Configuration 3 3 Number of Logical Heads 2 4 5 Undefined Number of Logical sectors per Logical track 2 7 9 Undefined 10 19 Serial number ASCII code 20 characters right Undefined uffer Size 1 LSB 512 Byte ex Buffer Size 8MByte X 4000 X 0004 Number of ECC bytes transferred at READ LONG or WRITE LONG command 23 26 Firmware revision ASCII code 8 characters left 27 46 Set by a device Model name ASC
78. ONG command The READ LONG command supports only single sector operation Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command At command issuance I O registers setting contents 87 1 0 0 0 1 R 1F6 DH Head No LBA MSB 1F5 CH Cylinder No MSB LBA 1F44 CL Cylinder No LSB LBA 1F34 SN Sector No LBA LSB 1F2 SC 01 IFly FR xx R Retry At command completion I O registers contents to be read 1F6 DH Head No LBA MSB 1F54 CH Cylinder No MSB LBA 1F44 CL Cylinder No LSB LBA 1F3y SN Sector No LBA LSB 1 2 1 1 Error information C141 E195 02EN 5 57 Interface 20 WRITE LONG X32 or X337 5 58 This command operates similarly to the READ SECTOR S command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium The device does not generate ECC bytes by itself The WRITE LONG command supports only single sector operation The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET FEATURES command This command is operated under the following conditions e READ LONG issued gt WRITE LONG Same address issues sequence After READ LONG is issued WRITE LONG can be issued consecutively If above condition 1 not satisfied the WRITE LONG Data becomes the Uncorrectable error fo
79. READ NATIVE MAX ADDRESS command is executed C141 E195 02EN 5 51 Interface At command issuance I O registers setting contents 1F74 CM 1 1 1 1 1 0 0 1 1F5 CH xx IFAKCL 1 2 1F1 FR At command completion I O registers contents to be read 1F6 DH 1 5 1F4 CL xx 1F3 SN IF2 SC xx e SET MAX UNLOCK 03h This command requests a transfer of single sector of data from the host and defines the contents of SET MAX ADDRESS password The password supplied in the sector of data transferred shall be compared with the stored password If the password compare fails the device returns command aborted and decrements the Unlock counter and remains in the Set Max Lock state On the acceptance of the SET MAX LOCK command the Unlock counter is set to a value of five When this counter reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If the password compare matches then the device makes a transition to the Set Max Unlocked state and all SET MAX commands will be accepted The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed 5 52 C141 E195 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F74 CM 1 1 1 1 1 0 0 1 1F5 CH xx IFA CL
80. S command FR C2h If a DEVICE CONFIGURATION SET command has already modified the original settings as reported by a DEVICE CONFIGURATION IDENTIFY command if DEVICE CONFIGURATION FREEZE LOCK is set if any of the bit modification restrictions described are violated or if a Host Protected Area has been established by the execution of aSET MAX ADDRESS EXT command an aborted error is posted C141 E195 02EN 5 93 Interface Table 5 18 DEVICE CONFIGURATION IDENTIFY data structure Word Value Content X 0001 Data structure revision X 0007 Multiword DMA modes supported Reflected in IDENTIFY information WORD63 Bit 15 3 Reserved Bit 2 1 Multiword mode 2 and below are supported Bit 1 1 Multiword mode 1 and below are supported Bit 0 1 Multiword mode 0 is supported X 003F Ultra DMA modes supported Reflected in IDENTIFY information WORD88 Bit 15 6 Reserved Bit 5 1 Ultra DMA mode 5 and below are supported Bit 4 1 Ultra DMA mode 4 and below are supported Bit 3 1 Ultra DMA mode 3 and below are supported Bit 2 1 Ultra DMA mode 2 and below are supported Bit 1 1 Ultra DMA mode 1 and below are supported Bit 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address Reflected in IDENTIFY information WORD60 61 WORD100 103 X 00CF X 01CF Command set feature set supported Reflected in IDENTIFY information WORDS2 87 Bit 15
81. Supports the Advanced Power Management feature set 2 Supports the CFA Compact Flash Association feature set Supports the READ WRITE DMA QUEUED command 2 Supports the DOWNLOAD MICROCODE command Option customizing Bit 15 Bit 14 Bit 13 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0 1 Reserved 2 Supports the SMART SELF TEST Supports the SMART Error Logging Undefined Supports the command Supports the READ BUFFER command Supports the WRITE BUFFER command Undefined Supports the Host Protected Area function 1 Supports the DEVICE RESET command 5 39 Interface Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16 WORD 86 Bits 15 Bit 13 10 Bit 9 Bit 8 Bits 7 6 Bit 5 Bit 4 Bit 3 Bits 2 0 17 WORD 87 Bits 15 Bits 14 Bits 13 2 Bit 1 0 5 40 Enables the SERVICE interrupt From the SET FEATURES command Enables the release interrupt From the SET FEATURES command Enables the read cache function From the SET FEATURES command Enables the write cache function Enables the P PACKET command set 2 Supports the Power Management function 2 Supports the Removable Media function From the SECURITY SET PASSWORD command From the SMART ENABLE OPERATION command Reserved Same definition as WORD 83
82. TY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command Issuing this command during FROZEN MODE returns the Aborted Command At command issuance I O register contents 1F7 CM ED mwe h 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 FR At command completion I O register contents Dm 1 5 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information 32 SECURITY ERASE UNIT F4h 5 84 This command erases all user data This command also invalidates the user password and releases the lock function The host transfers the 512 byte data shown in Table 5 15 to the device The device compares the user password or master password in the transferred data with the user password or master password already set The device erases user data invalidates the user password and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password C141 E195 02EN 5 3 Host Commands If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued the Aborted Command error is returned Issuing this command while in FROZEN MODE returns the Aborted Command error At command issuance I O register content
83. The following two types of technology are used for alternating processing 1 Sector slip processing In this method defective sectors are not used thereby avoiding the effects of defects and each defective sector is assigned to the next contiguous sector that is normal Depending on the format defined at shipment from the plant this processing is performed for defective sectors Figure 6 5 shows an example where sector physical 5 with cylinder 0 and head 0 is defective Index Sector physical 1 2 3 4 5 6 7 8 778 779 780 Cylinder 0 Defec Head 0 five sector 1 2 3 4 Not used 5 6 7 777 778 779 Note When an access request for sector 5 is issued physical sector 6 must be accessed instead of physical sector 5 Figure 6 5 Sector slip processing 2 Track slip processing In this method defective tracks not used there by avoiding the effects of defects and each defective track is assigned to the next contiguous track that is normal Depending on the format defined at shipment from the plant this processing is performed for defective tracks 6 10 C141 E195 02EN 6 3 Defect Processing 3 Automatic alternating processing This technology assigns a defective sector to a spare sector of an spare cylinder for alternate assignment This device performs automatic alternating processing in the event of any of the following errors e Automatic alternating p
84. The host shall pause an Ultra DMA burst by not generating an HSTROBE edge Note The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate Ultra DMA burst termination the device shall negate DDMARDY and wait tgp before negating DMARQ 3 The host shall resume an Ultra DMA burst by generating an HSTROBE edge Device pausing an Ultra DMA data out burst 1 The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2 The device shall pause an Ultra DMA burst by negating DDMARDY 3 The host shall stop generating HSTROBE edges within tgrs of the device negating DDMARDY 4 Ifthe device negates DDMARDY within tsp after the host has generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than tsp after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and timing for the host 5 The device shall resume an Ultra DMA burst by asserting DDMARDY 5 125 Interface 5 5 4 4 Terminating an Ultra DMA data out burst a Hostterminating an Ultra DMA data out burst The following stops shall occur in the order they are li
85. a format version numbers of the device attribute values and insurance failure thresholds are the same When a data format is changed the data format version numbers are updated Attribute ID The attribute ID is defined as follows 5 73 Interface 5 74 e Status Flag If this bit is 1 it indicates normal operations are assured with the attribute when the attribute value exceeds the threshold value If this bit is 1 0 it indicates the attribute only updated by an on line test off line test If this bit 1 it indicates the attribute that represents performance i If this bit 1 it indicates the attribute that represents an error rate If this bit 1 it indicates the attribute that represents the number of occurrences If this bit 1 it indicates the attribute that can be collected saved even if the drive fault prediction function is disabled Current attribute value It indicates the normalized value of the original attribute value The value deviates in a range of 01h to 64h range of O1h to C8h for the ultra ATA CRC error rate It indicates that the closer the value is to O1h the higher the possibility of a failure The host compares the attribute value with the threshold value If the attribute value is larger than the threshold value the drive is determined to be normal e Attribute value for the worst case so far This is the worst attribute value among the attribute values collected to date This val
86. ad write Circuit The read write circuit consists of the read write preamplifier PreAMP the write circuit the read circuit and the time base generator in the read channel RDC Figure 4 4 is a block diagram of the read write circuit 4 6 1 Read write preamplifier PreAMP PreAMP equips a read preamplifier and a write current switch that sets the bias current to the MR device and the current in writing Each channel is connected to each data head and PreAMP switches channel by serial I O In the event of any abnormalities including a head short circuit or head open circuit the write unsafe signal is generated so that abnormal write does not occur 4 6 2 Write circuit The write data is output from the hard disk controller HDC with the NRZ data format and sent to the encoder circuit in the RDC The NRZ write data is converted from 60 bit data to 63 bit data by the encoder circuit then sent to the HDIC and the data is written onto the media 1 32 34 RLL MEEPRML This device converts data using the 60 63 RLL Run Length Limited algorithm 2 Write precompensation Write precompensation compensates during a write process for write non linearity generated at reading RDC Block PreAMP NRZ Interface Syne Mark Gray Code Detector Servo Data 0 2 SGate PECL Precomp Driver W RGate L WGate Figure 4 4 Read write circuit block diagram C141 E195 02EN 4 9 Theory of Device Operati
87. ame format eee deese veri deett eter edes egens 4 16 4 7 4 Actuator motor control 4 17 4 7 5 Spindle motor eee tertiae 4 18 DRC Cole 5 1 5 1 Physical Interface eie ient Rae IH stares sed ertet hte bitten 5 2 SLL Interface signals dee pe eee eee ec et eene 5 2 5 1 2 Signal assignment on the 5 3 2 2 LEogical Inter eee Ideni 5 6 5 2 1 Testers ests un eee eee te eee eee i eee tenis 5 7 5 2 2 Command block registers eese ener 5 8 5 2 3 Control block registers reete ee ted Rete reete 5 13 25 9 Host Commands etre 5 14 5 3 1 Command code and parameters esee 5 14 5 3 2 Command enne 5 18 2 9 9 Error posting cy indere e EUR inte yen a 5 107 5 4 Command Protocol 5 109 5 4 1 Data transferring commands from device to host 5 109 5 4 2 Data transferring commands from host to device 5 112 5 4 3 Commands without data transfer sese 5 114 5 4 44 Other commands erenn n oen rentre ener eee intensa 5 115 5 4 5 data transfer commands eese 5 115 5 9 Ultra DMA Feature Set in eite ere Lp eed pee 5 118 eletti pb eee 5 118 5 5 2 Pha
88. and 5 34 Table 5 5 Features register values and settable 5 44 Table 5 6 Diagnostic code eerte te Reo tte 5 56 Table 5 7 Features Register values subcommands and functions 5 68 Table 5 8 Format of device attribute value data eese 5 72 Table 5 9 Format of insurance failure threshold value data 5 72 Table 5 10 Log Directory Data Format eese 5 77 Table 5 11 Data format of SMART Summary Error Log 5 78 Table 5 11 1 Data format of SMART Comprehensive Error Log 5 79 Table 5 12 SMART self test log data format eee 5 80 Table 5 13 Selective self test log data 5 81 Table 5 14 Selective self test feature flags see 5 82 Table 5 15 Contents of security password sese 5 83 Table 5 16 Contents of SECURITY SET PASSWORD 5 87 Table 5 17 Relationship between combination of Identifier and Security level and operation of the lock function 5 88 Table 5 18 DEVICE CONFIGURATION IDENTIFY data structure 5 94 Table 5 19 Operation of DOWNLOAD MICRO CODE 5 106 Table 5 20 Example of rewriting procedure of data 384 KBytes 30000h Bytes of microcode
89. asize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 17 Sustained Ultra DMA data out burst C141 E195 02EN 5 141 Interface 5 6 3 9 Device pausing an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra Modes trp DMARQ device DMACK host STOP host DDMARDY device dk host 0159 XK XX XX XXXXXXX host Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tgp after DDMARDY is negated 2 After negating DDMARDY the device may receive zero one two or three more data words from the host Figure 5 18 Device pausing an Ultra DMA data out burst 5 142 C141 E195 02EN 5 6 Timing 5 6 3 10 Host terminating an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ tss tu DMACK tu STOP ties tioRDvz DDMARDY ON host device HSTROBE host 4 tevs 00 15 0 DONE ROOK KORO ORG tack DAO DA1 DA2 C80 CS1 The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 19 Host terminating an Ultra DMA data out burst
90. at can be transferred by a single command is changed from 100h to 10000h Other command controls are the same as those of the READ MULTIPLE command At command issuance I O registers setting contents 1F7 CM 0 0 1 1 1 0 0 1 LE 1F5 CH 1F5 CH C 1F4 CL P 1F4 CL C 1F3 SN P 1F3 SN C 1F2 SC 1F2 SC C 1F1 FR P 1F1 FR C C Current P Previous LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 XX XX At command completion I O registers contents to be read IFAT LE 1F5 CH 1 1F5 CH 0 1F4 CL 1 1F4 CL 0 1F3 SN 1 1F3 SN 0 1F2 SC 1 1F2 SC 0 1F1 ER 0 HOB 0 1 HOB 1 5 102 LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 XX XX Error information C141 E195 02EN 5 3 Host Commands 45 WRITE SECTOR S EXT 34H Option customizing e Description This command is the extended command of the WRITE SECTOR S command The LBA specification is increased from 28 bits to 48 bits and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h Other command controls are the same as those of the WRITE SECTOR S command At command issuance I O registers setting contents 1F7 CM 0 0 1 1 1 0 0 1 LE 1F5 CH P 1 5 C 1F4 CL P 1F4 CL C 1F3 SN 1F3 SN C 1F2 SC 1F2 SC C 1F1 FR P IF
91. attachment American wire gage B Bad block detected Basic input output system C Corrected data Cylinder high register Cylinder low register Command register Current sense register Current start stop Cylinder register D dB A scale weighting Disk enclosure Device head register Drive ready Ddata request bit Drive seek complete Drive write fault E Error checking and correction Error register Error F Feature register H Host adapter C141 E195 02EN HDD IDNF 18014 LED MB MB S MPU PCA PIO RLL SA 5 5 SN ST TPI TRONF Typ UNC VCM Hard disk drive ID not found Interrupt request 14 L Light emitting diode Mega byte Mega byte per seconds Micro processor unit P Printed circuit assembly Programmed input output R Run length limited S System area Sector count register Signal ground Sector number register Status register T Track per inches Track 0 not found Typical U Uncorrectable ECC error V Voice coil motor AB 1 This page is intentionally left blank Index A active idle mode 6 7 active mode 6 7 alternating processing automatic 6 11 for defective sector 6 10 for defective sector 6 10 area spare 6 9 assignment processing alternate cylinder 6 10 automatic alternating processing 6 11 B blower 4 3 C caching operation 6 13 6 19 command sequential 6 16 command target of caching 6 13 command that is ta
92. becomes Microcode rewriting execution specification 1 Abnormality of the transmitted Microcode data is detected 2 The data transfer is not done The number of transfer 0 3 DOWNLOAD MICROCODE The command is not continuously issued Table 5 20 Example of rewriting procedure of data 384 KBytes 30000h Bytes of microcode Transfer example 1 1 CMD 92h SN 5 0100 FR Transfer of 127 KB from the first 2 CMD 92h SN SC20100h FR 20lh Transfer from 128 to 255 KB 3 CMD 92h SN SC 0100h FR Transfer from 256 to 383 KB 4 CMD 92h SN SC 0000h FR 207h Firmware rewriting execution Transfer example 2 1 CMD 92h SN SC20300h FR 20lh Transfer of 384 KB 2 CMD 92h SN SC 00006 FR 207h Firmware rewriting execution Transfer example 3 1 CMD 92h SN 5C20300h FR 07 Transfer of 384 KB and Firmware rewriting execution Transfer example 4 1 CMD 92h SN SC 0100h FR Olh Transfer of 127 KB from the first 2 CMD 92h SN SC20100h FR Olh Transfer from 128 to 255 KB 3 CMD 92h SN 01006 207h Transfer from 256 to 383 KB and Firmware rewriting execution When the data of the transfer microcode did the rewriting specification with the illegality and the data transfer not done or the DOWNLOAD MICROCODE command is not continuously issued reports on the Aborted Command error 5 106 C141 E195 02EN 5 3 Host Commands 5 3 3 Error posting Table 5 21 lists the defined err
93. c attribute save function is disabled the attributes are not saved Upon receiving this subcommand a device asserts BSY enables or disables the automatic attribute save function and clears BSY SMART Save Attribute Values When the device receives this subcommand it asserts the BSY bit saves device attribute value data then clears the BSY bit X DA SMART Executive Off line Immediate device which receives this command asserts the BSY bit then starts collecting the off line data specified in the SN register or stops In the off line mode after BSY is cleared off line data are collected In the captive mode it collects off line data with the BSY assertion as is then clears the BSY when collection of data is completed SN Off line data collection mode 006 Off line diagnosis off line mode 016 Simple self test off line mode 02h Comprehensive self test off line mode 03h Conveyance self test off line mode 04h Selective self test off line mode 7Fh Self test stop 81h Simple self test captive mode 82h Comprehensive self test captive mode 83h Conveyance self test captive mode 84h Selective self test captive mode 5 68 C141 E195 02EN 5 3 Host Commands Table 5 7 Features Register values subcommands and functions 2 of 3 Features Resister Function X DS SMART Read Log A device which receives this sub command asserts the BSY bit then reads the log sector specified in the S
94. ccurred see 5 5 5 The device shall release DDMARDY within tjogpyz after the host has negated DMACK 5 127 Interface 13 The host shall neither negate STOP nor HSTROBE until at least tacx after negating DMACK 14 The host shall not assert DIOW CSO CS1 DA2 DAI or DAO until at least tacx after negating DMACK 5 5 5 Ultra DMA CRC rules The following is a list of rules for calculating CRC determining if a CRC error has occurred during an Ultra DMA burst and reporting any error that occurs at the end of a command a Both the host and the device shall have a 16 bit CRC calculation function b Both the host and the device shall calculate a CRC value for each Ultra DMA burst c The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred d For each STROBE transition used for data transfer both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged e At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with
95. ces on the actuator and stores the calibration value 2 Servo burst capture circuit The servo burst capture circuit reproduces signals position signals that indicate the head position from the servo data on the data surface From the servo area on the data area surface via the data head the burst signal of SERVO A SERVO B SERVO C and SERVO D is output as shown in Figure 4 9 in subsequent to the servo mark gray code that indicates the cylinder position and index information The servo signals do A D convert by Fourier demodulator in the servo burst capture circuit At that time the AGC circuit is in hold mode The A D converted data is recognized by the MPU as position information with A B and C D processed 3 D A converter DAC The control program calculates the specified data value digital value of the VCM drive current and the value is converted from digital to analog so that an analog output voltage is sent to the power amplifier 4 Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM C141 E195 02EN 4 13 Theory of Device Operation 5 Spindle motor control circuit The spindle motor control circuit controls the sensor less spindle motor A spindle driver IC with a built in PLL FLL circuit that is on a hardware unit controls the sensor less spindle motor 6 Driver circuit The driver circuit is a power amplitude circuit that receives signals from
96. circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the Modified Extended Partial Response MEEPR and Data Dependent Media Noise Processor and contains the Viterbi detector programmable filter adaptable transversal filter times base generator data separator circuits 60 63 RLL Limited encoder Run Length and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice coil motor The MPU precisely sets each head on the track according on the servo information on the media surface 3 Spindle motor driver circuit The circuit measures the interval of a PHASE signal generated by counter electromotive voltage of a motor and controls the motor speed comparing target speed C141 E195 02EN 4 3 Theory of Device Operation 4 Controller circuit Major functions are listed below e Data buffer management interface control and data transfer control e Sector format control e Defect management e control e Error recovery and self diagnosis 5 0V 3 3V 1 8V generator generator circuit circuit MCU
97. cture 2 to bytes 02 to 5B Error log data structure 5 4 1C5 Number of unrecoverable errors that have occurred w 5 5B 5 78 C141 E195 02EN 5 3 Host Commands Command data structure Indicates the command received when an error occurs e Hrror data structure Indicates the status register when an error occurs Total number of drive errors Indicates total number of errors registered in the error log e Checksum Two s complementary for the lowest order 1 byte that is obtained by adding 1 byte after another for as many as 511 bytes beginning from the top of the structure e Status Bits 3 Indicates the drive status when received error commands according to the following table Bits 4 to 7 Vendor unique Status Meaning 0 Unclear status 1 Sleep status 2 Standby status 3 Active status BSY bit 0 4 Off line data collection being executed g5 Reserved Table 5 11 1 Data format of SMART Comprehensive Error Log C141 E195 02EN 5 79 Interface 5 80 Byte SMART Self Test The host computer can issue the SMART Execute Off line Immediate sub command FR Register D4h and cause the device to execute a self test When the self test is completed the device saves the SMART self test log to the disk medium The host computer can issue the SMART Read Log Sector sub command FR Regis
98. cuit is contained in the SVC that is used for this hard disk drive The circuit controls the hardware to keep the rotational state steady to maintain the target rotational speed The firmware calculates the time for one rotation based on the PHASE signal output from the SVC to monitor the rotational state The control of this mode charge discharge is performed every rotation 4 18 C141 E195 02EN CHAPTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 53 Host Commands 5 4 Command Protocol 5 5 Ultra Feature Set 5 6 Timing This chapter gives details about the interface and the interface commands and timings C141 E195 02EN 5 1 Interface 5 1 Physical Interface 5 1 1 Interface signals Figure 5 1 shows the interface signals DATA 0 15 DATA BUS DMACK DMA ACKNOWLEDGE DMARQ DMA REQUEST INTRO INTERRUPT REQUEST DIOW WRITE STOP STOP DURING ULTRA DMA DATA BURSTS DIOR I O READ HDMARDY DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE DATA STROBE DURING ULTRA DMA DATA OUT BURST PDIAG PASSED DIAGNOSTICS CBLID CABLE TYPE IDENTIFIER DASP DEVICE ACTIVE SLAVE PRESENT IORDY I O READY DDMARDY DMA READY DURING ULTRA DMA DATA OUT BURSTS DSTROBE DATA STROBE DURING ULTRA DMA DATA IN BURSTS DA 0 2 DEVICE ADDRESS CSO CHIP SELECT 0 CS1 CHIP SELECT 1 RESET RESET CSEL CABLE SELECT MSTR Master ENCSEL ENABLE CSEL GND GROUND Figure 5 1
99. d under the LBA mode of the EXT command Bit2 HS2 CHS mode head address 2 2 bit 26 for LBA mode Unused under the LBA mode of the EXT command Bit 1 HS1 CHS mode head address 1 2 bit 25 for LBA mode Unused under the LBA mode of the EXT command 0 HSO CHS mode head address 0 25 bit 24 for LBA mode Unused under the LBA mode of the EXT command 9 Status register X 1F7 The contents of this register indicate the status of the device The contents of this register are updated at the completion of each command When the BSY bit is cleared other bits in this register should be validated within 400 ns When the BSY bit is 1 other bits of this register are invalid When the host system reads this register while an interrupt is pending it is considered to be the Interrupt Acknowledge the host system acknowledges the interrupt Any pending interrupt is cleared negating INTRQ signal whenever this register is read C141 E195 02EN 5 11 Interface 5 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Busy BSY bit This bit is set whenever the Command register is accessed Then this bit is cleared when the command is completed However even if a command is being executed this bit is 0 while data transfer is being requested bit 1 When BSY bit is 1 the host system should not write the command block registers If the host system reads any command block register when BSY b
100. e executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the target track 1 Operation to move the head to the reference cylinder The MPU moves the head to the reference cylinder when the power is turned The reference cylinder is in the data area When power is applied the heads are moved from the outside of media to the normal servo data zone in the following sequence a Micro current is fed to the VCM to press the head against the outer direction b The head is loaded on the disk c When the servo mark is detected the head is moved slowly toward the inner circumference at a constant speed d Ifthe head is stopped at the reference cylinder from there Track following control starts 2 Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read write instruction 1s issued the MPU seeks the desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the difference speed error between the specified target position and the current position for each sampling timing during head moving The MPU then feeds the VCM drive current by setting the calculated resul
101. e Log Frequency MHz Figure 4 5 Frequency characteristic of programmable filter 4 10 C141 E195 02EN 3 FIR circuit 4 6 Read write Circuit This circuit is 10 tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response MEEPR waveform 4 A D converter circuit This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data 5 Viterbi detection circuit 6 ENDEC The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit The Viterbi detection circuit demodulates data according to the survivor path sequence This circuit converts the 63 bit read data into the 60 bit NRZ data 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant The drive divides data area into 30 zones to set the data transfer rate The MPU transfers the data transfer rate setup data SD SC to the RDC that includes the Digital PLL circuit to change the data transfer rate C141 E195 02EN 4 11 Theory of Device Operation 4 7 Servo Control The actuator motor a
102. e No of Device 1 00 Reserved 01 Using a jumper 5 41 Interface 5 42 Bits 7 0 2 WORD 94 Bit 15 8 Bit 7 0 10 Using the CSEL signal 11 Other method Bit 8 1 In the case of device 1 In the case of Device 0 master drive a valid value is set Bit 7 Reserved Bit 6 Device 1 is selected Device 0 responds Bit 5 Device 0 assertion of DASP was detected Bit 4 Device 0 assertion of PDIAG was detected Bit 3 Device 0 an error was not detected in the self diagnosis Bit2 1 Method for deciding the device No of Device 0 00 Reserved 01 Using a jumper 10 Using the CSEL signal 11 Other method Bit 0 2 In the case of device 0 X FE Recommended acoustic management value X XX Current set value FE CO Performance mode BF 80 Acoustic mode 00 Acoustic management is unused it It is same as FE CO 22 WORD 100 103 When 48 bit LBA of the option customize is supported same number of LBA as WORD 60 61 is displayed 23 WORD 128 Bit 15 9 Bit 8 Bit 7 6 Bit 5 Bit 4 Reserved Security level 0 High 1 Maximum Reserved Enhanced security erase supported 2 Security counter expired C141 E195 02EN Bit 3 Bit 2 Bit 1 Bit 0 14 SET FEATURES X EF 5 3 Host Commands Security frozen 2 Security locked Security enabled Security supported The host s
103. e content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command After execution of this command the settings are kept for the device power down or reset If a Host Protected Area has been set by aSET MAX ADDRESS EXT command or if DEVICE CONFIGURATION FREEZE LOCK is set an aborted error is posted e DEVICE CONFIGURATION FREEZE LOCK FR C 1h The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition is cleared by a power down not cleared by a hardware or software reset If the device has executed a previous DEVICE CONFIGURATION FREEZE LOCK command since power up an aborted error is posted 5 92 C141 E195 02EN 5 3 Host Commands e DEVICE CONFIGURATION IDENTIFY FR C2h The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure is shown in Table 5 18 The content of this data structure indicates the selectable commands modes and feature sets that the device 15 capable of supporting If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities t
104. e edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays on the ramp out of the disk and is fixed by a mechanical lock 5 Air circulation system 2 2 The disk enclosure DE is sealed to prevent dust and dirt from entering The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure C141 E195 02EN 2 2 System Configuration 6 Read write circuit The read write circuit uses a LSI chip for the read write preamplifier It improves data reliability by preventing errors caused by external noise 7 Controller circuit The controller circuit consists of an LSI chip to improve reliability The high speed microprocessor unit MPU achieves a high performance AT controller 2 2 System Configuration 2 2 1 ATA interface Figures 2 2 and 2 3 show the ATA interface system configuration The drive has a 44 PC AT interface connector and supports PIO mode 4 transfer at 16 6 MB s Multiword DMA mode 2 transfer at 16 6 MB s and also U DMA mode 5 100 MB s 2 2 2 1 drive connection MHT2080AH MHT2060AH MHT2040AH AT bus ATA interface Host interface Figure 2 2 1 drive system co
105. e host writes the Sector Count register with the desired power management level and executes this command with the Features register X 05 and then Advanced Power Management is enabled The drive automatically shifts to power saving mode up to the specified APM level when the drive does not receive any commands for a specific time The sequence in which the power management level shifts is from Active Idle to Low Power Idle to Standby The Mode 2 level requires the longest shifting time depending on the APM level settings The settings of the APM level revert to the Mode 1 when power on or a hardware reset occurs for the drive APM Level Sector Count Register Mode 0 Active Idle COh FEh Mode 1 Low Power Idle 80h BFh Mode 2 Standby 01h 7Fh Reserve State Keep 00h FFh Active Idle The spindle motor rotates and the head is loaded on the media Low Power Idle The spindle motor rotates and the head is unloaded Standby The spindle motor stops and the head is unloaded C141 E195 02EN 5 3 Host Commands 3 Automatic Acoustic Management AAM The host writes to the Sector Count register with the requested acoustic management level and executes this command with subcommand code 42h and then Automatic Acoustic Management is enabled The AAM level setting is preserved by the drive across power on hardware and software resets AAM Level Sector Count Register Performance mode Fast Seek COh FEh Acoustic mode Slow Se
106. e new address space an ID Not Found error will result When SC register bit 0 VV Value Volatile is 1 the value set by this command is held even after power on and the occurrence of a hard reset When the VV bit is 0 the value set by this command becomes invalid when the power is turned on or a hard reset occurs and the maximum address returns to the value most lately set when VV bit 1 The value by VV bit 0 is held in case that this command with VV bit 1 has not been issued or had set the default value and hard reset occurs After power on and the occurrence of a hard reset the host can issue this command only once when VV bit 1 If this command with VV bit 1 is issued twice or more any command following the first time will result in an Aborted Command error When the SET MAX ADDRESS EXT command is executed all SET MAX ADRESS commands are aborted The address value returns to the origin when the SET MAX ADDRESS EXT command is executed using the address value returned by the READ NATIVE MAX ADDRESS command At command issuance I O registers setting contents rem ILLA oW cd dod o 1F6 DH Max head LBA MSB 1 5 Max cylinder MSB Max LBA 1F4 CL Max cylinder LSB Max LBA 1F34 SN Max sector Max LBA LSB C141 E195 02EN 5 49 Interface At command completion I O registers contents to be read 1F6 DH Max head LBA MSB 1F54 CH Max cylinder MSB Max LBA 1F4 CL Max cylinder
107. e the DRQ status by resetting Figure 5 3 shows an example of READ SECTOR S command protocol and Figure 5 4 shows an example protocol for command abort Command Parameter write v Status read Status read VoM bi V a P i sy TL Loe Ls oy INTRQ Tes LLL Data Reg Selection Word 0 2 255 816 1 When IDD receives a command that hits the cache data during read ahead and transfers data from the buffer without reading from the disk medium Figure 5 3 Read Sector s command protocol 5 110 C141 E195 02EN 5 4 Command Protocol IMPORTANT For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple sector reading If the timing to read the Status register does not meet above condition normal data transfer operation is not guaranteed When the host new command even if the device requests the data transfer setting in DRQ bit the correct device operation is not guaranteed W Command Parameter write V Status read 1 BSY DRDY DRQ INTRQ es S Data TTTTTTTTTTTT
108. ector Number Cylinder and Device Head register The host initializes the DMA channel The host writes a command code in the Command register The device sets the BSY bit of the Status register The device asserts the DMARQ signal after completing the preparation of data transfer The device asserts either the BSY bit or DRQ bit during DMA data transfer When the command execution is completed the device clears both BSY and DRQ bits and asserts the INTRQ signal Then the host reads the Status register The host resets the DMA channel Figure 5 7 shows the correct DMA data transfer protocol C141 E195 02EN 5 4 Command Protocol Parameter write v Command Status read VA mmm eee 8 Bree Ces E DRDY a 5 transfer Expanded Multiword DMA transfer DRQ d J L DMARQ rrr tl DMACK e IOR au or IOW c ese Word 0 1 n 1 n Figure 5 7 Normal DMA data transfer C141 E195 02EN 5 117 Interface 5 5 Ultra DMA Feature Set 5 5 1 Overview 5 118 Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host This protocol applies to the Ultra DMA data burst only When this protocol is used there are no changes to other elements of the ATA protocol e g Command Block Register access Several
109. ek 80h BFh Abort Olh 7Fh Non Operate 00h FFh High speed seek to which gives priority to the performance operates as for Performance mode and low speed seek by which the seek sound is suppressed operates as for Acoustic mode Setting the seek mode by this command is applied to the seek operation in all command processing 15 SET MULTIPLE MODE 6 This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands The block count number of sectors in a block for these commands are also specified by the SET MULTIPLE MODE command The number of sectors per block is written into the Sector Count register The IDD supports 2 4 8 16 and 32 sectors as the block counts Upon receipt of this command the device sets the BSY bit of the Status register and checks the contents of the Sector Count register If the contents of the Sector Count register is valid and is a supported block count the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands Execution of these commands is then enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed t
110. erminated due to an error the remaining number of sectors for which data was not transferred is set in this register 3 READ DMA X C8 or X C9 This command operates similarly to the READ SECTOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal e The device posts a status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the error information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like in the CHS mode are set The host system can select the DMA transfer mode by using the SET FEATURES command e Multiword DMA transfer mode 0 to 2 e Ultra DMA transfer mode 0 to 5 5 22 C141 E195 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F6 DH Start head
111. es data transfer from the device to the host IDENTIFY DEVICE READ SECTOR S EXT READ LONG READ BUFFER SMART READ DATA SMART READ LOG SECTOR The execution of these commands includes the transfer one or more sectors of data from the device to the host In the READ LONG command 516 bytes are transferred Following shows the protocol outline a b c d e C141 E195 02EN The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers The host writes a command code to the Command register The device sets the BSY bit of the Status register and prepares for data transfer When one sector of data is available for transfer to the host the device sets DRQ bit and clears BSY bit The drive then asserts INTRQ signal After detecting the INTRQ signal assertion the host reads the Status register The host reads one sector of data via the Data register In response to the Status register being read the device negates the INTRQ signal The drive clears DRQ bit to 0 If transfer of another sector is requested the device sets the BSY bit and steps d and after are repeated 5 109 Interface Even if an error is encountered the device prepares for data transfer by setting the DRQ bit Whether or not to transfer the data is determined for each host In other words the host should receive the relevant sector of data 512 bytes of uninsured dummy data or releas
112. evice shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DDMARDY within tjogpyz after the host has negated DMACK The host shall neither negate STOP nor negate HSTROBE until at least tack after negating DMACK The host shall not assert DIOW CSO CS1 DA2 DAI or DAO until at least tacx after negating DMACK C141 E195 02EN 5 5 Ultra DMA Feature Set b Device terminating an Ultra DMA data out burst C141 E195 02EN The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 11 and 5 6 3 2 for specific timing requirements D 2 3 4 5 7 8 9 10 11 12 The device shall not initiate Ultra burst termination until at least one data word of an Ultra DMA burst has been transferred The device shall initiate Ultra DMA burst termination by negating DDMARDY The host shall stop generating an HSTROBE edges within tgrs of the device negating DDMARDY If the device negates DDMARDY within tsp after the host has generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than tsp after the host has ge
113. face control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean delay is the average time required for a head to reach a sector after the head is positioned on a track Seek time The seek time 15 the time required for a head to move from the current track to another track The seek time does not include the mean rotational delay Slave Device 1 The slave is a second drive that can operate on the AT bus The slave is daisy chained with the first drive operating in conformity with the ATA standard GL 2 C141 E195 02EN Glossary Status The status is a piece of one byte information posted from the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more magnets In this drive the VCM is used to position the heads accurately and quickly C141 E195 02EN GL 3 This page is intentionally left blank ABRT AIC AMNF ATA AWG BBK BIOS CORR CH CL CM CSR CSS CY dBA DE DH DRDY DRQ DSC DWF ECC ER ERR FR HA Acronyms and Abbreviations A Aborted command Automatic idle control Address mark not found AT
114. from the address where the data that 1s hit is stored until the top sector of the read requested data Remaining part of insufficient data is read then An example is a case where a partial hit occurs in cache data as shown below 1 TART LBA 2 AST LBA 1 HAPis set at the address where partial hit data is stored and Transfer is started HAP host address pointer U Cache valid data Partial hit data 2 DAP and HAP are set at the head of Buffer newly allocated and insufficient data is read AP host address pointer fr DAP disk address pointer 3 When reading the read requested data ends and the transmission of the read requested data to the host system ends the read ahead operation continues until a certain amount of data is stored The method of storing the read ahead data at Partial hit is the same as the Miss hit I gt LAST LBA START LBA 6 18 C141 E195 02EN 6 5 Write Cache 6 5 Write Cache Write Cache is the function for reducing the command processing time by separating command control to disk media from write control to disk media When Write Cache is permitted the write command can be keep receiving as long as the space available for data transfers remains free on the data buffer Because of this function command processing appears to be completed swiftly from the viewpoint of the host It improves system throughput 6 5 1 Cache operation 1 C
115. gnal assertion the host reads the Status register The device resets INTRQ the interrupt signal If transfer of another sector is requested steps d and after are repeated Figure 5 5 shows an example of WRITE SECTOR S command protocol 5 112 C141 E195 02EN 5 4 Command Protocol Command v DRQ lt gt Max 40 ms Data Reg Selection 7l pa ee Word 0 1 2 255 IOCS16 Figure 5 5 WRITE SECTOR S command protocol IMPORTANT For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer Note that the host does not need to read the Status register for the first and the last sector to be transferred If the timing to read the Status register does not meet above condition normal data transfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed C141 E195 02EN 5 113 Interface 5 4 3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device RECABLIBRATE SEEK READY VERIFY SECTOR S EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE SET MAX AD
116. gnal is negated according to timing at which the command is received When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal gt Master device Status Reg BSY bit Max 6 sec 4 1 If the slave device is preset PDIAG signal is checked for up to6 seconds Slave device BSY bit ES 6 6 gt 1 ms Max 5 sec 4 9 J 2 n T Figure 6 4 Response to diagnostic command C141 E195 02EN 6 2 Power Save 6 2 Power Save The host can change the power consumption state of the device by issuing a power command to the device 6 2 1 Power save mode There are five types of power consumption state of the device including active mode where all circuits are active e Active mode e Active idle mode e Low power idle mode e Standby mode e Sleep mode The device enters the active idle mode by itself The device also enters the idle mode in the same way after power on sequence is completed The subsequent mode transition changes depending on the APM setting 1 Active mode In this mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions The media access system is received 2 Active idle mode In this mode circuits on the device is set to power save mode The device en
117. he command register the correct device operation is not guaranteed 5 3 1 Command code and parameters Table 5 3 lists the supported commands command code and the registers that needed parameters are written 5 14 C141 E195 02EN 5 3 Host Commands Table 5 3 Command code and parameters 1 of 3 Command code Commandeode Bit Command name Be ee poscos fo fof SET MAX READ NATIVE MAX ADDRESS EXECUTE DEVICE DIAGNOSTIC READ LONG C141 E195 02EN Parameters used R N Y Z E xz zz E eee Interface Table 5 3 Command code and parameters 2 of 3 Command code Bit IDLE IMMEDIATE 111 110 0 1 STANDBY 1101011 111 1111110 011 STANDBY IMMEDIATE 1101011 1 1111110 0 SLEEP 1100011 111100 CHECK POWER MODE 1100110 0 11111101011 1 v v 1 1 SECURITY ERASE UNIT securmry eeezevoce ofr secumvserrsswon i muc 1 DEVICE CONFIGURATION SET MAX ADDRESS Es SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK IDENTIFY COMPONENT DEVICE CONFIGURATION DEVICE CONFIGURATION FREEZE LOCK Z Z Z Parameters used Command name 110 011 1
118. he data in transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 3 and 5 6 3 2 for specific timing requirements D 2 3 4 The device shall drive a data word onto DD 15 0 The device shall generate a DSTROBE edge to latch the new word no sooner than tpys after changing the state of DD 15 0 The device shall generate a DSTROBE edge no more frequently than tcyc for the selected Ultra DMA Mode The device shall not generate two rising or two falling DSTROBE edges more frequently than 2tcyc for the selected Ultra DMA mode The device shall not change the state of DD 15 0 until at least tpyg after generating a DSTROBE edge to latch the data The device shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first 5 5 3 3 Pausing an Ultra DMA data in burst 5 120 The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 4 and 5 6 3 2 for specific timing requirements a Device pausing an Ultra DMA data in burst 1 The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2 The device shall pause an Ultra DMA burst by not generating DSTROBE edges C141 E195 02EN b 3 5 5 Ultra DMA Feature Set NOTE The host shall not immediately assert STOP to initiate Ultra DM
119. he device clears the BSY bit and generates an interrupt C141 E195 02EN 5 47 Interface At command issuance I O registers setting contents 9 3 0 9 Dmes 1 5 1F4 CL XX 1F3y SN XX 1F24 SC Sector count block 1F1y FR XX After power on the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode At command completion I O registers contents to be read ips peIwIS 1F54 CH 1F4 CL XX 1F3y SN XX 1F24 SC Sector count block 1 15 Error information 16 SET MAX F9 SET MAX Features Register Values Value Command 00h Obsolete Olh SET MAX SET PASSWORD 02h SET MAX LOCK 03h SET MAX UNLOCK 04h SET MAX FREEZE LOCK 058 FFh Reserved e SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command 5 48 C141 E195 02EN 5 3 Host Commands This command allows the maximum address accessible by the user to be set in LBA or CHS mode Upon receipt of the command the device sets the BSY bit and saves the maximum address specified in the DH CH CL and SN registers Then it clears BSY and generates an interrupt The new address information set by this command is reflected in Words 1 54 57 58 60 and 61 of IDENTIFY DEVICE information If an attempt is made to perform a read or write operation for an address beyond th
120. he response to an IDENTIFY DEVICE command will reflect the reduced set of capabilities while the DEVICE CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities If the device has executed a previous DEVICE CONFIGURATION FREEZE LOCK command since power up an aborted error is posted e DEVICE CONFIGURATION SET FR C3h The DEVICE CONFIGURATION SET command allows to reduce the set of optional commands modes or feature sets supported by a device as indicated by a DEVICE CONFIGURATION IDENTIFY command The format of the overlay transmitted by the device is described in Table 5 18 As a result to the limitation of the function by the DEVICE CONFIGURATION SET command is reflected in IDENTIFY information When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit After execution of this command the settings are kept for the device power down or reset If the restriction of Multiword DMA modes or Ultra DMA modes is executed a SET FEATURES command should be issued for the modes restriction prior the DEVICE CONFIGURATION SET command is issued When the Automatic Acoustic Management function is assumed to be a unsupport Automatic Acoustic Management is prohibited beforehand by SET FEATURE
121. hecks the power mode of the device with this command The host system can confirm the power save mode of the device by the contents of the Sector Count register The device sets the BSY bit and sets the following register value After that the device clears the BSY bit and generates an interrupt Power save mode Sector Count register During moving to standby mode Standby mode X 00 At command issuance I O registers setting contents 1 7 X 98 or X ES ee 1 5 1F4 CL 1F3 SN 1 2 1 1 At command completion I O registers contents to be read mee a 1F54 CH 1F44 CL XX 1F3y SN XX 1F2y SC X 00 or X FF 1 15 Error information 5 66 C141 E195 02EN 5 3 Host Commands 29 SMART This command predicts the occurrence of device failures depending on the subcommand specified in the FR register If the FR register contains values that are not supported with the command the Aborted Command error is issued Before issuing the command the host must set the key values in the CL and CH registers 4Fh in the CL register C2h in the CH register If the key values are incorrect the Aborted Command error is issued If the failure prediction function is disabled the device returns the Aborted Command error to subcommands other than those of the SMART Enable Operations with the FR register set to D8h
122. hen device has received this command The APS timer allows the device to change to the standby mode automatically after specified period When the device enters the Waiting Host Command Mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer restarts countdown after completion of the command execution The period of timer count is set depending on the value of the Sector Count register as shown below At command issuance I O registers setting contents 1 5 1F44 CL XX 1F34 SN XX 1F24 SC Period of timer 1F1 amp FR C141 E195 02EN 5 61 Interface At command completion I O registers contents to be read mee a 1 5 1F44 CL XX 1F3y SN XX 1F2 SC XX 1F1 CER Error information 24 IDLE IMMEDIATE X 95 or X E1 Upon receipt of this command the device sets the BSY bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the APS timer function At command issuance I O registers setting contents S x ove 1F5 CH 1F4 CL 1F34 SN 1F24 SC 1F1 4 FR At command completion I O registers contents to be read Des fs Ts Ts 1
123. hen the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operation whichever occurs first Refer to item 3 in Subsection 3 2 for the measurement point of the DE surface temperature Also the operating conditions except the environment temperature are based on the MTBF conditions 4 Data assurance in the event of power failure Except for the data block being written to the data on the disk media is assured in the event of any power supply abnormalities This does not include power supply abnormalities during disk media initialization formatting or processing of defects alternative block assignment 1 10 C141 E195 02EN 1 8 Error Rate 1 8 Error Rate Known defects for which alternative blocks can be assigned are not included in the error rate count below It is assumed that the data blocks to be accessed are evenly distributed on the disk media 1 Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user s retry and ECC corrections shall occur no more than 10 times when reading data of 10 bits Read retries are executed according to the disk drive s error recovery procedure and include read retries accompanying head offset operations 2 Positioning error Positioning seek errors that can be recovered by one retry shall occur no more than 10 times in 107 seek operations 1 9 Media Defects Defective sect
124. his manual Manual name MHT2080AH MHT2060AH MHT2040AH DISK DRIVES PRODUCT MANUAL Please mark each item E Excellent G Good F Fair P Poor Illustration Technical level Glossary Organization Acronyms amp Abbreviations General appearance Clarity Index Accuracy Comments amp Suggestions List any errors or suggestions for improvement Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 37 10 Nishikamata 7 chome Oota ku Tokyo 144 0051 JAPAN Fax 81 3 3730 3702 Organization Name C141 E195 02EN This page is intentionally left blank MHT2080AH MHT2060AH MHT2040AH DISK DRIVES PRODUCT MANUAL C THET ET9S 0 MHT2080AH MHT2060AH MHT2040AH A DISK DRIVES PRODUCT MANUAL This page is intentionally left blank co FUJITSU
125. hysical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command registers Data block A data block is the unit used to transfer data A data block normally indicates a single sector DE Disk enclosure The DE includes the disks built in spindle motor actuator heads and air filter The DE is sealed to protect these components from dust Master Device 0 The master is the first drive that can operate on the AT bus The master is daisy chained with the second drive which can operate in conformity with the ATA standard C141 E195 02EN GL 1 Glossary MTBF Mean time between failures The MTBF is calculated by dividing the total operation time total power on time by the number of failures in the disk drive during operation MTTR Mean time to repair The MTTR is the average time required for a service person to diagnose and repair a faulty drive PIO Programmed input output Mode to transfer data under control of the host CPU Positioning Sum of the seek time and mean rotational delay Power save mode The power save modes are idle mode standby mode and sleep mode In idle mode the drive is neither reading writing nor seeking data In standby mode the spindle motor is stopped and circuits other than the inter
126. icates low order 8 bits of the starting cylinder address for any disk access At the end of a command the contents of this register are updated to the current cylinder number Under the LBA mode this register indicates LBA bits 15 to 8 Under the LBA mode of the EXT system command LBA bits 39 to 32 are set in the first setting and LBA bits 15 to 8 are set in the second setting 7 Cylinder High register 1F5 The contents of this register indicates high order 8 bits of the disk access start cylinder address At the end of a command the contents of this register are updated to the current cylinder number The high order 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 Under the LBA mode of the EXT system command LBA bits 47 to 40 are set in the first setting and LBA bits 23 to 16 are set in the second setting 5 10 C141 E195 02EN 5 2 Logical Interface 8 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 a maximum head No Bit 7 Unused Bit6 0 for CHS mode 1 for LBA mode Bit5 Unused Bit 4 DEV bit 0 for the master device and 1 for the slave device 3 HS3 CHS mode head address 3 25 bit 27 for LBA mode Unuse
127. ied with 28 bit address information the Device Head Cylinder High Cylinder Low Sector Number registers C141 E195 02EN 5 7 Interface indicate LBA bits 27 to 24 bits 23 to 16 bits 15 to 8 and bits 7 to 0 respectively If the LBA mode is specified with 48 bit address information the Cylinder High Cylinder Low Sector Number registers are set twice In the first time the registers indicate LBA bits 47 to 40 bits 39 to 32 and bits 31 to 24 respectively In the second time the registers indicate LBA bits 23 to 16 bits 15 to 8 and bits 7 to 0 respectively 5 2 2 Command block registers 1 Data register X 1F0 The Data register is a 16 bit register for data block transfer between the device and the host system Data transfer mode is PIO or DMA mode 2 Error register X 1F1 The Error register indicates the status of the command executed by the device The contents of this register are valid when the ERR bit of the Status register is 1 This register contains a diagnostic code after power is turned on a reset or the EXECUTIVE DEVICE DIAGNOSTIC command is executed Status at the completion of command execution other than diagnostic command X Unused Bit7 Interface CRC Error ICRC This bit indicates that a CRC error occurred during Ultra DMA transfer Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit4 ID
128. ine Subassemblies Circuit Configuration Power on Sequence Self calibration Read write Circuit Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks C141 E195 02EN 4 1 Theory of Device Operation 4 1 Outline This chapter consists of two parts First part Section 4 2 explains mechanical assemblies of the disk drive Second part Sections 4 3 through 4 7 explains a servo information recorded in the disk drive and drive control method 4 2 Subassemblies 4 2 1 Disk The disk drive consists of a disk enclosure DE and printed circuit assembly PCA The DE contains all movable parts in the disk drive including the disk spindle actuator read write head and air filter For details see Subsections 4 2 1 to 4 2 4 The contains the control circuits for the disk drive The disk drive has one PCA For details see Sections 4 3 The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm Servo data is recorded on each cylinder total 124 Servo data written at factory is read out by the read head For servo data see Section 4 7 4 2 2 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 5 400 rpm 1
129. information the IDD uses the two phase servo generated from the gray code and servo to D This servo information is used for positioning operation of radius direction and position detection of circumstance direction The servo frame consists of 6 blocks write read recovery servo mark gray code servo to D and PAD Figure 4 8 shows the servo frame format Write read recovery Servo mark Servo B Servo A Gray code PAD Figure 4 8 Servo frame format 1 Write read recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark This area generates a timing for demodulating the gray code and position demodulating the servo A to D by detecting the servo mark 3 Gray code including sector address bits This area is used as cylinder address The data in this area is converted into the binary data by the gray code demodulation circuit 4 Servo A servo B servo C servo D This area is used as position signals between tracks and the IDD control at on track so that servo A level equals to servo B level 5 PAD This area is used as a gap between servo and data 4 16 C141 E195 02EN 4 7 Servo Control 4 7 4 Actuator motor control The voice coil motor VCM is controlled by feeding back the servo data recorded on the data surface The MPU fetches the position sense data on the servo frame at a constant interval of sampling tim
130. it is 1 the contents of the Status register are posted This bit is set by the device under following conditions a Within 400 ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is set for no longer than 15 seconds after the IDD accepts reset b Within 400 ns from the host system starts writing to the Command register c Within 5 us following transfer of 512 bytes data during execution of the READ SECTOR S WRITE SECTOR S or WRITE BUFFER command Within 5 us following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ LONG or WRITE LONG command Device Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of the spindle motor reaches the steady speed The Device Write Fault DF bit This bit indicates that a device fault write fault condition has been detected If a write fault is detected during command execution this bit is latched and retained until the device accepts the next command or reset Device Seek Complete DSC bit This bit indicates that the device heads are positioned over a track In the IDD this bit i
131. itation of mounting Note These dimensions are recommended values if it is not possible to satisfy them contact us 2 5 Side surface _ 25 mounting 2 5 Pa iA Frame of system cabinet hs Bottom surface mounting 2 5 3 0 or less SES Screw 3 0 or less Screw Details of A Details of B Figure 3 3 Mounting frame structure 3 4 C141 E195 02EN C141 E195 02EN MADE IN THAILAND IMPORTANT Locating of breather hole is shown as Figure 3 4 Fufirsu MODEL m PART NO 06311 048 SER DATE 200X XX TO TEE RET HI RATING 5V 0 60A REV 0 0123456789 80 0GB LBA XXXXXXXX 5 248 25 tanner m E z 010 WARRANTY IF SEAL 00 PUSH ON THE TOF COVER ARD PCB AYOID EXCESSIY E SHOCK WRATTLE NOISE IS m WHEN HANDLED s lt JUMPER gt DEVICEO DEVICE CABLE SEL o ee o 93 Figure 3 4 Location of breather 3 2 Mounting Because of breather hole mounted to the HDD do not allow this to close during mounting For breather hole of Figure 3 4 at least do not allow its around 2 4 to block 3 5 Installation Conditions 4 Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive The ambient te
132. ite to the device register or data port DIOW must be negated by the host before starting the Ultra DMA transfer The STOP signal must be negated by the host before data is transferred during the Ultra DMA transfer During data transfer in Ultra DMA mode the assertion of the STOP signal asserted by the host later indicates that the transfer has been suspended Read strobe signal from the host to read the device register or data port Flow control signal for Ultra DMA data In transfer READ DMA command This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer The host can negate the signal to suspend the Ultra DMA data In transfer Data Out Strobe signal from the host during Ultra DMA data Out transfer WRITE DMA command Both the rising and falling edges of the HSTROBE signal latch data from Data 15 0 into the device The host can suspend the inversion of the HSTROBE signal to suspend the Ultra DMA data Out transfer Interrupt signal to the host This signal is negated in the following cases assertion of RESET signal Reset SRST of the Device Control register Write to the command register by the host Read of the status register by the host Completion of sector data transfer without reading the Status register The signal output line has a high impedance when no devices are selected or interruption is disabled C141 E195 02EN sig
133. ith a desired data pattern by issuing this command Upon receipt of this command the device sets the BSY bit of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the buffer then generates an interrupt At command issuance I O registers setting contents 1F74 CM 1 1 5 1FA CL 1F3 SN 1 2 1 1 At command completion I O registers contents to be read i Ts Ts ove 1 5 1F4 CL 1F34 SN 1 2 1F1 ER 5 60 XX XX XX Error information C141 E195 02EN 5 3 Host Commands 23 IDLE X 97 or Upon receipt of this command the device sets the BSY bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt The device generates interrupt even if the device has not fully entered the idle mode If the spindle of the device is already rotating the spin up sequence shall not be implemented By using this command the APS Automatic Power Standby timer function is enabled and the timer immediately starts the countdown When the timer reaches the specified value the device enters standby mode The APS timer is set to prohibition if the Sector Count register s value was 00h w
134. itiate termination of an Ultra DMA burst by not generating DSTROBE edges 2 The device shall negate DMARQ no sooner than tss after generating the last DSTROBE edge The device shall not assert DMARQ again until after the Ultra DMA burst is terminated 3 The device shall release DD 15 0 no later than t4z after negating DMARQ 4 The host shall assert STOP within tj after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 5 The host shall negate HDMARDY within t after the device has negated DMARQ The host shall continue to negate HDMARDY until the Ultra DMA burst is terminated Steps 4 and 5 may occur at the same time 5 121 Interface 5 122 b 6 7 8 9 10 11 12 13 14 The host shall drive DD 15 0 no sooner than after the device has negated DMARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 If DSTROBE is negated the device shall assert DSTROBE within tj after the host has asserted STOP No data shall be transferred during this assertion The host shall ignore this transition on DSTROBE DSTROBE shall remain asserted until the Ultra DMA burst is terminated If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 6 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5
135. itiation phase the data transfer phase and the Ultra DMA burst termination phase In addition an Ultra DMA burst may be paused during the data transfer phase see 5 5 3 and 5 5 4 for the detailed protocol descriptions for each of these phases 5 6 defines the specific timing requirements In the following rules DMARDY is used in cases that could apply to either DDMARDY or and STROBE is used in cases that could apply to either DSTROBE or HSTROBE The following are general Ultra DMA rules a AnUltra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b Arecipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst 5 5 3 Ultra DMA data in commands 5 5 3 1 Initiating an Ultra DMA data in burst C141 E195 02EN The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 1 and 5 6 3 2 for specific timing requirements 1 The host shall keep DMACK in the negated state before an Ultra DMA burst 15 initiated 2 The device shall assert DMARQ to initiate an Ultra DMA burst After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE 3 Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP 4 The host shall negate HDMARDY 5 The host shall negate CSO CS1 DA2 DAI and DA
136. k refer to the previous edition when those were deleted C141 E195 02EN This page is intentionally left blank Preface This manual describes about MHT2080AH MHT2060AH MHT2040AH out of the disk drive 2 5 inch hard disk drives These drives have a built in controller that is compatible with the ATA interface This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems This manual consists of seven chapters and sections explaining the special terminology and abbreviations used in this manual Overview of Manual CHAPTER 1 Device Overview This chapter gives an overview of the disk drive and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the disk drive and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the disk drive CHAPTER 4 Theory of Device Operation This chapter describes the operation theory of the disk drive CHAPTER 5 Interface This chapter describes the interface specifications of the disk drive CHAPTER 6 Operations This chapter describes the operations of the disk drive Glossary The glossary describes the
137. m the host with the Write Cache enable command is not completely written on disk media before the normal end interrupt is issued If an unrecoverable error occurs while multiple commands that are targets of write caching are received the host has difficulty determining which command caused the error An error report is not issued to the host if automatic alternating processing for the error is performed normally Therefore the host cannot execute a retry for the unrecoverable error while Write Cache is enabled Be very careful on this point when using this function If a write error occurs an abort response is sent to all subsequent commands C141 E195 02EN Glossary Actuator Head positioning assembly The actuator consists of a voice coil motor and head arm If positions the read write R W head AT bus bus between the host CPU and adapter board ATA AT Attachment standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors Interfaces based on this standard are called ATA interfaces BIOS standard for drives The BIOS standard collectively refers to the parameters defined by the host which for example include the number of cylinders the number of heads and the number of sectors per track in the drive The physical specifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the p
138. mand The device does not generate interrupts assertion of the INTRQ signal on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command The DRQ bit of the Status register is required to set only at the start of the data block not on each sector The number of sectors per block is defined by a successful SET MULTIPLE MODE command The SET MULTIPLE MODE command should be executed prior to the WRITE MULTIPLE command If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block If an error occurs the subsequent block shall not be transferred Interrupts are generated when the DRQ bit of the Status register is set at the
139. minating an Ultra DMA data in burst 5 138 5 6 3 6 Host terminating an Ultra DMA data in 5 139 5 6 3 7 Initiating an Ultra DMA data out burst sese 5 140 5 6 3 8 Sustained Ultra DMA data out burst sene 5 141 5 6 3 9 Device pausing an Ultra DMA data out burst 5 142 5 6 3 10 Host terminating an Ultra DMA data out burst 5 143 5 6 3 11 Device terminating an Ultra DMA data out burst 5 144 5 6 4 Power on and reset i sce eee ee ans tate gence 5 145 i9 e li oTi rer 6 1 6 1 Device Response to the Reset essere rennen 6 2 6 1 1 Response to power on 6 2 6 1 2 Response to hardware reset sess 6 3 6 1 3 Response to software reset sess rennen 6 5 6 1 4 Response to diagnostic command esee 6 6 C141 E195 02EN Contents 6 2 Power secs sq bee aee 6 7 6 2 1 Powersayve mode xen oe e e edocs 6 7 6 2 2 Power commands iere ep tret 6 9 6 3 Defect PfoCessimg e Dette Ule ete e Legit eet tee 6 9 6 3 1 Spare area cucciolo E e ede 6 9 6 3 2 Alternating processing for defective sectors sees 6 10 6 4 JRead ahead Cache ecrit nette t eee tees 6 12 6 4 1 DATA buffer 6 12 6 4 2 Caching operation
140. mperature must satisfy the temperature conditions described in Section 1 4 and the airflow must be considered to prevent the DE surface temperature from exceeding 60 C Provide air circulation in the cabinet such that the side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure 3 5 Surface temperature measurement points Table 3 1 Surface temperature measurement points and standard values Measurement point 3 6 C141 E195 02EN 3 2 Mounting 5 Service area Figure 3 6 shows how the drive must be accessed service areas during and after installation Mounting screw hole Mounting screw hole Figure 3 6 Service area A CAUTION Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 KQ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling cautions Please keep the following cau
141. n I O registers contents to be read Deme fs Ts Ts ove 1F5 CH 1F4 CL 1F3 SN 1 2 1F1 ER Note XX XX XX Error information Also executable in LBA mode 10 SEEK X70 to X7F This command performs a seek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt In the LBA mode this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address 5 30 C141 E195 02EN 5 3 Host Commands At command issuance I O registers setting contents x 1 ov hano 1F5 CH Cylinder No MSB LBA 1F4 CL Cylinder No LSB LBA 1 Sector No LBA LSB 1F2 SC IFly FR xx At command completion I O registers contents to be read 1F6 DH Head No LBA MSB 1 5 Cylinder No MSB LBA 1 4 Cylinder No LSB LBA 1F3y SN Sector No LBA LSB 1F24 SC XX 1 15 Error information 11 INITIALIZE DEVICE PARAMETERS X 91 The host system can set the number of sectors per track and the maximum head number maximum head number is number of heads minus 1 per cylinder with this command Upon receipt of this command the device sets the BSY bit of Stat
142. nal CS0 CS1 DA 0 2 KEY PDIAG CBLID DASP IORDY DDMARDY DSTROBE CSEL DMACK C141 E195 02EN I O I O I O 5 1 Physical Interface Description Chip select signal decoded from the host address bus This signal is used by the host to select the command block registers Chip select signal decoded from the host address bus This signal is used by the host to select the control block registers Binary decoded address signals asserted by the host to access task file registers Key pin for prevention of erroneous connector insertion This signal is an input mode for the master device and an output mode for the slave device in a daisy chain configuration This signal indicates that the slave device has been completed self diagnostics This signal is pulled up to 5 V through 10 kQ resistor at each device This signal is used to detect the type of cable installed in the system This signal is pulled up to 5 V through 10 kQ resistor at each device This is a time multiplexed signal that indicates that the device is active and a slave device is present This signal is pulled up to 5 V through 10 kQ resistor at each device This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system Flow control signal for Ultra DMA data Out transfer WRITE DMA command This signal is asserted by the device t
143. nce I O registers setting contents 1 ro 3 1 5 1F4 CL 1F3 SN 1 2 1F14 FR XX XX 1 3 See Table 5 5 At command completion I O registers contents to be read Deme fs Ts Ts 1F5 CH 1F4 CL 1F3 SN 1 2 1 XX XX XX Error information Data Transfer Mode The host sets X 03 to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error is posted PIO default transfer mode PIO flow control transfer mode X 00001 000 X 08 C141 E195 02EN 00001 001 X 09 00001 010 X 0A 00001 011 X OB 00001 100 X OC 00000 000 X 00 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 5 45 Interface Multiword DMA transfer mode X 00100 000 X 20 Mode 0 00100 001 X 21 Mode 1 00100 010 X 22 Mode 2 Ultra DMA transfer mode X 01000 000 X 40 Mode 0 01000 001 X 41 Mode 1 01000 010 X 42 Mode 2 01000 011 X 43 Mode 3 01000 100 X 44 Mode 4 01000 101 X45 Mode 5 2 Advanced Power Management 5 46 Th
144. nd the spindle motor are submitted to servo control The actuator motor is controlled for moving and positioning the head to the track containing the desired data To turn the disk at a constant velocity the actuator motor is controlled according to the servo data that is written on the data side beforehand 4 7 1 Servo control circuit Figure 4 6 is the block diagram of the servo control circuit The following describes the functions of the blocks 1 Servo burst capture VCM current Position Sense Spindle motor CSR Current Sense Resister control VCM Voice Coil Motor Figure 4 6 Block diagram of servo control circuit 4 12 C141 E195 02EN 4 7 Servo Control 1 Microprocessor unit MPU The MPU executes startup of the spindle motor movement to the reference cylinder seek to the specified cylinder and calibration operations Main internal operation of the MPU are shown below The major internal operations are listed below a Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied b Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 c Seekto specified cylinder Drives the VCM to position the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical for
145. negation until CRC may become invalid 3 Time from STROBE output released to driving until the first transition of critical timing Time from data output released to driving until the first transition of critical timing 230 200 170 130 120 90 First STROBE time for device to first negate DSTROBE from STOP during a data in burst C141 E195 02EN 5 133 Interface Table 5 23 Ultra DMA data burst timing requirements 2 of 2 in ns in ns in ns in ns in ns in ns eee M pep xp ep le pep eee m LI uu B A A Maximum time allowed for output drivers to release from asserted or negated Minimum delay time required for output Drivers to assert or negate from released tENV Envelope time from DMACK to STOP and HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation tres Ready to final STROBE time no STROBE edges shall be sent this long after negation of DMARDY Ready to pause time that recipient shall wait to pause after negating DMARDY 20 20 time before releasing Minimum time before driving IORDY 4 Setup and hold times for DMACK before assertion or negation Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst Except for some instances of tyr that apply to host signals only the parameters tur and indicate sender to recipient or recipient
146. nerated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and timing for the host The device shall negate DMARQ no sooner than tgp after negating DDMARDY The device shall not assert DMARQ again until after the Ultra DMA burst is terminated The host shall assert STOP with t after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated If HSTROBE is negated the host shall assert HSTROBE with t after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition of HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than tmu after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY and no sooner than tpys after placing the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that o
147. nfiguration C141 E195 02EN 2 3 Device Configuration 2 2 3 2 drives connection Note Host interface MHT2080AH MHT2060AH MHT2040AH HA Host adaptor AT bus MHT2080AH MHT2060AH MHT2040AH ATA interface When the drive that is not conformed to ATA 1 connected to the disk drive above configuration the operation is not guaranteed 2 4 Figure 2 3 2 drives configuration IMPORTANT HA host adaptor consists of address decoder driver and receiver is an abbreviation of attachment The disk drive is conformed to the ATA 6 interface At high speed data transfer PIO mode 4 or DMA mode 2 U DMA mode 5 occurrence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the Obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 6 standard and the cable length between the HA and the disk drive should be as short as possible No need to push the top cover of the disk drive If the over power worked the cover could be contacted with the spindle motor Thus that could be made it the cause of failure C141 E195 02EN CHAPTER 3 Installation Conditions 3 1 3 2 3 3 3 4 Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions installation conditions s
148. ng during writing onto media is created when the next command is issued Where the command reporting the error status is not executed only the error status is reported Only the status of an error that occurs during write processing is reported Exceptions The error status is not reported in the following case The reset command is received after an error has occurred during writing to media e Reset processing is performed as usual The error status that has occurred during writing to media is not reported 4 Enabling and disabling Enabling and disabling of the Write Cache function can be set only with the SET FEATURES command The setting does not changed even when the error status 15 reported The initial setting is stored in the system area of media System area information is loaded whenever the power is turned on 5 Reset response When a reset 1s received while cached data is stored on the data buffer data of the data buffer is written on the media and reset processing is then performed This 15 true for both a hard reset and soft reset 6 Cashing function when power supply is turned on 6 20 The cashing function is invalid until Calibration is done after the power supply is turned on about 10 sec It is effective in Default after that as long as the cashing function is not invalidly set by the SET FEATURES command IMPORTANT If Write Cache is enabled there is a possibility that data transferred fro
149. ntents 1F6 DH Tey Start head No LBA MSB 1 5 Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA 1F34 SN Start sector No LBA LSB 1F24 SC Transfer sector count 1FI amp FR XX R Retry At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1F54 CH End cylinder No MSB LBA 1F4 CL End cylinder No LSB LBA 1F3y SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 2 READ MULTIPLE X C4 5 20 The READ MULTIPLE Command performs the same as the READ SECTOR S Command except that when the device is ready to transfer data for a block of sectors and enters the interrupt pending state only before the data transfer for the first sector of the block sectors In the READ MULTIPLE command operation the DRQ bit of the Status register is set only at the start of the data block and is not set on each sector The number of sectors per block is defined by a successful SET MULTIPLE MODE Command The SET MULTIPLE MODE command should be executed prior to the READ MULTIPLE command If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The
150. o inform the host that the device is ready to receive the Ultra DMA data Out transfer The device can negate the DDMARD Y signal to suspend the Ultra DMA data Out transfer Data In Strobe signal from the device during Ultra DMA data In transfer Both the rising and falling edges of the DSTROBE signal latch data from Data 15 0 into the host The device can suspend the inversion of the DSTROBE signal to suspend the Ultra DMA data In transfer This signal to configure the device as a master or a slave device When CSEL signal is grounded the IDD is a master device When CSEL signal is open the IDD is a slave device This signal is pulled up with 240 resistor at each device The host system asserts this signal as a response that the host system receive data or to indicate that data is valid 5 5 Interface signal Description DMARQ This signal is used for transfer between the host system the device The device asserts this signal when the device completes the preparation of DMA data transfer to the host system at reading or from the host system at writing The direction of data transfer is controlled by the DIOR and DIOW signals This signal hand shakes with the DMACK signal In other words the device negates the DMARQ signal after the host system asserts the DMACK signal When there is other data to be transferred the device asserts the DMARQ signal again When the DMA data transfer is perfo
151. ode shifts from Active condition to Active Idle in 0 2 1 2 seconds and to Low Power Idle in 10 0 40 0 seconds Mode shifts from Active condition to Active Idle in 0 2 1 2 seconds and to Low Power Idle in 10 0 40 0 seconds After 10 0 40 0 seconds in Low Power Idle the mode shifts to standby 1 13 This page is intentionally left blank CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate C141 E195 02EN 2 1 Device Configuration 2 1 Device Configuration 1 Disk 2 Head Figure 2 1 shows the disk drive The disk drive consists of a disk enclosure DE read write preamplifier and controller PCA The disk enclosure contains the disk media heads spindle motors actuators and a circulating air filter Disk drive Figure 2 1 Disk drive outerview The outer diameter of the disk is 65 mm The inner diameter is 20 mm The heads are of the load unload L UL type The head unloads the disk out of while the disk is not rotating and loads on the disk when the disk starts 3 Spindle motor 4 Actuator The disks are rotated by a direct drive Sensor less DC motor The actuator uses a revolving voice coil motor structure which consumes low power and generates very little heat The head assembly at th
152. of self calibration Self calibration is performed once when power is turned After that the disk drive does not perform self calibration until it detects an error That is self calibration is performed each time one of the following events occur e When it passes from the power on for ten seconds and the disk drive shifts to Active Idle mode The number of retries to write or seek data reaches the specified value e The error rate of data reading writing or seeking becomes lower than the specified value 4 5 3 Command processing during self calibration 4 8 This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 72 ms When the error rate of data reading writing or seeking becomes lower than the specified value self calibration is performed to maintain disk drive stability If the disk drive receives a command execution request from the host while performing self calibration it stops the self calibration and starts to execute the command In other words if a disk read or write service is necessary the disk drive positions the head to the track requested by the host reads or writes data and then restarts calibration after 10 seconds If the error rate recovers to a value exceeding the specified value self calibration is not performed C141 E195 02EN 4 6 Read write Circuit 4 6 Re
153. om data valid until STROBE edge 1 tpuic 4 8 4 8 4 8 4 8 4 8 2 8 Recipient IC data hold time from STROBE edge until data may become invalid 1 tpvsic 72 9 50 9 33 9 22 6 9 5 Sender IC data valid setup time from data valid until STROBE edge 2 tpvuic Sender IC data valid hold time from STROBE edge until data may become invalid 2 The correct data value shall be captured by the recipient given input data with a slew rate of 0 4 V ns rising and falling and the input STROBE with a slew rate of 0 4 V ns rising and falling at tpsic and tpuic timing as measured through 1 5V The parameters tpvsic and tpvuric shall be met for lumped capacitive loads of 15 and 40 pf at the IC where all signals have the same capacitive load value Noise that may couple onto the output signals from external sources in a normally functioning system has not been included in these values Note timing measurement switching points low to high and high to low shall be taken at 1 5V C141 E195 02EN 5 135 Interface 5 6 3 3 Sustained Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra Modes DSTROBE at device DD 15 0 at device DSTROB at host tpH tps DD 15 0 tonic tosic at host OOE E T KKK XK Note DD 15 0 and DSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the
154. ommand that are targets of caching The Commands that are targets of caching are as follows e Write Sector s Write Multiple Write DMA e Write Sector s EXT e Write Multiple EXT e Write DMA EXT However the caching operation is not performed when the caching function is prohibited by the SET FEATURES command 2 Invalidation of cached data If an error occurs during writing onto media write processing is repeated up to as many times as specified for retry processing If retry fails for a sector because the retry limit is reached automatic alternate sector processing is executed for the sector If the automatic alternate sector processing fails the data in the sector for which automatic alternate sector processing failed is invalidated without being guaranteed If data remains in sectors following a sector for which automatic alternate sector processing failed the data is invalidated without being guaranteed Moreover when the command clause 6 4 2 3 is accepted and HOST CRC Error is generated the cashing data is invalidated lt Exception gt e Ifa Reset or command is received while a transfer of one sector of data is in progress data is not written in the sector of the media where the interruption occurred and sectors accepted before interruption occurred is written in the medium C141 E195 02EN 6 19 Operations 3 Status report in the event of an error The status report concerning an error occurri
155. ompares the user password or master password in the transferred data with the user password or master password already set and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error The section about the SECURITY FREEZE LOCK command describes LOCKED MODE and FROZEN MODE 5 82 C141 E195 02EN 5 3 Host Commands Table 5 15 Contents of security password Control word Bit 0 Identifier 0 Compares the user passwords 1 Compares the master passwords Bits 1 to 15 Reserved Password 32 bytes At command issuance I O register contents 1F7 CM 1F6 DH 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 FR 1 1 0 1 1 0 XX XX XX XX XX At command completion I O register contents FS 1F6 DH 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 ER C141 E195 02EN XX XX XX XX Error information 5 83 Interface 31 SECURITY ERASE PREPARE F3h The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command The SECURI
156. on 4 6 3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control AGC circuit Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit This clock signal is converted into the NRZ data by the ENDEC circuit based on the read data maximum likelihood detected by the Viterbi detection circuit then is sent to the HDC 1 AGC circuit The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off frequency of the low pass filter and boost up gain are controlled from the register in read channel by an instruction of the serial data signal from MPU M5 The MPU optimizes the cut off frequency and boost up gain according to the transfer frequency of each zone Figure 4 5 shows the frequency characteristic sample of the programmable filter Gain D dB 20 15 F Fb control Boost volume 3 dB 0 Fc control 1 2 3 4 5 10 20 30 40 50 100 F
157. ors are replaced with alternates when the disk are formatted prior to shipment from the factory low level format Thus the hosts see a defect free devices Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors 1 10Load Unload Function The Load Unload function is a mechanism that loads the head on the disk and unloads the head from the disk The product supports a minimum of 300 000 normal Load Unload cycles Normal Unload is a normal head unloading operation and the commands listed below are executed Reset e Standby e Standby immediate e Sleep Idle Emergency Unload other than Normal Unload is performed when the power is shut down while the heads are still loaded on the disk The product supports the Emergency Unload a minimum of 20 000 times When the power is shut down the controlled Normal Unload cannot be executed Therefore the number of Emergency other than Normal Unload is specified C141 E195 02EN 1 11 Device Overview Remark We recommend cutting the power supply of the HDD for this device after the Head Unload operation completes The recommended power supply cutting sequence for this device is as follows 1 Disk Flush Flush Cache command execution 2 Head Unload Standby Immediate command execution 3 Wait Status Checking whether bit 7 of the status register was set to 0 wait to complete STANDBY IMMEDI
158. ors that are valid for each command Table 5 21 Command code and parameters 1 of 2 Geoscos v vl v eanne v weren Dew va v v v weoma ve y weve y eao verrsecrono v v v ecas ux v v v_ wwevowwg Dwemevoew E lt lt lt lt lt lt lt lt lt lt 41 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Ierwxauss v READ NATIVEMAX ADDRESS __ __ mano mmo v E lt lt lt lt lt lt lt lt wem V Valid on this command lt lt lt lt lt lt lt lt lt lt See the command descriptions 2 Valid only for Ultra DMA command C141 E195 02EN 5 107 Interface Table 5 21 Command code and parameters 2 of 2 Command name Error register X IF1 Status register X 1F7 um l O Iscumossmrmswo _ v v v v summer
159. orted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURITY ERASE UNIT command causes the Aborted Command error until the device is turned off and then on or until a hardware reset is executed Issuing this command with LOCKED MODE canceled in UNLOCK has no affect on the UNLOCK counter Issuing this command in FROZEN MODE returns the Aborted Command error At command issuance I O register contents ue 1 1 1 9 9 1 9 mem Ts sTw w 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 FR C141 E195 02EN 5 89 Interface At command completion I O register contents Dee pepe 1 5 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information 36 FLUSH CACHE E7 This command is used to order to write every write cache data stored by the device into the medium BSY bit is held at 1 until every data has been written normally or an error has occurred The device performs every error recovery so that the data are read correctly When executing this command the reading of the data may take several seconds if much data are to be read In case a non recoverable error has occurred while the data is being read the error generation address is put into the command block register before ending the command Thi
160. pecified password is saved as a new user password User Maxi The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password only The master password already set cannot cancel LOCKED MODE Master Maximum The specified password is saved as a new master password The lock function is not enabled 5 88 At command issuance I O register contents XX 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 FR XX XX XX XX At command completion I O register contents 1F6 DH 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 ER XX XX XX XX Error information C141 E195 02EN 5 3 Host Commands 35 SECURITY UNLOCK This command cancels LOCKED MODE The host transfers the 512 byte data shown in Table 5 15 to the device Operation of the device varies as follows depending on whether the host specifies the master password e When the master password is selected When the security level is LOCKED MODE is high the password is compared with the master password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the security level in LOCKED MODE is set to the highest level the Aborted Command error is always returned e When the user password is selected The password is compared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Ab
161. perty may occur if the user does not perform the procedure correctly Normal Operation Data corruption Avoid mounting the disk near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 or greater Do not touch the printed circuit board but hold it by the edges C141 E195 02EN This page is intentionally left blank Manual Organization MHT2080AH MHT2060AH Maintenance and Diagnosis MHT2040AH Removal and Replacement Procedure DISK DRIVES MAINTENANCE MANUAL C141 F065 C141 E195 02EN vii This page is intentionally left blank Contents CHAPTER 1 Device OvervieW soie irri paco 1 1 1 Beatures ze RI e e e t Re eoe 1 2 1 1 1 Functions and 1 2 1 12 Adaptability epe HI Ret Rn 1 2 t re eU a cub ie d 1 3 1 2 Device Specifications a i eee iste HE npe cob eee 1 4 1 2 1 Specifications summary tionen 1 4 1 2 2 Model and product number esee 1 5 1 3 Power Requirements hee E 1 5 1 4 En
162. r on reset is performed a host can issue the SET MAX ADDRESS EXT command only once if the VV bitis 1 If the SET MAX ADDRESS EXT command is issued twice or more an ID Not Found error occurs When the SET MAX ADDRESS EXT command is executed all SET MAX ADDRESS commands are aborted The address value returns to the origin when the SET MAX ADDRESS EXT command is executed using the address value returned by the READ NATIVE MAX ADDRESS command Error reporting conditions This command is issued twice or more in an operation sequence ST 51h ER 10h ID Not Found The READ NATIVE MAX ADDRESS EXT command 27h is not issued immediately before this command ST 51h ER 04h Aborted 1s issued This command is issued while LBA 0 ST 51h ER 04h Aborted The SET MAX ADDRESS command has already been issued C141 E195 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F5 CH P SET MAX LBA 47 40 1F5 CH C SET MAX LBA 23 16 1F4 CL P SET MAX LBA 39 32 1F4 CL SET MAX LBA 15 8 IF3 SGN P SET MAX LBA 31 24 1F3 SN C SET MAX LBA 7 0 IF1 FR P xx 1F1 FR xx C Current P Previous 1F5 CH 1 SET MAX LBA 47 40 1F5 CH 0 SET MAX LBA 23 16 1F4 CL 1 SET MAX LBA 39 32 1F4 CL 0 SET MAX LBA 15 8 1F3 SN 1 SET MAX LBA 31 24 1F3 SN 0 SET MAX LBA 7 0 1F2 SC 1 xx 1F2 SC O xx 1F1 ER Error information
163. r subsequence READ command At command issuance I O registers setting contents 87 0 1 1 0 0 1 R 1F6 DH Head No LBA MSB 1F5y CH Cylinder No MSB LBA 1F4 CL Cylinder No LSB LBA IF34 SN Sector No LBA LSB 1F2 SC 01 IFly FR xx At command completion I O registers contents to be read 1F6 DH Head No LBA MSB 1 5 Cylinder No MSB LBA 1F4 CL Cylinder No LSB LBA 1F3y SN Sector No LBA LSB 1F2y SC XX 1 15 Error information C141 E195 02EN 21 READ BUFFER X E4 5 3 Host Commands The host system can read the current contents of the data buffer of the device by issuing this command Upon receipt of this command the device sets the BSY bit of Status register and sets up for a read operation Then the device sets the DRQ bit of Status register clears the BSY bit and generates an interrupt After that the host system can read up to 512 bytes of data from the buffer At command issuance I O registers setting contents 1F74 CM Dmes 1 5 1F4 CL 1F34 SN 1 2 1F14 FR At command completion I O registers contents to be read fs Ts Ts IS 1F5 CH 1F4 CL 1F3 SN 1 2 1F1 ER C141 E195 02EN XX XX XX Error information 5 59 Interface 22 WRITE BUFFER 8 The host system can overwrite the contents of the data buffer of the device w
164. r value 1 Standby timer value of the device is the smallest value 6 Word 51 PIO data transfer mode 15 8 PIO data transfer mode X 02 zPIO mode 2 Bit 7 0 Undefined 7 Word 53 Enable disable setting of word 54 58 and 64 70 15 3 Reserved Bit 2 1 Enable the word 88 Bit 1 1 Enable the word 64 70 Bit 0 1 Enable the word 54 58 8 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bit 15 9 Reserved Bit 8 Enable the multiple sector transfer Bit 7 0 Transfer sector count currently set by READ WRITE MULTIPLE command without interrupt supports 2 4 8 and 16 sectors 9 Word 63 Multiword DMA transfer mode Bit 15 11 Reserved Bit 10 multiword DMA mode 2 is selected Bit 9 multiword DMA mode 1 is selected Bit 8 multiword DMA mode 0 is selected Bit 7 3 Reserved Bit 2 1 Multiword DMA mode 2 1 and 0 supported Bit 1 0 1 Bit 1 1 Multiword DMA mode 1 and 0 supported Bit 0 1 Bit 0 1 Mode 0 10 Word 64 Advance PIO transfer mode support status Bit 15 8 Reserved C141 E195 02EN 5 37 Interface 5 38 Bit 7 0 Bit 1 Bit 0 11 WORD 80 Bit 15 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 12 WORD 82 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 13 WORD 83 Bits 15 14 Advance PIO transfer mode Mode 4 Mode 3 Reserved 1
165. rates an interrupt At command issuance I O registers setting contents 1F74 CM 1 1 1 1 1 0 0 0 1 5 1F4 CL xx 1F3 SN IF2 SC xx IF1y FR xx 5 54 C141 E195 02EN 5 3 Host Commands At command completion I O registers contents to be read 1F6 DH Max head LBA MSB 1 5 Max cylinder MSB Max LBA 1F4 CL Max cylinder LSB Max LBA 1F34 SN Max sector Max LBA LSB 1 2 1 15 Error information 18 EXECUTE DEVICE DIAGNOSTIC 90 This command performs an internal diagnostic test self diagnosis of the device This command usually sets the DRV bit of the Drive Head register is to 0 however the DV bit is not checked If two devices are present both devices execute self diagnosis If device 1 is present e Both devices shall execute self diagnosis The device 0 waits for up to 6 seconds until device 1 asserts the PDIAG signal If the device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own diagnostic status device 0 clears the BSY bit of the Status register and generates an interrupt The device 1 does not generate an interrupt e diagnostic status of the device 0 is read by the host system When a diagnostic failure of the device 1 is detected the host system can read a status of the device 1 by setting the DV bit selecting the device 1 When device
166. reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal devices and household appliances This product is not intended for special uses atomic controls aeronautic or space systems mass transport vehicle operating controls medical devices for life support or weapons firing controls where particularly high reliability requirements exist where the pertinent levels of safety are not guaranteed or where a failure or operational error could threaten a life or cause a physical injury hereafter referred to as mission critical use Customers considering the use of these products for mission critical applications must have safety assurance measures in place beforehand Moreover they are requested to consult our sales representative before embarking on such specialized use The contents of this manual may be revised without prior notice The contents of this manual shall not be disclosed in any way or reproduced in any media without the express written permission of Fujitsu Limited Rights Reserved Copyright FUJITSU LIMITED 2003 Revision History 1 1 oe Revised section 1 2 _ 1 2003 06 20 02 2003 10 28 Table 1 2 Altered Change of the order No Table 1 5 Altered Change of the acoustic noise specification Section s with asteris
167. rget of caching 6 13 6 19 D data target of caching 6 13 data buffer structure 6 12 data that is target of caching 6 13 data transfer multiword 5 131 PIO 5 130 Ultra DMA 5 132 defect processing 6 9 device pausing Ultra DMA data out burst 5 142 device response 6 2 to reset 6 2 device terminating Ultra DMA data in burst 5 138 5 144 out burst 5 144 E enabling and disabling 6 20 F fluctuation current 1 7 full hit 6 17 C141 E195 02EN H hit full 6 17 hit partial 6 18 hit sequential 6 16 host pausing Ultra DMA data in burst 5 137 host terminating Ultra DMA data in burst 5 139 out burst 5 143 initiating Ultra DMA data in burst 5 132 out burst 5 140 initiating Ultra DMA data in burst 5 132 out burst 5 140 invalidating caching target data 6 13 invalidating caching target data 6 13 invalidation of cached data 6 19 L low power idle mode 6 7 mean time mean time between failures miss hit 6 15 miss hit 6 15 mode active 6 7 mode active idle 6 7 mode power save 6 7 mode sleep 6 8 mode standby 6 8 multiword data transfer 5 131 multiword DMA data transfer timing 5 131 6 1 operation caching 6 13 operation read ahead 6 12 P partial hit 6 18 pausing device Ultra DMA data out burst 5 142 Index pausing host Ultra DMA data in burst 5 137 PIO data transfer 5 130 timing 5 130 power commands 6 9 power on 5 145 timing 5 145 powersave 6 7 mode
168. rgets of caching are as follows e READ SECTOR s EXT e READ MULTIPLE EXT e READ DMA EXT However if the caching function is prohibited by the SET FEATURES command the caching operation is not performed 2 Data that is a target of caching The data that is a target of caching are as follows 1 Read ahead data that is read from disk media and saved to the data buffer upon completion of execution of a command that is a target of caching 2 Pre read data that is read from disk media and saved to the data buffer before execution of a command that is a target of caching 3 Data required by a command that is a target of caching and has been sent to the host system one If the sector data requested by the host has not been completely stored in the read cache portion of the buffer this data does not become a target of caching Also If sequential hits occur continuously the caching target data required by the host becomes invalid because that data is overwrited by new data 3 Invalidating caching target data Data that is a target of caching on the data buffer is invalidated under the following conditions 1 1 Any command other than the following commands is issued All caching target data is invalidated READ LONG C141 E195 02EN 6 13 Operations 6 14 READ LOG EXT READ BUFFER WRITE LONG WRITE LOG EXT WRITE BUFFER RECALIBRATE FORMAT TRACK IDENTIFY COMPONENT SET FEATURES SECURITY ERASE UNIT DEVIC
169. ring the verify operation is posted After all sectors are verified the last interruption INTRQ for command termination is generated 5 28 C141 E195 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F6 DH TETTE Start head No LBA MSB 1 5 1F44 CL 1F34 SN 1 2 1F14 FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count XX At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1 5 IFA CL 1F34 SN 1 2 1F1 ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information Ifthe command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 10 to 1 This command performs the calibration Upon receipt of this command the device sets BSY bit of the Status register and performs a calibration When the device completes the calibration the device updates the Status register clears the BSY bit and generates an interrupt This command can be issued in the LBA mode C141 E195 02EN 5 29 Interface At command issuance I O registers setting contents 1F74 CM 0 1 5 1FA CL 1F3 SN 1 2 1 1 At command completio
170. rmed IOCS16 CS0 and CS1 signals are not asserted The DMA data transfer is a 16 bit data transfer 5 VDC I 5 VDC power supplying to the device GND Grounded signal at each signal wire Note indicates input signal from the host to the device indicates output signal from the device to the host indicates common output or bi directional signal between the host and the device 5 2 Logical Interface 5 6 The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device supports the LBA mode When the host system specifies the LBA mode by setting bit 6 in the Device Head register to 1 HS3 to HSO bits of the Device Head register indicates the head No under the LBA mode and all bits of the Cylinder High Cylinder Low and Sector Number registers are LBA bits The sector No under the LBA mode proceeds in the ascending order with the start point of LBAO defined as follows LBAO Cylinder 0 Head 0 Sector 1 Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command the sector LBA address is not changed LBA Cylinder No x Number of head Head No x Number of sector track Sector No 1 C141 E195 02EN 5 2 Logical Interface 5 2 1 registers Communication between the host s
171. rocessing is attempted for read error recovery by reaching the specified retry cycle while a read error retry is in progress Before attempting automatic alternating processing writing and reading of already corrected data is repeated for the sector in which an error occurred If a read error does not occur during this reading operation automatic alternating processing is not performed If error recovery is not successful even if a write fault error retry is executed automatic alternating processing is performed Figure 6 6 shows an example where automatic alternating processing is applied to sector physical 5 with cylinder 0 and head 0 Index Sector physical 1 2 3 4 5 6 7 779 780 Cylinder 0 Defec Head 0 tive sector 1 2 3 4 Not used 6 7 779 780 Alternate cylinder 0 Head 0 Already This is assigned to an unassigned sector assigned Notes 1 The alternate cylinder is assigned to an inner cylinder in each zone 2 When an access request for sector 5 is issued the sector assigned for alternating processing of the alternate cylinder must be accessed instead of physical sector 5 If an access request for sectors after sector 5 is issued seek is executed to cylinder 0 head 0 in order to continue processing Figure 6 6 Automatic alternating processing C141 E195 02EN 6 11 Operations 6 4 Read ahead Cache Read ahead Cache is the
172. ror Reserved Self test is in progress C141 E195 02EN 5 75 Interface 5 76 e Off line data collection capability Indicates the method of off line data collection carried out by the drive If the off line data collection capability is 0 it indicates that off line data collection is not supported If this bit is 1 it indicates that the SMART EXECUTE OFF LINE IMMEDATE sub command FR register D4h is supported Vendor unique If this bit is 1 it indicates that acquisition of off line data under execution is aborted when a new command is received 3 If this bit is 1 it indicates that the SMART Off line Read Scanning Technology is supported Bit If this bit is 1 it indicates that the SMART Self test function is supported If this bit is 1 it indicates that the SMART Conveyance Self test is supported If this bit is 1 it indicates that the SMART Selective Self test is supported Reserved bits e Failure prediction capability flag If this bit is 1 it indicates that the attribute value is saved on media before the drive enters the power save mode If this bit is 1 it indicates that the attribute value is saved automatically after the pre set operation of the drive e Error logging capability If this bit is 1 it indicates that the drive error logging function is supported Reserved bits e Check sum Two s complement of the lower byte obtained by adding 511 byte data one byte
173. s ST Te Ter 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 FR At command completion I O register contents Dm Ts F5 CH 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information 33 SECURITY FREEZE LOCK F5h This command puts the device into FROZEN MODE The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE e SECURITY SET PASSWORD e SECURITY UNLOCK e SECURITY DISABLE PASSWORD e SECURITY ERASE PREPARE e SECURITY ERASE UNIT C141 E195 02EN 5 85 Interface FROZEN is canceled when the power is turned off or when hardware is reseted If this command 1 reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged Issuing this command during LOCKED MODE returns the Aborted Command error The following medium access commands return the Aborted Command error when the device is in LOCKED MODE READ DMA EXT READ LONG READ MULTIPLE EXT READ SECTORS e READ VERIFY SECTORS WRITE DMA EXT WRITE LONG WRITE MULTIPLE EXT WRITE SECTORS EXT WRITE VERIFY e SECURITY DISABLE PASSWORD e SECURITY FREEZE LOCK e SECURITY SET PASSWORD SET MAX ADDRESS EXT FLUSH CACHE EXT DCO RESTORE DCOSET e SET MAX ADDRESS EXT At command issuance I O register contents 1F7 CM 1 Hon gu aa Dmm 1F5 CH
174. s always set to 1 after the spin up control is completed Data Request DRQ bit This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device Always 0 C141 E195 02EN 5 2 Logical Interface Bit 1 Always 0 Bit0 Error ERR bit This bit indicates that an error was detected while the previous command was being executed The Error register indicates the additional information of the cause for the error 10 Command register X 1F7 The Command register contains a command code being sent to the device After this register is written the command execution starts immediately Table 5 3 lists the executable commands and their command codes This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written 5 2 3 Control block registers 1 Alternate Status register X 3F6 The Alternate Status register contains the same information as the Status register of the command block register The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset Cw osc o o eee C141 E195 02EN 5 13 Interface 2 Device Control register X 3F6 The Device Control register contains device interrupt and software reset SRST Bit 7 High Order B
175. s error sector is deleted from the write cache data and the remaining cache data is written into the medium by the execution of the next Flush Cache command At command issuance I O register contents 1 1 1 9 9 1 1 mem Ts Ts 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 FR 5 90 C141 E195 02EN 5 3 Host Commands At command completion I O register contents to be read 1F6 DH 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 ER XX XX XX XX Error information 37 DEVICE CONFIGURATION Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register The following table shows these Features register values If this command sets with the reserved value of Features register an aborted error is posted DEVICE CONFIGURATION RESTORE DEVICE CONFIGURATION FREEZE DEVICE CONFIGURATION IDENTIFY DEVICE CONFIGURATION SET At command issuance I O register contents 1F7 CM 1 0 1 1 0 0 0 1 IT XX 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 FR C141 E195 02EN XX XX XX COh C1h C2h C3h 5 91 Interface At command completion I O register contents XX 1 5 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information e DEVICE CONFIGURATION RESTORE FR C0h The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns th
176. s of data to be transferred in a read or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 With the EXT system command the sector count is 65536 when value of this register is X 00 in the first setting and X 00 in the second setting When this register indicates X 00 at the completion of the command execution this indicates that the command is completed successfully If the command is not completed successfully this register indicates the number of sectors to be transferred to complete the request from the host system That is this register indicates the number of remaining sectors that the data has not been transferred due to the error The contents of this register has other definition for the following commands INITIALIZE DEVICE PARAMETERS SET FEATURES IDLE STANDBY and SET MULTIPLE MODE C141 E195 02EN 5 9 Interface 5 Sector Number register X 1F3 The contents of this register indicates the starting sector number for the subsequent command The sector number should be between X 01 and the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command Under the LBA mode this register indicates LBA bits 7 to 0 Under the LBA mode of the EXT system command LBA bits 31 to 24 are set in the first setting and LBA bits 7 to 0 are set in the second setting 6 Cylinder Low register X 1F4 The contents of this register ind
177. s the current that flows in the spindle motor b When the charge pump capacitor is charged enough the MPU sets the SVC to the motor start mode Then a current approx 0 3 A flows into the spindle motor A phase switching signal is generated and the phase of the current flowed in the motor is changed in the order of V phase to U phase W phase to U phase W phase to V phase U phase to V phase U phase to W phase and V phase to W phase after that repeating this order d During phase switching the spindle motor starts rotating in low speed and generates a counter electromotive force The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection e The MPU is waiting for a PHASE signal When no phase signal is sent for a specific period the MPU resets the SVC and starts from the beginning When a PHASE signal is sent the SVC enters the acceleration mode 2 Acceleration mode In this mode the MPU stops to send the phase switching signal to the SVC The SVC starts a phase switching by itself based on the counter electromotive force Then rotation of the spindle motor accelerates The MPU calculates a rotational speed of the spindle motor based on the PHASE signal from the SVC and waits till the rotational speed reaches 5 400 rpm When the rotational speed reaches 5 400 rpm the SVC enters the stable rotation mode 3 Stable rotation mode The PLL FLL cir
178. serts the BSY bit disables the failure prediction feature then clears the BSY bit C141 E195 02EN 5 69 Interface Table 5 7 Features Register values subcommands and functions 3 of 3 Features Resister Function X DA SMART Return Status When the device receives this subcommand it asserts the BSY bit and saves the current device attribute values Then the device compares the device attribute values with insurance failure threshold values If there is an attribute value exceeding the threshold F4h and 2Ch are loaded into the CL and CH registers If there are no attribute values exceeding the thresholds 4Fh and C2h are loaded into the CL and CH registers After the settings for the CL and CH registers have been determined the device clears the BSY bit SMART Enable Disable Auto Off line This sets automatic off line data collection in the enabled when the SC register specification 00h or disabled when the SC register specification 00 state This setting is preserved whether the drive s power is switched on or off If 24 hours have passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART READ DATA subcommand FR register DOh SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register
179. ses 0b Operation eie eet erbe REG 5 119 5 5 3 Ultra DMA data in commands eee 5 119 xi Contents CHAPTER 6 xii 5 5 3 1 Initiating an Ultra DMA data in burst see 5 119 5 53 32 in transtet iis ende e ed uote e 5 120 5 5 3 3 Pausing an Ultra DMA data in burst 5 120 5 5 3 4 Terminating an Ultra DMA data in 5 121 5 5 4 Ultra DMA data out commands eere 5 124 5 5 4 1 Initiating an Ultra DMA data out burst see 5 124 D542 The data out transfer o eget ettet tete eile te 5 124 5 5 4 3 Pausing an Ultra DMA data out burst eee 5 125 5 5 4 4 Terminating an Ultra DMA data out burst eese 5 126 5 5 5 Ultra rules ionan gei e Rie e Ice petet ede 5 128 5 5 6 Series termination required for Ultra DMA 5 129 SO 5 130 25 0 1 PIO data transler eee Ree etie 5 130 5 6 2 Multiword data transfer essen 5 131 5 6 3 Ultra DMA data transfer essere een 5 132 5 6 3 1 Initiating an Ultra DMA data in burst eene 5 132 5 6 3 2 Ultra DMA data burst timing requirements esee 5 133 5 6 3 3 Sustained Ultra data in burst esee 5 136 5 6 3 4 Host pausing an Ultra DMA data in burst esee 5 137 5 6 3 5 Device ter
180. signal lines are redefined to provide new functions during an Ultra DMA burst These lines assume these definitions when 1 an Ultra DMA Mode is selected and 2 a host issues a READ DMA or a WRITE DMA command requiring data transfer and 3 the host asserts DMACK These signal lines revert back to the definitions used for non Ultra DMA transfers upon the negation of DMACK by the host at the termination of an Ultra DMA burst of the control signals are unidirectional DMARQ and DMACK retain their standard definitions With the Ultra DMA protocol the control signal STROBE that latches data from DD 15 0 is generated by the same agent either host or device that drives the data onto the bus Ownership of DD 15 0 and this data strobe signal are given either to the device during an Ultra DMA data in burst or to the host for an Ultra DMA data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA Modes the device is capable of supporting The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA
181. sted unless otherwise specifically allowed see 5 6 3 10 and 5 6 3 2 for specific timing requirements 1 2 3 4 5 6 7 8 9 10 11 12 5 126 The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges The host shall assert STOP no sooner than tss after it last generated an HSTROBE edge The host shall not negate STOP again until after the Ultra DMA burst is terminated The device shall negate DMARQ within t after the host asserts STOP The device shall not assert DMARQ again until after the Ultra DMA burst is terminated The device shall negate DDMARDY with tu after the host has negated STOP The device shall not assert DDMARDY again until after the Ultra DMA burst termination is complete If HSTROBE is negated the host shall assert HSTROBE with t after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than tm after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY and no sooner than tpys after placing the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The d
182. t into the D A converter The calculation is digitally executed by the firmware When the head arrives at the target cylinder the track is followed 3 Track following operation Except during head movement to the reference cylinder and seek operation under the spindle rotates in steady speed the MPU does track following control To position the head at the center of a track the DSP drives the VCM by feeding micro current For each sampling time the VCM drive current is determined by filtering the position difference between the target position and the position clarified by the detected position sense data The filtering includes servo compensation These are digitally controlled by the firmware C141 E195 02EN 4 17 Theory of Device Operation 4 7 5 Spindle motor control Hall less three phase twelve pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC hereafter The firmware operates on the MPU manufactured by Fujitsu The spindle motor is controlled by sending several signals from the MPU to the SVC There are three modes for the spindle control start mode acceleration mode and stable rotation mode 1 Start mode When power is supplied the spindle motor is started in the following sequence a After the power is turned on the MPU sends a signal to the SVC to charge the charge pump capacitor of the SVC The charged amount define
183. technical terms that need to be understood to read this manual Acronyms and Abbreviations This section gives the meanings of the definitions used in this manual C141 E195 02EN 1 Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages An alert message consists of an alert signal and alert statements The alert signal consists of an alert symbol and a signal word or just a signal word The following are the alert signals and their meanings T C AUTI ON This indicates a hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly This alert signal also indicates that damages to the product or other property may occur if the user does not perform the procedure correctly This indicates information that could help the user IMPORTANT use the product more efficiently In the text the alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example A CAUTION Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert messages in the text are also listed in the Important Alert Items Operating Environment This product is designed to be
184. ter D5h SN Register 06h SC register 01h and can read the SMART self test log Table 5 12 SMART self test log data format 00 01 Self test log data structure 0 0 2 3 Self test log 1 Self test number SN Register Value 04 05 Life time Total power on time hours Self test error No 07 to 0A Error LBA OB to 19 Vendor unique to 1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 FA Vendor unique 1 1 1 Self test index FD Reserved 1 Check sum e Self test number Indicates the type of self test executed e Self test execution status Same as byte 16Bh of the attribute value Self test index If this is OOh it indicates the status where the self test has never been executed e Checksum Two s complementary for the lowest order 1 byte that is obtained by adding 1 byte after another for as many as 511 bytes from the top C141 E195 02EN Offset 00h 01h 02h 09h OAh 11h 12h 19h 1Ah 21h 22h 29h 2Ah 31h 32h 39h 3Ah 41h 42h 49h 4Ah 51h 52h 151h 152h 1EBh 1Ech 1F3h 1F4h 1F5h 1F6h 1F7h 1F8h 1F9h 1FAh IFBh 1FCh 1FDh 1FEh IFFh C141 E195 02EN 5 3 Host Commands Table 5 13 Selective self test log data structure Data Structure Revision Number Olh 006 Starting LBA O0h 00h Test Span 1 Ending LBA OO0h 00h Starting LBA O0h 00h Test Span 2
185. ters the Active idle mode under the following conditions e After completion of the command execution other than SLEEP and STANDBY commands 3 Low power idle mode Sets circuits on the device to the power save mode The heads are disabled in the safe state The device enters the low power mode under the following conditions e After certain amount of time has elapsed in the active idle state APM Mode 0 Mode 1 and Mode 2 Upon completion of the power on sequence C141 E195 02EN 6 7 Operations Upon receipt of a hard reset e Upon receipt of Idle Idle Intermediate 4 Standby mode 5 Sleep mode 6 8 In this mode the spindle motor has stopped from the low power idle state The device can receive commands through the interface However if a command with disk access is issued response time to the command under the standby mode takes longer than the active active idle or low power idle mode because the access to the disk medium cannot be made immediately The drive enters the standby mode under the following conditions ASTANDBY or STANDBY IMMEDIATE command is issued A certain amount of time has elapsed in the low power idle state APM Mode 2 time specified by the STANDBY or IDLE command has elapsed after completion of the command e A reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in
186. tes per Sector 512 Positioning time read and seek e Minimum Track Track 1 5 ms typ e Average Read 12ms typ e Maximum Full 22 ms typ Start time 4 0 sec typ Interface ATA 6 Max Cable length 18inches 0 46 m equipped with expansion function Data Transfer Rate e To From Media 55 4 MB s Max e To From Host 100 MB s Max U DMA mode5 Physical Dimensions Height x Width x Depth 9 5 mm x 100 0 mm x 70 0 mm Weight 99 g max Capacity under the LBA mode 1 4 C141 E195 02EN 1 3 Power Requirements Table 1 1 lists the formatted capacity number of logical cylinders number of heads and number of sectors of every model for which the CHS mode has been selected using the BIOS setup utility on the host Table 1 1 Specifications 2 2 Model Capacity 1 No of Cylinder No of Heads No of Sectors MHT2080AH 845 GB 16 383 63 MHT2060AH 8 45 GB 16 383 63 MHT2040AH 8 45 GB 16 383 63 On using for the units of BIOS parameter 1 2 2 Model and product number Table 1 2 lists the model names and product numbers of the disk drive Table 1 2 Model names and product numbers Model Name Mounting screw Order No user area MHT2080AH 80 GB M3 depth 3 CA06377 B048 MHT2060AH 60 GB M3 depth 3 CA06377 B046 MHT2040AH 40 GB M3 depth 3 CA06377 B024 B034 1 3 Power Requirements 1 Input Voltage 5V 45 2 Ripple _ 100 mV peak to peak C141 E195 02EN 1 5
187. the spindle motor control circuit and feeds currents to the spindle motor 7 VCM current sense resistor CSR This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back 4 7 2 Data surface servo format Figure 4 7 describes the physical layout of the servo frame The three areas indicated by 1 to 3 in Figure 4 7 are described below 1 Inner guard band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving 4 14 C141 E195 02EN 4 7 Servo Control Servo frame 124 servo frames per revolution CYLn 1 CYLn CYLn 1 n even number Cc Diameter direction W R Recovery W R Recovery W R Recovery Servo Mark Servo Mark Servo Mark Gray Code Gray Code Gray Code 1 Servo l Circumference Servo B Erase Servo B Erase Direction Servo C Erase Servo C Erase Servo D Erase Erase DC erase area PAD Figure 4 7 Physical sector servo configuration on disk surface C141 E195 02EN 4 15 Theory of Device Operation 4 7 3 Servo frame format As the servo
188. the bus strobe The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DDO is shifted in first and DD15 is shifted in last 5 5 6 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes The following table describes recommended values for series termination at the host and the device Table 5 22 Recommended series termination for Ultra IORDY DDMARDY DSTROBE Note Only those signals requiring termination are listed in this table If a signal is not listed series termination is not required for operation in an Ultra DMA Mode For signals also requiring a pull up or pull down resistor at the host see Figure 5 8 dove Figure 5 8 Ultra DMA termination with pull up or pull down C141 E195 02EN 5 129 Interface 5 6 Timing 5 6 1 PIO data transfer Figure 5 9 shows of the data transfer timing between the device and the host system to 4 gt Addresses tl t9 DIOR DIOW e E Qi 4 d Write data 200 2015 4 t3 gt lt t4 gt Read data DDO DD15 IORDY o T at Daa regiser selection setup u m Recovery tine of DIORIDIOW _ pbwmswpimetrpow __ o
189. the standby mode e Reset hardware or software e STANDBY command e STANDBY IMMEDIATE command e INITIALIZE DEVICE PARAMETERS command e CHECK POWER MODE command The power consumption of the drive is minimal in this mode The drive enters only the standby mode from the sleep mode The only method to return from the standby mode is to execute a software or hardware reset The drive enters the sleep mode under the following condition e A SLEEP command is issued In this mode the device does not accept the command It is ignored C141 E195 02EN 6 2 2 Power commands 6 3 Defect Processing The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SET FEATURES APM setting 6 3 Defect Processing This device performs alternating processing where the defective sector is alternated with the spare area depending on media defect location information The media defect location information is registered in the system space specified for the user area according to the format at shipment of the media from the plant 6 3 1 Spare area The following type of area is prepared as the spare area in user areas 1 Spare cylinder for alternate assignment This cylinder is used during automatic alternating processing for defective sector More than 2000 C141 E195 02EN sectors drive 6 9 Operations 6 3 2 Alternating processing for defective sectors
190. tion The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value of the VCM has a dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored For sensing the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value By this compensation loop gain becomes constant value and the stable servo control is realized To compensate torque constant value change depending on cylinder whole cylinders from most inner to most outer cylinder are divided into 14 partitions at calibration in the factory and the compensation data is measured for representative cylinder of each partition This measured value is stored in the SA area The compensation value at self calibration is calculated using the value in the SA area C141 E195 02EN 4 7 Theory of Device Operation 4 5 2 Execution timing
191. tions and handle the HDD under the safety environment C141 E195 02EN 3 7 Installation Conditions General notes ESD mat Wrist strap Shock absorbing mat Use the Wrist strap Place the shock absorbing mat on the operation table and place ESD mat on it Do not stack when carrying Do not place HDD vertically to avoid falling down Do not drop Figure 3 7 Handling cautions Installation 1 Please use the driver of a low impact when you use an electric driver HDD is occasionally damaged by the impact of the driver 2 Please observe the tightening torque of the screw strictly 0 49N m 5 kgf cm Recommended equipments Contents Model Maker ESD Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD mat SKY 8A Color Seiden Mat Achilles Shock Low shock driver SS 6500 HIOS 3 8 C141 E195 02EN 3 3 Cable Connections 3 3 Cable Connections 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 8 shows the locations of these connectors and terminals Connector PCA setting pins A Figure 3 8 Connector locations C141 E195 02EN 3 9 Installation Conditions 3 3 2 Cable connector specifications Table 3 2 lists the recommended specifications for the cable connectors Table 3 2 Cable connector specifications om om Tm ATA interface and power Cable socket 89361 1
192. to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding tur is an unlimited interlock that has no maximum time value tyr is a limited time out that has a defined minimum tr is a limited time out that has a defined maximum 2 80 conductor cabling shall be required in order to meet setup tps tcs and hold tcu times in modes greater than 2 3 Timing for tpvs tcvs and shall be met for lumped capacitive loads of 15 and 40 pf at the connector where all signals Data and STROBE have the same capacitive load value Due to reflections on the cable the measurement of these timings is not valid in a normally functioning system 4 For all modes the parameter tziogpy may be greater than tgxv due to the fact that the host has a pull up on IORDY giving it a known state when not actively driven 5 The parameters tps and tpu for mode 5 is defined for a recipient at the end of the cable only in a configuration with one device at the end of the cable Note timing measurement switching points low to high and high to low shall be taken at 1 5V 5 134 C141 E195 02EN 5 6 Timing Table 5 24 Ultra DMA sender and recipient timing requirements MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 in ns in ns in ns in ns in ns in ns NAME COMMENT so pen pe s us m o m tpsic 14 7 9 7 4 8 2 3 Recipient IC data setup time fr
193. ue indicates the state nearest to a failure so far e Raw attribute value Raw attributes data is retained e Off line data collection status C141 E195 02EN 5 3 Host Commands 00h or 80h Off line data acquisition is not executed 02h or 82h Off line data acquisition has ended without an error 04h or 84h Off line data acquisition is interrupted by a command from the host 5 or 85h Off line data acquisition has ended before completion because of a command from the host 06h or 86h Off line data acquisition has ended before completion because of an error that makes acquisition impossible Not used 40to 7Fh Vendor unique Not used COh to FFh 01h or 81h 03h or 83h 07h or 3Fh 87h to BFh Reserved e Self test execution status 0 to 3 Remainder of the self test is indicated as a percentage in a range of Oh to 9h corresponding to 0 to 90 96 Oh Self test has ended successfully or self test has not been executed Self test is suspended by the host Self test is interrupted by a soft hard reset from the host Self test cannot be executed 4h Self test has ended with an abnormality because of unknown contents Self test has ended with Write Read Test error Self test has ended with Servo Check error Th Self test has ended with SMART Drive Error Log Check Random Read Test or Read Scan Test error 8h Self test has ended with Pre SMART Check or Post SMART Check er
194. urface temperature conditions cable connections and switch settings of the hard disk drives For information about handling this hard disk drive and the system installation procedure refer to the following Integration Guide C141 E144 C141 E195 02EN 3 1 Installation Conditions 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm 100 0 4 90 640 25 3 99 0 25 7420225 14 0 25 69 85 0 25 72 0 25 10 61 Figure 3 1 Dimensions 3 2 C141 E195 02EN 3 2 Mounting 3 2 Mounting For information on mounting see the FUJITSU 2 5 INCH HDD INTEGRATION GUIDANCE C141 E144 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive gravity gravity gravity ertical 3 f Vertical 4 lt Figure 3 2 Orientation C141 E195 02EN 3 3 Installation Conditions 2 Frame The MR head bias of the HDD disk enclosure DE is zero The mounting frame 1s connected to SG IMPORTANT Use screw for the mounting screw and the screw length should satisfy the specification in Figure 3 3 The tightening torque must be 0 49N m 5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Lim
195. us register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is posted Other than X 00 is specified this command terminates normally The parameters set by this command are retained even after reset or power save operation regardless of the setting of disabling the reverting to default setting The device ignores the L bit specification and operates with only CHS mode specification C141 E195 02EN 5 31 Interface At command issuance I O registers setting contents WENN Dres iTi Te or __ 1 5 1F44 CL XX 1F3y SN XX 1F24 SC Number of sectors track 1F1y FR XX At command completion I O registers contents to be read x x bv oce 1F54 CH 1F44 CL XX 1F34 SN XX 1F24 SC Number of sectors track 1 15 Error information 12 IDENTIFY DEVICE X EC 5 32 The host system issues the IDENTIFY DEVICE command to read parameter information from the device Upon receipt of this command the drive sets the BSY bit to one prepares to transfer the 256 words of device identification data to the host sets the DRQ bit to one clears the BSY bit to zero and generates an interrupt After that the host system reads the information out of the sector buffer Table 5 4 shows the values of the parameter words and the meaning in the buffer At command issuance I
196. used in offices or computer rooms Conventions An disk drive device is sometimes simply referred to as a hard disk drive HDD drive or device in this document Decimal numbers are represented normally Hexadecimal numbers are represented as shown in the following examples X 17B9 17B9h 17B9H or 17B9H Binary numbers are represented as shown in the following examples 010 or 010b ii C141 E195 02EN Preface Attention Please forward any comments you may have regarding this manual To make this manual easier for users to understand opinions from readers are needed Please write your opinions or requests on the Comment at the back of this manual and forward it to the address described in the sheet Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk drive C141 E195 02EN iii This page is intentionally left blank Important Alert Items Important Alert Messages The important alert messages in this manual are as follows A hazardous situation could result in minor or moderate personal AC AUTION injury if the user does not perform the procedure correctly Also damage to the product or other pro
197. vice as described below PDIAG signal negated within 1 ms and asserted within 30 seconds The asserted PDIAG signal is negated 30 seconds after it is asserted if the command is not received When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal r Master device X 0C ATE X 00 or X 04 Status Reg BSY bit Max 31 sec gt If slave device is preset PDIAG is checked for up to 31 seconds Slave device R C BSY bit s gt Max 1 ms 1 1 1 1 PDIAG 1 Max 30 sec RIEN 5 DASP t 1 1 1 1 Figure 6 3 Response to software reset C141 E195 02EN 6 5 Operations 6 1 4 Response to diagnostic command X IF7 Reg Write When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present the master device checks the PDIAG signal for up to 6 seconds to see if the slave device has completed the self diagnosis successfully The master device does not check the DASP signal After the slave device receives the EXECUTE DEVICE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds The asserted PDIAG signal is negated 5 seconds after it is asserted if the command is not received If the command is received the PDIAG si
198. vice has asserted DDMARDY The host shall negate HSTROBE no sooner than tpys after the driving the first word of data onto DD 15 0 5 5 4 2 The data out transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 8 and 5 6 3 2 for specific timing requirements D 5 124 The host shall drive a data word onto DD 15 0 C141 E195 02EN 2 3 4 5 5 Ultra DMA Feature Set The host shall generate an HSTROBE edge to latch the new word no sooner than tpys after changing the state of DD 15 0 The host shall generate an HSTROBE edge no more frequently than tcyc for the selected Ultra DMA Mode The host shall not generate two rising or falling HSTROBE edges more frequently than 2 tcyc for the selected Ultra DMA mode The host shall not change the state of DD 15 0 until at least tpyy after generating an HSTROBE edge to latch the data The host shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first 5 5 4 3 Pausing an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 9 and 5 6 3 2 for specific timing requirements a b C141 E195 02EN Host pausing an Ultra DMA data out burst 1 The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2
199. vironmental Specifications esee ene 1 8 L3 NOISE e pe eee ei eee Tea eon e pe NER 1 9 1 6 Shock and Vibration ie sette he eR ved ene eee S eget etin 1 9 17 RR p e ee pe RUA 1 10 1 8 eerte 1 11 1 9 Media 1 11 1 10 Load Unload Function eese rennen ener 1 11 1 11 Advanced Power 1 12 CHAPTER 2 Device Configuration 2 1 2 1 Device Configuration ee e n tote 2 2 2 2 Systeri Configuration asesi ceine aea ne 2 3 22 1 ATA Interface interacial aids rtt d etel Riot 2 3 2 2 2 ldnveconnection uie E ees 2 3 2 2 3 2id v s conn ctiOn M es 2 4 C141 E195 02EN ix Contents CHAPTER 3 CHAPTER 4 Installation Conditions 3 1 3 1 Dimensions eg epp RU 3 2 3 2 oen teme te get deris eee HR pee Eee nee ees a 3 3 3 3 Cabl Connectons o eee ae e eee dere e cse 3 9 3 3 1 D vice connector ue e eee ou depone 3 9 3 3 2 Cable connector ene 3 10 3 3 3 Device connection tee e bed eens 3 10 3 3 4 Power supply connector CNI eene 3 10 3 4 Jumper Settings uoto ce Re e as 3 11 3 4 1 Location of setting jumpers esee ene 3 11
200. ystem and the device is done through input output I O registers of the device These I O registers can be selected by the coded signals CSO CS1 and DAO to DA2 from the host system Table 5 2 shows the coding address and the function of I O registers Table 5 2 O registers I O registers cso CSI DA2 DAO 8 Host I O i om m mensae reme xum Lx o a sesemner ser xir Lx o a omiies Cyimaertow x1r C T C mu T eee omit c T H H DevieiHead xire T T L H L H L Ce o e emere xi L H X X Invalid Invalid PF Control block registers 72 L Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATAO to 15 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus DATAO to DATA7 3 When reading the Drive Address register bit 7 is high impedance state 4 H indicates signal level High and L indicates signal level Low There are two methods for specifying the LBA mode One method is to specify the LBA mode with 28 bit address information and the other is to specify it with 48 bit address information command of EXT system If the LBA mode is specif
201. ystem issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Features register Then the device clears the BSY bit and generates an interrupt Table 5 5 lists the available values and operational modes that may be set in the Features register C141 E195 02EN 5 43 Interface Table 5 5 Features register values and settable modes Features Drive operation mode Register X 66 Disables the reverting to power on default settings after software reset 1 X 85 X AA X BB Specifies the transfer of 4 byte ECC for READ LONG and WRITE LONG commands 1 X CZ Disables the Acoustic management function Enables the reverting to power on default settings after software reset 1 Although there is a response to the command nothing is done Set the advanced power management mode to the Mode 0 Enables the read cache function Disables the write cache function At power on or after hardware reset the default mode is set as follows Write cashe function Enabled Transfer mode PIO Mode 4 Multiworld DMA Mode 2 Advanced power management function Enabled Mode 1 Acoustic management function State keeping Read cashe function Enabled 5 44 C141 E195 02EN 5 3 Host Commands At command issua
202. yte is the selector bit that selects higher order information or lower order information of the EXT system command If HOB 1 LBA bits 47 to 24 and the higher order 8 bits of the sector count are displayed in the task register If HOB 0 LBA bits 23 to 0 and the lower order 8 bits of the sector count are displayed in the task register Bit 2 Software Reset SRST is the host software reset bit When this bit is set the device is held reset state When two device are daisy chained on the interface setting this bit resets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 bit enables an interrupt INTRQ signal from the device to the host When this bit is O and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state 5 3 Host Commands The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the Command register The device can accept the command when the BSY bit is 0 the device is not in the busy status The host system can halt the uncompleted command execution only at execution of hardware or software reset When the BSY bit is 1 or the DRQ bit is 1 the device is requesting the data transfer and the host system writes to t

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