User Manual
Contents
1. P5V P1 C1 PLET P3 3V P1 B2 P1 D2 P1 G2 VCCO DC BO UL VCCO DC B1 U2 1 VCCO DC B2 U3 1 4 Daughter Card Headers The DNMEG INTERCON Daughter Card provides two 400 pin MEG Array connectors P1 P2 on the bottom of the printed circuit board assembly PCBA and an additional 400 pin MEG Array connector P3 on the top of the PCBA The MEG Array IO banks are connected 1 1 thus providing a bridging function between the headers The 400 pin MEG Array connectors on the bottom of the printed circuit board assembly PCBA are used to interface to the Dini Group products e g DNMEG INTERCONN User Manual The Dini Group 6 DN9000K10PCI The 400 pin MEG Array connector on the top of the PCBA can be used for IO expansion utilizing the DNMEG Obs Daughter Card All signals on the DNMEG_INTERCON Daughter Card Headers are all routed as differential 50 Ohm transmission lines No length matching is done on the PCB for Daughter Card signals except within a differential pair because the Virtex 5 FPGA is capable of variable delay input using the built in IDELAY capabilities Other connections on the daughter card connector system include three dedicated differential clock connections for inputting global clocks from an external source power connections bank Voco power and a reset signal 4 1 Daughter Card clocking Refer to External Clock Input in this User Manual 4 2 Daughter Card Header Pin As2. 0 5A 8 25v s00mA 5 QO 3 gt 3 LT1963AES8 E 3 m 2 5V 0 5A gt 25v 500mA_ 5 QO5 gt LT1963AES8 Figure 2 DNMEG_INTERCON Daughter Card Block Diagram DNMEG_INTERCON User Manual www dinigroup com 4 The DNMEG_INTERCON Daughter Card provides two 400 pin MEG Array connectors P1 P2 on the bottom of the printed circuit board assembly PCBA and an additional 400 pin MEG Attav connector P3 on the top of the PCBA The MEG Array IO banks are connected 1 1 thus providing a bridging function between the headers The 400 pin MEG Array connectors on the bottom of the printed circuit board assembly PCBA are used to interface to the Dini Group products e g DN9000K10PCI The 400 pin MEG Array connector on the top of the PCBA can be used for IO expansion utilizing the DNMEG Obs Daughter Card An external clocking LVDS option is provided via an SMA pair Independent linear power supplies are used to drive the IO bank voltages Discrete LED s indicate reset status and power supply presence 2 External Clock Input An external clocking LVDS option is provided via a 50Q SMA pair J1 J2 see Figure 3 Resistors R4 R5 can be replaced by capacitors to allow for AC coupling of the external clock input For single ended solutions resistors RZ R6 can be used to terminate the signal LK DC B Kr Prev acap El crepe B on Ji P12V 2 GCAN AUN L C1 z E
3. applying pressure to mate the connectors DNMEG_INTERCONN User Manual The Dini Group 18 DNMEG_INTERCONN User Manual The Dini Group 19 4 7 MEG Array Specifications Manufacturer Part Number RoHS Compatible Total Number Of Positions Lead Free Contact Area Plating Mating Force Unmating Force Insulation Resistance Withstanding Voltage Current Rating Contact Resistance Temperature Range Trademark Approvals and Certification Product Specification Pick up Cap Housing Material Contact Material Durability Mating Cycles DNMEG_INTERCONN User Manual FCI 74390 101LF Bottom Receptacle P5 84520 102LF Top Plug P4 ves 400 0 76 um 30 pin gold over 0 76 um 30 pin nickel 30 grams per contact average 20 grams per contact average 1000 M ohms 200 VAC 0 45 amps 20 to 25 m ohms max initial 10 m ohms max increase after testing 40 C to 85 C MEG Array UL and CSA approved GSe 12 100 from FCI websit yes LCP Copper Alloy 50 The Dini Group 20 5 Mechanical 5 1 Dimensions The DNMEG_INTERCON Daughter Card measures 55mm x 148mm ie pupa Bia a DNMEG_INTERCONN User Manual E an 2 ke B g do m m Cc b L I i 40 70 40 q 1 m em oa oO br t T The Dini Group 21
4. 4 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ The download section of the web page may contain a document called DNMEG_INTERCON Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the Users Manual DNMEG_INTERCONN User Manual www dinigroup com 3 HARDWARE DESCRIPTION Chapter Hardware Description This chapter describes the fictional blocks of the design and focuses on the 1 Overview The DNMEG_INTERCON Daughter Card allows the user to expand on the FPGA to FPGA interconnect utilizing the MEG Array Daughter Card header IO banks as interconnect A high level block diagram of the DNMEG_INTERCON Daughter Card is shown in Figure 2 followed by a brief description of each section STATUS LED S e e 6 e 602026 Or CQ C sx OO OR D Ouod D B LU LU Ww LU Ww LU LU LU Fur ee QNSE pc NES PS MARIE jj EXT Clock Input O CLK DC EXT 2p DC BOp 1 31 fidla ono8 i DC BOn 1 31 di pa M H CLK DC EXT 2n z O gt o m o DC Bip 1 31 D x D EEE EEE gt m p DC Bin 1 31 3 3 2 A Ez Z l Co m l II AR D 48 DC B2p 1 31 a a8 as DC B2n i 31 Te Bo 8 E Sg oe 59 ES BS 3 Linear PSU s 1 EE inear 3 4 2 5V 0 5 25v s500mA 22Y Q 09 gt g 2 LT1963AES8 a 5 L S9 lt f 2 5V
5. F1 P1 E1 P1 F3 P1 E3 DNMEG_INTERCONN User Manual The Dini Group 10 Signal Name Pin Pin Pin IMMA NEN IMMA DC T RSTN P2 J2 P3 J2 DC BONI P1 B4 P2 B4 P3 B4 1 DNMEG_INTERCONN User Manual The Dini Group MEG Array MEG Array Signal Name Pin Pin DG Bono ZU DC BONS31 DC BON4 DC BON5 DC BON6 DC BON7 DC BON8 DC BON9 DC BOPI1 DC BOP10 DC B0P11 DC_BOP12 DC_BOP13 DC_BOP14 DC_BOP15 DC_BOP16 DC_BOP17 DC_BOP18 DC_BOP19 P2 H11 DC_BOP2 P2 C3 DC_BOP20 P2 K11 DC_BOP21 P2 A13 DC_BOP22 P2 C13 DC BOP23 P2 H13 DC BOP24 P2 K13 DNMEG INTERCONN User Manual The Dini Group 12 Signal Name Pin Pin Pin DC_BOP25 P2 A15 T Dc 80629 TI DG BOP30 DG Bops DC BOP8 P3 K5 DC BOP9 P1 A7 P3 A7 DC BINI P1 G16 P3 G16 Dc BiNi0 TEMI ENT Do Bis Dc pini Do Bis ENT ET Dc BIN zm Dc BINIG zT DC B1N19 P2 B26 ITI E DNMEG INTERCONN User Manual The Dini Group 13 Signal Name Pin Pin DC_B1N20 P2 D26 DC B1N21 P2 G26 DC B1N22 P2 J26 DC B1N23 P2 B28 DC B1N24 P2 D28 DC B1N25 P2 G28 DC B1N26 P2 J28 DC B1N27 P2 F17 DC B1N28 P2 F19 DC B1N29 P2 F21 DC B1N3 P2 B18 DC B1N30 P2 F23 DC BIN31 P2 F25 DC BINA P2 D18 DC B1N5 P2 G18 DC B1N6 P2 J18 DC BIN7 P2 B20 DC B1N8 P2 D20 DC Bing P2 G20 DC BIPI P2 H15 DC B1P10 P2 K19 DC B1P11 P2 A21 DC B1P12 P2 C21 DC B1P13 P2 H21 DC BIP14 P2 K21 DC B1P15 P2 A23 DNMEG INTERCONN User Manual The Dini Group 14 MEG A
6. S CLK DC B ip i R2 O psvi E GCBP l Hij Psv x Geon ES CE LR Rota DNI 49 9R id La LK DC EXT 2 D701 B2 Ipaav 1 accep LES GLK CERA p RA AUR 1420701501 L D2 4 F5 CIK DC EXT 2n gt Ge P3 3V_2 GCCN B e P3 3V 3 d 5 J2 R6 RSTn l ib a DNI 49 9R PL Clock Power Reset 142 0701 501 74390 101LF z Figure 3 External Clock Input The connections between the SMA connectors and the MEG Array connector are shown in Table 1 Table 1 Connections between External Clock Input and MEG Array Connector Signal Name MEG Attav Pin CLK DC EXT 2p P1 E5 CLK DC EXT 2n P1 F5 DNMEG INTERCONN User Manual The Dini Group 5 3 LED Indicators The DNMEG_INTERCON provides various LED s to indicate that status of the board 3 1 RESET LED s Two ted LED s are provided to indicate the status of the DC_B_RSTn and DC_T_RSTn reset signals The LED s can be turned ON by driving the corresponding pin LOW Table 2 describes the user LED s and their associated pin assignments on the MEG Array connector Table 2 RESET LED s Signal Name MEG Atray pin DC_B_RSTn P1J2 DC T RSIn P2 J2 3 2 Power Supply Status LED s Five green LED s are provided to indicate the presence of vatious power supplies Table 3 describes the power supply status LED s and their associated voltage source Table 3 Power Supply Status LED s Signal Name Power Supply P12V P1 A1 PL K1
7. THE DINI GROUP LOGIC Emulation Source User Manual DNMEG INTERCON LOGIC EMULATION SOURCE DNMEG INTERCON User Manual Version 1 0 The Dini Group 7469 Draper Ave La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1278 support dinigroup com www dinigroup com Copyright Notice and Proprietary Information Copyright 2007 The Dini Group All rights reserved No part of this copyrighted work may be reproduced modified or distributed in any form or by any means without the prior written permission of The Dini Group Right to Copy Documentation The Dini Group permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks disclaimers and proprietary rights notices Disclaimer The Dini Group has made reasonable efforts to ensure that the information in this document is accurate and complete However The Dini Group assumes no liability for errors or for any incidental consequential indirect or special damages including without limitation loss of use loss or alteration of data delays or lost profits or savings arising from the use of this document or the product which it accompanies Table of Contents INTRODUCTION eH 1 1 ABOUT THE DNMEG_INTERCON DAUGHTER CARD sl 2 DNMEG INTERCON DAUGHTER CARD FEATURES wl 3 PACKAGE CONTENTS aora a A e A TA es 2 4 INSPECT THE BOARD wasa
8. d 12V power rails are supplied to the DNMEG INTERCON Daughter Card Headers from the host Dini Card eg DN8000K10PCI Each pin on the MEG Atray connector is rated to tolerate 1A of current without thermal overload Each power rail supplied from the Daughter Card Header is fused refer to Figure 6 P12V o C1 0 1uF 0 o2 5 PI g P12V ur 4 RI piv 1 GCAP HE P12V 2 GCAN PSV _ CI E3 F1 z P5V 1 a GCBP Ead HT psv 2 x acen FS P3 3V a 452 P3 3V_1 a GCCP EB EE P3 3V 2 GCCN 07 G2 533v L 0 tuF tid DC B RSTn J2 RSTn P3 3V DS1 Clock Power Reset R7 300R A SESS 74390 101LF RED LED Figure 6 Daughter Card Header Power amp RESET The DC_RSTn signal is driven by a pushbutton switch S1 and pulled up on the DNMEG_INTERCON Daughter Card The signal is also routed to the FPGA U15 and can be used as a reset to the logic refer to Table 5 Table 5 Daughter Card Reset Signal DC RSTn Signal Name FPGA Pushbutton Switch DC RSIn U5 AE13 1 4 4 6 Insertion Removal of Daughter Card Due to the high density MEG Array connectors the pins on the plug and receptacle of the MEG Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the MEG Array headers line up BEFORE
9. iia bika H 2 5 ADDEDONAR INFORMATION ME a bakar ka aa ta t nka 2 HARDWARE DESCRIPTION ssscccssecsaccossccsaccossscecssccssestsnssscvsssscesesesdcevosdececssosstessejsesectesteccanssaseedsesosdeossoescersedoosssesdsseesesesdsonsdcssessussesvcsstdacseassstsccensdessesveseacees 4 1 OVERVIEW lt lt v w e 4 EXTERNAL CLOCK INPUT 5 3 LEDINDIGATORS MP 3 1 RESET 2 BI andesite KG AISHA KEKI KI KIUKA BAE uawa 3 2 Power Supply Status LED s 4 DAUGHTER CARD HEADERS 5 irr thon LIE ONE EE PA KGA FEE Ii 6 4 1 Da ghter Card clo kirig ART 7 4 2 Daughter Card Header Pin Assignments A 4 2 1 Special Pins on the Daughter Card Header 9 REBA za ita te m las enact eee 9 4 3 Voco Rover Supply NA IAA KAMA MA WA MUA waw 9 4 47 Daughter Card Header TO Connections et rte RR EROR ERO TE LOEO EU ED YORKER LEE DR DI TRIB Bi 10 4 5 Power and Reset 4 63 Insertion Removal of Daughter Card ted tbe ep ee p EU Oe ERR EIER ER UL EE roe pue LUE E vene 18 47 MEG Array Specifications i re RR RR E e PRU R OI Ua ab b gt a 20 5 MECHANICAL 5 21 3d EAR a A A A M 21 List of Figures Figure T DNMEG INTERCON Daughter Card i ii gabe Ner ieu ues 1 Figure 2 DNMEG_INTERCON Daughter Card Block Diagram Figure 3 External Clock Input Figure 4 Daughter Card Header Pin Assignments Figu
10. own Veco pins Veco is determined by the IO standard for that particular IO bank Since a daughter card will not always be present on a daughter card connector a Veco bias generator is used on the motherboard for each daughter card bank to keep the Veco pin on the FPGA within its recommended operating range The Daughter Card drives Veco to the required level for the particular IO standard The Veco impressed by the Daughter Card needs to satisfy the Viimax Of the FPGA on the host board There are three Adjustable Linear Power Supplies U1 U1 and U2 on the DNMEG_INTERCON Daughter Card refer to Figure 5 Refer to the datasheet for the LT1963A from Linear Technology on how to adjust the output voltages DNMEG_INTERCONN User Manual The Dini Group 9 P3 3V C3 10uF C4 P3 3V Q P3 3V O bou CERAMIC 4 4 Daughter Card 63 16V 0 1uF 47771 16V Cuf 20 GND R3 20 CERAMIC LT1963AES8 SO8 1K CERAMIC LT1963AES8 SO8 1 v DC BO U1 E 1 VCCO DC BO SHDNSENSE ADJ im i L GND NC x GND Sour VCCO DC B1 o VCCO DC B1 C11 10uF C12 16V 0 1uF RQ 20 1K CERAMIC VCCO DC B2 Oo VCCO DC B2 C17 10uF 16V 0 1uF R12 20 1K CERAMIC Figure 5 VCCO Adjustable Linear Power Supplies Header IO Connections Table 4 lists the interconnect between the Daughter Card Headers Table 4 Daughter Card Header IO Connections Signal Name MEG Array Pin P1
11. re 5 VCCO Adjustable Linear Power Supplies Figure 6 Daughter Card Header Power amp RESET List of Tables Table 1 Connections between External Clock Input and MEG Array Connector cecssssessssscssssesssseesssssssssessssnecssssecsssscssssecssssssssscssssessssssssssesssuscssssesssssccsssesssscesssssessness 5 Table 2 RESET LED s Table 3 Power Supply Status LED s Table 4 Daughter Card Header IO Connections Table 5 Daughter Card Reset Signal DC RSTn INTRODUCTION Chapter Introduction This User Manual accormpames the DNMEG_INTERCON Daughter Card 1 About the DNMEG INTERCON Daughter Card The DNMEG_INTERCON Daughter Card allows the user to expand on the FPGA to FPGA interconnect utilizing the daughter card IO as interconnect The MEG Array IO banks are connected 1 1 thus providing a bridging function between the headers The DNMEG INTERCON Daughter Card can be used on any of the Dini Group products that have two adjacent MEG Array Daughter Card Headers eg DN9000K10PCI DN9000K10PCI 2 DNMEG INTERCON Daughter Card Features DNMEG_INTERCON Copyright 2006 E 0704020 Made in the USA ASSY NO The Dini Group Inc 502 0154 IA P N 501 0154 0000 REV 1 Figure 1 DNMEG INTERCON Daughter Card DNMEG_INTERCONN User Manual www dinigroup com 1 INTRODUCTION DNMEG_INTERCON Daughter Card features the following e Daughter Card Headers x3 LVDS MEG Attav 400 pin interface
12. rray MEG Array Signal Name Pin Pin DC B1P16 P2 C23 DC B1P17 P2 H23 DC B1P18 P2 K23 DC B1P19 P2 A25 DC B1P2 P2 K15 DC B1P20 P2 C25 DC B1P21 P2 H25 DC B1P22 P2 K25 DC B1P23 P2 A27 DC B1P24 P2 C27 DC B1P25 P2 H27 DC B1P26 P2 K27 DC B1P27 P2 E17 DC B1P9 P1 H19 P2 H19 MEG Array Pin P3 H19 DC B2N1 P1 B30 P2 B30 DC B2N10 P1 D34 P2 D34 DNMEG INTERCONN User Manual The Dini Group P3 B30 P3 D34 15 Signal Name Pin Pin DC_B2N11 P2 G34 DC_B2N12 P2 J34 DC_B2N13 P2 B36 DC_B2N14 P2 D36 DC_B2N15 P2 G36 DC B2N16 P2 J36 DC B2N17 P2 B38 DC B2N18 P2 D38 DC B2N19 P2 G38 DC B2N2 DC B2N20 DC B2N 1 DC B2N22 DC B2N23 DC B2N24 P2 J40 DC B2N25 P2 F27 DC B2N26 P2 F29 DC B2N27 P2 F31 DC_B2N28 P2 F33 DC_B2N29 P2 F35 DC_B2N3 P2 G30 DC_B2N30 P2 F37 DC_B2N31 P2 F39 DC_B2N4 P2 J30 DC_B2N5 P2 B32 DC B2N6 P2 D32 DNMEG INTERCONN User Manual The Dini Group 16 Signal Name Pin Pin DC_B2N7 P2 G32 DC_B2N8 P2 J32 DC_B2N9 P2 B34 DC_B2P1 P2 A29 DC_B2P10 P2 C33 DC_B2P11 P2 H33 DC_B2P12 P2 K33 DC_B2P13 P2 A35 DC_B2P14 P2 C35 DC_B2P15 P2 H35 DC B2P16 P2 K35 DC B2P17 P2 A37 DC B2P18 P2 C37 DC B2P19 P2 H37 DC B2P2 P2 C29 DC B2P20 P2 K37 DC B2P21 P2 A39 DC B2P22 P2 C39 DC B2P23 P2 H39 DC B2P24 P2 K39 DC B2P25 P2 E27 DC B2P26 P2 E29 DC B2P27 P2 E31 DC B2P28 P2 E33 DC B2P29 P2 E35 DNMEG INTERCONN User Manual The Dini Group Pin 17 4 5 Power and Reset The 43 3V 45V an
13. signments The pin assignments of the DNMEG_INTERCON Daughter Card Headers were designed to reduce cross talk to manageable levels while operating at full speed of the Virtex 5 LVDS standards The Daughter Card Header is divided into three banks The ground to signal ratio of the connector is 1 1 refer to Figure 4 General purpose IO is arranged in a GSGS pattern to allow high speed single ended or differential use On the host these signals are routed as loosely coupled differential signals meaning when used differentially they benefit from the noise resistant properties of a differential pair but when used in a single ended configuration they do not interfere with each other excessively DNMEG INTERCONN User Manual The Dini Group 7 ABCODEFGH J K 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 Figure 4 Daughter Card Header Pin Assignments DNMEG INTERCONN User Manual The Dini Group 4 2 4 Special Pins on the Daughter Card Header VREF These pins are connected 1 1 on the board and the function is determined be the mother board GCAp n GCBp n and GCCp n These pins are connected 1 1 on the board and the function is determined be the base board 4 3 Veco Power Supply On the Virtex 5 FPGA each IO bank has its
14. to DN900xK10xxx products e External Clock Input LVDS SMA x 2 e Power Supply Status LED s x6 e VCCO Linear Power Supplies x3 3 Package Contents The DNMEG_INTERCON Daughter Card would normally accompany one of the The Dini Group Logic Emulations products but could be ordered as a separate item 4 Inspect the Board Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment Verify that all components are on the board and appear intact 5 Additional Information For additional information please visit http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions Demonstration Videos MEG Array Daughter Card header insertion and removal video Dini Group Web Site The web page will contain the latest user manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com You may direct questions and feedback to the Dini Group DNMEG INTERCONN User Manual www dinigroup com 2 INTRODUCTION Resource Description URL using this e mail address support dinigroup com Phone Support Call us at 858 45
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