ISL54200 Datasheet
Contents
1. NOTES 11 12 sheet 13 14 range 15 VLocic Input voltage to perform proper function The algebraic convention whereby the most negative value is a minimum and the most positive a maximum is used in this data lowest max roy value between HSD2 and HSD1 or between FSD2 and FSD1 Test Circuits and Waveforms VINH LOGIC INPUT VINL SWITCH INPUT VINPUT SWITCH OUTPUT oy Logic input waveform is inverted for switches that have the opposite logic sense tr lt 20ns tf lt 20ns SWITCH INPUT capacitance FIGURE 1A MEASUREMENT POINTS VINPUT V OUT V INPUT Parts are 100 tested at 25 C Over temperature limits established by characterization and are not production tested Flatness is defined as the difference between maximum and minimum value of on resistance over the specified analog signal VOUT Repeat test for all switches C includes fixture and stray RL RL r on FIGURE 1B TEST CIRCUIT FIGURE 1 SWITCHING TIMES ron matching between channels is calculated by subtracting the channel with the highest max roy value from the channel with intersil FN6408 2 June 17 2010 ISL54200 Test Circuits and Waveforms continued VINH LOGIC INPUT VINL SWITCH 90 OUTPUT VOUT ov Le tD gt Repeat test for all switches C includes fixture and stray capacitance FIGURE 2A MEASUREMENT POINTS FIGURE 2B TEST CIRCUIT FIGURE 2 BREAK BE2. Note 11 Unless Otherwise Specified Bold face limits apply over the operating temperature range 40 C to 85 C TEMP MIN MAX PARAMETER TEST CONDITIONS C Notes 12 13 TYP Notes 12 13 UNITS ANALOG SWITCH CHARACTERISTICS NC Switches FSD1 FSD2 Analog Signal Range VanatoGc Vpp 3 3V IN OV EN 3 3V Full 0 VDD V ON Resistance ron Vpp 3 3V IN 0 5V EN LAN Icomx 40mA 25 7 10 Q Vesp1 Or Vesp2 OV to 3 3V See Figure 4 Full z 15 a ron Matching Between Vpp 3 3V IN 0 5V EN LAN Icomx 40mA 25 0 1 0 35 Q Channels Aron Vesp1 Or Vesp2 Voltage at max ron over signal range of OV to 3 3V Note 15 Full i 7 0 4 S ron Flatness rFLAT ON Vpp 3 3V IN 0 5V EN 1 4V Icomx 40mA 25 4 Q Vespi Or Vesp2 OV to 3 3V Note 14 Full A 7 8 e OFF Leakage Current Irsx oFF V 3 6V IN 3 6V EN OV and 3 6V Vcomx 25 20 2 20 nA 0 3V 3V Vesx 3V 0 3V Full ES 70 Se ON Leakage Current Irsx on V 3 6V IN OV EN 3 6V Vcomx 0 3V 25 20 2 20 nA She eg Full 70 70 nA NO Switches HSD1 HSD2 Analog Signal Range VanatoGc Vpop 3 3V IN 3 3V EN 3 3V Full o VDD V FN6408 2 4 intersil June 17 2010 ISL54200 Electrical Specifications 2 7V to 3 6V Supply Test Conditions Vpp 3 3V GND OV VynH 1 4V Vint 0 5V VENH LAN Vew 0 5V Note 11 Unless Otherw
3. HSD1 and HSD2 switches are ON and the FSD1 and FSD2 switches are OFF high impedance When a USB cable from a computer or USB hub is connected at the common USB connector and the part is in the high speed mode a link will be established between the high speed driver section of the media player and the computer The device will be able to transmit and receive data from the computer at a data rate of 480Mbps All Switches OFF Mode If the IN pin Logic O or Logic 1 and the EN pin Logic 0 all of the switches will turn OFF high impedance The all OFF state can be used to switch between the two USB sections of the media player When disconnecting from one USB device to the other USB device you can momentarily put the ISL54200 switch in the all off state in order to get the computer to disconnect from the one device so it can properly connect to the other USB device when that channel is turned ON 10 intersil FN6408 2 June 17 2010 ISL54200 Typical Performance Curves 1 25 c unless otherwise Specified pat esd Ni 2 WR PE Owe RR i i VOLTAGE SCALE 0 5V DIV D D Signals V e E 0 0 1 0 2 0 3 0 4 0 5 0 6 0 70 8 0 gt Time x10 8 s TIME SCALE 10ns DIV FIGURE 8 EYE PATTERN 12MBPS USB SIGNAL WITH FSx SWITCHES IN THE SIGNAL PATH 11 i D FN6408 2 intersil June 17 2010 ISL54200 Typical Performance Curves Ta 25 C Unless Otherwise Specified Continued V
4. for IN Logic 0O and EN Logic 1 Ordering Information ISL54200 10 LD pTQFN TOP VIEW PART NUMBER PART TEMP RANGE PACKAGE PKG Note 5 MARKING C Pb Free DWG ISL54200IRZ Note 3 200Z 40 to 85 10 Ld 3x3 TDFN L10 3x3A ISL54200IRZ T Note 2 3 200Z 40 to 85 10 Ld 3x3 TDFN Tape and Reel L10 3x3A ISL54200IRUZ T Note 2 4 FM 40 to 85 10 Ld 2 1mmx1 6mm uTQFN Tape and Reel L10 2 1x1 6A ISL54200EVAL1Z Evaluation Board NOTES 2 Please refer to TB347 for details on reel specifications 3 These Intersil Pb free plastic packaged products employ special Pb free material sets molding compounds die attach materials and 100 matte tin plate plus anneal e3 termination finish which is ROHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 4 These Intersil Pb free plastic packaged products employ special Pb free material sets molding compounds die attach materials and NiPdAu plate e4 termination finish which is ROHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 5 For Moisture Sensitivity Level MSL please see device informati
5. high speed signals with minimum edge and phase distortion to meet USB 2 0 high speed signal quality specifications See Figures 9 and 10 The HSx switches can also pass USB full speed signals 12Mbps with minimal distortion and meet all the USB 9 intersil FN6408 2 June 17 2010 ISL54200 requirements for USB 2 0 full speed signaling See Figure 11 The maximum signal range for the HSx switches is from 1 5V to Vpp The signal voltage should not be allowed to exceed the Vpp voltage rail or go below ground by more than 1 5V The HSx switches are active turned ON whenever the IN voltage is gt 1 4V and the EN logic voltage zl AN when operated with a 2 7V to 3 6V supply ISL54200 Operation The discussion that follows will discuss using the ISL54200 in the typical application shown in the Application Block Diagram on page 9 POWER The power supply connected at the VDD pin 1 provides the DC bias voltage required by the ISL54200 part for proper operation The ISL54200 can be operated with a VDD voltage in the range of 2 7V to 5 5V When used in a USB application the VDD voltage should be kept in the range of 3 0V to 5 5V to ensure you get the proper signal levels for good signal quality A 0 01pF or 0 1pF decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part The capacitor should be located as close to the VDD pin as possible L
6. 0 85 C z 40 5 0 Ki 50 ae 25 C a S N 60 z 70 4 0 S gt 80 al 90 110 3 o 0 1 0 2 0 3 0 4 v v 0 001 0 01 0 1 1 10 100 500 COM FREQUENCY MHz FIGURE 12 HSx SWITCH ON RESISTANCE vs SWITCH FIGURE 13 OFF ISOLATION VOLTAGE 10 Ry 459 20 Vin 0 2Vp _p TO 2Vp_p 2 30 z z 40 E Ki O 50 S N 60 Ny z 70 gt 80 90 110 0 001 0 01 0 1 1 10 100 500 FREQUENCY MHz FIGURE 14 CROSSTALK Die Characteristics SUBSTRATE AND TDFN THERMAL PAD POTENTIAL POWERED UP GND TRANSISTOR COUNT 98 PROCESS Submicron CMOS 15 intersil FN6408 2 June 17 2010 ISL54200 Revision History DATE REVISION CHANGE 5 17 10 FN6408 2 Updated Pb free bullet in Features on page 1 and Pb free notes 3 and 4 in Ordering Information on page 2 per Mark Kwoka s new verbiage based on lead finish Added TB347 link note 2 to Ordering Information on page 2 for reel specifications In Thermal Information on page 4 added 0jc for both TDFN and uTQFN packages Updated Oja for UTQFN from 140 to 145 Added applicable 8j 0jc notes 7 through 10 Changed Positive Supply Current IDD on page 6 for full temp from 80nA to 500nA Limit changes required to improve yield PCN required Changes to L10 2 1x1 6A on page 17 as fol
7. D TRANSCEIVER USB FULL SPEED TRANSCEIVER PORTABLE MEDIA DEVICE 12Mbps differential signals and meet the USB 2 0 full speed signal quality specifications See Figure 8 The FSx switches can also pass USB high speed signals 480Mbps but do not quite meet the USB 2 0 high speed signal quality eye diagram compliance requirement The maximum signal range for the FSx switches is from 1 5V to Vpp The signal voltage should not be allowed to exceed the Vpp voltage rail or go below ground by more than 1 5V When operated with a 2 7V to 3 6V supply the FSx switches are active turned ON whenever the IN logic control voltage is lt 0 5V and the EN logic voltage gt 1 4V HSx Switches HSD1 HSD2 The two HSx switches HSD2 HSD1 are bi directional switches that can pass rail to rail signals When powered with a 3 3V supply these switches have a nominal ron of 4 5Q over the signal range of OV to 400mV with a ron flatness of 0 4Q The roy matching between the HSD1 and HSD2 switches over this signal range is only 0 019 ensuring minimal impact by the switches to USB high speed signal transitions As the signal level increases the ron switch resistance increases At signal level of 3 3V the switch resistance is nominally 200 The HSx switches were specifically designed to pass USB 2 0 high speed 480Mbps differential signals typically in the range of OV to 400mV They have low capacitance and high bandwidth to pass the USB
8. FORE MAKE TIME VDD ron V1 40mA ron V1 ICOMx VHSX Repeat test for all switches Repeat test for all switches FIGURE 3 HSx SWITCH roy TEST CIRCUIT FIGURE 4 FSx SWITCH roy TEST CIRCUIT 7 x z FN6408 2 intersil June 17 2010 ISL54200 Test Circuits and Waveforms continued VDD HSx or FSx IMPEDANCE ANALYZER Repeat test for all switches o VINL OR VINH FIGURE 5 CAPACITANCE TEST CIRCUIT DIN DIN OUT OUT 50 l gt lt tskew_o FIGURE 7A MEASUREMENT POINTS FIGURE 7 SIGNAL GENERATOR 452 Signal direction through switch is reversed worst case values are recorded Repeat test for all switches FIGURE 6 CROSSTALK TEST CIRCUIT VIN 15 82 DIN 1439 15 89 DIN 14392 GND tro tri Delay Due to Switch for Rising Input and Rising Output Signals tfo tfi Delay Due to Switch for Falling Input and Falling Output Signals tskew_0O Change in Skew through the Switch for Output Signa tskew_i Change in Skew through the Switch for Input Signals FIGURE 7B TEST CIRCUIT SKEW TEST 8 intersil FN6408 2 June 17 2010 ISL54200 Application Block Diagram D D E H H z z Oo D v Detailed Description The ISL54200 device is a dual single pole double throw SPDT analog switch that operates from a single DC power supply in the range of 2 7V to 5 5V It was designed to function as a dual 2 to 1 multi
9. OGIC CONTROL The state of the ISL54200 device is determined by the voltage at the IN pin pin 2 and the EN pin pin 10 IN is only active when the EN pin is logic 1 High Refer to the Truth Table on page 3 The EN pin is internally pulled low through a 4MQ resistor to ground For logic 0 Low it can be driven low or allowed to Float The IN pin must be driven low or high and cannot be left floating Logic Control Voltage Levels EN Logic 0 Low when Ven lt 0 5V or Floating EN Logic 1 High when Ven zl AN IN Logic 0 Low when Vy lt 0 5V IN Logic 1 High when Viy 1 4V Full speed Mode If the IN pin Logic 0 and the EN pin Logic 1 the part will be in the full speed mode In this mode the FSD1 and FSD2 switches are ON and the HSD1 and HSD2 switches are OFF high impedance In a typical application Vpp will be in the range of 2 8V to 3 6V and will be connected to the battery or LDO of the portable media device When a computer or USB hub is plugged into the common USB connector and the part is in the full speed mode a link will be established between the full speed driver section of the media player and the computer The device will be able to transmit and receive data from the computer at a data rate of 12Mbps High speed Mode If the IN pin Logic 1 and the EN pin Logic 1 the part will go into high speed mode In high speed mode the
10. OLTAGE SCALE 0 1V DIV Differential Signal V 0 0 0 2 04 06 0 8 1 0 1 2 14 1 6 1 8 2 0 gt Time x10 9 s TIME SCALE 0 2ns DIV FIGURE 9 EYE PATTERN WITH FAR END MASK 480MBPS USB SIGNAL WITH HSx SWITCHES IN THE SIGNAL PATH 12 i P FN6408 2 intersil June 17 2010 ISL54200 Typical Performance Curves Ta 25 C Unless Otherwise Specified Continued VOLTAGE SCALE 0 1V DIV Differential Signal Y 0 0 0 2 04 0 6 0 8 1 0 1 2 14 1 6 1 8 2 0 gt Time x10 9 s TIME SCALE 0 2ns DIV FIGURE 10 EYE PATTERN WITH NEAR END MASK 480MBPS USB SIGNAL WITH HSx SWITCHES IN THE SIGNAL PATH 13 Dn P FN6408 2 intersjl June 17 2010 ISL54200 Typical Performance Curves Ta 25 C Unless Otherwise Specified Continued VOLTAGE SCALE 0 5V DIV D D Signals V 0 0 1 0 2 0 3 0 40 5 0 6 0 7 0 8 0 gt Time x10 8 s TIME SCALE 10ns DIV FIGURE 11 EYE PATTERN 12MBPS USB SIGNAL WITH HSx SWITCHES IN THE SIGNAL PATH 14 i D FN6408 2 intersjl June 17 2010 ISL54200 Typical Performance Curves Ta 25 C Unless Otherwise Specified Continued 6 0 10 V 3 3V Ri 459 Icom 40mA 20 vm 0 2Vp_p TO 2Vp p 5 5 RA E 1 3
11. Vpp 3 3V RL 450 C 10pF See Figure 1 25 15 7 ns Break Before Make Time Delay tp Vpp 3 3V RL 45 C 10pF See Figure 2 25 7 ns Skew tsxew Vpp 3 3V IN 3 3V EN 3 3V Ry 459 25 50 ps HSx Switch CL 10pF tr tp 720ps at 480Mbps Duty Cycle 50 See Figure 7 Total Jitter ty Vpp 3 3V IN 3 3V EN 3 3V RL 459 25 210 ps HSx Switch CL 10pF tp tr 720ps at 480Mbps Propagation Delay tpp Vpp 3 3V IN 3 3V EN 3 3V RL 459 25 250 S DS HSx Switch C 10pF See Figure 7 Skew tsxew Vpp 3 3V IN OV EN 3 3V RL 399 25 0 15 7 ns FSx Switch C 50pF tp tr 12ns at 12Mbps Duty Cycle 50 See Figure 7 Rise Fall Time Mismatch tm Vpp 3 3V IN OV EN 3 3V RL 399 25 10 FSx Switch CDs 50pF tp tf 12ns at 12Mbps Duty Cycle 50 Total Jitter ty Vpp 3 3V IN OV EN 3 3V RL 399 25 1 6 F ns FSx Switch C 50pF tp tf 12ns at 12Mbps Propagation Delay tpp Vpp 3 3V IN OV EN 3 3V RL 399 25 0 9 7 ns FSx Switch C 50pF See Figure 7 Crosstalk Vpp 3 3V RL 450 f 1MHz See Figure 6 25 7 70 dB Off Isolation Vpp 3 3V Rr 450 f 100kHz 25 98 dB FSx Switch 3dB Bandwidth Signal 10dBm 1 0VDC offset RL 459 25 550 S MHz CL 5pF HSx Switch 3dB Bandwidth Signal 10dBm 0 2VDC offset RL 459 25 880 MHz C SpF HSx OFF Capacitance Cysxorr f 1MHZ Vp
12. ation Thermal Resistance Typical 10 Ld uTQFN Notes 7 8 10 Ld TDFN Notes 9 10 Maximum Junction Temperature Plastic Package Dia C W Oe C W 145 90 55 16 5 Maximum Storage Temperature Range Pb free reflow profile http www intersil com pbfree Pb FreeReflow asp Operating Conditions Temperature Range Vpp Supply Voltage Range 150 C 65 C to 150 C see link below 40 C to 85 C 2 7V to 5 5V CAUTION Do not operate at or near the maximum ratings listed for extended periods of time Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty NOTES 6 Signals on FSD1 FSD2 HSD1 HSD2 COMD1 COMD2 EN IN exceeding Vpp or GND by specified amount are clamped Limit current to maximum current ratings 7 Dua is measured with the component mounted on a high effective thermal conductivity test board in free air See Tech Brief TB379 for details 8 For jc the case temp location is taken at the package top center 9 0jq is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features See Tech Brief TB379 10 For 0jc the case temp location is the center of the exposed metal pad on the package underside Electrical Specifications 2 7V to 3 6V Supply Test Conditions Vpp 3 3V GND OV Viqy 1 4V Vint 0 5V Veny 1 4V VenL 0 5V
13. interii USB 2 0 High Full Speed Multiplexer ISL54200 The Intersil ISL54200 dual 2 1 multiplexer IC is a single supply part that can operate from a single 2 7V to 5 5V supply It contains two SPDT Single Pole Double Throw switches configured as a DPDT The part was designed for switching between USB High Speed and USB Full Speed sources in portable battery powered products The 79 normally closed NC FSx switches can swing rail to rail and were specifically designed to pass USB full speed data signals 12Mbps that range from OV to 3 6V The 4 59 normally open NO HSx switches have high bandwidth and low capacitance and were specifically designed to pass USB high speed data signals 480Mbps with minimal distortion The part can be used in Personal Media Players and other portable battery powered devices that need to switch between a high speed transceiver and a full speed transceiver while connected to a single USB host computer The digital logic inputs are 1 8V logic compatible when operated with a 2 7V to 3 6V supply The part has an enable pin to open all switches It can be used to facilitate proper bus disconnect and connection when switching between the USB sources The ISL54200 is available in a 10 Ld 3mmx3mm TDFN and a small 10 Ld 2 1mmx1 6mm uTOEN package It operates over a temperature range of 40 C to 85 C Application Block Diagram VDD ISL54200 Ki bei Ex H H z z e H a v Feature
14. ise Specified Bold face limits apply over the operating temperature range 40 C to 85 C Continued TEMP MIN MAX PARAMETER TEST CONDITIONS C Notes 12 13 TYP Notes 12 13 UNITS ON Resistance ron Vpp 3 3V IN 1 4V EN LAN Icomx 1mA 25 20 30 Q V or V 3 3V See Figure 3 HSD2 Or VHsD1 igure 3 Full 35 S ON Resistance ron Vpp 3 3V IN 1 4V EN LAN Icom 40mA 25 4 5 6 Q Vv VM OV to 400mvV See Fi HSD2 Or Musep O mV See Figure 3 Full 8 Se ron Matching Between Vpp 3 3V IN 1 4V EN 1 4V Icomx 40mA 25 0 01 0 1 Q Channels Aron Vusp2 or Vusp1 Voltage at max roy Voltage at Full o max ron over signal range of OV to 400mV 5 5 7 dt S Note 15 ron Flatness rFLAT ON Vpp 3 3V IN 1 4V EN 1 4V Icom 40mA 25 0 4 1 Q V V OV to 400mvV Note 14 HSD2 Or VHsp1 o Full S 15 5 OFF Leakage Current Vpp 3 6V IN OV EN 0 and 3 6V Vcomp 25 20 2 20 nA I or I or V 3V 0 3V V or V 0 3V HSD2 OFF OF 4 HSD1 OFF Se COMD2 HSD2 OF VHSD1 Full 70 70 nA ON Leakage Current Iysp2 on Vpp 3 6V IN 3 6V EN 3 6V Vcompi or 25 20 2 20 nA orl V 0 3V 3 0V V or V 0 3V r 4HSD1 ON mor HSD2 OF VHSD1 Full 70 70 nA DYNAMIC CHARACTERISTICS Turn ON Time tony Vpp 3 3V RL 459 C 10pF See Figure 1 25 S 25 ns Turn OFF Time torr
15. lows Converted to new POD format Moved dimensions from table onto drawing Corrected leadframe thickness in Detail x from 0 2 REF to 0 125 REF Corrected Note 4 to read between 0 15mm and 0 30mm it previously read IT between 015mm and 0 30mm Corrected the word indentifier in Note 8 to read identifier Changes to L10 3x3A on page 18 as follows Added Typical Recommended Land Pattern Put into new data sheet format Changes include Addd Related Literature see page 16 on page 1 Added MSL note 5 to Ordering Information on page 2 Added Boldface limits apply over the operating temperature range 40 C to 85 C to common conditions of Electrical Specfications table beginning on page 4 Bolded applicable specs Added Products on page 16 Added Revision History on page 16 Updated the Pin Descriptions on page 3 to show the thermal pad Added latch up level to Absolute Maximum Ratings on page 4 7 11 07 FN6408 1 Made changes to Pin Descriptions on page 3 Made changes to Bandwidth in DYNAMIC CHARACTERISTICS on page 5 On page 11 to page 14 made changes to eye diagram axis labels Products Intersil Corporation is a leader in the design and manufacture of high performance analog semiconductors The Company s products address some of the industry s fastest growing markets such as flat panel displays cell phones handheld products and notebooks In
16. mum allowable burrs is 0 076mm in all directions 7 Same as JEDEC MO 255UABD except No lead pull back MIN Package thickness 0 45 not 0 50mm Lead Length dim 0 45mm max not 0 42mm The configuration of the pin 1 identifier is optional but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature 17 Dn D FN6408 2 intersil June 17 2010 ISL54200 Thin Dual Flat No Lead Plastic Package TDFN B TOP VIEW B 0 10 c A E y A 0 08 c Cc SIDE VIEW A3 SEATING PLANE DATUM B INDEX UU AREA NX k SE DATUM A me Nd 1 Xe gt 010 clalB REF W BOTTOM VIEW K Ser NX Kee L1 AdS a e SECTION C C cc TERMINAL TIP FOR ODD TERMINAL SIDE L10 3x3A 10 LEAD THIN DUAL FLAT NO LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0 70 0 75 0 80 A1 0 05 A3 0 20 REF b 0 20 0 25 0 30 5 8 D 2 95 3 0 3 05 D2 2 25 2 30 2 35 7 8 E 2 95 3 0 3 05 E2 1 45 1 50 1 55 7 8 e 0 50 BSC k 0 25 L 0 25 0 30 0 35 8 N 10 2 Nd 5 3 Rev 4 8 09 NOTES 1 Dimensioning and tolerancing conform to ASME Y14 5 1994 Nis the number of terminals Nd refers to the number of terminals on D All dimensi
17. on page for ISL54200 For more information on MSL please see techbrief TB363 2 _intersil FN6408 2 June 17 2010 ISL54200 Truth Table Pin Descriptions ISL54200 ISL54200 EN IN FSD1 FSD2 HSD1 HSD2 PIN NO NAME FUNCTION 1 0 ON OFF 1 VDD Power Supply 1 1 OFF ON 2 IN Select Logic Control Input 0 X OFF OFF 3 COMD1 USB Common Port Logic 0 when lt 0 5V Logic 1 when zt AN with a 2 7V to 4 COMD2 USB Common Port SREP RES Dont carg 5 GND Ground Connection 6 FSD2 Full Speed USB Differential Port 7 FSD1 Full Speed USB Differential Port 8 HSD2 High Speed USB Differential Port 9 HSD1 High Speed USB Differential Port 10 EN Bus Switch Enable PD Thermal Pad Tie to Ground or Float TDFN package only FN6408 2 3 i s intersil June 17 2010 ISL54200 Absolute Maximum Ratings VDD to GND i ios igo eee ee 0 3V to 6 0V Input Voltages FSD2 FSD1 HSD2 HSD1 Note 6 1V to Vpp 0 3V IN EN Note ei 0 3V to Vpp 0 3V Output Voltages COMD1 COMD2 Note 6 000008 1V to 5V Continuous Current HSD2 HSD1 FSD2 FSD1 40mA Peak Current HSD2 HSD1 FSD2 FSD1 Pulsed ims 10 Duty Cycle Max 100mA ESD Rating ABMs rse ae a ee ee EE PA ee eee gt 7kV MM fc en eee eee eee SSE eR gt 400V E EINEN gt 1 4kV Latch up Tested per JEDEC Class II LevelA at 85 C Thermal Inform
18. ons are in millimeters Angles are in degrees ar WN Dimension b applies to the metallized terminal and is measured between 0 15mm and 0 30mm from the terminal tip 6 The configuration of the pin 1 identifier is optional but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature 7 Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance 8 Nominal dimensions are provided to assist with PCB Land Pattern Design efforts see Intersil Technical Brief TB389 9 Compliant to JEDEC MO 229 WEED 3 except for D2 dimensions 2 30 me 10X 0 50 1 50 2 90 hor Pin oe ate 8x 0 a 10X 0 25 TYPICAL RECOMMENDED LAND PATTERN 18 intersil FN6408 2 June 17 2010
19. p 3 3V IN OV EN 3 3V 25 6 pF Vuspi or VHsp2 Vcomx OV See Figure 5 5 FN6408 2 intersil June 17 2010 ISL54200 Electrical Specifications 2 7V to 3 6V Supply Test Conditions Vpp 3 3V GND OV Vinny LAN Vint 0 5V VENH LAN Vew 0 5V Note 11 Unless Otherwise Specified Bold face limits apply over the operating temperature range 40 C to 85 C Continued TEMP MIN MAX PARAMETER TEST CONDITIONS C Notes 12 13 TYP Notes 12 13 UNITS FSx OFF Capacitance Crsxorr f 1MHz Vpp 3 3V IN 3 3V EN 3 3V 25 9 J pF Vesp1 Or Vesp2 Vcomx OV See Figure 5 COM ON Capacitance f 1MHz Vpp 3 3V IN 3 3V EN 3 3V 25 12 S pF Ccomx on Vusp1 or VHsp2 Vcomx OV See Figure 5 COM ON Capacitance f 1MHz Vpp 3 3V IN OV EN 3 3V 25 15 pF Ccomx on Vespi or Vesp2 Vcomx OV See Figure 5 POWER SUPPLY CHARACTERISTICS Power Supply Range Vpp Full 2 7 7 5 5 V Positive Supply Current Ipp Vpp 3 6V IN OV or 3 6V EN OV or 3 6V 25 20 60 nA Full 7 500 nA DIGITAL INPUT CHARACTERISTICS Input Voltage Low Vint VenL Vpop 2 7V to 3 6V Full 0 5 Input Voltage High Vino VENH Vpp 2 7V to 3 6V Full 1 4 Input Current Itn IENL Vpp 3 6V IN OV EN OV Full 10 nA Input Current Irwn Vpp 3 6V IN 3 6 Full 10 nA Input Current Iewn Vpp 3 6V EN 3 6 Full 1 pA
20. plexer to select between a USB high speed transceiver and a USB full speed transceiver in portable battery powered products It is offered in a TDFN package and a small HTQFN package for use in MP3 players cameras PDAs cellphones and other personal media players The device has an enable pin to open all switches The part consists of two 7Q full speed FSx switches and two 4 5Q high speed HSx switches The FSx switches can swing from OV to Vpp They were designed to pass USB full speed 12Mbps differential data signals with minimal distortion The HSx switches have high bandwidth and low capacitance to pass USB high speed 480Mbps differential data signals with minimal edge and phase distortion The ISL54200 was designed for MP3 players cameras cellphones and other personal media player applications that have both high speed and full speed transceivers and need to multiplex between these USB sources to a single USB host computer A typical application block diagram of this functionality is shown on page 9 A detailed description of the two types of switches are provided in the following sections FSx Switches FSD1 FSD2 The two FSx switches FSD1 FSD2 are bidirectional switches that can pass rail to rail signals When powered with a 3 3V supply these switches have a nominal ron resistance of 7Q over the signal range of OV to 3 3V They were specifically designed to pass USB full speed HCONTROLLER USB HIGH SPEE
21. s High Speed 480Mbps and Full Speed 12Mbps Signaling Capability per USB 2 0 1 8V Logic Compatible 2 7V to 3 6V supply Enable Pin to Open all Switches 3dB Frequency HSx Switches ce es 880MHz FSx Switches e 550MHz e Crosstalk IM 70dB e Off Isolation 100kKHz 98dB e Single Supply Operation Vpp 2 7V to 5 5V Available in Ultra thin uTQFN and TDFN Packages Pb Free RoHS Compliant Applications see page 16 e MP3 and other Personal Media Players e Cellular Mobile Phones e PDA s e Digital Cameras and Camcorders Related Literatu re see page 16 e Technical Brief TB363 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices SMDs e Application Note AN1330 ISL54200EVAL1iZ Evaluation Board User s Manual HCONTROLLER HIGH SPEED TRANSCEIVER FULL SPEED TRANSCEIVER PORTABLE MEDIA DEVICE June 17 2010 1 FN6408 2 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 1 888 468 3774 Intersil and design is a registered trademark of Intersil Americas Inc Copyright Intersil Americas Inc 2007 2010 All Rights Reserved All other trademarks mentioned are the property of their respective owners ISL54200 Pin Configurations ISL54200 10 LD TDFN TOP VIEW VDD COMD1 IN COMD2 gt COMD1 COMD2 NOTE 1 ISL54200 Switches Shown
22. tersil s product families address power management and analog signal processing functions Go to www intersil com products for a complete list of Intersil product families For a complete listing of Applications Related Documentation and Related Parts please see the respective device information page on intersil com ISL54200 To report errors or suggestions for this datasheet please go to www intersil com askourstaff FITs are available from our website at http rel intersil com reports search php For additional products see www intersil com product_tree Intersil products are manufactured assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www intersil com design quality Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its produc
23. ts see www intersil com 16 i P FN6408 2 intersil June 17 2010 ISL54200 Package Outline Drawing L10 2 1x1 6A 10 LEAD ULTRA THIN QUAD FLAT NO LEAD PLASTIC PACKAGE Rev 5 3 10 PIN 1 INDEX AREA i 2 10 HA PIN 1 ID ur 0 05 MIN p bo K s E 4X 0 20 MIN 3 10 5 l l 0 80 I 10X 0 40 0 4013 5 i 2X 6X 0 50 JL 40x 0 20 4 TOP VIEW 0 10 Cc AlB BOTTOM VIEW Ka wje Dasmi SEE DETAIL X p 10X 0 20 a PACKAGE EA 1 Ya OUTLINE 8 10X 0 60 0 10 z _ 0 10 MIN el ais SEATING PLANE 0 08 C 2 00 2 00 Jan SIDE VIEW L 1 30 l l Laast f S r 125 REF 6X 0 50 El I B en L 0 0 05 TYPICAL RECOMMENDED LAND PATTERN DETAIL X NOTES 1 Dimensioning and tolerancing conform to ASME Y14 5M 1994 2 All Dimensions are in millimeters Angles are in degrees Dimensions in for Reference Only 3 Unless otherwise specified tolerance Decimal 0 05 Lead width dimension applies to the metallized terminal and is measured between 0 15mm and 0 30mm from the terminal tip 5 Maximum package warpage is 0 05mm 6 Maxi
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