SingMai Electronics
Contents
1. 1 for the selected standard 11 bit word Vcount_length_ R W 2 0 Vcount_length_2 2 0 Vcount_length_1 7 0 Default value Vout_start_1 Start position of vertical sync output 11 bit word 31 Vout start 1 R W 2 0 Vout start 2 2 0 Vout start 1 7 0 Default value Dun D into BW 20 Test 1 fine Vout end 1 End position of vertical sync output 11 bit word 33 Vout end 1 BW 2 0 Vout end 2 2 0 Vout end 1 7 0 h Default value 54 o 720p 60Hz 1 LSB 1 line Start position of vertical blanking output 11 bit word 35 VBlank start 1 BW 2 0 VBlank_start_2 2 0 VBlank_start_1 7 0 Default value 74510 720p 60Hz 1 LSB 1 line End position of vertical blanking output 11 bit word 37 VBlank end 1 R W 2 0 VBlank_end_2 2 0 VBlank_end_1 7 0 Default value 2040 720p 60Hz 1 LSB 1 line SVBlank_start_1 Start position of short vertical blanking output burst blanking 39 SVBlank start 1 R W 2 0 11 bit word SVBlank_start_2 2 0 SVBlank_start_1 7 0 Default value 74419 720p 60HZz 1 LSB 1 line SA SVBlank end 1 end 1 End position of short vertical blanking output burst blanking 3B SVBlank end 1 R W 2 0 11 bit word SVBlank_end_2 2 0 SVBlank_end_1 7 0 es aseene Default value 2 720p 60H2 1 LSB 1 line Procamp 40 Sub_Luma_valu R W 7 0 Value subtracted from luma output to remove synchronizing e 1 pulses if in manual 10 bit word 41 Sub_Luma_valu R W 12. ET ti E Fa ES REA e e E Character Row No 1 32 30 for 525 line i 32 Figure 10 Character mapping The output of the character memory selects one of 128 characters each character is 12 pixels wide 74ns pixel by 16 lines high 112 of the characters are pre programmed see Table 3 16 of the characters are programmable by the user PT22 User Manual Revision 0 5 Page 22 of 28 SingMai Electronics 6 Register interface Figure 9 shows the timing diagram for the register interface it is a conventional microprocessor interface Each register is selected via an 8 bit address bus Writes to unused register locations are ignored To write to the selected register the aCVi_Rx_CSn chip select input must be asserted low Whilst this is low the aCVi Rx WRn must be taken low An internal write enable pulse is created at the next rising edge of the Reg Clk clock and writing occurs at the next clock edge following that enable For the write to occur reliably the address A 7 0 and data Din 7 0 must be stable and valid during the aCVi Rx WRn pulse The minimum width of the aCVi Rx WRn pulse is 2 Reg dk periods or 74ns for a 2 MHz clock The address input also selects the register data that is presented on the aCVi Rx Register out 7 0 bus This output is independent of the other control signals or the Reg Clk clock aCVi Rx CSn 1 ih aCVi Rx WRn Reg clk Generated register write enable Si Data i i
3. SingMai Electronics PT22 Advanced Composite Video Interface Decoder gt MI User Manual Revision 0 5 30 June 2014 PT22 User Manual Revision 0 5 Page 1 of 28 SingMai Electronics Revision History 21 02 2013 First Draft 30 06 2014 Document re written PT22 User Manual Revision 0 5 Page 2 of 28 SingMai Electronics Contents Revision History ccccsecccccseececeseeeeeeceeeeeesseeeeeeseaeeeessaueeesseeeeeeeeeeeeseaueeessaeeessaaeeeessueeesseeeesenaneees 2 ONO NS ss quado E ars saio E ee E ee ee eee 3 DADO sagas meer enn ae EA gs Ee ee ee eee eee 3 FOUG S esate Spa ies 3 Bi WORT UNS NOM EE 4 2 PT22 Module description cccccccccceecseeeeeeeceaeeeeeeeeeaeeseeeeeeseeseeeesseaaeeeeessaaeeeeeesaagseeeeeeas 9 3 Signal Interconnechons e eeeeereeeeeererenan ana rere aaa ane ereeaa narra eaa aa rerennaa 6 SEENEN 9 SR Klee OV E 11 aC VI 21610 2 tee 11 aC Vi Fx REGISTER ei te KE 11 GV EE 12 ES DEMOL EE 13 Le E EE 14 OLEO o pq EE 16 DE EE ee 16 Tee le DEE 17 le 17 GOVE ENEE 19 6 Rogister MAL CN EE 23 EN Geiger le 2 EE 24 0 E Elei COMMU ON EE 27 Tables Table 1 PT22 Altera FPGA resource requirement cccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeseeeeeeeeesaaaaees 4 Table 2 PT22 Verilog file structure ccccceeecccccsesseccecceeeeeeeeeceeaeeceeseeeaeeeeesseaaeeeeessaaeeeeessaages 5 Table 3 PT22 Input Output signals cc ccccccccc
4. a control voltage the PT22 has an 8 bit register PGA control which can be used to control a pulse width modulator Example Verilog code for a PWM as used on the evaluation boards is shown below PWM control of PGA Generate 100kHz always posedge XTAL_clk or negedge RESETn begin if RESETn begin Counter 100k lt 5 d0 end else if Counter 100k 4 0 5 d26 begin Counter 100k lt 5 d0 end else begin Counter 100k lt Counter 100k 5 d1 end end PWM counter always posedge XTAL_clk or negedge RESETn begin if IRESETn begin PWM counter lt 8 d0 end else if Counter 100k 4 0 5 d26 begin PWM counter lt PWM counter 8 d1 end else begin PWM counter lt PWM counter end PT22 User Manual Revision 0 5 Page 27 of 28 SingMai Electronics end always O posedge XTAL clk or negedge RESETn begin if IRESETn begin PWM latch lt 1 b0 end else if Counter 100k 4 0 5 d26 begin if PWM counter 8 d0 begin PWM latch lt 1 b1 end else if PWM counter PGA gain 7 0 begin PWM latch lt 1 b0 end else begin PWM latch lt PWM latch end end else begin PWM latch lt PWM latch end end Note PWM Gain control is inverted on DP17 assign Gain PWM_latch The output Gain is a PWM signal whose width is controlled by the PGA control register This output may then be low pass filtered to produce an analogue control voltage do 5Y A C18 ji 1808n U7 W CL
5. EE E UR CIR RR PR CR RD RSA SEND OR DEE PEER E PDR A ENVIEI RE RREO ena EE A Magnitude in dB TTT TTT DT 8 ZEN oa E fes DTN E TEE des DEEG E TTT Ti TEE D I ETH D OTTEN Di Frequency in MHz Figure 4 Chroma demodulator low pass filter aCVi SPG v The luma output from the comb filter with the subcarrier removed is further low pass filtered to reduce noise The response of this filter an 11 tap FIR is shown in Figure 5 Inphase Filter Frequency Response E E deseo ra praia nar o areias Magnitude in dB N O T E E E E E E E T T E E T C E E E T Reeder dd o Add iert dedi iert id la Cd al aa Peete Cee Cee CCRC CeCe AR Naa AR Man AR Nan AR E EEER ANIMAR ORAR EN ERE aan nan Frequency in MHz Figure 5 Sync filter frequency response PT22 User Manual Revision 0 5 Page 14 of 28 SingMai Electronics A fixed offset is subtracted from the low pass filtered luma video such that the midpoint of the sync pulse is at value 0 Values 1 44 from the horizontal counter address a look up table whose output coefficients form a FIR low pass filter to further reduce noise from the composite video The coefficients are multiplied by the offset video and accumulated across the 44 samples being updated once per horizontal line The frequency response of the sync filter is shown in Figure 6 Inphase Filter Frequency Response Magnitude in dB Frequency in MHz Figure 6 Phase detector low pass filter response When the midpo
6. aCVi Cmux is high 87 125MHz data rate 4 2 2 format aCVi Crout 9 is the MSB aCVi Cmux Data valid output for Cb and Cr outputs Cb and Cr data is valid on the rising edge of Clk74 when aCVi Cmux is high 4 2 2 data format aCVi Hout Horizontal sync output from decoder active low aCVi Vout Vertical sync output from decoder active low aCVi Fout Frame sync output from decoder low for field 1 Only valid during interlaced video formats aCVi Rx WRn aCVi HBlank Horizontal blanking output from decoder aCVi_VBlank Vertical blanking output from decoder Pulse width modulated output for the control of the analogue input stage voltage controlled amplifier AGC VCO PWM Pulse width modulated output for the control of external voltage controlled oscillator frequency VCO control voltage aCVi test 1 0 Test outputs Do not connect Table 3 PT22 Input Output signals The Verilog instantiation of PT22 is shown below Instantiate aCVi decoder PT22 aCVi_decoder aCVi_decoder_inst CIk74 CIk74 sig input CIk74 sig Clk148 CIk148_sig input CIk148 sig Reg_clk Reg_clk_sig input Reg_clk_sig RESETn RESETn_sig input RESETn_sig PT22 User Manual Revision 0 5 Page 7 of 28 SingMai Electronics ORNG ORNG sig aCVi_in aCVi_in_sig A A_sSig Din Din_sig aCVi Rx CSn aCVi Rx CSn sig SCHT CG CSn aCVi CG CSn sig aCVi Rx WRn aCVi Rx WRn sig aCVi Rx Register o
7. used which has an aperture of 3 lines 1 4 0H 1 2 1H 1 4 2H 1 line spacing For the comb filter to operate correcily the phase relationship of the colour component must be maintained If not the HF luma will not be cancelled and can even be reinforced It is therefore necessary to detect when the comb filter fails and switch to another mode Normally this failure mode is detected using luminance differences across the comb taps but there are instances where the same luminance value can occur but there are different chroma values which still cause the comb to fail The SC10 comb adaptation detects value differences in luma U and V comb taps thereby detecting all comb failure instances The output of the comb filter is combed U and V without high frequency luma The combed chroma signal is then frequency shifted back to the subcarrier frequency and subtracted from the low pass filtered aCVi video The sine and cosine waveforms from the demodulator are delayed to compensate for the low pass filter delay the waveforms are then multiplied by the combed U and V outputs and then added together to reconstruct a chrominance signal centred on the aCVi referenced subcarrier frequency This chrominance signal is then subtracted from the delayed low pass filtered luma video which provides a clean luma signal with no residual chroma aCVi_measure v The aCVi decoder makes a number of measurements of the video signal to aid in it automatic adaption and
8. 0 Sub Luma value 2 1 0 Sub Luma value 1 7 0 Default e 2 value 46010 Ygain value 1 Luma gain control 10 bit word Ygain value 2 voam value 2 1 0 Ygain value 1 7 0 Default value 7 74610 Ugain_value_1 7 0 Chroma B Y gain control 10 bit word Ugain value 2 Ugain value 2 1 0 Ugain value 1 7 0 Default value E E 51240 Vgain_value_1 0 Chroma R Y gain control 10 bit word 47 Vga value 2 value 2 Ugain value 2 1 0 Ugain value 1 7 0 Default value 91210 wel Tat ACC gain control value for demodulator default 6440 demod_value eva ACC gain control value for remodulator default 6410 remod value Status and Measurement PT22 User Manual Revision 0 5 Page 25 of 28 SingMai Electronics Register Register Name R W Bit Description Offset Value Measured negative peak value of the filtered luma video sync value 1 tip value 10 bit value Negative peak BEER Negative_peak_value_1 7 0 Negative_peak_value_2 1 0 value_2 Kata BP_value Measured back porch value of the filtered luma video black level 10 bit value Geer Video BP_value Bk Video_BP_value_1 7 0 Video_BP_value_2 1 0 54 Burst amplitude R 7 0 Measured peak U burst amplitude value Motors Field Rat ey Measured input video field rate field second H this bit high it indicates the video input ADC has overflowed video gain too high e ee a Scioversionnumber SSS
9. C1003 Figure 13 PWM analogue control Figure 7 shows the circuit used on the DP17 evaluation module The PWM gain signal is first buffered to move it from the digital powered circuit to the cleaner analogue power That output is low pass filtered R8 C17 to produce an analogue output This is then buffered by U7 the output of which drives the AD8337 control voltage input PT22 User Manual Revision 0 5 Page 28 of 28
10. DOE III Data Insertion control 60 Data_Instruction R W 3 0 Instruction word to be transmitted between receiver and transmitter Data Word Data word to be transmitted between receiver and transmitter 62 Tx_status Not used When the data word is written for transmission register 4D this bit will be set to 1 When the data has been transmitted the next occurring line 8 the flag will be reset to 0 New data should not be written for transmission while this flag is high Rx_Data_instruc pet Received data instruction tion Rx_Data_word OR Received data word ssi data word 505 DR Calculated instruction word parity 4 Received instruction word parity Coz Need OO 2 ZEEE data word parity O Received data word parity Table 8 Register description PT22 User Manual Revision 0 5 Page 26 of 28 SingMai Electronics 8 PGA amplifier control For more flexibility the analogue front end can utilize a programmable gain amplifier allowing automatic gain control to compensate automatically for cable length The evaluation board uses an Analog Devices AD8337 voltage controlled amplifier for this purpose The control voltage gain response for the AD8337 is shown in Figure 6 30 GAIN dB STIN ITT 05575 003 800 600 400 200 0 200 400 600 800 Veain mV Figure 12 AD8337 PGA gain response As the AD8337 is power from a single supply 5V the OmV gain point is at 2 5V To provide
11. UE 13 PWM analogue COMI Ol EE 28 PT22 User Manual Revision 0 5 Page 3 of 28 SingMai Electronics 1 Introduction PT22 is a decoder IP intellectual property core compatible with the aCVi Advanced Composite Video Interface aCVi is a method to transmit HD video over existing RG 59 UTP coaxial twisted pair cable networks or allow the use of less expensive RG 59 UTP coaxial twisted pair cable in long distance installations Details on the interface may be found here http www singmai com acvi aCVi technology htm The decoder IP accepts digital aCVi encoded video at 10 bit resolution which it decodes to a 20 bit YCbCr BT601 format output with separate horizontal and vertical synchronizing pulses and 74 25MHz clock PT22 supports 720p 50Hz 720p 60Hz 1080p 25Hz 1080p 30Hz 1080p 50Hz and 1080p 60Hz but may also be readily adapted to other standards and also non standard video formats such as VESA formats Control and status registers are written to and read from using a conventional 8 bit wide microprocessor interface The intellectual property block is provided as RTL compliant Verilog 2001 source code for FPGAs from all vendors or for ASICs Typical resource usage for an Altera FPGA is shown in Table 1 Logic Cells Memory Bits M9K blocks 9x9 Multipliers 18x18 multipliers 10375 349952 4 Table 1 PT22 Altera FPGA resource requirements An approximate equivalent for ASIC resource usage is 11623 LCs including mu
12. a BI E o EE Mp E E EE 18 Interface test Table 6 aCVi Control words Transmitter gt Receiver The next three bits must be a 010 sequence to ensure the uniqueness of the framing byte The next 9 bits are the data for that control function This is an 8 bit byte with any value between O and 255 The data byte is separated into nibbles each of 4 bits separated by a 0 again to ensure the uniqueness of the framing byte The last two bits are parity bits one for the control word and one for the data word The parity bits are both even parity The total length of the data sequence is 27 bits Each symbol bit is 32 x 1 74 25MHz long 430ns The low bit rate ensures that the data is received over long cable lengths even if the pre emphasis is incorrectly set the symbol length equates to a 2 23MHz data rate which is attenuated lt 2dB 100m of cable PT22 User Manual Revision 0 5 Page 18 of 28 The total data sequence length is just under 12us and it should be positioned centrally in the active video period although the exact position is not important The pre defined video lines used for the transfer of data are the same for all standards Data is transmitted between transmitter to receiver on Line 7 and between receiver and transmitter on line 8 The process to send data is the same for transmitter and receiver First the control word must be written to the register 48 Next the data word is written to regis
13. ackground only but no character Note3 No character Table 7 Character generator map The sync pulse generator detects the embedded TRS signals in the BT656 stream and generates horizontal and vertical addresses for the character memory Each horizontal row of characters is 64 bytes long of which the first 60 are displayed There are 32 rows of characters for 625 line formats and 30 rows for 525 line formats The addressing of the character is shown graphically in Figure 10 The character display is linearly memory mapped Each horizontal row has 64 addressable characters of which only 60 address 0 59 are displayed Address lines A 5 0 are used to select the horizontal character Each column from the top to the bottom of the image is contiguous so the first top row starts at address 0 and finishes at address 63 with addresses 60 63 not displayed The second row staris at address 64 and ends at address 127 with addresses 124 127 not displayed Address lines A 10 6 select one of the 32 rows 30 for 525 lines standards 625 line standards have 576 active displayed lines However 32 rows of characters each character being 16 lines high occupy 512 lines leaving 64 lines or 4 rows that cannot be written to The characters are arranged so that there are 2 rows at the top and bottom of the screen that cannot be written to PT22 User Manual Revision 0 5 Page 21 of 28 SingMai Electronics Character Column No 1 60
14. ary A 8 0 Address bus input used to select the control PT22 User Manual Revision 0 5 Page 6 of 28 SingMai Electronics register character generator location to be written to read from Din 7 0 Control chip select input active low Used in combination with the WRn input to control writing to the control registers aCVi Rx CSn aCVi CG CSn Character overlayl chip select input active low Used in combination with the WRn input to control writing to the character overlay memory Active low write enable input Used in combination with the CSn input to control writing to the control registers and character overlay Outputs Signal Description E al toa Os aCVi Rx Register out 7 0 Control output data bus Outputs the control status register data selected by the A 7 0 bus Note the character overlay is write onl aCVi Yout 9 0 Y luma output from the encoder The output is straight binary blanking level is 64 09 and peak level 96040 The data output is valid at the rising edge of Clk74 aCVi Yout 9 is the MSB aCVi Cbout 9 0 Cb B Y chroma output from the encoder The output is offset binary blanking level is 512 5 The data output is valid at the rising edge of Clk74 when aCVi Cmux is high 37 125MHz data rate 4 2 2 format aCVi Cbout 9 is the MSB aCVi Crout 9 0 Cr R Y chroma output from the encoder The output is offset binary blanking level is 512 0 The data output is valid at the rising edge of Clk74 when
15. ator to generate the sine and cosine waveforms For the demodulation to correctly operate the generated subcarrier must be frequency and phase locked to the aCVi video subcarrier which is done by measuring the amplitude of the demodulated and low pass filtered V output during the colour burst If the frequency and phase of the free running subcarrier and the colour burst are the same then this error will be zero The reference for the BLO is the demodulated and filtered V output from the demodulator low pass filter 32 samples of this waveform are taken during the burst pulse the burst gate pulse from the SPG is used for this purpose The seed word is thus modified using the phase error signal until the input colour burst and the ratio counter are phase locked The aCVi chroma signal is originally generated as follows chroma U sin at V cos at When the burst lock loop BLO is in lock the frequency and phase will be the same as when the signal was being modulated Thus multiplying the aCVi composite video by the sine and cosine of the same frequency and phase gives the following U U sin wt V cos at x sin at U U sin wt V sin at cos at a d cos 2 x eu V J x 2 sin wt cos at U U cos 2 x ot V sin 2 x ot 2 2 2 U PT22 User Manual Revision 0 5 Page 12 of 28 SingMai Electronics and for the V component V U sin at V cos wt x cos at V U sin at cos wt V cos at V x 2 sin at
16. ccsseeeeeeceeeeeeeaeeseeeeeeeeseeeeaeseeeeeeesseaeaeeeeeeeessaaeagess 7 Table 4 SC10 Line and subcarrier frequencies e eeeeeeeereeeee eee rerrreeenada 12 Table 5 Data transfer instructions Receiver gt Transmmtter eee 18 Table 6 aCVi Control words Transmitter gt Heceiver e eeeeereeeeeeeerenananoo 18 Table 7 Character generator Map EE 21 Table 8 Register e E e en EE 26 Figures Figure 1 PT22 Block symbol e eeeeeereee e ereerenen ane erreeaaa a erreana na errenanaaneena 6 Figure 2 aCVi Spectrum ccccccccccsseeseeceeeeeeceeeeeeeeceeeeeeaasaeeeeeeeeeeeaeaeeeeceeeeseeeaaaeeeeeeesssaaageses 10 Figure 3 FT 22 Block diagram EE 11 Figure 4 Chroma demodulator low pass filter cccceccseesceeeeeeeeseeeeeeaeeseeeeesaeeeeeeessaaeeeeesaaaees 14 Figure 5 Sync filter frequency response 14 Figure 6 Phase detector low pass filter response cccceeecccceeeeeeeeeeeeeeseeeeeeseaseeeeaaeeeesnaaeess 15 Figure 7 External VCO schematic ccccccccceseeseeeeeeeeeeeeeeeeeeeeeeeeseaeaeeeceeeeessuaaseeeeeeeessaaaasses 16 Figure S AG VI Data TOM MAb scisctsoceosecncvesatacacasnceexenestisedadnasdotecswunenvenusaadeveeSaadedavabalesencesieandeactessc 17 Figure 9 Character overlay address map 19 Figure 10 Character Mapping e eeeeeeeerreeeaa akea aitaka Keddi enika 22 Figure 11 PT22 Register timing ccccsssccccsssecccsesececcesseccseseecsseseeeceaueeesseeeesseseeesseneeessagees 23 Figure 12 AD8337 PGA gain response 27 PIQ
17. cos at dd 1 cos 2 x eu H sin 2 x wt A V E V cos 2 x ot Z 2 2 V The lower 9 bits of the 11 bit phase output from the BLO burst locked oscillator are used to address a sine and cosine lookup table These 9 bits comprise the phase angle at subcarrier frequency within a single quadrant and the top two bits are the quadrant this method save memory by only requiring a single quadrant to be stored in the LUT The output of the Sin Cos LUT is a 24 bit word 12 bits cosine and 12 bits sine The quadrant signs are used to manipulate the sine and cosine data such as to construct a full waveform The reconstructed sine and cosine waveforms are then multiplied by the input 74 25MHz free running composite video The output of the sine channel is the demodulated U signal and the cosine is the demodulated V output One over range bit caters for at the output to allow for twice subcarrier frequency components removed by the subsequent low pass filter aCVi_DemodLPF v The output of the demodulator also comprises twice subcarrier frequencies The output is therefore low pass filtered using a 63 tap filter the response for which is shown in Figure 4 The output of the filter is the clean simple demodulated U and V PT22 User Manual Revision 0 5 Page 13 of 28 SingMai Electronics Inphase Filter Frequency Response oe EE DE NR AON OE RED O CO RR E US pain dence DERRADEIRA RR ARDER RE NRO pas DENVER SP MS E RE o E DP RE
18. e difficult to resolve at the receiver end Because the cable system is a closed system it is only necessary for the transmitter and receiver to understand each other and we can modify the basic NTSC method to suit HD transmissions The first thing to overcome is the bandwidth restrictions of the cable HD 720p 60Hz transmission requires a luma bandwidth of 30MHz according to the SMPTE 296M Because we have only a single coaxial cable for the transport we have chosen to transmit luma and colour difference signals as opposed to component red green blue as the colour difference signals because of the visual perception of the eye being less acute to colour can be sent at half or less of the luma bandwidth i e 7 5Hz each As we are transmitting video for a complete system from camera to DVR or monitor we should take into account system bandwidth limitations such as the Kell factor and the camera Bayer colour filter The luma bandwidth may be set to either 30MHz default or 12MHz The chroma bandwidth is set to 7 5MHz which produces no visible degradation of the image To further reduce the bandwidth of the transmission the colour difference signals are modulated onto a carrier in quadrature so they effectively use the same bandwidth However to minimise the signal recovery problems of NISC and as we have no backward compatibility issues the upper sideband of the chroma and the luma baseband do not overlap for 720p 60Hz transmissi
19. ine 1 for the selected standard 12 bit word 1D ui _length_ 3 0 Hcount_length_2 3 0 Hcount_length_1 7 0 Default value 1649 720p 60HZ SME O Lee a aa a Start position of horizontal sync output 12 bit word SI Houtstanit RW do Hout start 2 3 0 Hout start 1 7 0 h Default value 10440 720p 60Hz 1 LSB 1 74 25MHz 20 Houtend1 RW 70 End position of horizontal sync output 12 bit word 21 R W 3 0 Hout end 2 3 0 Hout end 1 7 0 Default value 16440 720p 60Hz 1 LSB 1 74 25MHz BP gate start 1 R W 7 0 Start position of burst gate sample pulse 12 bit word 23 BP gate start 1 BW BP gate start 2 3 0 BP gate start 1 7 0 Default value w 19010 720p 60Hz 1 LSB 1 74 25MHz BP_gate_end_1 RW End position of burst gate sample pulse 12 bit word 25 BP gate end 1 R W BP_gate_end_2 3 0 BP_gate_end_1 7 0 Default value e per ant ei 223 3 120p 60H2 1 LSB 1 74 25MH HBlank_start_1 RW Start position of horizontal blanking pulse 12 bit word 2B HBlank start 2 R W HBlank start 2 3 0 HBlank start 1 7 0 Default value boll a bad le 153619 720p 60Hz 1 LSB 1 74 25MHz 2C HBlank end 1 Em End position of horizontal blanking pulse 12 bit word 2D HBlank end 2 ee Ke ms 7 0 Default value er Tewes ag oo ee 720p 60Hz 1 LSB 1 74 25MHz ee E Vertical pixel counter length Should be set to the number of lines frame
20. int of the falling edge of the horizontal pulse is coincident with the centre tap of the FIR filter the accumulated result will be zero When they are not coincident an error will be generated This error is filtered using a recursive filter integrator and proportional and integral terms are added to create an error word which is converted to a PWM signal to control and external voltage controlled oscillator VCO See Figure 7 The horizontal pixel counter is used by the SPG sync pulse generator to provide the horizontal timing pulses required by the decoder including the black level clamp pulse to the analogue front end and the burst gate pulse for the demodulator The vertical field pulses are recovered by using a digital integrator on the sliced composite video PT22 User Manual Revision 0 5 Page 15 of 28 SingMai Electronics A 3V3 A 3V3 ce4 R82 L pet xe 10k l ASYY 27MHZ N152 T 2 A 3 1M 1 1 NC752125 Ge VCO_PWM cB3 EI VI Figure 7 External VCO schematic LCD SCH 33R aCVi Comb filter v The upper luma frequencies and the lower sideband of the chroma overlap Although there is very little luma energy in this region for most applications it is still better to completely separate them This can separated because the chroma information has a known line based phase relationship whereas the HF luma and cross colour does not The comb filter provides this filtering operation A line comb filter is
21. ltipliers x 14 162722 2 input NAND gate equivalent The memory is single port ROM and RAM PT22 User Manual Revision 0 5 Page 4 of 28 SingMai Electronics 2 PT22 Module description The PT22 aCVi decoder IP core comprises 14 Verilog modules in a hierarchical structure see Table 2 Table 2 PT22 Verilog file structure The top level file is aCVi decoder v which in turn calls nine of the other modules aCVi Demod v calls a third level file Rx SinCos ROM v Chargen v the character overlay call three other modules PT22 User Manual Revision 0 5 Page 5 of 28 SingMai Electronics 3 Signal Interconnections The PT22 signal interconnect diagram is shown in Figure 1 Figure 1 PT22 Block symbol The signal descriptions are shown in Table 3 below Inputs Signal Description Clk74 74 25MHz clock input from VCO All outputs are valid wf on the rising edge of this clock Rising edges of Clk74 and Clk148 should be coincident Clk148 should be coincident Reg_Clk Clock used for writing to the control registers only If wf Clk74 is continuous and stable Reg_clk may be connected to this input RESETn Asynchronous active low reset signal Asserting this wf input sets all the control registers to their default value and resets all registers ORNG Over range input from the ADC aCVi_in 9 0 Input aCVI encoded data from ADC Data should be valid on the rising edge of Clk74 This input should be offset bin
22. nection between all the other modules aCVi Rx Register control v A conventional 8 bit microprocessor style control is used to write and read to the PT22 control registers Details of the interface may be found in Chapter 5 and the register descriptions may be found in Chapter 6 PT22 User Manual Revision 0 5 Page 11 of 28 SingMai Electronics aCVi Demod v A free running subcarrier frequency is generated using a 32 bit ratio counter clocked from the input 4 25MHz clock phasechange perline _ F AU subcarrier seed SC pixels per line 74 25 MHz E 360 Ge ratio The free running frequency of the subcarrier is depends on the colour standard see table 5 Pixels line Line frequency Fsc Fy ratio Subcarrier Seed value 1650 45 00kHz 549 5 24 7275MHz 554179544 720p 50 1980 37 50kHz 659 5 24 73125MHz 5544C8A94 720p 30 2200 22 50kHz 1097 5 24 69375MHz 5523AF524 _720p 25 3960 18 75kHz 1317 5 24 703125MHz S52BF5A8 1080p 30 2200 33 75kHz_ 731 5 24 688125MHz 551EB8514 1080p 25 2640 28 125kHz 879 5 24 7359375MHz 5548EBD4 1080p 24 2750 27 00kHz 915 5 24 7185MHz___ 553987BA _ 1080i 30_ 2200 33 75kHz_ 731 5 24 688125MHz 551EB851u _1080i 25 2640 28 125kHz 879 5 24 7359375MHz 5548EBD4 Table 4 SC10 Line and subcarrier frequencies The top 11 bits of this ratio counter the phase word are used by the demodul
23. omponent However automatic colour control in the receiver can maintain the colour saturation over a further 9dB signal attenuation The luma bandwidth will be gracefully reduced as the distance is increased Because of the similarity in the transmission method to NTSC both the transmitter and receiver can easily be made to accommodate conventional NTSC PAL transmissions ACVi also allows for the bidirectional transfer of data between receiver and transmitter One byte of data is transmitted in each direction per frame i e 50 or 60 bytes second data rate depending on the video frame rate The data rate is deliberately kept low to reduce the effects of cable attenuation Data is sent using two dedicated lines in the vertical blanking interval PT22 User Manual Revision 0 5 Page 10 of 28 SingMai Electronics 5 Technical Overview A simplified block diagram of the PT22 aCVi decoder is shown in Figure 2 VCo PWM H out Vout F out aCVi from ADC Y out 74 25MHz VCO clock U out V out Figure 3 PT22 Block diagram The aCVi input from the ADC is a straight binary 10 bit input sampled at 74 25MHz Analogue clamping prior to the ADC ensure the most negative value of the input signal the sync tips are clamped to the negative reference of the ADC code value 0 The following is a brief description of each Verilog module aCVi_decoder v This is the top level module for the PT22 It provides the intercon
24. on the carrier is 24 7Hz The effective bandwidth of the complete signal is therefore approximately 9 3MHz chroma upper sideband filter roll off 24 7MHz or about 34MHz setting a minimum sampling frequency of 2 x 34MHz or 68MHz For convenience we choose 74 25MHz as a sampling frequency as this is related to the 720p 60 SMPTE standard see Figure 12 For 300m of RG 59 cable we can expect 18dB loss at this frequency 6 2dB 100m 50MHz However the synchronizing signals are at a much lower frequency where the loss is only about 1 2dB so reliable rastering of the received signal should always be assured To simplify the high frequency compensation of the transmission pre emphasis is used The degree of pre emphasis is programmable to allow for different cable lengths The maximum pre emphasis is set at 40dB and the frequency response is set to approximate the cable characteristics A further improvement in the SNR is achieved through transmitting a peak to peak video level of 1 5V which maintains compatibility with any legacy SD equipment on the network and also allows common low power 5V drivers to be used PT22 User Manual Revision 0 5 Page 9 of 28 SingMai Electronics V Luma Chroma 40dB ee eee 300MHz et pepe CEEE 5MHz 24 MHz subcarrier Figure 2 aCVi Spectrum At extreme distances the bandwidth will start to further fall off The chroma signal will be the first affected by this being the highest frequency c
25. otused used Enables automatic colour control colour gain control level 1 Mee adjustment if 1 default else manual adjustment Register 40 and 41 LL ss GU default do o Enables automatic black level adjustment if 1 default else manual adjustment Register 40 and 41 pf RR Enables automatic luma gain adjustment if 1 default else manual adjustment Register 04 DO TO Bitvalue Function SSCS EE eessen control word from phase detector HPLL closed default 01 VCO control set to minimum control set to minimum EE E VOO corr set da control set to maximum FE E E VCO control set to 50 Freerun mode pasta control An 8 bit register intended for the control of the analogue front end programmable gain amplifier This register is not used when automatic luma gain control is enabled SPG Sync_slice_offs Value added to the negative video peak value for slicing the PT22 User Manual Revision 0 5 Page 24 of 28 SingMai Electronics Register Register Name R W Bit Description Offset Value L t LL sync pulses Default value 156 18 FSci RW 70 Subcarrier seed value 32 bit value FSc_1 7 0 FSc_2 7 0 ms se Inn SIA RW 70 Default value 6655D9BA 169367737510 Seed value for 21 FSCc3 RW 70 58559489MHz 720p 60Hz B pe RW 7 1C oo _length_ R W 7 0 Horizontal pixel counter length Should be set to the number of pixels l
26. t Din 7 0 Valid _ e ec Dout 7 0 aCVi Rx Register out A 7 0 Figure 11 PT22 Register timing PT22 User Manual Revision 0 5 Page 23 of 28 SingMai Electronics 7 Register descriptions Table 7 lists all of the control and status registers All of the registers are 8 bit unused register bits read back as zeros Please note that some registers can be set to values that are illegal and will produce invalid outputs Asserting the RESETn input sets the PT22 registers to their default values Register Register Name R W Bit Description Offset Value Control Registers Control 1 RW __ aCVi Rx control Output format 7 Set to 1 to enable the status character overlay else 0 to disable the overlay default o o 62 Not used eee used E O pe oe 00 Notused 4 used D n ee 20 bit H V F 74 25MHz clock Default DO o io Liese Notused oo gt mm Contra ni avi ee standard If set to 1 the aCVi output free runs video black at the selected video standard If set to OU the output is locked to the aCVi video input If default the video standard is manually selected using bits 3 0 If 1 the standard is automatically detected from input sync signals DO lo 5 vae sao Do lo o o ooo ooo 000 Um SSCSC SsS DO lo po po fofo Dl Do fon o Do lo o o i o iomp o 001 2 SS Do lo po po fio le 08 O O Oo Kee et N
27. ter 49 Once this is written the two words are signaled for transfer on the next video frame A status bit write busy is set during this time Further data transfers should not be initiated until this bit is reset aCVi_Chargen v The PT22 has a character generator built in that allows the display of error or information messages The display is a centrally located 20 character x 8 line display 20 character x 7 line display for 720p formats each character is 48x64 pixels in height The address map of the display is shown in Figure 9 Figure 9 Character overlay address map The characters are displayed as yellow on a dimmed monochrome background to aid visibility Over 100 pre programmed characters and symbols may be chosen from see Table 7 The character display may be enabled or disabled using bit 7 of the Control 1 register SingMai Electronics es ade Ud es E se WI sm IO Si zs je ET ee Ile es D sws ls M e RB se D e RB E sm BR sa zs A e Wi sm Is Is EI e HI se Siss jw sa EN wm O o Si e DI o OI RU IECH RE 1 ea KE mme o K i A L E EM lt i WI D wl H en e e ep J N J HD i BR PT22 User Manual Revision 0 5 Page 20 of 28 SingMai Electronics Hex Code Hex Code Hex Code Hex Code oe E TER E bs D sw en Value 0 displays nothing All other values automatically turn on the background Value 3F is a space i e it displays b
28. to provide control of the transmitter pre emphasis and luma and chroma automatic gain controls The luminance measurements are performed on the low pass filtered video from the sync filter The back porch value and the most negative video amplitude values are used to calculate the sync pulse amplitude which in turn is used to control the gain of the analogue programmable gain amplifier PT22 User Manual Revision 0 5 Page 16 of 28 SingMai Electronics The back porch value is also used to subtract an offset from the output luma value remove the syncs aCVi_Procamp v The low pass filtered luma is conditioned by the processing amplifier First the black level offset is subtracted from the luma signal to set the black level at zero The luma is then amplified to provide a 960 code 10 bit output for a 100 colour bar input The luma output is valid on the rising edge of the 74MHz clock The low pass filtered chroma outputs are amplified separately to provide a nominal 700mV output for a 100 colour bar input These outputs are then multiplexed into a Cb Cr output The output is valid on the rising edge of the 74MHz clock and the Cmux output 37MHz is used to de multiplex the video Cmux 0 Cb Cmux 1 Cr The SPG also provides Vout vertical Fout frame ID for interlaced video and Hout horizontal synchronizing pulses aCVi_data v The aCVi interface allows for the bi directional transmission of control data between the
29. transmitter and receiver The data is transferred during to two dedicated lines of the vertical blanking interval one for transmitter to receiver transmission the other for receiver to transmitter One byte of data is sent for each line allowing a maximum of 60 bytes to be transferred each second for a 60Hz frame rate The format of the data transfer is shown in Figure 17 Active Video 1260 pixels 1 74 25MHz 1724s Data period 27 symbols x 1 2 32MHz 11 64ys Framing byte Control word Data byte Parity Figure 8 aCVi Data format The format is the same regardless of the direction of transfer PT22 User Manual Revision 0 5 Page 17 of 28 SingMai Electronics The first 8 bits are the framing byte which is a unique code signifying the beginning of data The receiving device must monitor the pre defined vertical blanking line for this framing byte which is a unique code The next four bits are a control word which defines the function of the following data byte The control words between transmitter and receiver and receiver and transmitter are different See Tables 6 and 7 C3 C2 Ci Co Dec Function ojojo o 0 O O O 1 1 Pre emphasis value for transmitter auto cable equalization DA T E T Select video Pattern 00 Video 01 75 colour bars 02 30MHz luma frequency sweep 03 2T 30T pulse bar Cao EC En Function EU ESSES i a 3 po EENAOASO eee eo S CSC Er
30. ut aCVi Rx Register out sig aCVi Yout aCVi Yout sig SCHT CbCrout aCVi CbCrout sig SCHT Cmux aCVi Cmux sig aCVi Hout aCVi Hout sig aCVi Vout aCVi Vout sig aCVi Fout aCVi Fout sig aCVi HBlank aCVi HBlank sig aCVi VBlank aCVi VBlank sig Data out Data out sig Gain control Gain control sig VCO PWM VCO PWM sig aCVi test aCVi test sig PT22 User Manual Revision 0 5 input ORNG sig input 9 0 aCVi in sig input 8 0 A sig input 7 0 Din sig input aCVi_Rx_CSn_sig input aCVi CG CSn sig input aCVi Rx WRn sig output 7 0 aCVi Rx Register out sig output 9 0 aCVi Yout sig output 9 0 aCVi CbCrout sig output output output output output output output output output aCVi_Cmux_sig aCVi_Hout_sig aCVi_Vout_sig aCVi_Fout_sig aCVi_HBlank_sig aCVi_VBlank_sig Data_out_sig Gain_control_sig VCO PWM sig output 1 0 aCVi test sig Page 8 of 28 SingMai Electronics 4 aCVi Overview The following is a brief overview of the aCVi interface The basic concept of the aCVi interface is to build on the proven and reliable transport method of NTSC the advantages of PAL v v multi path reception is not relevant to a cable system so NTSC is used as the model NTSC transmissions are capable of more than 1km across RG 59 cable but the bandwidth is limited to 5MHz NTSC also has chroma luma crosstalk issues that ar
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