Quartus II Introduction Using Schematic Designs
Contents
1. E Assignment Editor D introtutorial light light File Edit View Tools Window Help lt lt new gt gt W Filter on node names Category All 5 From To Assignment Name Enabled mtii Comment Tag 1 lt lt new gt gt lt lt new gt gt lt lt new gt gt 0 00 00 00 Figure 24 The Assignment Editor window Pin assignments are made by using the Assignment Editor Select Assignments gt Assignment Editor to reach the window in Figure 24 shown here as a detached window In the Category drop down menu select All Click on the lt lt new gt gt button located near the top left corner to make a new item appear in the table Double click the box under the column labeled To so that the Node Finder button amp appears Click on the button not the drop down arrow to reach the window in Figure 25 In the Filter drop down menu select Pins all Then click the List button to display the input and output pins to be assigned f xl and x2 Click on x1 as the first pin to be assigned and click the gt button this will enter x1 in the Selected Nodes box Click OK x1 will now appear in the box under the column labeled To Alternatively the node name can be entered directly by double clicking the box under the To column and typing in the node name Follow this by double clicking on the box to the right of this new x1 entry in the column labeled Assignment Name Now the drop down menu in Figure 26 appears Scroll down an2. The software works on one project at a time and keeps all information for that project in a single directory folder in the file system To begin a new logic circuit design the first step 1s to create a directory to hold its files To hold the design files for this tutorial we will use a directory introtutorial The running example for this tutorial is a simple circuit for two way light control Start the Quartus II software You should see a display similar to the one in Figure 2 This display consists of several windows that provide access to all the features of Quartus II software which the user selects with the computer mouse Most of the commands provided by Quartus II software can be accessed by using a set of menus that are located below the title bar For example in Figure 2 clicking the left mouse button on the menu named File opens the menu shown in Figure 3 Clicking the left mouse button on the entry Exit exits from Quartus II software In general whenever the mouse is used to select something the eft button is used Hence we will not normally specify which button to press In the few cases when it is necessary to use the right mouse button it will be specified explicitly Altera Corporation University Program 3 May 2012 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 a onere _ Fie Edit View Project Assignments Processing Tools Window Help amp Search altera com Ded tenai JEY G VSe Tr SH gt Pro
3. Add Device fi up Down Figure 50 The Programmer window upon completion of programming 10 Testing the Designed Circuit Having downloaded the configuration data into the FPGA device you can now test the implemented circuit Flip the RUN PROG switch to RUN position Try all four valuations of the input variables x and x2 by setting the corresponding states of the switches SW and SW Verify that the circuit implements the truth table in Figure 11 If you want to make changes in the designed circuit first close the Programmer window Then make the desired changes in the Block Diagram Schematic file compile the circuit and program the board as explained above 40 Altera Corporation University Program May 2012 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For Quartus Il 12 0 Copyright 1991 2011 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications i
4. II 64 Bit Analysis amp Synthesis was unsuccessful 1 error 2 warnings Error 293001 Quartus II Full Compilation was unsuccessful 3 errors 2 warnings Messages 11 00 00 13 Figure 21 Compilation report for the failed design 20 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 db Compilation Report D introtutorial light light File Edit Tools Window Hep Table of Contents Analysis amp Synthesis Messages Flow Summary Type Message ES Flow Settings i Info 20030 Parallel compilation is enabled and will use 4 of the 4 processors Eze Flow Non Default Global Settinc b i Info 12021 Found 1 design units including 1 entities in source file light bd _ Flow Elapsed Time i Info 12127 Elaborating entity light for the top level hierarchy E Flow oss y i Warning 275008 Primitive AND2 of instance inst not used Fihan A Warning 275008 Primitive HOT of instance inst3 not used Error 12003 Node inst4 is missing source di Analysis amp Synthesis a e te Error Quartus II 64 Bit Analysis amp Synthesis was unsuccessful 1 error 2 warnin Ea Summary gt 4 Settings EEE E Parallel Compilation ocessing _Ex FAW ing 2 _ _ Critical Warning 4 TT Location i Locate 11 00 00 13 Figure 22 Error messages N Quartus II 64 Bit D introtutorial light light File Edit Vi
5. Observe also a solid vertical line which can be moved by pointing to its top and dragging it horizontally This reference line is used in analyzing the timing of a circuit move it to the time O position The waveforms can be drawn using the Selection Tool which is activated by selecting the icon in the toolbar To simulate the behavior of a large circuit it is necessary to apply a sufficient number of input valuations and observe the expected values of the outputs In a large circuit the number of possible input valuations may be huge so in practice we choose a relatively small but representative sample of these input valuations However for our tiny circuit we can simulate all four input valuations given in Figure 11 We will use four 50 ns time intervals to apply the four test vectors We can generate the desired input waveforms as follows Click on the waveform for the x node Once a waveform is selected the editing commands in the Waveform Editor can be used to draw the desired wave forms Commands are available for setting a selected signal to 0 1 unknown X high impedance Z weak low L weak high H a count value C an arbitrary value a random value R inverting its existing value INV or defining a clock waveform Each command can be activated by using the Edit gt Value command or via the toolbar for the Waveform Editor The Value menu can also be opened by right clicking on a selected waveform Set x to 0 i
6. XE XB a YR EB Master Time Bar 0 ps gt Pointer 952 56 ns Search altera com E 160 0 nm 200 0 ns Value at ns ns Ops 0 00 00 00 Figure 32 The augmented Waveform Editor window 6 Next we want to include the input and output nodes of the circuit to be simulated Click Edit gt Insert gt Insert Node or Bus to open the window in Figure 33 It is possible to type the name of a signal pin into the Name box or use the Node Finder to search your project for the signals Click on the button labeled Node Finder to open the window in Figure 34 The Node Finder utility has a filter used to indicate what type of nodes are to be found Since we are interested in input and output pins set the filter to Pins all Click the List button to find the input and output nodes as indicated on the left side of the figure Altera Corporation University Program May 2012 27 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 ca Insert Node or Bus Name Node Finder Bus width 1 Startindex 0 Display gray code count as binary count Figure 33 The Insert Node or Bus dialogue Nodes Found Selected Nodes Type Name M Type Output xi Input Input i x Input Input F Output Figure 34 Selecting nodes to insert into the Waveform Editor Click on the x signal in the Nodes Found box in Figure 34 and then click the gt sign to add it to the Selected Nodes box on the right
7. contains the data to be loaded into the configuration device on the DE series board The extension pof stands for Programmer Object File Upon returning to the Programmer window click on the Program Configure check box as shown in Figure 49 Some devices in current device list cannot be added to selected programming mode A Active Serial Programming Do you want to dear all devices in current device list and switch to selected mode Figure 46 Clear the previously selected devices Altera Corporation University Program 37 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 diiy Programmer D introtutonal light light light cdf File Edit View Processing Tools Window Help USB Blaster USB 0 Enable real time ISP to allow background programming for MAX II and MAX V devices i Checksum Usercode Frogram Verify Blank Examine pel Start Configure Check gil Stop cee Auto Detect 2 Delete Be Change File et Save File Fup Down Figure 47 The Programmer window with Active Serial Programming selected di atom_netlists J db di incremental_db di gaim light pof re nane res of type Figure 48 Choose the configuration file 38 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 diiy Programmer D introtutonal light light light cdf File Edi t View Processing Tools Windo
8. of a pin 5 3 Connecting Nodes with Wires The symbols in the diagram have to be connected by drawing lines wires Click on the icon 1 in the toolbar to activate the Orthogonal Node Tool Position the mouse pointer over the right edge of the x1 input pin Click and hold the mouse button and drag the mouse to the right until the drawn line reaches the pinstub on the top input of the AND gate Release the mouse button when you see a box appear which leaves the line connecting the two pinstubs Next draw a wire from the input pinstub of the leftmost NOT gate to touch the wire that was drawn above it Note that a dot will appear indicating a connection between the two wires Use the same procedure to draw the remaining wires in the circuit If a mistake is made a wire can be selected by clicking on it and removed by pressing the Delete key on the keyboard Upon completing the diagram click on the icon to activate the Selection Tool Now changes in the appearance of the diagram can be made by selecting a particular symbol or wire and either moving it to a different location or deleting it The final diagram is shown in Figure 19 save it Altera Corporation University Program 17 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 E Quartus I 64 Bit D introtutorial light light File Edit View Project Assignments Processing Tools Window Help E Search Deg a tena Hy GVO Tr veh oe Project Navigator eo x
9. side of the figure Do the same for x2 and f Click OK to close the Node Finder window and then click OK in the window of Figure 33 This leaves a fully displayed Waveform Editor window as shown in Figure 35 If you did not select the nodes in the same order as displayed in Figure 35 it is possible to rearrange them To move a waveform up or down in the Waveform Editor window click within the node s row i e on its name icon or value and release the mouse button The waveform is now highlighted to show the selection Click again on the waveform and drag it up or down in the Waveform Editor 28 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 Search altera com MA oh Ze ew e a 17 a A Master Time Bar 0 ps Pointer 952 56 ns Interval 952 56 ns Start Ops 160 0 ns 200 0 ns Value at ns ns fl T Name Ops BO BO BX ECCCECCOCEDCOCHOCOSHOCOCEOCOSOOCOSH OED OUS EOL LS EOS OS 0 00 00 00 Figure 35 The nodes needed for simulation 7 We will now specify the logic values to be used for the input signals x and x2 during simulation The logic values at the output f will be generated automatically by the simulator To make it easy to draw the desired waveforms the Waveform Editor displays by default vertical guidelines and provides a drawing feature that snaps on these lines which can otherwise be invoked by choosing the Snap To Grid button
10. the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in an actual FPGA chip it also chooses routing wires in the chip to make the required connections between specific LEs e Timing Analysis propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit e Timing Simulation the fitted circuit is tested to verify both its functional correctness and timing e Programming and Configuration the designed circuit is implemented in a physical FPGA chip by pro gramming the configuration switches that configure the LEs and establish the required wiring connections This tutorial introduces the basic features of the Quartus II software It shows how the software can be used to design and implement a circuit specified by means of a schematic diagram It makes use of the graphical user interface to invoke the Quartus I commands Doing this tutorial the reader will learn about e Creating a project e Entering a schematic diagram e Synthesizing a circuit from the schematic diagram e Fitting a synthesized circuit into an Altera FPGA e Assigning the circuit inputs and outputs to specific pins on the FPGA e Simulating the designed circuit e Programming and configuring the FPGA chip on Altera s DE series board 3 Getting Started Each logic circuit or subcircuit being designed with Quartus II software is called a project
11. the questions that may arise when using the software The documentation is accessed from the Help menu To get some idea of the extent of documentation provided it is worthwhile for the reader to browse through the Help menu If no web browser is specified Quartus will complain with an error message To specify a web browser go to Tools gt Options gt General gt Internet Connectivity Specify a path to a web browser in the web browser field The user can quickly search through the Help topics by selecting Help gt Search which opens a dialog box into which keywords can be entered Another method context sensitive help is provided for quickly finding documen tation for specific topics While using most applications pressing the F1 function key on the keyboard opens a Help display that shows the commands available for the application 4 Starting a New Project To start working on a new design we first have to define a new design project Quartus II software makes the designer s task easy by providing support in the form of a wizard Create a new project as follows 1 Select File gt New Project Wizard and click Next to reach the window in Figure 4 which asks for the name and directory of the project 2 Set the working directory to be introtutorial of course you can use some other directory name of your choice if you prefer The project must have a name which is usually the same as the top level design entity that will be inc
12. type of device in which the designed circuit will be implemented Choose the Cyclone series device family for your DE series board We can let Quartus II software select a specific device in the family or we can choose the device explicitly We will take the latter approach From the list of available devices choose the appropriate device name for your DE series board A list of devices names on DE series boards can be found in Table 1 Press Next which opens the window in Figure 8 Cyclone II EP2C35F672C6 DE2 70 Cyclone II EP2C70F896C6 DE2 115 Cyclone IVE EP4CE1 15F29C7 Table 1 DE series FPGA device names Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 EDA Tool Settings page 4 of 5 Specify the other EDA tools used with the Quartus II software to develop your project EDA tools Format s Run Tool Automatically v lt None gt a Run this tool automatically to synthesize the current design lt None gt m lt None gt v Run gateevel simulation automatically after compilation lt None gt lt None gt Run this tool automatically after compilation Formal Verification v Board Level Timing Symbol lt Back net gt msh J cancel Hep Figure 8 Other EDA tools can be specified 5 The user can specify any third party tools that should be used A commonly used term for CAD software for electronic circuits is EDA tools whe
13. GA prototype device Dual Purpose Pins Capacitive Loading Configuration scheme Active Serial can use Configuration Device X Board Trace Model ee E a Configuration mode v Configuration device CvP Settings v Use configuration device Configuration device I O voltage EPCS64 Force VCCIO to be compatible Epcs128 V Generate compressed bitstreams Active serial dock source Enable input tri state on active configuration pins in user mode Description Specifies the configuration device that you want to use as the means of configuring the target device Figure 45 Specifying the configuration device The rest of the procedure is similar to the one described above for the JTAG mode Select Tools gt Programmer to reach the window in Figure 40 In the Mode box select Active Serial Programming If you are changing the mode from the previously used JTAG mode the pop up box in Figure 46 will appear asking if you want to clear all devices Click Yes Now the Programmer window shown in Figure 47 will appear Make sure that the Hardware Setup indicates the USB Blaster If the configuration file is not already listed in the window press Add File The pop up box in Figure 48 will appear Select the file light pof in the directory introtutorial and click Open As a result the configuration file light pof will be listed in the window This is a binary file produced by the Compiler s Assembler module which
14. Ir ELT EE Riv GVS Or SOARE Project Navigator eo x light bd mafa dk SQ de amp b GM ca d Cydone Il EP2C35F gt light SE Critical Warning Location Locate af 2 00 00 14 Figure 14 Graphic Editor window 5 1 Importing Logic Gate Symbols The Graphic Editor provides a number of libraries which include circuit elements that can be imported into a schematic Double click on the blank space in the Graphic Editor window or click on the icon in the tool bar that looks like an AND gate A pop up box in Figure 15 will appear Expand the hierarchy in the Libraries box as shown in the figure First expand libraries then expand the library primitives followed by expanding the library logic which comprises the logic gates Select and2 which is a two input AND gate and click OK Now the AND gate symbol will appear in the Graphic Editor window Using the mouse move the symbol to a desirable location and click to place it there Import the second AND gate by simply moving the mouse pointer to a new position and clicking to place another AND gate symbol there A symbol in the Graphic Editor window can be moved by clicking the icon in the toolbar that looks like a mouse cursor then clicking the symbol you want to move and dragging it to a new location with the mouse button pressed Next select or2 from the library and import the OR gate into the diagram Then select not and import two instances of the NOT gate Rotate
15. P2C35F484c8 1 483840 lt 4 Migration compatibility Migration Devices HardCopy 0 migration devices selected Limit DSP amp RAM to HardCopy device resources Figure 43 The Device Settings window Altera Corporation University Program 35 May 2012 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For Quartus HI 12 0 General Specify general device options These options are not dependent on the configuration scheme Options Auto restart configuration after error Release clears before tri states Enable user supplied start up dock CLKUSR Enable device wide reset DEV_CLRn Enable device wide output enable DEV_OE Enable INIT_DONE output E Auto usercode JTAG user code 32 bit hexadecimal 9 FFFFFFFF In system programming damp state Delay entry to user mode Directs the device to restart the configuration process automatically if a data error is encountered If this option is turned off you must externally direct the device to restart the configuration process if an error occurs Figure 44 The Options window Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 f Device and Pin Options ligh General Configuration Configuration Programming Files Specify the device configuration scheme and the configuration device Note For HardCopy Unused Pins designs these settings apply to the FP
16. a is loaded into the FPGA upon power up or reconfiguration Thus the FPGA need not be configured by the Quartus II software if the power is turned off and on The choice between the two modes is made by the RUN PROG switch on the DE series board The RUN position selects the JTAG mode while the PROG position selects the AS mode 9 1 JTAG Programming The programming and configuration task is performed as follows Flip the RUN PROG switch into the RUN position Select Tools gt Programmer to reach the window in Figure 40 Here it is necessary to specify the programming 32 Altera Corporation University Program May 2012 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For Quartus IT 12 0 hardware and the mode that should be used If not already chosen by default select JTAG in the Mode box Also if the USB Blaster is not chosen by default press the Hardware Setup button and select the USB Blaster in the window that pops up as shown in Figure 41 diiy Programmer D introtutorial light light light cdf File Edit View Processing Tools Window Help S Zi Hardware Setup USB Baster S60 Vode Enable real time ISP to allow background programming for MAX II and MAX V devices Device Checksum Usercode Program pel Start Configure EP2C35F672 002F8360 FFFFFFFF al Stop dy Auto Detect Delete a Add File i gt Change File et Save File G Add Device i up Down Figure 40 The Programme
17. ate program Total PLLs 0 4 0 gt TimeQuest Timing Analysis TT j a Compile Design gt Analysis amp Synthesis Type Message ie i Info 332102 Design is not fully constrained for hold requirements y i Info Quartus II 64 Bit TimeQuest Timing Analyzer was successful 0 errors 3 warnings i Info 293026 Skipped module PowerPlay Power Analyzer due to the assignment FLOW ENABLE POWER ANALYZE _ i Info 293000 Quartus II Full Compilation was successful 0 errors 8 warnings wT Extra Info r Locate 100 00 00 48 Figure 20 Display after a successful compilation 6 1 Errors Quartus II software displays messages produced during compilation in the Messages window If the block diagram design file is correct one of the messages will state that the compilation was successful and that there are no errors If the Compiler does not report zero errors then there is at least one mistake in the schematic entry In this case a message corresponding to each error found will be displayed in the Messages window Double clicking on an error message will highlight the offending part of the circuit in the Graphic Editor window Similarly the Compiler may display some warning messages Their details can be explored in the same way as in the case of error messages The user can obtain more information about a specific error or warning message by selecting the message and pressing the F1 function key To see the effect of an erro
18. cify the path names of any non default libraries User Libraries Figure 6 The wizard can include user specified design files 3 The wizard makes it easy to specify which existing files Gf any should be included in the project Assuming that we do not have any existing files click Next which leads to the window in Figure 7 Altera Corporation University Program 7 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation Device family Family Cydone II z Devices Al Target device Auto device selected by the Fitter Specific device selected in Available devices list Other n a Available devices Show in Available devices list Package Any Pin count any Speed grade Any Name filter V Show advanced devices HardCopy compatible only Name Core Voltage LEs EP2C35F484C6 1 2V 33216 EP2C35F484C7 1 2V 33216 EP2C35F484C8 1 2V 33216 EP2C35F48418 1 2V 33216 EP2C35F672C6 1 2V 33216 EP2C35F672C7 1 2V 33216 EP2C35F672C8 1 2V 33216 4 m User I Os Memory Bits 322 322 322 322 475 475 475 483840 483840 483840 483840 jaaaaagaa Embedded multiplier 9 Companion device HardCopy ied Gres i Figure 7 Choose the device family and a specific device 4 We have to specify the
19. d select Location Accepts wildcards groups Instead of scrolling down the menu to find the desired item you can just type the first letter of the item in the Assignment Name box In this case the desired item happens to be the first item beginning with L Finally double click the box in the column labeled Value Type the pin assignment corresponding to SWo for your DE series board as listed in Table 2 22 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 Use the same procedure to assign input x2 and output f to the appropriate pins listed in Table 2 An example using a DE2 board is shown in Figure 27 To save the assignments made choose File gt Save You can also simply close the Assignment Editor window in which case a pop up box will ask if you want to save the changes to assignments click Yes Recompile the circuit so that it will be compiled with the correct pin assignments Look in light Include subentities Nodes Found Selected Nodes Assignments Unassigned Unassigned Assignment Name Value Enabled Entity Comment Tag Implement as Clock Enable Implement as Output of Logic Cell Infer RAMs from Raw Logic Input Delay from Dual Purpose Clock Pin to Fan Out Destinations Accepts wildcards groups Input Delay from Pin to Input Register Accepts wildcards groups Input Delay from Pin to Internal Cells Accepts wildcards groups Iteration limit for co
20. ew Project Assignments Processing Tools Window Help amp Daeha amp SB o fit UU r Or K s we je light bdf G EATA 0T ANGE ase S 8 Oo y Cydone It EP2C2_ 3H linkt al Error 12003 Node M inst4 is missing source gt j Error Quartus II 64 Bit Analysis amp Synthesis was unsuccessful 1 error 2 warnings Error 293001 Quartus II Full Compilation was unsuccessful 3 errors Z warnings T Locate 4 47 11 00 00 13 Figure 23 Identifying the location of the error 7 Pin Assignment During the compilation above the Quartus II Compiler was free to choose any pins on the selected FPGA to serve as inputs and outputs However the DE series board has hardwired connections between the FPGA pins and the other Altera Corporation University Program 21 May 2012 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For Quartus Il 12 0 components on the board We will use two toggle switches labeled SWo and SW to provide the external inputs x and x2 to our example circuit These switches are connected to the FPGA pins listed in Table 2 We will connect the output f to the green light emitting diode labeled LEDGp Its FPGA pin assignment can also be found in Table 2 DEO Nano DE2 70_ _DE2 115 PIN_J6 PIN_M1 PIN_L22 PIN_N25 PIN_AA23 PIN_AB28 PIN_H5 PIN_T8 PIN_L21 PIN_N26 PIN_AB26 PIN_AC28 LEDGy PIN_J1 PIN_AI5 PIN_U22 PIN_AE22 PIN_W27 PIN_E21 Table 2 DE Series Pin Assignments
21. generated by the Quartus II Compiler s Assembler module Altera s DE series board allows the configuration to be done in two different ways known as JTAG and AS modes The configuration data is transferred from the host computer which runs the Quartus II software to the board by means of a cable that connects a USB port on the host computer to the leftmost USB connector on the board To use this connection it is necessary to have the USB Blaster driver installed If this driver is not already installed consult the tutorial Getting Started with Altera s DE Series Boards for information about installing the driver Before using the board make sure that the USB cable is properly connected and turn on the power supply switch on the board In the JTAG mode the configuration data is loaded directly into the FPGA device The acronym JTAG stands for Joint Test Action Group This group defined a simple way for testing digital circuits and loading data into them which became an IEEE standard If the FPGA is configured in this manner it will retain its configuration as long as the power remains turned on The configuration information is lost when the power is turned off The second possibility is to use the Active Serial AS mode In this case a configuration device that includes some flash memory is used to store the configuration data Quartus II software places the configuration data into the configuration device on the DE series board Then this dat
22. gramming In this case the configuration data has to be loaded into the configuration device on the DE series board Refer to Table 3 for a list of configuration devices on DE series boards To specify the required configuration device select Assignments gt Device which leads to the window in Figure 43 Click on the Device and Pin Options button to reach the window in Figure 44 Now click on Configuration in the menu on the left to obtain the window in Figure 45 In the Configuration device box which may be set to Auto choose the correct configuration device name and click OK Upon returning to the window in Figure 43 click OK Recompile the designed circuit DEI EPCS4 EPCSI6 DE2 70 EPCS64 DE2 115 EPCS64 Table 3 DE series Configuration Device Names Select the family and device you want to target for compilation Device family Show in Available devices list Family Cydone II X j Package Any Devices All Pin count Any Speed grade Any Name filter Target device Auto device selected by the Fitter Specific device selected in Available devices ist V Show advanced devices HardCopy compatible only Other n a Device and Pin Options Available devices Name Memory Bits Embedded multiplier 9 bit elements EP2C20F 25618 239616 239616 239616 239616 EP2C20F48418 239616 EP2C200240C8 1 239616 EP2C35F484C6 1 483840 EP2C35F484C7 1 483840 E
23. gt In the pop up dialog box choose a specific VWF file and specify either functional or timing simulation gt gt Ron the simulation by selecting Processing gt Start Simulation gt gt Warning If you recompile your Quartus II project with new changes the Node Finder files may be invalid gt gt To prevent invalid nodes from showing up in the Node Finder regenerate the Node Finder files gt gt by selecting Processing gt Generate Node Finder Files after you recompiled your project tcl gt k Idle Version 12 0 Build 173 05 02 2012 5J Full Version Figure 30 The QSim Window 5 The Waveform Editor window is depicted in Figure 31 Save the file under the name light vwf note that this changes the name in the displayed window Set the desired simulation to run from 0 to 200 ns by selecting Edit gt Set End Time and entering 200 ns in the dialog box that pops up Selecting View gt Fit in Window displays the entire simulation range of 0 to 200 ns in the window as shown in Figure 32 You may wish to resize the window to its maximum size Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus I 12 0 Search altera com Gn HA Ko Ze eB XE Be yn ER Master Time Bar 0 ps gt Pointer 952 56 ns Interval 952 56 ns 0 00 00 00 Figure 31 The Waveform Editor window af Simulation Waveform Editor light vw File Edit View Help HAL sk Ze XE YE BY
24. i Quartus lI Introduction Using Schematic Designs For Quartus II 12 0 1 Introduction This tutorial presents an introduction to the Quartus II CAD system It gives a general overview of a typical CAD flow for designing circuits that are implemented by using FPGA devices and shows how this flow is realized in the Quartus II software The design process is illustrated by giving step by step instructions for using the Quartus H software to implement a very simple circuit in an Altera FPGA device The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system This tutorial makes use of the schematic design entry method in which the user draws a graphical diagram of the circuit Two other versions of this tutorial are also available which use the Verilog and VHDL hardware description languages respectively The last step in the design process involves configuring the designed circuit in an actual FPGA device To show how this is done it is assumed that the user has access to the Altera DE series Development and Education board connected to a computer that has Quartus II software installed A reader who does not have access to the DE series board will still find the tutorial useful to learn how the FPGA programming and configuration task is performed The screen captures in the tutorial were obtained using the Quartus II version 12 0 if other versions of the soft
25. ions listed on the left side Figure 20 displays the Compiler Flow Summary section which indicates that only one logic element and three pins are needed to implement this tiny circuit on the selected FPGA chip 18 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 E Quartus I 64 Bit D introtutorial light light File Edit View Project Assignments Processing Tools Window Help T PSG 6 LBB oo Ely y Project Navigator g x ia light bdf deh Table of Contents FEJE Flow Summary cay Flow Status Successful Tue May 08 13 37 25 2012 gt Cyclone Il EP2C35F67206 FB Flow sett Quartus II 64 Bit Version 12 0 Build 173 05 02 2012 5J Full Version ar light aig eee Revision Name light Lm ES Flow Non Default Global Setting Topjevel Entity Name light E Flow Elapsed Time Family Cyclone II ity Hierarchy B Fies 4 Design units Es Flow O5 Summary Device EP2C35F672C6 e Fax Flow Log Timing Models Fral Analysis amp Synthesis Total logic elements 1 33 2165 lt 1 Fim ae Total combinational functions 1 33 216 lt 1 Dedicated logic registers 0 33 216 0 Compilation Report x EJ Flow Summary Task j P LA Assembler Total registers D gt TimeQuest Timing Analyzer Total pins 3 475 lt 1 Total virtual pins 0 Total memory bits 0 483 840 0 5 gt Fitter Place amp Route A Embedded Multiplier 9 biteements 0 70 0 gt P Assembler Gener
26. itor light sim vwt Read Only File Edit View Help Search altera com AA 8 sh Ze Xe Xe Xe a XR ee Master Time Bar 0 ps ra gt Pointer 154 34ns Interval 154 34ns 200 0 ns Value at ns Ops 00 00 00 Figure 38 The result of functional simulation 8 1 2 Timing Simulation Having ascertained that the designed circuit is functionally correct we should now perform the timing simulation to see how it will behave when it is actually implemented in the chosen FPGA device Select Assign gt Simulation Settings to get to the window in Figure 37 choose Timing as the simulation type and click OK Run the simulator which should produce the waveforms in Figure 39 Observe that there is a delay of about 6 ns in producing a change in the signal f from the time when the input signals x and x2 change their values This delay is due to the propagation delays in the logic element and the wires in the FPGA device Altera Corporation University Program 31 May 2012 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For Quartus Il 12 0 a Simulation Waveform Editor light sim vwt Read Only File Edit View Help E coh si gt L gt Pointer 27 06 ns Interval 27 06 ns 200 0 ns 00 00 00 Figure 39 The result of timing simulation 9 Programming and Configuring the FPGA Device The FPGA device must be programmed and configured to implement the designed circuit The required config uration file is
27. ject Navigator _ eax amp Compilation Hierarchy ALTERAY Task a Compile Design E a Analysis amp Synthesis o gre raumas ll Oo Edit Settings a Documentation x Y lt lt Search gt gt amp Hierarchy B Files g Design Units Type Message Messages New Project Wizard Open Project Save Project Close Project Save cil4s Save As Save All Ctrl Shift4 s File Properties Create Update Export Page Setup Print Preview Print Recent Files Recent Projects Exit Figure 3 An example of the File menu 4 Altera Corporation University Program May 2012 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For Quartus Il 12 0 For some commands it is necessary to access two or more menus in sequence We use the convention Menu1 gt Menu2 gt Item to indicate that to select the desired command the user should first click the left mouse button on Menu1 then within this menu click on Menu2 and then within Menu2 click on Item For example File gt Exit uses the mouse to exit from the system Many commands can be invoked by clicking on an icon displayed in one of the toolbars To see the command associated with an icon position the mouse over the icon and a tooltip will appear that displays the command name 3 1 Quartus II Online Help Quartus IT software provides comprehensive online documentation that answers many of
28. light bd f a Se a jt Entity jaj db Gat Wd amp amp BB oo d Cydone Il EP2C35F gt light SE Critical Warning Location Locate 00 00 14 Figure 19 The completed schematic diagram 6 Compiling the Designed Circuit The entered schematic diagram file light bdf is processed by several Quartus II tools that analyze the file synthesize the circuit and generate an implementation of it for the target chip These tools are controlled by the application program called the Compiler Run the Compiler by selecting Processing gt Start Compilation or by clicking on the toolbar icon that looks like a purple triangle Your project must be saved before compiling As the compilation moves through various stages its progress is reported in a window on the left side of the Quartus II display Successful or unsuccessful compilation is indicated in a pop up box Acknowledge it by clicking OK which leads to the Quartus II display in Figure 20 In the message window at the bottom of the figure various messages are displayed In case of errors there will be appropriate messages given When the compilation is finished a compilation report is produced A tab showing this report is opened automat ically as seen in Figure 20 The tab can be closed in the normal way and it can be opened at any time either by selecting Processing gt Compilation Report or by clicking on the icon The report includes a number of sect
29. luded in the project Choose light as the name for both the project and the top level entity as shown in Figure 4 Press Next Since we have not yet created the directory introtutorial Quartus II software displays the pop up box in Figure 5 asking if it should create the desired directory Click Yes which leads to the window in Figure 6 Altera Corporation University Program 5 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus I 12 0 Directory Name Top Level Entity page 1 of 5 What is the working directory for this project D introtutorial What is the name of this project light What is the name of the topfevel design entity for this project This name is case sensitive and must exactly match the entity name in the design file light e Use Existing Project Settings lt Back Figure 4 Creation of a new project i Directory D introtutorial does not exist Do you want to create it Figure 5 Quartus II software can create a new directory for the project Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 Add Files page 2 of 5 al aa a ia Click Add All to add all design files in the project directory to the ce you can always add design files to the project later File name onus Add File Name Type Library Design Entry Synthesis Tool HDL Version Remove Up Down Properties Spe
30. matic File bdf In the Altera Corporation University Program 1 May 2012 New Quartus IT Project 4 Design Files AHDL File EDIF File Qsys System File State Machine File SystemVerilog HDL File Td Script File VHDL File Verilog HDL File 4 Memory Files Hexadecimal Intel Format File Memory Initialization File 4 Verification Debugaging Files In System Sources and Probes File Logic Analyzer Interface File SignalTap II Logic Analyzer File 4 Other Files AHDL Indude File Block Symbol File Chain Description File Synopsys Design Constraints File Text File i Figure 12 Choose to prepare a block diagram J c EB Date modified 11 4 2011 2 58 PM r3 4 File name Save as type Block Diagram Schematic Files bdf IM Add file to current project Figure 13 Name the file QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Type File folder For Quartus IT 12 0 box labeled File name type light to match the name given in Figure 4 which was specified when the project was created Put a checkmark in the box Add file to current project Click Save which puts the file into the directory introtutorial and leads to the Graphic Editor window displayed in Figure 14 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 Quartus I 64 Bit D introtutorial light light File Edit View Project Assignments Processing Tools Window Help cear Y
31. n accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties repre sentations or guarantees of any kind whether express implied or statutory including without limitation warranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed Altera Corporation University Program 41 May 2012
32. n is used to verify the functional correctness of a circuit as it is being designed This takes much less time because the simulation can be performed simply by using the logic expressions that define the circuit 8 1 1 Functional Simulation To perform the functional simulation return to the QSim Window and select Assign gt Simulation Settings to open the Simulation Settings window in Figure 37 Click the Browse button and select the light vwf file you created Choose Functional as the simulation type and click OK Before running the functional simulation it is necessary to create the required netlist which is done by selecting Processing gt Generate Simulation Netlist A simulation run is started by Processing gt Start Simulation or by using the icon E At the end of the simulation Quartus II software indicates its successful completion and displays a Simulation Report illustrated in Figure 38 If your report window does not show the entire simulation time range click on the report window to select it and choose View gt Fit in Window Observe that the output f is as specified in the truth table of Figure 11 30 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 E Simulation Settings Specify VWF File D introtutorial light wwf Simulation Type Functional f Timing OK Cancel Figure 37 Specifying the simulation type a Simulation Waveform Ed
33. n the time interval O to 100 ns which is probably already set by default Next set x to 1 in the time interval 100 to 200 ns Do this by pressing the mouse at the start of the interval and dragging it to its end which highlights the selected interval and choosing the logic value 1 in the toolbar Make x2 1 from 50 to 100 ns and also from 150 to 200 ns which corresponds to the truth table in Figure 11 This should produce the image in Figure 36 Observe that the output f is displayed as having an unknown value at this time which is indicated by a hashed pattern its value will be determined during simulation Save the file Altera Corporation University Program 29 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 Search altera com IQ Ho Ze eB XE E ye EH Master Time Bar Ops gt Pointer 3 26 ns Interval 3 25 ns Start 50 0 ns End 100 0 ns i l 40 0 ns 160 0 ns 200 0 ns Value at i i Name 0 ps x1 BO x2 BO F EX 0 00 00 00 Figure 36 Setting of test values 8 1 Performing the Simulation A designed circuit can be simulated in two ways The simplest way is to assume that logic elements and intercon nection wires in the FPGA are perfect thus causing no delay in propagation of signals through the circuit This is called functional simulation A more complex alternative is to take all propagation delays into account which leads to timing simulation Typically functional simulatio
34. nstant Verilog loops Iteration limit for non constant Verilog loops nchronous dear preset behavior for DDIO INPUT when unmap 1 0 wysiwyg primitives Location Accepts wildcards groups Figure 26 The available assignment names for a DE series board Altera Corporation University Program 23 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 E Assignment Editor D introtutorial light light File Edit View Tools Window Help Search altera com lt lt new gt gt Filter on node names ka Category All Assignment Name Value Enabled nti Comment Location PIN_N25 Yes FP Location PIN_N26 Yes Ps Location PIN_AE2 2 Yes 0 00 00 00 Figure 27 The complete assignment The DE series board has fixed pin assignments Having finished one design the user will want to use the same pin assignment for subsequent designs Going through the procedure described above becomes tedious if there are many pins used in the design A useful Quartus II feature allows the user to both export and import the pin assignments from a special file format rather than creating them manually using the Assignment Editor A simple file format that can be used for this purpose is the Quartus II Settings File QSF format The format for the file for our simple project on a DE2 board is set_location_assignment PIN_N25 to x1 set_location_assignment PIN_N726 to x2 set_location_assignment PIN_AE22 to f By adding lines t
35. nto light gsf bak before importing Advanced Figure 29 Importing the pin assignment For convenience when using large designs all relevant pin assignments for the DE series board are given in individ ual files For example the DE2 pin assignments can be found in the DE2_pin_assignments gqsf file in the directory tutorials design_files which is included on the CD ROM that accompanies the DE series board and can also be found on Altera s DE series web pages This file uses the names found in the DE2 User Manual If we wanted to make the pin assignments for our example circuit by importing this file then we would have to use the same names in our Block Diagram Schematic design file namely SW 0 SW I and LEDG O for x1 x2 and f respectively Since these signals are specified in the DE2_pin_assignments qsf file as elements of vectors SW and LEDG we must refer to them in the same way in our design file For example in the DE2_pin_assignments qsf file the 18 toggle switches are called SW 17 to SW O In a design file they can also be referred to as a vector SW 17 0 Altera Corporation University Program 25 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 8 Simulating the Designed Circuit Before implementing the designed circuit in the FPGA chip on the DE series board it is prudent to simulate it to ascertain its correctness The QSim tools can be used to simulate the behavior of a designed circui
36. o the file any number of pin assignments can be created Such gqsf files can be imported into any design project If you created a pin assignment for a particular project you can export it for use in a different project To see how this is done open again the Assignment Editor to reach the window in Figure 27 Select Assignments gt Export Assignment which leads to the window in Figure 28 Here the file light qsf is available for export Click on OK If you now look in the directory you will see that the file light qsf has been created 24 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 Assignments to export File name D introtutorial atom_netists light qsf Export assignments hierarchy path light E Export back annotated routing Save intermediate synthesis results Save a nodedevel netlist of the entire design into a persistent source file File name Figure 28 Exporting the pin assignment You can import a pin assignment by choosing Assignments gt Import Assignments This opens the dialogue in Figure 29 to select the file to import Type the name of the file including the gsf extension and the full path to the directory that holds the file in the File Name box and press OK Of course you can also browse to find the desired file Specify the source and categories of assignments to import File name Categories Copy existing assignments i
37. p Search altera com 2 Coeha St BB Oo it EY 2S VS Dr SH A Project Navigator hed ANTERA m m NRN a Version 12 oP eae E 4 Analysis amp Synthesis o View Quartus II Information 1D Edit Settings m Documentation x Y lt lt Search gt gt Type Message System Pr Location Z Locate 00 01 08 Figure 10 The Quartus II display for a created project 5 Design Entry Using the Graphic Editor As a design example we will use the two way light controller circuit shown in Figure 11 The circuit can be used to control a single light from either of the two switches x and x2 where a closed switch corresponds to the logic value 1 The truth table for the circuit is also given in the figure Note that this is just the Exclusive OR function of the inputs x and x2 but we will implement it using the gates shown X1 SERO f 0 0 0 f 0 1 1 1 0 1 1 1 0 Xa Figure 11 The light controller circuit The Quartus II Graphic Editor can be used to specify a circuit in the form of a block diagram Select File gt New to get the window in Figure 12 choose Block Diagram Schematic File and click OK This opens the Graphic Editor window The first step is to specify a name for the file that will be created Select File gt Save As to open the pop up box depicted in Figure 13 In the box labeled Save as type choose Block Diagram Sche
38. r open the file light bdf Remove the wire connecting the output of the top AND gate to the OR gate To do this click on the icon click the mouse on the wire to be removed to select it and press Delete Compile the erroneous design by clicking on the icon A pop up box will ask if the changes made to the light bdf file should be saved click Yes After trying to compile the circuit Quartus II software will display a pop up box indicating that the compilation was not successful Acknowledge it by clicking OK The compilation report Altera Corporation University Program 19 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 summary given in Figure 21 now confirms the failed result In the Table of Contents panel expand the Analysis amp Synthesis part of the report and then select Messages to have the messages displayed as shown in Figure 22 The Compilation Report can be dispayed as a separate window as in Figure 22 by right clicking its tab and selecting Detach Window and can be reattached by clicking Window gt Attatch Window Double click on the first error message which states that one of the nodes is missing a source Quartus II software responds by displaying the light bdf schematic and highlighting the OR gate which is affected by the error as shown in Figure 23 Correct the error and recompile the design Quartus I 64 Bit D introtutorial light light File Edit View Project Assignment
39. r window Observe that the configuration file light sof is listed in the window in Figure 40 If the file is not already listed then click Add File and select it This is a binary file produced by the Compiler s Assembler module which contains the data needed to configure the FPGA device The extension sof stands for SRAM Object File Click on the Program Configure check box as shown in Figure 42 Altera Corporation University Program May 2012 33 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 Hardware Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Curent selected hardware Available hardware items Remove Hardware Figure 41 The Hardware Setup window diiy Programmer D introtutorial light light light cdf File Edit View Processing Tools Window Help Checksum Usercode O02F836D FRFFFFFFF Figure 42 The updated Programmer window Now press Start in the window in Figure 42 An LED on the board will light up when the configuration data has been downloaded successfully If you see an error reported by Quartus II software indicating that programming failed then check to ensure that the board is properly powered on 34 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 9 2 Active Serial Mode Pro
40. re the acronym stands for Electronic Design Automation This term is used in Quartus II messages that refer to third party tools which are the tools developed and marketed by companies other than Altera Since we will rely solely on Quartus II tools we will not choose any other tools Press Next 6 A summary of the chosen settings appears in the screen shown in Figure 9 Press Finish which returns to the main Quartus II window but with light specified as the new project in the display title bar as indicated in Figure 10 Altera Corporation University Program 9 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 Summary page 5 of 5 When you dick Finish the project will be created with the following settings Project directory D introtutorial Project name light Toptevel design entity light Number of files added 0 Number of user libraries added 0 Device assignments Family name Device EDA tools Design entry synthesis lt None gt lt None gt Simulation lt None gt lt None gt Timing analysis lt None gt lt None gt Operating conditions Core voltage Junction temperature range Figure 9 Summary of project settings 10 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus I 12 0 p Quartus I 64 Bit D introtutorial light light File Edit View Project Assignments Processing Tools Window Help am
41. s Processing Tools Window Help amp TLEL EE DY GODE WOREE Project Navigator Og x fr light bdf E Compilation Report E Table of Contents OF very E5 Flow Summary Flow Status Flow Failed Tue May 08 13 39 46 2012 Cydone II EP2C35F672C6 i Quartus II 64 Bit Version 12 0 Build 173 05 02 2012 SJ Full Version ight d Flow Settings Revision N light ES Flow Non Default Global Setting 4 m Top evel Entity Name light ES Flow Elapsed Time Family Cydone II y Hierarchy Files d Design Units EB Flow OS Summary Device EP2C35F672C6 Analysis amp Synthesis Total logic elements N A until Partition Merge Flow Customize Total combinational functions N A until Partition Merge Dedicated logic registers N A until Partition Merge Task E Total registers N A until Partition Merge x 4 Compile Design Total pins N A until Partition Merge gt Analysis amp Synthesi Total virtual pins N A until Partition Merge Total memory bits N A until Partition Merge Fitter Place amp Route Embedded Multiplier 9 bit elements N A until Partition Merge Assembler Generate program Total PLLs N A until Partition Merge gt TimeQuest Timing Analysis WT p Entity Type Message Warning 275008 Primitive AND2 of instance inst not used Warning 275008 Primitive NOT of instance inst3 not used Error 12009 Node inst4 is missing source Error Quartus
42. t Before the circuit can be simulated it is necessary to create the desired waveforms called test vectors to represent the input signals It is also necessary to specify which outputs as well as possible internal points in the circuit the designer wishes to observe The simulator applies the test vectors to a model of the implemented circuit and determines the expected response We will use the Quartus II Waveform Editor to draw the test vectors as follows 26 Select Start gt All Programs gt Altera gt University Program gt Simulation Tools gt QSim to open the QSim tools which will display the window in Figure 30 Select File gt Open Project to display a popup window in which you can browse your directories and choose a project file gpf file Select the project you wish to simulate and click OK Generate the node finder files by selecting Processing gt Generate Node Finder Files From QSim open the Waveform Editor window by selecting File gt New Simulation Input File 7E Qsim File Assign Processing Help a lt gt gt To get started open an existing Quartus II project by selecting File gt Open Project gt gt To produce an input waveform file select File gt New Simulation Input gt gt In the displayed window create the desired input waveforms Give it a suitable name and save it gt gt gt To specify a setting for simulation select Assign gt Simulation Settings gt
43. t port and one instance of the output port to obtain the image in Figure 17 Altera Corporation University Program 15 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 E Quartus I 64 Bit D introtutorial light light File Edit View Project Assignments Processing Tools Window Help E Search altera com DSW S teno Hr G VS Tr KY od Be eS ProjectNavigator A itb B Entity SB e amp O AD O0A17TINNNOONS A Cydone I EP2C35F light Fa Ja daa W g BA a 4 m Tasks ax o n Task Location x Locate 317 176 2 00 00 14 Figure 17 Import the input and output pins Assign names to the input and output symbols as follows Make sure nothing is selected by clicking on an empty spot in the Graphic Editor window Point to the top input symbol and double click the mouse The dialog box in Figure 18 will appear Type the pin name x1 and click OK Similarly assign the name x2 to the other input and f to the output Alternatively it is possible to change the name of an element by double clicking on the name and typing a new one directly 16 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 General Format To create multiple pins enter a name in AHDL bus notation For example name 3 0 or enter a comma seperated list of names Pin name s xil Default value VCC Figure 18 Naming
44. the NOT gates into proper position by using the Rotate left 90 icon de Arrange the gates as shown in Figure 16 Altera Corporation University Program 13 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 4 amp d gshell_11_1_now2 acds quartus b E megafunctions gt EQ others a 4 amp primitives gt buffer 4 EF logic bt andiz ET and2 Et and3 and2 Repeat insert mode Insert symbol as block Launch MegaWizard Plug In Figure 15 Choose a symbol from the library 14 Altera Corporation University Program May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 E Quartus I 64 Bit D introtutorial light light File Edit View Project Assignments Processing Tools Window Help E Search altera com Dad St Se oo Evy G VS Orv sd or eS ProjectNavigator A itb B Entity SRS MTADZ OTIINN VOON NS d Cydone Il EP2C35F light Fa j 4 4 at amp y BA Nna 4 coll Tasks eax 0 F Pad Task Location x Locate 36 183 2 00 00 14 Figure 16 Import the gate symbols into the Graphic Editor window 5 2 Importing Input and Output Symbols Having entered the logic gate symbols it is now necessary to enter the symbols that represent the input and output ports of the circuit Use the same procedure as for importing the gates but choose the port symbols from the library primitives pin Import two instances of the inpu
45. w Help G Parc h a t era com E lt Hardware Setup USB Blaster USB 0 Mode Active Serial Programming Enable real time ISP to allow background programming for MAX II and MAX V devices Checksum Usercode Program Verify Blank Examine Configure Check ih Stop 10790424 ooo0o000 aN E E cee Auto Detect Delete Add File Change File Save File G Add Device Up Down Figure 49 The updated Programmer window Flip the RUN PROG switch on the DE series board to the PROG position Press Start in the window in Figure 49 An LED on the board will light up when the configuration data has been downloaded successfully Also the Progress box in Figure 49 will indicate when the configuration and programming process is completed as shown in Figure 50 Altera Corporation University Program 39 May 2012 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS For Quartus II 12 0 diiy Programmer D introtutonal light light light cdf File Edit View Processing Tools Window Help Search altera com Atadnare sete EEE Mode Active Seral Programming Progress E Enable real time ISP to allow background programming for MAX II and MAX V devices ile Device Checksum Usercode Program Verify Blank Examine pe Start Configure Check gilt Stop EPC516 1 790424 ooooo000 E E wi LULI cee Auto Detect Delete ta Add File i Change File et Save File G
46. ware are used some of the images may be slightly different Contents Typical CAD Flow Getting Started Starting a New Project Schematic Design Entry Compiling the Design Pin Assignment Simulating the Designed Circuit Programming and Configuring the FPGA Device Testing the Designed Circuit Altera Corporation University Program 1 May 2012 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For Quartus Il 12 0 2 Background Computer Aided Design CAD software makes it easy to implement a desired logic circuit by using a programmable logic device such as a field programmable gate array FPGA chip A typical FPGA CAD flow is illustrated in Figure 1 Design Entry Functional Simulation Timing requirements met Yes Programming and Configuration Figure 1 Typical CAD flow The CAD flow involves the following steps e Design Entry the desired circuit is specified either by means of a schematic diagram or by using a hardware description language such as Verilog or VHDL e Synthesis the entered design is synthesized into a circuit that consists of the logic elements LEs provided in the FPGA chip e Functional Simulation the synthesized circuit is tested to verify its functional correctness this simulation does not take into account any timing issues 2 Altera Corporation University Program May 2012 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For Quartus Il 12 0 Fitting
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