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1. CHAPTER 5 EXAMPLES In order to implement the algorithms discussed in the previous chapters two examples with details are presented in this chapter In the first section a linear circuit a BJT sadi signal amplifier circuit with beta independent bias is used to describe the procedure of a linear circuit package The second example is a power supply circuit which demonstrates the nonlinear circuit package Linear Case Consider a linear circuit a BJT small signal amplifier circuit with beta independent bias as shown on the data sheet in Table 5 1 The data sheet contains information about the three Mts in the test program generation process The user will enter the above input data by responding to the prompt shown on the terminal under off line L Matrix After the circuit description is entered an incidence matrix for this circuit is created as follows 0 1 0 0 1 0 OO OO omer OOo QOO O00 dO OO O0O0Q0c 00 000 20000 m ooo o 1 0 0 0 0 C O OO OOO 0 The matrix D in the equation 4 4 is calculated by calling a sub routine DMXGEN to transfer the matrix A to the following form 7 72 Table 5 1 Data Sheet Linear Circuit Number of components Eo Number of Nodes 2 Cenponent Description m do rud E A E E A A Ls e e am am am E HZ gt hm ZO O Ht SS YH AnS S MCN d C R i Ro R i Q Ro C i C 0 p ooo boat 4 HH 4 pe eae CL c RIS
2. Maximum Number e of Simultaneous Failures Data File for Z and u Test program Data File for Test Data y Component Subdivisions Table Component Subdivision J Result a oer Decision Algorithm Print Display Faulty Component s Figure 3 9 On Line Component Nonlinear Case 38 CHAPTER 4 ALGORITHMS Along with the software developed in the previous chapter it is desirable that the AATPG be run in a fully automatic mode or inter actively inorder to simplify the process of generating new test pro grams for both linear and nonlinear circuits To this cause some supporting algorithms are discussed in the first section In the second section three decision algorithms are presented to make the de cision for the choice of the component subdivision Supporting Algorithms As described in the previous section given a circuit one can generate a data base by computing the matrix K together with some known parameters The measured data and the stimuli will be used as the inputs to the test program while a test is conducted and then a number of on line simulations pod out In this section the following problems with algorithms are discussed 1 The generation of the mena matrix L with the users inputs 2 The kind of subdivisions to be chosen under the assumption that fie exists 3 Based on the above subdivisions
3. Oe e eo ee io Q e 9 e ea o O CO e nm OS 9 O x os e 8 gt O O e n 66 The above algorithm is called Regular Boolean algorithm To accelerate the speed of convergence one may specify the maximum number of simultaneous failures Once this number has been specified the im possible patterns will be reduced For example if a single failure is assumed recall from the first term of 4 13 a the component a is bad and the remaining components are don t dion either good or bad Since at most one faulty component is allowed the remaining components would not be bad therefore the component a is the only bad component in this possible pattern It is the same as the remaining terms in equation 4 13 The tabulated expression will be rewritten as follows OOOooOo0 OOooo0 oO CeOoOo docoIio COOo o0o0dcojia CQ 2 0 O0 O OIjn OO0O0OO O x 00000 OO0OOOOON Similarly the tabulated expression for 4 14 can be simplified by replacing 6 by 0 The intersection of these two expressions as shown above will be reduced by deleting those terms which contain more than one failure that is the items 4 5 6 7 and 8 are deleted and by replacing all e by 0 in items 1 2 and 3 The tabulated expression of this inter section is thus shown as follows abcde x y Z 1i 0 000000 0100000 0 001000 0 0 67 which shows that the components a b and c ar
4. a v 2 ss 6 E lx ALGORITHM II Component Subdivisions Table Step 1 Matrix L2 is an m by b matrix pick any m columns of matrix L2 to form a matrix Step 2 IF matrix is invertible THEN record the number of these m s column ELSE pick next m columns to form a matrix Step 3 Repeat 2 until all combinations have been chosen Data Base Given any component subdivision a pseudo circuit with connection matrix K is created by computing the equations 2 12 through 46 2 15 The data base for the linear case is generated by computing matrix M equation 2 16 and stored in the data files In the nonlinear case the data base is SPICE codes for equations 2 23 through 2 26 The SPICE code is generated as follows Consider the equations 2 23 through 2 26 EE x aly al ah x 0 0 2 23 ia 1 aS Ke be Kur 2 24 P 1 p y Koi b Ko u 2 25 x2 Fe x a 2 x 0 2 0 2 26 b sg ka where uP col u y and yP col a b Our goal is to compute the 2 2 1 values of b and b from the above equations Solving the values b from equations 2 23 and 2 24 plugging p into equation 2 25 for yP j e a and b and substituting the values ac into 2 26 to solve b Mathematically the equation 2 24 shows that the element PE i th element of 3 is the sum of the products of the i th row of Kay and pb and the products of the i th row of Ky5 and uP Physically suppose
5. m TTT TT O E Tee K Lo X ONT n 1 Ti i Ey Ty ye i TU E ve 1 A te et ME ID i Y 3 3 i i A Lennon o eo dono ER Ho 4 oooo 4 y C i DI Y 4 5 i i i i woe ee ee a a ee eae ae errr gt o 1 t i 1 i v 1 VPL L Y G 7 NETS er a ooo Ho ooo doo R ooo de 44 i i i i H 4 o Foo tooo 4 oo o hno l E T Ca fren the entries of a Y N 2 number of nonzero elements 86 SPICE Code for the Circuit Based on the circuit description a SPICE code is generated as shown below several new nodes are assigned due to the performance of current measurements The generated SPICE code is stored in a data file named MAIN DT The circuit diagram with new nodes is shown in Figure 5 1 Figure 5 1 Power Supply Circuit T 87 The SPICE code is SPICE CODE MODEL DM D IS 1 0E 06 N 0 97 VIN 4 0 SIN 0 10 60 VK21 1 5 0 W22 2 6 0 RI 4 1 5 C1 1 2 1 D1 5 2 DM C2 2 0 M L1 6 3 0 1 C3 3 0 IM RL 3 0 K TRAN 10M 200M Recall that the test points are ID IL and VRL In order to measure the current flow through Dl a zero valued voltage source VK21 is added and a new node node 5 is assigned to the circuit diagram The current flows through the voltage source VK21 I VK21 is then equal to ID Similarly a zero valued voltage source and node 6 are added to the circuit diagram for IL S
6. the group 1 components The equation 2 11 can be written as constant term n m a S bi 2 i es 21 n m 2 z t k d by J K5 b constant term t m i k If s or 58 K K is not 2j 15 not zero then the group 1 component k effects the group 2 component i and the components i and k are therefore coupled ALGORITHM VI Step 1 Step 2 Coupling Table Generate the matrix A for the relationship between the group 1 components 1 By a transitive closure algorithm Te cto eck A 18 where EK gives an explicit accounting of all the vertices jointed by paths of length k 6 is the Boolean or ex pression and Ais is defined as A ij if i effects j O otherwise Let E be the matrix Kj in the equation 2 12 a m by m matrix and Ko is a 2m by m matrix Initialize A 0 F 1 1 1 for 1 1 2 m K11 is DO i TO m l F lt F E i e F E IF F j k 1 THEN M m for all j and k End of loop Generate the matrix B for the relationship between the group 2 components and the group 1 components Let By and Bo be two Boolean matrices which are defined as follows DNE M ER B 0 if Ko 0 o m B f ij o J7 15 2 n m if K53 A and a 1 1j 8n 0O if 21 0 i mtl m 2 2m if Ko 20 j 1 2 n m therefore B B9B define the matrices Bj and Bo DO i TO m DO j TO n m IF Koi 1 3 0 THEN B1 1 3 0 59 ELSE Bisa IF
7. Measurement Unit Simulus Unit UUT ATE Interface Automatic Test Equipment Figure 1 1 Simplified Block Diagram of Typical ATE 9 directly measurable quantity such as a voltage or it may be a derived quantity from physical measurements such as a resistance Therefore these units include voltmeters current meters phase meters impedance bridges frequency counters A D converters etc UUT ATE Peas provides the connection of the UUT to the ATE which has the incompatible connecting points Usually an adapter is used to define items that in terface the UUT to the switch unit It may be test boards fixtures or sockets that contact the leads or terminals of a component Output unit is a device which is used to display the test results It may be a CRT terminal or line printer or may transfer this test data to the host computer which provides a fault diagnosis The testing starts after connecting the UUT to the test equipment through an interface The computer output a synthesis of an electrical signal is converted by means of a digital to analog D A converter into voltage or current levels These signals are applied to the UUT yia a switching unit and interfaces The test results are routed via the switching unit to a sampling instrument The measured quantity is con verted to digital representation and this time series is analyzed by the computer The computer output of the results can be presented in any for
8. false j 1 2 n Step 2 Choose a component subdivision Step 3 Call subroutines to derive the simulation results Step 4 Let G00D j be the good components j 1 2 8 Step 5 Retrieve the coupling table TABLE m n m DO j 1 TO s Let x be the row of the component GOOD j DO k 1 TO n m IF TABLE x k 1 THEN record this component as good End of Loop k End of Loop j Step 6 IF t 1 GOTO Step 9 For single failure case All or all but one components in group 2 are inoue to be good Step 7 FLAG GOOD j true j 1 2 5 Step 8 To have more simulations if so go to step 2 Otherwise end of this algorithm Boolean Algorithm In this algorithm a Boolean expression is derived from each step of the test algorithm which includes all possible fault patterns associated with the test data The actual fault s can be located by multiplying the Boolean expressions associated with several steps of the algorithm or equivalently comparing the fault patterns obtained from each test step and excluding the impossible fault patterns Consider the case where group 1 contains five components a b c d and e group 2 contains three components X y and z Suppose that the test results is indicated as follows 61 The group 1 components are assumed to be all good so that the test is reliable that is the components a b c d and e are good The test results show that x and z are good and y is possibly faulty where the test res
9. i i ii 5 2 2 po 2 z i i wee Lo i 2 o3 0 3 od 0 i i i 3 y 4 1 I 1 1 i I L L 1 i 1 i 27 2G D LUI ES RARUS Wozu Xu anene wells Dese Soy SACS R n TESI STENTCE E E RE A C Cn CUSEL LLANES E PN x LN ee L Lr Ineve rence Cpls ha dicas D DT model mane PE GLO insensatos E Cn moze name C 3 E AE oC IE moce Nanc Rig ted o8 e eL CIE 5 Table 5 2 Continue i Number of Voltage Sources Number of Current Sources M T T T 4T branch number n y d a Ho an aE S S S value 0 O85 SIN O 10 50 i i S notation AE xxv VIN H y i mmm A O e a mi a q l A E A A O AA OA OA O Ht coincide 2 Y N N i 1 i i A e ee HH AAA Does the orientetion of this source coincide with thet of the branch 7 1 Fe any numerical expression PRANe tent Time step 10M Final time 200M opticn setaeariing time Control Cards options 1 z fest Pointes Number ef Test Points 3 o ba a ea a ee eer rant ro notation 1 entry i 2 coiumns i valves p tee
10. 22 2L Lj Ha Lo Koo el L21 Lo mI Bazsa Kia I2 gt Lig E Lag Lyg ial TA E Ly Lz 2 4 L 2 12 2213 2 14 2 15 For each pseudo circuit substituting equation 2 9 into equations 2 10 and 2 11 the equations with the transfer function matrix M are shown as follows l p p T1 p y 12 b Koo u and y M uP where ee LEA A Raak 21 11 12 22 Specifically 2 16 14 a My u Mo y 2 17 b Mnr u M 2 22 Y 2 18 Since the matrix M is independent of the test data and computed in terms of the nominal values of the group 1 components it may be com puted off line and stored in a data base to be retrieved at the time a test is conducted Furthermore since only a single test vector is required single frequency testing can be employed In this case M need only be computed at a single frequency The only on line computation required for the fault diagnosis of a linear system is the matrix vector multiplication indicated by equations 2 17 and 2 18 together with the computation of b e 2 m 2 19 to determine which if any of the group 2 components are bad Nonlinear Case For the nonlinear case one may formulate an identical algorithm in which the component characteristics are represented by a set of decoupled state models together with an algebraic equation as follows x Bos 1 ME a x 0 20 i5 1 2 n 2 20 b g x a and a La
11. H i i i i i i Soto R ho Y do Ho ooo tooo i J 3 i i 1 I n 1 1 i D 1 i n o bo Ho Ho toooo ooo L i t 1 L D i i 3 LI I t V i t 1 E 4 R q ho boo Hoooo 3 1 1 i L t L a b 3 y i L L Hon tooo tooo Ho Ft o i i 1 5 1 Lj a 1 y a 1 4 5 1 i 3 b a i 3 ee he ee a o A LLL ae e T i 1 J I y y Y 1 1 J 2 D i D 1 i i D poe ee a ee a a a te ett ret 0 i i i 1 i 1 fA A 4 HMMM Soo Ho T c t i I 1 1 3 i Li 3 i MMMM 4 tooo 4 o 4 i i i i gt o dioe pi E e SA A eme a cie e Sa eee 1j 2 2 CA seir morator component veive poca K r n resistance C Cn cpecitence tt Cd L L ri inductence don O Cn voltege cain input 4 0u0tpu G en h ugbraid p C R E Hie Hre hfe moc 3s DEEP T tr formation rimaru vcTaoneczovinCcv An TTVENSTOVMa esa Os P lat wu Tc tio secondary tes les s A ae ME M e A A D a 74 Table 5 1 Continued Con Ve ced E SUTEE Descriptio Number of Voltage Sources 5 pr os Number of Current Sources 0 O a Th re a o a a E E E branch number n i 1 i 11 i IN O ER De
12. Iscilla EE TE IS 96 SPICE codes for ASTABLE and OSC CKTs 97 CHAPTER 1 INTRODUCTION Electronics design has become very sophisticated during the past quarter century Graphical algorithms have been replaced by CAD Computer Aided Design and features of design implementation can be studied by simulation rather than requiring T breadboarding Electronics maintenance however has changed very little during the same period In fact many industries have found that the life cycle maintenance costs for their electronics equipment exceed their capital investment Consequently it is becoming apparent that the new maintenance process like the design process must be automated Several formidable problems are faced in the maintenance of mili tary electronics the avionics and missiles are becoming far too complex for the typical military technician to maintain the time required to test systems is becoming excessively large system designs are changing too fast to keep maintenance documents current Hence a more economical approach to maintenance is an actual necessity Therefore a multi purpose automatic test equipment ATE which promises testing at computer speeds fully automatic operation by low skill operators the virtual elimination of maintenance documents and universal designs adaptable to any test problem through the flexibility of programming has been in vestigated by several research groups Efforts at producing algorit
13. Regular Boolean algorithm However some of these patterns will be eliminated when one or more components which were known to be good were predicted as bad by the pattern Don t care values in the pattern will be replaced with good when a component is known to be good 68 For example consider the resultant expressions Ty and Tos since the components x and z are known to be good in the first subdivision T and then all in columns x and z are replace by 0 to rewrite the tabulated expression for T4 abc dex yz l 6 4 4 09 0 l 9 9 9 0 0 14 4 09 0 6 14 09 0 9 10 49 0 0000001 0 Similarly the eomponent y is known to be good in the second subdivision T Therefore the impossible patterns in T will be eliminated again for the good component y that is the last row will be deleted because of contradicting that component y is known to be good and all 6 in the column y of the remaining rows will be replaced by 0 Since the com ponents x y and z are known to be good as a result all in the columns x y and z in T are replace by 0 This heuristic reduces and simplifies the possible patterns for both Ta and To ly d b c d e x yc To b c d e 1 0 0 1 4 0 0 0 14 000 14 4 0 0 0 8 1 9 0 0 0 6 9 1 6 000 6 6 14 0 D0 OD 0 0011000 6 6 6 4 1000 After multiplying these two Boolean expressions the reduced table for the intersection is a b c
14. SS A E SS SS SSS ner trom the entrics of a Y Y N See of Trans ro elements 75 0 0 0 E 0 0 0 0 0 0 0 0 0 and the matrix D is ee a ES 0 0 1 0 D 0 0 1 0 0 0 0 0 1 I 0 0 1 0 1 0 0 By the equation 4 6 the Li matrix is then derived as 0 0 0 0 0 0 0 0 0 D 0 0 oo a 0 0 0 L E M D 00 OF lt 1 0 0 0 1 1 1 1 0 1 1 0 0 Oo 0 0 0 0 0 0 0 0 0 OOooOoooc Lani ap i ae i ap Ei ee ae oOO0O00 0 OOOO 00 Oo0o0o0Oo0O The order of the components was Cl R1 R2 RC Q1 1 Q1 2 RE CE C2 RL and R3 After the transformation is performed the order is rearranged to be C1 R1 RL RC Q1 1 CE RE C2 Q1 2 R3 and R2 and the component inputs vector a and component outputs vector b are shown as follows 76 IC VCI IR VRI IRL VRL IRC VRC d 1801 b VBEQI VCE ICE VRE IRE VC2 IC2 VCEQ1 ICQ VR3 IR3 VR2 IR2 where the first five components are in the tree edges and the remaining components are in the co tree edges As illustrated in the data sheet information for source description Shows that two voltage sources are located in the branches 1 and 1l respectively Since in branch 1 the capacitor Cl is located in the tree edge and the orientation of the voltage source is opposite to that of this branch equation 4 7 therefore implies that the first column of Lio is the same as the row corresponding to Cl in the matrix Li An other voltage source VCC i
15. The system is k diagnosable if and only if the global column rank of the matrix Lo is at least k 1 Theorem 6 General case The system is k diagnosable if and only if the L rank of the matrix Lo is at least k 1
16. a a a E E E value 33 2 6E 03 1 10 i i o A netetion Lo OXXXXX 4 VIN i VCC i i o ooo tH HH A coincide x Y N N i y i i i iiM n aaa aaa aaa S Does the orientation of this source coincide with thet of the crcnch 7 2 enu numericel expression Input EFE CUECA FEvegquentyg 1000 Test Fointe Number of Tesi Points 4 4 a bP netatjon 1 sentry vr te i columns values ee et o bl ooo i XZXXX i YZI i n 1 T i mw t HF E 1 x X eet ee t 4 SSA ASA SS T 34 101 1 Y o 1 i i ooo T R k i 121 i Y 4 2 i 1 R Eo p L mE V45 ME KE A A 15 10 o 1 1 1 am eL am ee e a Roo _ __ _ _ _ _ _ 0 _c _ _ _ _ __ __ _ _ _ _ _ _ A2 d V13 i No E 2 4 i l 1l ee re dy tooo HR SS RS OO SO t L 1 t 1 NT 1 4 1 1 1 D R p S E a E E E amp a i h o t M qoe um omnee jh ese
17. but one of the group 2 components are found to be good i e at most one faulty component is found in each step Lemma 1 A system is l diagnosable if and only if every pair of elements appear in at least one group M a 104 105 Proof If x and y are two possible faulty components there exists a subdivision which contains x and y As shown in the above note in each step at most one faulty component is found implying that x and y cannot be faulty simultaneously therefore the system is diagnosable Conversely in the worst case if x and y do not appear in the same group 2 and also x and y are found to be possibly faulty implying that two possible faulty components are in this system contradicting the assumption of 1 diagnosable Theorem 1 For the case of all one port components The system is l diagnosable if and only if the flobal column rank of the matrix Loy is at least 2 Proof If the system is l diagnosable by Lemma 1 every pair of elements appears in at least one group 2 Let x and y be any pair of elements appearing in the group 2 In our algorithm the group 2 components are formed e combination of columns of Lor in which the matrix 1s invertible Therefore any two columns of this matrix of the column combination must be linearly independent i e the columns correspond ing to x and y are linearly independent The global column rank is then at least 2 Conversely if the global colu
18. d e x y Zz 16069606 000 1686 9 000 1 4 4 0 00 0 0 0 1 1000 69 The tremendous number of possible fault patterns is then greatly reduced Moreover if the maximum number of simultaneous failures is specified the resultant expression will be much more applicable ALGORITHM XI Boolean Exact Algorithm Step Step Step Step Step Step Step Step Step 9 ds Retrieve the component subdivisions table and input t The maximum number of simultaneous failures FLAG j false j 1 2 n Choose a subdivision Call subroutines to derive the test results and the tabulated expression Search the pattern which contains more that t s 1 and delete the impossible patterns Let GOOD j be the good components j 1 2 s For single failure case all or all but one components in group 2 are known to be good For multiple failure case the component with test result Q is indicated to be good FLAG GOOD j true j 1 2 S If this subdivision is the first one go to Step 2 Eliminate the impossible patters for both expressions Delete the patterns which predict the good components as bad and replace all 4 to be 0 for the good components Call a subroutine to compute the product of this expression and the previous one Search for the impossible patterns and delete them Repeat the above steps until the actual faulty components are determined Boolean Heuristic Algorithm Because of the advan
19. for components 72 8 and 9 are O and for component 1 is 1 With aid of the de cision algorithm the actual faulty components will then be determined Nonlinear Case Consider a nonlinear circuit power supply circuit as per the data sheet in Table 5 2 After user enters the number of components the number of nodes the circuit description and the test point descrip tion the connection matrix L and vectors a b u and y are automatically generated in the form IRI VRI vc IC u uy VIN ID VD a V2 b IC2 Y IDI IL 11 1 _ 1 VC3 103 dd ES a VRL IRL Y3 Mis 84 Table 5 2 Data Sheet Nonlinear Circuit Number cf components i 7 Number of Nodes bu we a a a ae ee ee eee a III ILI ILIILI LI IZLIILILLIII IIILILI LILLDLILLIIIII IILILLIILILIL ya D 1 D 1 p E i D od C Me L a AE Doa i i ILL ILuL No 1 1 I 1 Li 1 Cu qu ch qu dc oppor px p h ee eR oa be bo An A A A PE dy E iU DMI 1 Mo CI y op ve MD os IK 3 i er A A A EE Ee ASAS 4 eee l l iiIiMiIiMli ii iiiIiMi iMi iii Ii i i i I Ii iMii i
20. how to set up the data base off line so that the executing time of the on line can be mini mized and 4 How to decide a good component from the computed data 39 40 L Matrix This commonly encountered geometric connection model is the linear graph used for electric networks and other bilateral com ponents The linear graph like the signal flow graph is a directed graph composed of vertices and edges Here each edge represents a single bilateral component or a part thereof Associated with each edge is pair of variables Vs and I For an erectis network Vi depicts the port voltage and I the port current Vs is often generically termed an across variable and I a through variable They are not a priori identi fied as the component input and output For most components either may serve as the input with the other taken as the output The usual conser vation laws constrain the variables Vs and I In particular the Kirchhoff voltage law constrains Vio the Kirchhof currant law constrains I Let a graph have a specified tree containing r edges and the comple mentary co tree containing p r edges Here p is the number of edges in the graph The number r always equals h where n is the number of vertices in the graph Let B be the fundamental circuit matrix and f 5 be the fundamental cut set matrix then Be X Lap 4 1 5 LI D 4 2 where X is a p r xp matrix em and L are identity matrices and D
21. loop j End of Loop i Step 2 Reorder the expressions of Ty and T2 by placing the common terms to the beginning terms and copy this common terms to the first NUM terms of T4 IF NUM 0 THEN GOTO Step 3 ELSE Reorder Ty and T2 Copy first NUM terms to T4 Step 3 Find the intersection TERMS NUM DO izNUM 1 TO ty DO j NUM 1 TO t TERMS TERMS T DO k 1 TO n IF T1 k i o THEN T3 Uc TERMS T2 k 3 ELSE IF Ti k 4 1 AND T2 k 3 0 OR Ty k 1 0 AND To k j 1 THEN T3 k TERMS T1 k i ELSE TERMS TERMS 1 End of Loop k End of Loop j and i Following the above algorithm the tabulated expression of the inter and T section of T can be expressed as follows 1 2 M T n T row a b c d e x y z a b c d e x y z To 9 9 4 4 4 4 l p 9 6 9 6 6 2 9 1 9 6 9 6 6 b 149 06 06 06 9 3 6 9 16 6 6 6 6 x 06 4 16 06 94 94 6 4 9 9 1 9 9 9 6 b 9 9 49 l 5 6 6 9 4 l 9 9 6 6 6 9 9 6 6 4 l 6 0000001 0 0 0 0 17 1 0 0 0 B cb cC od s8 X Ve Z operation 16 9 6 9962 5 6 common term o 1 4 6 6 9 0 6 common term 6 6 9 9 4 6 6 common term 06 1 1 6 906 T1 4 T2 4 6 6 TG 94 l T1 4 T2 5 00011000 T1 4 T2 6 p o 4 1 l 9 T1305 T2 4 b 6 6 1 e 9 I TI165 12 5 0 001 OP 929 720 T1 5 T2 6 nul T1 6 To 4 0 1 for x nul I56 12 5 e D T or z nul T1 6 T2 6 0 1 for d After deleting the duplicated terms and rearranging their order the re duced table becomes Oe e 0 9
22. standard elements while in the nonlinear code standard SPICE circuit models are employed The input syntax is a free format style Linear Case Off line Component Design Stage The objective of the off line component is to generate the test program and the appropriate data for the test program verify and vali date the test program so that the faulty components can be actually detected and located Test Program Generation As illustrated in Figure 3 2 the input re quirements in the test program generation are Circuit Description Input Frequency and Accessible Test Terminals Circuit Description The Component Connection Model is used to simulate the UUT under nominal and faulty conditions In the case of a linear circuit the UUT components are characterized by a composite component model and the component equations are modeled in frequency domain The circuit description consists of two steps namely 20 Circuit Description Input Display Print L1 Matrix Frequency L1 Matrix Test Points 2sMatrix j Display Print Description L2 Matrix Pseudo Circuit Component K Subdivisions Eqns 2 12 2 15 Table Calculate Data Base Matrix M M Eqn 2 16 Figure 3 2 Test Program Generation Linear Case 21 1 Component Description 2 Source Description In the former the user is required to input the component type the component types currently available in this package are resistors in ductors c
23. that a is a one port component if the element a is a voltage measurement the b is then a current measurement Therefore the voltage a is the sum of the measured voltages of b and uP where the corresponding terms of the i th rows of Kay and Kio are not zero For example if 47 col V I V I pi Ipz Voz Ipaq gal I V P s col Vii Vu u3 ual i th row of Ku 1 0 1 0 0 and i th row of Kio 1 0 0 1 then Ngee Nga fc Vua 4 3 i e the voltage measurement at component a 1s the sum of the measured voltages Vii V53 V and V 4 In order to solve the equation 4 9 with SPICE program a cirduit type of description is used to generate the SPICE code Here the voltage controlled sources connected in series are used to indicate the sum of measured voltages Figure 4 1 Controlled Sources and the voltage measured at node is then the value of Vai Obviously once the values are known the component equation 2 23 will give the values pl In circuit specification the above box will be filled 1 by the component Given the values al evidently the values b may be 48 derived from their characteristics For example if the component is a resistor connecting the resistor in series with the above sources as shown in Figure 4 2 Since a is a voltage measurement the current la is the current that flows through the resistor Figure 4 2 Controlled Sources with Component Similarl
24. through 2 26 Program Verification In the linear case three tests are used to verify the software s ability to locate the faulty component Instead of using the test data y by computing equation 3 1 in the linear case here as indicated in Figure 3 7 we will modify the SPICE code for the Data File Test for Z and u Program Test with nonfaulty component Calculate y Component Component Subdivisions eqn 3 1 Subdivision Table 0 0 Data Base M Test Result Figure 3 7 Program Verification Nonlinear Case 34 Test with single Data File Test out of tolerance for Z and u Program failure component Test with single catastrophic failure component Loop for Component i 1 1 to n Loop for Component i i to n OPEN CKT SHORT CKT Out of From Tolerance Modification Modification User Modification Calculate Calculate y y Component Component Subdivisions Table Subdivision Component Subdivision Actual Fault s Figure 3 7 Continued 35 given circuit by assigning a simulated faulty value Concatenating this code the code for u and y and the code for any subdivision as an input file of the SPICE program the output file stores the 2 2 values of b and b The test results are then obtained by comparing these two values Following the successful test program verification the test pro gram is
25. validated as shown in Figure 3 8 by measurement of the actual UUT On line Component Test Stage To implement the actual test on a UUT as illustrated in Figure 3 9 the user inputs the maximum number of simultaneous failures allowed The host computer loads the test program and sends instructions to command the HP 9825A controller conducting the test measurement A data file is created to store the test data which is transferred from controller A SPICE code for these test data is generated to replace the code for the given circuit when the SPICE program is run for the test results Data File for Test Program Test with nonfaulty component Data File for Test Data Component Component Subdivisions Subdivision Table Next Test Type ese o Data Base U UT pl A see Test Result Test Data y Figure 3 8 Program Validation Nonlinear Case 36 Data File for Z and u Test Program Test with single catastrophic Loop for Component 1 i to n OPEN CKT SHORT CKT Modification Modification Test Data 1 b e Component Component Subdivisions Subdivision Continued Figure 3 8 Test with single out of tolerance failure component failure component From User 37 Loop for Component i i to n Out of Tolerance Modification Component Subdivision Ps Test Result Actual Fault s
26. which affect the choice of test systems and a dis cussion on the planning studies which should precede any decision to 16 adopt ATE Another book written by Healy concentrates on the automatic testing of the digital integrated circuits Several articles published in IEEE Sprectrum also survey the ATE systems 2 3924237 A test is a process which is not only performed to obtain informa tion about the performance of a component or device it is also allowed to detect locate or identify faults The electronic component or device which is to be tested is called a unit under test UUT Fault detection is a procedure for evidencing the presence of faults in a system which is performed either during quality control or during maintenance Fault Location determines the faulty element after de tection of a fault Fault Diagnosis or identification determines the causes of a fault There are essentially two purposes for testing First to determine whether or not the UUT is bad functional testing and then to find out which element is faulty and needs to be repaired fault isolation 24 Testing may be performed manually or automatically Manual testing is 7 usually performed by connecting individual pieces of test equipment in cluding measurement devices special purpose signal generators power supplies decade boxes and a collection of clip leads The technician must plug in set up and connect all of this equipment to the UUT t
27. zero valued voltage source in series Remark In SPICE a zero valued voltage source is used to measure the current End if Connecting the group 1 component i in series End of Loop Step 3 For equations 4 10 and 2 26 DO i to M 2 If a is a voltage measurement THEN Connecting the controlled sources which have nonzero elements in Kjj and K 2 in series 50 ELSE Connecting the controlled sources which have nonzero elements in Kj and K12 in parallel Connecting a zero valued voltage source in series End if Connecting the group 2 component i in the series End of Loop Step 4 For equation 4 11 DO i TO M 2 IF b is a voltage measurement THEN Connecting the controlled sources which have nonzero elements in Ky and K12 in the series Connecting a resistor with resistance 1 ELSE Connecting the controlled sources which have nonzero elements in Kj1 and Ki in parallel Connecting a zero valued voltage source in series End If End of Loop Test Results In the linear case only matrix vector multiplica tions equations 2 17 through 2 19 are required to evaluate b and pe while the SPICE program is executed for the nonlinear case Use of this computed data to determine test outcome either good or bad for each group 2 component may be obtained by compar 2 If b is equal to be then we say that the test outcome ing b and b for the group 2 component i is good otherwise the c
28. INT TRAN PLOT TRAN OUTPUT V3 3 O PRINT TRAN PLOT TRAN OUTPUT V4 4 O PRINT TRAN PLOT TRAN MODEL QSTD NPN IS 1E 16 BF 50 BR 0 1 RB 50 RC 10 TF 0 12NS TR 5NS CJE 0 4PF PE 0 8 ME 0 4 CJC 0 5PF PC 0 8 MC 0 333 CCS 1PF VA 50 END OSC CKT 1KHZ OSCILLATOR VCC 2 0 5 6 0121801 Q2 365 Q1 Q3 2 10 12 Ql Q4 11 3 7 QI Q5 10 11 13 81 Q6 2 10 9 Q1 Q7 38 4 Q1 Ri 2 3 12K R2 4 5 300 R3 4 0 1 5K R4 10 1 98 603K R5 2 11 7 5K R6 7 0 1K R7 12 6 5K R8 6 0 10K R9 2 10 1 5K R10 13 0 240 R11 9 0 150 MODEL Q1 NPN BF 60 BR 0 205 IS 1 21E 15 END Figure 5 4 SPICE Codes for ASTABLE and OSC CKTs 98 mm M M M e Ls A 8 IN 6l 8l ZL 91 SL bl EL ZL Ll 01 e 35 e49 031 j0 3n0 1YOHS A wame neee yeee 6 B 9 9 M v E Zz JOFETGIATI LNW 9Lqe7sy a 7Y 7e ueJs8 oi te ern pre A m te 2 LYOHS MAE E N3d0 MEN N E IOMA iddns Jamog e S LNOUL Jeau uoy SILNSIY 3591 E G PLIPL CHAPTER 6 CONCLUSTONS An analog Automatic Test Program Generator AATPG for both linear and nonlinear circuits based on the self test algorithm has been pre sented The AATPG code was divided into off line and on line components In the former the test engineer inputs the system specifications to generate the test program and data base The test program was also verified and validated before the
29. Ko litm 3 0 THEN Bo i j 0 ELESE Bota End of Loop j End of Loop i define B By 0 Bo DO i TOm DO j 1 TO n m IF By i j 1 OR B2 1 3 1 THEN B i j 1 ELSE B i53 0 End of Loop j and i Step 3 Generate a matrix C for coupling table Let C B A where is the Boolean multiplication and then matrix C is the desired coupling table Interestingly our heuristic can be carried a step further than indicated above since under our heuristic a bad group 1 component would normally yield erroneous test results An exception would how ever occur if some of the group I components are totally decoupled from some of the group 2 components Consider the coupling table and the simulation results are shown in the following table Table 4 1 Coupling Table with the Test Results UMS NIN 4 3 5 57 E aA The test results show that 2 and 6 are good in the test Our heuri stic implies that the components 5 77 8 9 and 10 which are coupled by components 2 and 76 are also good There are no informa tion from 1 and 3 Therefore all components are good except 1 3 60 and 4 are unknown Moreover in the single failure case the test results show that the components 1 and 3 are also good and a con clusion will be immediately obtained in this simulation result the component 44 is faulty ALGORITHM VII Heuristic Algorithm Step 1 Input t the maximum number of simultaneous failures FLAG j
30. Modified SPICE code for the given circuit or 2 SPICE code for test data Retrieve the data base assume i th subdivision is used Concatenating the file SPICE DT SOURCE DT and TEOO DT where i as an input file of SPICE program The output values b2 and b are stored in a data file 52 Once the test outcomes have been obtained the algorithm reduces to a combinatorial self testing problem in which one locates the actual failure In other words one may complete the test algorithm by implementing an appropriate decision algorithm Decision Algorithms Three decision algorithms with their software implementation are presented 1 Exact Algorithm 2 Heuristic Algorithm and 3 Boolean Expression Algorithm The first algorithm is employed to locate single failures while the re maining two algorithms are used to identify multiple failures Exact Algorithm In the single failure case we assume that at most one component is faulty As discussed in 42 we summarize all possible test results obtained from a given step of the algorithm to gether with the conclusions as follows Test Result Conclusions 123 ar a m 000 0 all group 2 components are good 100 0 all group 2 except are good Te Og 0 all group 2 components are good Vhs a T D Hb du all group 2 components are good In the first case we conclude that all group 2 components are good If a group two component were actually faulty then our test
31. ON THE IMPLEMENTATION OF AN ANALOG ATPG by CHIN LONG WEY B S M S A DISSERTATION IN ELECTRICAL ENGINEERING Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY A cop E ACKNOWLEDGEMENTS I would like to express my sincere thanks to Paul Whitfield Horn Professor Richard E Saeks for his expert guidance of this dissertation Professors Kwong Shu Chao John F Walkup Erich E Kunhardt and Kazuo Nakajima for serving on my committee Thanks also to Mrs Pansy Burtis for her fine work in typing this dissertation and Mr Henry Ford and Dr Ashok Iyer for their suggestions It is a pleasure acknowledging their help Finally a special thanks to my wife Lih Er my parents brothers sisters and friends for their encouragement and support during my entire education TABLE OF CONTENTS O TA ii LIST OF TABLES uos cue crepat ET EEE EU sa UR iv LIS FOF FIGURES ere node io vee ueeee ns AN v lx SPACPOUUCT ION os unge x VERE ECRVPHEDOEE da 1 The Selt T sting AGO COM ss pas 4 Overview of Automatic Testing Programming 6 Organizacion eee o uS PUR Ra EE 9 Pl The Simulation Modelo ase 11 Lincar Case a AS 11 Nonlinear Case 0 RO A III Software Development c lace Ra A 17 Linear Casen dia ds Pa teri eroe Pese sae 18 Nonlinear Case ET EEE ETEO E 26 IVe Algoritmi AAA DA 39 Supporting Algorithms c
32. OR REC QA RE ER ee 7 RE 77 Soo oo Yo Ho Ho 1 0E 05 40000 10000 1800 2000 500 1 0E 041 0E 05 1000 Ho p too 4 Eo ooo 4 Y Y i i i 0 i i i Co perfec ee t A ES is AAA EAS i i i i 240 i Ho R R tooo i i i OE 05 i i i e e to tooo Ho E R Ho Ho 0 2 i l oth 2 3 i 4 3 1 5 Ho E Ho Hoi 1 A i 0 3 0 0 5 0 i Hess a eR SA ee eee a A Sa o Moe eem H 4 i i Fasnia he too doo ooo doo EN 4 tooo R doo Ho Hoooo do oo Ho 17 2 3 2 componert abbr notetion component velue noe veS15t0T R Ru resistance C7 co pecitor C Cri cepacitence 4 inductoT L Ln inguctence on ernn O On voltage cain input output trensictor G Cn hirbi ce p3 C B E Hie He Hte Hoe tranctormer X zn transformation primary 93 CS ratio secondary 6 A A A A A a eee Se A A ma end SS A ADIDAS SO AU e hf es Table 5 1 Continued of Node E er of components 73 AS a ee a too db Sms to ooo T T CF Rp i i poo tooo do boo Poo yoo ooo tooo iji R3
33. PICE Code for the External Input of Pseudo Circuit The external input of pseudo circuit UP col u y col VIN IDI IL VRL That is Uy VIN V 4 0 the voltage at node 5 y IDI I VK21 the current flows through VK21 Yoo TEE S I VK22 the current flows through VK22 y VRL V 3 0 the voltage at node 3 Therefore the SPICE code is generated and stored in a file named SOURCE DT 88 EE701 700 0 4 0 1 RR701 700 0 1 FF702 0 702 VK21 1 VK702 702 0 0 FF703 0 703 VK22 1 VK703 703 0 0 EE704 704 0 3 0 1 RR704 704 0 1 The first two cards describe the voltage measurement for VIN A voltage controlled voltage source EE701 which is controlled by node 5 VIN and a resistor with resistance 1 are connected in series The voltage at node 701 is therefore equal VIN EE701 RR701 1 For the current measurement cards 3 and 4 a current controlled current source FF702 which is controlled by 1 VK21 1D1 and zero valued voltage source is connected in the series so that the current flowing through the zero valued source is the same as IDI FF702 VK702 0 702 Component Subdivisions table 12 possible component subdivisions are generated as follows 89 Subdivision Component Number Number a a XI OS m nO 00 CO Y dh O1 4 Y MN eS Se 4 2 0 CO P9 r9 r9 NN f 0101 C0 CO 4 PM P9 Y DO 1 C Y DNDN OID Qe Pseudo Circuit and Data Base If the firs
34. SPICE Codes Test Program Generation Nonlinear Case 31 32 MOSFET is based on the Frohman Grove model however channel length modulation subthreshold condition and some short channel effects are included In the source description any independent source in SPICE can be assigned a time dependent value for transient analysis and the source value can be a constant or independent source function Pulse Exponential Sinusoidal or Piecewise Linear Therefore the user may input the source value by a constant or any above function Time Steps for Transient Analysis The transient analysis portion of SPICE computes the transient output variables as a function of time over a user specified time interval Accessible Test Terminals When the accessible test terminals are specified the L2 matrix a table consisting of all possible component subdivisions and a SPICE code for the test inputs u and test data y are generated As discussed in the linear case the connection matrix K of a pseudo circuit is created by computing the equations 2 12 through 2 15 For each subdivision based on this generated K matrix and equations 2 23 through 2 26 a SPICE code is generated and stored in a data base which will be used by the on line component At the end of the program generation process the following data files are generated SPICE code for the given circuit SPICE code for u and y and data base SPICE codes for the equations 2 23
35. W and Sakla A A Calculation of parameter values from node voltage measurements IEEE Trans Circuits Syst Vol CAS 26 pp 466 474 July 1979 Wey C L AATPG Linear Circuit Version User Manual Texas Tech University 1982 Wey C L AATPG lonlinear Circuit Version User Manual Texas Tech University 1903 Wu C c Ph D Dissertation Texas Tech Univ 1981 Wu C c Nakajima K Wey C L and Saeks R Analog Fault Diagnosis with Failure Bounds IEEE Trans Circuits Syst Vol CAS 29 May 1982 pp 277 284 APPENDIX Let B bea m by n matrix n gt m Definition The global column rank of B is said to be k if every combination of k columns of B is linearly independent and some combination of k 1 columns of B is linearly dependent Definition 30 A system is t diagnosable if given the results of all tests one can identify the faulty units provided that the number of faulty units does not exceed t In the single failure case we assume that at most one component is faulty All possible test results obtained from a given step of an algorithm are summarized and together the conclusions are summarized as follows Test Result Conclusions PEE wae hy l 000 0 all group 2 components are good 100 0 all group 2 except 1 are good 110 0 all group 2 components are good 1 l all group 2 components are good Consistent with the above arguments at each step of test algorithm either all or all
36. actual on line test was performed The test is run in a fully automatic mode Basically the algorithm is unique in its ability to test linear and nonlinear subsystems or models of arbitrary size Actually as shown in Chapter 1 an IC chip or a subsystem can be considered as an individual component in the test process Thus one can use the algo rithm to test modern electronic circuits Although the on line computational requirements for the test algo rithm do not compare with a simulation before test algorithm they can be kept within reasonable bounds One can limit the on line computation for instance by restricting the number of algorithm steps Therefore the proposed AATPG code permits one to trade off between on line compu tational requirements and test points A formula was derived in Chapter 4 to define the maximum number of algorithm steps required This number depends on the structure of the matrix Lo which relates to the choice of the test points As the number of test points increase the steps in the algorithm decreases We believe the testability 99 100 discussed in the Appendix can be used to pick upa set of good test points An alternate way to reduce the computational requirements using parallel processing was presented in Chapter 4 The minimum number of algorithm steps required shows that these subdivisions are chosen inde pendentlys therefore those steps can be carried out simultaneously To identify the fau
37. al systems A graph theoretic approach in Rational Fault Analysis ed R Saeks and S R Liberty Marcel Dekker New York pp 1 12 1977 Hakimi S L and Nakajima K On a theory of t diagnosable analog systems IEEE Trans Circuits and Syst to appear Healy J T Automatic Testing and Evaluation of Digital Integrated Circuits Prentice Hall Reston Virginia 1981 Hayes J P Modeling faults in digital circuits in Rational Fault Analysis ed R Saeks and S R Liberty Marcel Dekker New York pp 78 95 1977 Knowles R Automatic Testing Systems and Applications McGraw Hill UK 1976 Lee S C Digital Circuits and Logic Design Prentice Hall Engle wood Cliffs N J 1976 Liguori F Editor Automatic Test Equipment Hardware Software and Management IEEE Press New York 1974 Lin C S Huang Z F and Liu R W Fault Diagnosis of Linear Analog Networks A Theory and its Application Proc IEEE Int Symp Circuits and Syst pp 1090 1093 May 1983 Liu R W unpublished notes Univ of Notre Dame 1980 Mayeda W Graph Theory Wiley New York 1972 McAleer H T A Look at Automatic Testing in Automatic Test Equipment Hardware Software and Management ed F Liguori IEEE Press New York N Y 1974 Nagel L W SPICE2 A computer program to simulate semiconductor circuits Univ of California Berkeley 1975 NAP2 A Nonlinear Analysis Program for Electric Circuits Vers
38. am in which the test data y is cal culated by the following equation In the first test since no faulty component is assumed all the group 1 components are good so that the test results should be ravine If one of the test one is found to be bad in an arbitrary subdivision which contradicts our nonfaulty component assumption the process will be terminated with an error message An error check routine is then loaded to check for correctness of the Circuit and Test Point Descriptions If no error is detected the program generation process is repeated with new test points If no faulty component is detected in all possible sub divisions the catastrophic failure test will be executed In this test components taken one at a time are modeled as open circuits Using the calculated y of equation 3 1 the test results are obtained and the actual faulty component will be located by the exact single fault algo rithm The details of the decision algorithms will be discussed later 26 After the test with the open circuits for each component is executed successfully a similar test where the components are short circuited is performed If either one of the above tests fails the error check routine will be loaded If all the above tests are processed successfully similar tests for out of tolerance failures are executed Once all tests are completed successfully the test program is assumed correct Following the successful test
39. apacitors transistors op amps and transformers give a unique name to each component where the first letter identifies the component type define the value of the appropriate elements by the input of a numerical constant and indicate the current flow direction by specifying the nodes Nodes must be nonnegative integers but need not be numbered sequentially The ground node must be numbered zero In the source description the independent sources are assumed to be lo cated in series parallel with a component therefore the branch which contains the source will be specified as well as the orientation of this branch Input Frequency The component equations for our linear circuits are modeled in the frequency domain Since a single test vector is re quired single frequency testing can be employed With this single fre quency the component transfer matrix Z is generated by computing the impedance or tias for each one port component such as a resistor capacitor or inductor The square matrix Z contains all zeros every where except the diagonal blocks where the block size depends on the number of ports of each component For the two port components such as transistor the hybrid pi parameters are used to characterize the com ponent and the dimension f the diagonal block is two rows by two columns with the h parameters or the transformed parameters depending 22 upon the entries selected in the vector a Together with the data g
40. controlled courses to simulate the test data and stored in a data file named SI0001 DT Assume the 5th subdivision is chosen then the SPICE program is executed with an input file which concatenates the data files as follows 94 SI0001 DT SOURCE DT TEOOO5 DT and b are stored in the output file Similar to the The values b linear case with the comparison of these two values and the aid of the decision algorithm one will be able to identify the faulty component s The test tesults of the program verification for the Power Supply Circuit are summarized in Table 5 3 In addition to the Power Supplv example a couple more examples are 2 presented They are the Astable Multivibrator in Figure 5 2 and the 25 25 Oscillator in Figure 5 3 The SPICE codes for both circuits are shown in Figure 5 4 and their test results are also summarized in Table 5 3 Figure 5 2 RBZ 30K Astable Multivibrator RC2 IK r Q2 95 403e1112s50 G e4nb14 y3 o09 8b yy OS LO b obese Al 16 uM gt QU Soius 9M OOE Y a O pA T ve j E 95 E Ae AS En RS 8 IO y O Ta DIA 97 ASTABLE CKT A SIMPLE ASTABLE MULTIVIBRATOR TRAN 0 1US 10US VIN 5 O PULSE O 5 0 1US IUS 100US 100US VCC 6 0 5 0 RCl 6 1 1K RC2 6 2 1K RB 6 3 30K RB2 5 4 30K Cl 1 4 150PF C2 2 3 150PF Q1 1 3 0 QSTD Q2 2 4 0 QSTD OUTPUT V1 1 O PRINT TRAN PLOT TRAN QUTPUT V2 2 O PR
41. course this approach is a kind of brute force search which requires one to simulate all possible responses to the various combinations of hypothesized faults However all these simulations need only be ieee once at the factory of a maintenance depot The cost of simulation is therefore relatively cheap Clearly this approach is ideally suited for the maintenance environment With the aid of some sophisticated software engineering this apparently brute force approach to the fault diagnosis problem has slowly evolved into a workable concept 3 Unfortunately the above described success in the digital world has not been paralleled by progress in the analog world The difficulty arises from a number of characteristics of the analog problem which are ot encountered in digital circuits namely 1 Analog systems have a continuum of possible failures These failures may range from short circuit to open circuit 2 A good component may be in tolerance but not nominal 3 Complex feedback structures are encountered 4 Simulation is slow and costly because analog systems are frequently nonlinear 5 Post fault component characteristics may not be known and 6 A fault in one component may induce an apparent fault in another Items 5 and 6 imply that the kind of brute force fault simulation algorithm associated with the digital problem will not be applicable to the analog or hybrid case A number of academic researchers have prop
42. current measurements which are selected from the entries of a and the remaining are voltage measurements which are input by the users specifications Therefore the first two rows of L5 matrix duplicate the first two rows of L matrix In the third row since 78 V45 VCl VBEQ VRL all elements inthis row are O but the positions 1 5 and 10 are 1 Similarly the fourth row contains all 0 except for the 2nd and 4th columns which are 1 and 1 respectively That is SE Loy Loo O 0 1 0 0 0 1 TS 4 0 Of EVE u0x 0s 207 Os El 0 Os 1 0 9 0 0 sr 20 D oe MIO OO 0 0 0 Y Ost 0 0 0 0 0 0 0 0 0 The component connection model for this linear circuit can be expressed as follows bl NE rl crm where yl IC L L y2 IRI L H y y vas 21 22 y4 V13 The Component Transfer Matrix Z When the single frequency is input the matrix Z is generated and stored in a data file named ZU DT The component transfer matrix in this example is formed as follows Zu 0 c9 0 0 0 Zp 0 0 0 00 0 0 0 0 0 0 Ye 0 CO 0 OU 2 A 0 G zet 2 GO p o 0 p xe d o T e Xup Xue o E 9 o d D e Bat t 0 0 0 0 0 0 0 0 Yu 0 0 0 0 0 0 0 O08 80 OD 0 Veo oO p G o d r w w o ygt d 0 0 0 0 0 0 0 0 Zo 0 d X 00 d 10 X R3 79 For the on port components resistors capacitors and inductors the corresponding element in the matrix Z is nothing but the impedance or admittance d
43. d Bok A sau at least one of group 1 components are faulty pe a ux A We conclude that at each step no more than two faulty components are found in the group 2 Similar to the arguments and proofs in the single failure case we conclude the following lemma and theorems for multiple failure case Lemma 2 A system is 2 diagnosable if and only if every triplet of elements appears in at least one group 2 Theorem 3 For the case of al one port components The system is 2 diagnosable if and only if the global column rank of the matrix Loy is at least 3 Theorem 4 General case The system is 2 diagnosable if and only if the L rank of the matrix L is at least 3 2 Similarly consider an arbitrary integer k i e k failure case all the possible results with the conclusions are shown as follows Test Results 123 k 1 k k 000 000 100 000 1 ee o0 Itte fe EE A L 1 111 We conclude are found in the Lemma 3 A system is elements appears Theorem 5 For oos 1 108 Conclusions all group 2 components are good all group 2 except 1 are good all group 2 except 1 through k 1 are good all group 2 except 1 through k are good at least one of group 1 components are faulty that at each step no more than k faulty components group 2 k diagnosable if and only if every k41 tuple of in at least one group 2 the case of all one port components
44. d as foll ws FFI01 0 101 VK702 1 VK101 102 00 As shown in the following circuit if the current flow through the diode is known then the voltage across the diode can be computed FF101 XK101 0 D1 Therefore the voltage at node 102 is VDI For the voltage case consider the second row of the matrix in equation 5 1 VC2 VLI Ya The voltage across C2 equals to the voltage across inductor Ll and the external input Y4 The voltage source EE101 is controlled by the sum of the voltages at nodes 106 and 704 EE10 103 O POLY 2 106 0 704001 1 which is equivalent to v 103 0 V 106 0 V 704 0 where POLY 2 is the number of controlled nodes the last three numbers are the coefficients of the polynomial s 1 To calculate VC2 in the entry of b Two cards are specified 92 VK102 103 104 0 CC101 104 0 M the equivalent circuit is EE101 VK102 0 CC101 1mF 103 104 When the voltage is calculated the voltage at node 103 is known therefore the current flows through the capacitor IC is represented by I VK102 2 and b consider the first element of a To compute b IRI IC2 Yo The equivalent SPICE code is EE103 0 109 POLY 2 VK102 VK703 0 1 1 VK105 109 110 0 gives the value of IRI I VK105 and RR102 110 0 5 Using this value of IR and the component values Rl the voltage VR SL which is an element of b is computed The first element of b is to measure the v
45. e Mee Poe enc re Hoe 23 Hea Hoe eee ig For the combination 4 zi am ie eum re sp te PA Hoe If one of the above combinations is computable the combination is then selected as elements of the vectors a and b 81 Component Subdivisions Table The component subdivisions table is generated by the assumption that E Ie exists Therefore 34 sub divisions are generated as follows Subdivision Component Subdivision Number Number Number 1 1 2 3 9 18 2 8 10 d 2 1 2 3 11 19 3 4 9 10 3 1 2 7 9 20 3 4 10 11 4 2 7 M 21 7 9 10 5 2 8 9 22 4 7 10 11 6 1 2 8 11 23 4 8 9 10 7 1 3 4 989 24 4 8 10 11 8 Bo oe A 25 2 3 5 6 9 1 4 7 9 26 2 5 6 7 10 1 4 7 11 27 2 5 6 8 11 4 8 9 28 2 5 6 9 12 l 4 8 1I 29 2 5 6 11 13 C 3 9 19 30 3 4 5 6 14 2 3 10 11 z x31 4 5 6 7 15 2 x 9 YO 32 4 5 6 8 16 2 7 10 11 33 4 5 6 9 C17 2 8 9 10 34 4 5 6 11 where the component pair 5 and 6 is a two port component Pseudo Circuit and Data Base To generate the data base assume the first component division is chosen i e the group components are 4 5 6 7 28 10 and 11 and the components 1 2 3 and 9 are contained in the group 2 By equations 2 12 2 15 the K matrix is computed as follows The connection of the pseudo circuit can be verified by the test that they satisfy the Kirchoff s laws For the data base the matrix M is de
46. e pas qe nnn 39 Decision A gor VEDIIUS 4o hue aco da 52 M SEX GMD NCS naar eee S ROBORE Ra eios das 71 Cincar C256 e chosen vuU RRODESNERN E ME P MEISTE FERA 71 Nonlinear Laser aces pi acp E Ud 83 Vis CONCUSSIONS wind a e yas ee sa eR qa aree porem eda 99 REFERENCES a deett abut ide SAS 101 APPENDI ck a ada es eae leben wees RE MESS 104 iii Table 4 1 Table dos Table 5 2 Table 5 3 LIST OF TABLES Coupling Table with the Test Result 59 Data Sheet Linear Circuit esee 72 Data Sheet Nonlinear Circult o o ooo 84 Test Results Nonlinear circuits Me Le ere 98 dv Figure a Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure LIST OF FIGURES Simplified Block Diagram of Typical ATE 8 Design and Test of a Unit Under Test UUT 18 Test Program Generation Linear Case 20 Program Verification Linear Case 23 Program Validation Linear Case 27 On Line Component Linear Case 29 Test Program Generation Nonlinear Case 31 Program Verification Nonlinear Case 33 Program Validation Nonlinear Case 36 On Line Component Nonlinear Case 38 Controlled SOURCES 22223498 bee EAR EX OR X YR XS x 47 Controlled Sources With Component 48 Power Supply Circuit S wes daa 86 Astable MUTE Vibrators cuse4 ea as 95
47. e possibly faulty Similarly for any multiple failure case say t failures the impossible fault patterns with more than t faulty components will be eliminated ALGORITHM X Regular Boolean Algorithm Step 1 Retrieve the component subdivisions table and input t the maximum number of simultaneous failures Step 2 Choose a subdivision Step 3 Call subroutines to derive the test results and the tabulated expression Step 4 Search the pattern which contains more than t s and delete the impossible patterns step 5 If the subdivision is the first one go to step 2 otherwise do the next step Step 6 Call a subroutine to compute the product of this expression and the previous one Step 7 Search for the impossible patterns and delete them Step 8 Repeat the above steps until the actual faulty component is determined Since the Regular Boolean algorithm often requires a great number of steps to accelerate the speed of convergence two additional algo rithms are presented Boolean Exact Algorithm and Boolean Heuristic Algorithm Boolean Exact Algorithm This algorithm is developed by applying the concept of the Exact algorithm into the Regular Boolean algorithm Conceptually recall from the discussion of the Exact algorithm the test result obtained from a given step of the algorithm will indicate all of the good components in group 2 and a set of all possible fault patterns will be generated by this test result by
48. enerated in the above description the first part of the connection is generated as shown in equation 2 2 Accessible Test Terminals The accessible Test Terminals are used to generate the second part of the connection matrix In our test package the user is required to input manually the test point locations where the test points may be current measurements through components or voltage measurements across any two nodes However the test points may not be an entry of the vector a With the assumption that the matrix Eo exists a component subdivisions table is gen erated where the elements in each subdivision are the group 2 com ponents As discussed in the previous section given a subdivision a pseudo circuit with the connection matrix K is created by computing equations 2 12 through 2 15 and the data base M matrix is derived by using equation 2 16 At the end of the test program generation process the following data files are created the connection matrix L the component transfer matrix Z and the external input vector u the component subdivisions table the data base iet ds and the test program Program Verification The generated test program is tested in software as shown in Figure 3 3 to verify its ability to detect and locate faults To verify the test program three tests are performed on each circuit namely 23 Test Program Test with nonfaulty component Component Component Subdivisions Subdiv
49. epending on whether a current or voltage appears in the vector a Consider the first component Cl where the current measure ment is in the vector a and voltage measurement in b therefore the first diagonal block is the impedance of the onon Cl Similarly the impedance admittance of the remaining one port components will be located in the corresponding diagonal block For the two port com ponents such as transistors a two by two block is used to describe this component the values are defined by the hybrid pi parameters or appropriate transformed parameters depending upon the elements of the transistor model employed Recall that two pairs of transistor nodes are used to describe the incidence matrix To define them as component inputs outputs there are four possible combinations which appear in the vectors a and b a b a b 1 Vie Ip 2 Vee b lc Vee Vee Ic 3 1 be 4 lo Vbe Ic Vee Ves Ic When one of the above combinations is selected the following calculation will be performed Let the matrix Lai be a 2x2 block of the component transfer matrix with the respect to the transistor where Lai is written as 80 For the combination 1 2 7 Hoe Hio Hoe Hre Hee 2 da Hre Hee Hoe 7 Pre Hee 23 Hey Hie Hoe 7 Hre Hee 24 Hija Hi le Dm i Hee For the combination 2 Zi 1 0 Hie A Hre Hie eq fe Hie 247 Hoe 7 Hee Hre Pie For the combination 334 24 Pig 7 Hp
50. ex ez abcdexyz The number of possible faulty patterns is really reduced in this re sultant expression there were 249 faulty patterns for each and now it becomes 241 patterns Each test step generates a temendous number of possible fault patterns This is almost useless unless we can combine the fault patterns from the various test steps and eliminate patterns which do not appear in each step and or pattern The interesting problems are how to implement this symbolic Boolean expression to a software program And how to accelerate the speed of convergence A tabulated expression may be readily implemented in software One can tabulate all possible fault patterns corresponding to the test re sults in 4 13 as follows where denotes the don t care terms 63 a b c d e x y z 1 6 6 4 9 1 6 6090 6 19 9 4 94 4 6 9 l 9 6 9 4 gt 6 9 1 9 0000001 0 Recall for the expression of equation 4 13 the first term a means the component a is bad and the remaining components are don t care Therefore as a tabulated expression the bad component a is denoted by 1 and the remaining components are denoted by 4 The following four terms have similar expressions as above For the last term in equation 4 13 the group 1 components are all good i e the com ponents a b c d and e are good denoted by 0 and the test results for x y and z will be copied under them ALGORITHM VIII Tabulated E
51. gram and the data base In the test package the greatest part of the re quired computation is carried out by the off line component with the pseudo internal test data being obtained from the test measurements via a simple on line matrix vector multiplication of equations 2 17 and 2 18 To the contrary in the nonlinear code SPICE is used to evaluate the pseudo internal test data via the on line simulation of an appropriate pseudo circuit In our implementation to use the actual measured test data with these AATPGs a HP 9825A is used to control special purpose ATE 17 18 LAN 2531 Japup tun e 40 353 pue ubisag LE aun Ld 1ueuoduo A3 n 3 weuBboud 3591 uot4eptLeA I 4 3591 JNIT1 NO weuBboud SJULOg 959 BALON UOL euauag JO JQuawautnbay uieuboug UOLZRILJ LU weuhoud Sa t329fqg 3531 weuBboug UOLZRLNWLS weubetg 31n2419 3NI 1 340 19 Automatic Test Equipment which generates test signals and stores the measured test results After some necessary calculations the data is transferred to the host VAX 11 780 where the on line component of the ATPG takes over Both the off line and on line components have user oriented inter faces to simplify the process of generating a new test program The AATPG has been implemented on a VAX 11 780 in FORTRAN 77 and DCL Dec Command Language 3 40 In the linear code the user specifies the circuit in terms of certain
52. gt Prentice Hall Englewood Cliffs N J 1977 p 290 Breuer M A Editor Design Automation of Digital Systems Vol 1 Theory and Techniques Prentice Hall Englewood Cliffs N J 1972 Chang H Y Manning E G and Metze G Fault Diagnosis of Digital Systems Wiley New York N Y 1970 DeCarlo R A and Saeks R Interconnected Dynamical Systems Marcel Dekker New York 1981 Duhamal P and Rault J C Automatic test generation techniques for analog circuits and systems a review IEEE Trans on Circuits Syst Vol CAS 26 pp 411 440 July 1979 Eleccion M Automatic Test Equipment Hardware and Software TEEE Spectrum June 1976 pp 60 64 El Turkey F M and Vlach J Calculation of element values from node voltage measurements 1980 Int Symp Circuits Syst Proc pp 170 172 Friedman A D and Menon P R Fault Detection in Digital Circuits Prentice Hall Englewood Cliffs N J 1970 Greenbaum J R Computer aided fault analysis today tomorrow or never in Rational Fault Analysis ed R Saeks and S R Liberty Marcel Dekker New York pp 96 111 1977 Greenspan A M Automatic Test Systems Dedicated or Integrated in Automatic Test Equipment Hardware Software and Management ed F Liguori IEEE Press New York N Y 1974 101 15 16 18 19 20s 2l 22 ese 24 EF 26 21 28 102 Hakimi L S Fault analysis in digit
53. h are known to be good will be excluded from R Therefore the set R is getting smaller Repeating the above process until no such subdivision can be chosen the algorithm is then terminated Here the number of times of the above processes plus t the minimum steps needed in 55 equation 4 12 is the maximum steps needed to locate the faulty com ponent and the components remaining in the set R is the ambiguity set ALGORITHM V Exact Algorithm for single failure case Step 1 Off line job Select the minimum subcollection of the subdivisions which covers all components B B4 B5 B J Step 2 On line Simulate each subdivision Dis hue ig Gye sts Step 3 Let P P1 P2 PgJ c B where P are the subdivisions with pattern all 0 but one 1 Step 4 Let R R Ro R R eP are the components with test result nga 2 E Step 5 IF s 1 THen STOP the component r is faulty Step 6 More than one subdivisions with the above pattern Find a subdivision that contains more than one component in R Step 7 IF no such subdivision THEN GOTO Step 8 ELSE Simulate the test result R R excludes the simulated good components GOTO Step 6 l Step 8 R is the ambiguity set and the components in R are all possible faulty components From the above algorithm the step 1 B B4 B5 B4 J can be derived off line and each B subdivision is simulated independently Therefore they can be computed by multiple p
54. hms for automatic test program genera tion systems has concentrated mainly on digital circuits for which satisfactory solutions have been found Several digital automatic test Z program generation systems have been developed and widely used by both military and industrial communities D LASAR by Digitest ATVG by General Electric TGAS by the U S Navy FAS SDAP by Honeywell LOGOS 12 by Grumman GLASH by Micro SALT by IBM TESTAID III by hewlett Packard etc are some of the well known systems 5 6 11 19 27 33 34 35 have discussed the Several books and articles fault detection and diagnosis in digital circuits Typically in the digital circuit one assumes that all permanent component failures are either stuck at zero CEA or stuck at one a 1 7 Under this assumption one hypothesizes some limit on the number of simultan eous faults and then simulates the responses of UUT Unit Under Test to a family of test vectors for each allowed combination of faults The simulated responses are used to set up a fault dictionary which is stored in some bulk storage media such as disks and magnetic tapes When the test is conducted the actual responses of UUT are compared with the responses in the fault dictionary to locate the failure Of course this approach is a kind of brute force search which requires one to simulate all possible responses to the various combinations of hypothesized faults However all these simulation
55. initiated by Preparata Metze and Chein their study of self testing computer networks if one assumes a bound on the maximum number of components it is possible to determine the actual fault s from an analysis of the test results obtained at the various steps of the algorithm To this end we have derived the complete theory required to locate a single fault together with Boolean algebraic and heuristic methods which is applicable to the multiple fault case 32740242 CHAPTER 3 SOFTWARE DEVELOPMENT l The AATPG code for both linear and nonlinear circuits is subdivided into off line and on line components The former corresponding to the test system design stage is used by test system designer to input nom inal system on to generate a data base which is used by the on line component To implement the actual test the field engineer in vokes the on line component input data describing the UUT the assumed maximum number of simultaneous failures the type of decision algorithm to be employed and the source of the test data The actual test can then be run in a fully automatic mode or interactively As illustrated in Figure 3 1 a circuit description and test objec tives are given to the off line component to generate the test program Necessary changes are indicated if the resultant test does not satisfy all of the requirements If the design is satisfactory the off line component will generate the necessary data for the on line test pro
56. ion 2 Technical Univ of Denmark Lyngby Denmark Dec 1976 Peatman J B The Design of Digital Systems McGraw Hill 1972 Plice W A A survey of analog fault diagnosis presented at the Workshop on Analog Fault Diagnosis Univ of Notre Dame Notre Dame IN May 1981 29 30 31 36 335 34 dos 36 2 38 992 40 4 42 103 Plice W A Automatic generation of fault isolation tests for analog circuit boards a survey presented at ATEX East 78 Boston Sept 1978 pp 26 28 Preparata F P Metze G and Chien R T On the connection assignment problem of diagnosible systems IEEE Trans Electronic Computers Vol EC 16 pp 448 454 1967 Saeks R Criteria for analog fault diagnosis in Nonlinear Fault Analysis Texas Tech Univ Lubbock TX pp 19 28 Saeks R Singh S P and Liu R W Fault isolation via com ponents simulation IEEE Trans Circuit Theory Vol CT 19 pp 634 640 Nov 1972 Sellers F F Hsiao M Y and Bearson L W Error Detecting Logic McGraw Hill New York N Y 1968 Special Issue on Fault Tolerant Computing IEEE Trans Computers Vol C 20 Nov 1971 Special Issue on Fault Tolerant Computing IEEE Trans Computers Vol C 22 Mar 1973 TESTAID III Logic Simulator Hewlett Packard Palo Alto California Jan 1977 To K and Tullos R E Automatic Testing Systems IEEE Spectrum September 1974 pp 44 53 Trick T N Mayeda
57. is a px p r matrix It can be easily verified that x xe p therefore the equation 4 1 can be written as 41 Let I col 1 I and V col ViVa be the current and voltage vectors of the circuit respectively where I V and I VL are denoted as the currents voltage in the tree and co tree edges respectively According to the Kirchhoff s current law and Kirchhoff s voltage law we obtain the equations 0 Sp 1 1 D1 and 4 3 RE 0 Bs V D V TS therefore I 0 D Me 4 4 Ve D 0 I To obtain the matrix D an incidence matrix A can be tr nsformed I D into the form E JE using a Gaussian elimination process In order to derive the L matrix equations 2 2 and 2 3 we will specify a tree in a linear graph modeling the topology of an electric network Let js col 1 V and b col V I be our composite compon ent input and output vectors Inherently tree edges correspond to com ponents having the impedence models and co tree edges correspond to com ponents with admittance models Usually the choice of a tree depends on the choice of a model for the various components Assuming that there is no intra component coupling between components represented by tree edges and co tree edges the composite component model for the linear circuit becomes 42 4 5 where Ls and Ye are block diagonal matrices the size of the diagonal block depends on the number of ports of the component For one port co
58. ision Table End of Table ED a LE SPICE SPICE Code for the Code SPICE Code for u and y Call SPICE Program Test Data Base Result Compare SPICE Codes Error Component Check Figure 3 3 Program Verification Linear Case 24 Test with single Test out of tolerance Program failure component Test with single catastrophic Loop for failure component Loop for Component i Component 1 i t n is ton Out of From Tolerance User Modification OPEN CKT SHORT CKT Modification Modification Modified SPIC Code for the given circuit Modified SPICE Code for the given circuit Component Component Subdivisions W Table Subdivision Component Subdivision dl Test Result Actual Fault s Figure 3 3 Continued 25 1 A test with nonfaulty components 2 Tests with single catastrophic open and short circuits failures and 3 Tests with a single out of tolerance failure The first test verifies the correctness of the test program while the remaining tests are performed to check whether or not the selected test points can actually locate and detect the faults If the test is not satisfactory the design engineer may change the test points and repeat the process of program generation The source of test data for program verification is a simulation progr
59. ith the test data to determine whether or not the remaining components are good In effect the first group of components is testing the second hence the self test algorithm Of course if the testers are actually good then the resultant test results for the remaining components will be reliable On the other hand if any one of the testers is faulty the test data on the remaining components will be unreliable Consequently we repeat the process at the next step of the test algorithm with a different subdivision of components Of course the number of components which may be tested at any one step is dependent on the number of test points available while the number of steps required is determined by the number of components which may be tested at any one step and the bounds on the maximum number of simultaneous failures Therefore this procedure yields a natural set of tradeoffs between the number of test points simultaneous failures and steps required by the algorithm Overview of Automatic Testing Programming The Purpose of this overview is to introduce the Automatic Test Equipment ATE which provides test data to our test program A collec ener papers relating to hardware software and management aspects of automatic test equipment was edited by Liguori Y In Knowles book he introduced the automatic test systems and its applications He gave a review of the elements which comprise automatic test systems a survey of those factors
60. lgorithm can be formulated in terms of any of the standard circuit or system models for the purpose of this exposi tion we will assume a component connection for the circuit or system under test The component connection model naturally divides the system into two sets of equations Component equations characterized by block composite component model for linear case or by decoupled State model for nonlinear case and the Connection equations character ized by coupled linear algebraic equations Equations 2 1 and 2 20 are the component equations of linear and nonlinear systems respective ly while the equations 2 2 and 2 3 are the connection equations The connection matrix L equations 2 2 and 2 3 characterizes the connection of components in the system At each step of the algorithm a pseudo circuit is generated and formulated by the equations 2 9 through 2 15 with a new connection matrix K The data base which is used by the on line component is computed by equation 2 16 matrix M for linear case while a SPICE code based on the equations 2 23 through 2 26 is generated for the nonlinear case Linear Case In the linear case the UUT is represented by a composite component model characterizing its components and or subsystems together with an algebraic connection equation as follows b Za 2 1 11 and i 2 2 2 b Za 2 5 Ku 1 Here Z a and b are the vectors of group 1 transfer functions co
61. lty component s from the test results three decision algorithms were presented The next algorithm subdivision can be chosen automatically or manually for the single failure case by user s choice But the exact algorithm for the multiple failure case is not available However it is noteworthy that the underlying combi natorial decision problem is quite similar to the t diagnosability problem usually associated with self testing computer networks wherein the multiple fault has been resolved 14215330 Another major open question with respect to the performance of the algorithm is robustness i e its sensitivity intolerance deviations from nominal of the good components Finally a big ambiguity set shown in Table 5 3 c is due to the performance of the simulation program Since in our algorithm the test data and the test results are simulated from a pseudo circuit the Simulation may not be handled by the conventional circuit package Therefore either accurate simulation models or new circuit packages are needed REFERENCES Aho A V Hopcroft J E and Ullman J D The Design and Analysis of Computer Algorithm Addison Wesley 1974 pp 199 200 Amin T unpublished notes Bell Laboratories 1980 Aprille T J and Trick T N Steady State Analysis of Nonlinear Circuits with Periodic Inputs Proc IEEE Vol 60 pp 108 114 1972 Boylestad R and Nashelksy L Electricity Electronics and Electromagnetic
62. m most suitable to the users display or print out requirements Organization The purpose of this dissertation is to present an Analog Automatic Test Program Generation AATPG for both linear and nonlinear circuits based on the self testing algorithm In Chapter 2 a Component Connection 10 Model CCM is described This model is used to formulate our test al gorithm for both linear and nonlinear circuits The simulation model is used to test one set of components under the assumption that the remain ing components are good Based on this model the software development of AATPGs for both linear and nonlinear circuits are discussed in Chapter 3 Each code is subdivided into off line and on line components The off line component is used by the test system designer to input nominal system specification to generate the test program and data base which is used by an on line component To verify the software s ability to locate and detect the faulty component s Program Verification is used Similarly the test program is validated by the measurement of the actual UUT The on line component is used in the implementation of the actual test In order to run the actual test ina fully automatic mode several supporting algorithms and decision algorithms are discussed in Chapter 4 Examples for both linear and nonlinear circuits are present ed in Chapter 5 The conclusions follow in Chapter 6 CHAPTER 2 THE SIMULATION MODEL Although our test a
63. mn rank of Los is at least 2 i e any two columns of Loy matrix are linearly independent then every 106 pair of elements can be selected in the same group 2 by Lemma 1 the system is l diagnosable For the multiple port component case Let Los B M M MJ and W of columns in Mi i 1 2 r r where W n il Definition M and M are linearly independent if z M A M A 0 then A where A and A are vectors Definition Generalized Global column rank L rank 0 and A 0 1 205 Let B be subdivided into r partitioned columns M gt as shown above The L rank of B is said to be k if every combination of k parti tioned columns of B is linearly independent Theorem 2 General case The system is a aago ie if and only if the L rank of the matrix Loy is at least 2 Note Since if any one port of the multiple port component is faulty the group is faulty hence we can group the multiple ports as one Therefore the multiple port problem is equivalent to the one port case In the k failure case we assume that at most k components are faulty Consider the case of k 2 the possible test results with the 107 conclusions in each step of the algorithm are summarized as follows e lest Results 123 m 000 0 all group 2 components are good VOD 0 all group 2 components are good except component 1 110 0 all group 2 except 1 and 2 are goo
64. mponent input and output variables and similarly for y a and b To retain notational compatibility with equations 2 4 and 2 5 we re order and partition the connection equations of 2 2 and 2 3 to be conformable with 2 4 and 2 5 as follows dagegen ul da b oed b Ly u 2 6 ac egt pl a a o u 2 7 11 11 12 zcd c p Unlike the commonly encountered circuit analysis problem in which one desires to simulate the output responses y of a given circuit in our application the vector y is obtained by the test engineer measuring the responses at various test points The test responses y are there fore known for the purpose of our application Given equations 2 4 through 2 8 our goal is to compute the group 2 component vari ables al and b To this end we assume that E admits a left inverse which in turn determines the allowable component subdivisions Under this assumption one may then formulate a component connection model for a pseudo circuit composed of the group 1 components with external input vector uP col u y and external vector yP co a b in the form b zl a 2 9 and _y K 13 2 10 2 11 where K is the connection matrix of the pseudo circuit Some algebraic manipulation of equations 2 6 through 2 8 together with the assump tion that ei exists will yield ee ee ee ia Li hoy la 12 21 22 4 2 aL Luc bay bz 7 54 K 21 E Lo gt Lo
65. mponents resistors capacitors and inductors Z is the composite t component impedance matrix for components identified with tree edges and Y is the composite component admittance matrix for components identi fied with co tree edges For two port components such as the transis tors a two by two block is used to describe this component the values are defined by the hybrid pi parameters or appropriately transferred parameters depending upon the elements of the transistor model employed With the choice of a and b the connection matrices follow directly from the equation 4 4 taking the form big S E 2 i D 0 However for the network sources the following assumptions will be made each voltage source is connected inseries with an element which is not a source and each current source is connected in parallel with an element which is not a source Under these assumptions the matrix L n will be derived from the location of sources 12 Suppose a voltage source Es is located in the tree edge i oM Vig TELE where w is defined as follows 43 if the orientation of the source w coincides with that of the edge otherwise From the equations 4 3 4 4 and 4 6 we obtain n f kj E Veg jh Ly Ve k nl N 2 b n kj ki ki a n L11 Vej bt Yu t tt Eg 4 7 jfi Hence the k s entry of the matrix Lio equals to aL Similarly if a current source Je is located in the co tree edge i the l ki k s e
66. nent Test with single catastrophic Loop for failure component Loop for Component 1 i ton Component i i to n Qut of From y Tolerance Modification User Modification SHORT CKT OPEN CKT Modification 7 T T SPICE Code p SPICE Code i for E j for I _Test Data L _ Test Data Component Component Subdivisions Table Subdivision Component Subdivision Figure 3 4 Continued Maximum Number of Simultaneous Failures Data File for Z and u Test program Data File for Test Data y Component Subdivisions Table Component Subdivision pas Test Decision Algorithm Print Display Faulty Component s Figure 3 5 On Line Component Linear Case 29 E 30 2 26 Similar ways to verify and validate the test program in the linear case are also employed here As illustrated in Pure the input requirements in the test program generation are Circuit Description Time Steps for Transient Analysis and Accessible Test Terminals Circuit Description In the SPICE program each component in the circuit is specified by a component card that contains the component name the circuit nodes to which the component is connected and the values of the parameters that determine the electrical characteristics of the component The first letter of the component name specifies the component type Nodes must be no
67. nnegative integers but need not be numbered sequentially The ground node must be numbered zero To des cribe the circuit analysis to SPICE whichis the same as the component description discussed in the linear case the user is required to input the component type any SPICE accepted component type with a unique name define the component value by any number field accepted by SPICE and specify the nodes For the semiconductor components such as diodes BJTs JFETs and MOSFETs user needs to specify only the pertinent model parameter values The model for the BJT is based on the integral charge model of Gummel and Poon however if Gummel Poon parameters are not specified the model reduces to the simpler Ebers Moll model In either case charge storage effects ohmic resistances and a current dependent output conductance may be included The diode mode can be used for either junction diodes or schottky barrier diodes The JFET model is based on the FET model of Shichman and Hodges The model for Circuit Description Test Points Description SPICE Code for u and y Figure 3 6 SPICE Code for the given circui Time Steps for Transient Analysis Display Print L1 Matrix L1 Matrix Display Print L2 Matrix L2 Matrix Component Subdivisions Table Pseudo Circuit Eqns 2 12 2 15 SPICE Code for Eqns 2 23 2 28 Data Base
68. ntry of Lio is also why Suppose a voltage source Es is located in the co tree edge i and Vek jh L3 Veg k ntl n 2 b which implies Ea kj _ ck jh L Vez 7 Es 4 8 therefore the k s entry of Ls equals w Similarly the k s entry of Lio for a current source de located in the tree edge i is also u Since the vector y is the system responses measured at the various test points the matrices Loy and Loo in the equation 2 3 therefore depend on the selection of the test points The test points can be selected to measure the current or voltage of any edge or the voltage across any two nodes In the former case i e the current flow through k th co tree edge or the voltage across the k th tree edge the response y is then an element of vector a Therefore the jth rows of the 44 matrices Loy and Loo are just the k th rows of L3 and L12 respectively In the latter case the responses y will be written in terms of vectors b and y and the coefficients form the jth rows of L and L 11 22 respectively ALGORITHM I L Matrix Step 1 Generate the incidence matrix A Step 2 Obtain matrix D from matrix A by Gaussian elimination process Step 3 Generate L7 matrix from the equation 4 5 Step 4 Let e be the number of voltage sources and j be the number of current sources L12 5 9 0 Step 5 IF e 0 THEN go to step 6 no voltage source DO i 1 TO e IF the voltage source is in the tree edge assume they a
69. o make the tests he feels are pertinent by the help of some sort of manual or set of instructions Automatic testing is a test procedure which is performed with the aid of a computer There are power supplies stimuli measurement de vices and a switching system to allow the equipment to be arranged in desirable configurations The instruction manual is replaced by a pro gram file which instructs the computer to carry out test instructions in the proper sequence judge test results and or perform calculations The test results are either written by a line printer or displayed on a CRT terminal A block diagram of a typical ATE system is shown in Figure 1 1 The switch unit is an equipment which is used to connect the device UUT ATE interface to the test system and to vary the connections of the device terminals Examples are multiplexers relay trees scanner and so forth The stinulus unit isa device which generates stimuli such as power supplies oscillators synthesizes function generators waveform generators and D A converters among others For use in automatic test such sources are often required to be programmable that is all of their functions should be controllable by electric signals instead of manua control The measurement unit is an instrument which quantifies the response of a UUT to stimuli The response of a UUT may be a UUT Test Program Program Input Unit Digital Computer
70. oltage across node 110 V 110 Consider the first element of b VRI VDI VLI Ui 7 3 The equivalent SPICE code is EE105 115 O POLY 4 102 0 106 0 701 070400 1 1 1 RR108 115 0 1 These cards compute the voltage of Rl VR1 V 115 93 To compare these two values a print control card is used PRINT TRAN V 115 V 110 in which the values of b and bf are stored in the output file Each component subdivision creates a pseudo circuit and each pseudo Circuit generates a SPICE code as above which is stored in a data file named TEOO DT where is the subdivision number Test Results When the on line component is conducted either a simulation program or the ATE interface is used to obtain the test data If the simulation program is used user will specify the simulated faulty component it may be open or short circuit or out of tolerance A data file named SIOO0 DT is used to store the SPICE code for the circuit with simulated faulty component where is the faulty component number Suppose that the component 1 Rl is faulty and it is simulated as an open circuit the SPICE code for the first component was R1 5 1 5 and now is changed to be IRI 5 3 0 The SPICE code is stored in S10001 DT If the test data is obtained from the measurement of the actual UUT a data file is created in the host computer to collect the test data which transfers from the controller A SPICE code is then generated by using the voltage
71. omponent is EN 2 bad In a more realistic environment instead of requiring that b TE m and b be equal one may say that a component is good if b is suffi ciently close to b in some reasonable sense In this way one may com i 10 M r b and b are pensate for numerical errors and tolerance oreover b i 91 not necessarily scalars they may be vectors depending upon the com ponent type with which one deals For instance a two port component may require a two tuple vector to represent its input output character istics ALGORITHM IV Test Results Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step l Step 2 Step 3 Step 4 Linear Case Let Z2 be the transfer function matrix for group 2 UY col u y M be the matrix for the data base Choose a component subdivision Retrieve the matrix M for this subdivision from the data base Compute a and b2 DO i TO m DO j 1 TO s s is the dimension of UY A2 i A2 1 M 4 3 UY j B2 i B2 1 M m i j UY j End of Loop j ics of cog Compute b DO i l TO m B2W i A2 1 Z2 i i End of Loop Compare b with b2 Let e be the tolerance DO i l TO m VALUE TRAN 1 82 1 1 182 3 IF VALUE lt SEN RESULT i 0 ELSE RESULT i 1 End If End of Loop Nonlinear Case Let SOURCE DT be a data file which contains the SPICE code for test inputs and test data Let SPICE DT be a data file which contains either 1
72. onent in group 1 If none of the group 1 components were actually faulty then the test results obtained at this step are reliable The system would then have t 1 faulty components contradicting our assumption to the effect that at most t components are faulty The remaining cases are the same as above Unfortunately the above argument gives the in formation that at least one of the group 1 components is faulty but the identification of the faulty component in group 1 is still not available 57 Heuristic Algorithm Based upon the Analog heuristic the Heuristic algorithm was presented as a multifailure decision algo 41 42 rithm In practice the Heuristic algorithm is used with a cou pling table The coupling table is designed to detect whether or not a faulty group 1 component will effect the test results on a group 2 com ponent Two components are called coupled if they are functions of each other In order to set up this coupling table we first look for the relationship between the group 2 components and the group 1 components Consider the equations 2 10 and 2 11 with the constant matrix K One can rewrite the equation 2 10 as follows l i b a 3 KJ constant term E n m Dn m and then 1 n m ik a J Ka b constant term 1 A k If E is not zero then the group 1 component k effects the group l component i Thus the n m equations give the relationships between
73. osed a variety of analog B 20 29 fault diagnosis algorithms Conceptually these algorithms can be subdivided into three classes i simulation before test ii simulation after test with a single test vector and iii simulation after test with multiple test vectors The first is commonly employed in digital testing and is characterized by minimal on line computational requirements but the high cost of analog circuit simulation coupled with the large number of potential fault modes limits the applicability of this algorithm Typically the simulation after test technique attempts to model the analog fault diagnosis problem as a nonlinear equation in which the internal variables or component parameters are computed in terms of the test data In this case where sufficiently many test points are available only a single test vector is required and the problem reduces to the solution of a linear equation 22 38 Therefore the on line computational require ments are moderate However the test point requirements grow linearly with circuit complexity To reduce the test point requirements one may consider using multiple test vectors to increase the number of equations obtained from a given set of test points However the on line compu tation required to solve these complex sets of nonlinear equations even for linear systems is extremely expensive Comparing the above three techniques the simulation after test with single te
74. program verification the test program is validated by the measurement of the actual UUT as shown in Figure 3 4 On line Component Test Stage The implementation of the actual test on a UUT is as illustrated in Figure 3 5 The maximum number of simultaneous failures allowed is specified by the user the data files matrix Z and vector u and the test program are loaded and the host computer will send an instruction to the HP 9825A controller to conduct the test measurement After the ATE is instructed to generate stimuli for the UUT the measured test data will be stored and transferred to the host computer When the data transfer is completed the test program will compute the test result and identify the faulty component s with the aid of the decision algorithm Nonlinear Case Off line Component Design Stage In the nonlinear case the objective of the off line component is to generate the test program test data for test program use and SPICE codes These SPICE codes are generated for the given circuit test in puts u and test data y and pseudo circuits with equations 2 23 through Test Program Component Component Subdivisions Subdivision Data File for Test Data E SPICE code Call SPICE Code for SPICE for Test Data Program u and y Test Result Figure 3 4 Program Validation Linear Case 27 28 Test with single Test out of tolerance Program failure compo
75. re k th edge and jth source THEN DO m p r TO p IF Li1 m k 20 THEN L72 m j w L11 m k End of loop ELSE in the co tree edge Ly2 k Jj TW End If End of Loop Step 6 IF j o THEN go to step 7 no current source DO i 1 TO J IF the current source is in the tree edge THEN DO m 1 TO r IF L71 m k 0 THEN L12 m j zu L 11 m k End of loop ELSE Li2 k 3 o End If End of Loop Step 7 Generate matrices L2 and L22 assume the number of test points is m DO i l TO m assume y4 is the i th system response IF y4 is selected from the entry of a let it be the k th entry of vector waT THEN L21 1 L7 k and L22 i L12 k 45 ELSE y is specified by user let P t be the specified value corresponding to the nonzero column t Lo i t P t for all nonzero t End If End of Loop Component Subdivisions Table The component subdivisions table is derived from the allowable component subdivisions which satisfy the assumption that not exists Consider an n components circuit with m test points The Loy matrix is then a m by n matrix For the soft ware implementation m X mmatrices are constructed by selecting all possible combinations of m columns from the n columns in the matrix Loy and checking whether or not the matrices are invertible The sub divisions are recorded into the following table if and only if the matrices are invertible Subdivision Group 1 Group 2 Group m number Component Component Component 1
76. results are incorrect which would only happen if one of the group 1 components 53 was faulty This would imply that the system has two faulty components contradicting our assumption that at most one component is faulty In case two the same argument we used above will guarantee that the components which test good say 2 through m are good and we have no in formation about x It may be faulty or alternatively the test results may be due to a faulty group 1 component In the remaining cases we have the same conclusion as in the first case Since under our assump tion of a single failure it is impossible for two or more group 2 components to be faulty these test ne imply that at least one of the group 1 components is bad However since we have assumed that there is at most one faulty component and the group 1 component is the only faulty component then the group 2 components are all good Consistent with the above arguments at each step of the test al gorithm either all or all but one of the group 2 components are found to be good If we choose our subdivision so that good components are included in group 1 the test results obtained at that step will be reliable thereby allowing us to accurately determine the faulty components in group 2 From the above algorithm one may be interested in the problem of how many steps are required to locate the faulty component s For single failure case in each
77. rived from equations 2 17 and 2 18 and a data file for each matrix M is created with the name TEOO DT where is the subdivision number After the test generation process is completed consider the program verification with the test in which the impedance of the first component Cl is changed to 1 of the nominal value i e change the value from j 5 000E 04 to j 5 000E 02 The values of y are then computed as 0 246291D 03 j 0 348101D 05 _ 0 249843D 03 j 0 309305D 06 Y 0 302768D 01 j 0 305966D 01 j 0 414982D 00 0 116744D 00 Suppose also that the fifth subdivision is chosen i e group 2 contains the components 1 2 8 and 9 then the data base M matrix ina file es 2 named TE0005 DT will be retrieved With the known values u and y a and b are computed from the equations 2 17 and 2 18 We then substitute 83 the computed value of al into the component transfer matrix for the group 02 to obtain the corresponding value for b Comparing the com 2 puted values b and b if the difference of each component is less than a given tolerance the result is defined to be good 0 otherwise it is bad 1 The result of this simulation is illustrated as follows Components b b Result 1 2 492637D 02 2 492638D 04 1 2 9 994136D 00 9 994136D 00 0 78 1 756785D 04 1 756785D 04 0 79 3 486035D 03 3 486035D 03 0 From this subdivision we conclude that the test results
78. rocessors i e the parallel processors can be used to reduce the executing time Thus the number t is the maximum number of processors needed To handle the multiple failure following Liu the problem can be greatly simplified if an analog heuristic is adopted The effect will c0 Need be that two independent analog failures will never cancel less to say this is an inherently analog heuristic since two binary failures have a fifty fifty chance of canceling one another In the analog case however two independent failures are highly unlikely to 56 cancel one another as long as one works with reasonably small tolerances Based on the above argument we may assume that a com ponent is definitely good if the test result shows 0 Therefore if a t diagnosable system is assumed that is the number of faulty components does not exceed t al possible test results with the conclusions are shown as follows Test Result Conclusions QE TM MEE OO Oe xd A 10 all group 2 components are good 100 0z ate O components 2 thru m are good b db ue 0 0 0 components t thru m are good Lug P1959 components t 2 thru m are good and at least one faulty component in group nq 1 1 1 a l i 1 at least one faulty component in group ie dc In the first t cases the results show that the component with test result O will be good In the t 2 th case we claim that the com ponents t 2 through m are good and at least one faulty comp
79. s located in the co tree edge R3 with the same orientation By equation 4 8 all elements of the second column of Lio are zero except the position which corresponds to that of Cl i e the 10th row and second column is 1 The L matrix is then generated as follows ly l Ln lig J 6 0 0 d OW ow 4 3 0 0 D O SOc iG Dr dssdo sk idc Oe 0 0 000 0 0 1 00 01 0 0 00 00 00 71 1 001 0 0 0 0 0 0 1 0 1 0 0 0 0 z 0 0 0 100000 01 1 O0 0 0 0 1 0 000 001 0 top xp 3o de a i vc E X o c0 9 0 1 0 0 00 0 0 00 01 1 0 cO 0 0 0 9 0 6 oO L3 77 For convenience we would like to change the component order back to the original component order A matrix transformation where the L matrix and the component input output are reordered is shown a L4 b Lio u where 0 4 0 0 0 7 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 i 1 0 0 0 0 0 L 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 9 0 0 x 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 16 IC VCI IR VRI VR2 IR2 IRC VRC VIN a IBQ b VBEQI u VCEQI ICQI VCC VRE IRE VCE ICE VC2 IC2 IRL VRL VR3 IR3 The dan Ly can be easily checked for correctness by using Kirchoff s laws For Lo matrix a test point description is input The following four test points are selected IC IRI V45 and V13 The first two are
80. s need only be donde once at the factory of a maintenance depot The cost of simulation is therefore relatively cheap Clearly this approach is ideally suited for the maintenance environment With the aid of some sophisticated software engineering this apparently brute force approach to the fault diagnosis problem has slowly evolved into a workable concept 2 program generation systems have been developed and widely used by both military and industrial communities D LASAR by Digitest ATVG by General Electric TGAS by the U S Navy FAS SDAP bv Honeywell LOGOS 12 by Grumman GLASH by Micro SALT by IBM TESTAID III by Hewlett Packard etc are some of the well known systems 9304 1 1419527 33 34335 Several books and articles have discussed the fault detection and diagnosis in digital circuits Typically in the digital circuit one assumes that all permanent component failures are either stuck at zero s a 0 or stuck at one sace Under this assumption one hypothesizes some limit on the number of simultan eous faults and then simulates the responses of UUT Unit Under Test to a family of test vectors for each allowed combination of faults The simulated responses are used to set up a fault dictionary which is stored in some bulk storage media such as disks and magnetic tapes When the test is conducted the actual responses of UUT are compared with the responses in the fault dictionary to locate the failure Of
81. st vector seems to be the closest to the ideal algo 3l The remaining question is how to reduce the number of test rithm points so that this algorithm can be made more applicable An algorithm based on the simulation after test with single test vector was presented to reduce the number of test points The Self Testing Algorithm A bound on the maximum number of simultaneous failures is used to reduce the test point requirements while still retaining the computation al simplicity inherent in a single test vector algorithm It is reasonable to assume that at most two or three components have failed simultaneously in a given circuit iih several hundred IC s and or dis crete components In fact rather than solving a set of simultaneous un equations in n space the solution to our fault diagnosis problem actually lies in a two or three dimensional submanifold which should yield a considerable reduction in test point requirements Unfortunately we do not know which two or three have failed and a further search is still required Fortunately with the aid of an appropriate decision algorithm the required search can be implemented quite simply Conceptually the components individual chips discrete components or subsystems are subdivided into two groups at each step of the test algorithm At each step we assume that one group is composed of good components and we use the known characteristics of these components together w
82. step of the algorithm one concludes that all or all but one group 2 components are good Thus one may select a minimum collection of subdivisions which covers all components i e Let N 1 2 n be a set of n components 54 S 1 2 C be a collection of all possible subdivisions where C is the number of subdivisions then BemniteS NeT 4 12 is the minimum subcollection of S which covers N The subcollection B is not unique If B 1B gt B Bi ts where B is pees in S then t is the minimum steps needed to locate the faulty component Recall that all or all but one components are known to be good at each step of the algorithm After completing the test simulations with the above indicated subdivisions a component which is the only one with test results 1 in a subdivision may be faulty If there exists only One such component eventually the component is located as faulty However if more than than one such components exist more steps are needed to identify the faulty components Let P P4 P5 Po c B where P is the subdivision with the pattern that contains all 0 but one I R R R sls tar a test results 1 all R may not be distinct and oRUS R Pos where Rs is the component with Let R Py sPosee shoud R where all r are distinct In the next steps a subdivision with more than two components of R is selected to simulate the test results and the components whic
83. t subdivision is chosen i e the components 3 4 5 and 7 test the components 1 2 and 6 By the equations 2 12 through 2 15 the K matrix is calculated as follows ID VDI VC2 IC2 IL VLI VRL IRL IRI u VCI y 5 1 VC3 1 VR Y3 IC 0 IC3 0 where uy VIN da IDI y IL and Y3 VRL A SPICE code for the equations 2 23 through 2 26 is generated as follows 90 X k kk 1 FFl0 0 101 VK702 1 VK101 101 102 0 DI 102 0 DM Cock xA amp 2 EE101 103 0 POLY 2 106 0 704 0 0 1 1 VK102 103 104 0 Cc101 104 0 IM XKXk 3 FF102 0 105 VK703 1 VK103 105 106 0 LL101 106 0 0 1 kkkk 4 EE102 107 0 704 0 1 VK104 107 108 0 RRIO 108 0 1K xk k FF103 0 109 POLY 2 VK102 VK703 0 1 1 VK105 109 110 0 RR102 110 0 5 kx 2 EE103 111 0 102 0 4 VK106 111 112 0 ccio2 112 0 U ckokok 3 EE100 113 0 704 0 1 VK107 113 114 0 cc103 114 0 W KKKK EE105 115 0 POLY 4 102 0 106 0 701 0704 0 0 1 1 11 RR108 115 0 1 kx 2 FFl04 0 116 POLY 3 VK102 VK702 VK703 0 1 1 1 VK109 116 0 0 pos dr dr s 3 FFl05 0 117 POLY 2 VK104 VK703 0 1 1 vK110 117 0 0 PRINT TRAN V 115 V 110 PRINT TRAN I VK109 1 VK106 PRINT TRAN I VK110 I VK107 END As shown in equation 5 1 the first row shows that IDI yy j e the current flow through diode Dl equals to the external input yi 91 Define a controlled current source FF101 which is controlled by the current source y 1 VK702 therefore the code is generate
84. tages discussed in the previous algorithms where the heuristic algorithm was applied to the Regular Boolean algorithm the heuristic algorithm can be carried a step further than indicated above Most of the good components will be de termined in few steps using the help of the coupling table ALGORITHM XII Heuristic Boolean Algorithm Step 1 Step 2 Retrieve the component subdivisions table and input t The maximum number of simultaneous failures FLAG j false j 1 2 n Choose a subdivision Step Step Step Step Step Step Step 70 Call subroutines to derive the test results and the tabulated expression Search the pattern which contains more than t s and delete the impossible patterns Let GOOD j be the good components j 1 2 s Retrieve the coupling table TABLE m n m DO j 1 TO s Let x be the row of the component GOOD j DO k 1 TO n m IF TABLE x k 1 THEN Record this component as good End of Loop k End of Loop j FLAG GOOD j strue j 1 2 s If this subdivision is the first one go to Step 2 Eliminate the impossible patterns for both expressions Delete the patterns which predict the good components as bad and replace all 4 to be 0 for the good components Call a subroutine to compute the product of this expression and the previous one Search for the impossible patterns and delete them Repeat the above steps until the actual faulty components are determined
85. ult 0 means good and 1 means fault Therefore the Boolean form for this possible test result can be expressed as follows abcde xyz Here the letter a indicates the component a is bad and a means the component a is good However the test may be unreliable if one of the group 1 components is bad In that case the remaining components could be either good or bad and those components are thus defined as don t care with the notation If the group 1 component a is assumed to be bad for instance the possible pattern is that a is bad and the remaining components are don t care and the expression for this pattern is a adoooooo Therefore the completed results for this test will be expressed by a Boolean form as follows T atb tct d etabcdexyz 4 13 Our goal is to combine the information derived from various test results so that the actual fault s can be fully identified Consider the test results for another subdivision in this example where components a b C X and z are in group 1 and components d e and y are in group 2 The test result is assumed to be 62 gn n tt a b C X Z The Boolean expression for this test is IE ES A 4 14 If we combine these two results the intersection of the two expressions T and T5 is derived by directly applying the multiplica tion rule of two logical functions and thus Tag AT 2 atb tctdtetabcdexyz atbtct x z abcdexyz atb c dx dz
86. xpression Step 0 Let GRy i be the group 1 components i 1 2 n m GR2 1 be the group 2 components i 1 2 m RESULT i be the test results i 1 2 m TABLE n n m 1 be the tabulated expression Step 1 If one of group 1 components is faulty DO i TO n m Initialize TABLE m i 9 j 1 2 n TABLE GR i i 1 End of Loop Step 2 Case of the group 1 components are all good DO i l TO n m TABLE i n m 1 0 End of Loop Step 3 Copy the test results DO i TO m TABLE n m i n m 1 RESULT i End of Loop Similarly following this algorithm the tabulated expression for equation 4 14 can be written as follows 64 abc de x y z 1 4 6 6 6 6 6 1 9 9 6 9 0 4 1 9 9 9 9 4 6 6 9 1 9 4 9 06 gt l 0001 171 0 0 0 The following rules will be used to compute the intersection of any two Boolean expressions Rule 1 Let the Boolean set B 0 1 q the l1 x x x 2 x o xX xX where x 0 1 or 6 3 0 1 1 0 null impossible pattern Rule 2 A B C A B D A B CD ALGORITHM IX Intersection of two Boolean expressions Step 0 Let Tilni ta and To n to be the two inputs expressions T3 n t3 be the output expression NUM be the number of the common terms of T4 and To NUM is initialized by O Step 1 Searching for the common terms DO i 1 TO t DO j 1 TO t Compare f ki with To k j k 1 2 n If they have the common terms then record them End of
87. y the current controlled sources connected in parallel are used to describe the current measurement case After the SPICE code for equation 2 24 is generated properly con sider the equation 2 25 with the partitioned matrices A NES 1 p a Koi b Ko u 4 10 2 v 2 1 2 p The SPICE code for equation 4 11 is generated the same as that for equation 2 24 except that the box in Figure 4 1 is replaced by a zero valued voltage source if the element of b is a current measurement or by a resistor with resistance 1 for a voltage measurement Similarly the SPICE code for equation 4 11 can be generated in the same way 49 however what we are interested in is the values b Therefore the box in Figure 4 1 is filled by the component with equation 2 26 to compute the v lue b ALGORITHM III Data Base Step 1 Linear Case Let C be the number of all possible subdivisions DO i 1 TOC Compute K matrix Equations 2 12 through 2 15 Compute M matrix Equation 2 16 Store M to a data file named TEOO DT End of Loop Step 1 Nonlinear Case Let N be the number of components M be the number of test points NM N M Step 2 For equations 2 23 and 2 24 DO i 1 TO NM IF al 1S a voltage measurement THEN Connecting the controlled sources which have nonzero elements in Kj and Kyo in series ELSE Connecting the controlled sources which have nonzero elements in K and Kj in parallel Connecting a
88. y b Lio u 2 2 y L4 b Los vu 2 3 15 Here XS are the component state variables The component equation 2 20 is modeled in the time domain Similarly as in the linear case the components are subdivided into two groups The variables in 2 20 are then partitioned as x 0 0 E 2 21 NI OE b g x a and xe f x a x 0 0 2 22 b g x a The connection equations 2 2 and 2 3 are partitioned as the equations 2 5 through 2 7 For each component subdivision a pseudo circuit is generated in the form T uta 1 x 0 0 2 23 b g x a l1 p a Ku b Kio u 2 24 y E Koy b Kno uP 2 25 where the connection matrix K of the pseudo circuit is derived in the equations 2 12 through 2 15 Since in our test algorithm both u and y are known the above equations can be solved via any standard circuit 25 26 2 2 analysis code SPICE NAP2 etc to compute yP Col a b Once the values al and b are computed with the computation of 16 2 245 x 0 0 2 26 b g x a to determine which if any of the groups two components are faulty However the above test results are dependent on our assumption that the group 1 components are not faulty they are not immediately applicable A decision algorithm is required to cope with this ambiguity problem so that the actual fault s can be precisely identified Follow 2 14 30 in ing the philosophy

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