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PMC-SLX150 / PMC-SLX150-1M User`s Manual

1. USER S MANUAL Reconfigurable Xilinx FPGA In system configuration of the FPGA is performed through a flash configuration device or via the PCI bus This provides a means for creating custom user defined designs Dual Port SRAM A 256K x 64 bit dual port static random access memory SRAM is included One port of the SRAM provides a direct link from the PCI bus to the SRAM memory The second port of the SRAM provides a direct link to the Xilinx user programmable FPGA There is an order option 1M to increase the SRAM size to 1 Meg x 64 bit Interface to Front Multifunction Modules Various mezzanine modules AXM model prefex ordered separately allow the user to select the Front I O required for their application Interface to Rear P4 Connector The Spartan 6 FPGA is directly connected to 64 pins of the rear P4 connector All 2 5volt IO standards supported by the Spartan 6 device are available The example design provides low voltage differential signaling as 32 LVDS input output signals Write Disable Jumper User configurable flash memory can be hardware write disabled by removal of an on board zero ohm surface mount resistor Example Design Provided The example VHDL design includes implementation of the Local bus interface control of digital front and rear I O and SRAM read write interface logic PCI Bus Modes The board supports PCI X at 100MHz 66MHz and 33MHz PCI Bus Master The PCI interface lo
2. RloaN 111 routed to pins 1 3 2 4 etc 5 12 6 RIOGP 13 RIO6GN 115 7 16 8 19 9 RIOOP 18 rogn 20 10 23 11 24 12 27 13 28 14 31 15 32 16 35 17 36 18 39 19 40 20 43 21 44 22 47 23 RI023P 146 RIO23N 48 24 RIO22 P 149 JRI2AN 51 25 52 26 55 27 56 28 59 29 60 30 63 31 RIO31 P 62 RIO31_N 64 This connector is a 64 pin female receptacle header AMP 120527 1 or equivalent which mates to the male connector on the carrier board AMP 120521 1 or equivalent Non Isolation Considerations The board is non isolated since there is electrical continuity between the logic and field I O grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections Acromag Inc Tel 248 295 0310 9 WWW acromag com PMC SLX150 Flash Write Disable Resistor USER S MANUAL By default the flash memory U6 is read write enabled Removal of resistor R90 disables writing the flash configuration device Refer to Resistor Location Drawing at the end of this manual to identify the board location of R90 3 0 PROGRAMMING INFORMATION This Section provides the specific information necessary to program and operate the board GETTING STARTED Acromag Inc Tel 248 295 0310 The PMC SLX150 board is shipped wi
3. Tel 248 295 0310 27 www acromag com PMC SLX150 USER S MANUAL SYSTEM MONITOR REGISTERS U5 PCI bus System Monitor Status Control Register Read Write BAR2 38H This read write register will access the system monitor register at the address set in the System Monitor Address Register For example the address of the System Monitor Status register that is to be accessed is first set via the System Monitor Address register at BAR2 plus 3CH Next this register at BAR2 plus 38H is read Bits 22 to 16 of this register hold the address of the system monitor register that is accessed Data bits 15 to 6 of this register hold the ADCcode temperature Vccint or Vccaux value Data bits 5 to O are not used Valid addresses are given in column one of Table 3 12 Reading or writing this register is possible via 32 bit data transfers The 10 bits digitized and output from the ADC can be converted to temperature by using the following equation Temperatur C A 273 15 The 10 bits digitized and output from the ADC can be converted to voltage by using the following equation DCcode X A SupplyVolage volts 3V pplyVolag amp volts m System Monitor Address Register Write Only BAR2 3CH This write only register is used to set the system monitor address register with a valid address for the System Monitor internal status or control registers Valid addresses are given in the following table Additio
4. 33MHz 64 32 bit interface to the carrier CPU board per PCI Local Bus Specification 3 0 The interface to the carrier CPU board allows complete control of all board functions Note that the PMC SLX board requires that system 3 3 volts be present on the PCI bus 3 3V pins There are some older systems that do not provide 3 3 Volts on the PCI bus 3 3 volt pins The PMC SLX boards will not work in those systems This is a master target board with the PCI bus interface logic contained within the board This logic includes support for PCI commands including configuration read write and memory read write In addition the PCI interface performs target abort retry and disconnect The logic also implements interrupt requests via interrupt line INTA amp The board becomes the PCI bus master to perform DMA transfers on channels 0 and 1 The DMA transfers can be started via software or hardware Hardware signal DREQO driven active by the programmable FPGA will start a DMA channel 0 transfer Hardware signal DREQ1 driven active will start a DMA channel 1 transfer To identify the pins corresponding to these signals see the user constraints UCF file provided in the engineering design kit The DACKOH and DACK14 signals will go active upon the start of a DMA transfer and remain active until its completion The example device driver software purchased separately can be used to exercise DMA block software and demand hardware modes of operation
5. Distributed RAM e 268 18Kbit Block RAMs e 180 DSP Slices 6 Clock Management Tiles Acromag Inc Tel 248 295 0310 45 www acromag com PMC SLX150 USER S MANUAL REAR I O The rear I O P4 PMC connector connects directly to banks O of the FPGA The bank 0 Vcco pins are powered by 2 5 volts and thus will support the 2 5 volt IOStandards Refer to the Spartan 6 SelectlO User Guide available from Xilinx for more information on the IOStandards available The example design defines the rear I O with 2 5 volt LVDS e Maximum Recommended Clock Rate 150MHz 6 7ns clock period e Veco Supply Voltage sss 2 5 volt e VOH Output High Voltage 1 602 volt e VOL Output Low Voltage 0 898 volt e VODIFF Differential Output Voltage 350m volt typical e VOCM Output Common Mode Voltage 1 25 volt typical e VIDIFF Differential Input Voltage 100m volt minimum e VICM Input Common Mode Voltage 0 3 volt min 1 2 volt typical 2 35 volt max FRONT I O If optional AXM mezzanine modules are used air cooled operation only refer to the AXM user s manual for front I O specifications This PMC module uses the 150 pin Samtec connector part number QSS 075 01 L D A which mates with the mezzanine module connector part number QTS 075 02 L D A K Write Disable Jumper Write Disable Jumper Removal of surface mount resistor R90 disables writ
6. aae dde ee a eek eae Fu o een ita ha retra nione naa 8 Default Hardware Configuration esssssessssesesesee eese enne nnn nnns aaa te sanas essen satanas assess sata a sanis 8 Front Panel Field I O Connector eee eee aaa aaa aa aaa aaa aaa zaawan aaa aa aaa aaa iata aa aeta dass nanda 8 Rear PA Field O Connector eee aaa anna ann aaa nae aaa aa aaa aaa seii anna aaa za ansiano oaao aitei 8 Non Isolation Considerations ccsscccssseccsscccnsscccssccassccccsesccseecceseccnssceccnscecaeeceseseseseness 9 Flash Write Disable ResiStOF c ccsssceiesssscensssacectsesoaccssvscnseseosetecsensedendendtnsndecseisebecdesensevsodecdessatcctessatiniseseae 10 3 0 PROGRAMMING INFORMATION eene enne enn nn nnn nnn nnn nua nn nuu nn nana annuus 10 GETTING STARTED pe 10 PCI CONFIGURATION ADDRESS SPACE eseseseseseseseseseseseseseseseseseseseseseseseseseseseseseseseseseses 11 CONFIGURATION REGISTERS 2 saseta suis io rotta t a E a a Sesi 12 BARO MEMORY MAP 14 Interrupt Control Status Register Read Write BARO OOH ccscccesecssscesseecsecesseecssecesseeesseeeseees 15 DMA Status Abort Register Read Write BARO 04H rrnvrrrsnrrenvrnorvrrenvrrrrvrrenvrsrsvrrnnvrsrsrnsenvrsssrnsnnvssne 16 Global Interrupt Enable Bit 31 Read Write BARO 08H rrrennrernnrrnrnvnrenrrrrnrennnvrsnnvrnenressnressnvr
7. read as logic 0 Acromag Inc Tel 248 295 0310 23 www acromag com PMC SLX150 USER S MANUAL Configuration Control Read Write BAR2 04H Table 3 9 Configuration Control Register This read write register is used to stop Xilinx configuration and clear Xilinx configuration memory This Configuration Control register is accessed at base address plus 04H Bit s FUNCTION 0 Stop Xilinx Configuration Oo Enable Xilinx FPGA configuration Stop Xilinx FPGA configuration This bit should be 1 set to logic high until after the Flash device is m written with valid program data 1 Not Used bit is read as logic O 2 Clear Current Xilinx Configuration Logic low has no effect Logic high resets the Xilinx configuration logic Re configuration can begin after INIT transitions high 3to7 Not Used bits are read as logic 0 Configuration Data Write Only BAR2 08H This write only register is used to write Xilinx configuration data directly to the Xilinx FPGA from the PCI bus The Configuration Data register is accessed at base address plus 08H The entire configuration file must be written to the Xilinx FPGA one byte at a time Configuration complete is verified by reading DONE bit 0 of the Configuration Status Register as logic high A write to the Configuration Data register while auto configuration from Flash is active will cause the Xilinx configuration to f
8. same device and vender ID in a given system Reading from this register is possible via 32 bit 16 bit or 8 bit data transfers 36 www acromag com PMC SLX150 USER S MANUAL Temperature Data Register Read only BAR2 8090H This read only register provides the data from the external temperature monitor on the PMC SLX This register is automatically updated every second Data bits 12 to 0 of this register hold the temperature information Reading this register is possible via 16bit or 32 bit data transfers The 12 bits digitized output from the temperature sensor reads from 55 C minimum to 150 C maximum The number is stored in two s compliment format with each bit equal to 0 0625 C Refer to table 3 19 for data values Table 3 19 Temperature Data FO External Temperature Data 0 0000 0000 0000 0 0000 0000 0001 0 1001 0110 0000 1111111111111 111100111 0000 1 1100 1001 0000 55 C Min DUAL PORT MEMORY A 256K x 64 bit standard model or 1Meg x 64 bit 1M model Dual Port synchronous SRAM DP SRAM is provided on the PMC SLX board One port of the SRAM connects directly to the local bus to allow for PCI access The remaining port connects directly with the user programmable FPGA This design allows for the user to maximize data throughput between the Field I O s and the controlling processor There are two automatic DMA initiators available that will trigger upon a user set threshold Furthermore upon a DMA transfe
9. 0 1 Threshold Registers Read Write BAR2 8048H 804CH Note An SRAM DMA Request The FPGA Port SRAM DMA Channel 0 1 Threshold Registers are used to will occur only after a data initiate an automatic DMA transfer When the internal address counter is write cycle to the address equal to the value in the DMA Channel 0 Threshold Register and there is valid defined by the DMA Threshold data at that address a Channel O DMA request will be initiated Similarly Registers when the internal address counter is equal the value in the DMA Channel 1 Threshold Register and there is valid data at that address a Channel 1 DMA request will be initiated This feature must be enabled via bits 1 and 2 for Channels 0 amp 1 respectively of the FPGA SRAM Control Register Note that DMA settings must be configured prior to the initiated transfer on both the PCIBARO and PCIBAR2 registers A DMA transfer in progress is indicated via bits 0 and 1 for DMA Channels 0 and 1 respectively in the DMA Control Register See the DMA Registers section of this manual for further details Reading of the Threshold register will return the corresponding DMA Threshold Writing the Threshold registers will set the corresponding DMA Threshold to the provided value Bits O to 17 of this register are used on the standard model while bits O to 19 are used for the 1M model Reading or writing to this register is possible via 32 bit data transfers only Table 3 18 Dual Por
10. 1 PMC SLX150 E 0x5702 PMC SLX150 E 1M 16D5 1 Command 2 Rev ID 00 3 Cache 4 32 bit Memory Base Address for Memory Accesses to PCI interrupt and DMA Registers 4K Space PCIBARO 5 32 bit Memorv Base Address 64 bit Data to Dual Port Memory 4M Space for standard model PCIBAR1 SM Space for 1M model PCIBAR 6 32 bit Memorv Base Address 32 bit Data to Spartan 6 User Registers 4M Space PCIBAR2 7 10 Not Used 11 Subsystem ID Subsystem Vendor ID 0x5701 PMC SLX150 E 0x5702 PMC SLX150 E 1M 16D5 12 Not Used 13 14 Reserved 15 Max Lat Min Gnt Inter Pin Inter Line This board is allocated memory space address PCIBARO to access the PCI interrupt and DMA registers The PCI bus decodes 4K bytes for these memory space registers PCIBARO space is accessed using 32 bit data transfers This board is allocated PCIBAR1 memory of 4M byte for a standard model and 8M byte for 1M model The PCIBAR1 memory is addressable in the PCI bus memory space to access the board s Dual Port Memory using 32 bit or 64 bit transfers In addition this board is allocated a 4M byte block of memory PCIBAR2 that is addressable in the PCI bus memory space PCIBAR2 space is used to access the board s flash configuration functions and the reprogrammable Spartan 6 FPGA functions via 32 bit data transfers Acromag Inc Tel 248 295 0310 13 www acromag com PMC SLX150 BARO MEMORY MAP Table 3 2 BARO Registers Note that any registers bits not
11. 248 295 0310 41 WWW acromag com PMC SLX150 USER S MANUAL Local Bus Write Cycle Diagram pidk EJ LD LR IL OLE LETE ETT pd cbe pd_ad te Jzzzzzzzzo0000033 1 1j pci stop p desd Doe DO m GO Og la 0000018 1002011 Ibe0_n lbei n ld 00000000 00000033 00000033 Acromag Inc Tel 248 295 0310 42 www acromag com PMC SLX150 USER S MANUAL 5 0 SERVICE AND REPAIR Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested before shipment Service and Repair Assistance Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Preliminary Service Procedure CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Where to Get Help Before beginning repair be sure that all of the procedures in the Preparation for Use section have been followed Also refer to the documentation of your board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have pr
12. 310 32 WWW acromag com PMC SLX150 Table 3 16 FPGA Port SRAM Control Register 1 Bits are not used and will return logic 0 when read 2 All DMA transfer settings in the DMA Registers at BARO should be set prior to enabling automatic DMA transfers 3 WARNING Before enabling Address Reset on DMA Thresholds bits 3 amp 4 verify that the DMA Ch 0 Threshold Register is not equal to the Address Reset Register 0 and the DMA Ch 1 Threshold Register is not equal to the Address Reset Register 1 If these registers are equal and automatic reset is enabled an infinite loop will be created within the internal logic of the FPGA Acromag Inc Tel 248 295 0310 USER S MANUAL BIT 5 15 FUNCTION This bit controls the VHDL signal SRAM_ENABLE This signal must be set to logic high to enable writes to SRAM from the FPGA The SRAM Internal Address register must also be set with the start address at which the data begins filling the SRAM Logic 0 Disable Write and Enable Read Logic 1 Enable Write and Disable Read If enabled via this bit a DMA channel 0 request will be issued when the internal address counter is equal to the DMA Channel 0 Threshold Register This will have the same effect as writing a 1 to bit 0 of the DMA Control Register at BAR2 plus 8034H See Synchronous DP SRAM in Section 4 0 for further details on using this feature Logic 0 Disable Auto DMA Request Ch
13. 3V Compliant INTA Interrupt A is used to request an interrupt Source of interrupt can be from the Digital I O or DMA Channels Acromag Inc Tel 248 295 0310 47 www acromag com PMC SLX150 USER S MANUAL Certificate of Volatility Certificate of Volatility Acromag Model PMC SLX150 E PMC SLX150 E 1M Manufacturer Acromag Inc 30765 Wixom Rd Wixom MI 48393 Volatile Memory Does this product contain Volatile memory i e Memory of whose contents are lost when power is removed m Yes No Type SRAM SDRAM etc size User Modifiable Function Process to Sanitize SRAM m Yes Data storage for Power Down 256K x 72 or No FPGA 1Meg x 72 Type SRAM SDRAM etc Size User Modifiable Function Process to Sanitize FPGA based RAM Variable up m Yes Data storage for Power Down to 1 28Mbyte No FPGA Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed m Yes No Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize Flash 16Mbyte m Yes Storage of Code for Clear Flash memory by writing No FPGA a logic 1 to bit 0 of the Flash Erase Chip Register at BAR2 24H Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize Flash 32Mbit Yes Storage of Code for N
14. 95 0310 11 WWW acromag com PMC SLX150 USER S MANUAL microprocessors uses Little Endian byte ordering Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Big endian means that the most significant byte is stored at the lowest memory address and the least significant byte is stored at the highest memory address Low address Layout of a 64 bit long int High address Big Endian Byte 7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte 0 CONFIGURATION REGISTERS The PCI specification requires software driven initialization and configuration via the Configuration Address space This board provides 512 bytes of configuration registers for this purpose It contains the configuration registers shown in Table 3 1 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Ports The most important Configuration Registers are the Base Address Registers and the Interrupt Line Register which must be read to determine the base address assigned to the board and the interrupt request line that goes active on a board interrupt request Acromag Inc Tel 248 295 0310 12 www acromag com PMC SLX150 USER S MANUAL Table 3 1 Configuration Reg D31 D24 D23 D16 D15 D8 D7 DO Registers Num 0 Device ID Vendor ID 0x570
15. Acromag 4 THE LEADER IN INDUSTRIAL 1 0 PMC SLX150 PMC SLX150 1M Spartan 6 Based FPGA PMC Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2011 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 923 B13C012 PMC SLX150 USER S MANUAL Table of Contents LO GENERAL INFORMATION Gs 4 Ordering Informatio T 4 Key Features M 5 PCI Interface Features oir eee eee eere u ehe ee ese au evo descuido erp eo o eae EE PER SEEE dades do den dobic Rp w de 5 Sh AVEICETEATIERSDTECCREUOLAIUTTI IUD 6 ENGINEERING DESIGN KIT NONE NONONO NONE NTNTNONONONENONONONEAE 6 BOARD DLL CONTROL SOFTWARE ue eu eu en eu enea ea ea enea aa nnn nnn aa aa nasa aa sana aaa aaa aa AN ETE aa sa aa ANAN iia ANa aran iiaa 6 BOARD VXWORKS SOFTWARE eeueueueu eee eee aaa aaa aaa aaa aaa aaa aa aa waza ana aaa aaa aa aaa aaa aa aeee nene aeee aa aa aa aa aeee aeee area area nanda 6 BOARD Linux SOFTWARE t 7 2 0 PREPARATION FOR USE sj 7 Unpacking and Inspecting sss ow o Wow dessus ERR INE EY aa a FE ENS Ere VE REPE EVER duas 7 Card Cage Considerations er riri pa tuor eo EV a WE w k mh 7 Board Configuration eise erronee ea eto itta ae nant aaa no viana seta ada ee eaa c
16. EA AGA A Alnes 48 PME SLX Block Diagram a d k 49 All trademarks are the property of their respective owners IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility The information of this manual may change without notice Acromag makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Acromag Inc Tel 248 295 0310 3 www acromag com PMC SLX150 USER S MANUAL RELATED PUBLICATIONS The following manuals and part specifications provide the necessary information for in depth understanding of the AX board Virtex 5 Data Book IDT70T3519S Spec IDT70T3509MS Spec CY23EP05 Specification http www xilinx com http www idt com http www id
17. ER S MANUAL Table 3 13 Software Reset and BIT FUNCTION Status Register Mezzanine interrupt status is identified via data bits O 1 All bits labeled Not Used to 7 Read of a 1 indicates that an interrupt is ill return logic O wh pending for the corresponding data bit A pending VE GE U WREN 7 0 interrupt will remain active until disabled via the read mezzanine interrupt control registers Logic 0 Interrupt Not Pending Logic 1 Interrupt Pending USERo Control 8 Logic 0 Board clock PLL CLK Default Logic 1 Board clock 125MHz 12 9 Not Used Mezzanine Identification Code 15 13 001 for all Acromag digital I O mezzanine boards 010 for the AXM A30 mezzanine board 26 16 Not Used DACKO Status 27 Logic high is a valid acknowledgement for DMA channel 0 DACK1 Status 28 Logic high is a valid acknowledgement for DMA channel 1 29 30 Not Used The most significant bit of this register when set to a logic 1 will issue a software reset Bit 31 Logic 0 No Operation Software reset issued to Xilinx user Logic 1 programmable FPGA Rear I O Connector Read Register Read Only BAR2 802CH The Rear I O Connector Read Register is used to read the LVDS input status of 16 channels This example design has 16 channels identified in Table 3 14 programmed as LVDS input only channels Table 2 1 shows each channel and its corresponding P4 connector pin assign
18. R S MANUAL of U7 only when bit 18 is set to logic high The Software Reset and Status Register at BAR2 8000H can be read to identify the exact source of the Programmable Virtex 5 FPGA interrupt Bits 16 to 18 of this register are used to enable or disable interrupts from specific functions This Interrupt register must have bits 16 and 17 set to logic high in order for DMA interrupts to occur on DMA channels 0 and 1 respectively Bit 18 must be set to logic high to enable interrupts from U7 the programmable FPGA The mezzanine board interrupt enable bits must also be set if interrupts are to originate from the mezzanine board which are passed through the programmable FPGA to this register s pending status bits DMA Status Abort Register Read Write BARO 04H This DMA Status register at BARO base address plus 04H is used to identify a DMA transfer complete status and to issue a DMA channel abort The DMA complete status bit O or 1 will remain logic high until cleared by writing logic high back to the same bit The start of a new DMA transfer hardware initiated will also clear a set Transfer Complete bit The DMA abort bits 8 and 9 corresponding to channels O and 1 respectively when set to logic high will abort the current DMA transfer If asserted and the channel still has outstanding requests all requests are handled before the transfer is aborted otherwise the transfer is immediately aborted If asserted and the current tr
19. SLX150 USER S MANUAL reconfiguration of the Xilinx FPGA 1 8 Acromag Inc Tel 248 295 0310 Disable auto configuration by setting bit 0 Stop Configuration of the Configuration Control register to logic high Clear the Xilinx FPGA of its previous configuration by setting the Configuration Control register bit 2 to logic high Software must also keep bit 0 set to a logic high Read INIT as logic high Bit 1 of Configuration Status register before programming is initiated Verify that the Flash Chip is not busy by reading bit 7 of the Flash Status 2 register at base address plus 10H as logic 0 before starting a new Flash operation Erase the current flash contents by using the Flash Erase Sector method Flash erase sectors are implemented by setting bit 0 of the Flash Erase Sector register to logic high There are 128 flash sectors which are addressed via the most significant seven flash address lines The most significant seven flash address lines are set via the Flash Address 23 16 register at base address plus 34H Issuing a Flash Erase Sector command will erase the contents of the flash chip only in the sector specified Verify that the Flash Chip is not busy by reading bit 7 of the Flash Status 2 register at base address plus 10H as logic O before going to the next step Download the Configuration file to the flash configuration chip via the PCI bus i Write the byte to be sent to the Flash Data register at b
20. SYNCHRONOUS Dual Port SRAM A 256K x 64 bit standard model 1Meg x 64 bit 1M model synchronous Dual Port SRAM is provided on the board One port of the SRAM interfaces to the PCI bus interface chip the Xilinx Virtex 5 LX30 device U5 The other port connects directly to the programmable FPGA U7 This configuration allows for a continuous data flow from the field inputs through the FPGA to the SRAM and then to the PCI bus Both ports of the SRAM operate in Pipeline mode This allows for faster operational speed but does cause a one cycle delay during read operations The pins corresponding to the control signals address and data buses are in the user constraint UCF file Acromag Inc Tel 248 295 0310 39 www acromag com PMC SLX150 Local Bus Signals USER S MANUAL provided in the engineering design kit The SRAM port connected directly to the user programmable FPGA U7 supports continuous writes or single cycle reads The SRAM port connected to the PCI bus through U5 supports reading and writing using a continuous single cycle or DMA transfers For single cycle accesses address and control signals are applied to the SRAM during one clock cycle and either a write will occur on the next cycle or a read in two clock cycles DMA accesses operate using the continuous burst method for maximum data throughput The control signal starting address and data if writing are applied to the SRAM during one clock cycle Then durin
21. ail Auto configuration is stopped by writing logic 1 to bit 0 of the Configuration Control register at base address plus 04H The Xilinx FPGA should also be cleared of its current configuration prior to loading of a new configuration file The FPGA is cleared of its current configuration by writing logic 1 to bit 2 at address plus 04H Acromag Inc Tel 248 295 0310 24 www acromag com PMC SLX150 USER S MANUAL Flash Status 1 Read Only BAR2 OCH This read only register is used to read the DQ5 status of the flash chip The Flash Status 1 register is at base address plus OCH Table 3 10 Flash Status 1 Register Chip enabled for reading array data The system must issue the Flash Reset command to re enable the device for reading array data if DQ5 goes high DQ5 will go high during a Flash Start Write Flash Erase Chip or Flash Erase Sector operation Not Used bits are read as logic 1 or 0 Flash Status 2 Read Only BARZ 10H This read only register is used to read the ready or busy status of the flash chip The Flash Status 2 register is at base address plus 10H The system must first verify that that Flash Chip is not busy before executing a new Flash command The Flash Chip is busy if bit 7 of this register is set to logic 1 The Flash will always be busy while bit 0 of the Configuration Control register is set to logic O FUNCTION Not Used bits are read as logi
22. all board interrupts An interrupt can originate from the two DMA channels or U7 the programmable FPGA All board interrupts are enabled when bit 31 is set to logic high Likewise board interrupts are disabled with bit 31 set to logic low Bit 31 of this register can be read or written Table 3 5 Global Interrupt Enable Bit FUNCTION Not Used bits are read as logic 0 PMC Board Interrupt Enable This bit must be set to enable the PCI bus interrupt signal to be driven active 0 Board Interrupts Disabled 1 Board Interrupts Enabled 31 Acromag Inc Tel 248 295 0310 17 WWW acromag com PMC SLX150 USER S MANUAL DMA System Starting Address LSB Registers Read Write BARO 100H and 114H The DMA System Starting Address register meaning depends on the selected DMA mode see bit 3 of DMA command register For Direct DMA Mode this address register specifies the physical address of a contiguous memory buffer where data will be read written For scatter gather DMA mode this address register points to the first element of the chained listed of page descriptors The DMA System Starting Address Register at PCIBARO base address plus 100H 114H is used to set the DMA channel 0 1 data starting address Writing to these registers is possible via 32 bit transfers only DMA System Starting Address MSB Registers Read Write BARO 104H and 118H The DMA PMC Board Starting Address register specifi
23. annel 0 Logic 1 Enable Auto DMA Request Channel 0 If enabled via this bit a DMA Channel 1 request will be issued when the internal address counter is equal to the DMA Channel 1 Threshold Register This will have the same effect as writing a 1 to bit 1 of the DMA Control Register at BAR2 plus 8034H Logic 0 Disable Auto DMA Request Channel 1 Logic 1 Enable Auto DMA Request Channel 1 If enabled via this bit the Internal Address Counter will be loaded with the value in Address Reset Register O when the counter is equal to the DMA Channel 0 Threshold Register See the Address Reset Register description for further details DMA does not have to be enabled to use this feature Logic 0 Disable Add Reset on DMA Ch 0 Threshold Logic 1 Enable Add Reset on DMA Ch 0 Threshold If enabled via this bit the Internal Address Counter will be loaded with the value in Address Reset Register 1 when the counter is equal to the DMA Channel 1 Threshold Register See the Address Reset Register description for further details DMA does not have to be enabled to use this feature Logic 0 Disable Add Reset on DMA Ch 1 Threshold Logic 1 Enable Add Reset on DMA Ch 1 Threshold Not Used 33 WWW acromag com PMC SLX150 USER S MANUAL FPGA Port SRAM Internal Address Register Read Write BAR2 8044H Warning To guarantee functionality disable DP SRAM write cycles via bit 0 of the DP SRAM Con
24. ansfer is a Completion than a Completion with Completion Abort status is sent and the DMA transfer is stopped This register can be read or written via 32 bit transfers Acromag Inc Tel 248 295 0310 16 www acromag com PMC SLX150 USER S MANUAL Table 3 4 DMA Status Register Bit s FUNCTION 0 DMA Channel 0 Transfer Complete This bit is cleared by write of logic high to this bit or start of a new DMA transfer DMA BARO REGISTERS 0 Transfer not Complete 1 Transfer Completed 1 DMA Channel 1 Transfer Complete This bit is cleared by write of logic high to this bit or start of a new DMA transfer 0 Transfer not Complete 1 Transfer Completed 2 7 Not Used bits are read as logic 0 8 ES Channel 0 Interrupt Abort on write of logic high to this it 0 No Action 1 Abort Channel 0 DMA transfer 9 DMA Channel 1 Interrupt Abort on write of logic high to this bit 0 No Action 1 Abort Channel 1 DMA transfer 10 15 Not Used bits are read as logic 0 16 19 DMA Channel 0 or State Encoding 0000 Transfer Completed Successfully 0001 to 0111 Transfer Aborted 1000 to 1100 Transfer not yet completed DMA Channel 1 State Encoding see bit descriptions given for Channels 0 on bits 16 19 24 31 Not Used bits are read as logic 0 20 23 Global Interrupt Enable Bit 31 Read Write BARO 08H This Global Interrupt Enable bit at BARO base address offset 08H is used to enable
25. ase address plus 28H ii Write the address of the Flash Chip to receive the new data byte to the Flash Address registers at base address plus 2CH 30H and 34H Issuing a Flash Start Write will automatically increment this address after the prior Flash Write has been completed Thus the address will not need to be set prior to issuing the next Flash Start Write The first byte of the configuration file should be written to address O of the Flash Chip The Flash Start Write operation will take 9u seconds to complete iii Issue a Flash Start Write command to the Flash Chip by writing logic 1 to bit O of base address plus 1CH iv Verify that the Flash Chip is not busy by reading bit 7 as logic O of the Flash Status 2 register at base address plus 10H before going back to step i to write the next byte Enable auto configuration by setting bit 0 Stop Configuration of the Configuration Control register to logic low 22 WWW acromag com PMC SLX150 9 USER S MANUAL Verify that the configuration is complete by reading DONE bit 0 of Configuration Status Register as logic high 10 Thereafter at power up the configuration file will automatically be loaded into the FPGA Direct PCIe bus to Xilinx Configuration Configuration of the Xilinx FPGA can be implemented directly from the PCI bus The following is the general procedure for re configuration of the Xilinx FPGA via the PCI bus 1 Disable auto configuration by setting b
26. assigned by system software upon power up via the configuration registers A PCI bus configuration access is used to read write the PCI card s configuration registers When the computer is first powered up the computer s system configuration software scans the PCI bus to determine what PCI devices are present The software also determines the configuration requirements of the PCI card The system software accesses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base address The configuration registers are also used to indicate that the board requires an interrupt request line The system software then programs the configuration registers with the interrupt request line assigned to the board Since this board is relocatable and not fixed in address space its device driver must use the mapping information stored in the board s Configuration Space registers to determine where the board is mapped in memory space and which interrupt line will be used The memory maps in this chapter reflect byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte Little Endian means that the least significant byte is stored at the lowest memory address and the most significant byte is stored at the highest memory address The Intel x86 family of Acromag Inc Tel 248 2
27. board s SRAM memory Register The Memory Write Burst command is used to program a write transfer The data moves from the board s SRAM to system memory DMA transfers must start aligned to a Lword boundary Writing to these registers is possible via 32 bit transfers only when implemented as a 32 bit transfer and a Double Lword boundary when performing 64 bit DMA transfers Acromag Inc Tel 248 295 0310 Bit s FUNCTION Not Used bit is read as logic 0 Priority Setting this bit marks the DMA channel as high priority A higher priority channel takes precedence over the second channel and thus has access to the PCI bus more 1 quickly O Low Priority High Priority 64 bit or 32bit Mode 32 bit Mode DMA Transfers 64 Bit Mode DMA Transfers Scatter gather Setting this bit enables scatter gather mode 0 Direct DMA Mode 1 Enable Scatter Gather Mode 7to4 DMA Command 1110 Memory Read Burst Memory Read Line 4111 Memory Write Burst Memory Write and Invalidate DMA Byte Enables 8to 11 9000 All bytes are transferred These bits should always be logic low 12 to 31 Not Used bit is read as logic 0 19 WWW acromag com PMC SLX150 BAR2 MEMORY MAP Table 3 7 BAR2 Memory Map 1 The board will return 0 for all addresses that are Not Used USER S MANUAL The memory space address map used to program the FPGA and flash device is shown in Table 3 7 Note that
28. c 0 Busy Ready Set bit 0 of the Configuration Control register to logic 1 before monitoring this busy bit Flash Chip is Ready Flash Chip is Busy Table 3 11 Flash Status 2 Register Flash Read Read Only BAR2 14H A Flash Read command is executed by reading this register at base address plus 14H Prior to issue of a Flash Read the Flash Address registers must be set with the desired address to be read See the Flash Address registers at base address plus 2CH 30H and 34H The system must issue the Flash Reset command to re enable the device for reading array data if DQ5 goes high DQ5 can go high during a Flash Start Write Flash Erase Chip or Flash Erase Sector operation DQ5 can be monitored via the Flash Status 1 register at base address plus OCH Flash Reset Write Only BAR2 18H This write only register is used to initiate a reset of the flash chip A Flash Reset command is executed by writing logic 1 to bit 0 of this register at base address plus 18H Writing the flash reset command resets the chip to Acromag Inc Tel 248 295 0310 25 WWW acromag com PMC SLX150 USER S MANUAL reading data mode Flash reset can be useful when busy is held active Flash Start Write Write Only BAR2 1CH This write only register is used to initiate the write of a byte to the flash chip A Flash Start Write command is executed by writing logic 1 to bit 0 of this register at ba
29. c bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Refer to the specifications section for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the system boards plus the installed Acromag board within the voltage tolerances specified In an air cooled assembly adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering In a conduction cooled assembly adequate thermo conduction must be provided to prevent a temperature rise above the maximum operating temperature Acromag Inc Tel 248 295 0310 7 www acromag com PMC SLX150 USER S MANUAL Board Configuration Remove power from the system before installing board cables termination panels and field wiring Default Hardware Configuration The board may be configured differently depending on the application When the board is shipped from the factory it is configured as follows e Theon board flash memory device is read write enabled e The default configuration of the programmable software control register bits at power up are described in section 3 The control registers mus
30. direct electrical connection Conduction Cooled PMC mezzanine card Complies with ANSI VITA 20 Acromag Inc Tel 248 295 0310 44 www acromag com PMC SLX150 EDK Example Design USER S MANUAL 2001 R2005 The PMC SLX without a faceplate is fully compatible with a conduction cooled host card Radiated Field Immunity RFI Complies with IEC 61000 4 3 with no register upsets Conducted R F Immunity CRFI Complies with IEC 61000 4 6 with no register upsets Surge Immunity Not required for signal I O per IEC 61000 4 5 Electric Fast Transient EFT Immunity Complies with IEC 61000 4 4 Level 2 0 5KV at field I O terminals Electrostatic Discharge ESD Immunity Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge Level 2 4KV enclosure port contact discharge Radiated Emissions Meets or exceeds European Norm 61000 6 3 2007 for class B equipment Shielded cable with I O connections in shielded enclosure is required to meet compliance Xilinx XC5SLX150T 1FF1136 Resource Usage e 535 Used 184 304 Available CLB Flip Flops 1 Utilization e 505Used 92 152 Available Slice LUTs 1 Utilization e 2Used 12 Available DCM DCM CLKGENs 16 Utilization e 6 BUFG BUFGMUXs 16 Available 37 Utilization Example design tested with DCM generated clock running at 100MHz over product operation temperature User Programmable U7 FPGA VPX SLX150 Xilinx XC5SLX150T 1FF1136 e 184 304 CLB Flip Flops e 1 355Kbit
31. e to the to the Xilinx FPGA configuration flash device The location of R90 is shown in resistor location drawing in the last pages of this manual If write disable to the configuration flash is required it is recommended that the board be returned to Acromag for removal of R90 The board can be easily damaged without the use of special SMT tools Board Crystal Oscillator 125MHz Frequency Stability 0 002096 or 20ppm Dual Port SRAM PMC SLX150 or PMC SLX150E 256K x 64 bit Integrated Devices Technology IDT70T3519S133BC 133 Megahertz Speed PMC SLX150 1M or PMC SLX150E 1M 1Meg x 64 bit Integrated Devices Technology IDT70T3509MS133BP 133 Megahertz Speed Flash Memory 16M x 8 bit 128 addressable sectors of which 41 are used for FPGA Configuration Acromag Inc Tel 248 295 0310 46 www acromag com PMC SLX150 PCI Bus Interface USER S MANUAL PMC Compatibility Conforms to PCI Bus Specification Revision 3 0 and PMC Specification P1386 1 PCI X bus Master Target The board supports 32 bit or 64 bit PCI X at 100MHz 66MHz and 33MHz 4K Memory Space Required Base Address Register 0 for access to configuration registers 4M Memory Space Required Base Address Register 1 for access to Dual Port SRAM Standard Model 8M Memory Space Required Base Address Register 1 for access to Dual Port SRAM 1M Model 4M Memory Space Required Base Address Register 2 for access to the user programmable FPGA U7 Signaling 3
32. en oen nn Ha Ee aa aen re ee aT a eva erue Va dras 29 Software Reset and Status Register Read Write BAR2 8000H rrrenvrrrrnrrnnvrnernrrrnvrnesvrrsnnrsesrrrsnvrsennn 29 Rear I O Connector Read Register Read Only BAR2 802CH ccccccssecsssceeseecseceeseecssecesseecsseeeeees 30 Rear I O Connector Write Register Read Write BAR2 8030H ccccccccssscesseecsseceeseecssecesseecsseceseees 31 DMA Control Register Read Write BAR2 8034H eee eau ao aaa aaa aaa aaa aa aaa aaa aaa nhe nennen 32 FPGA SRAM Data Register Read Write BAR2 8038H and 803CH erernrnrenvrrrovrrenvrrrrrnrenvrsrrrnsenvener 32 FPGA Port SRAM Control Register Read Write BAR2 8040H rrsrnrenvrrrrrnnenvrnrevrnenvrrrrrnrenvrsssrnsenvenee 32 FPGA Port SRAM Internal Address Register Read Write BAR2 8044H ueeuaoaa aaa saaesanscansca 34 FPGA Port SRAM DMA Channel 0 1 Threshold Registers Read Write BAR2 8048H 804CH 35 FPGA Port SRAM Address Reset Registers 0 1 Read Write BAR2 8050H 8054H 36 PMC Board Identification Code Register Read Only BAR2 8058H esesaaaao iii 36 Temperature Data Register Read only BAR2 8090H rrrrnnnnnrnrrnonnrnrnnavvrnnnnnrrrsnnnnnnrnnsnvnnnnnnvnssnnnnnnee 37 DUAL PORT MEMORY 5 iere nre acid ow dzik otw owania sacada 37 BARI MEMORY MAP e 38 S
33. es including clock multiplication and division for generation of a user defined clock PLL CLK A 125MHz crystal generated clock signal FPGA_CLK_PLL is input to the FPGA for use in generation of the user defined clock signal PLL CLK The PLL_CLK can be a minimum of 10MHz and a maximum of 125MHz Since the PLL_CLK signal is generated and driven by the FPGA it will only be available after the FPGA is configured See the example VHDL file included in the engineering design kit and the Xilinx documentation on the Digital Clock Manager for more information The USERo signal is controlled via a bit 8 of the Software Reset and Status Register at BAR2 plus 8000H The USERo control bit 8 is by default set to a logic low to select the PLL_CLK clock as the board clock frequency Bit 8 set to logic high will select the 125MHz clock as the board clock frequency Bits 15 to 13 of this register will read 001 for all Acromag digital I O AXM DOx mezzanine modules These bits will read 010 when the AXM A30 high speed analog input mezzanine module is present Bits 27 and 28 are DMA acknowledgement bits and will read a logic high while the corresponding DMA channel transfer is active Bit 31 of this register when set to a logic 1 will issue a reset signal to the FPGA hardware Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 295 0310 29 www acromag com PMC SLX150 US
34. es the physical address of the board s Dual Port SRAM memory where data will be read written The DMA PMC Board Starting Address Register at PCIBARO base address plus 104H 118H is used to set the DMA channel 0 1 data starting address Writing to these registers is possible via 32 bit transfers only DMA Transfer Size Registers Read Write BARO 108H and 11CH The DMA Transfer Size Register is used to set the size of the DMA transfer that moves data between system memory and the board s Dual Port SRAM The transfer size indicates the total amount of data to transfer in units of bytes The onboard static RAM has 2 MegaByte standard model or 8 MegaByte 1M model maximum capacity As such the maximum value that can be written to this register is 1FFFFF hex standard model or 7FFFFF hex 1M model The DMA Transfer Size Register at PCIBARO base address 108H 11CH is used to set the DMA channel 0 1 data transfer size Writing to these registers is possible via 32 bit transfers only Acromag Inc Tel 248 295 0310 18 www acromag com PMC SLX150 DMA Command Registers Re USER S MANUAL ad Write BARO 10CH and 120H The DMA Command Register is used to set the priority 64 bit versus 32 bit mode Scatter Gather enable and to indicate the command to be used for the DMA transfer The Memory Read Burst command is used to program a read transfer The Table 3 6 DMA Command data is moved from system memory to the
35. g a write DMA transfer new data is applied to the bus every subsequent clock cycle until the transfer is complete During DMA transfers the address is incremented internally in the Dual Port SRAM Please refer to the IDT70T3519S133BC standard model or IDT70T3509SM 1M model Data Sheet See Related Publications for more detailed information The local bus interface between the PCI bus interface chip U5 and the user programmable FPGA U7 consists of the following signals The Local Address bus LA bits 21 to 2 are used to decode the 4M byte address space allocated by the PCI bus to BAR2 Also LA 26 bit 26 of the local address bus is logic high when the PCI bus is performing an access to BAR2 address space LBEO n LBE1 n LBE2 n and LBE3 nare the local bus byte enables LBEO n when logic low indicates that the least significant byte on data lines D7 to DO is selected for the read or write transfer Likewise LBE3 n when logic low indicates that the most significant byte on data lines D31 to D24 is selected for the read or write transfer The Local Data LD bus bits 31 to O are bi directional signals used for both read and write data transfers ADS n the address data strobe signal will pulse low for one local bus clock cycle at the start of a new read or write access The ADS n signal is driven by the PCI bus interface chip U5 Readyn must be driven low on read or write cycle by the programmable FPGA U7 and held low un
36. gic becomes the bus master to perform DMA transfers DMA Operation The PCI bus interface supports two independent DMA channels capable of transferring data to and from the on board SRAM The example design implements DMA block and demand modes of operation 64 32 16 8 bit I O Register Read Write is performed through data transfer cycles in the PCI memory space All registers can be accessed via 32 16 or 8 bit data transfers Access to Dual Port Memory can be accessed via 64 or 32 bit transfers Compatibility Complies with PCI Local Bus Specification Revision 3 0 Provides one multifunction interrupt Board is 3 3V signaling compliant 5 www acromag com PMC SLX150 USER S MANUAL The voltage provided on the PCI connector VIO pins determines the operating voltage of the PCI bus e Supply Voltage Requirement The board requires that 3 3 volts external power be provided on the 3 3 volt signal lines of the PCI bus connector Software The PMC SLX150 products will require support drivers specific to your operating system ENGINEERING DESIGN KIT Acromag provides an engineering design kit for the SLX boards sold separately a must buy for first time SLX module purchasers The design kit model PMC SLX150 EDK provides the user with the basic information required to develop a custom FPGA program for download to the Xilinx user programmable FPGA The design kit includes a CD containing schematics parts list pa
37. guaranteed to be held active a minimum of 2 clock cycles after Readyn goes active Also Rdyack n will not pulse active sooner than 2 LCLK FPGA CLK clock cycles after Readyn goes active Both LCLK and FPGA CLK are driven by the same zero delay Cypress clock driver Signal ADS n is driven by an OLogic register using the LCK at the bus interface FPGA ADS n is received at the programmable FPGA using FPGA CLK at an ILogic register This interface is considered synchronous to the LCLK FPGA CLK by Acromag CIk the local bus clock as seen in the following timing diagrams can be one of two sources By default clk is a Digital Clock Manager DCM generated clock frequency Clk can also be selected directly from the board 125MHz frequency The Local bus clk signal is controlled by USERo The board clock is routed to the Dual Port SRAM and user programmable FPGA U7 using a low skew clock driver Cypress CY23EP05 The on board 125MHz crystal oscillator is input to the user programmable FPGA via signal FPGA CLK PLL After the user programmable FPGA U7 is configured an FPGA DCM generated clock signal PLL CLK is selected as the board clock the default condition By setting bit 8 of the Software Reset and Status register at BAR2 plus 8000H to a logic high the 125MHz clock may be selected as the board clock By setting bit 8 to a logic low the PLL CLK becomes the board clock frequency The default state of bit 8 is logic low Acromag Inc Tel
38. iguration USER S MANUAL BAR2 BAR2 8003 Software Reset and Status Register 8000 Mezzanine Module Memory Space 802F Rear I O Connector Read Register 802C 8033 Rear I O Connector Write Register 8030 8037 DMA Control Register 8034 803B FPGA Port SRAM Register 8038 Ko Comme FPGA Port SRAM Register 803C oo eene 8043 FPGA Port SRAM Control Register 8040 2053 Address Reset Register 0 DP SRaM 8050 805B PMC SLX Board Identification Code 8058 A3 for Acromag Example Design 805F 805C 4 Not Used y 808F 808C Register 809F Not Used 8094 l Additional Mezzanine Module Space 8100 8137 v 3FFFFF Otherwise Not Used 3FFFFC This memory map reflects byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering In Big Endian the lower order byte is stored at odd byte addresses The PMC SLX150 board uses a flash configuration device to store programming information for the Xilinx FPGA The flash configuration device and FPGA are hardwired together so that during power up the contents of the configuration device are downloaded to the FPGA The flash configuration data can be reprogrammed using the PCI bus interface The following is the general procedure for reprogramming the flash memory and Acromag Inc Tel 248 295 0310 21 www acromag com PMC
39. ing 1 Interrupt Pending DMA Channel 1 Interrupt Pending Status Bit 17 must be set to 2 logic high for this bit to go active Write logic high to clear bit 0 No Interrupt Pending 1 Interrupt Pending U7 Programmable FGPA Interrupt Pending Status Bit 18 must be set to logic high for this bit to go active 0 No Interrupt Pending 1 Interrupt Pending 4 15 Not Used bits are read as logic 0 16 DMA Channel 0 Interrupt Enable 0 DMA Channel 0 Interrupt Disabled 1 DMA Channel 0 Interrupt Enabled 17 DMA Channel 1 Interrupt Enable 0 DMA Channel 1 Interrupt Disabled 1 DMA Channel 1 Interrupt Enabled 18 U7 Programmable FPGA Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled 19 31 Not Used bits are read as logic O A board pending interrupt is identified via bit O of this register Logic high on bit 0 indicates a board pending interrupt Bit O indicates a pending interrupt as long as DMA Channel 0 DMA Channel 1 or U7 Programmable FPGA interrupt pending status bits 1 2 or 3 respectively remain active A DMA channel 0 pending status can be cleared released by writing logic high to bit 1 the interrupt pending status bit Likewise writing logic high to bit 2 of this register clears DMA channel 1 pending status The U7 Programmable FPGA interrupt Pending status will pass the interrupt status Acromag Inc Tel 248 295 0310 15 WWW acromag com PMC SLX150 USE
40. ing the Flash Ready Busy status Bit 7 of the Flash Status 2 register at base address plus 10H will read as logic O when chip erase is completed Any other flash commands written to the flash chip during execution of the flash erase sector operation are ignored Note that a hardware reset during the erase sector operation will inmediately terminate the operation Flash Erase Chip Write Only BAR2 24H This write only register is used to erase the entire contents of the flash chip A flash bit cannot be programmed from logic 0 to logic 1 Only an erase chip operation can convert logic 0 back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip command must be performed A Flash Erase Chip command is executed by writing logic 1 to bit O of this register at base address plus 24H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is Acromag Inc Tel 248 295 0310 26 www acromag com PMC SLX150 USER S MANUAL accomplished by reading bit 7 of the Flash Status 2 register as logic O The system can determine the status of the erase operation by reading the Flash Ready Busy status Bit 7 of the Flash Status 2 register at base address plus 10H will read as logic O when chip erase is completed Any other flash commands written to the flash chip during execution of the flash erase chip operation will be ignored Note that a hardware reset during the chip erase
41. it 0 Stop Configuration of the Configuration Control register to logic high Clear the Xilinx FPGA of its previous configuration by setting the Configuration Control register bit 2 to logic high Read INIT as logic high Bit 1 of Configuration Status register before programming is initiated Download the Configuration file directly to the Xilinx FPGA by writing to the Configuration Data register The entire configuration file must be written to the Xilinx FPGA one byte at a time to the Configuration Data register at base address plus 08H Verify that the configuration is complete by reading DONE bit 0 of Configuration Status Register as logic high DONE is expected to be logic high immediately after the last byte of the configuration file is written to the Xilinx FPGA At each power up the configuration file will need to be reloaded into the FPGA Configuration Status Register Read Only BAR2 0000H This read only register reflects the status of configuration complete and Xilinx configuration clear bits This Configuration Status register is read at base address plus OH Table 3 8 Configuration Status Register Bits FUNCTION 0 DONE O Xilinx FPGA is not configured Xilinx FPGA configuration is complete INIT INIT is held low until the Xilinx is clear of its current 1 configuration 1 INIT transitions high when the clearing of the current Xilinx configuration is complete 2 to7 Not Used bits are
42. ls DREQO or DREQ14 active The SRAM control register method allows a DMA transfer to be initiated when an FPGA generated address counter is equal to the DMA Channel Threshold Register That is when the predetermined amount of data is available in the SRAM the hardware will automatically start a DMA transfer Acromag Inc Tel 248 295 0310 14 www acromag com PMC SLX150 USER S MANUAL Interrupt Control Status Register Read Write BARO 00H This Interrupt Control Status register at BARO base address offset OOH is used to monitor and clear pending board interrupts An interrupt can originate from the two DMA channels or U7 the user programmable FPGA All board interrupts are enabled or disabled via bit 31 of the Global Interrupt Enable register at BARO 08H Table 3 3 Interrupt Control Status Register Bit s FUNCTION When designing software This bit when set indicates a pending board interrupt It reflects a pending interrupt from DMA channel 0 or DMA drivers it is best to ear this 0 channel 1 or the U7 FPGA It will reflect this status even if the register as two 16 bit registers Board Interrupt enable bit 31 is disabled The upper 16 bits are Interrupt 0 No Interrupt Pending Control bits and the lower 16 Interrupt Pending bits are Interrupt Status DMA Channel 0 Interrupt Pending Status Bit 16 must be set to 1 logic high for this bit to go active Write logic high to clear bit 0 No Interrupt Pend
43. ly BAR2 14H ee eueaae ae aaa aaa aaa aa aa aa aaa ener aawaaa nnne nnns etta na sse e tans aeee rn assa nas 25 Flash Reset Write Only BAR2 18H srrrrronornnnnnrvrnnnnnrnrrnannrnnnnarrrnnnnnnnrsnsnnnnnnnnrsrnnennnnssssvnnnnnnnvsssnnnnnner 25 Flash Start Write Write Only BAR2 1CH cccccccccssscccssssececsssseceessesecesssececsssseceesaeeecseeseceeseeeceeaaes 26 Flash Erase Sector Write Only BAR2 20H u ccccccccceccccssssececsseseceessececsessececssseceesaeeecsseeeeeeseseceeaaes 26 Flash Erase Chip Write Only BAR2 24H ccccccccsccccssscccssssececsssceceessececsessececssseceesaeescseseeeeeseseceeaaes 26 Flash Data Register Read Write BAR2 28H eee uuu aou aaa aaa aaa aaa aaa aaa aaa aaa aaa wana nnnin 27 Flash Address 7 gt 0 Read Write BAR2 2CH eee eee ao is aaa aa aaa aaa aaa aaa ayaa trn rennen 27 Flash Address 15 gt 8 Read Write BAR2 30H nennen eher eterne enne tenis 27 Flash Address 23 216 Read Write BAR2 34H eene enhn enne 27 SYSTEM MONITOR REGISTERS U5 PCI bus eene eene eene nennen nennen he nn reno sese steer nun 28 System Monitor Status Control Register Read Write BAR2 38H 28 System Monitor Address Register Write Only BAR2 3CH rrrrrnnnrnnnnnrvrrnnnnrnrrnanvrnnnnnrsrnnnnnnnssnsnvnnnnne 28 BAR2 U7 FPGA REGISTERS eei ris tat eva iss eo oris rea ea ee Ea e
44. ment This Rear I O Connector Read register is a read only register and writing to this register has no effect on the LVDS input channels Reading from this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 295 0310 30 WWW acromag com PMC SLX150 Rear I O Connector Write Register Read Write BAR2 8030H The Rear I O Connector Write Register is used to set 16 LVDS output channels This example design has 16 channels identified in Table 3 14 fixed as LVDS output only channels Table 2 1 shows the P4 connector pins and their corresponding channel identifiers Table 3 14 Rear I O Registers Column 1 identifies the write data bit that drives the output channel listed in column 2 Column 1 also identifies the read data bit that returns the input channel listed in column 3 For example data bit 0 drives output channel 1 when written and returns channel 0 register setting when read All bits labeled Not Used will return logic 0 when read USER S MANUAL This Rear I O Connector Write register is written to set the LVDS output channels and can also be read to verify the output channel settings Reading or writing to from this register is possible via 32 bit 16 bit or 8 bit data transfers 0 WO COIN OD WM A W N R p plE E P R u 2B wIN P O 16 31 Write Read Data Register Bit Rear Connector Write Rea
45. mentioned will remain at the default value logic low USER S MANUAL The BARO registers are implemented in the PCI bus interface chip rather than the user programmable FPGA As such the user cannot change the logic functions implemented in BARO These are read write registers that are software controlled provide interrupt control status and DMA control status The Interrupt Control Status is at BARO base address plus 00H offset The DMA registers are at BARO base address plus offset 100H to 124H These registers control the transfer direction size system address and PMC addresses for DMA channels 0 and 1 PARO PSE Bit s Description 00H 31 0 Interrupt Control Status 04H 31 0 DMA Status Abort Register 08H 31 0 Global Interrupt Enable Bit 31 OCH gt FFH 31 0 Reserved 100H 31 0 DMA Channel 0 System Starting Address 104H 31 0 S 0 PMC Board Starting 108H 31 0 DMA Channel 0 Transfer Size in bytes 10CH 7 0 DMA Channel 0 Command 110H 0 DMA Channel 0 Start DMA Transfer Bit 114H 31 0 DMA Channel 1 System Starting Address 118H 31 0 Le Me 1 PMC Board Starting 11CH 31 0 DMA Channel 1 Transfer Size in bytes 120H 7 0 DMA Channel 1 Command 124H 0 DMA Channel 1 Start DMA Transfer Bit 128H gt FFFH 31 0 Reserved The Dual Port SRAM control registers at PCIBAR2 must also be used to set up a DMA Demand Mode transfer The Demand mode transfer is initiated by driving signa
46. nal addresses can be found in the Xilinx System Monitor document UG192 available from Xilinx Writing this register is possible via 32 bit data transfers The address value written to this register can be read on bits 22 to 16 of the System Monitor Status Control register at BAR2 plus 38H Table 3 12 System Monitor Address Status Register Register Map 00h Temperature 01h Vccint 02h Vccaux 20h Maximum Temperature 21h Maximum Vccint 22h Maximum Vccaux 24h Minimum Temperature 25h Minimum Vccint 26h Minimum Vccaux Acromag Inc Tel 248 295 0310 28 www acromag com PMC SLX150 USER S MANUAL BAR2 U7 FPGA REGISTERS Software Reset and Status Register Read Write BAR2 8000H This read write register is used to Software reset the board monitor the status of board interrupts and select the on board active clock as shown in Table 3 13 Bits O to 7 of this register are used to monitor the interrupt pending status of interrupts originating from the front AXM mezzanine module if present USERo CLOCK CONTROL Bit 8 of this register controls the USERo signal The USERo control signal is used to select between the 125MHz clock and the user defined clock PLL_CLK The user defined clock is defined in the example code of the Note USERo selects the Local FPGA and output on signal PLL_CLK The Digital Clock Manager of the FPGA bus clock offers a wide range of clock management featur
47. oblems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Acromag s application engineers can also be contacted directly for technical assistance via email telephone or FAX through the contact information listed at the bottom of this page When needed complete repair services are also available Acromag Inc Tel 248 295 0310 43 WWW acromag com PMC SLX150 USER S MANUAL 6 0 SPECIFICATIONS PHYSICAL Height 13 5 mm 0 531 in Stacking Height 10 0 mm 0 394 in Depth 149 0 mm 5 866 in Width 74 0 mm 2 913 in Board Thickness 2 21 mm 0 08 in Unit Weight 3 5902 0 1016 Kg POWER REQUIREMENTS Power will vary dependent on 3 3 VDC 45 Typical 700 mA Max 840 mA the application Power values 5 0 yc 5 Std Model Typical 1400 mA Max 1680 mA are given of Acromag Example Design 5 0 VDC 5 1M Model Typical 1800 mA Max 2160 mA 12 VDC 5 OmA 5V Maximum rise time of 100m 12 VDC 5 OmA seconds On Board 1 0V Power to Current Rating Spartan e EPOR Maximum available for the user programmable FPGA 1 0V 45 4A Maximum ENVIRONMENTAL Operating Temperature PMC SLX150 0 C to 70 C PMC SLX150 1M PMC SLX150E 40 C to 85 C PMC SLX150E 1M Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 100 C Non lsolated PCI bus and field commons have a
48. operation will immediately terminate the operation Flash Data Register Read Write BAR2 28H This read write register holds the data byte which is sent to the flash chip upon issuing of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Flash Address 7 gt 0 Read Write BAR2 2CH This read write register holds the least significant byte of the address to which the flash chip is written upon issue of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Flash Address 15 gt 8 Read Write BAR2 30H This read write register sets bits 15 to 8 of the address to which the flash chip is written upon issue of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Flash Address 23 gt 16 Read Write BAR2 34H This read write register sets bits 23 to 16 of the address to which the flash chip is written upon issue of a Flash Start Write command The upper 7 bits of this register are used to select Flash sectors for erasure Reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfer Acromag Inc
49. ot Applicable m No PCI bus Interface Device Acromag Representative Name Title Email Office Phone Office Fax Joseph Primeau Dir of Sales jprimeau acromag com 248 295 0823 248 624 9234 and Marketing Acromag Inc Tel 248 295 0310 48 www acromag com USER S MANUAL PMC SLX150 PMC SLX Block Diagram 21901 LdNYYILNI T 0 HO VG 21901 104LNOD Su3AIW4d 49019 MAAS MOT 21907 104LNOD 490175 YIKITALLTNU NOLLYYNDIANOD sna 19201 2012 lIg P9 JOVWIYILNI JOYIVALNI Ered o adi WOW sna Idd Idd L0 X1 S XILYIA are 9073 Tid 2012 ae TT T WYUS 1uog wna VISA 32012 Odd LOCAL BUS 21501 40 443LNI sna 19301 21901 108LNOD dNYYILNI IDVIYILNI Wvus LYOd 17Nd 119 8 X W9T AYOWIW HJDYNYW NOLLYYNDIINOD 532012 TYLIDIG HS 14 9 N v Luvds 51501 ginaow YOSNIS LdNYYILNI TOULNOD WAY JANLYYJdWIL IV 0 1 INOW sna JNINYZZJW JINYd 1NO34 AdODSdIHO OVLE WOd4 9 NYLHYdS www acromag com 46 248 295 0310 Acromag Inc Tel PMC SLX150 USER S MANUAL P C BOARD BOTTOM SIDE SHOWN a M D a o p JE 91 S cos s dd did ACROMAG USA 1018 901A 2011 m Remove R90 to disable flash write Acromag Inc Tel 248 295 0310 50 www acromag com
50. r the internal counter can be reset to a user specified value See DMA Registers for more information on these operations These features can be individually controlled through the SRAM Control Registers Acromag Inc Tel 248 295 0310 37 WWW acromag com PMC SLX150 USER S MANUAL BAR1 MEMORY MAP Static RAM Memory Read Write BAR1 000000H to 1FFFFFH Standard model BAR1 000000H to 7FFFFFH 1M model The Static RAM memory space is used to provide read or write access to on board SRAM memory This memory space allows access to the SRAM from the port on the PCI bus side of the SRAM The Static RAM device has a 256K x 64 bit memory configuration for the standard models and 1Meg x 64 bit for the 1M model Reading or writing to this memory space using DMA access is also only possible in 32 bit or 64 bit transfers The FPGA Port SRAM Register at BAR2 8038H and 803CH are provided for testing the SRAM port that links directly to the user programmable Spartan 6 FPGA Acromag Inc Tel 248 295 0310 38 www acromag com PMC SLX150 USER S MANUAL 4 0 THEORY OF OPERATION PCI INTERFACE LOGIC This section contains information regarding the design of the board A description of the basic functionality of the circuitry used on the board is also provided Refer to the PMC SLX Block Diagram shown at the end of this manual as you review this material The PCIx bus interface logic on this board provides a 100Mhz 66MHz or
51. r Connector Read Output Channels Input Channels 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Not Used Not Used Acromag Inc Tel 248 295 0310 31 www acromag com PMC SLX150 USER S MANUAL DMA Control Register Read Write BAR2 8034H The DMA Control Register is used to request a DMA Demand mode transfer The hardware signals DREQO and DREQ1 are driven active by software setting of bits O or 1 of this register to request the DMA transfer The transfer must include the Static RAM Memory as either the source or the destination For software triggered DMA bit 0 is used to request a DMA channel 0 transfer while bit 1 is used to request a channel 1 transfer The bit must be set to logic high to request a transfer Once set the bit will remain asserted until the DMA transfer has started If both bits are set simultaneously the channel 0 DMA transfer will be implemented first followed by channel 1 In a user application a data ready condition such as a memory buffer full condition can be physically tied via logic in the FPGA to the DREQO or DREQ1 FPGA signals to cause the DMA transfer to start Signals DACKO_n and DACK1_n input to the programmable FPGA from the bus interface FPGA U5 are held active during a DMA transfer These signals are not accessible via a register but can be used in custom firmware The DMA Status Abort register at BARO plus 04H
52. register bits O and 1 can be used to identify DMA transfer complete status FPGA SRAM Data Register Read Write BAR2 8038H and 803CH The FPGA SRAM Data Read Register is provided to access the SRAM port that links directly to the user programmable Spartan 6 FPGA Reading or writing BAR2 8038H accesses the SRAM least significant data lines 31 to 0 Reading or writing BAR2 803CH accesses the most significant SRAM data lines 63 to 32 Reading or writing these registers is only possible using 32 bit transfers The address for the SRAM read or write is initialized by the Dual Port SRAM Internal Address register at BAR2 8044H With each additional read or write to BAR2 803CH the address is automatically incremented Writing the SRAM would proceed by first setting the Address register at BAR2 8044H Next the least significant 32 bit data word is written to BAR2 8038H Finally after the most significant 32 bit data word is written at BAR2 803CH the address is automatically incremented FPGA Port SRAM Control Register Read Write BAR2 8040H This read write register is used to control the Dual Port SRAM including enabling write automatic DMA transfer and automatic address reset on DMA thresholds The default power up state of this register is logic low A reset will set all bits in this register to O Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 295 0
53. rt location drawing example VHDL source and other utility files The SLX modules are intended for users fluent in the use of Xilinx FPGA design tools BOARD DLL CONTROL SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows 2000 XP Vista 7 applications accessing Acromag PMC XMC and VPX I O board products PCI and PCIe I O Cards and CompactPCI I O Cards This software Model PCISW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLs that are compatible with a number of programming environments including Visual C Visual Basic NET and others The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers BOARD VxWORKS SOFTWARE Acromag provides a software product sold separately consisting of board VxWorks software This software Model PMCSW API VXW is composed of VxWorks real time operating system libraries for all Acromag PMC XMC and VPX I O board products PCI and PCle I O Cards and CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag Inc Tel 248 295 0310 6 WWW acromag com PMC SLX150 BOARD Linux SOFTWARE USER S MANUAL Acromag provides a software product consisting of board Linux soft
54. se address plus 1CH Prior to issuing of a Flash Start Write the Flash Data and Address registers must be set with the desired data and address to be written See the Flash Data and Address registers at base address plus 28H 2CH 30H and 34H Issuing a Flash Start Write will automatically increment this address after the previously issued Flash Write has completed Thus the address will not need to be set prior to issuing the next Flash Start Write if consecutive addresses are to be written Flash Erase Sector Write Only BAR2 20H A Flash Erase Sector command is executed by writing logic 1 to bit O of this register at base address plus 20H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is accomplished by reading bit 7 of the Flash Status 2 register as logic O There are 128 flash sectors which are addressed via the most significant seven flash address lines The most significant seven flash address lines are set via the Flash Address 23 16 register at base address plus 34H Issuing a Flash Erase Sector command will erase the contents of the flash chip only in the sector specified A flash bit cannot be programmed from logic 0 to logic 1 Only an erase chip operation can convert logic O back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip or Flash Erase Sector command must be performed The system can determine the status of the erase operation by read
55. srnvenennee 17 DMA System Starting Address LSB Registers Read Write BARO 100H and 114H 18 DMA System Starting Address MSB Registers Read Write BARO 104H and 118H 18 DMA Transfer Size Registers Read Write BARO 108H and 11CH suueeeu aaa aaa ananas nazwana asaaaaenana 18 DMA Command Registers Read Write BARO 10CH and 120H ccccccecsseceeseecsseceeseecsseceeseeesseeeeeees 19 Acromag Inc Tel 248 295 0310 1 www acromag com PMC SLX150 USER S MANUAL BAR2 MEMORY MAP suisse R 20 Elash Gontlguration eroe eoe edle Aakre brest GA 21 Direct PCle bus to Xilinx Configuration arrrnrrnanannnnrrrnronsnonannrrrnrnnsnnnannrnnnrnssnanannrnnsrnssennnrnnsensssssennnnnsensene 23 Configuration Status Register Read Only BAR2 0000H ees uuu aaa aaa aaa aaa ener nne 23 Configuration Control Read Write BAR2 04H uu eee uses ua aaa aaa aaa anawa aaa aaa aa nre nnne ens 24 Configuration Data Write Only BAR2 08H u u eee euaa aaa aaa aa aaa aaa aaa aa waza aa nnnn entren th nasse anna nnne 24 Flash Status 1 Read Only BAR2 OCH ccccccccsssccceessececsessececsssseceessececesssececsseseceesaeeecssseceesaeeeceeaaes 25 Flash Status 2 Read Only BAR2 10H ereronnnornnnnarvrnnnnnrnrrnnnnrnnnnarsrnnnnnnnrsnsnnnnnnnnrvrnnnnnnnssssvnnnnnnnvsssnnnnnner 25 Flash Read Read On
56. t DMA FPGA Port SRAM DMA Channel 0 1 Threshold Registers Reset Values Threshold Registers Reset D30 D18 standard D17 DO standard model Values Register D30 D20 1M D19 DO 1M model om 1FFFFH standard model Channel 0 T Threshold Not Used Read as logic 0 Reg 7FFFFH 1M model DMA Channel 1 Threshold Reg 3FFFFH standard model Not Used Read as logic 0 FFFFFH 1M model Acromag Inc Tel 248 295 0310 35 WWW acromag com PMC SLX150 USER S MANUAL FPGA Port SRAM Address Reset Registers 0 1 Read Write BAR2 8050H 8054H WARNING The DMA Ch 0 Threshold Register must not equal the Address Reset Register 0 and the DMA Ch 1 Threshold Register must not equal the Address Reset Register 1 If these registers are equal and the address reset is enabled via the FPGA Port SRAM Control Register an infinite loop will be created within the internal logic of the FPGA The FPGA Port SRAM Address Reset Registers are used to reset the internal address counter to a user defined value immediately upon reaching the DMA Threshold value For example after an SRAM write cycle where the internal address counter is equal to the value defined in the DMA Channel 0 Threshold Register the internal address counter will then be loaded with the value defined in the Address Reset Register O Similarly after a SRAM write cycle where the internal address counter is equal to the val
57. t be programmed to the desired configuration before starting data input or output operation Front Panel Field I O Connector The front panel connector provides the field I O interface connections via optional mezzanine I O modules purchased separately Rear P4 Field I O Connector The rear I O P4 connector connects directly to the user programmable FPGA The VCCO pins are powered by 2 5 volts and thus will support the 2 5 volt lOStandards The IOSTANDARD attribute can be set in the user constraints file UCF For example rear I O can be defined for LVCMOS25 low voltage CMOS The example design defines the rear I O to LVDS 25 Low Voltage Differential Signaling in the user constraints file The 2 5 volt IOStandards available are listed in table 6 39 of the Spartan 6 User Guide available from Xilinx The example design defines the rear I O connector with 32 LVDS I O pairs The LVDS pairs are arranged in the same row in table 2 1 For example RIOO P and RIOO N form a signal pair The P identifies the Positive input while the N identifies the Negative input Acromag Inc Tel 248 295 0310 8 WWW acromag com PMC SLX150 USER S MANUAL Table 2 1 Board Rear Field I O Ch Positive Pin Description Pin Negative Pin Description Pin Pin Connections 0 RIOO P 3 1 RIOLP 4 The example design implements 3 RIO2 P 7 2 5volt LVDS I O to the rear 3 RIO3_P 16 RIO3N 8 connector Signal Pars are 4 RIO4P 19
58. t com http www cypress com 1 0 GENERAL INFORMATION Ordering Information Table 1 1 The PMC SLX boards are available in both standard and extended temperature ranges with an option of memory The re configurable PMC SLX modules use the Xilinx Spartan 6 XC6SLX150 FPGA Re configuration of the FPGA is possible via a direct download into the Xilinx FPGA over the PCI bus In addition on board flash memory can be loaded with FPGA configuration data for automatic Xilinx configuration on power up Flash programming is also implemented over the PCI bus Acromag provides an example design that includes an interface to the user rear I O and front I O connectors The example design also includes an interface to the SRAM with DMA hardware support The following table list the orderable models and their corresponding operating temperature range Model PMC SLX150 is an air cooled with front or rear I O or conduction cooled product with only rear I O Model PMC SLX150E is an extended temperature air cooled or conduction cooled product The conduction cooled product only support rear I O OPERATING MODEL Dual Mn TEMPERATURE RANGE PMC SLX150 256K x 64 bit EE PMC SLX150E 256K x 64 bit AC to 485 C PMC SLX150 1M 1M x 64 bit CER PMC SLX150E 1M 1M x 64 bit 40 to 485 C Acromag Inc Tel 248 295 0310 4 www acromag com PMC SLX150 Key Features PCI Interface Features Acromag Inc Tel 248 295 0310
59. tatic RAM Memory Read Write BAR1 000000H to 1FFFFFH Standard model 38 BAR1 000000H to 7FFFFFH 1M model ea aaa aaa east 38 4 0 THEORY OF OPERATION sicccicsssiaisicsstadsncscccctacnveddecvaetdsctuastadineacadetatuanietcsavistecnsetasineses I PCIEINTERFACE EOGIC rito Ni RE ERE ai rick ai RERO ala dade 39 SYNCHRONOUS Dual Port SRAM e uueeee e naa aaa aa aa aa aaa aaa tnra annis ener tiras aside arena nana sa sess etta ta gas s ass naa 39 LOCalEBUS SIgNAIS ii ett tete eer tae WW tee ear ere eee ee Z RN Reds 40 Acromag Inc Tel 248 295 0310 2 WWW acromag com PMC SLX150 USER S MANUAL Local B s CLOCK CONTRODL eret a dioda A e eee rr o E PUE EE EE a A EE PEE EET FERRE EUN Rd 41 5 0 SERVICE AND REPAIR iii a id a a aa 4O Service and Repair Assistance sis 2342 oro wii Ga O en 43 Preliminary Service Procedure nio a oil Aaaa wdw 43 Where to Get Heparin 43 PHYSICAL EIC EAM 44 POWER REQUIREMEN TS rtr EREXIT E NER ARP OW ERR URS ERR 44 ENVIRONMENTAL ED 44 EDKiExample D6SIBhi m since em dec e kin ek ee eee 45 FPGAS VPXESEX ASO 22 eni iiti niano ebbe reno alnus 45 REAR ALO ices Cua EE 46 FRONTO eee seems 46 Write Disable Jump ruuanussaslansersb r PoE ue DR eee saia caido DEUSA an 46 D al Port SRAM arena 46 El sh MemoOrFys iid t rite E TA ti ER E E ARE OH Al ha ede e 46 PCI Busl terface RAPI 47 Certificate of Volatility iiie oi eI
60. th the user programmable Xilinx FPGA code stored in flash memory Upon power up the PMC SLX150 will automatically configure the FPGA with the example design code stored in flash As a first step become familiar with the PMC SLX150 with the example code supplied by Acromag The board will perform all the functions of the example design as described in this manual The Example Design Memory Map section gives a description of the I O operations performed by the example design It will allow testing of digital I O interrupts read write of dual port SRAM and testing of both DMA channels It is strongly recommended that you become familiar with the board features by using the example design as provided by Acromag CAUTION Do not attempt to reconfigure the flash memory until after you have tested and become familiar with the PMC SLX150 as provided in the example design After you are familiar with the PMC SLX150 and have tested it using the example design you can move on to step 2 Here you will modify the example design VHDL code slightly It is recommended that you test this modified example design using the reconfiguration direct method It is not recommended that the flash be overwritten until you have tested your code The reconfigure direct method will allow programming of the FPGA directly from the PCI bus If for some reason the PMC SLX150 does not perform as expected you can power the PMC SLX150 down Upon power up the example design pro
61. the base address for the board BAR2 in memory space must be added to the addresses shown to properly access these registers Register accesses as 32 16 and 8 bit transfers in memory space are permitted All addresses in BAR2 from O to 7FFF hex are fixed and cannot be changed by the user via the programmable Spartan 6 FPGA BAR2 Addr 0003 0007 000B 000F 0013 0017 001B 001F 0023 0027 002B 002F 0033 0037 003B 003F 0043 7FFF D31 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used D08 DO7 DOO Configuration Status Register Configuration Control Register Configuration Data Flash Status 1 Register Flash Status 2 Register Flash Read Flash Reset Flash Start Write Flash Erase Sector Flash Erase Chip Flash Data Register Flash Address 7 50 Flash Address 15 58 Flash Address 23 516 PCle bus FPGA System Monitor Status Control Register PCle bus FPGA System Monitor Address Register Not Used Not Used Not Used BAR2 Addr 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 0038 003C 0040 4 7FFC Acromag Inc Tel 248 295 0310 20 www acromag com PMC SLX150 Table 3 7 Example Design BAR2 Memory Map 1 The board will return 0 for all addresses that are Not Used Flash Conf
62. til Rdyack n is driven low by the PCI bus interface chip U5 This is shown on the read and write diagrams that follow Rdyack n is driven low by the PCI bus FPGA U5 to signify the end of the read or write cycle The LW R nsignal when logic high indicates a write transfer in which data is moving from the PCI bus to the reprogrammable FPGA U7 This signal Acromag Inc Tel 248 295 0310 40 WWW acromag com PMC SLX150 Local Bus CLOCK CONTROL USER S MANUAL when logic low indicates a read transfer in which data is moving from the reprogrammable FPGA U7 to the PCI bus The PCI bus FPGA is always the local bus master The programmable FPGA is always the local bus slave There are no other devices on the local bus so bus arbitration is not required The PCI bus FPGA will drive ADS n active low at the start of a bus access and the LW R n signal identifies the read or write access The programmable FPGA drives READYn active low to accept write data or to validate read data places on the data bus LD The PCI bus FPGA will respond with RdyACKn low and the programmable FPGA can stop driving READYn For a read cycle the LD data signals should be driven active prior to driving Readyn active LD and Readyn should be held active until Rdyack n is detected active The LA LBEO n LBE1 n LBE2 n LBE3 n LD LW R nsignals are guaranteed setup at least 2 LCLK FPGA CLK clock cycles before signal ADS n goes active These signals are also
63. trol Registers before writing to the DP SRAM Internal Address Register Table 3 17 FPGA Port SRAM Internal Address Register The FPGA Port SRAM Internal Address Register is used to view and set the internal SRAM address The FPGA will only write using 64 bit data transfers allowing for 3FFFF hex standard model or FFFFF hex 1M model unique memory accesses Reading this register will return the internal SRAM address Due to delays during data processing and the PCI transfer the actual internal address may be slightly greater than the address read Writing to this register will set the Internal SRAM Address to the provided value Bits O to 17 of this register are used on the standard model while bits 0 to 19 are used for the 1M model Writing logic 1 to bit 31 of this register or a system reset will cause the Internal SRAM Address to reset to 00000H the start of the SRAM memory Reading or writing to this register is possible via 32 bit data transfers only The SRAM Internal Address will automatically be incremented upon a write or read of the most significant SRAM Data Port at BAR2 803CH FPGA Port SRAM Internal Address Register D30 D18 standard D17 DO standard model D31 D30 D20 1M D19 DO 1M model SRAM Internal Nor Used Read as logic SRAM Internal Address Address Reset 0 Acromag Inc Tel 248 295 0310 34 www acromag com PMC SLX150 USER S MANUAL FPGA Port SRAM DMA Channel
64. ue defined in the DMA Channel 1 Threshold Register the internal address counter will then be loaded with the value defined in the Address Reset Register 1 This allows for the internal address counter to be changed without any interruption in the transfer of data from the front connector input to the DP SRAM This feature must be enabled via bits 3 and 4 for Channel 0 amp 1 thresholds respectively of the FPGA Port SRAM Control Register Note that the DMA transfers do not have to be enabled for this feature to function Reading of either register will return the corresponding internal address reset value Writing this register will set the corresponding internal address reset register to the provided value Bits O to 17 of this register are used on the standard model while bits O to 19 are used for the 1M model The most significant bits are not used and will return logic 0 when read A system reset will cause these registers to reset to 00000H PMC Board Identification Code Register Read Only BAR2 8058H Acromag Inc Tel 248 295 0310 The PMC Board Identification Code register at BAR2 plus 8058H stores an ID code that can used to uniquely identify the PMC Spartan 6 card This register will read A3 hex as provided by the Acromag example design The user can change the hardware setting of this register in the programmable FPGA code This ID code can be used to properly assign software drivers to multiple PMC boards that may have the
65. vided by Acromag will again be loaded into the FPGA See the Direct PCI bus to Xilinx Configuration section for a description of the steps required to perform reconfiguration directly from the PCI bus The registers provided in the FPGA Programming Memory Map are used to implement a direct reconfiguration 10 www acromag com PMC SLX150 USER S MANUAL 3 After you have thoroughly tested your customized FPGA design you can erase the flash and write your application code to flash Once the flash is erased you will not be able to go back to the example design by simply powering down and restarting the board See the Flash Configuration section for a description of the steps required to write new data or to reprogram the example design code to the flash device The registers provided in the FPGA Programming Memory Map are used to implement a flash erase and reprogram operations PCI CONFIGURATION ADDRESS SPACE This board is a PCI Specification version 3 0 compliant PCI bus master target board The PCI bus is defined to address three distinct address spaces I O memory and configuration space This board can be accessed via the PCI bus memory and configuration spaces The card s configuration registers are initialized by system software at power up to configure the card The board is a Plug and Play PCI card As a Plug and Play card the board s base address and system interrupt request line are not selected via jumpers but are
66. ware This software Model PMCSW API LNX is composed of Linux libraries for all Acromag PMC XMC and VPX I O board products PCI and PCIe I O cards and CompactPCI I O cards The software supports X86 PCI bus only and is implemented as library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards 2 0 PREPARATION FOR USE Unpacking and Inspecting af U GAUTION SENSITIVE ELECTRONIC DEVIGES DO N T SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNING This board utilizes static sensitive components and should only be handled at a static safe workstation Card Cage Considerations Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti stati

PMC-SLX150 / PMC-SLX150-1M User`s Manual

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