ChipS12 V1.11 User Manual
Contents
1. include datatypes h include lt mc9s12dp512 h gt include s12 atd h Func Initialize ATD module Args Retn void initATDO void enable ATD module ATDOCTL2 BM_ADPU 10 bit resolution clock divider 12 allows ECLK 6 24MHz 2nd sample time 2 ATD clocks ATDOCTL4 BM PRS2 BM PRSO Func Perform single channel ATD conversion Args channel 0 7 Retn unsigned left justified 10 bit result UINT16 getATDO UINT8 channel select one conversion per sequence ATDOCTL3 BM S1C right justified unsigned data mode perform single sequence one out of 8 chamels ATDOCTL5 BM DJM channel amp 0x07 wait until Sequence Complete Flag set CAUTION no loop time limit implemented while ATDOSTATO amp BM SCF 0 read result register return ATDODRO 16 User Manual Indicator LED Port pin PE7 drives a single indicator LED D1 To control this LED some simple macros can be used as shown in the following C header file ifndef __CHIPS12_LED_H define CHIPS12 LED H Macros define initLED PORTE 0x80 DDRE 0x80 define offLED PORTE 0x80 define onLED PORTE amp 0x80 define toggleLED PORTE 0x80 Function Prototypes2. module contains no code endif __CHIPS12_LED_H RS232 Interface The MC9S12Cxx contains an asynchronous serial interface SCIO including one receive line and one transmit line RXDO TXD0 Handshake lines are not provided by the SCI module they can be added by using general purpose I O port lines if reguired On the ChipS12 the SCI signal lines are connected to an RS232 transceiver circuit IC2 If the RS232 interface 1s not needed in an application the output RIOUT of IC2 can be tri stated by connecting contacts 2 3 of solder bridge BR2 As a conseguence the MCU signals PSO and PS1 can be used as additional general purpose I Os To reduce current consumption IC2 can be brought into suspend mode by setting the solder bridge BR3 to position 2 3 Now MCU signal PE4 can be used to control the SHDN input of the RS232 transceiver chip Low level activates power saving suspend mode Please note PE4 can be configured as clock output ECLK by software Avoid doing so while PE4 is used for suspend control 17 ChipS12 The following code example shows how to use SCIO in polling mode include datatypes h include mc9s12dp512 h include s12 sci h void initSCIO UINT16 bauddiv SCIOBD SCIOCR1 0 SCIOCR2 BM_TE BM_RE BOOL testSCIO void if SCIOSR1 amp BM RDRF return TRUE UINT8 getSCIO void while SCIOSR1 amp BM_RDRF return SCIODRL
3. ChipS2 Hardware Version 1 11 User Manual May 30 2008 ChipS12 Copyright C 2003 2008 by ELMICRO Computer GmbH amp Co KG Hohe Str 9 13 D 04107 Leipzig Germany Tel 49 0 341 9104810 Fax 49 0 341 9104818 Email leipzig elmicro com Web http elmicro com This manual and the product described herein were designed carefully by the manufacturer We have made every effort to avoid mistakes but we cannot guarantee that it is 100 free of errors The manufacturer s entire liability and your exclusive remedy shall be at the manufacturer s option return of the price paid or repair or replacement of the product The manufacturer disclaims all other warranties either expressed or implied including but not limited to implied warranties of merchantability and fitness for a particular purpo se with respect to the product including accompanying written material hardware and firmware In no event shall the manufacturer or its supplier be liable for any damages whatsoever including without limitation damages for loss of business profits business interruption loss of business information or other pecuniary loss arising out of the use of or inability to use the product even if the manufacturer has been advised of the possibility of such damages The product is not designed intended or authorized for use in applications in which the failure of the product could create a situation where personal injury or death ma
4. 16KB Flash equals Page 3D 1000 3FFF with 12KB of it visible the lower 4KB are hidden by RAM and Control Registers 4000 7FFF 16KB Flash equals Page 3E 16KB Flash Page 38 2000 SBEFE Page 38 3F selectable using PPAGE 16KB Flash equals Page 3F C000 SFFFF TwinPEEKs uses the top 4KB old board version no longer available 33 ChipS12 11 Carrier Board Plan Parts Location 900000000000 Ko Yo Ko Wo Ko No Ko No Ko Ko Ko Ko o Mo Mo Mo Mo Mo Wo Wo Ko Wo Mo Wo o Ko Ko Ko Ko Mo Ko No No Ko No No o Mo Ko Wo Mo te Ko Wo Ko No No No o Ko Mo Wo No Mo Mo Mo Wo Ko Wo Wo o No Mo No Ko Ko No No Wo Wo o o Mo Wo Ko Ko Wo Wo Wo Ko 0 KG Mo Wo Mo Ko No Wo No No Wo Wo o KG No WG Wo Mo No Ko Wo Wo Wo Wo o No No No Ko Ko No No No No No WO o fe No No No No No Ko No Ko No No 0 NG No Wo Ko No te Wo Wo Wo Wo Wo o NG Wo No Wo Wo No No Wo Wo NG Bei 0 Ko No Wo No No No No No No NG Wo Mo Mo Ko No No NG Ko Wo Wo Wo NG Wo Mo Mo Ko Ko No No No No No Wo No Wo 000000000000 000000000000 Ee Me y o Ko Mo No No No 000000 0 Ko Ko No Ko Ko Ko Ko Wo Mo Wo Wo WI o No Ko No No No 000000 0 No Mo No No No No Wo Wo No Wo Wo e Ko o OO e He O fif III OI Wi IRI 006 um o Ko No Wo Wo Se Ad 34 User Manual Jumpers and Connectors ChipS12 supply voltage VCC 3 3V Icc lt 0 1A ChipS12 supply voltage VCC 5V J1 not Connection so
5. destination address CANOTXFG 1 canid amp Oxe0 CANOTXFG 4 c CANOTXFG 12 1 one byte data CANOTXFG 13 0 priority 0 highest CANOTFLG BM TXEO initiate transfer 24 User Manual 8 Application Hints Behaviour after Reset As soon as the reset input of the microcontroller is released the MCU reads the Interrupt Vector at memory address FFFE F and then jumps to the address found there In the default delivery condition of the ChipS12 the Flash module of the MCU contains the TwinPEEKs Monitor Program The reset vector points to the start of this Monitor Software As a result the monitor will start immediately after reset Startup Code Every Microcontroller firmware starts with a number of hardware initialization commands For the ChipS12 only setting up the stack pointer is crucial While it was important for HC12 derivatives to disable the Watchdog the COP Watchdog of HCS12 devices is already disabled out of reset Additional Information on the Web Additional information about the ChipS12 Controller Module will be published on our Website as it becomes available http elmicro com en chips12 html 25 ChipS12 9 TwinPEEKs Monitor Software Version 2 3 Serial Communication TwinPEEKs communicates over the RS232 interface using a line speed of 19200 Baud Settings are 8N1 no hardware or software hand shake no protocol Autostart Function A
6. EC OK StartIIC if sendIIC SEEP DEVICE ID IIC WRITE IIC ACK 20 User Manual SEEP_ErrorCode SEEP_EC_NOTRDY else if sendIIC UINT8 addr gt gt 8 amp 0x7f IIC ACK SEEP_ErrorCode SEEP_EC_ADDRERR else if sendIIC UINT8 addr IIC ACK SEEP_ErrorCode SEEP_EC_ADDRERR else restartIIC if sendIIC SEEP DEVICE ID IIC READ IIC ACK SEEP ErrorCode SEEP EC RDERR else b receiveIIC IIC NOACK StopIIC if SEEP ErrorCode SEEP EC OK return SEEP ErrorCode return b INT16 pokeSEEP UINT16 addr UINT8 bval SEEP ErrorCode SEEP EC OK startIIC if sendIIC SEEP_DEVICE_ID IIC_WRITE IIC_ACK SEEP_ErrorCode SEEP_EC_NOTRDY else if sendIIC UINT8 addr gt gt 8 0x7f IIC_ACK SEEP_ErrorCode SEEP_EC_ADDRERR else if sendIIC UINT8 addr IIC ACK SEEP_ErrorCode SEEP_EC_ADDRERR else if sendIIC bval IIC ACK SEEP_ErrorCode SEEP_EC_WRERR StopIIC return SEEP ErrorCode dT INT16 getLastErrSEEP void return SEEP ErrorCode 21 ChipS12 Real Time Clock The ChipS12 can be optionally equipped with a R2051 Real Time Clock RTC from Ricoh This chip has an IIC interface and provides time reference and calendar information Interrupts can be generated by the R2051 in different ways The periodic interrupt system is configured to generate interrupt signals with a user selectab
7. MHz by default To realize higher bus clock rates the PLL has to be engaged The MC9S12Cxx can be operated with a bus speed of up to 25MHz though most designs use 24MHz because this value is a better basis to generate a wide range of SCI baud rates A passive external loop filter must be placed on the XFC pin The filter R3 C3 C4 is a second order low pass filter to eliminate the VCO input ripple The value of the external filter network and the reference frequency determines the speed of the corrections and the 13 ChipS12 stability of the PLL If PLL usage is not required the XFC pin should be pulled up to VDDPLL level The choice of filter component values is always a compromise over lock time and stability of the loop 5 to 10kHz loop bandwidth and a damping factor of 0 9 are a good starting point for the calculations With a quartz frequency of 16MHz and a desired bus clock of 24MHz a possible choice is R3 4 7k and C3 22nF C4 should be approxi mately 1 20 1 10 x C3 e g 2 2nF in our case These values are suitable for a reference frequency of 1MHz Note to be defined in example file S12_CRG H The according reference divider register value is REFDV 15 and the synthesizer register setting becomes SYNR 23 Please refer to the chapter XFC Component Selection in the MC9S12DP256B Device User Guide for detailed description of how to calculate values for other system configurations The following source listing sh
8. void putSCIO UINT8 c while SCIOSR1 amp BM TDRE SCIODRL c bauddiv amp Oxlfff baudrate divider has 13 bits mode 8N1 Transmitter Receiver enable 0 return FALSE 18 User Manual SPI Bus The MC9S12C128 contains one SPI module SPIO which can be used for synchronous serial communication with external SPI chips SPIO consists of four individual signals MISO MOSI SCK and ISS MCU port pins PM2 PMS These signals are not used on board the ChipS12 They can be accessed at connector X0 The following listing demonstrates some basic functions initializa tion 8 bit data transfer for the SPI Port SPIO chip select signal handling not included include datatypes h include lt mc9s12dp512 h gt include s12 spi h Code void initSPIO UINT8 bauddiv UINT8 cpol UINT8 cpha set SS SCK MOSI lines to Output DDRM 0x38 for HCS12C Series DDRS Oxe0 for HCS12D Series SPIOBR bauddiv set SPI Rate enable SPI Master Mode select clock polarity phase SPIOCR1 BM SPE BM MSTR cpol BM CPOL 0 cpha BM CPHA 0 SPIOCR2 0 as default UINT8 xferSPIO UINT8 abyte while SPIOSR amp BM SPTEF 0 wait until transmitter available SPIODR abyte start transfer while SPIOSR amp BM SPIF 0 wait until transfer finished return SPIODR read
9. 6 FF88 FF8A FF8C FF8E FF90 FF92 FF94 FF96 FF98 FF9A FF9C FF9E FFAO FFA2 FFA4 FFA6 FFA8 FFAA FFAC FFAE FFBO FFB2 FFB4 FFB6 FFB8 FFBA FFBC FFBE FFCO FFC2 FFC4 FFC6 FFC8 FFCA FFCC FFCE FFDO FFD2 FFD4 FFD6 FFD8 FFDA FFDC FFDE FFEO FFE2 FFE4 FFE6 FFE8 FFEA FFEC FFEE FFFO FFF2 FFF4 FFF6 FFF8 FFFA FFFC FFFE 0F43 OF46 OF49 OF4C OF4F OF52 OF55 OF58 OF5B OF5E OF61 OF64 OF67 OF6A OF 6D OF70 0F73 OF76 OF79 OF7C OF7F OF82 OF85 OF88 OF8B OF8E OF91 WIER OF97 OF9A OF9D OFAO OFA3 OFA6 OFA9 OFAC OFAF OFB2 OFB5 OFB8 OFBB OFBE OFC1 OFC4 OFC7 OFCA OFCD OFDO OFD3 OFD6 OFD9 OFDC OFDF OFE2 OFES DEES DEER DEER OFF1 OFF4 OFF7 OFFA OFFD F000 dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc d dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc S SS ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss ss sg TP RAMTOP 189 TP RAMTOP 186 TP RAMTOP 183 TP RAMTOP 180 TP RAMTOP 177 TP RAMTOP 174 TP RAMTOP 171 TP RAMTOP 168 TP RAMTOP 165 TP RAMTOP 162 TP RAMTOP 159 TP RAMTOP 156 TP RAMTOP 153 TP RAMTOP 150 TP RAMTOP 147 TP RAMTOP 144 TP RAMTOP 141 TP RAMTOP 138 TP RAMTOP 135 TP RAMTOP 132 TP RAMTOP 129 TP RAMTOP 12
10. 6 TP RAMTOP 123 TP RAMTOP 120 TP RAMTOP 117 TP RAMTOP 114 TP RAMTOP 111 TP RAMTOP 108 TP RAMTOP 105 TP RAMTOP 102 TP RAMTOP 99 TP RAMTOP 96 TP RAMTOP 93 TP RAMTOP 90 TP RAMTOP 87 TP RAMTOP 84 TP RAMTOP 81 TP RAMTOP 78 TP RAMTOP 75 TP RAMTOP 72 TP RAMTOP 69 TP RAMTOP 66 TP RAMTOP 63 TP RAMTOP 60 TP RAMTOP 57 TP RAMTOP 54 TP RAMTOP 51 TP RAMTOP 48 TP RAMTOP 45 TP RAMTOP 42 TP RAMTOP 39 TP RAMTOP 36 TP RAMTOP 33 TP RAMTOP 30 TP RAMTOP 27 TP RAMTOP 24 TP RAMTOP 21 TP RAMTOP 18 TP RAMTOP 15 TP RAMTOP 12 TP RAMTOP 9 TP RAMTOP 6 TP RAMTOP 3 main Please note the actual vector usage depends on the particular HCS12 derivative see Device Guide reserved reserved reserved reserved reserved reserved PWM Emergency Shutdown Port P CANA transmit CANA receive CANA errors CANA wake up CAN3 transmit CAN3 receive CAN3 errors CAN3 wake up CAN2 transmit CAN2 receive CAN2 errors CAN2 wake up CAN1 transmit CAN1 receive CANT errors CAN1 wake up CANO transmit CANO receive CANO errors CANO wake up FLASH EEPROM SPI2 SPI1 ANG BDLC Self Clock Mode PLL Lock Pulse Accu B Overflow MDCU Port H Port J ATD1 ATDO SCIL SCIO SPIO Pulse Accu A Input Edge Pulse Accu A Overflow Timer Overflow TC7 TC6 CS TC4 TC3 TOZ TCL TCO RTI IRQ XIRQ SWI Illegal Opcode COP Fail Clock Monitor Fail Reset 28 User Manual Usage A TwinPEEKs command is comprised by a single
11. A VSSA The nominal operating voltage designated as VCC in the schematic diagram of the MC9S12C128 is in the range of 3V to 5V Internally the MCU uses a core voltage of only 2 5V The necessary voltage regulator is already included in the chip as well as I O buffers for all general purpose input output pins Therefore the MCU behaves like a 5V or 3 3V device from an external point of view There is just one exception the signals for oscillator and PLL are based on the core voltage and must not be driven by an external voltage The three terminal pairs mentioned above must be decoupled carefully A ceramic capacitor of 100nF is connected directly at each pair C15 C16 C17 plus an additional 10uF tantalum capacitor C5 Special care must be taken with VDDA since this is the reference point for the internal voltage regulator 11 ChipS12 The internal core voltage appears at the pin pairs VDD1 VSS1 and VDDPLL VSSPLL in order to allow adding decoupling capacitors here as well C7A C7B C14 A static current draw from these terminals is not allowed This is especially true for VDDPLL which serves as the reference point for the external PLL loop filter combination R3 C3 C4 There are two MCU pins VRH VRL to define the upper and lower voltage limits for the internal analog to digital ATD converter While VRL is grounded VRH is connected to VDDA via solder bridge BRI C18 is used for decoupling VRH can be supplied exter
12. IDAC 0x10 set up acceptance filter and mask register 1 1 eee 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 IDO RTR IDE xxx XXX XXX AU we are going to detect data frames with standard identifier 11 bits only so bits RTR bit4 and IDE bit3 have to be clear CANOIDARO idar 8 top 8 of 11 bits CANOIDAR1 idar amp 0xe0 remaining 3 of 11 bits CANOIDMRO idmr 8 top 8 of 13 bits CANOIDMR1 idmr amp Oxe0 0x07 remaining 3 bits RTR IDE set up acceptance filter and mask register 2 3 4 just as 1 CANOIDAR6 CANOIDAR4 CANOIDAR2 CANOIDARO 23 ChipS12 CANOIDAR7 CANOIDARS CANOIDAR3 CANOIDAR1 CANOIDMR6 CANOIDMR4 CANOIDMR2 CANOIDMRO CANOIDMR7 CANOIDMR5 CANOIDMR3 CANOIDMR1 CANOCTLO amp BM INITRQ exit Init Mode while CANOCTL1 amp BM_INITAK 0 wait until Normal Mode is established CANOTBSEL BM TX0 use only TX buffer 0 Le tasi m ae aa EE BOOL testCANO void if CANORFLG amp BM_RXF 0 return FALSE return TRUE Ji UINT8 getCANO void UINT8 c while CANORFLG amp BM_RXF 0 wait until CAN RX data pending c CANORXFG 4 save data CANORFLG BM_RXF clear RX flag Teturn c void putCANO UINT16 canid UINT8 c while CANOTFLG amp BM TXEO 0 7 wait until Tx buffer released CANOTXFG 0 canid gt gt 8
13. U controls suspend mode of IC2 disable reset by RTC VDCC output of RTC IC6 not in use VDCC output of RTC connected to RESET provides additional LVI function RTC causes reset if battery switchover is activated see RTC data sheet factory default ChipS12 6 Mechanical Dimensions The ChipS12 module fits on a standard DIP40 socket The pin spacing is 0 1 2 54 mm and the distance between pin rows is 0 6 15 24 mm The outline dimensions of the module are 2 0 50 8 mm x 0 7 17 78 mm 10 User Manual 7 Circuit Description In this section a number of details will be presented on how to work with the HCS12 in general and the ChipS12 Controller Module in particular Please be aware that even if this manual can provide some specific hints it is impossible to cover all kinds of knowledge and techniques required to design a microcontroller application Please refer to the data sheets of the silicon vendors and to the manuals of your software tools to get additional information The software demos included in this paragraph are for demonstra tion puposes only Please note that we cannot guarantee for the correct ness and fitness for a particular purpose Schematic Diagram To ensure best visibility of all details the schematic diagram of the ChipS12 is provided as a separate document Controller Core Power Supply The MCU IC1 has three supply pin pairs VDDR VSSR VDDX VSSX and VDD
14. a voltage that is higher than the nominal full load voltage Therefore in order to get real 9V a nominal settinmg of 6V or 7 5V is usually sufficient The higher the input voltage the more heat will be produced by VR1 W Once powered up LD1 on the carrier board and D1 on the ChipS12 module will turn on and the Monitor program will start displaying a message and awaiting your commands We hope you will enjoy working with ChipS12 User Manual 3 Module Pinout RXD VCC TXD SCK RESET MISO PP5 MOSI PMO SS PM1 PS1 PTO PSO PT1 PB4 PT2 PAO PT3 VRH PT4 PADO7 PT5 PADO6 PT6 PADO5 PT7 PAD04 PE4 PAD03 IRTC PADO2 VBAT PADO1 CANL PADOO CANH XIRO GND 1RQ ChipS12 4 Components Location Diagram oH oma n D o O O O O O O O O O O O O O O O O O Top View Bottom View User Manual 5 Jumpers and Solder Bridges Jumpers There are no jumpers on the ChipS12 module Solder Bridges The following solder bridges are located on the bottom side of the PCB see components location diagram on previous page BR1 VRH open closed BR2 RTOUT 1 2 2 3 BR3 SHDN 1 2 2 3 BR4 RRTC open closed external supply of VRH required VRH connected to VDDA VCC on board enable RS232 receiver output RIOUT drives PSO of MCU disable tristate RS232 receiver output RIOUT Port pin PSO freely available enable RS232 transceiver IC2 permanently PE4 of MC
15. allows adjusting performance vs current consumption according to the needs of the user application For HCS12 microcontrollers a wide range of software tools monitors C compilers BDM debuggers is available to accelerate the development process ChipS12 Technical Data Ww Ww SZ SS SS SS SS SS SS zz MCU MC9S12C128 with LQFP48 package SMD HCS12 16 bit CPU uses same programming model and command set as the HC12 16 MHz crystal clock up to 25 MHz bus clock using PLL 128 KB Flash 4 KB RAM 256 KBit serial EEPROM 1x SCI asynch serial interface incl RS232 drivers 1x SPI synch serial interface 1x msCAN module CAN 2 0A B compatible High Speed CAN bus driver optional for 5V or 3 3V 8x 16 bit Timer Input Capture Output Compare 5x PWM Pulse Width Modulator 8 channel 10 bit A D Converter Integrated LVI circuit Reset Controller BDM Background Debug Mode Interface 6 pin connector Indicator LED up to 26 general purpose I Os available depends on usage of other on board functions Option Real Time Clock providing time of day calendar alarm function and automatic switch over to ext backup battery Operating voltage either 3 3V or 5V depending on installed CAN driver type current consumption typ 25mA 2 0 x 0 7 x 0 5 module size DIP40 footprint User Manual Development Package Contents W ChipS12 Controller Module with MC9S12C128 incl Real Time Clock and 5V CAN bus d
16. back data received 19 ChipS12 IC Bus The MC9S12C128 does not contain a IIC hardware module To control the on board peripherals IC5 RTC and IC6 serial EEPROM a simplified software implementation of the IIC bus protocol can be used for an example please refer to file S12 SIIC S The MCU signal PAO is used as bidirectional data line SDA while PB4 provides the clock SCL Both signals can also be used to access external IIC slaves Serial EEPROM On the ChipS12 extra non volatile storage space can be provided by IC6 This serial EEPROM device has a capacity of 16 Kbit Optio nally larger devices can be used up to 256Kbit IC6 communicates over an IIC interface The file CHIPS12 SEEP C shows how to control the device using the software IIC module described above kaa File CHIPS12_SEEP C V1 01 for ChipS12 using 256kBit EEPROM 24LC256 sssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss55 include datatypes h include s12 siic h include chips12 seep h Defines device signature of 24LC256 8 bit left justified value define SEEP DEVICE ID 0xA0 Variables static INT16 SEEP ErrorCode Fit Dode Er P E void initSEEP void SEEP ErrorCode SEEP EC OK INT16 peekSEEP UINT16 addr UINT8 b SEEP ErrorCode SEEP
17. be done using the freely available Motorola Tool SRECCVT SRECCVT m 0x00000 Oxfffff 32 o lt outfile gt lt infile gt A detailed description of this tool is contained in the SRECCVT Reference Guide PDF Redirected Interrupt Vectors The interrupt vectors of the HCS12 are located at the end of the 64KB memory address range which falls within the protected monitor code space Therefore the application program can not modify the interrupt vectors directly To provide an alternative way the monitor redirects all vectors except the reset vector to RAM The procedure is similar to how the HC11 behaved in Special Bootstrap Mode The application program can set the required interrupt vectors during runtime before global interrupt enable by placing a jump instruction into the RAM pseudo vector The following example shows the steps to utilizy the IRQ interrupt ldaa 06 JMP opcode to staa SOFEE IRQ pseudo vector ldd isrFunc ISR address to std SOFEF IRQ pseudo vector 1 For a C program the following sequence could be used install IRQ pseudo vector in RAM if running with TwinPEEKs monitor unsigned char OxOfee 0x06 JMP opcode void void OxOfef isrFunc The following assembly listing is part of the monitor program It shows the original vector addresses 1st column from the left as well as the redirected addresses in RAM 2nd column 27 ChipS12 FF80 FF82 FF84 FF8
18. character follo wed by a number of arguments as required All numbers are hexadeci mal numbers without prefix or suffix Both upper and lower case letters are allowed The CPU s visible address range is 64KB therefore address arguments are not longer than 4 digits An end address always refers to the following not included address For example the command D 1000 1200 will display the address range from 1000 to including 11FF User input is handled by a line buffer Valid ASCII codes are in the range from 20 to 7E Backspace 08 will delete the character left of the cursor The lt ENTER gt key 0A is used to conclude the input The monitor prompt always displays the current program page 1 e the contents of the PPAGE register Monitor Commands Blank Check Syntax B Blank check whole Flash Memory ex monitor code space If Flash memory is not blank then display number of first page containing a byte not equal to FF Dump Memory Syntax D adr1 adr2 Display memory contents from address adr1 until address adr If end address adr2 is not given display the following 40 bytes Memory location adr1 will be highlighted in the listing 29 ChipS12 Edit Memory Syntax E addr byte Edit memory contents In the command line the start address addr can be followed by up to four data bytes byte thus allowing byte word and doubleword writes The write access will be performed immediately an
19. d then the function will return to the input prompt If the command line did not contain any data byte the interactive mode will be started The monitor is able to identify memory areas which can only be changed on a word by word basis Flash EEPROM In such cases the monitor always awaits and uses 16 bit data To exit the interactive mode simply type O Additional commands are lt ENTER gt next address previous address same address exit like Q Fill Memory Syntax F adr1 adr2 byte Fill memory area starting at address adr1 and ending before adr2 with the value byte Goto Address Syntax G addr Call the application program at address addr Note there is no regular way for the application program to return to the monitor Help Syntax H Display a brief command overview 30 User Manual System Info Syntax I Display system information This includes address range of register block RAM EEPROM and Flash and the MCU identifier PARTID Load Syntax L Load an S Record file into memory Data records of type S1 16 bit MCU addresses and S2 linear 24 bit addresses can be processed SO Records comment lines will be skipped S8 and S9 Records are recognized as end of file mark S2 Records use linear adresses according to Motorola guidelines The valid address range for the MC9S12C128 starts at OXOE0000 0x38 16KB and ends at OXFFFFF 0x40 16 KB 1 Before loading into non vola
20. ens 25 Additional Information on the Web lusus 25 9 TWINPEEKS MONITOT amp uiua Arte ae AG HAS Vads 26 Serial Communication 26 Autostart Function 26 Write Access to Flash EEPROM 0000 ce eee 26 Redirected Interrupt Vectors 27 USAGE PC 29 Monitor Commands 29 10 Memory Map NNN NEE emm eye cba 33 Id eg MT rm 34 Parts Location Plan 34 Jumpers and Connectors 35 Schematic Diagram 36 Notes on Power Supply 36 User Manual Overview ChipS12 is a miniaturized controller module based on a powerful 16 bit HCS12 microcontroller It can be easily plugged into a DIP40 socket on the user s application PCB The module can be operated with either 3 3V or 5V which makes it suited for a wide range of industrial applications A complete development package is available to kick start your development work It contains a ChipS12 controller module a carrier board including a large number of useful peripherals such as LEDs buttons buzzer and LC display and a set of cables Tool software documentation and example programs are provided on a CD ROM The ChipS12 is equipped with a MC9S12C128 microcontroller unit MCU It contains a 16 bit HCS12 CPU 128KB of Flash memory 4KB RAM and a large amount of peripheral function blocks such as SCI SPI CAN Timer PWM ADC and General Purpose I Os The MC9S12C128 has full 16 bit data paths throughout An integrated PLL circuit
21. fter reset the TwinPEEKs monitor checks whether port pins PT2 and PT3 X0 9 10 are connected If this is the case the monitor immediately jumps to address 8000 This feature allows to start an application program automatically without modifying the reset vector which is located in the protected Flash Boot Block Write Access to Flash EEPROM The CPU can read every single byte of the microcontroller s resour ces the type of memory does not matter However for write accesses two rules are important Flash EEPROM has to be erased before any write attempt Programming is done by writing words two bytes at a time to aligned addresses To form such aligned words two subsequent bytes have to be combined TwinPEEKs is aware of this but the following problem can not be avoided by the monitor The monitor is processing each S Record line seperately If the last address of such an S Record is even the 2nd byte to form a complete word is missing TwinPEEKs will append an FF byte in this case so it is able to perform the word write The problem occurs if the byte stream continues with the follo wing S Record line The byte that was missing in the first attempt 26 User Manual would require a second write access to the same word address which is not allowed As a consequence a write error not erased will be issued To avoid this problem it is necessary to align all S Record data before programming This can
22. in the schematic diagram CAN communication software can be quite complex There are many and diverse ways to establish some CAN protocol particularly when looking at the higher protocol layers However to establish a simple connection between two CAN bus nodes can easily be done as the following example may show include datatypes h include mc9s12dp512 h include s12 can h Defines Variables Code Func initialize CAN Args Retn Note void initCANO UINT16 idar UINT16 idmr CANOCTLO BM_INITRQ request Init Mode while CANOCTL1 amp BM_INITAK 0 wait until Init Mode is established set CAN enable bit deactivate listen only mode and use Oscillator Clock 16MHz as clock source CANOCTL1 BM_CANE set up timing parameters for 125kbps bus speed and sample point at 87 5 complying with CANopen recommendations OSC 16MHz prescaler 8 gt 1tq 16MHz 8 1 0 5ps tBIT tSYNCSEG tSEG1 tSEG2 ltg 13tq 2tq 16tg Bus fBUS tBIT 1 125kbps CANOBTRO 0x07 sync jump width 1tq br prescaler 8 CANOBTR1 Oxlc one sample point tSEG2 2tg tSEG1 13tq we are going to use four 16 bit acceptance filters CANO
23. lder pads to equipd ChipS12 pin 21 40 J2 not Connection solder pads to equipd ChipS12 pin 3 20 J3 not optional same pin out as J4 may be used as equip d 2C bus connection requires software driver J4 open 1 VCC 2 PT2 3 PT3 4 GND if pin 2 and pin 3 are connected during reset monitor autostart becomes active open close to activate CAN bus termination by R5 required at both bus end points open close to connect supply voltage VIN to K2 9 can be used to share power supply with another CAN bus node open close to connect backup battery BAT1 to VBAT input of ChipS12 RTC backup supply RS232 connector use Sub D9 1 1 cable to PC CAN connector Sub D9 optional may be used as SPI port Connector for wall power supply polarity does not matter input ca 8 15Volt DC is BDM connection to ChipS12 module eal BDM connector for debugger BDM pod P Connector for alphanum LC display factory default 35 ChipS12 Schematic Diagram To ensure best visibility of all details the schematic diagram of the ChipS12 Carrier Board is provided as a separate document Notes on Power Supply On the carrier board the voltage regulator VR2 can deliver up to 100mA see data sheet of the LE33 This value is more than sufficient for the ChipS12 Module alone However if additional external compo nets are connected the limit could easily be exceeded In this case the total current cons
24. le rate Furthermore two alarm interrupts can be genera ted at preset times The INTR pin of the RTC is brought out to X0 16 as signal IRTC It can be connected externally to one of the MCU s interrupt inputs IRQ XIRQ or some general purpose I O pin A backup battery can be connected to the module s VBAT pin X0 17 in order to provide a backup supply in case the main power VCC fails For this purpose the use of a 3V LiMn primary battery is recommended The switchover to backup power is accomplished when VCC falls below 2 4V In this state also the VDCC output of the RTC is driven low By closing BR4 this signal can be used as an additional system reset source Example routines showing how to drive the RTC of ChipS12 are contained in the file CHIPS12_RTC C CAN Interface The MC9S12C128 contains one CAN Module designated as CANDO It utilizes port pins PMO and PM1 IC3 option serves as physi cal CAN bus interface The CAN bus signals CANH and CANL are available at connector XO If the ChipS12 is the last node in a CAN bus chain an external termination resistor is required Use a resistor of 120 Ohm between CANH and CANL R6 determines the slope control setting The standard value 10k must be modified for high speed communication according to the datas heet of the manufacturer 22 User Manual The device type used for IC3 must match the supply voltage of the module Please check the part numbers mentioned
25. lse will only be applied during a power cycle event IC4 will not stretch pulses coming from the MCU s internal reset sources This is essentially important since otherwise the MCU would not be able to detect the source of a reset This would finally lead to a wrong reset vector fetch and could result in a system software crash Please be aware that also a capacitor on the reset line would cause the same fatal effect therefore external circuitry connected to the RESET pin of a HC12 HCS12 MCU should never include a large capacitance Clock Generation and PLL The on chip oscillator of the MC9S12Cxx can generate the primary clock OSCCLK using a quartz crystal Q1 connected between the EXTAL and XTAL pins The allowed frequency range is 0 5 to 16MHz As usual two load capacitors are part of the oscillator circuit C1 C2 However this circuit is modified compared to the standard Pierce oscillator that was widely used for the HC11 and HC12 On the ChipS12 the MC9S12Cxx uses a Colpitts oscillator with translated ground scheme The main advantage is a very low current consumption though the component selection is more critical The ChipS12 circuit uses a high quality quartz crystal together with two load capacitors of only a few picofarad Furthermore special care was taken for the PCB design to introduce as little stray capacitance as possible in respect to XTAL and EXTAL With an OSCCLK of 16 MHz the internal bus speed ECLK becomes 8
26. nally after opening solder bridge BR1 This can be useful if the main supply is not in the desired tolerance band or if the ATD should work with a reference value lower than VCC VRH must not exceed VDDA regard less of the selected supply mode The TEST pin is used for factory testing only in an application circuit this pin always has to be grounded Reset Generation RESET is the MCU s active low bidirectional reset pin As an input it initializes the MCU asynchronously to a known start up state As an open drain output it indicates that a system reset internal to MCU has been triggered The HCS12 MCUs already contain on chip reset generation circuitry including power on reset COP watchdog timer and clock monitor Additionally the MC9S12C128 is equipped with a Low Voltage Inhibit LVI circuit The task of this LVI circuit is to issue a stable reset condition if the power supply falls below the level required for proper MCU operation To furthermore increase system reliability IC4 can be added as an external LVI circuit IC4 has an open drain output in order to prevent collisions with the MCU s bidirectional reset pin The RESET signal is high in inactive state because IC4 contains an integrated pull up resistor approx 5kOhm Therefore R1 is not needed if the optional IC4 is equipped 12 User Manual The reset pulse issued by IC4 has a typical duration of 250ms minimum is 140ms It is important to note that this pu
27. nning on the HCS12 The HCS12 operating mode used for download and debugging is called Background Debug Mode BDM BDM is active immediately out of reset if the mode pins MODA MODB BKGD are configured for Special Single Chip Mode This is done by pulling the BKGD pin low during reset while MODA and MODB are pulled down as well Because only the BKGD level is different for the two modes it is quite easy to change over However there is no need to switch the BKGD line manually via a jumper or solder bridge because this can be done by a BDM Pod such as ComPOD12 attached to connector X1 A BDM Pod is required for BDM based download and or debugging anyway so it can handle this task automatically usually controlled by a PC based debugging program Integrated A D Converter The MC9S12C128 contains a 10 bit Analog to Digital Converter module This module ATD provides eight multiplexed input channels VRH is the upper reference voltage for all A D channels On the ChipS12 VRH is connected to VDDA VCC through solder bridge BRI After opening BR1 it is possible to use an external reference voltage connected to X0 31 The following example program shows the initialization sequence for the A D converter module ATD and a single channel conversion routine The source file S12 ATD C also contains some additional functions for the integrated ATD module 15 File S12 ATD C V1 00 Includes
28. ows the steps required to initialize the PLL include mc9s12dp512 h include s12 crg h NEN GOD mass nasee A ED void initPLL void CLKSEL amp BM_PLLSEL make sure PLL is not in use PLLCTL BM_PLLON BM_AUTO enable PLL module Auto Mode REFDV S12 REFDV set up Reference Divider SYNR S12_SYNR set up Synthesizer Multiplier the following dummy write has no effect except consuming some cycles this is a workaround for erratum MUCTS00174 mask set OK36N only CRGFLG 0 while CRGFLG amp BM_LOCK 0 wait until PLL is locked CLKSEL BM_PLLSEL switch over to PLL clock R4 is used to pull XCLKS high during reset which will select Colpitts configuration of the oscillator If XCLKS were low during reset the oscillator would assume Pierce mode which would require an alternate circuitry However this mode could be used to apply an exter nal clock signal to the EXTAL pin of the MC9S12Cxx 14 User Manual Please note that different derivatives of the HCS12 have different funtionality regarding the XCLKS pin Operating Modes BDM Support Three pins of the HCS12 are used to select the MCU operating mode MODA MODB and BKGD MODC While MODA and MODB are internally pulled low to select Single Chip Mode BKGD is pulled high R2 by default As a consequence the MCU will start in Normal Single Chip Mode which is the most common operating mode for application code ru
29. river W TwinPEEKs Monitor in the MCU s Flash memory W Carrier Board with DIP40 socket for the ChipS12 module LC display and a large number of peripheral functions W RS232 cable Sub D9 W BDM cable between ChipS12 and Carrier Board W User manual this document W Schematic Diagrams W CD ROM contains assembler software data sheets CPU12 Reference Manual code examples C compiler evaluation version etc e a TELALLA pr ChipS12 2 Quick Start As no one likes to read lengthy manuals we will summarize the most important things in the following section If you need any additio nal information please refer to the more detailed sections of this manual Here is how you can start with the development package W Please check the board for any damages due to transportation W Check if the ChipS12 module is mounted correctly on the carrier board red BDM connectors adjacent to each other w Connect the device via RS232 connector K1 on the carrier board to your PC Use the serial cable Sub D9 1 1 which comes in the box W On the PC start a Terminal Program An easy to use Terminal Program is OC Console which is available at no charge from our Website W Select a baudrate of 19200 Bd Disable all hardware or software protocols W Connect a power supply to K4 delivering approx 9V 8 12V polarity does not matter W Please note wall plug power supplies are usually not stabilized and they provide
30. tile memory Flash EEPROM this kind of memory must always be erased Also only word writes can be used in this case It may be required to prepare S Record data accor dingly before it can be downloaded see instructions above The sending terminal program such as OC Console must wait for the acknowledge byte before starting the transmission of another line This way the transmission speed of both sides PC and MCU are synchronized Move Memory Syntax M adr1 adr2 adr Copy a memory block starting at address adr and ending at adr not included to the area starting at address adr3 31 ChipS12 Select PPAGE Syntax P page Select a program page PPAGE This page will become visible in the 16KB page window from 8000 to BFFF Erase Flash Syntax X page Erase one page 16KB of Flash memory If page is not specified the whole Flash memory ex monitor code space will be erased after user confirmation To remove erase the monitor code a BDM tool such as ComPOD12 StarProg is required 32 User Manual 10 Memory Map The memory map of the MC9S12C128 is initialized by the TwinPEEKs monitor as follows ChipS12 C32 Sur m be o 2KB RAM 0800 SOFFF VinPEEKs uses the top 512 res Were epe Poon ChipS12 C128 0000 03FF Control Registers 4KB RAM with 3KB of it visible the lower 1024 0400 OFFF bytes are hidden by Control Registers TwinPEEKs uses the top 512 Bytes
31. umption should be monitored e g on jumper J8 pins 1 and 2 The LC display LCD1 is always 5V powered even if the controller module is operated with 3 3V The R W input of the LCD is perma nently connected to L level so display control is done by write accesses only The 3 3V CMOS outputs of the microcontroller deliver sufficient voltage levels to drive the 5V TTL inputs of the LC display 36
32. y occur Should you use the product for any such unintended or unauthorized application you shall indemnify and hold the manufacturer and its suppliers harmless against all claims even if such claim alleges that the manufacturer was negli gent regarding the design or implementation of the product Product features and prices may change without notice All trademarks are property of their respective holders User Manual Contents AA PR PAPA 3 Technical Data 4 Development Package Contents 5 E DEC AA 6 3 Module PINOUT EE 7 4 Components Location Diagram 8 5 Jumpers and Solder Bridges 9 NA cM 9 Solder Bridges i e l4 e e Rex Rx eds 9 6 Mechanical Dimensions suse 10 7 Qircuit DGSOHDIOR Gerd EE ban PEE ee 11 Schematic Diagram 11 Controller Core Power Supply 11 Reset Generation 12 Clock Generation and PU 13 Operating Modes BDM Support 15 Integrated A D Converter 0 aaa 15 Indicator LED v ro eean sas cite EEN s wha AN Eh ERES 17 RS232 Interfaces garas ena eee Rm een wees 17 SPIBUS 20204404 deuce Adel EE C eq m ad bres ob 19 NC BUS its Musee rota b E EI Ede hd 20 Serial EEPROM cse ese SUE uses SURROUND SURE AR 20 Real Time GIOGK o sro seska ser ec te C orco Ce scs eed 22 CAN Interface enaere 22 ChipS12 8 Application Hints isis bes OE CR kt 25 Behaviour after Reset 25 Startup Code e
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