the LAP-A Series brochure
Contents
1. sese 21 Task 3 Signal Bus Trigger Edge Setup eee eee 26 Task 4 Run to Acquire Data sees 26 93 2 BUS LOGIC Analysis cesse eiit ota odetmact edes ona ede ranee Dad edet sie ees RA ENEO EEKE R T ENEE 28 The Zeroplus Logic Analyzer Installation Guide Page 1 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide Preface This Quick Start Guide is designed to help new and intermediate users navigate and perform common tasks with the Zeroplus Logic Analyzer Despite its simple packaging and interface the Logic Analyzer is a sophisticated measurement and analysis tool It is also a highly sensitive electrical current sensing device Users must carefully read instructions and procedures pertaining to installation and operation Any instrument connected to the unit should be properly grounded A pair of anti static gloves is strongly recommended when performing a task with the device To ensure accuracy and consistency of output data use of the bundled components is strongly recommended User opinions are very important to Zeroplus Please contact our engineering team by telephone fax or email with your questions or feedback Thank you for choosing the Zeroplus Logic Analyzer The Zeroplus Logic Analyzer Installation Guide Page 2 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 1 Features of the Zeroplus Logic Analyzer In this chapter users will learn about the package contents description hardwar2. J 4 Za ll 228A 31 16 2A LES Logic Analyzer LaDocl E File BusSignal Trigger RunStop Data Tools Window Help Dea amp AES bbc s 28K jos 200MHz v mw due 10 T y Page 1 Count amp Gg BM A Rm k 2293us vR oy BE Be LL BB le ol PEDIS YR Heit 40 Tahe 4 AL x Scale 2 293us Display Pos Uns APos 06049us v A T 6049us v A B 150ns v Total655 36us Trigger Dos Uns BPos 06034us v B T 60 34us v Compr Rate No I J sx Bus Signal Trigger D45 864us 84 39Bus 4122 B2us D11 466us M 11 46 us 22 932us 34 398us 45 864us ii i i i L i i i i Li i i i 1 L 1 Lt i L Li 1 i L i 1 i i L i 1 i i ENS x 43 5 LI LJ LJ Fig 3 8 Trigger Count Screen shot 2 Step 4 Trigger Page Delay Time and Clock The Trigger Page and The Delay Time and Clock can t be applied at the same time 1 Trigger Page Click Trigger Page then Type the numbers or select the numbers from the pull down menu of the Page Pe f on the Tool Bar or Click the pull down menu of the Trigger Page on the Trigger Delay page of the Trigger Properties dialogue as shown in Figs 3 9 3 10 and 3 11 The page numbers selected will be displayed on the screen Tip The Trigger bar T bar will not be displayed when the set up of the Trigger page is more than 1 Tagger ferries Jeger Delay 7 Dais Time acd Shek Tega Dele To di Sea bci dar m Tagger Delay Chek din deo JOT f fore Dua Sta
3. E Fue BS Trigger Run Stop Data Tools Window Help n b b d 128K lt Sampling Setup amp G iy Channels Setup Scale 1 Clock Source Total 6 Ungroup from Bus Ct Asynchronous Clock Busig Y Internal Clock r Ei Frequency 200MHz v Format Row PAN Synchronous Clock DEM External Clock val z x C Min 0 001Hz Max 100MHz 4 2 Se Note The external clock voltage level is the same as the port trigger level E Samplina RAM Size Compression Mode Enable Mode RAM Size 128k Data compression Enable Setup Channel number will be limited ta 32 Cancel Help Restore Defaults Fig 3 1 Clock Source The Zeroplus Logic Analyzer Installation Guide Page 19 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide Step 2 Internal Clock Asynchronous Clock Click on Internal Clock and then select the Frequency from the pull down menu to set up the frequency of the device under test DUT The frequency of the Internal Clock must be at least four times higher then the frequency of the Oscillator on the DUT Or select the frequency fzoomnz from the pull down menu on Tool Bar as Fig 3 2 shows Tip Connect the signal output pin of the tested board to the Signal connector of Logic Analyzer to measure it using the internal clock of Logic Analyzer ds Alit igEl nu Clack Source lhe E l d Asynchronous Clock nM Y Internal Clock aus Frequency 2 61 3 Synchronous Cloc
4. Windows 2000 XP 300 MHz or above strongly suggest 900 MHz or above We have tested various 32 Bit and 64 Bit CPUs Overall we find that all 32 Bit CPUs work very well with Logic Analyzer software Moreover we find that AMD s 64 Bit CPUs except Opteron with a 64 Bit Windows operating system work just fine with Logic Analyzer no significant problems occur e Memory Windows NT 98 98 SE 128 MB or above 64 MB minimum Windows 2000 XP 256 MB or above 128 MB minimum e Hard Drive At least 100 Mb available space e USB USB 1 1 compatible recommend USB 2 0 e Display Devices recommended 1 17 monitor with 1024x786 resolution or higher 2 8MB SDRAM on Video Card The Zeroplus Logic Analyzer Installation Guide Page 9 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 1 5 Device Maintenance and Safety Follow these instructions for proper operation and storage of the Logic Analyzer Table 1 7 General Advice Do not place heavy objects on the Zeroplus Logic Analyzer Avoid hard impacts and rough handling Protect the Logic Analyzer from static discharge Do not disassemble the Zeroplus Logic Analyzer this will void the warranty and could affect its operation Use a soft damp cloth with a mild detergent to clean Do not immerse or spray any liquid on the Zeroplus Logic Analyzer Do not use harsh chemicals or cleaners containing substances such as benzene toluene xylene or acetone
5. C External Clack E D Mote The exte Samoling RAM Size 100MHz cm RA Size 126k 2 U00MHz Channel number wr limited to 32 Z UMHE Fig 3 2 Clock source drop down menu External Clock Synchronous Clock Click on External Clock and then select Rising Edge or Falling Edge as the trigger condition of the DUT In the Frequency column type the frequency of the oscillator on the DUT Tip The External Clock is applied when the frequency of the oscillator on the tested board is less then 100MHz Connect the output pin of oscillator on the tested board to the CLK pin of Logic Analyzer as shown in Fig 3 3 The Zeroplus Logic Analyzer Installation Guide Page 20 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide Step 3 RAM size Click on the RAM size 2K ai from the pull down menu on the Sampling Setup dialogue as shown in Fig 3 3 Synchronome Eo Gare rp T You selected the Double mode The Enable option is Rif not available under this made Samolina After clicking Apply Enable Setup will disabled RAI Size u Moke bli 1 26K i Don t show me this warning again Channel nu 18 eK LS E limited 16k Samnplina hee imited to 16 15 32k RAM Size RAM Size 256k x m Channel number will be limited to 16 Fig 3 3 RAM Size Tip The relationship between RAM size Enable Compression and channels as shown in Table 3 1 and Fig 3 3 Table 3 1 RAM size vs Enable and RAM siz
6. Table 1 8 Electrical Specifications tems Minimum Typical Maximum Current at Rest Error in Phase Off input Of Testing Channels V Reference Input Resistance Working Temperature Storage Temperature Table 1 9 refer to the User Manual for error analysis calculation The Zeroplus Logic Analyzer Installation Guide Page 10 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide WARNING Storage Environment Conclusion Operating Environment Avoid direct sunlight Use in a dust free non conductive environment see Note Relative Humidity 80 Altitude 2000m Temperature 0 40 degrees C This is a Class A product which may cause radio interference in a domestic environment Note EN 61010 1 2001 specify degrees of pollution and their requirements Logic Analyzer falls under Level 2 Pollution refers to addition of foreign matter solid liquid or gaseous ionized gases that may produce a reduction of dielectric strength or surface resistivity Pollution Degree 1 No pollution or only dry non conductive pollution occurs This pollution has no effect Pollution Degree 2 Normally only non conductive pollution occurs Occasionally however temporary conductivity caused by condensation must be expected Pollution Degree 3 Conductive pollution occurs or dry non conductive pollution occurs which becomes conductive due to condensation In such conditions equipment is nor
7. the internal sampling frequency within the Logic Analyzer is at least four times the external board frequency 2 Ifthe signal connector does not work well with the pins on the test board try using the supplied probes 3 Usages of probes 3 1 Take the loose end of the cable and insert it into the clip 3 2 Compress the probe as shown to reveal 2 metal prongs Fig 2 8 3 3 Place the metal prongs on a metal connector on the motherboard and release the fingers so that the prongs grip the metal connector Fig 2 9 y t PE s L 5 e r m if pU a UA L X L AAAA hiihiihii d TN 2 FRNA Fig 2 9 ow I The Zeroplus Logic Analyzer Installation Guide Page 16 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 4 The Logic Analyzer will connect to the Zeroplus server for software updates if an internet connection is available Unwanted signals can be filtered out using the Enable or Enable Delay functions When measuring for a long period Compression makes memory more efficient 7 Trigger condition depends on the test board If triggering does not work well try narrowing the trigger conditions and optimize them repeatedly 8 lfatest board has a lower frequency than Logic Analyzer sample signals according to the external clock 9 When clocking by an external clock filter extra signals with the Enable function 10 Unused channels may be removed from the Bus Signal display using Bus Sig
8. 128 Kbits 128 KBits 1 MBits Internal Clock Rate 100 200 MHz asynchronous Max External Clock Max 100MHz synchronous Trigger Channels 16 Channels 32 Channels Trigger Condition Edge Pattern Pre Trigger Ye Post Trigger Trigger Level Trigger Count 1 65535 Max Trigger Page Max 8191 S Enable Channel 16 Buses Data Decoded Start Edge and Pattern Enable Delay End 1 65535 Compression Us ene 24 Channel Compression 1 255 Compression The Zeroplus Logic Analyzer Installation Guide Page 8 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 1 4 System Requirements This section discusses basic operating system and hardware requirements for the Logic Analyzer Software and hardware capabilities may vary depending on PC configuration This manual assumes proper installation of a supported operating system as listed below 1 4 4 Operating System Requirements In this sub section we share our experiences testing the Zeroplus Logic Analyzer on the following Microsoft Windows operating systems Since the Zeroplus Logic Analyzer requires operating system support of the USB protocol Windows 95r2 and earlier OS versions are incompatible 1 Windows 98 98 Second Edition supported 2 Windows ME supported 3 Windows 2000 Professional Server Family supported 4 Windows XP Home Professional Editions 32 Bit versions supported 1 4 2 Hardware System Requirements e CPU Windows NT 98 98 SE 166 MHz or above
9. Fig 3 24 3 Set and type the value of bus into value column to set the trigger condition of the bus 4 Click OK Step 4 Click run and activate the signal from the tested board to the system to get the result as shown in Fig 3 26 Tip Click icon to view all data and then select the wave analysis tools to analyze the waves Set Value is 5E as Hexadecimal and set Operator equal to then click OK Click run and activate the signal from the tested board to the system to get the result as the trigger happens on OX5E Bus Trigger Setup i Bus Name Operator Value Edit Base Mode C Binary Hexadecimal C Decimal Ok Cancel Fig 3 26 Bus Trigger Setup The Zeroplus Logic Analyzer Installation Guide Page 30 Best Measure Best Quality www zeroplus com tw O ZEROPLUS Instrument Sales Department 3F No 121 Jian Ba Rd Chung Ho City Taipei County 235 Taiwan R O C Tel 886 2 6620 2225 Fax 886 2 6620 2226 6F No 265 Wuling Rd North District Hsinchu City 300 Taiwan R O C Tel 886 3 542 6637 87 Fax 886 3 542 4917 Best Measure Best Quality
10. M Best Measure Best Quality O ZEROPLUS LAP Installation Guide PC Based Logic Analyzer LAP A Series LAP 16128U LAP 32128U A LAP 321000U A The Zeroplus Logic Analyzer ZEROPLUS Installation Guide mie 2 1 Features of the Zeroplus Logic Analyzer 3 1 1 e Teze cii m 9 Bs WM OGUICUOM PER TE 5 1 8 Hardware Specifications ccccccccccccccccecceesseeceeeeeeeseeeeceeeeeseeeeeeeeeeessaaaseeeeeees 8 1 4 System Requirements cccccseeeccccseseeceeceeeeeeeeceeaeeeeesseaeeescueaeeeeseaeeeesssaaeeeess 9 1 4 1 Operating System Requirements esse eee eee ee 9 1 4 2 Hardware System Requirements sse 9 1 5 Device Maintenance and Safety ccccccccseeccccceeceeeeseeeceeeessaeeeeeeeeeeeeaeneees 10 P rici M 12 2 1 Software InstallallODisu ence set vrsupaxE c EUpEXSEKIPEREEI SU EUER UprEE EK RE OEVR FOrx XE OK SU XEAT EROS 12 22 uicelrsii aigcti cis 14 2 3 Tips and Be Ue M 16 2 4 Flow of software operation sse eee eee 18 3 Introduction to Logic Analysis eese 19 SL Logie Abas adequmeiedbste usitate a Eei 19 Task 1 Clock Source Frequency and RAM Size set up 19 Task 2 Trigger Properties Setup
11. S OAS 5 4 AB eS eal De 4 B 5 g B2 es B Z J B4 5 J 3 zan ae ag dy S End Normal Z Fig 3 19 Click icon to view all the data 3 Stop to End Run Click the Stop 8 icon to End the Run Tip If the status stays displays Waiting with no signal output as shown in Fig 3 20 click the stop icon to end the run check the setup again and try the run process again The Zeroplus Logic Analyzer Installation Guide Page 27 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 3 2 Bus Logic Analysis Section 4 2 presents detailed instructions about logic analysis with a set of grouped signals which is known as Bus Logic Analysis Basic Software setup of the Bus Logic Analysis Step 1 Set up the RAM size Frequency Trigger level and Trigger position as described in Section 3 1 Step 2 Group Signals into a Bus Click Channels setup on Bus Signal of menu bar or click i icon The dialogue window shown in Fig 3 21 will appear x33 3 sape 1 3 Gh Cn n cn cn cn cn en E Kn tn tn kn Un in Un Ln dues we kas el ee tele oo a a a a RORIS 414 t Fig 3 22 R 1 Click the column with blue then type the given name of the bus and then press enter to confirm it 2 Go to the relative channels show as shown in the example and go to numbers 1 2 3 4 5 which are located on column A and row Bus1 Click them to b
12. cb Wmbw Bk mm SMS RAK eB pE fizo s n fonn je o e T Ca fi S cus vion m pidum Ij seb RY mee ea nin 13 7596 T 60499 A BelDe YNZ Xa edog S B t Me e Conge Pat No E anal Tum IN Ma a s a A I E BAR TATUR QIIIA Im 6 Oe H 10x 90 Fig 3 14 Trigger Position 10 SERGOFLUS Lope Agalyeer afl L Bk rare poe Beda fxm Inch Redec Bel ISM S BBB HD bbs a iae Sl seme Ge FON 4 ne ji i a aOR SR re OA See Le ww aa T KL C Seale Ld er Daley Poe Date Lar Nite e Ateis i p Trggn Pea T Port 55 G Tei hes F Mab 7 M a m w Fig 3 15 Trigger Position 70 Step 6 Click OK to confirm the setup and exit the Trigger Properties dialogue The Zeroplus Logic Analyzer Installation Guide Page 25 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide Task 3 Signal Bus Trigger Edge Setup Highlight a designated signal and then set its required trigger edge 1 Left click to set the signal trigger edge as shown in Fig 3 16 2 Right click to set the signal trigger edge as shown in Fig 3 17 3 Click Trigger on the menu bar and choose a trigger from the list of triggers as shown in Fig 3 18 Busiga Trager a Ms Li rau id 4 right click KA E dun al Pepa i Tri 7 A2 Dus EE left click e pM Huh M 4 Y M Lee JF Riin Hp lt M o en 9 N Filing Edge zx St Fiber Edge E E 4 A2 Ea F AG Fig 3 16 Trigger Left click Fig 3 17 Trigge
13. e When crre Hur oce bigger pepe ars oe edd Hn in eger bag dein pps Emm the view EUN D w t ma Fig 3 11 Trigger Position and screen 2 Delay Time and Clock Click the Delay Time and Clock then type the numbers into the column of the Trigger Delay Time or type numbers into the Trigger Delay Clock at the Trigger Delay page of the Trigger Properties dialogue as 0 and Fig 0 Or type the numbers into the column of Trigger Delay ass Deky 5ns on the Tool Bar The system will display the wave start Tip The formula of Delay Time and Clock is Trigger Delay Time Trigger Delay Clock 1 Frequency The Zeroplus Logic Analyzer Installation Guide Page 24 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide Step 5 Type the percentages or select the percentages from the pull down menu of the de Em on the Tool Bar or Click the pull down menu of the Trigger Position on the Trigger Delay page of the Trigger Properties dialogue as shown in Figs 3 12 3 13 3 14 and 3 15 The Trigger Position percentages selected will be displayed where counted from the right side of the screen of the system Eng Prepi frage faks T Tant fep S Tart Baier Da Deb Mui D B M lal B BRR 609 HORS dec zr GR Jermen s pee hn POG BE sion R Zer ele BI BINI 4 muse ez nempe d Setha fa 1t Tn A faita Tob 535 Misi med pari Bi tea pw J a Mis e i nel x T lt 7 B Boligi fares Kea D o
14. e specifications system requirements and safety issues of the Zeroplus Logic Analyzer Though this chapter is purely informative we highly recommend reading this carefully to ensure safety and accuracy when performing any operation with the Zeroplus Logic Analyzer 1 1 Package Contents Verify the package contents before discarding packing materials The following components should be included with your product For assistance please contact our nearest distributor Table 1 1 Parts list for retail packages Models LAP 16128U LAP 32128U A LAP PARIA A Logic Analyzer 1 1 O 16 Pin Testing Cable 8 Pin Testing Cable sp a USB Cable Getting Started 1 1 1 Guide White Black This Driver CD consists of a multilingual software interface program as well as a multilingual User s Manual The Zeroplus Logic Analyzer Installation Guide Page 3 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide M Mi ji f ii V f i f l T UE 16 Pin x 1 8 Pin x 2 Fig 1 2 Testing Cables Fig 1 1 Logic Analyzer P ZEROPLUS Fig 1 3 Probes SSS varied depending on models Fig 1 4 USB Cable Fig 1 6 Driver CD Fig 1 7 1 Pin External Clock Wire Fig 1 8 2 Pin Ground Wire White Black The Zeroplus Logic Analyzer Installation Guide Page 4 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 1 2 Introduction Zeroplus Logic Analyzer mode
15. e vs Compression and channels RAM Channel Compression RAM hannels Compression Model No sizes available Mode amp size aae Mode amp channel Enable Mode channel Enable Mode 2K 128K 16 channels Available 256K 16 channels Disable LAP 32128U A 2K 128K 32 channels Available 256K 16 channels Disable 2 LAP 321000U A 32 channels Available 16 channels Disable Task 2 Trigger Properties Setup Step 1 Click if icon or Click Properties from the Trigger on the Menu Bar The dialogue will appear as shown in Fig 3 4 Tn esr Progestin Trigger Daels Tigger Level Fan TIL e Por TTL a Pe D tt fis e Trigger Count t Min d Max Gos l ak Cuncel bett Help Fig 3 4 Trigger Properties The Zeroplus Logic Analyzer Installation Guide Page 21 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide Step 2 Trigger Level Setup Click the drop down menu of Trigger Level on Ports A B C and D to select the Trigger Level as the voltage level that a trigger source signal must reach before the trigger circuit initiates a sweep Tip There are four commonly used preset voltages for Trigger Level TTL CMOS 5V CMOS 3 3V and ECL Users also may define their own voltage from 6V to 6V to fit with their DUT Port A represents the pins from AO A7 on the signal connector of the Logic Analyzer and so do Ports B C and D The voltage of each port may be configured indepe
16. ecome purple to set these segments of signals 3 Click OK to get the result as shown in 0 area 1 The Zeroplus Logic Analyzer Installation Guide Page 28 Tip Step 3 Tip The Zeroplus Logic Analyzer Installation Guide Delete Al Restore Def ows Fig 3 23 Channel setup Window Channels Setup In Dialogue of Channels Setup there isn t only Add Bus Signal but also Delete Bus Signal Delete All Restore Defaults functions provided 1 Delete Bus Signal first highlight the bus or channels on area 6 of Fig 3 23 then click Delete Bus Signal to delete it 2 Delete All click Delete All to delete all bus signals on area 6 of Fig 3 23 3 Restore Defaults click Restore Defaults to restore the dialogue of Channels Setup as shown in Fig 3 21 Set Trigger condition 1 Highlight the bus which will be triggered then click icon or select Bus from the Trigger of the Menu bar the dialogue window as shown in Fig 3 24 will appear Hus Ingger Setup Bus Mame Operator value Busi ka lrer Edit Base Mode J Y Binary f Hexadecimal C Decimal Fig 3 24 Bus Trigger Setup or double click on trigger column of the bus as shown in Fig 3 25 The Zeroplus Logic Analyzer Installation Guide Page 29 The Zeroplus Logic Analyzer Installation Guide Double Clicks Z AU De Al ex Fig 3 25 Trigger Column 2 Set Binary Hexadecimal or Decimal as the signal of the bus to represent the value see
17. gic Analyzer to your computer with the included USB Cable as shown in Figures 2 4 and 2 5 1 Plug the fixed end of the cables into the LA Fig 2 1 2 Plug the loose ends into the connectors on the circuit board to be analyzed Fig 2 2 Z T Note The following sequence must be observed when connecting the connectors into the circuit board AO Brown A1 Red A2 Orange and so on Fig 2 2 E ig 3 The circuit board must be grounded to ES 5 the Logic Analyzer with the ae j connecting cables Fig 2 3 pw A OM E L Ei X KL N S 3 by Fig 2 3 Step 1 Plug the thin male end of the USB cable into the laptop or PC Step 2 Plug the square female end into the logic analyzer The Zeroplus Logic Analyzer Installation Guide Page 14 The Zeroplus Logic Analyzer Installation Guide 4 Plug the square end of the USB cable into the Logic Analyzer Fig 2 4 5 Plug the thin end into the computer Fig 2 5 Fig 2 5 At this point the computer should be able to detect the Logic Analyzer and finalize the installation for hardware connection For further information refer to the Troubleshooting and Frequently Asked Questions FAQ chapters in the User Manual Fig 2 6 An assembly of Laptop Logic Analyzer and a testing board The Zeroplus Logic Analyzer Installation Guide Page 15 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 2 3 Tips and Advice 1 When testing a circuit board make sure that
18. grounding the Logic Analyzer with a Ground given external module to be analyzed Table 1 3 Definitions and Functions of pins for advanced models 1 When the Logic Analyzer is about to upload data from Read Out memory to the PC the R O will send a Rising Edge signal of DC3 3V When the upload is finished a Falling Edge signal is sent To memon When a trigger condition is established the T_O will T O Trigger Out send a Rising Edge signal of DC3 3V When memory is full a Falling Edge signal is sent When a user initiates a sampling task by clicking the RUN icon in the window or clicking the START button Start Out on the device the R_O will send a Rising Edge signal of DC3 3V When the Logic Analyzer finishes uploading a falling edge signal is sent The Zeroplus Logic Analyzer Installation Guide Page 7 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide Table 1 4 Definitions and Functions of pins for advance models 2 Voltage Drain Provides 3 3 V for external modules by draining VDD Semiconductor voltage from the Logic Analyzer Ext l O Module A Transmits signals from an external model or device not being tested Ext I O Module B Same as IOA Ext UO Module C Same as IOA GND J Ground Grounds external devices in sequence 1 8 Hardware Specifications Table 1 5 Hardware specifications of LAP A Model Interface USB20 L1 16 32 Memory Depth l Per Channel
19. ion proceeds Step 3 Choose the desired language Step 4 Click Next to proceed with the Install wizard Step 5 Select Il accept the term in this license agreement and click Next Step 6 Enter User and Organization name Step 7 Choose the setup type We recommend Complete for most users Step 8 Click Install to confirm settings and begin actual installation Step 9 Click Yes to acknowledge the Microsoft Digital Signature message and continue the installation Step 10 Click Finish to complete the installation Step 11 Click Yes to restart the PC The Zeroplus Logic Analyzer Installation Guide Page 12 O ZEROPLUS CT 2x Type Uw name of a program folder document or 1 Internet resource and Windows will open K for vou Qpem ELAP 321200 A VZ Uz Setup exe ZEROPLUS Pirparing Sa lna LAE prima X TU aka k uer pdr rad Rat IF and Arel etrn acl pai pu Broap Fe mP ma wiy Pao Pasce at Tiet ru pum drai rle mma LICENSE AGREEMENT IMPOR TANT FEAD CAREFULLY Tha LICENSE AGREEMENT ii miatti gin eiTeri heaem ZEROPLUS Technaiegy Ca Lid homie ORLA and Coriomer iniia or Reena Company Wheres TEXSOPLUS cars a poun product gate cerai pB Barz 81 a pae lege product Sar centum coer prsd eis pei emelary oduct nfernanon eectrons fle and gara E Lre rms ha Kee ager 1 hared aco Re Ene He Ket ere Corder rd anaien i ee fo deem anm un eT L eR md bere Pn rK e ta B K
20. ls LAP 16128U LAP 32128U A and LAP 321000U A all share the same external features as illustrated in the following figures __ TRIGGER Wa oe AW AW 4 Signal Connecto Adjustable Base Stand Fig 1 9 A view of the Zeroplus Logic Analyzer LAP A Series see Fig 1 12 for detailed information on the Signal Connectors Fig 1 10 Side view of the Zeroplus Logic Analyzer which draws its power from the USB connection The Zeroplus Logic Analyzer Installation Guide Page 5 The Zeroplus Logic Analyzer Installation Guide Fig 1 11 The above illustration demonstrates how the Base Stand Support may be adjusted Gently pull the plate away from the analyzer rotate it 90 and release it Fig 1 12 Rear view of the Zeroplus Logic Analyzer LAP A Series Port A AO A7 Port B BO B7 Port C CO C7 Port D DO D7 For extended modules or devices not designated to be For signal transmission to analyzed active other instruments For the External Clock For grounding test connection circuits The Zeroplus Logic Analyzer Installation Guide Page 6 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide List of functional pins in each model Model LAP 16128U LAP 32128U A LAP 321000U A O S0 XXX O O Table 1 2 Definitions and Functions of pins for all models CLK Connects a given external module to be analyzed Two pins used for
21. mally protected against exposure to direct sunlight precipitation and wind but neither temperature nor humidity is controlled Relative Humidity lt 80 Temperature 0 50 Degrees C After reading this section users should have a basic grasp of the Logic Analyzer A complete understanding of the Safety and Care Recommendations section is a critical prerequisite of any further operation as presented in the User Manual The Zeroplus Logic Analyzer Installation Guide Page 11 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 2 Installation This chapter describes installation of the Logic Analyzer hardware and software Software installation steps must be followed precisely to ensure successful installation 2 1 Software Installation In this section users will learn how to install the software interface and drivers As with proper installation of many USB devices the Logic Analyzer application and driver software must be installed prior to connection of the hardware The following steps illustrate an installation of a Zeroplus LAP 32128U A Logic Analyzer The other two models mentioned in Chapter 1 would follow identical procedures Step 1 Insert the driver CD ROM in the PC CD drive Step 2 Execute the installation program Go to the START menu click START click Run click Browse select Setup exe file in the appropriate model folder and then click OK It is recommended that all other programs are closed while installat
22. nal Menu gt Channel Setup The Zeroplus Logic Analyzer Installation Guide Page 17 oA Aon om eee S ki eS at Pak SPI Bus Analysis Enable Enable Delay START RAM Size n 128K Sample Rate 200MHz Trigger Edge Trigger Level LH Delay Time Clock Tanti 0 Trigger Page Select Analysis Function Active Signal IIC Bus Analysis From Tested Board UART Bus Analysis Acquire Wave SPI Bus Analysis Tools to Analysis Data o RE Ron D mM le 90 m IIC Bus Analysis UART Bus Analysis to G Bi ki i SPI Bus Analysis uH x Sns E T Hegh The Zeroplus Logic Analyzer Installation Guide Page 18 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 3 Introduction to Logic Analysis Chapter 3 gives detailed instructions in performing two basic analysis operations and five advance analysis applications with the Logic Analyzer The basic analytical operations are the Logic Analysis and the Bus Analysis which are fundamental to all further applications 3 1 Logic Analysis Logic Analysis is meant for a single signal analysis Section 3 1 gives detailed instructions on the software s basic setup Basic Software setup of the Logic Analysis Task 1 Clock Source Frequency and RAM Size set up Step 1 Click ii icon or Click Sampling Setup from Bus Signal on the menu bar the dialogue as shown in Fig 3 1 will appear ZEROPLUS Logic Analyzer LaDoc1
23. ndently Trigger Properties Trigger Properties Trigger Delay Trigger Level PotA TIL sijfis 0 peni B CMOSGv v V Pote cMosG e o PotD ECL PPP ex l CMOS S LogicAnalyzer Trigger Co EMOSI 3 ECL ser Define Min 1 Max 65535 Cancel Default Help Fig 3 5 Trigger Properties Error Step 3 Trigger Count Type the numbers or select the number from the pull down menu of the Count Count fi z on the Tool Bar or Click the pull down menu of the Trigger Count on the Trigger Properties dialogue as shown in Fig 3 5 The system will be triggered where the Trigger Count is set as shown in Figs 3 6 3 7 and Fig 3 8 PotD TTL or Fig 3 6 Trigger Count Drop down Menu The Zeroplus Logic Analyzer Installation Guide Page 22 The Zeroplus Logic Analyzer d Installation Guide ZEROPLUS Logic Analyzer LaDoc1 48 File BusSignal Trigger RunStop Data Tools Window Help Deh amp xS S 6 9 BD bb aie t2ek x io av 200MHz ww we 10 He Page 1 Count A f E EH RO dd BE 45 2293us amp oe 8E By Te dS BB le of E ES UR S Hehe 40 Trigger Delay Scale 2 293us Display Pos 013 571us APos 060 49us v A T 6049us v A B 150ns v Total 655 36us Trigger Poz Uns BPos 060 34us B T 260 34us Compr Rate No BusiSignal LJ Miss 047 969us 86 50Bus 025 087us e de 2 T 9 361us 20 827us 32 208us i 1 2 i 2 Dems 288 Z 4 Al 4 2
24. r Right Click Fig 3 18 Trigger menu Task 4 Run to Acquire Data 1 Single Run Click the Single Run gt icon from the tool bar or press START button on top of Logic Analyzer or press F5 then activate the signal from the DUT to the Logic Analyzer to acquire the data shown in the wave display area 2 Repetitive Run Click the Repetitive Run icon from the tool bar then activate continuous signal to the Logic Analyzer to acquire the repetitive Data and then click the stop icon to end the repetitive run Tip Click icon to view all the data and then select the wave analysis tools to analyze the waves The Zeroplus Logic Analyzer Installation Guide Page 26 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide ZEROPLUS Logic Analyzer LaDocl TER File Busignal Trigger RuwStop Data Tools Window Help 2 EE R amp OUS s HE BD bb c sie 120k v o a 200MHz Sl 10 T Pae i Count fi Gg E ER A 8 i BH 5 13759os IR zs Re Be Te dy B le 1 ED ES SR Hei 40 Trigger Dehay cale 72 679KH2 Display Pos 250 932us APos 060 49us lv T 16 532KHz v B 6667MHz v i lotal 655 36us Trigger Poz Uns BPos 060 34us v B T 16 573KHz v Compr Rate No x cm TE ww num lusSignal Trigger i al m 44 544us 113 34us 182 136us 250 982us 319 728us 388 524us 457 32us 526 116us SA 40 g hl 5S gt N ER III AB 5S J BA j
25. ra ia n He rpe Iden T Cry ba gun 799 The Zeroplus Logic Analyzer Installation Guide i LAP 32128U A STD Installer Information changes made to LAP 32128LI A STD to take effect Click Yes to restart now or No if you plan to restart later KV You must restart your system For the configuration fe LAP 175291 A STD Iribe Wirard Ires allia Wired Cre de te The kret alie Fc gae ha ducet ully roai deZ Li SE LE LA TEs Check preh bo exit the epar ax The Micron Tegrusture soni thet niewe har bezn tahid Heth And Hat tha sofas hike nol fren diaii sanc id uet Marii The saltare vous aa Abol to alal der nof corte Meros KRN paes Thermore there i no guain thal Bus aliae veces Gonisclly valh Zenon li gena enini bi techo dor Macroeoft ditio digne Pean p vcl Ee Mesh eet Lipeika Valet side a hit eandosreupdate miecraspit pom Io 566 I ong in Dn ger vani ho erant Tos este DITFDEXIUIKNIDETUT UIT au Setup Type i Chess the setae Eye Hat beet dul pour repo Pies preci a SET Kre Complete a A program Features all be ret de 96165 the moet del space T Cugtom Cheese etch teme arm aure pou ward eid ale red here they eal be ret dez Recomended Por advare ener tek ome core So The Zeroplus Logic Analyzer Installation Guide Page 13 The Zeroplus Logic Analyzer ZEROPLUS Installation Guide 2 2 Hardware Installation Hardware installation simply involves connecting the Lo
26. rt fon 08 LL Re ed Fo 51 L oen p fap one Epp paged ace kredl the Ejer bar depen freg F Cub teint iep Fig 3 9 Trigger Page The Zeroplus Logic Analyzer Installation Guide Page 23 The Zeroplus Logic Analyzer i ZEROPLUS Installation Guide neds Mas Dimples faa Sea irki A Ie062585u A Bei BRE Tomita 621m Trigger Postes B iwl ima F H T 1245 oF Compe Rae NG a Tse LT Les Ee AH E gp s AR d Tnigrer Frnpertzes Trigger Properties Trigger Delay fai Start Pos Ds 242 12us T gger Page Delay Tune and Clock End Pos Dp Inger Page Trigger Delay Time z73597ms fi Mint Masc E28 Miva May 133 185m T Debr Chock Tigger Poubon cia i lt Min Mase 16859251 T Poz Un Zt Per 2677 Lat dl Poot Tes Bote When more fan coe tigger pages sze elected the appr bar eee peace from Ue ves Fig 3 10 Trigger Position Boake G5 ius Display Pe Gert A Pos 1 nma F Ae TF Mma Be RE 555a Talal frz Lens Terr Bers lm B fos 3 iin B T hie Tm Ceempr Bake Ho F bul al Trigger m Maes Ay m m Ale A A A a Trigger Properties Tripper Delay End Pos Dp 4 B1ms Stam Pos Ds 2 35 ms Trigger Page C Dalley Time and Clock Trigger Page Tagger Delay Tico jz Eu Min Max 128 Min es Max 333 1853 Trigger Delay Clock Tngges Poshin lE C Mil Masc 186 59251 T Pase Das leri Pot 2 Zina Enel Pe d Sl nmg Rol
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