FPGA Programming Guide
Contents
1. Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 8 IP EP2 Series Programming Guide Device Settings 17 Select the Error Detection category and disable uncheck error correction User may optionally enable The remaining categories have no impact on any IP EP2 module 18 Click OK to close Device and Pin Options 19 Click OK the close the Device page Engineering Design Kit rn Device and Pin Options ninek528c pi Category General Configuration Programming Files Unused Pins Dual Purpose Pins Capacitive Loading Board Trace Model I O Timing Voltage Pin Placement Error Detection CRC CvP Settings Partial Reconfiguration Error Detection CRC Specify whether error detection is used and the rate at which it is checked E Enable error detection CRC Enable open drain on CRC_ERROR pin Enable internal scrubbing Divide error check frequency by 1 Zi Description Specifies error detection CRC usage for the selected device If error detection CRC is turned on the device checks the validity of the programming data in the device Any changes in the data while the device is in operation generates an error ox cae Hele Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engine2. Assignment Editor ix lt lt new gt gt Z Fiter on node names Category Loge Optons 24 In the Category Windows Status From To Assignment Name Value Enabled Entity Comment Tag click on Logic Options 1 EE 3 oo Weak Pull Up Resistor On Yes ninek528c 2 Diciis Weak Pull Up Resistor On Yes ninek528c O EE a a 25 In the Spreadsheet double Sut DirCtri 10 Weak Pull Up Resistor On Yes ninek528c i i S H woa kapes on ys nosze click on lt lt new gt gt in the To 7 EE 010146 Weak Pull Up Resistor On Yes ninek528c column Then enter DIO 8 lt lt new gt gt lt lt new gt gt lt lt new gt gt Then double click on the Assignment Name column and select Weak Pull Up Resistor from the pull down menu Confirm that the Value column is set to On and the Enabled column is set to Yes 26 Repeat Step 25 with the following names in the To column DirCtrl 6 DirCtrl 7 ee DirCtrl 8 DirCtri 9 DirCtrl 10 and DirCtrl 1 1 These signals require pull up resistors All assignments are summarized in the Appendix Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 1 0 IP EP2 Series Programming Guide REQUIRED VHDL This section highlights the functionality of some of the VHDL in the Acromag example EnableCPLD Configuration Control Signal WARNING MODIFYING THE VHDL SOURCE CODE FROM THE EXAMPLE DESIGN COULD RESULT IN
3. IPRead_En_High The I PRead_En_Low signal is the direction control for A BUS CONFLICT the lower eight data bits DO to D7 The IPRead_En_High signal is the i direction control for the upper eight data bits D8 to D15 The data flow direction is indicated by the table below In most cases these signals will be identical WARNING FAILURE TO Signal ___ Value Data Flow IPRead_En_Low o0 IP BUS gt FGPA Write operation Default IPRead_En_High FPGA gt IP BUS Read operation The IP BUS gt FPGA data flow should be the default since this will avoid potential data bus conflicts The only time the data flow should from the FPGA to the IP bus is during either I O Space Identification ID Space Interrupt Space or Memory Space read cycles This is done in the software by taking the logical Or of each of these cycles Refer to the example design vhdl code to observe how each read cycle is identified and then passed to the two direction control variables Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 1 2 IP EP2 Series Programming Guide Engineering Design Kit Compilation At this point the user can compile the example design If you are already familiar with the capabilities and specifications of the IP EP2 Series modules then modify the VHDL as desired The design can be compiled by selecting Start Compilation from the Processing menu After the process has finished correct any e
4. 239616 52 EP2C20F484C8 1 2V 18752 315 239616 52 EP2C20F48418 1 2V 18752 315 239616 52 Lal m Bl Migration compatibility Companion device Q 1 migration devices selected Limit DSP amp RAM to HardCopy device resources Earst x S r Gy Device and Pin Options ninek528c Dual Purpose Pins Capacitive Loading Board Trace Model I O Timing Voltage Pin Placement Error Detection CRC CvP Settings Partial Reconfiguration Category m General Configuration Programming Files Unused Pins L General Specify general device options These options are not dependent on the configuration scheme Options v Auto restart configuration after error Release dears before tri states Enable user supplied start up clock CLKUSR Enable device wide reset DEV_CLRn E Enable device wide output enable DEV_OE Z Enable INIT_DONE output V Auto usercode JTAG user code 32 bit hexadecimal FFFFFFFF In system programming damp state 7 Delay entry to user mode v Device initialization dock source v Description Directs the device to restart the configuration process automatically if a data error is encountered If this option is turned off you must externally direct the device to restart the configuration process if an error occurs Engineering Design Kit 5 Device Settings 1 Access t
5. CLK8MZ event and CLK8MZ 1 then EnableCPLD lt EnableCPLD_Reg and not ACK or EnableCPLD_REG and EnableCPLD end if end process Note Using the above VHDL will delay changing the EnableCPLD signal until after the IP EP2 module has acknowledged the write to the control register This prevents the IP bus from locking due to an unacknowledged write cycle 4 After the Altera FPGA has returned control to the configuration mode the CPLD will take over control of the IP bus Once disabled the CPLD will not pass any IP bus signals from the FPGA to the carrier However the I O and interrupts will still function as last programmed Since the CPLD will not be able to handle an interrupt request it is recommended that all interrupts be disabled prior to re entering configuration mode Once Configuration Mode is enabled in this manner the only way to return back to user mode is to reconfigure the board or by issuing an IP module Reset from the carrier board The Altera FPGA requires buffers between itself and the IP bus This is IPRead_Enable Data Bus due to the fact that the FPGA is not 5V tolerant and the IP bus specification Direction Control Signals is based upon 5V signaling levels Buffering is not an issue for any unidirectional signal However the IP data bus is bi directional and as such requires a direction control signal at the buffer This is accomplished through the use of two signals on the FPGA IPRead_En_Low and TA Brag near
6. DISABLE WARNING REMOVING HARDWARE FROM BOARD MAY VOID ACROMAG WARRANTY WARNING PROCEDURES REQUIRE THE REMOVAL OF SMALL SURFACE MOUNT COMPONENTS WARNING ONCE PART IS REMOVED THE BOARD CAN NOT RE REPROGRAMMED WITHOUT A REPLACEMENT Engineering Design Kit This section provides instruction in how to disable all device programming This section is for advanced users only These procedures should be used only when it is critical to remove the ability to reprogram the IP EP2 module Note that to remove all programming abilities the user program must reside in FLASH These procedures require the use of the part location drawing provided on the Engineering Design Kit CD WARNING These procedures require the removal of small surface mount components Removing these parts may void the Acromag warranty Furthermore once these parts are removed the board cannot be reprogrammed without replacing these parts Disable Programming over the IP Bus Remove 0 Ohm Resistors R32 and R33 This will disconnect the programming data and clock lines from the CPLD to the FPGA Once removed programming over the IP bus will no longer function Do not attempt programming after these resistors have been removed Note that there is no method to verify resistor removal through software Disable JTAG Programming Remove 0 Ohm Resistors R34 and R37 This will disconnect the data and clock JTAG programming lines Once removed the JTAG connection will n
7. Industry Pack bus specification provides timing diagrams to use for the simulation Why are there over 100 warnings when I compile the example design The majority of these warnings are related to I O pins that are defined as pins but not utilized or fixed at a certain logic level within the example design Examples include the IP bus DMA control signals and strobe signals Can we utilize the Error Signal on the IP bus No The Error signal is reserved for factory use and is pulled high during normal operation Consider using interrupts to indicate error conditions Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 22 IP EP2 Series Programming Guide PIN ASSIGNMENTS The pin assignments as well as a brief description and the corresponding name in the schematic and VHDL file are detailed in the Pin Assignments table A similar table is also provided in Excel format on the IP EP2 EDK CD Note that the pin location is preceded by Pin_ Pin assignments are stored in the project qsf file Note that schematic connection names preceded by are active low signals Field I O signals are either a bi directional I O line to a transceiver or a direction control line TTL inputs on the EP201 area one to one match to the DIO bus signals The TTL direction is controlled in groups of eight via DirCtrl bits 6 to 11 The even numbered DIO bus channels are mapped to the differen
8. Passive Serial PS and Active Serial AS cancel Hep a Device and Pin Options ninek528c Category General Configuration Programming Files Unused Pins Dual Purpose Pins Capacitive Loading Board Trace Model I O Timing Voltage Pin Placement Error Detection CRC CvP Settings Partial Reconfiguration Programming Files Selects the optional programming file formats to generate For device families with multiple configuration schemes if you select a passive configuration scheme in the Configuration tab the Quartus II software always generates an SRAM Object File sof and either a Partial SRAM Object File psof or a Programmer Object File pof depending on the configurable device you are targeting E Tabular Text File ttf E Serial Vector Format File svf E Raw Binary File rbf In System Configuration File isc E Jam STAPL Byte Code 2 0 File jbc E JEDEC STAPL Format File jam Compressed V Hexadecimal Intel Format Output File hexout Start address 0 Count up Za Description Generates a Tabular Text File ttf containing configuration data that an intelligent external controller can use to configure the target device Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engineering Design Kit T1 FG Device and Pin Options nine D
9. be used to create an instance of the SignalTap II debugger in the VHDL code Within the Wizard select the Cyclone II family as well as the memory depth and the number and type of triggers After running the wizard and integrating the newly creating component into the design compile the program Then set up a STP file for each instance of a SignalTap analyzer by the Create Signal Tap II file from Design Instance command under the File gt Create Update menu Refer to the Quartus II Help files for more information on this procedure and using the SignalTap II Logic analyzer Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engineering Design Kit 2 1 What configuration mode do select in the Quartus II software Acromag recommends that you select the AS configuration mode regardless of the configuration method used This option in the Quartus II GIES ONS ASKED software only reserve pins The actual configuration method is defined at power up via the configuration jumper on the IP EP2 series board Can I program the flash memory over the IP bus Acromag only supports programming the flash device over the JTAG connection However Altera provides a Megafunction altasmi_parallel Active Serial Memory Interface Parallel to allow the Cyclone II FPGA to access the flash This library component could be used to program the flash or to utilize the remaining space for non volati
10. to the Programming Window 16 From the Mode pull down window select JTAG 17 In the left pane click the Add File button Then select the jic file generated in step 5 Click Open Now the programming file and the Cyclone II device should be listed in the window 18 Check both boxes under the Program Configure column 19 Then click on the Start button to download the file to the FLASH via JTAG Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engineering Design Kit 1 T1 ninek528a cdf DER FLASH Pee voei a Pogee ox CONFIGURATION VIA Tl Enable real time ISP to allow background programming for MAX II devices J T AG ph Start File Device Checksum Usercode Progam Verify Security Configure Bit Blank pean checks xamine Erase Eii CLAMP Quartus II Programmer Example for Flash configuration aw Auto Detect ab Add File Add Device 20 Once complete the IP EP2 module will still be in configuration mode To trigger a configuration cycle to load the program from Flash either write a 1 to bit O of the Configuration Control Status Register Base Addr 0x0 or power down and then power the board back up Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 1 8 IP EP2 Series Programming Guide 3 0 HARDWARE PROGRAM
11. Acromag 4 Series IP EP201 202 203 204 Industrial I O Pack Engineering Design Kit FPGA PROGRAMMING GUIDE ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A Copyright 2011 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 798 D13F007 2 IP EP2 Series Programming Guide Engineering Design Kit TABLE OF IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring CONTENTS component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 GETTING STARTED The information of this manual GENERAL INFORMATION ccsssseeeeeessseeeeees 3 may change without notice DESIGN FILES ocieccceceieceseectecesceseviueescteieess arinnar Eei 3 Acromag makes no warranty LOADING THE PROJECT cccsssseereeeseseceees 4 of any kind with regard to this PROJECT SETTINGG ccccessssceeeessssceeeensseeeees 4 material including but not IP EP2 ASSIGNMENTS ccsssceeeeeeeseeeeeesseseees 8 limited to the implied REQUIRED VHDL LOGIC cceceseeeeeeseeeeeeeeeeeees 9 warranties of merchantability C
12. BOARD FAILURE BE SURE TO SIMULATE AND UNDERSTAND ANY MODIFICATION PRIOR TO ITS IMPLEMENTATION Engineering Design Kit After the Project settings and assignments have been set or verified the user should become familiar with the IP EP2 Series board prior to modifying the VHDL They should understand the IP Bus and Cypress Programmable clock interface the asynchronous interface with the SRAM and learn how the I O are controlled Acromag recommends that you do not directly modify the interface with either the IP bus or the Cypress Clock If it is necessary to modify either interface be sure to completely understand the requirements as defined in the IP specification or the appropriate data sheet Failure to do so may cause the board to stop responding to IP bus requests In addition to these interfaces several control signals to the CPLD must be maintained by the FPGA These signals one to enable configuration mode and another to assist with IP bus control must be included in any program targeting the FPGA There are two main modes of operation on the IP EP2 Series module configuration mode and user mode The IP EP2 Series powers up in configuration mode and remains in that mode until the Altera FPGA is successfully configured Once the Altera FPGA is successfully configured control is automatically transferred to user mode and the Altera FPGA has control of the IP bus interface In order to implement this transition the following requ
13. FLASH memory via JTAG the jumper must be set in the FLASH position If using the JTAG cable to either direct program the FPGA or when using the SignalTap II debugger the jumper can be in either position What can I do if I cannot communicate with the IP module after I download a custom program If the IP module does not respond then there is likely a problem with the VHDL controlling the IP interface The first step should be to download the example program Once the IP EP2 module is reconfigured test the IP interface with the sample program provided in the Acromag OS software support packages If the example program interface functions then you can start debugging your own code Use the Quartus II functional simulator to emulate a sample IP bus cycle Another option is to use SignalTap Il a JTAG debugger though modification of the VHDL will be necessary How do I implement the Signal Tap II debugger SignalTap Il is a FPGA debugging tool that allows the user to debug the firmware under real operation conditions The debugger interfaces with the Cyclone II FPGA on the IP EP2 modules via the JTAG connection To use this feature an Altera JTAG download cable is required Acromag does not directly support the SignalTap II debugger though it can be integrated into our example design The following procedure is a brief introduction on using SignalTap Il and is provided for reference only The MegaWizard Plug In Manager under the Tools menu can
14. GA is not 5V tolerant Refer to the IP Specifications available from www vita com for further information RAMa 15 RAMd 0 RAMd 1 RAMd 2 AMD2 HDL Name Pin Direction Schematic Connection RAMd 3 PINT6 Bidir RAMD3 RAMd 4 RAMd 5 RAMd 6 B B B D d d P gt gt ojg gt o Sz I gt g oo RAMA RAMA RAMAJO RAMA 10 RAMA T RAMAT RAMAT RAMA RAMATS i PINN9 input FPGA A A PIN_J2 input FPGA A2 3 PIN_J1 input FPGA A3 4 PINAS Input FPGA_Ad F 5 6 CK n S0_n Si_n LK8MZ DHIGH 0 FPGA_D8 DHIGH 1 PIN_C2 Bidir FPGA_D9 DHIGH 2 IPIN F3 Bidir FPGA_D10 DHIGH 3 DHIGH 4 DHIGH 5 Bidir DHIGH 6 DHIGH 7 PIN J4 Bidir FPGA_D15 DLOW 0 PINL1 Bidir __ FPGA_DO DLOW 1 PIN_AS Bidir __ FPGA_D1 DLOWI2 DLOW 3 DLOWI4 DLOWI5 DLOW 6 Bidir DLOW 7 Bidir DMAAck_n DMAend_n DHIGH O DHIGH DHIGH 2 DHIGHIS DHIGH 4 DHIGH S DHIGH 6 DHIGH 7 pLowto LOW LOW LOW DLOW 4 DLOW 5 DLOW e DLOwI7 DMAAck n DMAendn Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engineering Design Kit 25 DMAReGO_n DMAReqt_n IDSEL_n INTREQO n HDL Name Ping Direction Schematic Connection INTREQT_n INTSEL_n OSEL_n MEMSEL n R Wn RESET n troben KOUT_REF EN CLK CK ER_DATA nableCPLD PRead_En_High PRead En Low trob
15. OMPILATION s cececebccccevstcisentecectenerscbeesnate enaena 11 and fitness for a particular purpose Further Acromag 2 0 PROGRAMMING THE BOARD assumes no responsibility for any errors that may appear in FPGA CONFIGURATION OVER THE IP BUG 12 this manual and makes no DIRECT FPGA CONFIGURATION VIA JTAG 13 commitment to update or FLASH CONFIGURATION VIA UTAG 0c s eeseeeeoe 14 keep current the information vartof this manualmay be 3 0 HARDWARE PROGRAM DISABLE copied or reproduced in any DISABLE PROGRAMMING OVER THE IP BUG 17 form without the prior written DISABLE JTAG PROGRAMMING sssssssssee 17 consent of Acromag Inc REMOVING THE CONFIGURATION JUMPER 17 4 0 TROUBLESHOOTING FREQUENTLY ASKED QUESTIONG 0 18 APPENDIX PIN ASSIGNMENT 0 cecceeeseceeseeessceneeessseeeees 21 WEAK PULL UP ASSIGNMENTG ceeeeeeeee 25 DEVICE SETTINGG ccssccccsssseccesssssssersssseeeeeens 25 REVISION INFORMATION ccsssseceeeeeeseeeeeenees 26 The following manuals and part specifications provide the necessary RELATED information for in depth understanding of the IP EP2 Series board PUBLICATIONS IP EP2 Series User s Manual www acromag com 71V016SA SRAM Specifications hitp www idt com Cyclone Il Data Book http www altera com CY22150 Specification http Awww cypress com Trademarks are the property of their respective owners Ac
16. UBLESHOOTING FREQUENTLY ASKED QUESTIONS Helpful Tip Users should be familiar with the Quartus II software prior to modifying the IP EP2 firmware If not run the Quartus ll tutorial available from the Help Menu Helpful Tip If the board does work correctly try downloading the example program If this works then simulate your firmware to try to find the problem Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 20 IP EP2 Series Programming Guide Engineering Design Kit FREQUENTLY ASKED QUESTIONS Helpful Tip The Quartus I MegaWizard Plug in Manager can create functional blocks for many common components such as FIFO s or internal RAM Note to enable SignalTap II in the Quartus II Web Edition the Altera TalkBack feature must be enabled Refer to Altera documentation for more information on this program How does the Configuration Jumper setting work The configuration jumper controls the voltage of the Cyclone II MSELO pin This jumper ties the pin to either 3 3V or ground The pin controls where the FPGA receives its configuration data If the pin is high the FPGA is set in Passive Serial PS mode and the configuration data is passed from the IP bus If the pin is set low the FPGA is in Active Serial AS mode and the FPGA is configured directly from FLASH memory How should the Configuration Jumper be set when I am using the JTAG cable When programming the
17. ample for direct FPGA JTAG pa Auto Detect 5 Programming ab Add File Add Device The IP EP2 Series module can also implement configuration using a FLASH standard JTAG interface The JTAG interface can either program the FPGA CONFIGURATION VIA directly or program the FLASH configuration memory Note that the FPGA JTAG will require reprogramming after power down 1 Power down the IP EP2 module and connect the 10 pin Altera JTAG cable not included to the board This cable is available from Altera 2 Set the Configuration Jumper to FLASH as shown in JTAG Interface Jumper Location drawing located in the IP EP2 Series User s Manual Failure to set this jumper correctly will cause programming to fail 3 Power up the IP EP2 module and start the Quartus II software 4 Generate the sof programming file This file is automatically generated by Quartus II upon successful compilation The file is located in your Quartus II project directory 5 Select Convert Programming Files from the File menu 6 Inthe Convert Programming Files dialog box select JTAG Indirect Configuration File jic from the Programming file type pull down menu 7 Inthe Configuration Device pull down menu select EPCS4 8 Inthe File name field set the output file name and directory 9 Click on SOF Data in the Input Files to convert section 10 Click Add File and select the sof file generated in step 1 Click OK 11 Highlight FlashLoader and c
18. arted by first starting the Quartus II software and then selecting Programmer under the Tools menu 5 Inthe Programming Window click Hardware Setup Under the Currently Selected Hardware pull down menu select the device that connects to the IP EP2 board i e ByteBlaster Il Click close to return to the Programming Window 6 From the Mode pull down window select JTAG 7 Inthe left pane click the Add File button Then select the sof file generated in step 1 Click Open Now the programming file and the Cyclone II device should be listed in the window 8 Check the Program Configure check box 9 Then click on the Start button to download the file to the FPGA via JTAG 10 Upon successful configuration the board will be in User mode with the Altera FPGA in control of the IP bus interface It is good practice to issue a software reset prior to operating the board Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engineering Design Kit 1 5 Note that all configuration data will be lost at power down DIRECT FPGA W ninek528a cdf f ae ByteBlaster LPT1 ee z CONFIGURATION VIA eq Hardware Setup lastel ot efta ogress I Enable real time ISP to allow background programming for MAX II devices J TAG wih Start File Device creceu Usercode Ree Verify ne Examine oa Erase Paal eet PE TT Quartus II Programmer Ex
19. cromag com IP EP2 Series Programming Guide Engineering Design Kit 2 1 REV Date Description REVISION A 12 11 06 Initial Release INFORMATION Added Revision Information Modified Strobe_n to Bidir and added CPLD control signal Strobe_Dir in table on B Obie SOL page 24 Removed Enable Init_Done requirement on pages 5 and 25 Added Frequently Asked Questions c 1 04 11 Correct EnableCPLD pin reference from F3 to L3 on pages 9 and 12 Updated references to Rev C EDK D 6 17 13 Updated to be compatible with Altera Quartus II Version 12 1 SP1 development tools Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com
20. e timing constraints file Synopsis Design Constraints 1 0 GETTING STARTED GENERAL INFORMATION DESIGN FILES Quartus II version 12 1 with Service Pack 1 or later is required Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 4 IP EP2 Series Programming Guide Engineering Design Kit LOADING THE PROJECT PROJECT SETTINGS In addition to the VHDL design files the IP EP2 Series Engineering Design Kit includes a schematic parts list parts location drawing manuals and other utility programs e 4502063a pdf IP EP2 Series Schematic and Part Location Drawing e IPEP2_797a pdf IP EP2 Series User s Manual e IPEP2_Programming_Guide pdf IP EP2 Series Engineering Design Kit Programming Guide IPEP201 pdf Part list for IP EP201 IPEP202 pdf Part list for IP EP202 IPEP203 pdf Part list for IP EP203 E model IPEP204 pdf Part list for IP EP204 E model HFileGenerator exe This program generates C style h output file from an Intel hex input file such as the NineK528 hex file The h file can be used to compile in the Altera configuration data into your own C program This program can also be modified to allow programming of the IP EP2 Series module over the IP bus However you will need the base address of the IP EP2 module in your system e HFileGenerator c Source C file for HfileGenerator exe e BitCalc2k1 exe The BitCalc2k1 exe file is an executable program which
21. e Dir VHDL Name Pin Schematic Connection INCE Pro mco P P N N14 N F4 PGA TDI PGA TDO PGA TMS The remaining pins on the package are either unused power or ground pins All GND and GND_PLL pins are connected to an internal ground plane in the PCB All VCCIO pins are connected to 3 3V All VCCINT VCCD and VCCA pins are connected to 1 2V The unused pins are either left unconnected or connected to ground Refer to the schematic provided in the EDK for further information A complete list of pinouts for the Cyclone Il FPGA is provided on the EDK CD in an Excel spreadsheet PIN ASSIGNMENTS The Programmable Clock Generator Interface provides the interconnect between the Cypress clock generator and the Cyclone II device Refer to the manufacturer s data sheet for further information The CPLD Control Signals are required signals to assist the CPLD in controlling the IP EP2 module Refer to the Required VHDL section earlier in this manual for further information 1 The Init_Done signal was not used within the CPLD As such its function was changed to a direction control signal for the IP Bus Strobe_n signal Configuration Pins Table The configuration pins do not have to be assigned in the Quartus II software The table is for reference purposes only Power Pins Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 26 IP EP2 Series Programming Guide Engineering D
22. ering Design Kit Q K Assignment Editor a l IP EP2 ASSIGNMENTS lt lt new gt gt v Filter on node names X Category Al ooo r 2 E con ee ne el 2O T The example design contains all A Ok ocati _ es 1 i pm m Err bs l of the assignments required for 4 Zo Location PIN KL Yes _ s the proper operation of the 5 vo EE Location PIN_N10 Yes eS c vk n Location PIN D10 Yes s module Instructions for setting 7 vo are ari __ the assignments are below 3 vo B Location PIN_D3 Yes E 1 Yok E Location PIN_B6 Yes aa u so B Location PNL Yes m 20 Select Assignments gt 2 so a Location PINES Yes a i 3 ok B Location PIN P11 Yes B Assignments Editor 14 Vo 6 Location PIN_C11 Yes 15 Vok M Location PIN_R9 Yes a ie 21 In the Category Window 1s Yok D Location PIN_R3 Yes zq click on All 19 vok a Location PIN_M1 Yes e j 2 vo E Location PIN_B10 Yes s aS i ocati K es Se 2 Vo M Te Ny ve d_ 22 In the pin spreadsheet 7 s A T E place the signal name in the oS Ok E ocati E es a r i o ME ee ice ao s E To column and the pin z2 sok M Location PNT Yes alphanumeric id in the 2 2o B Location PIN_B13 Yes ay Value column 52 This cell shows the status of the assignment in the current row 23 Enter all pin names and locations as given in the Pin Assignments Table in the Appendix
23. esign Kit WEAK PULL UP ASSIGNMENTS DEVICE SETTINGS Several I O lines require that the weak pull up resistors logic option be enabled in the FPGA The pull up resistors are required to prevent the I O from floating These assignments are done in the Assignment Editor The following I O pins require weak pull ups DIO 0 through DIO 47 DirCirl 6 DirCtrl 7 DirCtrl 8 DirCtrl 9 DirCtrl 10 and DirCtrl 1 1 The IP EP2 module design requires that some FPGA device settings be fixed These settings are found under Device in the Assignments category Assume that all settings listed below are required and ENABLED checked or selected unless stated otherwise Any disabled unchecked options are not listed Family Cyclone II Specific Device EP2C20F256C8 Click the Device amp Pin Options button for the follow settings Remember that only ENABLED options are listed General Tab e Auto restart configuration after error e Auto usercode User can enter own usercode if desired Configuration Tab e Active Serial Configuration Scheme e Use Configuration Device EPCS4 e Generate Compressed Bitstreams Optional Programming Files Tab e Hexadecimal Output File e Start Address 0 e Count UP Unused Pin Tab e Reserve as inputs tri stated with weak pull up Dual Purpose Pins e nCEO0 Use as programming pin Voltage Tab e l O standard LVTTL Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www a
24. ettings are correct A summary of all the project settings and assignments is available in the Appendix of this manual The following procedure was written for Quartus II version 12 1 with Service Pack 1 Note that the location of the settings and assignments may vary with newer versions of Quartus II Refer to Quartus II Help if you are unable to find a specific project setting Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide epee Select the family and device you want to target for compilation Device family Show in Available devices list Family Cyclone 1 X Package Any gt Devices All Pin count Any X Speed grade any Target device k Name filter Auto device selected by the Fitter Specific device selected in Available devices list V Show advanced devices HardCopy compatible only a Other n a Device and Pin Opti me Available devices Name Core Voltage LEs User I Os Memory Bits Embedded multiplier 9 bit elements EP2C20AF25618 1 2V 18752 152 239616 52 EP2C20AF484A7 1 2V 18752 315 239616 52 EP2C20AF48418 1 2V 18752 315 239616 52 EP2C20F256C6 1 2V 18752 152 239616 52 EP2C20F256C7 1 2V 18752 152 239616 52 EP2C20F256C8 1 2V 18752 152 239616 52 b EP2C20F25618 1 2V 18752 152 239616 52 EP2C20F484C6 1 2V 18752 315 239616 52 EP2C20F484C7 1 2V 18752 315
25. evice Settings Category ened 15 In the Unused Pins ose en SRY a te Ce aa oS ree Le on Be eo rea ee category reserve all unused ea ppost configuration pis 99 lo Ihe Diet Puspoos Pits tab To reserve o pins individually use pins AS inputs tri stated ba cere Reserve all unused pins As input tri stated with weak pull up with weak pull up I O Timing Voltage aT k WARNING Due to the dual a configuration nature of the IP Partial Reconfiguration EP2 Series module this option must be set correctly Failure to do so may cause contention on the FPGA programming pins Description Reserves all unused pins on the target device in one of 5 states as inputs that are tri stated as outputs that drive ground as outputs that drive an unspecified signal as input tri stated with bus hold or as input tri stated with weak pull up 16 Select the Voltage category cons a Configuration P 3 3 level to 3 3 V LVTTL in the Programming Files Specify voltage options for the device Unused Pins pull down menu Dual Purpose Pins Default 1 O standard 3 3 VLVTTL ee VCCIO I O bank1 voltage n a in Cydone II use Pin Planner to adjust VCCIO voltage VCCIO I O bank2 voltage n a in Cydone II use Pin Planner to adjust VCCIO voltage Core voltage 1 2V Partial Reconfiguration Description Specifies the default I O standard to be used for pins on the target device
26. he Device Settings by selecting Assignments gt Device 2 Inthe Device window select the Family as Cyclone II 3 Select the Specific device selected in Available device list radio button 4 Inthe Available devices list select EP2C20F256C8 EP2C20F 25618 can be selected for Industrial Temperature Rage modules Device amp Pin Options 5 From the Device page click the Device amp Pin Options button 6 From the General Category check the following options Auto Restart configuration after error and Auto usercode All other options should NOT be selected 7 The user may change the JTAG user code if desired The default setting is Auto usercode 8 Select the Configuration category Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 6 Device Settings 9 Inthe Configuration category select Active Serial as the configuration scheme 10 Then check the Use configuration device box and select the EPCS4 from the dropdown menu Note that either configuration scheme can be used with this setting The Quartus II software selection simply reserves the appropriate pins 11 The Generate compressed bitstreams is a user selectable option The default option is on 12 Select the Programming Files category 13 In the Programming Files category check Hexadecimal Output File Then set the Sta
27. ing the Altera Serial Flash Loader The Serial Flash Loader creates a logic bridge between the Cyclone II JTAG interface and the controls of the FLASH device This bridge allows the user to program the Flash via the JTAG interface The FLASH device cannot be programmed through the IP interface This method is recommended for debugged designs since the Flash device programs the Altera FPGA at power up The programming procedures for each of the three methods are below The Cyclone II FPGA can be programmed directly over the IP bus To Kpa SrA program the Cyclone II FPGA over the IP bus follow the procedure below 1 Generate the Intel hexadecimal programming file This file is generated automatically upon compilation in your Quartus II project directory if the correct option is selected in the Programming Files Tab under Device Options To generate an Intel hexadecimal file manually in Quartus Il select Convert Programming Files under the File Menu Then under programming file type select Hexadecimal Intel format Set the output file name and directory as desired Then add the sof file from your project If no sof file exists then the project has not yet compiled to completion Once the sof file has been added click Generate Close the window when finished Note that the hexadecimal file must be accessible by the computer that contains the IP EP2 Series module 2 Power down the computer with the IP EP2 module and set the Configurati
28. irements must be respected by the Altera FPGA 1 Pin L3 of the Altera FPGA is reserved as an EnableCPLD control When Pin L3 is driven low the IP EP2 module is in user mode and the Altera FPGA has control of the IP bus interface When Pin L3 EnableCPLD is driven high the IP EP2 module is in configuration mode 2 The EnableCPLD signal Pin L3 should be driven by Altera FPGA logic similar to that shown in the following VHDL process Notice that after the Altera FPGA is configured the EnableCPLD signal is driven to a logic low by the configured Altera FPGA A logic low holds the IP EP2 Series module in user mode 3 The EnableCPLD signal L3 can be driven to a logic high via an IP bus write cycle to base address 0 hex with Data line 0 set high Setting EnableCPLD high returns the IP EP2 module to configuration mode Note that this procedure is only required when programming the FPGA over the IP bus The JTAG interface will automatically disable the FPGA and hand control over to the CPLD process CLK8MZ RESET begin if RESET 1 then EnableCPLD_Reg lt 0 elsif CLK8MZ event and CLK8MZ 1 then if WR_Ctrl_L 1 then EnableCPLD_Reg lt DLOW 0 else EnableCPLD_Reg lt EnableCPLD_Reg end if end if end process Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engineering Design Kit 1 1 process CLK8MZ RESET REQUIRED VHDL begin if
29. le memory Why do I need to write 01H to the Configuration Control Register after JTAG programming the FLASH Programming the FLASH via JTAG requires that a bridge program be loaded into the FPGA that allows the JTAG signals to control the serial flash interface Upon completion of programming the FLASH device the FPGA is not reset and still contains the bridge program As such the IP EP2 board will be in configuration mode Writing a 01H to the Configuration Control Register will then instruct the FPGA to reload its new program from FLASH Is the Strobe_n IP bus signal accessible on the IP EP2 and if available how does it work Yes the Strobe_n signal is available for use on all Revision B or later IP EP20x models Contact Acromag for information on determining your products revision level The Strobe_n signal is routed from the FPGA to the CPLD and then to the IP bus Due to the intermediary stop on the CPLD a direction control signal is required This control signal is called Strobe_Dir in the example design and must be set properly Logic low 0 sets the Strobe_n signal as an input and logic high 1 sets the Strobe_n signal as an output Does Acromag provide a test bench Acromag currently does not provide test benches for these models since few uses retain the exact functionality of the example design We recommended that you simulate the design using the built in simulator within Quartus ll The ANSI VITA 4
30. lick Add Device 12 Select the Cyclone Il EP2C20 device Click OK 13 Click the Generate process to create the JIC file Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 1 6 IP EP2 Series Programming Guide Engineering Design Kit FLASH Convert Programming Files CONFIGURATION VIA Specify the input files to convert and the type of programming file to generate JTAG You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Convert Programming Files Dialog for example JIC creation Programming file type JTAG Indirect Configuration File jic sd Configuration device EPCS4 Mode e File name 9000528a ic Hi Remote Local update difference file N I Memory Map File Input files to convert Flash Loader i EP2C20F 256 SOF Data Page_0 i ninek528a sof EP2C20F256 Hex User Data Generate Close 14 Start the Quartus Il Programmer The Programmer can be started by first starting the Quartus II software and then selecting Programmer under the Tools menu 15 In the Programming Window click Hardware Setup Under the Currently Selected Hardware pull down menu select the device that connects to the IP EP2 Series board i e ByteBlaster II Click close to return
31. o longer function All JTAG operations will be disabled Note that there is no method to verify resistor removal through software Replacing the Configuration Jumper The configuration jumper can be replaced with a 0 Ohm resistor This would fix the programming methodology to a single method Please contact Acromag for more information on ordering boards with a fixed programming method Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide This section contains some of the frequently asked questions regarding the IP EP2 series modules This is by no means an exhaustive list Users can also consult with the IP EP2 Series User s Manual Quartus II Help and the part Data Sheets for further information What do I need to implement an IP EP2 Series module To program the IP EP2 Series module you will need Acromag s Engineering Design Kit IP EP2 EDK For easier integration with your operating system we also recommend our OS software support packages for Linux VxWorks and Windows The Engineering Design Kit includes schematics for the boards example VHDL code and example software for downloading the Hex code converted from VHDL code to the FPGA on the IP EP2 module It does not contain the VHDL design software The most commonly used design tool used for this purpose is the QUARTUS II software which is downloadable at no cost from Altera This free software incl
32. on Jumper to IP BUS as shown in JTAG Interface Jumper Location drawing located in the IP EP2 Series User s Manual Failure to set this jumper correctly will cause programming to fail 3 Power up the system Upon system power up the IP EP2 Series module is in configuration mode If the Altera FPGA is currently configured and operational configuration mode can be entered by driving pin L3 of the Altera FPGA to a logic high via the control register bit 0 Pin L3 is the Config_Enable signal which upon system power up is held high by a pullup resistor 4 You can verify that you are in configuration mode by reading ID space at base address OAH The byte read will be 48H when in configuration mode and 49H when in user mode 5 Configuration is started by setting bit O of the control register at base address 00H to a logic high Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 1 4 IP EP2 Series Programming Guide Engineering Design Kit FPGA CONFIGURATION OVER THE IP BUS DIRECT FPGA CONFIGURATION VIA JTAG 6 This same register bit O must be read next When read as a logic high software can proceed to the data transfer phase A polling method should be used here since this bit will not be read high until at least 40u seconds after the control bit is set high The status of the Altera FPGA during configuration can be monitored via the Status register at base address OOH Bit 1 monit
33. ors the Altera nStatus signal which must remain high during configuration Bit 2 of the Status register reflects the Altera FPGA CONF_DONE signal The CONF_DONE signal must remain at a logic low until configuration has completed Write program data from the Intel Hexadecimal file one byte at a time to the Configuration Data register at base address 02H Upon successful configuration control of the IP bus will automatically be switched to user mode and the Altera FPGA will have control of the IP bus interface It is good practice to issue a software reset prior to operating the board Note that all configuration data will be lost when the board is powered down The IP EP2 Series Cyclone II FPGA can be configured using a standard JTAG interface The JTAG interface can either program the FPGA directly or program the FLASH configuration memory When programming the FPGA directly the programming jumper may be in either position The following is the general procedure for direct programming of the Altera FPGA using the JTAG interface 1 Generate the sof programming file This file is automatically generated by Quartus II upon successful compilation The file is located in your Quartus II project directory 2 Power down the IP EP2 module and connect the 10 pin Altera JTAG cable not included to the board This cable is available from Altera 3 Power up the IP EP2 module 4 Start the Quartus II Programmer The Programmer can be st
34. provides the register values needed to program the clock generator chip By entering the desired frequency and selecting the IP clock speed 8MHz or 32MHz this program will compute the correct values to write to the Clock control Registers e IPEP2_Assignments xls Summary of Quartus II assignments in excel format The pin assignments can be copied directly into Quartus II E model E model E Dam The example design project is provided in its entirety on the IP EP2 Series Engineering Design Kit CD To load the example design follow the steps detailed below 1 Copy the Quartus Project folder located on the CD that accompanied the IP EP2 EDK to the local hard drive 2 Start the Quartus II Program WARNING Quartus II version 12 1 with Service Pack 1 or later is required to open this project The latest version of Quartus II is available at no cost for download at www altera com 3 From Quartus II select File gt Open Project Then in the dialog box select the file ninek528 qpf from the folder Click Open to complete the procedure Upon loading of the example design all project settings and assignments are present If you have loaded the example design you do not have to perform the following procedure and may skip to the Required VHDL section However to familiarize yourself with the Quartus II software as well as the settings required for this board it is recommended that you read this procedure and confirm that all s
35. romag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engineering Design Kit 3 The Industrial I O Pack EP2 Series module is a reconfigurable digital input output board The modules use an Altera Cyclone II Field Programmable Gate Array FPGA This allows designers to implement logic functions unique to their application Furthermore the FPGA can be configured in system using either the industry standard JTAG interface or directly through the IP bus The IP EP2 Series Engineering Design Kit contains an example Altera FPGA program including configuration files and the corresponding VHDL source files The example design includes an IP bus interface to ID space IO space and Interrupt space IO space is used to access a 64K x 16 RAM array control field data I O and control a clock generation chip This guide assumes that the user is proficient in the use of VHDL and the Altera Quartus II software tools Prior to editing any of the VHDL code the user should become familiar with the example design as provided by Acromag Do not attempt to reconfigure the FPGA until after you have thoroughly tested the IP EP2 Series module and understand the operation of the various features including the SRAM programmable clock and I O control The IP EP2 Series Engineering Design Kit EDK includes a variety of files to assist the user in their development of the IP EP2 Series Module A
36. rrors and review the warning statements Review the compilation report that will appear on the screen This is also an ideal time to simulate the FPGA using the Quartus II built in simulator The procedure for simulation is beyond the scope of this manual but it is well documented in the Quartus II help files The next step is to program the board Please refer to the appropriate method for detailed instructions on programming the board Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engineering Design Kit 1 3 i PA ee e 2 0 PROGRAMMING The IP EP2 Series module has three methods of configuration e first is configuring the Altera FPGA directly over the IP Bus This method uses THE BOARD the passive serial scheme to directly program the FPGA Note that this technique requires the FPGA to be reprogrammed at power up The second method is to configure the part directly using the JTAG interface The JTAG interface will automatically over write any existing configuration and can be completed at any time using a standard Altera JTAG download cable such as the ByteBlaster 2 This cable is NOT provided by Acromag Once again all programming is lost at power down using the direct JTAG configuration approach Finally the IP EP2 Series module contains a Flash Configuration Device Altera EPCS4 or equivalent that can be programmed indirectly through the JTAG interface us
37. rt address to 0 and the count as up The Intel Format Hexadecimal file is used when programming the FPGA over the IP bus The FPGA direct JTAG programming file is always generated during compilation The indirect FLASH programming file must be created separately Refer to the FLASH programming portion of this manual for further details 14 Select the Unused Pins category IP EP2 Series Programming Guide Engineering Design Kit r a evice ai in Options Device and Pin Opti ninek528c Category General Configuration Programming Files Unused Pins Dual Purpose Pins Capacitive Loading Board Trace Model I O Timing Voltage Pin Placement Error Detection CRC CvP Settings Partial Reconfiguration Configuration Specify the device configuration scheme and the configuration device Note For HardCopy designs these settings apply to the FPGA prototype device Configuration scheme Active Serial can use Configuration Device z Configuration mode Configuration device EPCS4 X 7 Use configuration device Configuration Device Options Configuration dex jO voltage Force VCCIO to be compatible with configuration I O voltage V Generate compressed bitstreams Active serial dock source v Enable input tri state on active configuration pins in user mode Description The method used to load data into the device Two configuration schemes are available
38. summary of the various components of the EDK is given below The Quartus II project Ninek528 contains all of the files and settings necessary to implement the example design as described in the IP EP2 Series User s Manual The primary design files are listed below e NineK528 vhd Top Level Acromag provided VHDL hardware design language source file Supports IP bus interface to ID INT and IO space e Clkgene vhdl Acromag provided VHDL source file Supports the programming of the Cypress Clock IC e DIG_IO_8 vhd Acromag provided VHDL source file Supports 8 channels of digital change of state COS interrupts e Ninek528 qsf Quartus II assignments file This ASCII file contains all required user assignments included FPGA pin assignments and device options e Ninek528 pof Altera specific configuration file This file is generated by the Quartus II software and is used to directly program the FPGA via JTAG e Ninek528 jic Altera specific configuration file This file is generated by the Quartus II software and is used to program the FLASH device via JTAG e Ninek528 hex Hexadecimal Intel Format configuration file The Hex file is an ASCII file in the Intel Hex format This file is generated by the Quartus II software and is used to direct program the FPGA over the IP bus e Ninek528 qpf Altera Quartus Il specific master project file Use to file to open the Quartus II example design project provided on the CD e Ninek528 sdc
39. tial transceivers This includes all differential channels on the EP202 and EP204 The differential direction is controlled in groups of four via DirCtrl bits 0 to 5 The EP203 maps to the lower 24 TTL channels and the upper 12 differential channels The exact mapping of the direction control can be found in the IP EP2 Series User s Manual Acromag Inc Tel 248 295 0310 Engineering Design Kit APPENDIX Pin Assignments Table VHDL Name Pin Direction Schematic Connection pop PNpe Bor pemo gt Dio PN R3 Biar pie Doe Dop Pan vair pe no 777 Fax 248 624 9234 Email solutions acromag com www acromag com IP EP2 Series Programming Guide Engineering Design Kit 23 VHDL Name Pin Direction Schematic Connection FIELD I O SIGNALS DirCtri 1 PIN_R14 Output DIFF_DIR1 LOBAL_DIO18 LOBAL_DIO22 LOBAL_DIO46 PIN ASSIGNMENTS The SRAM Interface pins provide the interconnect between the Cyclone II device and the SRAM Refer to the SRAM data sheet for more information The data sheet is available from the manufacturer s web site listed immediately following the Table of Contents Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com www acromag com 24 IP EP2 Series Programming Guide Engineering Design Kit PIN ASSIGNMENTS The IP Interface pins provide the interconnect between the Cyclone II device and the IP bus Note that each IP line is buffered since the FP
40. udes a VHDL compiler timing analysis tools and more Additionally the EDK does not provide an Altera JTAG download cable This cable is available for purchase from Altera Contact Altera for guidance on which software package or download cable would be appropriate for your use with the Cyclone Il FPGA Where can I find information on the Cyclone Il FPGA Documentation on the Cyclone II FPGA is available from Altera s website at www altera com literature lit cyc2 jsp Where can l find information on the SRAM or Clock Generator IC Documentation of the SRAM IC is available from IDT s website at www idt com Then search for the part 71V016SA Documentation of the Cypress Clock Generator is available from the Cypress website at www cypress com Then search for the part CY22150 Where can l find information on the IP Bus Interface The IP bus specification ANSI VITA 4 1995 is available for purchase from www vita com Why does the IP EP2 module require me to implement wait states The Cyclone II FPGA has a buffer between itself and the IP bus This buffer allows for 5V signaling on the IP carrier Unfortunately the buffer adds an additional 10ns maximum of propagation delay for all IP signals The propagation delay may not allow bus signals to settle during 32MHz operations As such 1 wait state is required for all IP module read write operations to take into account the additional delay of the buffer Engineering Design Kit 1 Q 4 0 TRO
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