Data collection terminal high speed communication link interrupt logic
Contents
1. U S Patent Feb 24 1987 Sheet3 of7 4 646 260 SHEET 2 OF4 377 3 16 4 1 1 1 t 1 D 1 1 1 A4 A6 E 1 3 26 F d INTERNAL l TIMER 6 3 40 i ox 1 1 1 1 7 1 EN O 1 60 1 y 1 SEEN SE 1 Loic LOGIC LL 3 40 5 DEN l nne 9 96 3 44 ES 5 mel 277 prae a ja i TREN 3 42 1 1 3 U S Patent Feb 24 1987 Sheet4of7 4 646 260 m SHEET 3 OF 4 U S Patent Feb 24 1987 Sheet5of7 4 646 260 FIG 2 SHEET 4 OF 4 U S Patent Feb 24 1987 Sheet60f7 4 646 260 BACKGROUND 80 82 INTR YES 84 INTA RECEIVE VECTOR ADDRESS 86 88 90 BRANCH TO ROUTINE PROCESS 92 INTERRUPT 94 WRITE SIGNAL 1 0 SIGNAL Fl G 3 ADDRESS SIGNA 4 646 260 Sheet 7 of 7 U S Patent Feb 24 1987 E SS3HAAV YOLIJA x 240 00 91 6 T t 1 8N31NI p D ERE 1uvsn 232V 119 H 1 1 8 f VINI AAA H NI 4 646 260 1 DATA COLLECTION TERMINAL HIGH SPEED COMMUNICATION LINK INTERRUPT LOGIC RELATED APPLICATION The following U S patent application filed on an even date with the instant application and assigned to the same assignee as the instant application is related to the instant applicati2. United States Patent 11 Patent Number 4 646 260 Chasse et al 45 Date of Patent Feb 24 1987 54 DATA COLLECTION TERMINAL HIGH 4 519 028 5 1985 Olsen et al 364 200 SPEED COMMUNICATION LINK 4 547 849 10 1985 Louie et al 364 200 INTERRUPT LOGIC OTHER PUBLICATIONS 75 Inventors Dennis Chasse Nashua N H MCS 80 85 Family User s Manual Intel Oct 1979 pp David R Bourgeois Framingham 6 132 to 6 137 Todd R Comins Chelmsford both of Mass Primary Examiner James D Thomas Assistant Examiner Thomas Lee 73 Assignee Honeywell Information Systems Inc Attorney Agent or Firm George Grayson John S Waltham Mass Solakian 21 Appl No 538 697 57 ABSTRACT 2 Filed Oct 3 1983 A data collection terminal includes a microprocessor a 51 Int GO6F 13 14 GO6F 15 00 Memory and number of devices coupled to a system 52 cds 364 900 Included among the devices is a communication 58 Field of Search 364 200 MS File 900 MS File controller An interrupt controller processes the device interrupt requests by sending a vector address to the 56 References Cited microprocessor This enables the microprocessor to U S PATENT DOCUMENTS branch to a subroutine to process the interrupt Appara 4 240 140 12 1980 Stafford et al 364 200 tus is provided to enable the communication controller 42255786 3 198
3. control the terminal 1 The RAM and ROM 4 store up to 32K bytes of RAM and 32K bytes of ROM The microprocessor 2 is an Intel 8088 central process ing unit described in the 8086 Family User s Manual October 1979 published by Intel Corporation 3065 Bowers Avenue Santa Clara Calif 95051 Coupled to the microprocessor 2 are a control bus 13 an address bus 15 and a data address bus 17 A number of logic blocks are coupled to busses 15 17 and 19 An input output device 6 provides logic for control ling an RS232 or an RS422 communication line a high signal 20 25 30 35 40 45 55 65 4 speed coaxial cable data link handling a 750 000 bit per second serial data stream and a relay port Up to 32 terminals 1 may be coupled to a central system not shown via the high speed coaxial cable data link The relay port controls a relay to control typically an external device such as a door lock solenoid for secure access to an area in the factory or turn on an alarm for work shift changes An interface personality logic 8 couples the ATC board 3 to the APCP board 5 via a control bus 37 an address bus 9 and a data bus 11 and an interface daugh ter board logic 10 couples the ATC board 3 to a number of daughter boards The ATC board 3 can support up to 3 daughter boards A decoder 12 receives control signals and address signals from the microprocessor 2 over busses 13 and 15 to generate control signals over bus 19 a
4. enable signals to activate the logic of a selected daughter board Peripheral control signals are transferred between the daughter boards and the interface daughter boards 10 via a control bus 25 FIG 2 shows the interrupt operation of the periph eral devices The microprocessor 2 controls the opera tion of the elements of terminal 1 As an example if a peripheral device requires a transfer of information between RAM and ROM 4 and the device a unique signal is generated by the peripheral device Sensing this signal causes one of the interrupt controllers to interrupt the microprocessor 2 which acknowledges the interrupt The interrupt controller responds to the ac knowledge signal by generating a unique vector ad dress microprocessor 2 receives the unique vector ad dress and branches to a microprogram which controls the information transfer Other interrupt signals are generated by the peripheral device to inform the micro processor 2 that a particular event has occurred for example a badge is inserted in the badge reader This conditions the microprocessor 2 to branch to a micro program to receive data read from the badge Since the microprocessor 2 is controlling all of the functions of terminal 1 the interrupt operation allows for efficient control of the terminal 1 by the micro processor 2 The microprocessor 2 processes two classes of inter rupts from the peripheral devices The first class of interrupt having a higher prio
5. forcing output signal ACK2 the output of a negative AND gate 3 6 to logical ONE This forces signal IPI the output of negative NAND gate 3 10 to logical ZERO If a device other than USART 3 16 requested an interrupt of interrupt controller 3 24 then when micro processor 2 generates the first occurrence of interrupt acknowledge signal INTA in response to interrupt signal INTR interrupt controller 3 24 generates cas cade signals CASO CAS1 and CAS2 which address either interrupt controller 18 2 or 18 4 Signal IN TENB 02 the output of NAND gate 3 14 is at logical ONE and signal INTENB the output of inverter 3 8 is at logical ZERO The first occurrence of interrupt acknowledge signal INTA at logical ZERO is ap plied to an inverter 3 5 to generate signal INTA at logical ONE Flop 3 4 is set on the fall of signal INTA that is as the interrupt acknowledge signal INTA goes to logical ONE Signal ACK1 is set to logical ZERO forcing signal ACK2 to logical ZERO thereby forcing signal IPI to logical ONE This conditions USART 3 16 to ignore the second oc currence of interrupt acknowledge signal INTA However flop 3 4 is reset at the end of the second occurrence of interrupt acknowledge signal INTA by 25 30 35 45 55 60 65 10 the fall of signal INTA Flop 3 4 is a 745112 circuit element described in the TTL Data Book for Design Engineers Second Edition published by
6. interrupt controller 3 24 which responds by generating microprocessor 2 inter rupt signal INTR Microprocessor 2 generates the first occurrence of interrupt acknowledge signal INTA which is received by interrupt controller 3 24 Interrupt controller 3 24 generates the cascade signal CASO at logical ONE and cascade signals CAS1 and CAS2 at logical ZERO which are applied to a negative NAND gate 3 12 and a NAND gate 3 14 to generate signal INTENB 02 at logical ZERO and signal IN TENB the output of an inverter 3 8 to logical ONE Signal INTENB at logical ONE applied to a negative NAND gate 3 10 forces signal IPI to logical ZERO This conditions USART 3 16 to respond to the second occurrence of interrupt acknowledge signal INTA by sending the vector address signals DO through D7 cor responding to the operation required by USART 3 16 to microprocessor 2 via transceiver 3 30 Transceiver 3 30 is enabled by signal INTENB 02 at logical ZERO negative NOR gate 3 36 NAND gate 3 44 and signal XEN 01 at logical ZERO The direction signal DTREC conditions XCVR 3 30 to transfer vector address signals DO through D7 to microprocessor 2 as signals ADO through AD7 Initially signal IPI is at logical ZERO to condition USART 3 16 to generate an interrupt request Flop 3 4 is reset by signal ORDRST on power up or microprocessor 2 Output signal is at logical ONE as is interrupt acknowledge signal INTA thereby
7. signal IOMEM to gener ate signal IORD including an input output read oper ation signal Signal IOMEM is generated by an in verter 3 37 Signal IOMEM 4 is generated by micro processor 2 to indicate an input output operation FIG 3 shows a block diagram of the microprocessor interrupt microprogram Block 80 shows the micro processor 2 executing a background microprogram Periodically decision block 82 is tested to determine if microprocessor interrupt signal INTR was gener ated by interrupt controller 3 24 If signal INTR was not received then microprocessor 2 continues to exe cute the background microprogram When signal INTR is received and tested by deci sion block 82 the interrupt microprogram branches to block 84 which generates the first occurrence of inter rupt acknowledge signal INTA Block 86 then generates the second occurrence of interrupt acknowledge signal INTA Block 88 receives the vector address which is used in block 90 to branch to a microprogram to process in block 92 the particular device requesting the interrupt After the interrupt is processed block 94 generates signals WRITE IOMEM to generate signal IOWR and address signals A4 through A7 which are applied to decoder 3 10 to generate signal Y11 Signals Y11 and IOWR are applied to nega tive AND gate 18 10 to enable decoders 18 6 and 18 8 to generate the clear interrupt signals FIG 4 is a timing di
8. slave interrupt controller is addressed it responds to the second occurrence of the interrupt acknowledge signal INTA with the vector address of the request ing device that received access to the microprocessor by requesting access from that slave interrupt control ler 4 646 260 3 If the USART 3 16 generated its interrupt request signal IRQI then the master interrupt controller 3 24 generates the microprocessor 2 interrupt INTR The microprocessor 2 responds with the first occurrence of interrupt acknowledge signal INTA which is received by master interrupt controller 3 24 which generates the cascade signal CASO at logical ONE and signals CAS1 and CAS2 at logical ZERO Addressing the USART by the cascade signals forces the IPI signal to logical ZERO This conditions the USART 3 16 to accept the second occurrence of inter rupt acknowledge signal INTA to generate the vec tor address indicative of the operation being performed by the USART 3 16 When the cascade signals do not address the USART 3 16 then signal IPI is forced to logical ONE This results in the USART 3 16 not responding to the second occurrence of interrupt acknowledge signal INTA Signal IPI is forced to logical ONE by setting a flop 3 4 at the end of the first occurrence of interrupt ac knowledge signal INTA forcing signal ACK1 to logical ZERO The second occurrence of interrupt acknowledge signal INTA forces signal ACK2 t
9. terminal IRQ1 of interrupt controller 18 2 Signal MGEOR indicates that the mag netic wand logic 30 finished reading the document Interrupt signals BD BIS and BFSI of badge reader logic 26 are applied to interrupt terminals IRQ2 IRQ3 and IRQ4 respectively of interrupt controller 18 2 Signal BD indicates that badge reader logic 26 has data to transfer to the RAM of RAM and ROM 4 Signal BIS indicates that the badge is inserted in the badge reader and signal BFSI indicates that the badge is fully seated in the badge reader Interrupt signal KED is applied to interrupt terminal IRQS of interrupt controller 18 2 indicating that key board logic 22 has data to transfer to the RAM of RAM and ROM 4 Interrupt signals CBD CI TED COE CP and CIS from multifunction reader logic 34 are applied to inter rupt terminals IRQO through IRQS respectively of interrupt controller 18 4 Signal CBD indicates that the multifunction reader logic 34 has data to transfer to RAM and ROM 4 Signal CI indicates that a card is inserted into the reader Signal TED indicates that the trailing edge of the card has passed through the reader Signal COE indicates that there was a card oriented error Signal CP indicates that a card is present in the reader Signal CIS indicates that column one of the card is under the read head of the reader These interrupt signals indicate to the microprocessor 2 to start the reader motor to feed the card when the CI signal is a
10. 1 Holt d ei xix d rein 364 200 to generate vector addresses when it sends an interrupt 4 275458 6 1981 Khera n 364 900 Tequest to the interrupt controller 4 349 873 9 1982 Gunter et al 364 200 4 479 179 10 1984 Dinwiddie Jr 364 200 14 Claims 4 Drawing Figures INTR INTA ACKI ACK2 INTENB DO D7 VECTOR ADDRESS USART 3 16 o SAN LE L USART 3 167 sna vive 4 21901 91901 39IA30 lt 4 646 260 STVN9IS 2 1 1 2 Sqdvog H31H9hvO 7 VH3Hdlu3d SQuvog YILHINVO 39V3M31NI sng ss3yady 125 TJOHLNOD Sheet 1 of 7 54 yozezsy 9 os EM g 21901 21901 GNVOBA33 be CC tt Ss o DE AM t ssaudav vivd 1 awa 5535007 HOSSIIOYJOYIIM 011231102 VIVA 19 i IN TOHLNO 2 7 i el si E e 21 U S Patent Feb 24 1987 U S Patent Feb 24 1987 Sheet20f7 4 646 260 dr MONATE S FIG 2 mE ORG SHEET OF4 3 5 F F 0 INTA Poy INTAS B po AN 3 10 ORDRST p ACKg q olNTENB INTENB 02 3 8 8 T 3 28 XCVR DO D7 8 E INTR 3 30 00 07 8 AO A7 8 ionene
11. S of slave interrupt con troller 18 4 has the lowest priority of all of the signals applied to the IRQ input terminals of interrupt control lers 3 24 18 21 and 18 3 The interrupt logic operates in the following manner Assume the multifunction reader logic 34 generates signal COE which is applied to interrupt controller 18 4 indicating that the card is not oriented properly in the reader The interrupt controller 18 4 responds by gener ating signal IRQ7 which is applied to the interrupt terminal IRQ7 of interrupt controller 3 24 Interrupt controller 3 24 generates interrupt signal INTR which is applied to microprocessor 2 which acknowl edges the interrupt by generating interrupt acknowl edge signal INTA Interrupt controller 3 24 is re sponsive to signal INTA by generating CASO CASI and CAS2 identifying the interrupt controller 18 4 which initiated the interrupt request In response to signals CASO CAS1 and CASA interrupt controller 18 4 generates signal EN2 at logical ZERO which is applied to a negative OR gate 18 6 to generate output signal TREN at logical ZERO which is inverted by an inverter 3 41 to signal TREN Signal DEN from an inverter 3 40 at logical ONE is applied to a NAND gate 3 42 to generate signal XEN 03 at logical ZERO Signal XEN 03 enables a XCVR 3 28 and a XCVR 18 8 Signal DTREC 4 from microprocessor 2 is ap plied to the direction selection terminals of XCVR s 18 8 and 3 28 to transfer vector sig
12. Texas Instru ments 1976 During a status write operation a register ICW2 3 25 in interrupt controller 3 24 and a register ICW2 18 5 in interrupt controller 18 4 are loaded with the vector address for the respective IRO interrupt terminal The outputs of these registers are incremented by the prior ity position IRQO through IRQ7 to generate the vec tor address To write the initial vector address in register 3 25 of interrupt controller 3 24 microprocessor 2 generates a number of signals Address signal A0 from register 3 32 indicates status operation signal WRITE indicates that the interrupt controller 3 24 will receive data and signal DEVS2 generated from microprocessor 2 ad dress signals selects interrupt controller 3 24 The bool ean equation for DEVS2 is as follows where signal IOMEM 4 indicates an input output op eration and not a RAM and ROM 4 operation If signal READ is applied to interrupt controller 3 24 in place of the signal WRITE then the contents of register ICCW2 18 3 are transferred to microprocessor 2 Registers ICW2 18 3 ICW2 18 5 are loaded in a similar manner Signal Y8 from decoder 3 20 selects interrupt controller 18 4 Again address signal 0 indi cates the status mode Signal WRITE is applied to negative AND gate 3 38 along with signal IOMEM to generate signal IOWR indicating an input output write operation Signal READ is applied to negative AND gate 3 36 along with
13. agram showing the interrupt logic sequence control of the USART 3 16 enable signal IRQ indicates a request by a peripheral device which is applied to an interrupt controller INTR shows the 4 646 260 11 timing of the interrupt signal INTR generated by interrupt controller 3 24 to interrupt microprocessor 2 indicates the timing of the interrupt ac knowledge signal with the first occurrence at A time and the second occurrence at B time ACKI indicates the setting of flop 3 4 at the time of the rise of the first occurrence of INTA and the reset ting of flop 3 4 at the time of the rise of the second occurrence of ACK2 shows the output signal timing of negative AND gate 3 6 Its timing coincides with the timing of the second occurrence of INTA INTENB indicates that USART 3 16 generated our interrupt request dotted and that another device generated an interrupted request solid IPI dotted indicates that USART 3 16 requested an interrupt and IPI solid indicates that USART 3 16 did not request an interrupt and will therefore not respond to the interrupt acknowledge signal INTA D0 through D7 shows the timing of the vector ad dress sent to microprocessor 2 from interrupt controller 3 24 18 2 18 4 or USART 3 16 Having shown and described a preferred embodiment of the invention those skilled in the art will realize that many variations and modification may be made to affe
14. as universal synchro nous asynchronous remote transmit controllers OBJECTS OF THE INVENTION It is accordingly a primary object of the invention to provide an improved operation of a data collection system It is another object of the invention to provide im proved apparatus for processing device interrupts It is another object of the invention to provide im proved apparatus for processing interrupts from a cer tain class of devices including communication control lers SUMMARY OF THE INVENTION A data collection terminal includes a number of de vices including a universal synchronous asynchronous receive transmit USART communication controller a random access memory a read only memory and a microprocessor coupled to a common bus Devices bid against each other for access to the com mon bus by generating their respective interrupt request signal Master interrupt controller 3 24 receives the interrupt request signals from certain devices or from slave interrupt controller 18 2 or 18 4 and generates a microprocessor interrupt signal The microprocessor responds to its interrupt signal by generating two occurrences of an interrupt acknowl edge signal INTA The master interrupt controller 3 24 responds to the first occurrence of the interrupt acknowledge signal INTA by generating cascade signals CASO CAS1 and CAS2 which address slave interrupt controller 18 2 slave interrupt controller 18 4 or USART 3 16 If a
15. ct the described invention and still be within the scope of the claimed invention Thus many of the elements indi cated above may be altered or replaced by different elements which will provide the same result and fall within the spirit of the claimed invention It is the inten tion therefore to limit the invention only as indicated by the scope of the claims What is claimed is 1 A data collection terminal comprises microprocessor means a plurality of first devices and at least one second device each of said plurality of first devices and said at least one second device being coupled to a respective one of a plurality of interrupt request signal lines one of said plurality of first devices and said at least one second device generating one of a plurality of interrupt request signals on said one of said plurality of interrupt request signal lines when said one of said plurality of first devices and said at least one second device requires said microproces sor means to process an interrupt interrupt controller means coupled to said each of said plurality of interrupt signal lines for receiving said one of said plurality of interrupt request signals and generating a microprocessor interrupt signal said each of said plurality of interrupt signal lines being coupled to said interrupt controller means establishing a predetermined priority in accor dance with a terminal of said interrupt controller means to which said each of said p
16. d communi cation controller requires said microprocessor means to process the interrupt said master inter rupt controller means being coupled to said inter nal timer and receiving a second of said plurality of interrupt request signals from said internal timer for generating said microprocessor interrupt signal when said internal timer requires said microproces sor means to process the interrupt said master interrupt controller means being coupled to said bar code reader and receiving a third of said plural ity of interrupt request signals for generating said microprocessor interrupt signal when said bar code reader requires said microprocessor means to pro cess the interrupt 5 The terminal of claim 4 wherein said first and said second occurrence of said interrupt acknowledge signal each has a leading edge at the start of the signal and a trailing edge at the finish of the signal 6 The terminal of claim 5 wherein said selection means comprises 4 646 260 13 first selection means for generating a first acknowl edge signal in a second state prior to said first oc currence of said interrupt acknowledge signal and second selection means coupled to said first selection means and responsive to said first acknowledge signal in said second state for generating said en able signal in a first state said communication con troller being responsive to said enable signal in said first state for generating said one of said plurality o
17. er 18 6 disables decoder 18 6 Signal Y11 is 20 25 30 35 40 50 55 60 65 8 generated by address signals A4 through A7 ap plied to a decoder 3 20 via a register 3 32 signals AD4 through AD7 and microprocessor 2 Signal 7 the output of an inverter 3 40 enables decoder 3 20 Register 3 32 is enabled by the microprocessor 2 address latch enable signal ALE Signal IOWR indi cates a microprocessor 2 input output write control signal which is generated by a microinstruction to cause a clear interrupt operation Signal WRITE and IOMEM at logical ZERO applied to a negative AND gate 3 38 generates the IOWR signal at logical ZERO Signals DAO and DA1 at logical ONE signals DA2 and DA3 at logical ZERO and signal DA4 at logical ONE generates the card error interrupt clear signal COECL which is applied to multifunction reader logic 34 to reset the card error interrupt The other clear signals from decoders 18 6 and 18 8 are generated in a similar manner Assume the magnetic wand logic 30 generates an end of read interrupt signal MGEOR which is applied to interrupt terminal IRQ1 of interrupt controller 18 2 which generates signal IRQ6 Signal IRQ6 is ap plied to interrupt terminal IRQ6 of interrupt controller 3 24 Signal INTR interrupts microprocessor 2 which generates interrupt acknowlege signal INTA indicat ing that microprocessor 2 is conditioned to accept the interrupt Interrupt contro
18. essor 2 via signals DO through D7 XCVR 3 30 and signals ADO through AD7 The vector address signals are used by the microprocessor 2 to branch to the first microwords of the microprogram which pro cesses the internal timer 3 26 Interrupt signals IRQ3 IRQ4 and IRQ5 are processed in a similar manner to the signal IRQ24 from internal timer 3 26 s The interrupt operation of the USART 3 16 operates differently than the other peripheral devices in terminal 1 in that USART 3 16 generates its own vector ad dresses Note that the interrupt controller generates the vector address for those peripheral logic units which are coupled to that interrupt controller Since 4 646 260 9 USART s may generate a number of different vector addresses representing different modes of operation the interrupt operation is speeded up by having the USART generates the vector address As an example one vector address generated by the USART may point to a microprogram for processing a communication line receive transmission another vector address may point to a microprogram for processing a communication line transmit transmission The USART 3 16 is an Intel 8274 described in the Microprocessor and Peripheral Hand book 1983 published by Intel Corporation If the USART 3 16 requested access to microproces sor 2 then signal IRQ1 which is applied to an inverter 3 18 is generated Output signal IRQ is applied to the IRQ1 interrupt terminal of
19. f interrupt request signals if said communication controller requires said microprocessor means to process said interrupt 7 The terminal of claim 6 wherein said first selection means generates said first acknowledge signal in a sec ond state after said first and said second occurrences of said interrupt acknowledge signal 8 The terminal of claim 7 wherein said selection means further comprises third selection means coupled to receive a first plural ity of cascade signals addressing said one of said at least one second device for generating a second acknowledge signal in a second state 9 The terminal of claim 8 wherein said second selec tion means is coupled to receive said second acknowl edge signal in said second state for generating said en able signal in said first state said communication con troller being coupled to receive said enable signal in said first state and said second occurrence of said interrupt acknowledge signal for generating said second plurality of vector address signals 10 The terminal of claim 9 wherein said third selec tion means is coupled to receive a second plurality of cascade signals for generating said second acknowledge signal in a first state said second selection means being coupled to receive said second acknowledge signal in said first state for generating said enable signal in a second state said communication controller being cou pled to receive said enable signal in said second state
20. for not responding to said second occurrence of said inter rupt acknowledge signal 11 The terminal of claim 10 wherein said first selec tion means comprises a flip flop having means for resetting and generating a third acknowledge signal in a second state said 10 15 25 30 45 55 65 14 flip flop being set by said trailing edge of said first occurrence of said interrupt acknowledge signal thereby generating said third acknowledge signal in a first state a negative AND gate coupled to receive said third acknowledge signal in said second state for gener ating said first acknowledge signal in said second state and coupled to receive said third acknowl edge signal in said first state and said first occur rence of said interrupt acknowledge signal for gen erating said first acknowledge signal in said first state 12 The terminal of claim 11 wherein said third selec tion means comprises a first negative NAND gate coupled to receive a second cascade signal in a first state and a third cascade signal in a first state for generating a fourth cascade signal in a second state a positive NAND gate coupled to receive a first cas cade signal in a second state and said fourth cas cade signal in said second state for generating said select signal in a first state and an inverter coupled to receive said select signal in said first state for generating said second acknowl edge signal in said second state said f
21. irst cascade signal in said second state and said second and said third cascade signals in said first state forming said first plurality of said plurality of cascade signals 13 The terminal of claim 12 wherein said second selection means comprises a second negative NAND gate coupled to receive said first acknowledge signal in said second state or said second acknowledge signal in said second state for generating said enable signal in said first state 14 The terminal of claim 13 wherein said first selec tion means is shared by said each of said at least one second device and wherein said selection means in cludes a plurality of said second and said third selection means one of said plurality of said second and said third selection means being associated with said each of said at least one second device
22. ller 3 24 responds to the fall of signal INTA by generating signals CASO CASI and CAS2 Interrupt controller 18 2 responds to signals CASO CASI and CAS2 by sending out its vector ad dress on the data bus Again XCVR s 3 28 and 18 8 are enabled to transfer the vector address to microproces sor 2 The vector address is stored in register 18 12 on the rise of the interrupt acknowledge signal INTA In this case decoder 18 6 is enabled and signal WGEORCL is generated to clear the end of read interrupt signal WGEOC in magnetic wand logic 30 A number of peripheral devices generates interrupt request signals which are applied directly to master interrupt controller 3 24 Assume that an internal timer 3 26 generates an interrupt signal IRQ2 when a pre timed event occurred The interrupt controller 3 24 generates signal INTR 4 to interrupt the microproces sor 2 which generates the interrupt acknowledge signal INTA The interrupt controller 3 24 responds to the second occurrence of the fall of signal INTA to gen erate signal INTENB 01 which enables XCVR 3 30 via a negative NOR gate 3 36 a NAND gate 3 44 signal XEN 01 and XCVR 3 30 The direction of the signal accepted by XCVR 3 30 is specified by transmit receive signal DTREC from microprocessor 2 The interrupt controller 3 24 is responsive to the second occurrence of interrupt acknowledge signal INTA to generate the vector address signals which it sends to micro proc
23. lurality of inter rupt signal lines is coupled said microprocessor means being coupled to said interrupt controller means for receiving said mi croprocessor interrupt signal and generating a first and a second occurrence of an interrupt acknowl edge signal when said microprocessor means is ready to process the interrupt said interrupt controller means being coupled to said microprocessor means to receive said interrupt acknowledge signal for generating a plurality of cascade signals on first occurrence of said interrupt acknowledge signal when said one of said plurality of first devices and said at least one second device 15 20 25 35 40 45 50 65 12 generates said one of said plurality of interrupt request signals said interrupt controller means generating a first plurality of vector address signals on second occurrence of said interrupt acknowl edge signal when said one of said plurality of first devices generated said interrupt request signal said one of said at least one second device including selection means for generating an enable signal thereby enabling said one of said at least one sec ond device to generate said one of said plurality of interrupt request signals said selection means being coupled to said interrupt controller means to receive a first plurality of said plurality of cascade signals when said one of said at least one second device generated said interrupt request signal and on receipt
24. nals that the magnetic wand read the information correctly from the card The multifunction reader logic 34 includes interfaces to a number of devices not shown including typically a motorized reader The motorized reader is capable of reading 80 and 60 column cards as well as 22 column plastic badges The display logic 24 controls a one row by 40 charac ter display which is capable of displaying the full ASCII character set in several modes including a cursor mode a mode for inserting or replacing characters a blinking mode or a mode for turning the display on or off The keyboard logic 22 includes a sealed laminated keyboard using membrane technology not shown which is used for data entry The audio visual indicator logic 20 controls audible alarms and LED indicators to give the operator infor mation that the inputs to the terminal 1 were in the proper format and that the proper input procedures were used The interrupt control logic 18 receives interrupt re quests from the other control logic blocks on the APCP board 5 and couples the highest priority device to the 4 646 260 5 ATC board 3 for transfer of information between the device and RAM and ROM 4 under microprocessor 2 control The interrupt control logic 18 also under firm ware or software control causes the peripheral devices to be activated or deactivated Bidirectional data bus 1 40 is coupled to the interface personality logic 8 via a transceiver XCVR 14 a
25. nals generated by interrupt controller 18 4 when interrupt controller 18 4 receives a second interrupt acknowledge signal from microprocessor 2 that is on the fall of the second INTA signal The vector signals IDB 0 7 are applied to microprocessor 2 via XCVR 18 8 signals 00 07 XCVR 3 28 and signals ADO through AD7 Microprocessor 2 uses the vector sig nals to generate the starting address in RAM and ROM 4 of a microprogram which will process the card ori ented error routine For the interrupt clear operation the vector signals 0 through IBD4 are stored in a register 18 12 on the rise of the second interrupt acknowledge signal INTA Output signals DAO through DA4 are applied to the input terminals of decoders 18 6 and 18 8 Signals DAO through DA2 applied to select terminals 0 1 and 2 select one of eight output terminals of decoders 18 6 and 18 8 The interrupt clear operation is controlled by microprocessor 2 generating signals Y11 and IOWR at logical ZERO which are applied to a nega tive AND gate 18 10 Output signal DIS at logical ZERO enables both decoders 18 6 and 18 8 Signal DA3 at logical ONE applied to terminal G1 of decoder 18 6 enables decoder 18 6 and signal DA4 at logical ONE applied to terminal G1 of decoder 18 8 enables decoder 18 8 Signal DA3 at logical ONE applied to terminal G2A of decoder 18 8 disables decoder 18 8 and signal DA4 at logical ONE applied to terminal G2A of decod
26. nd data bus 11 Bidirectional data bus 2 42 is coupled to the interface personality logic 8 via a transceiver 48 and data bus 11 A buffer 46 applies address signals received via an address bus to a device selection 48 which generates a separate peripheral enable signal for each peripheral device logic block on the APCP board 5 Only one peripheral device may be enabled for a data cycle on data bus 1 40 or data bus 2 42 A buffer 16 receives control signals from control bus 7 for transfer to the peripheral device A number of control signals are transferred to control bus 7 from the peripheral devices These control signals are described infra A number of peripheral devices are coupled to the interface daughter boards 10 via a data bus 21 a XCVR 62 and data bus 3 44 These devices include a bar code reader not shown coupled to data bus 3 44 via a bar code reader logic 56 and a number of unspecified de vices coupled to data bus 3 44 via special 1 logic 56 and special 2 logic 60 Whereas each of the logic blocks coupled to the interface personality logic are mounted on the APCP board 5 the three logic blocks bar code reader logic 56 special 1 logic 58 and special 2 logic 60 coupled to the interface daughter boards 10 are mounted on individual daughter boards which are phys ically connected to the ATC board 3 A buffer 52 receives address signals from address bus 23 which are applied to device selection 54 Device selection 54 provides
27. nd receives control signals over bus 19 for transfer to the micro processor 2 over bus 13 A number of types of APCP boards are available One type of APCP board 5 may provide the terminal 1 with a labor reporting personality wherein the terminal 1 provides manufacturing information or another APCP board 5 may perform as a timeclock In general the APCP board 5 contains a number of peripheral logical blocks Another type of APCP board 5 for labor reporting would include typically a badge reader logic 26 a reset control logic 28 a magnetic wand logic 30 a magnetic wand indicator 32 and a multifunction reader interface logic 34 all coupled in common to a data bus 2 42 and an interrupt control logic 18 an audio visual indicator logic 20 a keyboard logic 22 and a display logic 24 all coupled in common to a data bus 1 40 The badge reader logic 26 interfaces an employee identification badge reader not shown to the terminal 1 This provides the terminal 1 with the information necessary to identify the terminal 1 operator who is providing input information The reset control logic 26 gives the software and firmware reset control over the devices coupled to the APCP board 5 The magnetic wand logic 30 allows a hand held magnetic wand not shown and a swipe reader not shown to read infor mation on credit cards or similar documents The magnetic wand indicator 32 controls the indica tors on the magnetic wand to give the operator sig
28. o logical ZERO Since the cascade signals do not address USART 3 16 signal INTENB is at logical ZERO forcing signal IPI to logical ONE Flop 3 4 is reset at the end of the second occurrence of interrupt acknowl edge signal INTA BRIEF DESCRIPTION OF THE DRAWINGS The novel features which are characteristic of the invention are set forth with particularity in the ap pended claims The invention itself however both as to organization and operation may best be understood by reference to the following description in conjunction with the drawings in which FIG 1 is a block diagram of the data collection termi nal FIG 2 is a logic diagram of the interrupt system FIG 3 is a block diagram of the microprocessor interrupt microprogram and FIG 4 is a timing diagram of the interrupt logic asso ciated with a universal synchronous asynchronous re ceive transmit communication controller DESCRIPTION OF THE PREFERRED EMBODIMENT FIG 1 is a logic block diagram of a factory data collection terminal 1 The logic elements are mounted on two logic boards a terminal controller board ATC 3 and a personality controller panel board APCP 5 A number of optional daughter boards 7 may be added to the ATC board 3 The ATC board 3 provides the logic for controlling the terminal 1 This logic includes mi croprocessor 2 which operates with microinstructions and data stored in a random access memory RAM and read only memory ROM 4 to
29. of sources such as peripherals connected to an input output bus Typi cally the procedure followed for servicing interrupts from such peripherals first requires identifying the inter rupting peripherals next requesting the status of the peripheral and then updating the status This procedure is relatively slow and in certain types of systems where interrupt routines are executed frequently the acknowl edge routine time may pose serious speed restraints on the total system In one such interrupt system as indi cated in U S Pat No 3 881 174 the interrupt process ing apparatus includes a computer which allows a pe ripheral upon receiving an acknowledgement from computer of an interrupt request which the peripheral previously generated to simultaneously provide the computer with its address and status This shortens the time required for processing the interrupt routine U S Pat No 4 030 075 describes a data processing system having a distributed priority network This pri ority network is coupled with each of the units and indicates which is the highest priority unit requesting to transfer information over the bus The priority network includes a priority bus with the units coupled closest to one end of the bus having a highest priority and units coupled at the other end of the bus having a lowest priority All of the above systems have the disadvantage of having considerable hardware and time consuming cycles to perform the c
30. on and is incorporated herein by reference Data Collection Terminal Interrupt Structure by Vincent M Clark Jr David R Bourgeois Dennis W Chasse and Todd R Comins having U S Ser No 538 695 and filed on Oct 3 1983 now abandoned BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates generally to data collection terminals This invention relates particularly to appara tus for processing device interrupt signals including such devices as communication controllers 2 Description of the Prior Art A data collection terminal is made up of a number of peripheral devices and a microprocessor all coupled to a common bus When a peripheral device requests at tention it sends an interrupt signal on the bus to the microprocessor In the prior art system a central pro cessor would poll the devices to determine which de vice interrupted The central processor would then process the interrupt and generate a unique interrupt vector address on the bus This required the central processor to utilize hardware and firmware to poll all the devices in the subsystem prioritize those devices with active interrupts and generate the unique interrupt vectored address to enter into the firmware interrupt service routine There are various other types of interrupt processing systems in the prior art which are coupled to provide interrupt service in response to an interrupt signal re ceived from any one of a number
31. onnection to the bus 10 15 45 55 60 65 2 The Honeywell 7760 display system is a central pro cessor subsystem which controls a fixed number of peripheral subsystems The 7760 is described in the VIP 7760 Subsystem User s Reference Manual Order No AT45 Rev 0 May 1978 Each peripheral subsystem sends a unique request for an interrupt signal to the central processor subsystem which makes the highest priority peripheral subsystem operative in the display system The number of periph eral subsystems in the display system is limited to the throughput capability of the central processor subsys tem The interrupt and priority apparatus in the display system can readily process interrupts from the maxi mum number of peripheral subsystems U S Pat No 4 240 140 describes priority interrupt apparatus for generating vectored addresses which does not have the versatility of the instant invention The Intel 8259A Programmable Interrupt Controller provides for more efficient interrupt operation by pro viding the capability of being used as a master and a slave whereby readily handling up to 64 vectored pri ority interrupts The Intel 8259A controller is described in the Component Data Catalog 1981 published by Intel Corporation 3065 Bowers Avenue Santa Clara Calif 95051 However the prior art still limits the throughput of such proposal devices such as document handlers and communication cardholders such
32. pplied to interrupt controller 18 4 and to stop the reader motor when the TED signal is applied to the interrupt controller 18 4 The CP signal applied to the interrupt controller 18 4 results in the interrupt control ler 18 4 indicating to the microprocessor 2 that the card is in the reader and to await signals CIS and CBD to transfer data to RAM The COE signal applied to inter rupt controller 18 4 results in microprocessor 2 branch ing to an error routine which will delete from the RAM of RAM and ROM 4 any data stored in memory which was read from that card and indicates to the operator that the punched card should be reinserted if the infor mation in the punched card is correct In the event that a number of the devices requests access to RAM and ROM 4 by generating their respec tive interrupt signals those devices having their inter 4 646 260 7 rupt signals coupled to interrupt controller 3 24 receive first or higher priority those devices having their inter rupt signals coupled to interrupt controller 18 2 receive second priority and those devices having their inter rupt signals coupled to interrupt controller 18 4 receive third or lowest priority Within an interrupt controller the IRQO input terminal has highest priority and the IRQ7 terminal has lowest priority In summary signal 1 applied to input terminal IRQ1 of master inter rupt controller 3 24 has highest priority and signal CIS applied to input terminal IRQ
33. rity are those operations whereby data is being transferred between the periph eral device and RAM and ROM 4 The second class of interrupt having a lower priority are those operations 20 25 30 35 40 45 60 65 6 whereby the peripheral device is presenting a status of punched card or badge in a reader Microprocessor 2 is responsive to that interrupt to generate signals which are decoded to for example turn on a card reader motor or to activate a badge read mechanism Terminal 1 includes an interrupt controller 3 24 which acts as a master interrupt controller and two interrupt controllers 18 2 and 18 4 which act as slave interrupt controllers Coupled to the master interrupt controller 3 24 is the interrupt signal IRQ1 for a uni versal synchronous asynchronous remote transceiver USART 3 16 interrupt signal IRQ2 for an internal timer 3 26 interrupt signal IRQ3 for the bar code reader 56 interrupt signal IRQ4 for special 1 logic 58 and interrupt signal IRQ5 for special 2 logic 60 pe ripheral controllers Note that special 1 logic 58 and special 2 logic 60 refer to undefined peripheral devices and controllers to be installed in the future Interrupt signal MG is applied to interrupt terminal IRQO of interrupt controller 18 2 Signal MG indi cates that the magnetic wand logic 30 is ready to trans fer data signals to RAM and ROM 4 Interrupt signal MGEOR from magnetic wand logic 30 is applied to interrupt
34. thereof to address said one of said at least one second device and to gener ate said enable signal on said second occurrence of said interrupt acknowledge signal said one of said at least one second device generating a second plurality of vector address signals on receipt of said enable signal and said second occurrence of said interrupt acknowledge signal said microprocessor means receiving said first vector address signals from said interrupt controller means when said one of said plurality of first de vices generated said interrupt request signal and said second vector address signals from said one of said second devices when said one of said at least one second device generated said interrupt request signal for branching to a microprogram to process the interrupt 2 The terminal of claim 1 wherein said at least one second device includes a communication controller wherein said predetermined priority of said communi cation controller is a first priority 3 The terminal of claim 2 wherein said plurality of first devices includes an internal timer having a second priority and a bar code reader having a third priority 4 The terminal of claim 3 wherein said interrupt controller means comprises master interrupt controller means coupled to said communication controller and receiving a first of said plurality of interrupt request signals from said communication controller for generating said mi croprocessor interrupt signal when sai
Download Pdf Manuals
Related Search