FC6301 User Manual - 4DSP LLC
Contents
1. 11 4 3 1 Gigabit Ethernet nessen nnn nenne net 11 4 92 asas 11 4 3 8 LED 11 44 FPGA Mezzanine Card FMC 12 4 4 1 Bank A LA HA connections r enna 12 44 2 Bank B HB connections tiie 15 4 4 3 Gigabit transceiver connections 00nxnmwennnennnnnnnnnannnnnnannnnnnanna 16 4 4 4 Miscellaneous FMC connections uussssssnssssennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn ern 17 MNS ages 18 46 Virt x 6 FPGA device une UI E MUR E 18 47 BLAST SIISE metere 19 20 or ae 19 48 1 FMC GTX Reference Clock 20 4 8 2 FMC Clock connections nennen nnne 20 49 FPGA device configuration uuss44nnnnnnnnnannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnn 21 494 Flash storage ae E IM 21 4 9 2 NOW IERI o Saas 21 2933 DIP SGI 21 4 9 4 CPLD LEDs and board status ze ee 22 1835 WA2. CoolRunner Il J CPLD Virtex 6 Y XC2C256 VQ100 8 bit parallel configuration DIP switch LED x4 Figure 6 Configuration circuit 4 9 2 CPLD device As shown on Figure 4 a CPLD is present on board to interface between the flash device and the FPGA device It is of type CoolRunner Il The CPLD is used to program and read the flash The data stored in the flash is transferred from the host motherboard via the PCI bus to the Virtex 6 device and then to the CPLD that writes the required bit stream to the storage device A 50MHz clock connects to the CPLD and is used to generate the configuration clock sent to the FPGA device At power up if the CPLD detects that an FPGA configuration bitstream is stored in the flash it will start programming the FPGA device in SelectMap mode The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from a host computer via the JTAG connector The FPGA device configuration can also be performed using the JTAG chain 4 9 3 DIP Switch A switch is located next to the JTAG programming connector The switch positions are defined as follows Sw1 OFF Default setting The Virtex 6 configuration is loaded from the flash at power up ON The Virtex 6 safety configuration is loaded from flash at power up To be used only if the Virtex 6 cannot be configured from flash or does not perform properly with the switch in the OFF position
3. ee ee sen 22 4 10 Power supply een 23 4 11 zio em Baer 24 4 12 Power and temperature rte 24 5 a 26 5 1 Temperature eT 26 22 COConvecuon COO IDO eintreten 26 12cm 26 f AAA 26 AA cl tm 26 UM027 www 4dsp com 3 UMO27 FC6301 Appendix A Errata UMO27 User Manual ft gt r1 3 www 4dsp com LIE UMO27 FC6301 User Manual r1 3 1 Acronyms and related documents 1 1 Acronyms A D Analog to Digital Converter BLAST Board Level Advanced Scalable Technology CPLD Complex Programmable Logic Device D A Digital to Analog Converter DCI Digitally Controlled Impedance DDR Double Data Rate DSP Digital Signal Processing FBGA Fineline Ball Grid Array FFT Fast Fourier Transformation FMC FPGA Mezzanine Card FPDP Front Panel Data Port FPGA Field Programmable Gate Array GPIO General Purpose Input Output GUI Graphical User Interface HPC High pin count IP Intellectual Property JTAG Join Test Action Group LED Light Emitting Diode LSB Least Significant Bit s LVDS Low Voltage Differential Signaling LVTTL Low Voltage Transistor Logic level MGT Multi Gigabit Transceiver MSB Most Significant Bit s PCB Printed Circuit Board PCI Peripheral Component Int
4. N38 05 E24 HB05 P P35 HB N06 CC K29 HB06 N CC P36 HB 06 CC K28 HB06 P CC P37 HB N07 J28 7 N N36 HB 07 J27 7 P M42 HB N08 F29 HBO8_N M41 HB 08 F28 HB08 P R38 HB N09 E28 N T39 HB 09 E27 P N41 HB N10 K32 HB10 N N40 HB P10 K31 HB10 P P41 HB_N11 J31 HB11_N P40 HB_P11 J30 HB11_P UM027 www 4dsp com 15 UMO27 FC6301 User Manual u TB r1 3 R42 HB_N12 F32 HB12_N P42 HB_P12 F31 HB12_P T36 HB_N13 E31 HB13_N U36 HB_P13 E30 HB13_P T40 HB_N14 K35 HB14_N R40 HB_P14 K34 HB14_P T35 HB_N15 J34 HB15_N T34 HB_P15 J33 HB15_P T42 HB_N16 F35 HB16_N T41 HB_P16 F34 HB16_P J38 HB_N17_CC K38 HB17_N_CC K38 HB_P17_CC K37 HB17_P_CC K32 HB_N18 J37 HB18_N K33 HB_P18 J36 HB18_P P28 HB_N19 E34 HB19_N N28 HB_P19 E33 HB19_P K34 HB_N20 F38 HB20_N K35 HB_P20 F37 HB20_P L32 HB N21 E37 HB21 N L31 HB P21 E36 HB21 P Table 5 FMC HB connections 4 4 3 Gigabit transceiver connections The FC6301 connects the ten DP signals on the FMC connector to gigabit transceivers GTX blocks on the FPGA The reference clock connections are described in section 4 8 1 FMC HPC FPGA Pin Net Name GTX Block Pin Number Pin Name AP4 DP_C2M_NO C3 DPO_C2M_N AP3 DP_C2M_PO C2 DPO_C2M_P MGTO 112 AN6 DP M2C NO C7 DPO M2C N AN5 DP M2C PO C6 DPO M2
5. Sw2 Reserved Sw3 Reserved Sw4 Reserved Table 13 Switch description UM027 www 4dsp com 21 UMO27 FC6301 User Manual et gt r1 3 4 9 4 CPLD LEDs and board status Four LEDs connect to the CPLD and give information about the board status LED 0 Flashing Virtex 6 FPGA bitstream or user_ROM_register is currently being written to the flash ON Virtex 6 FPGA device not configured OFF Virtex 6 FPGA device LED 1 ON Switch 1 is on position ON The CPLD has been forced to configure the FPGA with the safety configuration OFF Switch 1 is on position OFF LED 2 Flashing The Virtex 6 has been configured with the safety configuration bitstream programmed in the flash at factory because an invalid bitstream was detected in the user configuration space Please write a valid Virtex 6 device A bitstream to the flash ON Flash is busy writing or erasing OFF Flash device is not busy ON CRC error Presumably a wrong or corrupted FPGA bitstream LED 3 has been written to the flash Once on this LED remains on OFF No CRC error detected Table 14 LED board status 4 9 5 JTAG A JTAG connector footprint is available on the FC6301 for configuration purposes and the JTAG chain can be accessed using a press fit JTAG connector The JTAG chain is connected via a DIP switch that enables the following configurations e CPLD gt FPGA e CPLD only The JTAG connector can be placed on both sides o
6. as the temperature The ADT7411 data are constantly passed to the Virtex 6 device Measurements can be accessed from the host computer via the PCI bus Parameter Device 1 Formula On chip temperature ADT7411 Die Temperature On chip AINO Vpp 3 3V External temperature FPGA A temperature External AIN3 12V AIN3 1249 249 External AIN4 1V0 AIN4 External AIN5 3V3 AIN5 External AIN6 1V2 AIN6 External AIN7 MGT1V2 AIN7 External AIN8 MGT1VO AIN8 Table 16 Monitoring device 1 connections UMO27 www 4dsp com 24 UMO27 FC6301 User Manual DSP n Parameter Device 2 Formula On chip temperature ADT7411 Die Temperature On chip AINO Voo 3 3V External AIN1 BLASTO_vcore AIN1 External AIN2 BLAST2_vcore AIN2 External AIN3 5V AIN3 1249 249 External AIN4 0V9 AIN4 External AIN5 VADJ AIN5 External AIN6 1V8 AIN6 External AIN7 12V current Tbd External AIN8 2V5 AIN8 Table 17 monitoring device 2 connections UMO27 www 4dsp com 25 UMO27 FC6301 User Manual u TB r1 3 5 Environment 5 1 Temperature Operating temperature 0C to 60 C Commercial e 40 C to 85 C Industrial Storage temperature e 40 C to 120 C 5 2 Convection cooling The air flow provided by the chassis fans the FC6301 is enclosed in will dissipate the heat generated by the on board components A minimum airflow of 3
7. available on LX240T D26 C21 FP_RTM_60 1 8V Not available on LX240T M22 D13 FP_RTM_61 1 8V Not available on LX240T B26 D15 FP_RTM_62 1 8V Not available on LX240T C25 D17 FP_RTM_63 1 8V Not available on LX240T N23 D19 FP_RTM_64 1 8V Not available on LX240T M24 D21 FP_RTM_65 1 8V Not available on LX240T D25 E11 FP_RTM_66 1 8V Not available on LX240T E25 E12 FP_RTM_67 1 8V Not available on LX240T P21 E13 FP_RTM_68 1 8V Not available on LX240T P22 E14 FP_RTM_69 1 8V Not available on LX240T AL22 A11 FP_RTM_7 1 8V Not available on LX240T P20 E15 FP_RTM_70 1 8V Not available on LX240T N20 B21 FP_RTM_71 1 8V Not available on LX240T BA26 B2 FP_RTM_8 1 8V Not available on LX240T AJ23 B4 FP_RTM_9 1 8V Not available on LX240T K42 A6 FP_RTM_CLKinn 2 5V J42 A5 FP_RTM_CLKinp 2 5V P31 E21 FP_RTM_CLKoutn 2 5V P30 E20 FP_RTM_CLKoutp 2 5V Table 2 P2 connections UM027 www 4dsp com 10 UMO27 FC6301 User Manual 19 SPE r1 3 4 2 PO connector A one lane PCI express is connected to a bridge device PI7C9X110 thus making the Virtex 6 FPGA available for access on the parallel PCI bus The following performances have been recorded on the bus gt PCI 33 MHz Host to FC6301 60 Mbytes s sustained gt PCI 33 MHz FC6301 to Host 110 Mbytes s sustained gt PCI 66 MHz Host to FC6301 120 Mbytes s sustained gt PCI 66 MHz FC6301 to Host 140 Mbytes s sustained 32 bits PCI 33 or 66 MHz Virtex6 PI7C9X110 cPCI P1 o 3 o ac x 8 oS o A Fi
8. 00 LFM is recommended Optionally a low profile heat sink fan can be glued on top of the Quad ADC The card has a fan power connection that can be switch on and off under carrier card control TBD For standalone operations such as on a Xilinx development kit it is highly recommended to blow air across the FMC and ensure that the temperature of the devices is within the allowed range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 6 Safety This module presents no hazard to the user 7 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 8 Warranty Basic Warranty 1 Year from Date of Shipment 90 Days from Date of Shipment included Extended Warranty 2 Years from Date of Shipment 1 Year from Date of Shipment optional UMO27 www 4dsp com 26 UMO27 FC6301 User Manual Appendix A Errata PCB revision 2 1 SPI FLASH not supported UMO27 www 4dsp com Jor r1 3 27
9. 18 N CC W30 LA P18 CC C22 LA18 P CC Y33 LA N19 H23 LA19 N W32 LA P19 H22 LA19 P Y42 LA_N20 G22 LA20_N w42 LA_P20 G21 LA20_P w31 LA_N21 H26 LA21_N v31 LA_P21 H25 LA21_P W33 LA N22 G25 LA22 N V33 LA P22 G24 LA22 P W41 LA N23 D24 LA23_N v4 LA_P23 D23 LA23_P W40 LA_N24 H29 LA24_N V40 LA P24 H28 LA24 P W38 LA N25 G28 LA25_N v38 LA_P25 G27 LA25_P V36 LA N26 D27 LA26 N W36 LA P26 D26 LA26 P V35 LA N27 C27 LA27_N W35 LA_P27 C26 LA27_P U41 LA N28 H32 LA28 N U42 LA P28 H31 LA28 P V39 LA N29 G31 LA29 N U39 LA P29 G30 LA29 P U38 LA N30 H35 LA30 N U37 LA P30 H34 LA30 P U34 LA N31 G34 LA31 N V34 LA P31 G33 LA31 P U33 LA N32 H38 LA32 N U32 LA P32 H37 LA32 P T32 LA N33 G37 LA33 N R32 LA P33 G36 LA33 P Table 3 FMC LA connections UMO27 www 4dsp com 13 SJ SPF UM027 FC6301 User Manual r1 3 FMC HPC FPGA Pin Net Name Pin Number Pin Name AE32 HA N00 CC F5 N CC AD32 HA P00 CC F4 P CC AJ35 HA NO1 CC E3 HA01 N CC AH34 HA P01 CC E2 HAO1 P CC AM42 HA_NO2 K8 2 N AL42 HA P02 K7 2 P AM41 HA N03 J7 HA03 N AL41 HA P03 J6 HA03 P AL40 HA N04 F8 HAO4_N AK40 HA_PO4 F7 HA04 39 HA N05 E7 N AK39 HA P05 E6 HA05 P AJ40 HA N06 K11 HA06 N AH39 HA P06 K10 HA06 P AH41 HA 7 J10 HA07 N AG42 HA P07 J9 7 P AG41 HA N08 F11 N AF40
10. C P AN2 DP C2M N1 A23 DP1 C2M N AN1 DP C2M P1 A22 DP1 C2M P MGT1 112 AM8 DP_M2C_N1 A3 DP1_M2C_N AM7 DP_M2C_P1 A2 DP1 M2C P AL2 DP C2M N2 A27 DP2 C2M N AL1 DP C2M P2 A26 DP2 C2M P MGT3 112 AJ6 DP M2C N2 A7 DP2 M2C N AJ5 DP M2C P2 A6 DP2 M2C P AJ2 DP C2M N3 MGT1 113 A31 DP3 C2M N UMO27 www 4dsp com 16 UMO27 FC6301 User Manual LIEF AJ1 DP_C2M_P3 A30 DP3_C2M_P AF4 DP_M2C_N3 A11 DP3_M2C_N AF3 DP_M2C_P3 A10 DP3_M2C_P AG2 DP_C2M_N4 MGT3_113 A35 DP4_C2M_N AGI DP_C2M_P4 A34 DP4_C2M_P AD4 DP_M2C_N4 A15 DP4 2 N AD3 DP M2C P4 A14 DP4 M2C P AC2 DP C2M N5 MGT1 114 A39 DP5 C2M N AC1 DP C2M P5 A38 DP5 C2M P ABA DP_M2C_N5 A19 DP5_M2C_N AB3 DP_M2C_P5 A18 DP5 M2C P AE2 DP C2M MGTO 114 B37 DP6 C2M N AE1 DP C2M P6 B36 DP6 C2M P AC6 DP M2C 6 B17 DP6_M2C_N AC5 DP_M2C_P6 B18 DP6_M2C_P AH4 DP_C2M_N7 MGT2_113 B33 DP7_C2M_N AH3 DP_C2M_P7 B32 DP7_C2M_P AE6 DP_M2C_N7 B13 DP7_M2C_N AE5 DP_M2C_P7 B12 DP7_M2C_P AK4 DP_C2M_N8 MGTO 113 B37 DP8 C2M N AK3 DP_C2M_P8 B36 DP8_C2M_P AG6 DP_M2C_N8 B17 DP8_M2C_N AG5 DP M2C P8 B18 DP8 M2C P AM4 DP C2M N9 MGT2 112 B37 DP9 C2M N AM3 DP_C2M_P9 B36 DP9_C2M_P AL6 DP_M2C_N9 B17 DP9_M2C_N AL5 DP M2C P9 B18 DP9 M2C P Table 6 FMC GTX GTH connections 4 4 4 Miscellaneous FMC connections The differential clock connections ar
11. ES YES YES YES ADV212 JPEG2000 YES YES YES YES 32GB NAND FLASH YES YES YES YES Table 10 BLAST Memory Processing Options 4 8 Clock tree The FC6301 clock architecture offers an efficient distribution of low jitter clocks A 100 MHz clock from a low jitter oscillator is distributed to the FPGA and the PClexpress to PCI bridge using a PCI express jitter attenuator ICS847003 This clock is used as the PClexpress reference clock A low jitter programmable clock device CDCE925 able to generate frequencies from 62 5MHz to 255 5MHz in steps of 0 5MHz is also available This clock management approach ensures maximum flexibility to efficiently implement multi clock domains algorithms and use the memory devices at different frequencies Further there is also a fixed 50 MHz clock is distributed to the FPGA and the CPLD UM027 www 4dsp com 19 UMO27 FC6301 User Manual et gt r1 3 CDCV304 CPLD Jitter PCle PCI attenuator H and buffer bridge clock 33 66 MHz FMC ref CLK VITA 57 1 FMC mer 50MHz crystal Clock synthesizer CDCEL925 16 MHz crystal Figure 5 Clock tree 100MHz Low jitter LVDS 4 8 1 FMC GTX Reference Clock The FMC standard defines two high precision reference clocks that are driven from the FMC to the carrier The FC6301 connects these clocks directly to GTX reference clock inputs The following table shows which GTX GTH
12. HA 08 F10 HA08 P AF36 HA N09 E10 AF35 HA 09 9 HA09_P AF34 HA_N10 K14 HA10_N AG34 HA_P10 K13 HA10_P AD41 HA N11 J13 HA11_N AC41 HA P11 J12 HA11_P AE39 HA_N12 F14 HA12_N AE40 HA_P12 F13 HA12_P AE35 HA_N13 E13 HA13_N AE34 HA_P13 E12 HA13_P AD33 HA_N14 J16 HA14_N AE33 HA_P14 J15 HA14_P AC33 HA_N15 F17 HA15_N AC34 HA_P15 F16 HA15_P AD40 HA_N16 E16 HA16_N AC40 HA_P16 E15 HA16_P AD37 HA_N17_CC K17 HA17_N_CC AE37 HA_P17_CC K16 HA17_P_CC AB38 HA N18 CC J19 HA18 N AB37 HA P18 CC J18 HA18 P UM027 www 4dsp com 14 LIEF UM027 FC6301 User Manual r1 3 AB36 HA_N19 F20 HA19_N AC36 HA_P19 F19 HA19_P AB33 HA_N20 E19 HA20_N AB32 HA_P20 E18 HA20_P AB42 HA N21 K20 HA21_N AA42 HA_P21 K19 HA21_P AB41 HA N22 J22 HA22_N AA41 HA_P22 J21 HA22_P AA40 HA N23 K23 HA23_N AB39 HA_P23 K22 HA23 P Table 4 FMC HA connections 4 4 2 Bank B HB connections Differential routing is applied with matched delay within all pairs on bank B HB FMC HPC FPGA Pin Net Name Pin Number Pin Name P38 CC K26 CC R39 HB P00 CC K25 P CC M37 HB N01 J25 N M36 HB P01 J24 L40 HB N02 F23 HBO2_N L39 02 F22 HBO2_P M39 HB N03 E22 HB03 N M38 HB P03 E21 HB03 P L42 HB N04 F26 HB04 N L41 04 F25 HB04_P N39 5 E25
13. Manual r1 3 4 1 2 P2 connections Signal name Bank Voltage Notes AT26 FP RTM 0 1 8V Not available on LX240T AU27 A2 FP RTM 1 1 8V Not available on LX240T AK23 B6 FP_RTM_10 1 8V Not available on LX240T BB26 B8 FP_RTM_11 1 8V Not available on LX240T BB27 B10 FP_RTM_12 1 8V Not available on LX240T AM23 C1 FP RTM 13 1 8V Not available on LX240T AN23 C3 FP_RTM_14 1 8V Not available on LX240T AU23 C4 FP_RTM_15 1 8V Not available on LX240T AU24 C6 FP RTM 16 1 8V Not available on LX240T AP25 C8 FP RTM 17 1 8V Not available on LX240T AP26 C10 FP RTM 18 1 8V Not available on LX240T AK24 D1 FP RTM 19 1 8V Not available on LX240T AK22 A3 FP RTM 2 1 8V Not available on LX240T AL25 D2 FP RTM 20 1 8V Not available on LX240T AP23 D3 FP RTM 21 1 8V Not available on LX240T AR23 D5 FP RTM 22 1 8V Not available on LX240T AM24 D7 FP_RTM_23 1 8V Not available on LX240T AL24 D9 FP_RTM_24 1 8V Not available on LX240T BA25 D11 FP_RTM_25 1 8V Not available on LX240T AN24 E1 FP_RTM_26 1 8V Not available on LX240T AN25 E2 FP_RTM_27 1 8V Not available on LX240T AV26 E3 FP_RTM_28 1 8V Not available on LX240T AU26 E4 FP_RTM_29 1 8V Not available on LX240T AJ22 A7 FP RTM 3 1 8V Not available on LX240T AR24 E5 FP_RTM_30 1 8V Not available on LX240T AT24 E6 FP_RTM_31 1 8V Not available on LX240T AW25 E7 FP_RTM_32 1 8V Not available on LX240T AW26 E8 FP_RTM_33 1 8V Not available on LX240T AT25 E9 FP_RTM_34 1 8V Not available on LX240T AR25 E10 FP_RTM_35 1 8V Not ava
14. UMO27 FC6301 User Manual E gt r1 3 FC6301 User Manual 4DSP LLC USA Email support 4dsp com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP LLC 4DSP LLC 2013 UMO27 FC6301 User Manual u TB r1 3 Revision History Y 1 1 2013 05 01 Updated Table 5 FMC GTX GTH connections 1 2 to use the MGTx_abc notation Also fixed wrong reference to MGT bank 115 and changed it to MGT bank 113 2014 04 15 Added Table 2 P2 connections and updated section 4 1 with a description of the P2 connector limitation UM027 www 4dsp com 2 UM027 FC6301 User Manual r1 3 Table of Contents 1 Acronyms and related documents U 5 u oem 5 12 Related Documents ee 6 2 6 XM 8 3 1 Requirements and handling instructions a raras 8 3 2 Firmware and Software mvnnnnnennnnaennnnanannnannnnnaeenenanaaanenanneanennnanana 8 4 Hardware Specification PET U s ra naa Kaka u u 8 4 1 Phycisal specifications als 8 4 1 1 Pongau 8 42 11 SONNE ee een 9 4 3
15. ards that can be used on the FC6301 http www 4dsp com fmc php 4 4 1 Bank A LA HA connections Differential routing is applied with matched delay within pairs on bank A LA HA FMC HPC FPGA Pin Net Name Pin Number Pin Name AF30 LA CC G7 LAO0 N CC AE30 LA P00 CC G6 LAO0 P CC AK37 LA NO1 CC D9 LAO1 N CC AJ37 LA P01 CC D8 LAO1 P CC AK30 LA N02 H8 LAO2_N AJ31 LA P02 H7 LA02 P AJ32 LA_NO3 G10 LAOS N AK33 LA 03 G9 LA03 P AG29 LA_N04 H11 LA04_N AH29 LA_P04 H10 LA04 P AG39 LA N05 D12 LAO5_N AF39 LA 05 D11 LAO5_P AG37 LA_NO6 C11 LAO6 N AF37 LA 06 C10 LA06 P AG33 LA N07 H14 N AF32 LA P07 H13 LAO7 P AF41 LA N08 G13 LAO8 N AF42 LA P08 G12 LA08 P AE42 LA N09 D15 LAO9 N AD42 LA 09 D14 LAO9 P AD38 LA N10 C15 LA10 N AE38 LA P10 C14 LA10 P AD30 LA N11 H17 LA11 N AD31 LA P11 H16 LA11 P Y39 LA N12 G16 LA12 N Y40 LA_P12 G15 LA12 P AA39 LA N13 D18 LA13 N Y38 LA P13 D17 LA13 P UMO27 www 4dsp com 12 LIEF UM027 FC6301 User Manual r1 3 Y37 LA N14 C19 LA14 N W37 LA P14 C18 LA14 P Y35 LA N15 H20 LA15 N AA35 LA P15 H19 LA15 P AA30 LA N16 G19 LA16 N Y30 LA P16 G18 LA16 P AB31 LA N17 CC D21 LA17 N CC AA31 LA P17 CC D20 LA17 P CC V30 LA N18 CC C23 LA
16. connected to a bank that supports 1V8 whereas the serial flash will be operating at 3V3 This will not cause problems for the signals from the Virtex 6 to the flash device but the signal from the flash device to the Virtex 6 will pass through a level translator SN74AVC4T245 4 6 Virtex 6 FPGA device The Virtex 6 FPGA device is the DSP processing node of the FC6301 The Virtex 6 FPGA device is from the Virtex 6 SXT and LXT family in a 1759 balls fine line ball grid array package It can be an XC5VLX240T XC5VLX365T XC5VLX550T XC5VSX315T or XC5VSX475T UM027 www 4dsp com 18 UMO27 FC6301 User Manual p gt r1 3 4 7 BLAST sites Thanks to the availability of 3 BLAST sites a wide variety of memory and processing modules can be connected to the Virtex 6 device For each BLAST site itis possible to choose from the list of available BLAST modules For more information about the available BLASTs on the FC6301 please consult the following page BLAST modules http www 4dsp com BLAST htm Due to its small form factor and ease of design the BLAST modules enable a rapid solution for custom memory or processing requirements BLAST SITE 1 2 3 4 Single BLAST YES YES YES YES Single Extended YES YES YES YES BLAST Double BLAST NO NO NO NO Double Extended NO NO NO NO BLAST Table 9 BLAST Configuration Options BLAST SITE 1 2 3 4 DDR3 YES YES YES YES DDR2 YES YES YES YES QDR Y
17. e described in section 4 8 2 The global address pins GAO and GA1 on the FMC site are tied to ground FMC HPC FPGA Pin Net Name DIR Pin Number Pin Name Through 20 SCL C30 SCL CPLD Through I2C SDA FMC C31 SDA CPLD AJ41 PG M2C F1 PG_M2G r1 3 UM027 17 UMO27 FC6301 User Manual 1 r1 3 AH40 PRSNT M2C L 2 PRSNT_M2C_L AJ42 PG C2M O D1 PG_C2M Table 7 Miscellaneous FMC connections The I O standard to be assigned depends on VADJ configuration by default this is 2V5 Contact factory for other VADJ voltages The FMC 126 bus signals connect to the CPLD and can be controlled from the FPGA using two signals per I2C line The connections and CPLD logic are depicted in the following image Figure 4 FMC I2C connections FPGA Pin Net Name DIR AT12 SCL oe O BA15 SCL BA14 SDA_oe O AR12 SDA Table 8 FMC I2Cconnections 4 5 SPI flash A 128 Mbits serial flash device S25FL128P will be available to the Virtex 6 device This flash allows the storage of vital data like processor boot code and settings into a non volatile memory The flash is operated using a standard SPI interface that can run up to 104 MHz allowing for a page programming speed up to 208 KB s Reading data from the flash can be done at speeds up to 13 MB s The SPI programming pins will be
18. erconnect PCle PCI Express PLL Phase Locked Loop pps Pulse Per Second QDR Quadruple Data rate SDRAM Synchronous Dynamic Random Access memory sFPDP Serial FPDP SPI Serial Peripheral Interconnect SRAM Synchronous Random Access memory SRIO Serial Input Output SSC Spread Spectrum Clocking TTL Transistor Logic level UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus Table 1 Glossary UM027 www 4dsp com 5 UMO27 FC6301 User Manual 19 SPE r1 3 1 2 Related Documents 3U CompactPCI specifications PICMG 2 0 R3 0 e CompactPCI Hot Swap specifications PICMG 2 1 R2 0 e VITA 57 1 FPGA Mezzanine Card Standard Xilinx Virtex 6 documentation 2 General description The FC6301 is a high performance CompactPCI cPCI card with advanced digital signal processing capabilities The design has been targeted for customer programmable implementations of complex FPGA algorithms for Digital Signal Processing DSP applications The FC6301 product is in the 3U cPCI form factor offering various direct on board interface options that are closely coupled to large fast on board memory resources of the Xilinx Virtex 6 FPGA The FC6301 is an excellent choice for high performance applications that require the use of accelerated frequency domain algorithms such as with FFTs 4DSP has many off the shelf Intellectual Property IP cores for applications that require the highest level of performance CompactPCI cPCI is an adaptation of
19. f the PCB The connector location seen from the top of the PCB is shown in Figure 10 GND OO TDI OOTMS Figure 7 JTAG connector location UM027 www 4dsp com 22 UMO27 FC6301 User Manual u TB r1 3 4 10 Power supply The Power is supplied to the FC6301 via the CompactPCI connectors Several DC DC converters generate the appropriate voltage rails for the different devices and interfaces present on board The FC6301 power distribution is as follows p 5v to 1v2 EN5365Q1 1V2 gt MGT 1 3A V2 to vi TPS74401 SI7110DN BLAST voltage 4 s cPCI H 0 004 R IL 1v5 1v8 4 A SIT DN c AOR 1v8 FP gt 3v3 cPCI H 0 004 Bi i MGT 1 8A pericom 0 5A vi Vi zd BLAST 4A me fem LTC 1644 n Sv gt 3V3 gt 12v cPCI TPS2420 12V 3v3 to 2v5 TPS74401 va msic 1A 3v3 to 2v5 1v2 EN5365QI Mc Vadj 39 FMC 3A 3v3 to 0v9 TPS54572 0vg llon gt ddr term 7A 3v3 to 1v0 85 EP5396Q1 1v0 FP V6 8A 3v3 to 1v0 EP5396Q1 V6 8A Figure 8 FC6301 power distribution Device Interface Voltage Maximum supported current DCI and mem
20. gure 3 PCI interface diagram 4 3 Front panel The FC6301 offers different front panel IO options Not all can be used simultaneously In case an FMC is used no Ethernet connection is possible 4 3 1 Gigabit Ethernet Two Ethernet ports RJ45 connectors are available on the FC6301 in the front panel I O area The FPGA is connected to a 2 port Ethernet PHY 88E1121 that connects to two RJ45 connectors The Gigabit Ethernet ports are capable to adapt to lower Ethernet speeds 10 100 if reguired This is a specific option which is not available in combination with an FMC daughter card 4 3 2 UART One UART connection will be available on the fontanel via a mini USB connection The serial interface is made using a USB to UART Bridge CP2102 The UART will connect directly to the Virtex 6 FPGA via a level translator 4 3 3 LED Four LEDs are connected to the CPLD and are available in the front panel I O area UMO27 www 4dsp com 11 UMO27 FC6301 User Manual et gt r1 3 4 4 FPGA Mezzanine Card FMC The Virtex 6 FPGA interfaces to an FPGA Mezzanine Card FMC via a high pin count HPC VITA 57 1 site All the differential and control signals are connected to the Virtex 6 FPGA The FC6301 also connects all ten high speed differential signals DP_M2C 9 0 and DP C2M 9 0 The FMC site provides flexibility for adding analog and or digital via customer developed third party or 4DSP FMC boards 4DSP offers a wide variety of FMC c
21. ilable on LX240T H24 A12 FP_RTM_36 1 8V Not available on LX240T G24 A13 FP_RTM_37 1 8V Not available on LX240T E27 A14 FP_RTM_38 1 8V Not available on LX240T D27 A15 FP_RTM_39 1 8V Not available on LX240T AY27 A8 FP_RTM_4 1 8V Not available on LX240T F25 A16 FP_RTM_40 1 8V Not available on LX240T F24 A17 FP_RTM_41 1 8V Not available on LX240T C28 A18 FP_RTM_42 1 8V Not available on LX240T B28 A19 FP_RTM_43 1 8V Not available on LX240T UM027 www 4dsp com 9 LIE UM027 FC6301 User Manual r1 3 H26 A20 FP_RTM_44 1 8V Not available on LX240T G26 A21 FP_RTM_45 1 8V Not available on LX240T F26 B12 FP_RTM_46 1 8V Not available on LX240T K25 B14 FP_RTM_47 1 8V Not available on LX240T J25 B16 FP_RTM_48 1 8V Not available on LX240T B27 B18 FP_RTM_49 1 8V Not available on LX240T AW27 A9 FP_RTM_5 1 8V Not available on LX240T A27 B19 FP_RTM_50 1 8V Not available on LX240T J23 B20 FP_RTM_51 1 8V Not available on LX240T K23 C12 FP_RTM_52 1 8V Not available on LX240T M19 C14 FP_RTM_53 1 8V Not available on LX240T N19 C15 FP_RTM_54 1 8V Not available on LX240T N21 C16 FP_RTM_55 1 8V Not available on LX240T M21 C17 FP_RTM_56 1 8V Not available on LX240T A26 C18 FP_RTM_57 1 8V Not available on LX240T A25 C19 FP_RTM_58 1 8V Not available on LX240T C26 C20 FP_RTM_59 1 8V Not available on LX240T AM22 A10 FP_RTM_6 1 8V Not
22. ory reference voltage 0 9V 6A Virtex 6 core 1V 16A CPLD BLAST sites 1 8V 8A Virtex 6 Vccaux Virtex 6 bank connected to A D 2 5V 2A daughter card EP80579 CPLD PCI bridge power generation 3 3V 11A power generation 5V 12A Front Panel IO daughter card 12V 2A MGT power supply 1 V 1 2V 2A 1 5A UMO27 www 4dsp com 23 UMO27 FC6301 User Manual u TB r1 3 Table 15 Power supply 4 11 Hotswap Hot Swap is the act of removal and insertion of cards into a platform while that system is operational This process should not cause any failures on the systems power supply and system s I O signals Protection of the card s circuitry also needs to be taken into account in this process A compact PCI board can implement three different types of hot swap e Non Hot Swap do not have hot swap features e Basic Hot Swap boards have the minimum features required e Full Hot Swap have the minimum requirements plus the ability for software connection control The Pericom bridge is a hot swap friendly device but full hot swap is not supported A hot swap controller is required to monitor all power levels pre charge the cPCI signals and to switch the backend power on and off The LTC 1643A hot swap controller from linear technologies is used For more information on hot swap refer to the hot swap specifications 4 12 Power and temperature monitor Two ADT7411 devices are used to monitor the power on the different voltage rails as well
23. r the FPGA is provided The FC6301 is delivered with an interface to the Xilinx PClexpress endpoint in the Virtex 6 device and an example VHDL design so users can start performing data transfers over the PCI bus right out of the box For more information about software installation and FPGA firmware please refer the 4FM Get Started Guide 4 Hardware Specification 4 1 Phycisal specifications The FC6301 card complies with the compact PCI standard known as PICMG 2 0 R3 0 The card is a 3U 100 mm by 160 mm module which incorporates a 32 bits PCI bus on the P1 connector The P2 connector is fully routed to the Virtex6 FPGA through zero ohm resistors However the LX240T version of the Virtex6 FPGA does not completely support the P2 connector Table 2 lists the signals the connections of P2 and which signals are not available on the LX240T Also addition the zero ohm resistors are not mounted by default contact factory in case connections on P2 are required 4 1 1 Front panel layout There are three front panel options One front panel is used when an FMC board is mounted The other front panel is used when the Ethernet option is chosen And the third option has no cutout at all L ee Figure 2 FMC option Bezel drawing UM027 www 4dsp com 8 SJ SPF UM027 FC6301 User
24. s can use these reference clocks FPGA Pin Net name GTX REFCLK GTX GTHs reached AK7 GBTCLKO_M2C_n GTXREFCLKO_112 112 113 AK8 GBTCLKO_M2C_p AD7 GBTCLK1 M2C n GTXREFCLK1 113 112 113 114 ADB GBTCLK1 M2C p Table 11 FMC GTX reference clock connections 4 8 2 FMC Clock connections The FMC clocks are connected to LVDS capable I O on the FPGA CLKO and CLK1 are connected to global clock inputs CLK2 and CLK3 are connected to regular I O FMC HPC FPGA Pin Net Name Pin Number Pin Name AN13 CLKO_M2C_n H5 CLKO_M2C_N AN14 CLKO_M2C_p H4 CLKO_M2C_P AY13 CLK1_M2C_n G3 CLK1_M2C_N AY14 CLK1_M2C_p G2 CLK1_M2C_P AM12 CLK2_BIDIR_n K5 CLK2_BIDIR_N AM13 CLK2_BIDIR_p K4 CLK2_BIDIR_P AW16 CLK3 BIDIR n J3 CLK3_BIDIR_N AV16 CLK3 BIDIR p J2 CLK3 BIDIR P Table 12 FMC clock connections UMO27 www 4dsp com 20 UMO27 FC6301 User Manual u TB r1 3 4 9 FPGA device configuration 4 9 1 Flash storage The FPGA firmware is stored on board in a flash device The 512Mbit device is partly used to store the configuration for both FPGAs In the default CPLD firmware configuration the Virtex 6 device is directly configured from flash if a valid bitstream is stored in the flash The flash is pre programmed in factory with the default firmware example JTAG Header S29GL512M 512Mbit Flash JTA JUNE
25. the Peripheral Component Interconnect PCI Specification for industrial and military embedded applications requiring a more robust mechanical form factor than a desktop PC UM027 www 4dsp com 6 UMO27 FC6301 User Manual te C r1 3 10x MGT 3 125Gbps 160 single ended 80 LVDS pairs Virtex 6 XC6VLX240T XC6VLX365T XC6VLX550T XC6VSX315T XC6VSX475T 512Mbit parallel flash CPLD LED x4 PCle x1 72 single ended iuser defined 10 PCle x1 to PCI bridge A cPCI J1 do user lO 32 bit 33 66MHz L Figure 1 FMC122 block diagram 4 BLAST site only fully supported on SX475T and LX550T devices on other devices only the DDR2 BLAST A is supported Refer to the Appendix for Errata 3 FMC and Ethernet are mutually exclusive Either Ethernet or FMC can be used Default configuration does not mount series zero ohm resistors contact factory if J2 connections are required UMO27 www 4dsp com 7 UMO27 FC6301 User Manual u TB r1 3 3 Installation 3 1 Requirements and handling instructions The FC6301 daughter card must be installed backplane compliant to the standard Do not flex the board and prevent electrostatic discharges by observing ESD precautions when handling the card 3 2 Firmware and Software Drivers libraries and a program example working in combination with a pre programmed firmware fo
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