ADSST-EM-3035 - Analog Devices
Contents
1. 25 ns 65 mA Ci Input Pin Vin 2 5 V Capacitance 12 fn 1 0 MHz TAMB 25 C 8 pF Co Output Pin Vin 2 5 V Capacitance gt 12 13 fin 1 0 MHz Tamp 25 C 8 pF NOTES 1 Bidirectional pins D0 D23 RFS0 RFS1 SCLK0 SCLK1 TFS0 TFS1 Al A13 PFO PE7 Input only pins RESET BR DRO DR1 PWD 3Input only pins CLKIN RESET BR DRO DR1 PWD Output pins BG PMS DMS BMS IOMS CMS RD WR PWDACK A0 DT0 DT1 CLKOUT FL2 0 BGH 5 Although specified for TTL outputs all ADSST 2185KST 133 outputs are CMOS compatible and will drive to V pp and GND assuming no dc loads Guaranteed but not tested 7Three statable pins A0 A13 D0 D23 PMS DMS BMS IOMS CMS RD WR DT0 DT1 SCLK0 SCLK1 TFS0 TFS1 RFSO RFS1 PFO PF7 80 V on BR CLKIN inactive Idle refers to ADSST 2185KST 133 state of operation during execution of IDLE instruction Deasserted pins are driven to either V pp or GND 10T p measurement taken with all instructions executing from internal memory 50 of the instructions are multifunction types 1 4 5 12 13 14 30 are type 2 and type 6 and 20 are idle instructions lV 0 V and 3 V For typical figures for supply currents refer to Power Dissipation section 12 Applies to TQFP package type 13 Output pin capacitance is the capacitive load for any three stated output pin Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Supply Vo2. 05 In lt I lt Inax 1 0 0 05 0 1 Vy t 10 0 1 In lt I lt Imax 0 5 Lagging 0 05 0 1 REV 0 19 ADSST EM 3035 Table XVI Harmonic Distortion Error Table XVIII Voltage Unbalance Error Current Current Min Typ Max Unit Current Voltage Min Typ Max Unit 10 of Third 0 05 In lt I lt Imax 0 05 0 1 In Vy 15 0 1 0 2 Harmonic Table XIX Starting Current Table XVII Reverse Phase Sequence Error Voltage Min Typ Max Unit Current Voltage Min Typ Max Unit Vn 0 0007 0 001 In 0 1 In Vy 0 05 Yo ELECTRICAL CHARACTERISTICS OF ADSST EM 3035 ABSOLUTE MAXIMUM RATINGS Supply Voltage Input Voltage Output Voltage Swing Operating Temperature Storage Temperature 0 3Vto7V 0 3 V to Vpp 0 3 V 0 3 V to Vpp 0 3 V UA Sots 40 C to 85 C 65 C to 150 C RECOMMENDED OPERATING CONDITIONS A Grade B Grade Parameters Min Max Min Max Unit Vpp 7 0 7 V Temperature 0 70 40 85 C Ordering Codes A Grade ADSST EM 3035 BST B Grade ADSST EM 3035 KST ORDERING GUIDE Temperature Model Range Model Included Package Option ADSST EM 3035K 0 to 70 C ADSST 2185KST 133 SU 100 ADSST 73360AR RW 28 OUTLINE DIMENSIONS 100 Lead Thin Plastic Quad Flat Package TQFP SU 100 Dimensions shown in millimeters 0 75 1 20 16 00 SQ 0 60 44 14 00 sa 0 45 ry 100 76
3. KWords On Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU Multiplier Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16 Bit Interval Timer with Prescaler 100 Lead TOFP 16 Bit Internal DMA Port for High Speed Access to On Chip Memory Mode Selectable 4 MBytes Byte Memory Interface for Storage of Data Tables and Program Overlays 8 Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers Mode Selectable 1 0 Memory Interface with 2048 Locations Supports Parallel Peripherals Mode Selectable Programmable Memory Strobe and Separate I O Memory Space Permits Glueless System Design Mode Selectable Programmable Wait State Generation Two Double Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On Chip Program Memory from Byte Wide External Memory e g EPROM or through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE Port Emulator Interface Supports Debugging in Final Systems GENERAL DESCRIPTION The ADSST 2185KST 133 is a single chip microcomputer optimized for digital signal processing DSP and other high speed numeric processing applications Th
4. PGA 0 dB 86 dB PGA 38 dB 80 dB Intermodulation Distortion 79 dB PGA 0 dB Idle Channel Noise 76 dB PGA 0 dB Crosstalk ADC to ADC 85 dB ADCI Input Signal Level 1 kHz 0 dBm0 ADC2 Input at Idle DC Offset 20 mV PGA 0 dB Power Supply Rejection 55 dB Input Signal Level at AVDD and DYDD Pins 1 0 kHz 100 mV p p Sine Wave Group Delay 25 us 64 kHz Output Sample Rate 50 us 32 kHz Output Sample Rate 95 us 16 kHz Output Sample Rate 190 us 8 kHz Output Sample Rate Input Resistance at VIN 25 ko DMCLK 16 384 MHz FREOUENCY RESPONSE ADC Typical Output Frequency Normalized to fs 0 0 dB 0 03125 0 1 dB 0 0625 0 25 dB 0 125 0 6 dB 0 1875 1 4 dB 0 25 2 8 dB 0 3125 4 5 dB 0 375 7 0 dB 0 4375 9 5 dB gt 0 5 lt 12 5 dB REV 0 9 ADSST EM 3035 Parameter Min Typ Max Unit Test Conditions Comments LOGIC INPUTS Vina Input High Voltage Vpp 0 8 Vpp V Vii Input Low Voltage 0 0 8 V Im Input Current 0 5 UA Cm Input Capacitance 10 pF LOGIC OUTPUT Vox Output High Voltage Vpp 0 4 Vpp V IOUT lt 100 pA Vor Output Low Voltage 0 0 4 V IOUT lt 100 pA Three State Leakage Current 0 3 pA POWER SUPPLIES AVppl AVpp2 4 5 5 5 v DVpp 4 5 5 5 V Ipp See Table II NOTES 1Operating temperature range is as follows 40 C to 85 C Therefore Tym 40 C and Tmax 85 C 2Test conditions Input PGA set for 0 dB gain unless otherwise noted 3At input to sigma delta modulat
5. a OD 220 C Analog I O Voltage to AGND 0 3 V to AVpp 0 3 V i i i Operating Temperature Range Industrial A Version Stresses above those listed under Absolute Mazimum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the o o FRAO ACRE IEE EPR RIES IA GeO SE MAUA 40 C to 85 C device at these or any other conditions above those listed in the operational Storage Temperature Range 65 C to 150 C sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although WARNING the ADSST EM 3035 features proprietary ESD protection circuitry permanent damage may occur Oe on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE 10 REV 0 ADSST EM 3035 PIN CONFIGURATION VINP2 1 28 VINN3 VINN2 2 VINP3 VINP1 3 26 VINN4 VINN1 4 25 VINP4 REFOUT 5 24 VINNS REFCAP 6 ADSST 23 VINP5 AGND2 s Not to Scale 77 vinpe DGND 9 20 AVpp1 DVpp 10 19 AGND1 RESET 11 18 SE SCLK 12 SDI MCL
6. 04d OSs H99 oLa AIYAMd Zdd ZOUl ov x 94d 110Ul oaviiv aE and Lavizv 26 S4d 070Ul zavuev a vid 30ul fe f fer fe feo tT fem fem St SY 1 SY YET SY HLS Ha ON ee few co eatrtrae PRK ORSOorTNAZAAEFEAALAMMWM Ww ees 2e 25a 8 cS ES ssSER RRR ES 22 282222858 O 3 qaq d REV 0 ADSST EM 3035 System Interface Figure 2 shows typical basic system configurations with the ADSST 2185KST 133 two serial devices a byte wide EPROM and optional external program and data overlay memories mode selectable Programmable wait state generation allows the proces sor to connect easily to slow peripheral devices The ADSST 2185KST 133 also provides four external interrupts and two serial ports or six external interrupts and one serial port Host Memory Mode allows access to the full external data bus but limits address ing to a single address bit A0 Additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals FULL MEMORY MODE ADSST 2185 KST 133 1 2x CLOCK OR CRYSTAL Do3 16 gt A0 A21 BYTE MEMORY DATA VO SPACE DATA PERIPHERALS CS 2048 LOCATIONS SPORT1 SCLK1 a gt RFS1 OR IRGO lt Data SERIAL TFs1 OR IRAT DEVICE LI or oR FO l ADDR OVERLAY MEMORY TWO 8K PM SEGMENTS TWO 8K SPORTO DM SEGMENTS HOST MEMORY MODE ADSST 2185 KST 133 ADDRO RFS1 OR I
7. 3 includes an on chip oscillator circuit an external crystal may be used The crystal should be connected across the CLKIN and XTAL pins with two capacitors connected as shown in Figure 3 Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer A parallel resonant fundamental frequency microprocessor grade crystal should be used CLKOUT Figure 3 External Crystal Connections A clock output CLKOUT signal is generated by the processor at the processor s cycle rate This can be enabled and disabled by the CLKODIS bit in the SPORTO Autobuffer Control Register Reset The RESET signal initiates a master reset of the ADSST 2185KST 133 The RESET signal must be asserted during the power up sequence to assure proper initialization RESET dur ing initial power up must be held long enough to allow the internal clock to stabilize If RESET is activated any time after power up the clock continues to run and does not require stabi lization time The power up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor and for the internal phase locked loop PLL to lock onto the specific crystal frequency A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start up time During this power up sequence the RESET signal should be held low On any subse
8. 80 mW Max Power Consumption at 2 7 V On Chip Reference 28 Lead SOIC VINP1 SIGNAL 0 38dB a CONDITIONING i PGA VINN1 O VINP2 Q REFOUT ba Am VINP4 VINP5 ANALOG X A CONDITIONING Ku ae8e poe PGA VINN2 CONDITIONING MINPS O ANALOG joan gees 2 A DECIMATOR V NN3 CONDITIONING _PGA CONDITIONING O REFCAP REFERENCE CONDITIONING PGA VINN4 CONDITIONING a SIGNAL Ei WAB ANALOG CONDITIONING PGA VINN5 CONDITIONING VINP6 ia SIGNAL Ei 0 3848 ANALOG CONDITIONING PGA VINN6 O CONDITIONING GENERAL DESCRIPTION The ADSST 73360AR is a six input channel analog front end processor for power metering It features six 16 bit A D conver sion provide 76 dB signal to noise ratio over a dc to 4 kHz signal bandwidth Each channel also features a programmable input gain amplifier PGA with gain settings in eight stages from 0 dB to 38 dB The ADSST 73360AR is particularly suitable for industrial power metering as each channel samples synchronously ensur ing that there is no phase delay between the conversions The ADSST 73360AR also features low group delay conversions on all channels An on chip reference voltage is included with a nominal value of 1 2 V The sampling rate of the device is programmable with four separate settings offering 64 kHz 32 kHz 16 kHz and 8 kHz sampling rates from a master clock of 16 384 MHz A serial port SPORT allows easy interfacing of single or cas cade
9. ANALOG DEVICES SALEM Three Phase Electronic Energy Meter ADSST EM 3035 FEATURES IEC 687 Class 0 5 and Class 0 2 Accuracy ANSI C12 1 IEC 1268 Requirements for Reactive Power Configurable as Import Export or Import Only Simultaneous Measurement of Active Power and Energy Import and Export Reactive Power and Energy Apparent Power Power Factor for Individual Phases and Total Frequency RMS Voltage for All Phases RMS Current for All Phases Harmonic Analysis for Voltage and Current All Odd Harmonics up to 21st Order Interface with a General Purpose Microcontroller User Friendly Calibration of Gain Offset and Phase and Nonlinearity Compensation on CTs Patent Pending Two Programmable Output E Pulses Programmable E Pulse Constant from 1 000 Pulses kWh to 20 000 Pulses kWh 15 kHz Sampling Frequency Tamper Proof Metering Single 5 V Supply GENERAL DESCRIPTION The ADSST EM 3035 Chipset consists of a fast and accurate 6 channel 16 bit sigma delta analog to digital converter ADSST 73360AR ADC an efficient digital signal processor ADSST 2185KST 133 DSP and Metering Software The ADC and DSP are interfaced together to simultaneously acquire voltage and current samples on all the three phases and perform mathematically intensive computations to accurately calculate the Powers Energies Instantaneous Quantities and Harmonics The chipset could be interfaced to any general purpose micropro cessor to develop state
10. Energy Import Total Apparent Energy Total Inductive Energy Total Active Energy Export Total Capacitive Energy Frequency R Phase Channel_Present Y Phase Channel_Present NAA A A ANAMRAA AAA AMAANAAAANNAAAMAANAAMAANNAAAAANAAAANN eH 15 ADSST EM 3035 DATA from DSP on SPI BUS Byte s B Phase Channel_Present R Phase Current Division FlagUnits flag R Y Phase Current Division FlagUnits flag Y B Phase Current Division FlagUnits flag B R Phase Negative Power Flag Y Phase Negative Power Flag B Phase Negative Power Flag R Phase INDUC CAP POWER Flag Y Phase INDUC CAP POWER Flag B Phase INDUC CAP POWER Flag ee a a ep GAIN CONTRASTS AND DC OFFSETS R Phase Voltage Gain Y Phase Voltage Gain B Phase Voltage Gain R Phase Current Low Gain Y Phase Current Low Gain B Phase Current Low Gain R Phase Current High Gain Y Phase Current High Gain B Phase Current High Gain R Phase Voltage DC Offset Y Phase Voltage DC Offset B Phase Voltage DC Offset R Phase Current Low Gain DC Offset Y Phase Current Low Gain DC Offset B Phase Current Low Gain DC Offset R Phase Current High Gain DC Offset Y Phase Current High Gain DC Offset B Phase Current High Gain DC Offset DC_Offset Calibration Done EFh Total Negative Power Flag Total Inductive Capacitive Flag Fr rFNNNNNNNNNNNNNNNNLDND LDH HARMONIC ANALYSIS DATA All odd harmonics sequenced from fundamental to 21st order total 11 harmonics
11. Input to the Negative Terminal of Input SE is low Channel 4 SDOFS Framing Signal Output for SDO Serial Transfers The za frame sync is one bit wide and it is active one SCLK period SINES s tothe Positive Terminal of Input before the first bit MSB of each output word SDOFS is referenced to the positive edge of SCLK SDOFS is VINN5 Analog Input to the Negative Terminal of Input in three state when SE is low Channels SDIFS Framing Signal Input for SDI Serial Transfers The frame VINP6 Analog Input to the Positive Terminal of Input sync is one bit wide and it is valid one SCLK period Channel 6 before the first bit MSB of each input word SDIFS is sampled on the negative edge of SCLK and is ignored VINN6 Analog Input to the Negative Terminal of Input when SE is low Channel 6 z F SDI Serial Data Input of the ADSST 73360AR Both data REFOUT Buffered Reference Output which has a nominal value and control information may be input on this pin and are of 1 2 V or 2 4 V the value being dependent on the clocked on the negative edge of SCLK SDI is ignored status of Bit 5 VEN CRC 7 This pin can be overdriven when SE is low by an external reference if required 7 SE SPORT Enable Asynchronous input enable pin for the REFCAP A Bypass Capacitor to AGND2 of 0 1 uF is required SPORT When SE is set low by the DSP the output pins for the on chip reference The capacitor should be of the SPORT are three stated and the input pins are fixed to this pin
12. K 13 16 SDIFS spo 14 PIN FUNCTION DESCRIPTIONS Mnemonic Function Mnemonic Function VINP1 Analog Input to the Positive Terminal of Input RESET Active Low Reset Signal This input resets the entire chip Channel 1 resetting the control registers and clearing the digital VINN1 Analog Input to the Negative Terminal of Input oe Channel 1 SCLK Output Serial Clock whose rate determines the serial trans F fer rate to from the ADSST73360AR It is used to clock VINP2 Analog Input to the Positive Terminal of Input data or control information to and from the serial port Channel 2 SPORT The frequency of SCLK is equal to the frequency VINN2 Analog Input to the Negative Terminal of Input of the master clock MCLK divided by an integer number Channel 2 This integer number being the product of the external master clock rate divider and the serial clock rate divider VINP3 Analog Input to the Positive Terminal of Input Channel 3 MCLK Master Clock Input MCLK is driven from an external clock signal VINN3 Analog Input to the Negative Terminal of Input Channel 3 SDO Serial Data Output of the ADSST 73360AR Both data and control information may be output on this pin and are VINP4 Analog Input to the Positive Terminal of Input clocked on the positive edge of SCLK SDO is in three Channel 4 state when no information is being transmitted and when VINN4 Analog
13. O Combined Memory Interrupts Select Output F1 FO Flag In Flag Out RD 1 O Memory Read Enable Output PWD 1 I Power Down Control Input WR 1 O Memory Read Enable Output PWDACK l O Power Down Control Output IRQ2 PF7 1 I Edge or Level Sensitive FLO FL1 33 O Output Flags Interrupt Request FL2 IRQLO PF5 1 I Level Sensitive VDD 16 I VDD and GND Interrupt Requests AND IRQLI PF6 1 I Level Sensitive GND Interrupt Requests EX Port 9 1 0 For Emulation Use TRQE PF4 1 I Edge Sensitive NOTES Interrupt Requests 1 Interrupt Flag pins retain both functions concurrently If IMASK is set to enable PF3 1 1 0 Programmable 1 0 Pin the corresponding interrupts the DSP will vector to the appropriate interrupt PF2 Mode C 1 I Programmable I O Pin Mode vector address when the pin is asserted either by external devices or set as a Select Input Checked only 2 ANA determined by the DSP System Control Register Software During RESET configurable PF1 Mode B 1 I Mode Select Input Checked only During RESET REV 0 eer e ee ee ee ee ee eee SEGSGSSSSSESESS ASS RASASEEER RIR RRR P S feo siel Si S BS S S SS fe fo fo S gia Nii zia nna sia 1n073 61a 104 an9 33 A oza sna z iza 13534 8 zza 13s343 Pa eza o LyT9S v ha HI zld YA and x 4 TEE bua g 013 was oouyissy a edd o gt LOH SL fy o 3aowl z4d NOs OJ 1A So aaa 5 E aga aMd 2 0y79S S GND lt x oya d la 3aowl Ld 0534 2 v IQON
14. RQO lori onFo WA DR1 OR FI SERIAL DEVICE SPORTO SCLKO ui SERIAL 4 DEVICE e4 are IDMA PORT TRD D6 SYSTEM INTERFACE OR Figure 2 Basic System Interface Recommended Operating Conditions A Grade B Grade Parameters Min Maz Min Max Unit Vpp Supply Voltage 45 5 5 4 5 55 V Tams Ambient 0 70 40 85 C Operating Temperature Clock Signals Either a crystal or a TTL compatible clock signal can clock the ADSST 2185KST 133 The CLKIN input cannot be halted changed during operation or operated below the specified frequency during normal operation The only exception is while the processor is in the power down state For additional information refer to Chapter 9 ADSP 2100 Family User s Manual Third Edition for detailed information on this power down feature If an external clock is used it should be a TTL compatible signal running at half the instruction rate The signal is connected to the processor s CLKIN input When an external clock is used the XTAL input must be left unconnected The ADSST 2185KST 133 uses an input clock with a frequency equal to half the instruction rate a 20 00 MHz input clock yields a 25 ns processor cycle which is equivalent to 40 MHz Normally instructions are executed in a single processor cycle All device timing is relative to the internal instruction clock rate which is indicated by the CLKOUT signal when enabled Because the ADSST 2185KST 13
15. UUUL CLOCK AAKA AKI DATA Figure 9 SPI Sequence of Operation Quadrant and Other Conventions The data sent by the DSP is based on the following convention e Figure 10 gives the quadrant convention used by the chipset e Import means delivered from the utility to the user e Export means delivered by the user to the utility e Total means total of all three phases REACTIVE lt 4 ____ _____ _ ACTIVE EXPORT ACTIVE IMPORT CAPACITIVE INDUCTIVE REACTIVE Figure 10 Power Up Initialization To reduce the component count cost and to give designer a greater flexibility in designing ADSST EM 3035 has not been provided with any Nonvolatile Memory to store the calibration constants and initialization data On power up after the boot loading of the DSP software the microcontroller provides the DSP with all the initialization data After receiving the initializa tion data the DSP starts the metering The table below list outs the data that has to be transferred to the DSP on power up REV 0 ADSST EM 3035 Table III Data Transfer to DSP on Power Up Initialization Gain Constants and DC Offsets Value Defaults R Phase Voltage Gain 2 4000h Y Phase Voltage Gain 2 4000h B Phase Voltage Gain 2 4000h R Phase Current Low Gain 2 4000h Y Phase Current Low Gain 2 4000h B Phase Current Low Gain 2 4000h R Phase Current High Gain 2 4000h Y Phase Current High Gain 2 4000h B Phase C
16. a 1 75 SeaTiIna PLANE TOP VIEW PINS DOWN 0 50 BSC COMPLIANT TO JEDEC STANDARDS MS 026AED HD CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED 28 Lead Standard Small Outline Package SOIC Wide Body RW 28 Dimensions shown in millimeters and inches 18 10 0 7126 0 30 0 0118 0 10 0 0039 y COPLANARITY 17 70 0 6969 PAA AAR RRR 28 15 i 7 60 0 2992 7 40 0 2913 10 65 0 4193 zi ihs 10 00 0 3937 HH yo 2 65 0 1043 0 75 0 0295 4 2 35 0 0925 0 25 0 0098 a a 4 gt e le 8 gt je 1 27 0 0500 0 51 0 0201 Beene 0 32 0 0126 0 1 27 0 0500 0 33 0 0130 0 23 0 0091 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 20 REV 0 C02740 0 11 02 0 PRINTED IN U S A
17. aken with regard to grounding and layout The printed circuit board that houses the ADSST 73360AR should be designed so the analog and digital sections are sepa rated and confined to certain sections of the board The ADSST 73360AR pin configuration offers a major advantage in that its analog and digital interfaces are connected on opposite sides of the package This facilitates the use of ground planes that can be easily separated as shown in Figure 5 A minimum etch technique is generally best for ground planes as it gives the best shielding Digital and analog ground planes should be joined in only one place If this connection is close to the device it is recommended to use a ferrite bead inductor as shown in Figure 5 Avoid running digital lines under the device for they will couple noise onto the die The analog ground plane should be allowed to run under the ADSST 73360AR to avoid noise coupling The power supply lines to the ADSST 73360AR should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply lines Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs Traces on opposite sides of the board should run at right angles to each other This will reduce the effects of feedthrough through the board A micro strip technique is by far t
18. ata address pointers Perform a computational operation This takes place while the processor continues to Receive and transmit data through the two serial ports Receive and or transmit data through the internal DMA port Receive and or transmit data through the byte DMA port Decrement timer DATA ADDRESS GENERATORS SEQUENCER POWER DOWN CONTROL FULL MEMORY MODE MEMORY 16K x 24 16K x 16 PROGRA DATA MEMORY MEMORY PROGRAMMABLE Vo EXTERNAL AND ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER OR DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS SERIAL PORTS INTERNAL mah PORT ADSP 2100 BASE ARCHITECTURE HOST MODE Figure 1 Functional Block Diagram REV 0 ADSST EM 3035 ARCHITECTURE OVERVIEW The ADSST 2185KST 133 instruction set provides flexible data moves and multifunction one or two data moves with a computation instructions Every instruction can be executed in a single processor cycle The ADSST 2185KST 133 assembly language uses an algebraic syntax for ease of coding and read ability A comprehensive set of development tools supports program development Figure 1 is an overall block diagram of the ADSST 2185KST 133 The processor contains three independent computational units the ALU the multiplier accumulator MAC and the shifter The computational units process 16 bit data directly and have provisions
19. cess of executing the metering code on the DSP does not start Soon after receiving all the constants i e 154 bytes the metering process starts Four dummy bytes have to be sent after the start of execution for the DSP to send back the check sum of its internal code The microcontroller can use this to verify that the complete metering code has been loaded on the DSP processor properly The DSP is now ready to provide the computed data on the SPI port T1 MINIMUM 6 DSP PIN BOOT 1 CLOCK CYCLES PIN BOOT 2 BR H Figure 7 Timing Diagram for Boot Loading the DSP Processor REV 0 13 ADSST EM 3035 SERIAL PERIPHERAL INTERFACE SPI AND CONTROL The DSP and the microcontroller are interfaced through Serial Peripheral Interface SPI The microcontroller is always config ured as a master and the DSP as a slave FRAMING SIGNAL DSP CONTROL SPI TRANSMIT SPI RECEIVE CLK INTERRUPT DSP MICROCONTROLLER Figure 8 Serial Peripheral Interface and Control SPI OPERATION There are two modes of communication between DSP and microcontroller e Microcontroller to DSP while uploading the initial data of 154 bytes including four bytes to read checksum of code from DSP and sending a command Bring the DSP_control pin low i e give a high to low transition This informs the DSP that the data after this transition is a valid data Send the data byte on the microcontroller s SPI po
20. d devices to industry standard DSP engines The SPORT transfer rate is programmable to allow interfacing to both fast and slow DSP engines The ADSST 73360AR is available in 28 lead SOIC DECIMATOR O SDI SDIFS O SCLK DECIMATOR RESET ADSST 73360AR sis ays ere DECIMATOR DECIMATOR SDO DECIMATOR SE Figure 4 Functional Block Diagram 8 REV 0 SPECIFICATIONS ADSST 73360AR ADSST EM 3035 AVDD 5 V 10 DVDD 5 V 10 DGND AGND 0 V fuck 16 384 MHz frou 8 192 MHz fs 8 kHz Ta Twin to Tmax unless otherwise noted Parameter Min Typ Max Unit Test Conditions Comments REFERENCE REFCAP Absolute Voltage Vgercap 1 25 V 5 VEN 0 2 5 V 5 VEN 1 REFCAP TC 50 ppm C 0 1 UF Capacitor Required from REFCAP to AGND2 REFOUT Typical Output Impedance 130 Q Absolute Voltage VREfoUT 1 25 V 5 VEN 0 Unloaded 2 5 V 5 VEN 1 Unloaded Minimum Load Resistance 2 kQ 5 VEN 1 Maximum Load Capacitance 100 pF ADC SPECIFICATIONS Maximum Input Range at VIN 3 156 Vp p 5 VEN 1 Measured Differentially 3 17 dBm Nominal Reference Level at VIN 2 1908 V p p 5 VEN 1 Measured Differentially 0 dBm0 0 dBm Absolute Gain PGA 0 dB 0 1 dB 1 0 kHz PGA 38 dB 0 5 dB 1 0 kHz Gain Tracking Error 0 1 dB 1 0 kHz 3 dBm0 to 50 dBm0 Signal to Noise Distortion PGA 0 dB 76 dB 0 Hz to fs 2 fs 8 kHz PGA 38 dB 70 dB 0 Hz to 4 kHz fs 64 kHz Total Harmonic Distortion
21. e ADSST 2185KST 133 combines the ADSP 2100 family base architecture three computational units data address generators and a program sequencer with two serial ports a 16 bit internal DMA port a byte DMA port a programmable timer Flag I O extensive interrupt capabilities and on chip program and data memory The ADSST 2185KST 133 integrates 40 kBytes of on chip memory configured as 8 Kwords 24 bit of program RAM and 8 Kwords 16 bit of data RAM Power down circuitry is also provided to meet the low power needs of battery operated portable equipment The ADSST 2185KST 133 is available in a 100 lead TQFP package In addition the ADSST 2185KST 133 supports instructions that include bit manipulations bit set bit clear bit toggle bit test new ALU constants new multiplication instruction x squared biased rounding result free ALU operations I O memory trans fers and global interrupt masking for increased flexibility Fabricated in a high speed double metal low power CMOS process the ADSST 2185KST 133 operates with a 25 ns instruction cycle time Every instruction can execute in a single processor cycle The ADSST 2185KST 133 s flexible architecture and com prehensive instruction set allow the processor to perform multiple operations in parallel In one processor cycle the ADSST 2185KST 133 can e Generate the next program address e Fetch the next instruction e Perform one or two data moves e Update one or two d
22. els Set current at 20 A lt I lt 7 A and perform phase compensation for all channels Set current at 1 5 A lt I lt 7 A and perform phase compensation for all channels Set current at 1 5 A lt I lt 0 A and perform phase compensa tion for all channels Table XI Nominal Value Reference Design Parameters Parameters Nominal Value Nominal Voltage Neutral to Line Vy Max Voltage Neutral to Line Max Current Imax Base Current Frequency Power Factor Vn 230 V 1 300 V Imax 20A In 5A Fy 50 Hz 60 Hz 10 1 THD of Voltage lt 2 Temperature 23 2 C Table XII Maximum Error Power and Energies Current Voltage PF Min Typ Max Unit 0 01 In lt I lt 0 05 In Vn 1 0 0 1 0 2 0 05 In lt I lt Imax Vn 1 0 0 1 0 2 0 02 In lt I lt 0 1 In Vn 0 5 Lagging 0 15 0 35 0 8 Leading 0 15 0 35 0 1 In lt I lt Imax Vn 0 5 Lagging 0 1 0 2 0 8 Leading 0 1 0 2 Table XIII Unbalanced Load Error Current Voltage PF Min Typ Max Unit 0 05 In lt I lt Inax Vy 1 0 0 15 0 2 0 1 In lt I lt Imax Vn 0 5 Lagging 0 15 0 2 Table XIV Voltage Variation Error Voltage Current PF Min Typ Max Unit Vy 10 0 05 In lt I lt Inax 1 0 0 05 0 1 Yo Vn 10 0 1 In lt I lt Imax 0 5 Lagging 0 05 0 1 Table XV Frequency Variation Errors Frequency Current PF Min Typ Max Unit Vnt 10 0
23. en grouped as e High current range From 20 Amps to 7 Amps e Middle current range 7 Amps to 1 5 Amps e Low current range 1 5 Amps to 0 Amps REV 0 Data from DSP to Microcontroller To facilitate easy of operation the data transfer form DSP to microcontroller has been segregated into multiple blocks Table IV lists the various data blocks Table IV Data Transfer Sequence from DSP to Microcontroller DATA from DSP on SPI BUS a A g REQUEST CODE 45h R Phase Voltage R Phase Current R Phase Active Power R Phase Apparent Power R Phase Inductive Power R Phase Capacitive Power R Phase Power Factor R Phase Active Energy Import R Phase Apparent Energy R Phase Inductive Energy R Phase Active Energy Export R Phase Capacitive Energy Y Phase Voltage Y Phase Current Y Phase Active Power Y Phase Apparent Power Y Phase Inductive Power Y Phase Capacitive Power Y Phase Power Factor Y Phase Active Energy Import Y Phase Apparent Energy Y Phase Inductive Energy Y Phase Active Energy Export Y Phase Capacitive Energy B Phase Voltage B Phase Current B Phase Active Power B Phase Apparent Power B Phase Inductive Power B Phase Capacitive Power B Phase Power Factor B Phase Active Energy Import B Phase Apparent Energy B Phase Inductive Energy B Phase Active Energy Export B Phase Capacitive Energy Total Active Power Total Apparent Power Total Inductive Power Total Capacitive Power Average Power Factor Total Active
24. erated and the count register is reloaded from a 16 bit period register TPERIOD Serial Ports The ADSST 2185KST 133 incorporates two complete synchronous serial ports SPORTO and SPORT1 for serial communications and multiprocessor communication Here is a brief list of the capabilities of the ADSST 2185KST 133 SPORTs For additional information on Serial Ports refer to the ADSP 2100 Family User s Manual Third Edition e SPORTS are bidirectional and have a separate double buffered transmit and receive section e SPORTs can use an external serial clock or generate their own serial clock internally e SPORTs have independent framing for the receive and transmit sections Sections run in a frameless mode or with frame synchro nization signals internally or externally generated Frame sync signals are active high or inverted with either of two pulsewidths and timings e SPORTS support serial data word lengths from 3 to 16 bits and provide optional A law and M law companding according to CCITT recommendation G 711 e SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer e SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word An interrupt is generated after a data buffer transfer ADSST EM 3035 e SPORTO has a multichannel interface to selectively receive and transmit a 24 or 32 word time division multiplexed serial bi
25. g for circular buffers Efficient data transfer is achieved with the use of five internal buses e Program Memory Address PMA Bus e Program Memory Data PMD Bus e Data Memory Address DMA Bus e Data Memory Data DMD Bus Result R Bus The two address buses PMA and DMA share a single external address bus allowing memory to be expanded off chip and the two data buses PMD and DMD share a single external data bus Byte memory space and I O memory space also share the external buses Program memory can store both instructions and data permitting the ADSST 2185KST 133 to fetch two operands in a single cycle one from program memory and one from data memory The ADSST 2185KST 133 can fetch an operand from program memory and the next instruction in the same cycle When configured in host mode the ADSST 2185KST 133 has a 16 bit Internal DMA port IDMA port for connection to external systems The IDMA port is made up of 16 data address pins and five control pins The IDMA port provides transparent direct access to the DSP s on chip program and data RAM REV 0 An interface to low cost byte wide memory is provided by the Byte DMA port BDMA port The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off chip storage of program overlays or data tables The byte memory and I O memory space interface supports slow memories and I O memory mapped peripherals with programmable wai
26. gy e Reactive energy Table III gives the default conditions and configuration for first E pulse The E pulse constant is variable from 1 000 pulses kWh to 20 000 pulses kWh Example To set 1 500 pulses kWh the new E pulse con stant will be 1 500 Inaccuracy of the E pulse Higher E pulse constant is always desirable as it reduces the testing time However increase in pulses kWh may increases the error at higher power The error can be calculated by the given formula General Note About Calibration e It should be noted that ADSST EM 3035 does not have any permanent memory and hence all the calibration data are to be stored by the microcontroller and provided to the DSP at the time of power up e Before starting the calibration the meter should be supplied with the default calibration constants as specified in the Table III REV 0 ADSST EM 3035 MEASUREMENT ACCURACY Overall Accuracy Power and Energy Measurement The accuracy figures are measured in nominal conditions unless otherwise indicated The measurement are taken on the reference design with the given below nominal values Reference Design with p Metal CT 0 5 Class e The whole calibration can be done in very few steps as shown in the example below Start meter with nominal voltage and calculate dc offset Set current at 20 A and calculate voltage gain and low current gain for all channels Set current at 5 A and calculate low current gain for all chann
27. he best but is not always possible with a double sided board In this tech nique the component side of the board is dedicated to ground planes while signals are placed on the other side Good decoupling is important when using high speed devices All analog and digital supplies should be decoupled to AGND 12 and DGND respectively with 0 1 UF ceramic capacitors in parallel with 10 UF tantalum capacitors To achieve the best from these decoupling capacitors they should be placed as close as possible to the device ideally right up against it In systems where a common supply voltage drives both the AVDD and DVDD of the ADSST 73360AR it is recommended that the system s AVDD supply be used This supply should have the recommended analog supply decoupling between the AVDD pins of the ADSST 73360AR and AGND and the recommended digital supply decoupling capacitors between the DVDD pin and DGND NOTE FOR MORE DETAILS ON ADSST 73360AR PLEASE REFER TO DATA SHEET OF AD73360 Interfaces between ADSST EM 3035 and Microcontroller Overview The following paragraphs describe the interface between the ADSST EM 3035 chipset and the microcontroller The sequence of operations is a critical issue for proper functioning of the two processors on the board The DSP processor is primarily used to compute various parameters provide the impulse outputs on the external LEDs and provide automatic gain switching inside the ADC The microcontroller can co
28. ignored SCLK is also disabled internally in order to decrease AVpp2 Analog Power Supply Connection power dissipation When SE is brought high the control and data registers of the SPORT are at their original values AGND2 Analog Ground Substrate Connection before SE was brought low However the timing counters DGND Digital Ground Substrate Connection and other internal registers are at their reset values DVpp Digital Power Supply Connection AGNDI Analog Ground Connection AVpp1 Analog Power Supply Connection REV 0 11 ADSST EM 3035 Grounding and Layout ANALOG GROUND DIGITAL GROUND Figure 5 Grounding and Layout Since the analog inputs to the ADSST 73360AR are differential most of the voltages in the analog modulator are common mode voltages The excellent common mode rejection of the part will remove common mode noise on these inputs The analog and digital supplies of the ADSST 73360AR are independent and separately pinned out to minimize coupling between analog and digital sections of the device The digital filters on the encoder section will provide rejection of broadband noise on the power supplies except at integer multiples of the modulator sampling frequency The digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modulator However because the resolution of the ADSST 73360LAR ADC is high and the noise levels from the ADSST 73360AR are so low care must be t
29. ipset is an executable file for calculation of the phase compensation coefficients e Set the voltage equal to 230 V which is the nominal voltage at all phases Inject I current at 0 5 inductive 60 lagging in all phases e The chipset performs the harmonic analysis by providing information about the magnitude and phase angle for all odd harmonics sequenced from fundamental to 21st order The DSP sends the phase angle information along with other data as described in Table IV after sending the command 0x45 e The value of the phase angle for line current A B and C is available at the locations 283 371 and 459 respectively say Pa Pg Pc in the data stream sent by the DSP 18 e Calculate the normalized lag value La Lg Lc for each phase as under 60 P 2 1 A 1 20 g 60 P Lz 2 2 P 1 20 60 P pe 3 1 20 Mm Run ADSSTCOMP EXE on PC Feed the normalized lag value during the ezecution of ADSSTCOMP EXE The ADSSTCOMP EXE will provide six coefficients for each phase and the size of each coefficient is 2 bytes The phase compensation should be performed for the three currents on each phase These coefficients must be stored in a suitable location such that DSP can get these coefficients on power up in the same sequence as shown in Table II Configuration of Output E pulses The ADSST EM 3035 Chipset provides two pulse outputs e Configurable for Active energy or Apparent ener
30. llect the data from the chipset for data management for further processing There are two basic functions that the microcontroller performs in a handshaking mode with the DSP processor e Boot loading the DSP with metering software on power up for non ROM coded version only e Communication with the DSP on SPI to Send Initialization data on power up after boot loading the DSP with metering software Receive data from DSP during normal operation Receive and send data during calibration This section describes the Boot loading and SPI operations BOOT LOADING THE DSP PROCESSOR FROM THE MICROCONTROLLER The DSP processor has an internal program memory RAM that supports boot loading With boot loading the processor reads instructions from a byte wide data bus connected to the microcon troller and stores the instructions in the 24 bit wide internal program memory The host microcontroller is the source of bytes to be loaded into on chip memory The choice of which technique to use depends upon the I O structure of the host microcontroller availability of I O port lines and the amount of address decoding logic already available in the system The description here is one of the many ways that this could be configured However the software on the microcontroller has been written in way to make optimum use of the configuration Figure 6 illustrates the system implementation to allow a microcontroller to boot the DSP processor The only ha
31. ltage 0 3 V to 7 0 V Input Voltage 0 3 V to Vpp 0 3 V Output Voltage Swing 0 3 V to Vpp 0 3 V Operating Temperature Range Ambient 40 C to 85 C Storage Temperature Range 65 C to 150 C Lead Temperature 5 sec TQFP 280 C Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability REV 0 ENVIRONMENTAL CONDITIONS Ambient Temperature Rating Tame Tcasz PD X Oca Tcasr Case Temperature in C PD Power Dissipation in W Oja Thermal Resistance Junction to Ambient Ojc Thermal Resistance Junction to Case Oca Thermal Resistance Case to Ambient Package Oya c 8ca TQFP 50 C W 2 C W 48 C W ADSST EM 3035 ADSST 73360AR ADC FEATURES Six 16 Bit A D Converters Programmable Input Sample Rate Simultaneous Sampling 76 dB SNR 64 kS s Maximum Sample Rate 83 dB Crosstalk Low Group Delay 125 ps Typ per ADC Channel Programmable Input Gain Flexible Serial Port which Allows Multiple Devices to be Connected in Cascade Single 2 7 V to 5 5 V Supply Operation
32. n resistance on the secondary side of the CT ADSST 73360AR being a unipolar ADC the ac poten tial and current have to be offset by a desired dc level The reference design has a dc offset of 2 5 V This limits the p p signal range of potential and current to 1 64 V peak or 1 16 Vrms For details please refer to the data sheet of AD73360 Potential Section The selection of potential divider circuit should be such that it can Handle high surge voltages Should have minimum VA burden e Give approximately 0 656 V rms output at nominal voltage such that it sufficiently takes care of over voltage The reference design has 1 MQ and 3 3 kQ resistance network Current Section The selection of CT ratio and burden resistance should be such that it can e Handle the complete dynamic range for the current signal input e Give around 1 V 0 pk output at maximum current such that it sufficiently takes of loads with low crest factors and current surges REV 0 The reference design has a CT with turn ratio of 1 2500 and burden resistance of 82 Q This generates 0 656 V rms or 0 928 V 0 pk at 20 amps current This leaves enough margins for cur rent pulses or low crest factor loads such as electronic loads such as SMPS The maximum current can be up to 32 767 amps CALIBRATION ADSST EM 3035 Chipset has a highly advance calibration routines embedded into the software Easy of calibration is the philosophy in ADSST EM 3035 Chipse
33. of 2 bytes each R Phase Voltage Components Magnitude 2X 11 22 R Phase Current Components Magnitude 22 R Phase Voltage Components Phase 22 R Phase Current Components Phase 22 Y Phase Voltage Components Magnitude 22 Y Phase Current Components Magnitude 22 Y Phase Voltage Components Phase 22 Y Phase Current Components Phase 22 B Phase Voltage Components Magnitude 22 B Phase Current Components Magnitude 22 B Phase Voltage Components Phase 22 B Phase Current Components Phase 22 16 Table V Interpretation of the Voltage Data Phase Voltage Data from DSP Hex 2 byte Decimal Voltage 5A10h 23056 230 56 V Table VI Interpretation of the Current Data Line Current Data Unit from DSP flag X Hex 2 Byte Decimal X RIYIB Current 278Bh 10123 1 1 0123 A 278Bh 10123 0 10 123 A Frequency Data from DSP The frequency data is with two decimal places This means that the value has to be divided by 100 to get the frequency For example if DSP data 139Fh decimal value 5023 then the frequency is 50 23 Hz Interpretation of the Power Data As in the case of current and voltages described above all the power data supplied by DSP has to be interpreted as shown in Table VII The data received from the DSP is in a 4 byte format The least significant word comes first and the most significant word comes last e g 000D1C4A will come as 1C4A000D and this word reversal has to be perfo
34. of the art polyphase or Tri vector energy metering solution in accordance with IEC 1036 IEC 687 or ANSI C12 1 All calibrations are done in digital domain and no trimming potentiometers are required SALEM is a registered trademark of Analog Devices Inc REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM LCD DISPLAY RESISTOR SPI BUS BUTTONS ADSST EM 3035 CHIPSET One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2002 ADSST EM 3035 ADSST 2185KST 133 DSP SPECIFICATION FEATURES 30 ns Instruction Cycle 33 MIPS Sustained Performance Single Cycle Instruction Execution Single Cycle Context Switch Three Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power Down Condition Low Power Dissipation in Idle Mode ADSP 2100 Family Code Compatible with Instruction Set Extensions 40 kBytes of On Chip RAM Configured as 8 KWords On Chip Program Memory RAM and 8
35. or of ADC 4Guaranteed by design Overall group delay will be affected by the sample rate and the external digital filtering The ADCs input impedance is inversely proportional to DMCLK and is approximated by 4 10 DMCLK Frequency response of ADC measured with input at audio reference level the input level that produces an output level of 10 dBm0 with 38 dB preamplifier bypassed and input gain of 0 dB 8Test Conditions no load on digital inputs analog inputs ac coupled to ground Specifications subject to change without notice Table II Current Summary AVpp DVpp 3 3 V Analog Digital Total MCLKON Conditions Current Current Current Max SE ON Comments ADCs Only On 16 16 32 1 YES REFOUT Disabled REFCAP Only On 0 8 0 0 8 0 NO REFOUT Disabled REFCAP and REFOUT Only On 3 5 0 3 5 0 NO All Sections Off 0 1 1 9 2 0 0 YES MCLK Active Levels Equal to 0 V and DVpp All Sections Off 0 0 05 0 06 0 NO Digital Inputs Static and Equal to 0 V and DVpp ABSOLUTE MAXIMUM RATINGS Maximum Junction Temperature 150 C Ta 25 C unless otherwise noted SOIC ja Thermal Impedance 75 C W AVpp DVpp tOGND 6 esie eaii e A E e 0 3 V to 7 V Lead Temperature Soldering AGND to DGND 0 3 V to 0 3 V Vapor Phase 60 sec ii mesar cece eee cence R 215 C Digital I O Voltage to DGND 0 3 V to DVpp 0 3 V Infrared I5 SEO ea o E vied ag A
36. quent resets the RESET signal must meet the minimum pulsewidth specification tpsp The RESET input contains some hysteresis however if you use an RC circuit to generate your RESET signal the use of an external Schmidt trigger is recommended The master reset sets all internal stack pointers to the empty stack condition masks all interrupts and clears the MSTAT register When RESET is released if there is no pending bus request and the chip is con figured for booting the boot loading sequence is performed The first instruction is fetched from on chip program memory location 0x0000 once boot loading completes REV 0 ELECTRICAL CHARACTERISTICS ADSST EM 3035 KIB Grade Parameters Test Conditions Min Typ Max Unit Vin High Level Input Voltage Vpp max 2 0 V Vin High Level CLKIN Voltage Vpp max 2 2 V Vit Low Level Input Voltage Vpp min 0 8 V Vou High Level Output Voltage gt Vpp min Io 0 5 max 2 4 V Vpp min lou 100 ua Vpp 0 3 V VoL Low Level Output Voltage gt Vpp min 0 4 V IoL 2 mA lu High Level Input Current Vpp max Vin Vpp max 10 UA I Low Level Input Current Vpp max Vin 0V 10 UA loz Three State Leakage Current Vpp max Vin Vpp max 10 UA loz Three State Leakage Current Vpp max Vin 0 V8 10 uA Ipp Supply Current Idle Vpp 5 0 12 4 mA Ipp Supply Current Vppmt 5 0 Dynamic Tamp 25 C tcx 30 ns 55 mA tex
37. rdware required is a D type flip flop and a 5 kQ resistor The resistor is used to pull the DSP processor s BMS pin Boot Memory Select high The DSP processor boots using the BDMA option The BDMA option can be used when pins Mode A Mode B and Mode C on the DSP are tied low With these pins tied low the DSP auto matically enters its boot sequence after the processor is reset REV 0 ADSST EM 3035 In the sequence of booting the DSP it has to be loaded with an object code into the internal program memory The byte wide memory boot code file has the following structure a 32 words or 96 bytes of the initial header program code it will overwrite the first 113 words i e 339 bytes After reading 20136 bytes it will start execution auto matically The process of loading the code to the DSP is as follows b 81 words or 243 bytes for initializing BDMA and associated e After the microcontroller is reset hold DSP in reset by bringing registers c 6712 words or 20136 bytes of program code Figure 6 System Architecture for Boot Loading DSP Processor From Microcontroller When the DSP is reset with the pins Mode A Mode B and Mode C tied low it enters into the byte wide memory data access mode The boot loading process will consist of the DSP reading the first 32 words a small delay say one millisecond for it execute these 32 words of program The DSP will then read the next 81 words After which a small dela
38. rmed by the controller Table VII Interpretation of the Power Data Power Data from DSP Hex 4 Byte Decimal Power 000D1C4A 859210 859 210 W Interpretation of the Power Factor Data The DSP data for power factor has a resolution up to four deci mal places To get the value of Power Factor the DSP data has to be divided by 10 000 Table VIII Interpretation of the Power Factor Data Power Factor Data from DSP Hex 2 Byte Decimal Power Factor 1388h 5000 0 5 Interpretation of the Energy Data The DSP data for energy has a resolution up to four decimal places To get the value of Energy the DSP data has to be divided by 10 000 Table IX Interpretation of the Energy Data Energy Data from DSP Hex 4 Byte Decimal Energy 000D1C4Ah 859210 85 9210 kWh REV 0 ADSST EM 3035 Interpretation of Harmonics Data Each harmonic data from DSP is two byte wide The voltage and phase angle values have a resolution of up to second deci mal place and the current has up to third decimal place INPUT SECTION PHASE VOLTAGE 0 001 uF 3 3kQ NEUTRAL GND PDSP LINE CURRENT 1000 TO ADC 820 0 01pF GND Voc VALUE MAY CHANGE ACCORDING Figure 11 Input Section ADSST 73360AR has an input range of Vref Vrer X 0 6525 to Vrer Vrer X 0 6525 V p p 0 856 V to 4 14 V for 2 5 V Veer This limit defines the resistance network on the potential circuits and the burde
39. rt Since the microcontroller is configured as a master the clock signal will be generated by the microcontroller and the DSP being a slave will read the data byte in sync with the clock signal Bring DSP_control signal back to high state e DSP to Microcontroller while transmitting computed data to the microcontroller The DSP during its metering code execution is ready to give the computed parameters to the microcontroller after every 32 cycles of power line To request data from the DSP the microcontroller sends a request code 45h on the SPI bus The DSP then sends a high to low transition on Pin FL2 soon after it completes the next 32 cycles of computation as an indication to the microcontroller that it is ready to transmit most recent data Since the microcontroller is a master it has to now send clock signal to the DSP on the SPI to receive data For the clock signal to be generated the microcontroller has to send a dummy byte The dummy byte say OxFF should be one that is not recognized by the DSP as a command The microcontroller may send as many dummy bytes as it requires up to a maximum of 522 bytes for the complete 14 data train The data received from the DSP will be in the same sequence as described in Table IV If the micro controller does not require all the parameters then it may stop sending dummy bytes at any time The diagram below shows the sequence of operation j eee j FRAMING SIGNAL JUUUUU
40. s DC Offset Calibration for Voltage and Current Writing EFh to DSP on SPI initiates the dc offset calibration in the DSP After 32 cycles the DSP returns back the offset values and sends FEh as a mark of completion on the SPI The microcontroller has to store the dc offset constants for uploading during power up 17 ADSST EM 3035 Table X DC Offset Calibration Data Command from Setup Input DC Offset Microcontrolled Voltage and Calibration in Hex Current Offset OxEF V Nominal Calibration Voltage All Three Phases I 0 The microcontroller now issues 0x45H command on SPI to the DSP The DSP sends back Table IV This table will contain new dc offset coefficients The microcontroller should store these coefficients Procedure e Power up the meter with nominal voltage e Give command for calculation of the coefficient EFh to DSP on SPI o Receive the coefficient by sending Ox45 on SPI after waiting at least 1s e Store the coefficient Phase Compensation The ADSST EM 3035 employs a patent pending algorithm for phase compensation and non linearity This also reduces the cost of the end product by reducing the cost of the sensing ele ments i e CT To compensate for the phase non linearity in CTs the compensation is performed at three current ranges The three current ranges for calibration are e20A gt gt 7A e7TA gt L gt 15A e15A gt L gt 0A Procedure e The ADSSTCOMP EXE supplied with the ch
41. t ADSST EM 3035 chipset enables dc offset and gain computation on the voltage and current channels and also performs phase and nonlinearity compensation on the current transformer Calibrations for power is done internally and no extra procedure is required for it This section describes the calibration procedure required Voltage Gain Calibration To calibrate voltage channel e Inject a known voltage V to the meter based on ADSST EM 3035 Note the voltage read by meter say VM e Voltage gain coefficient Vy V q X 0x4000 e The calculated coefficients are to be communicated to the microcontroller for storage e Repeat the same procedure for all the three channels e Note Where 0x4000 is default coefficient in hex Current Gain Calibration The Current Gain calibration is performed at two current set tings to compute two current gain coefficients namely current high gain and current low gain coefficients In all six current gain coefficients are calculated for all the three phase currents The gains are calculated at eT 20A eL 5A Inject the meter with current value I Note the value of the current sent by meter I Current low gain coefficient I Iq X 0x4000 Inject the meter with I current Note the value of the current sent by meter Im Current high gain coefficient I I X 0x4000 The calculated coefficients are to be communicated to the microcontroller for storage Repeat the procedure for other Phase
42. t state generation External devices can gain control of external buses with bus request grant signals BR BGH and BG One execution mode Go Mode allows the ADSST 2185KST 133 to continue running from on chip memory Normal execution mode requires the processor to halt while buses are granted The ADSST 2185KST 133 can respond to 11 interrupts There are up to six external interrupts one edge sensitive two level sensitive and three configurable and seven internal inter rupts generated by the timer the serial ports SPORTs the Byte DMA port and the power down circuitry There is also a master RESET signal The two serial ports provide a complete synchronous serial interface with optional companding in hard ware and a wide variety of framed or frameless data transmit and receive modes of operation Each port can generate an internal programmable serial clock or accept an external serial clock The ADSST 2185KST 133 provides up to 13 general purpose flag pins The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag In addition eight flags are programmable as inputs or outputs and three flags are always outputs A programmable interval timer generates periodic interrupts A 16 bit count register TCOUNT decrements every n processor cycle where n is a scaling value stored in an 8 bit register TSCALE When the value of the count register reaches zero an interrupt is gen
43. to support multiprecision computations The ALU performs a standard set of arithmetic and logic operations division primitives are also supported The MAC performs single cycle multiply multiply add and multiply subtract operations with 40 bits of accumulation The shifter performs logical and arithmetic shifts normalization denormalization and derive exponent operations The shifter can be used to efficiently implement numeric format control including multiword and block floating point representations The internal result R bus connects the computational units so the output of any unit may be the input of any unit on the next cycle A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these com putational units The sequencer supports conditional jumps subroutine calls and returns in a single cycle With internal loop counters and loop stacks the ADSST 2185KST 133 executes looped code with zero overhead No explicit jump instructions are required to maintain loops Two data address generators DAGs provide addresses for simul taneous dual operand fetches from data memory and program memory Each DAG maintains and updates four address pointers Whenever the pointer is used to access data indirect addressing it is post modified by the value of one of four possible modify registers A length value may be associated with each pointer to implement automatic modulo addressin
44. tstream e SPORT can be configured to have two external interrupts IRQO and IRQ1 and the Flag In and Flag Out signals The internally generated serial clock may still be used in this configuration Pin Descriptions The ADSST 2185KST 133 is available in a 100 lead TQFP package To maintain maximum functionality and reduce pack age size and pin count some serial ports programmable flags interrupt and external bus pins have dual multiplexed function ality The external bus pins are configured during RESET only while serial port pins are software configurable during program execution Flag and interrupt functionality is retained concur rently on multiplexed pins In cases where pin functionality is reconfigurable the default state is shown in plain text alternate functionality is shown in italics Table I Common Mode Pins Pin Number Input Pin Number Input Name s of Pins Output Function Name s of Pins Output Function RESET 1 I Processor Reset Input PFO Mode A 1 I Mode Select Input Checked BR 1 I Bus Request Input only During RESET BG 1 O Bus Grant Output CLKIN 2 I Clock or Quartz Crystal Input BGH 1 O Bus Grant Hung Output XTAL DMS 1 O Data Memory Select Output CLKOUT 1 O Processor Clock Output PMS 1 O Program Memory Select Output SPORTO 5 1 0 Serial Port I O Pins IOMS 1 O Memory Select Output SPORT1 5 1 0 Serial Port I O Pins BMS 1 O Byte Memory Select Output IRQ1 0 Edge or Level Sensitive CMS 1
45. urrent High Gain 2 4000h R Phase Voltage DC Offset 2 0 Y Phase Voltage DC Offset 2 0 B Phase Voltage DC Offset 2 0 R Phase Current Low Gain DC Offset 2 0 Y Phase Current Low Gain DC Offset 2 0 B Phase Current Low Gain DC Offset 2 0 R Phase Current High Gain DC Offset 2 0 Y Phase Current High Gain DC Offset 2 0 B Phase Current High Gain DC Offset 2 0 E pulse Type Energy Pulse ed active el Apparent 1 1 Pulse E pulse Constant Range from 1 000 20 000 Impulse Constant 1 2 2000 pulses kWh Pulse E pulse Constant Range from 1 000 20 000 2 2000 PHASE COMPENSATION VARIABLES R Phase Coeff for High Current Range 12 0000 0000 7FFF 0000 0000 0000 R Phase Coeff for Middle Current Range 12 Do R Phase Coeff for Low Current Range 12 Do Y Phase Coeff for High Current Range 12 Do Y Phase Coeff for Middle Current Range 12 Do Y Phase Coeff for Low Current Range 12 Do B Phase Coeff for High Current Range 12 Do B Phase Coeff for Middle Current Range 12 Do B Phase Coeff for Low Current Range 12 Do The first byte to be sent for initialization is 45h followed by all the above tabled parameters in the same sequence Phase Compensation Coefficients Three sets of filter coefficients have been provided which will be automatically selected by the DSP during execution based on the maximum current Imax In the ADSST EM 3035 the Imax is fixed at 20 Amps Therefore the current ranges have be
46. y of say one milli second will be required for it to execute these 81 words The DSP will now with BDMA registers initialized read the code length also initialized in the previous process It should be noted that when the DSP reads the 20136 bytes from its port of the 1ST BYTE OF DATA DATA DO D7 reset pin low e Make PX high and clock PY low to high transition This will make BR low In effect the DSP will not read because it has granted its buses since BR is asserted e Put the first byte of the program code on the DSP bus D8 to D15 and deassert BR which is done by taking PX low and clocking a transition on PY low to high Since the DSP buses have been released it will read the byte and assert BMS The assertion of BMS will cause the flip flop to preset PR on 74LS74 itself and therefore BR is again asserted e Continue this process byte by byte for 96 bytes and give a small delay e After the delay continue the byte loading process for the next 243 bytes and give a small delay again e Continue the byte loading process for 20136 bytes e Soon after the last program byte is loaded the DSP starts execution of the code At the start of execution the DSP waits for uploading of 154 bytes of data consisting of calibration constants gain amp dc offsets E pulse constants and filter coefficients This data has to be sent to the DSP processor on the SPI port Until the DSP receives the 154 bytes the actual pro
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