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CRD49530-USB User`s Manual

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1. 4 7 4 4 1 DAO Output of 54953 2 2 4 7 4 4 2 Changing Serial Control Protocol 204 Or SPI Memory Usage 4 8 4 5 Programming the On board Serial 4 8 5 1 DS705RD3 Copyright 2008 Cirrus Logic iii CRD49530 USB User s Manual 5 2 Detailed Schematic 5 5 1 5 2 1 CS49530 USB Block 2 0004 0000 5 1 922058 qc M 5 1 INS E eas 5 2 Oe UPTO Ol T x 5 2 oap IS E 5 3 52 6 INPUY OUTOUT FINETS 5 3 5 2 7 Microphone PFEAMIDINICL 5 4 0 2 6 Power and CONMCCION 5 4 5 3 Obtaining Schematic Updates 5 5 6 1 Troubleshooting 6 1 SEIS Rab rr ne ee ee ee 6 1 6 1 2 Board not Recognized by 6 1 6 1 3 Audio is not 6 2 6 1 4 Only Stereo Audio is
2. 10 11 12 Installation Setup and Running First Application CIRRUS LOGIC CRD49530 USB User s Manual Opal Kelly FrontPanel Driver Setup m x Welcome to the Opal Kelly FrontP anel Driver Setup Wizard This wizard will quide you through the installation of the FrontPanel Driver only package We suggest you uninstall any previous versions af FrontPanel make sure that FrontPanel is not currently running It is also recommended that vou close all other applications before continuing This will make it possible to update relevant system files without having to reboot your computer Click Next to continue Figure 3 1 Front Panel Driver Setup Wizard The Opal Kelly Licensing Agreement window will appear next Click Agree to agree to the terms and continue The next window asks the user to choose components for installation By default only one component is available and is pre selected Unified USB Driver Click Next to continue The wizard will then ask the user to choose the install location Select the default location of C Program Files Opal Kelly FrontPanel and click Install This should take only few seconds Click Finish once the wizard has completed installation of the drivers The Cirrus DSP evaluation software will then prompt the user to click Finish to exit the setup wizard 3 1 2 Setting up the CS49530 USB Boards 1 2 DS705RD3 Place th
3. Plum nium in mmm Figure 5 3 SDRAM and Flash Block 514951 451 0646 0 90 50 snuio 8002 9160 6 S il 10uF 12 3 3 ANA 1 EXCML45A910H 1000pF 50V 8 SPDIF_RX3 gt 1 ourck 28 gt CSB416_LRCLK 12 51 SPDIF _RX2 2 Rxp2 OSCLK gt CS8416 SCLK 2 5 t8 SPDIF _RX1 5 exp SDOUT 58416_5000 121 SPDIF gt 4 Irxpo XTAL_OUT 121 5 RMCK CS8416_MCLK 121 6 Cis 1000 7 a 22 feeder DGND 22 22 1 ils ME p t 3 8 BRD RST 9 658416 INT 8 10 Inxp4 GPO1 6542448 51 exps 02 6 02 12 SDA CDOUT lt gt SCP_MISO SDA 2 5 8 2 81 gt H 13 SCL CCLK SCP_CLK 12 5 81 81 CS8416 CS 14 ADO CS AD1 CDIN SCP_MOSI 2 5 8 CS8416 CZZ E SOFTWARE_MODE 10K GND 3 3VD SPI ADDR 0x20 12 ADDR 0010 AD2 AD1 ADO 0 CRD49500 I2C ADDR 0x2A Figure 5 4 S PDIF Receiver 514951 451 0646 quso sqd 1 snuio 8002 2160 01 4 c lt c1
4. Serial Control Interface PC Reset Signals Board Control Signals C H D 4953 0 USB Port 2 1 XEM3001 4 Audio Data Future Development Figure 2 1 CRD49530 USB System Block Diagram This document will concentrate on the features and basic operation of the CRD49530 board Detailed information regarding the operation and programming of the CS4953xx DSP is covered by the CS4953xx Data Sheet CS4953xx Hardware User s Manual and application note AN288 see Other Useful Information on page 1 9 for more details The CRD49530 is a convenient and easy to operate evaluation platform It has been designed to demonstrate the majority of the CS4953xx functions a small 6 x 5 5 base board These features include e PC control of the CS4953xx using the DSP Composer graphical user interface Serial control of audio devices on CRD49530 via 12 9 or SPI protocols Digital audio input of PCM or compressed data via optical or coaxial S PDIF e 6 channel analog audio input via the CS42448 audio codec e 8 channel analog output through the CS42448 audio codec Digital audio output of PCM data via optical S PDIF Multi channel digital audio input via the USB Master feature not currently supported e Separate input and output clocking domains to allow 1FS to 2FS audio processing on the CS4953xx e DSP Memory expansion through external 64 Mbit SDRAM e Fast boot host controlled master b
5. 6 2 6 14 Revision EHSIODV uae ERA cus seen ee ae dure 6 2 Figures Figure 1 1 CRD49530 Kit 1 1 Figure 1 2 OHD49530 USB Block Diagram nce aeu rino hoa beset 1 2 6 07 1 6 Figure T4 S PDIF CIO CIAO PER 1 7 Foue mes 1 8 Figure 2 1 CRD49530 USB System Block 2 1 Figure 2 2 CRD49530 Top View 2 2 Figure 3 1 Front Panel Driver Setup nnne 3 2 Figure 3 2 Board Setup Diagram ERIT LIU 3 3 Figure 3 3 ound New Hardware 3 4 Figure 3 4 Found New Hardware Wizard 3 4 Figure 3 5 Found New Hardware Wizard with Automatic Installation Option Window 3 5 Figure 3 6 Hardware Installation WindOw 2 3 5 Figure 4 1 PCM Pass through Example Application 2 nnn 4 2 Figure 4 2 CRD49530 System Properties 4 3 Figure 4 3 CRD49530 DAO Channel nennen nnn nnne 4 3 Figure 4 4 CRD49530 Audio In nnns 4 4 Figure 4 5 CRD49530 S PDIF Rx Properties 4 4 Figure 4 6 CRD49530 Analog Properties 4 5 Figure 4 7
6. 4 e ow E b 7 lt f 4 M b 4 Y 4 ke dr Figure 2 2 CRD49530 Top View CS4953xx DSP U5 CS42448 Audio Codec U4 CS8416 S PDIF Receiver U3 4 Mbit Serial Flash U11 64 Mbit SDRAM 166 MHz U7 1 8 Microphone Input Jack Optical S PDIF Input Jacks gt DS705RD3 Copyright 2008 Cirrus Logic 2 2 Introducing the CRD49530 USB Customer Reference Kit CRD49530 USB User s Manual 2 3 H lt VO 2ZEF Coaxial S PDIF Input Jacks Analog Inputs 2 VRMS Max USB Connector on CRD USB Master Alternate 12V Jumper J3 3 3V Switching Regulator 1 5A U8 3 3V Selection Header Regulator External J17 1 8V Selection Header Regulator External J18 1 8V Linear Regulator 1A U10 15V Selection Header Regulator External 919 5V Linear Regulator 1A U9 Analog Audio Outputs DC Power Input Jack 9VDc to 4 12VDC Optical S PDIF Output Jack On board External Digital Audio Mux U1 amp U2 Power Indicator LEDs 99 Copyright 2008 Cirrus Logic DS705RD3 Introducing the CRD49530 USB Customer Reference Kit CRD49530 USB User s Manual DS705RD3 Copyright 2008 Cirrus Logic 2 4 Installation Setup and Running First Application CRD49530 USB User s Manual Chapter 3 Installation and Setup for Running Application 3 1 Installation Setup and Running First A
7. 514951 451 0646 Obtaining Schematic Updates CRD49530 USB User s Manual 99 05705803 Copyright 2008 Cirrus Logic 5 14 Troubleshooting Guide CRD49530 USB User s Manual Chapter 6 Troubleshooting 6 1 Troubleshooting Guide This section provides solutions to problems that users might experience when using the CRD49530 USB 6 1 1 Power LEDs Problem Power LEDs are not illuminated Possible cause DC power supply is not connected to CRD49530 USB Solution Ensure the DC wall supply is connected to the DC power input jack J25 and the supply is plugged into a wall outlet Possible cause Power selection headers J17 J18 J19 are set incorrectly Solution If you are using the DC wall supply provided with the CRD49530 USB all jumpers should be in the REG position Possible cause Jumper settings when using an external power supply are set incorrectly Solution If you are using an external power supply for any of the system voltages 5V 3 3V 1 8V ensure that the jumper for that voltage has been removed and power is applied to the center pin of the appropriate header 6 1 2 Board not Recognized by PC Problem CRD49530 USB is not Recognized by PC Possible cause DC power supply is not connected to CRD49530 Solution The CRD49530 is not a USB powered device Make sure the DC wall supply is connected to the DC power input jack J25 and
8. lt GOXOA peti tet 2 be 2220000o0ooooo mam lt lt lt lt gt lt lt lt lt lt lt lt lt lt gt AOUT4 gt AOUT3 gt 0072 SPI ADDR 0 9 I2C ADDR 1001 O AD1 ADO 0 CRD49500 12 ADDR 0x92 Figure 5 5 CS42448 CODEC gt AOUTI gt AOUT5 61 61 61 61 61 AIN6 61 AIN6 61 AIN54 61 lt PREAMP 7 AIN4 6 AIN4 6 AIN3 6 AIN3 61 61 C16 0 tuF ELEC 4 7uF R38 5 52 5VA rae MMUN2111LT1G E a MUTE 61 514951 451 0646 quso sqd 8 1 snuio 8002 9160 8 5 LL S INPUT FILTERS OAM 15 i 51 16 C51 R5 C06 2 55K 2700pF mD 1 4 ELEC D gt BILAN NL DE C 15 54 RIB 06 Siis 2700F DOAN 5 4055 TEC AIF AINA RIDA AA Zi es 8 16 57 R20 2 06 2 55K 2700pF L LOM 51 058 ELEC CO ANS 15 16V ls R22 COG 255K 2700 ANS 15 223 R24 COG 2 55 2700pF 4 ELEC AING 5 04 247 us un 5 AQUTI 2 us un
9. 5 2 4 e us un 5 AOUT4 7 1 AIN5 comes from the PREAMP 58 2 08 9 gt v 5 MUTE 56 MUTE OUTPUT FILTERS 9 28C3326 A TAL F T AQUT2 28C3326 A TSL F T AOUTS 28C3326 A TAL F T 6 28C3326 A TAL F T 8 8 8 0075 18 15 5 2SC3326 A TSL F T 181 15 0076 gt 5 AQUT7 5 um At VAVA t RSI 770 f No 156 af cio 2s unm n At 10K 7700 58 D 3 M 28C3326 A TSLF T f 0077 8 5 M 28C3326 A TSLF T f 0078 B 15 gt Figure 5 6 Input Output Filters 5 MUTE gt un J RAM R53 EO k 2700F 55 O 02 28C3326 A TSL F T TEGDI 514951 451 0646 quso sqd 91607 8002 1 cS 5VA 1 INPUT R105 1X 105K R106 5 90K OUTPUT 1 8 3 5mm stereo 22 yeti COE 2 15pF TO ADC v 8104 2 21K 45 3 C71 MN Bes AN 16 8100 124 Rass SJ 3523 SMT Z cene 5 L3 2 1 MIC PREAMP 51 69 C79 2700pF 5VA cz Sine
10. SCP MOSI pulled low by pull down 61 61 61 gt 00 8 6 gt 0077 61 gt AOUT6 6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 81 05 DAO0 HSO gt 2 8 DSP SCLK 2 8 DSP_LRCK lt CODEC FILT ADC les lee ELEC 0 0 0 tuF 8 CS42448 INT 2 4 81 SCP_CLK 12 4 81 5 MISO SDA lt gt 3 3VD deu Um Ja ues s zs eese E ELEC ELEC 10uF O 1uF o otuF O tur o otuFo tur o otuF 16V 2552222040 2222 85 lt lt lt lt lt lt lt lt 58 5454 22 2222 3542448 CS gt 1 ADO CS 5251 AIN2 18 lt AIN2 SCP_MOSI gt 5 AD1 CDIN AIN2 bag lt AIN2 41 CS42448 RST gt X RST AINI 5 15 5 VLC AIN1 44 lt 2 4 CS8416_LRCLK gt amp ADC LRCK VA 7 0 P VQ 42 2 CS42448 CQZ 51 VLS AQUTB Hir on SPDIF RX page 2 41 58416 SCLK gt 16 ADC SCLK AOUTB 10 2 5 17 MCLK 0077 2 542448 SDOUT3 lt 12 ADC 500 75 CS42448 CQZ D AOUT7 H7 35 t2 542448 SDOUT2 __ 838 13 ADC SDOUT2 AOUT6 55 10K t2 CS42448 SDOUT lt 14 ADC 500011 AOUT6 35 2 81 DSP DAO3 XMTA gt 15 DAC SDINA MUTEC 32 12 81 DSP DAO2 HS2 gt 18 SDIN3 AOUT5 55 2 81 DSP DAO1 HS DAC SDIN2 AOUT5 gt gt
11. SD_D10 EXT_D10 SD_D9 EXT_D9 SD DB EXT DB EXT CS EXT CS2 EXT WE EXT OE 50 DQMO 50 DQM 50 CLKOUT SD CLKIN SD CLKEN SD CS SD RAS SD CAS SD WE DAO_MCLK DAO1_LRCLK DAOT_SCLK DAO1 00 50 DAOT Di HS1 DAO D2 HS2 0 01_03 DAO2 LRLCK DAO2 SCLK DAO2 D0 HS3 DAO2 D1 HS4 DAO2 D2 EE CS DAO2 D3 XMTB GNDD1 GNDD2 GNDDS GNDD4 GNDDS GNDD6 GNDD7 GNDD8 GNDIO1 GNDIO2 GNDIO3S GNDIO4 GNDIOS GNDIO6 GNDIO7 GNDIO8 DEFAULT SPI amp I2C ADDR 0x80 NOPOP R41 5 90K 1 C195 2 2uF C196 1 COG C197 47pF COG R34 0 OHM R41 5 e 1x C195 NOPOP C196 NOPOP C197 NOPOP SPI MODE SEL 8 SPI 54 3 12 5 81 DSP_DAOO HSO lt RELA 10 2 5 8 DSP DAOI HS lt gt R K 3 3VD 12 5 81 DSP_DAO2 HS2 lt gt 10K A 29 i 88 RNI2 C 3 6 56 87 RNIZ D 4 VVN L2 B8 131 85 RNII A 56 B B4 RNII B 2 7 56 77 4 56 550 Sui N 74 RNI3 B 2 ANA 56 L 5 26 L3 39 696 560 131 RNS 2 06 19 80 13 58 RN8 D 4 56 SP 59 56 50 9 5 81 RN9 B 2 7 56 3 CENE ES 64 RN10 D 4 NNN 5 56 TS SD A5 i 68 RN10 B 2 7 56 3 70 RNIO A 1 VV N56 151 7i RNIS
12. on page 4 5 and the audio input source multiplexer U1 U2 is used to select on board audio sources Figure 1 4 illustrates this clocking configuration MCLK recovered from the incoming S PDIF stream must be MCLK for the system and the codec masters the input clocks MUXED SCLK MUXED LRCLK of the CS4953xx In this configuration the internal multiplexer of the CS8416 routes the recovered MCLK to MUXED MCLK 1 7 Copyright 2008 Cirrus Logic DS705RD3 CRD49530 USB System Description CRD49530 USB User s Manual The CS4953xx always masters its output clocks DSP_SCLK DSP_LRCLK Table 1 2 S PDIF Clocking Clock Name Clock Master Source Clock Driver Clock Frequency 256 S PDIF Fs MUXED MCLK CS8416 CS8416 e g 12 288 MHz for 48 kHz MUXED SCLK MUXED MCLK CS8416 64 Input Fs default MUXED_LRCLK MUXED MCLK CS8416 Input Fs DSP SCLK MUXED MCLK CS4953xx 64 Output Fs default DSP LRCLK MUXED MCLK CS4953xx 1 Input Fs default Note MUXED MCLK is the clock signal that is driven by the CS8416 s RMCK pin The CS8416 provides the recovered clock from the S PDIF input unless it loses signal lock in which case the CS8416 passes the DSP clock XTAL OUT that it receives on the pin 1 3 10 3 Clock and Data Flow for USB Data Delivery This feature is used by engineering development and debugging purposes MUXED DAI 4 0 HDMI
13. 012 78 2 2uF MC33078DG ELEC ey 1 100uF 10V 4 Condenser MIC Reference Panasonic 61 51 5 dB Max 7 mVpp ADC 0 53 Va 2 65 Vpp Figure 5 7 MIC 514951 451 0646 0 90 50 418VD 3 3VD 3 3VD 5VD INPUT CONNECTORS Dual RCA for dual footprint R72 R73 R74 R75 576 124 243 RCJ 0222 RED VERT 1K RCJ 022 VERT LEFT RIGHT ANg OUTPUT CONNECTORS RED GREEN YELLOW v gt gt pi 02 Y 04 Y NI 2 2 iz RCJ T DEUM VERT ee RCJ 023 NHT VERT RCJ 022 RED VERT 5 Z 6 AIN3 2 Q10 t61 2SC3326 A TSL F T a SBL RCJ 023 WHT VERT CENTER RCJ 022 RED VERT RoJ o22 RED VERT RCJ 023 WHT VERT AINS t6 VIDEO BOARD USB BOARD CONNECTOR fei elTe 3 3VD E A d 0 Ohm placeholders for CENTER series term of USB tol ke VID_BRD_1 8VD 3 41 R92 0 So 64 RB4 J lt gt 12 51 DSP RESET
14. Figure 1 2 The sections that follow provide a detailed description of each block 6x Eg EM 8x In Analog 542448 Out MIC In gt band SS SS aed 4 SPDIFOUT _ S PDIF Out Clocks Data 1 12 CS4953xx DSP RESET Memory Bus E FLASH 3 SPI Master _ SPIFLASH 5 4x SPDIF CS841 6 lt SPDIF SPDIF IN BRD RESET I Figure 1 2 CRD49530 USB Block Diagram DS705RD3 Copyright 2008 Cirrus Logic 1 2 CRD49530 USB System Description CRD49530 USB User s Manual 1 3 1 Audio Inputs 1 3 1 1 Analog Line level Inputs Connector Type RCA Female e Absolute Maximum Signal Level 6 5V e Absolute Minimum Signal Level GND 0 7V Full Scale Amplitude 2VRMS e Reference Designators J12 J26 J30 or AIN1 AING 1 3 1 2 Optical Digital Inputs Connector Type Fiber Optic RX for Digital Audio JIS F05 JIS C5974 1993 F05 e Reference Designators J1 J2 or SPDI
15. IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITI CAL APPLICATIONS CUSTOMER AGREES BY SUCH USE TO FULLY INDEMNIFY CIRRUS ITS OFFICERS DIRECTORS EMPLOYEES DISTRIB UTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY INCLUDING ATTORNEYS FEES AND COSTS THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES Cirrus Logic Cirrus the Cirrus Logic logo designs and DSP Composer are trademarks of Cirrus Logic Inc All other brand and product names in this doc ument may be trademarks or service marks of their respective owners Microsoft and Windows XP are registered trademarks of Microsoft Corporation SPI is a trademarks of Motorola Inc is a registered trademark of Philips Semiconductor Corp HDMI is a trademark or registered trademark of HDMI Licensing LLC in the United States and or other countries Dolby Digital is a registered trademark of Dolby Laboratories Licensing Corporation DS705RD3 Copyright 2008 Cirrus Logic 1 CRD49530 USB User s Manual Contents gi jn 24544522422 ee eee ee eee V 1 1 CRD49530 USB Kit 1 1 1 2 HeguiremehIS 1 1 1 2 1 PC eU EMI RPM M IM DOR UE 1 1 1
16. SNNN EXCML45A910H 127 C172 i 192 pur C174 pt es C199 ELEC 16V C176 put eus 0 1uF O tuF NOPOP R34 OPULATED 195 pur C182 pur 33 100 ELEC 16 SCP1 CLK 5 1 MOSI SCP1 MISO SDA CS SCP1 IR SCP1 BSY A0 A8 PCP_A1 A9 A2 SCP2_MOSI AS SCP2_MISO PCPDS SCP2CK PCP_RD R W PCP SCP2 CS PCP SCP2 IRQ ADO DO PCP_AD1 D1 PCP AD2 D2 AD3 D3 PCP AD4 D4 AD5 D5 PCP AD6 D6 AD7 D7 RESET TEST DBDA DBCK UART_CLK UART_TXD UART_RXD GPIO28 DDAC XMTA_IN XMTB_IN 143 6 027 GPIO26 DAI2LRCK PREQ DAI2_SCLK DAI2 DATA DSD5 LRCK DSD4 SCK DSDCK DAN DO DSDO DAN 01 0501 DAI_D2 DSD2 03 0503 XTI XTO XTAL OUT PLL REF RES NC GNDA VDDA 3 3V VDD1 VDD2 VDD3 VDD4 VDD5 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIOS VDDIO6 VDDIO7 VDDIOB EXT A19 EXT A18 EXT 17 EXT A16 EXT A15 50 A14 50 BAO EXT 15 SD_A10 EXT_A10 SD_A12 EXT_A12 50 SD 9 A9 SD AB EXT SD 7 A7 SD A6 EXT A6 50 A5 SD 4 A4 50 A3 EXT A3 SD A2 EXT A2 SD AT EXT A1 50 A0 EXT 50 07 07 SD D6 EXT 06 50 D5 EXT 05 SD D4 EXT 04
17. domains operate at different frequencies e g 48 kHz input 96 kHz output Systems utilizing 125 delivery of S PDIF input ADC input or other digital audio input use isochronous delivery The requirements are slightly more complicated for systems using bursty delivery on the input side of the DSP but the CRD49530 is designed to emulate isochronous systems The CRD49530 can operate in three different clocking modes Each of these modes is explained in the following sections 1 3 10 1 Clock and Data Flow for ADC Input MUXED DAI 3 0 MUXED LRCLK MUXED SCLK C 58416 S PDIF Input MUXED MCLK l 5 SDOUT DAI 4 DSP SCLK 4 SDIN DSP LRCLK CS4953xx 542448 LL zo Figure 1 3 ADC Clocking The ADC clocking architecture is used when the ADCs are used as the only audio input i e S PDIF is disabled as described in USB 125 Audio Input on page 4 5 and the audio input source multiplexer U1 U2 is used to select on board audio sources Figure 1 3 illustrates this clocking configuration XTAL OUT from the CS4953xx is MCLK for the system and the codec masters the input clocks SCLK MUXED LRCLK of the 54953 The system routing of the clocks was simplified by using the CS8416 to drive MCLK to the system but the internal clock multiplexer of the CS8416 is force
18. lt RIN WO So emi i im jose 217 121 DSP CS lt 5 MAN gt HDMI_LRCLK VID_BRD_5VD aki T A RCJ 023 WHT VERT CP CLK lt 4 139 gt HDMI_SDATA1 121 RCJ 0222 VERT 12 4 51 SCP 50 50 gt 15 VID BRD 12V AOUTS 3 5VD 2 45 DSPLBSY HDMI_SCLK e 4 2 DAO2 D3 XMTB gt gt HDMI_SDATA4 121 T t2 41 HDMI_SPIDF lt 2350 gt 21 0 C 0 47uH 121 DSP_DBCK lt R93 NAA 28e lt J2 2 DSP_DBDA lt gt 350 lt gt DSP 5 12 51 e 2 SPI MODE SEL 35 DSP_DAI4 121 NC J31 5 T5898 lt DSP DAQO HSO 12 51 ES 51 542448 INT 19 DSP_LRCK 2 51 E 058416 gt tio 044 lt 05 DAOI HS 12 51 RCJ 022 RED VERT RCJ 023 WHT VERT gt vec 2 0 0 copic 4 558416 CS 430 lt 105 0 02 52 12 51 L7 1 59 lt DSP_DA03 XMTA 2 5 8 38075 ABUTI 2 VID BRD 3 3VD L 771 7 our G44 2 4 pE SPDIF _ 4 75 d 3 5 3 RIGHT LEFT NC 3 3VD TORX147PL F T m Even Odd swap of USB DIO 93 to J1 L1 A 0 47uH USB J35 1 J11 2 USB J5 2 11 1 J24 lt J32 21 RCJ 023 WHT VERT smi sei NC 60 2 cs 0 0 gt SPDIF _RX3 4 igi TPB 12 5 81 DSP DAO3 XMTA 3 53 2 vec 4 5 43 30 Ovce R2 E O GH 5 7
19. 1 5 3 Audio Codec Information e CS42448 Data Sheet 2542448 Errata 1 5 4 S PDIF Receiver Information The following information is located on the www cirrus com web site e 58416 Data Sheet e 58416 Errata 1 9 Copyright 2008 Cirrus Logic DS705RD3 NN Information Shipped with the Evaluation Kit CRD49530 USB User s Manual 1 5 5 DSP Software Utility Information DSP Composer User s Manual The documents listed above are updated periodically and may be more up to date than the information in this document Check the Cirrus Logic web site for the latest updates 661 1 The 56 symbol is used throughout this manual to indicate the end of the text flow in a chapter DS705RD3 Copyright 2008 Cirrus Logic Introducing the CRD49530 USB Customer Reference Kit CRD49530 USB User s Manual Chapter 2 Introduction to CRD49530 USB Kit 2 1 Introducing the CRD49530 USB Customer Reference Kit The CRD49530 USB kit is composed of the CRD49530 customer reference design and the CRD USB Master USB Control board The CRD49530 provides a practical platform for emulating a typical multi channel audio system application The CRD USB Master is a USB control board used to interface the host PC to the CRD49530 and convert GUI commands into the serial control protocol required for configuring the CS4953xx CS42448 and CS8416 audio ICs Figure 2 1 shows the relationship between the CRD49530 and the CRD USB Master
20. 2 2 Software Requirements ceccceeccccccseeceecesseeececeeeeenscceeeeensaseeeececeseeeeescceseesseaeeeeeses 1 2 1 2 3 Support Hardware 1 2 1 2 4 Cabling Hequlrerrielils cien cvi vk kPa eins nb aud va 1 2 1 3 CRD49530 USB System Description 1 2 T 1 3 Vie M 1 3 1 A 1 4 1 3 4 On Board Voltage Selection Headers 1 4 1 3 5 Audio Input Source 1 4 1 3 6 CS4959XX od DOP MNT 1 4 19 7 ec 1 5 1 3 8 542448 Audio 1 5 Hii T 1 5 dojes ieedi c 1 6 14 Other Useful Information 252 usc dt ES 1 9 LU S RI NETTEN m 1 9 1 5 Information Shipped with the Evaluation 1 9 URN WTO mmm 1 9 1 5 2 Board a 1 9 1 5 9 Audi
21. 3 5 Copyright 2008 Cirrus Logic DS705RD3 3 6 Installation Setup and Running First Application CRD49530 USB User s Manual 4 3 1 4 Running a Stereo PCM Application on CRD49530 USB 1 2 3 4 Launch DSP composer Start gt Program gt Cirrus DSP In DSP Composer go to File gt Open and open C CirrusDSP CS4953X projects ocm_1fs cpa Press the GO button Insert PCM material into the DVD player e g music CD If a DVD is being used as the audio source make sure that the DVD Player or other digital audio source is configured to output PCM data Press Play on the DVD player or other digital audio source You should now hear audio from the speakers 3 1 5 Downloading Other Applications Separate project files cpa are provided for other applications such as Dolby Digital In order to evaluate these please contact your local FAE to ensure that the necessary licensing agreements have been completed 99 Copyright 2008 Cirrus Logic DS705RD3 Introduction CRD49530 USB User s Manual Chapter 4 Programming the CRD49530 USB Board 4 1 Introduction With the exception of the power selection jumpers the CRD49530 is configured exclusively through software The DSP Composer software is a graphical user interface GUI that is used to program the CS4953xx DSP and to configure the CRD49530 This section provides basic instruction for using the GUI to control the CRD49530 but detaile
22. 5 8 1075 116 eno 412V VID BRD 12V a ou ott C22 p 01uF 1 5 SPDIF Rx1 4 as TP12 0 tuF Qi 516 i NC NC HDR2X1 TOTXI47PL F T GND TEST POINTS TORX147PL F T NO POP Note R2 C4 close to U3 Note R3 C3 close to U3 MT7 SPCR STANDOFF 4 40 THR 875L AL NPb yu MT2 5VD 5VA FDLOCAL1 FDLOCAL1 FDLOCAL1 A MT5 L5 FD10 012 91 1 12V IAW 2 4 3 3VD A EXCML45A810H c FDLOCAL FDLOCAL1 FDLOCAL1 C28 FDI FD2 FD3 FD4 1027 x 9 69 4 10 To tur 16V 12V FDLOCAL1 FDLOCAL FDLOCAL FDLOCALI 3 3 0 5VD 1 8VD R76 3 3 REG 100 a lt J19 ano eye 5v REG Auxiliary H W amp Docs 22 s gt BV REG HDR3X1 5 2 4 co 3 R79 2 C30 4C35 B SHUNT 2P 15 29 1025 100 SR ELEC 2 526 SCREW PHILIPS 4 40THR PH 5 1 Our lt E 4 PH 5 16 LPMS 440 0031 PH 10V R78 our NELE ASSY DWG 603 00238 01 3 124 HE iov PCB DWG 240 00238 Z1 1 H DWG 600 00238 01 zu 5 R94 4 C29 ELEC 25 15K X7R C65 150uF 5 6800pF 150uF 16V zu R80 VID_BRD_5VD Q tuF 16V E a T 22087 VID BRD 1 8VD DC Input from 9V to 12V 91 2200pF E VID BRD 3 3 VD d 1 cc T 17 L8 EXCML45A910H EXCML45A910H 1 1 Figure 5 8 Connectors and Power
23. 6 Set to Master when using S PDIF input SPDIF RX3 and NONE Choosing NONE forces the CS8416 to pass the DSP clock that comes in on the pin to MUXED MCLK Use this setting when using the ADC e Analog Only Enable microphone input 4 3 3 USB 12 Audio Input This feature is used for debugging and development purposes via the usb play utility 4 5 Copyright 2008 Cirrus Logic DS705RD3 Changing Audio Input Source CIRRUS LOGIC CRD49530 USB User s Manual 4 3 4 DAI Input Each available audio source for the board is shown as a block connected to the DAI port of the CS4953xx as illustrated in Figure 4 7 Right clicking any of the sources and selecting Device Properties produces the DAI Properties dialog Schematic DAI Properties SCLE polarity Rising edge LACLE polarity Channel low Channel mode SPDIF on pin 4 Temperature grade Commercial 0 70 Ref clock freq 24 575 MHz Figure 4 7 CRD49530 DAI Input Properties This dialog allows the user to set the following parameters for the CS4953xx SCLK polarity Rising edge Falling edge e LRCLK polarity Channel 0 low Channel 0 high e Channel Mode SPDIF on pin 4 SPDIF on pin 0 Temperature Grade CRD49530s are populated with commercial grade chips by default Ref Clock Set to the frequency of the crystal driving the CS49353xx Y1 This is the reference clock is used
24. AAA DSP XTI Y1 BAAN A atj 24 576MHZ C215 _ 06 33pF DSP XTO 2 2 2 2 4 5 81 5 81 5 gt MUXED_MCLK 12 51 3 3VD R98 3 32K lt DSP CS DH DSP_IRQ lt lt DSP_BSY DH C3 scP lt 5 50 6 lt 156 MOSI 3 3VD A R97 3 32K R45 R96 3 3VD 3 3VD 3 3VD A A 2 81 2 81 2 8 2 4 5 8 SDA 2 4 5 8 2 4 5 8 u5 CS495313 CQ4Z A SCP_CLK CD gt 81 SCP_MISO SDA 81 81 81 3 SPI FLASH 051 gt 3 SPI FLASH MISO lt 3 SPI FLASH 81 DSP_DBCK 4 8 SPIDF DSP IRQ SCP_MOSI lt gt 37 DSP CS ae DSP_BSY lt 3 3VD A 3 3V0 R25 AA A22K R26 05 8 RESET 8 DSP DBDA lt 8 DSP_DAI4 MUXED LRCLK 138 MUXED SCLK 157 MUXED DAIO 135 MUXED 134 MUXED DAI2 132 Al 131 124 125 NOTES UNLESS OTHERWISE SPECIFIED 1 ALL RESISTOR VALUES ARE IN OHMS PLL CONFIGURATIONS 2 CS49500 L4 4 3 549530 L POPULATED L1 NOPOP L10 0 P 1 8VD 3 3VD 123 141 XTAL_OUT Yaa AA Ek 282 L10 91 45 910
25. C 3 6 56 72 RNIS D 4 B6 29 RN2 B 2 7 56 30 RN2 A 1 56 lt 50 07 131 31 RN3 D 4 5 56 131 32 RN3 C 3 AVA 56 50 05 131 34 RN3 B 56 50 04 151 ENNE B 37 RN4 D 4 56 i 38 RNA B 2 NNN 56 SS 50 01 131 40 56 2 5 Sp pts Bl 21 RNS D 4 326 550014 51 42 3 6 56 550 013 43 RNS B 26 50012 45 RN5 1 56 M i IS ES Bi 48 RN6 C 3 6 56 E 49 RN6 B 2 NNN 56 SS 50 09 BI 30 RN2 1 AAA 56 131 38 RNA C 3 6 56 MEE 89 RNI2 B 2 NNN 256 I EINE 13 25 3 6 56 50 000 131 50 RN6 A 1 AAN 56 SD DOMI 31 E 30 CLKOUT DSP 13 SD CLKIN 3 53 RN7 D 4 56 81 RNH D 4 56 30 131 80 1 56 S SIRAS 131 79 RNI4 B 56 GI 5 78 4 3 NNN 56 ES SD WE 31 8 R27 MUXED_MCLK 2 5 22 09 LRCK 5 8 19 32 56 gt DSP_SCLK 5 8 ig gt DSP DAO0 HsO0 2 5 8 17 gt DSP_DAO1 HS1 2 5 8 E M gt 02 52 25 81 gt DSP DAO3 XMTA 5 81 L4 2 gt DA02 D3 XMTB 181 Figure 5 2 CS49953xx DSP on CRD49530 USB Board 514951 451 0646 0 90 50 91607 8002 1 8 4 HLT 1 SPI FLASH POPULATED BOTH REPRESENTED M 3 ID SORA cehi und i am ls PEN Pm Ed ung nium 4
26. CRD49530 USB Customer Reference Design CRD49530 USB User s Manual Pralimi Product Int T This document contains information for a new product Cirrus Logic reserves the right to modify this product without notice o Copyright 2008 Cirrus Logic Inc SEP 2008 CIRRUS LOGIC E http www cirrus com CRD49530 USB User s Manual Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative To find the one nearest to you go to www cirrus com IMPORTANT NOTICE Preliminary product information describes products that are in production but for which full characterization data is not yet available Cirrus Logic Inc and its subsidiaries Cirrus believe that the information contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS IS without warranty of any kind express or implied Customers are advised to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty indemnification and limitation of liability No responsibility is assumed by Cirrus for the use of this information including use of th
27. CRD49530 DAI Input Properties 2 4 6 Figure 4 8 CRD49530 Audio Out Properties 4 7 Figure 4 9 CRD49530 Digital Audio Output Properties nnn 4 7 iV Copyright 2008 Cirrus Logic DS705RD3 CRD49530 USB User s Manual Figure 4 10 CRD49530 Comm Mode Memory Usage 2 4 8 Figure 5 1 CRD49530 USB Block Diagram nn nhan nnn nara 5 6 Figure 5 2 549953 DSP on CRD49530 USB Board 5 7 Figure 5 3 SDRAM and Flash 5 8 Figure 5 4 AelgBMicu g c 5 9 PIQUE 979515042540 CODES m HQ 5 10 Figure 5 6 Input Output Filters 5 11 Figure 5 74 ues m 5 12 Figure 5 8 Connectors POWer Ec iu 5 13 Tables Table 1 1 ADC nnne nennen nnne nnn 1 7 Hio eer 1 8 HDMI CIOCKINO m 1 9 DS705RD3 Copyright 2008 Cirrus Logic V CRD49530 USB Kit Contents CIRRUS LOGIC CRD49530 USB User s Manual Chapter 1 Kit Contents and Requirements 1 1 CRD49530 USB Kit
28. Contents Each CRD49530 USB kit comes with the following e CRD49530 Development Board Power Supply 9V 1 67A 100V 240V with AC Power Cord e CRD USB Master USB Digital Card USB Cable Document Card explaining how to get the latest board software Figure 1 1 CRD49530 Kit Contents 1 2 Requirements 1 2 1 PC Requirements Microsoft Windows XP Operating System e USB 2 0 Support DS705RD3 Copyright 2008 Cirrus Logic 1 1 CRD49530 USB System Description CRD49530 USB User s Manual 1 2 2 Software Requirements e Cirrus Evaluation Software Package available from your local Cirrus Logic representative 1 2 3 Support Hardware Requirements Digital or Analog Audio Source e g DVD player PC with a digital audio card device e Amplified Speakers for audio playback e g powered PC speakers AVR amp speakers 1 2 4 Cabling Requirements Digital Audio Inputs S PDIF Optical Cables RCA Audio cables Connect to digital audio card audio analyzer or DVD player Digital Audio Output S PDIF Optical Cables Connect to digital audio card audio analyzer or AVR Analog Audio Inputs RCA Audio Cables Connect CRD49530 line level inputs to analog audio source e Analog Audio Outputs RCA Audio Cables Connect CRD49530 line level outputs to powered speakers 1 3 CRD49530 USB System Description A detailed block diagram of the CRD49530 USB Customer Reference Design is shown below in
29. D3 0 90 50 21601 8002 1 ov DSP Composer CS4953X 115 File Edit View Mode Tools Windows Help S e G FS Q y Audio In Audio Out System block H D Decoders 1 Matrix decoders DSP 4 Matrix decoders DSP B Post processors H Graphic Elements amp Blocks Sf Yefell Passthru Passthru e cum cum cum cum cum cum cum cum cwm Page 1 4 User Devices Elements Flyoffs Compile Results 4 Find Results Debug edit Audio Qut Figure 4 1 PCM Pass through Example Application uoneunBijuo pue olseg 5 495 gSri 0886r ado Basic Application Download and System Configuration PCM Pass through CRD49530 USB User s Manual CIRRUS LOGIC 4 2 1 System Block In DSP Composer when you drag the System block onto the work space a pop up menu is displayed as illustrated in Figure 4 2 This menu offers the option of selecting the Target chip that you need to evaluate the Firmware version and the PCM input mode from the pull down menu System System Properties Target chip Firmware version 02 input made 2 0 LAA Figure 4 2 CRD49530 System Properties 4 2 2 Channel Remap of CS4953xx The audio output channels of the CRD49530 can be mapped by double clicking on the Sys
30. F RX0 SPDIF RX1 1 3 1 3 Coaxial Digital Inputs Connector Type RCA Female e Maximum Signal Level 3 3V e Minimum Signal Level GND 0 7V e Reference Designators J31 J32 or SPDIF RX2 SPDIF RX3 1 3 1 4 Microphone Input e Absolute Maximum Signal Level 5V e Absolute Minimum Signal Level GND 0 7V Full Scale Amplitude 7mVp p e Reference Designator J5 The microphone preamplifier shares the AIN5 ADC with the AIN5 RCA jack Only one analog source can be sampled at any given time When the microphone input is selected the AIN5 audio jack is ignored The default configuration enables the AIN5 audio jack 1 3 2 Audio Outputs 1 3 2 1 Analog Line level Outputs Connector Type RCA Female e Full Scale Amplitude 1 21 5 e Reference Designators J33 J40 or AOUT1 AOUT8 1 3 2 2 Optical Digital Output e Connector Type Fiber Optic TX for Digital Audio JIS F05 JIS C5974 1993 F05 e Reference Designator J24 or SPDIF TX e The S PDIF output uses the same data line as AOUT7 8 When the digital output has been enabled and you have speakers connected to AOUT7 and AOUTS white noise will be heard This could damage the speakers 1 3 Copyright 2008 Cirrus Logic DS705RD3 CRD49530 USB System Description CRD49530 USB User s Manual 1 3 2 3 DC Power Input e Voltage Range 9 TO 12VDC Minimum Power 8W supply Connector Type 2mm Female positive center pin e Reference Desi
31. MUXED LRCLK SOURCE MUXED SCLK MUXED MCLK lt 4 e gt DSP SCLK gt a D DAO DSP LRCLK gt CS4953xx 542448 42 22 Figure 1 5 HDMI Clocking When the audio input source multiplexer U1 U2 is used to select HDMI clocks and data the HDMI source masters the system MCLK and the input clocks MUXED SCLK MUXED LRCLK of the CS4953xx DS705RD3 Copyright 2008 Cirrus Logic 1 8 Other Useful Information CRD49530 USB User s Manual The CS4953xx always masters its output clocks DSP_SCLK DSP_LRCLK Table 1 3 HDMI Clocking Clock Name Clock Master Source Clock Driver Clock Frequency 256 S PDIF Fs MUXED MCLK HDMI Source e g 12 288 MHz for 48 kHz MUXED SCLK MUXED MCLK HDMI Source 64 Input Fs default MUXED LRCLK MUXED MCLK HDMI Source Input Fs DSP SCLK MUXED MCLK CS4953xx 64 Output Fs default DSP LRCLK MUXED MCLK CS4953xx 1 Input Fs default Note MUXED_MCLK is the clock signal that is driven by the HDMI source 1 4 Other Useful Information 1 4 1 Web Sites Cirrus Logic main web site www cirrus com 1 5 Information Shipped with the Evaluation Kit By installing cs4953x eval kit exe end users can access the information described in the followin subsections 1 5 1 DSP Information e CS4953xx Data Sheet e CS4953xx Hardware User s Manual e AN288 CS4953xx CS497xxxx Firmware User s Manual 1 5 2 Board Information e Schematics e BOM Artwork and PCB stackup
32. S42448 should be considered inverted signal for processing purposes 5 2 8 Power and Connectors The audio input connectors consist of 6 jacks for analog input e 2 RCA jacks for coaxial S PDIF input e 2 optical jacks for optical S PDIF input The audio output connectors consist of e 8 RCA jacks for analog output 1 optical jack for S PDIF output There is one control connector on the board J11 This 50 pin connector provides pins for the following functions e Serial control interface for configuring the DSP codec and S PDIF RX Reset lines for the DSP and other board devices Pins to provide power to the CRD USB Master USB control board e An interface for delivering audio data from the USB board feature not yet available The DC input connector J25 for the CRD49530 can accept 9 to 12 VDC and the power supply should be capable of supplying at least 1 amp of current The 3 voltage regulators on the CRD49530 generate the 1 8V 3 3V and 5V necessary for powering all of the ICs on the board Note that the 5 V and 3 3 V regulators run directly off the DC input supply connected to the CRD49530 while the 1 8 V regulator is dependent upon 3 3 V system power not necessarily the 3 3 V regulator The 8 power jumpers J17 J18 J19 are used to choose between the on board regulators and an external source for 5 V 3 3 V and 1 8 V This is a feature intended only for special applications so these jumpers should b
33. S49500 DSP_RESET SPI Master SPI FLASH XTAL_OUT S PDIF Data CS42448_RST CS8416 BRD_RST S PDIF IN S PDIF OUT 1 Block Diagram 2 549500 DSP 3 SDRAM and FLASH CS8416 SPDIF RX 4 5 CS42448 ADC and DAC 6 Analog Filters 7 Preamp 8 Power and Connectors Figure 5 1 CRD49530 USB Block Diagram 514951 451 0646 0 90 50 1 snuio 8002 9160 2 9 8 8 8 81 81 81 181 HDMI_MCLK HDMI_LRCLK HDMI_SCLK HDMI_SDATA1 HDMI_SDATA2 HDMI_SDATA3 HDMI_SDATA4 8 ADC HDMI_SEL 3 3VD gt gt gt gt WROD 0 2 U2 11 RN15 D Y7 12 C gt ADC SEL 121 Y6 13 Y5 14 Y4 15 D 36 RN16 4 3 2 1 4 5 Y L7 RNI6 B 2 56 18 RN16 A 1 AAA le 74LVC541APW 3 3VD 41 58416 SDOUT 4 CS8416_MCLK 4 51 58416 14 51 58416 SCLK 5 542448 5000 1 5 CS42448 SDOUT2 5 CS42448_SDOUT3 121 ADC SEL R83 10K gt gt gt gt gt OG ROOM Ia gt gt gt 0 2 vec 20 3 0 GND C36 0 12 GND RB 74LVC541APW 10K
34. U6 is not populated serial Flash is recommended for all CS4953xx systems as it makes layout of the SDRAM interface much simpler but the parallel flash footprint has been included as an option 5 2 4 S PDIF Receiver Figure 5 4 shows the schematic for the CS8416 which is a S PDIF receiver capable of supporting sample rates up to 192 kHz The serial host control port SCL CCLK SDA CDOUT AD1 CDIN ADO CS shares clock and data lines with the CS4953xx and CS42448 The CS8416 5 line is unique to this chip and driven only when in SPI mode The pull ups required for the SCL and SDA pins are shared with the other devices on the CRD49530 board The BRD_RST signal is a shared reset signal The reference clock for the CS8416 is the XTAL OUT buffered 24 576 MHz crystal output from the CS4953xx The CS8416 MCLK signal is the master audio clock for on board audio sources This clock can be either an MCLK recovered from a S PDIF stream or the XTAL OUT reference depending on the setting of the CS8416 s internal multiplexer The 58416 is master only for the 58416 MCLK signal which is one possible source for the MUXED MCLK master audio clock The CS8416 slaves to the 58416 SCLK and 58416 LRCLK signals which are used to shift 25 data out of the CS8416 and shift 125 data into the CS4953xx DS705RD3 Copyright 2008 Cirrus Logic 5 2 Detailed Schematic Descriptions CRD49530 USB User s Manual The CS8416 has 5 different S PDIF input
35. ader but cannot be used when connected to the CRD USB Master 1 3 5 Audio Input Source Multiplexer Source 0 CRD USB Master USB Board This feature is used by engineering development and debugging purposes Source 1 CS8416 and CS42448 e Reference Designators U1 U2 This multiplexer is used to select which audio sources feed the 54953 DAI pins When the on board sources CS8416 U3 and CS42448 U4 are being used the CRD USB Master data cannot be processed Likewise when the HDMI source CRD USB Master is selected the on board audio inputs are disabled 1 3 6 CS4953xx Audio DSP 54953 audio DSP U5 are a family of dual core processors designed specifically for audio applications The CRD49530 allows a designer to evaluate the CS4953xx DSPs in many different modes of multi channel input and output The 144 pin footprint on this board is compatible with any 54953 or CS497xx chip that uses the LQFP144 package DS705RD3 Copyright 2008 Cirrus Logic 1 4 CRD49530 USB System Description CRD49530 USB User s Manual Audio input data to the DSP can come from any of the following sources e CS8416 U3 e 542448 U4 e USB Master feature not currently supported Audio output data from the DSP can be sent to the following destinations e CS42448 for conversion to Analog Output AOUT1 AOUT8 e Optical S PDIF Out SPDIF TX this option disables AOUT7 and AOUT8 The CS4953xx has m
36. any applications stored in internal ROM but a host is still required to configure the application for a particular system The CRD49530 allows the PC to act as a host to boot and configure the DSP through the GUI software The CS4953xx can also be booted from external serial flash for custom applications that are not stored in the DSP s ROM Note The 144 pin footprint on this board is also compatible with the CS495xx family of DSPs The CRD49530 can support any CS495xx chip if the alternate stuffing options shown on the DSP schematic page have been followed 1 3 7 CS8416 S PDIF RX The CS8416 U3 is 192 kHz S PDIF receiver with an integrated input multiplexer All of the S PDIF input jacks RX0O RX3 are connected to the CS8416 The active S PDIF jack is selected by changing the internal mux through the serial host port of the CS8416 This selection is controlled through the Audio In configuration within DSP Composer see Chapter 4 for details When S PDIF audio is being processed the CS8416 must master MCLK for the system see Audio Clocking on page 1 6 for details 1 3 8 CS42448 Audio Codec The 542448 U4 is a high performance multi channel audio codec capable of supporting sample rates up to 192 kHz on its 6 ADCs and 8 DACs This device is used for all analog to digital and digital to analog conversions on the CRD49530 All analog inputs AIN1 AIN6 and all analog outputs AOUT1 AOUTS are connected to the CS42448 The micr
37. d to the OMCK setting to pass XTAL OUT DS705RD3 Copyright 2008 Cirrus Logic 1 6 CRD49530 USB System Description CRD49530 USB User s Manual The CS4953xx always masters its output clocks SCLK DSP LRCLK Table 1 1 ADC Clocking Clock Name Clock Master Source Clock Driver Clock Frequency MUXED MCLK CS4953xx CS8416 24 576 MHz MUXED SCLK MUXED MCLK CS42448 64 Input Fs default MUXED LRCLK MUXED MCLK CS42448 Input Fs DSP SCLK MUXED MCLK CS4953xx 64 Output Fs default DSP LRCLK MUXED MCLK CS4953xx 1 Input Fs default Note MUXED MCLK is the clock signal that is driven by the CS8416 s RMCK pin The CS8416 provides the recovered clock from the S PDIF input unless it loses signal lock in which case the 58416 passes the DSP clock XTAL OUT that it receives on the 1 3 10 2 Clock and Data Flow for S PDIF Input MUXED DAI 3 0 MUXED LRCLK MUXED SCLK C 58416 S PDIF Input MUXED MCLK a a SDOUT DAI DAO d SDIN DSP_LRCLK gt DSP DAO 3 0 CS 42 44 8 CS4953xx LL a 0 20 Figure 1 4 S PDIF Clocking The S PDIF clocking architecture is used when any S PDIF RX is used as an audio source whether S PDIF is the only audio input or is used at the same time as ADC audio i e any S PDIF RX is selected as described in USB 125 Audio Input
38. d information can be found in the DSP Composer User s Manual Both the DSP Composer software and the User s Manual for the software package will be provided by your local Cirrus Logic representative 4 2 Basic Application Download and System Configuration PCM Pass through 4 1 Follow the instructions in Installation Setup and Running First Application on page 3 1 in order to install the USB drivers on your PC and launch CS4953x version of DSP Composer the GUI used to control the CRD49530 After following the instructions in Running a Stereo PCM Application on CRD49530 USB on page 3 6 the DSP Composer main window will appear as shown in Figure 4 1 Figure 4 1 shows the DSP Composer main window for a PCM pass through application on the CRD49530 The blocks shown in the main window of DSP Composer can be selected from the folders in the left hand window pane and then connected together by wires to indicate the processing path as shown The Audio In and Audio Out blocks represent the hardware ports that need to be configured The Audio In block is used to select the S PDIF Input or Analog input that is to be processed and configure the digital audio format for the CS8416 CS42448 ADCs and the CS4953xx DAI port The Audio Out block is used to configure the digital audio format for the CS4953xx DAO port the CS42448 DACs and enable or disable the S PDIF TX output of the CRD49530 Copyright 2008 Cirrus Logic DS705R
39. d selecting Device Properties produces the DAO Properties dialog Audio Out DAO Properties polarity LARA E SELE polarity Rising edge walid v 0401 0402 relationship Dependent MELK SCLK ratios 256F s B4Fs Figure 4 9 CRD49530 Digital Audio Output Properties 4 7 Copyright 2008 Cirrus Logic DS705RD3 Programming the On board Serial Flash CRD49530 USB User s Manual il This dialog allows the user to set the following parameters for the CS4953xx Audio Output e LRCLK polarity Select the phase of LRCLK when the left sample will be shifted out e SCLK polarity Select which edge of SCLK for which the output data will be valid e 1 0 2 Select independent or unified clock domains for the DAO1 and DAO2 audio output ports MCLK SCLK Ratios Select the ratio of LRCLK to MCLK and LRCLK to SCLK 4 4 2 Changing Serial Control Protocol or SPI Memory Usage The CRD49530 is designed to communicate using either 2 or SPI protocols In order to change the communication mode in DSP Composer go to the menu bar and select File gt Properties which brings up the Project Properties dialog To configure Memory usage click on the Advanced button as illustrated in Figure 4 10 Max memory allocation and external memory can be enabled from this panel Project Properties Advanced properties Control poll rate 0 Allocate mas memory sizes External me
40. e CRD49530 and the CRD USB Master on a static free surface If the boards are not mated connect them together as shown in Figure 3 2 Notice that the USB connector on the CRD USB Master and the power connector on the CRD49530 are on the same side Connect the power supply jack to the CRD49530 board at J25 and the adapter to a wall power socket or power strip Check that the D3 green D2 red and D4 orange power indicator LEDs illuminate on the CRD4953x Make Audio Input connections to the to CRD49530 baord Connect one end of the digital audio S PDIF optical cable to SPDIF RXO on the CRD49530 board Copyright 2008 Cirrus Logic 3 2 Installation Setup and Running First Application CRD49530 USB User s Manual CIRRUS LOGIC Connect the other end of the optical cable to the optical output on the back of a DVD player or other digital audio source 6 Make Audio Output connections from the CRD49530 board e The RCA connectors labeled AOUT1 and AOUT 2 are the left and right analog output channels Use the RCA audio cables to connect these line level analog outputs to powered speakers Optical Output on DVD Player VD Optical Player Cable SPDIF_RXO SPDIF RX2 SPDIF SPDIF RX3 e CS4953x C Analog e Inputs Analog Outputs USB 2 0 Power gt Optical P To Powered Por Cable Output RCA Cables Speakers Figure 3 2 Board Setup Dia
41. e left in the REG position for normal operation DS705RD3 Copyright 2008 Cirrus Logic 5 4 Obtaining Schematic Updates CRD49530 USB User s Manual The DC input power jumper J3 is used to bring the main 9 to 12VDC supply voltage from the control connector J11 rather than the standard DC input connector J25 This jumper is not populated on the board and is intended only for special applications J3 should not be used in normal operation 5 3 Obtaining Schematic Updates Updates to the schematics for the CRD49530 Development Board can be can be obtained from your local Cirrus Logic representative as part of a design package including the associated BOM and layout artwork The schematics are provided in Adobe s portable document format PDF and PADS format The schematics included in this document are the original Revision A schematics of the CRD49530 and reflects the board as it was manufactured Newer schematics may be available that incorporate feature additions or corrections and may not match Rev A hardware DS705RD3 Copyright 2008 Cirrus Logic 5 5 0 90 50 91607 8002 1 9 4 HDMI Clock Data SPI I2C MIC Preamp CS42448 ADC Data Audio Out DESCRIPTION INC BY DATE CHK BY DATE A INITIAL DESIGN CHANGED FROM CRD49500 ADDED U13 WBD WBD SPI FLASH NOPOP U6 ROUTE HDMI SPDIF TO XMTB IN 3 13 06 3 13 06 RWN WBD aa f 8x Analog Outputs C
42. flect Rev A hardware 5 2 Detailed Schematic Descriptions 5 2 1 CS49530 USB Block Diagram Figure 5 1 shows the CRD49530 USB block diagram 5 2 2 CS4953xx DSP 5 1 The schematic for the CS4953xx core is shown in Figure 5 2 The DSP core is driven by an external crystal circuit This fixed 24 576 MHz clock is buffered and driven out the XTAL OUT pin of the CS4953xx chip and can be used as the audio MCLK for analog sampling in the CS42448 codec The PLL filter circuit on the CRD49530 is designed to allow the use of the CS4953xx family of DSPs and the legacy CS495xx DSPs The board is configured for the CS4953xx PLL by default but extra components can be populated to support the CS495xx as explained by the note on the bottom of the schematic page The DSP has a dedicated reset line 5 RESET that must be driven by the host to initialize the CS4953xx s communication mode and initiate the first boot sequence This signal is independent of any other reset on the board and can be used to sequence device power up The host communication protocol of the DSP is determined by the state of the HS 3 0 pins at the rising edge of reset The communication mode for the CRD49530 is slave I C when the SPI MODE SEL signal is driven low and slave SPI when the SPI MODE SEL pin is driven high The serial host control SCP1 SCP1 MOSI SCP1 MISO SDA SCP1 CS SCP1 IRQ SCP1 BSY is used by the host controller to boot and control the DSP N
43. gnator J25 1 3 3 Control Header e Connector Type 2x25 0 100 inch Shrouded Male Reference Designator J11 This connector is the interface between the CRD49530 and the CRD USB Master Control signals clocks data and 3 3V power are passed across this connector 1 3 4 On Board Voltage Selection Headers Connector Type 1x3 0 100 inch Stake Header Reference Designator J17 J19 The CRD49530 USB is designed to operate from a single DC power input The 9V power supply provided with the kit is connected to the DC power input jack J25 and is regulated down to the system voltages 5V 3 3V 1 8V The power selection headers should be set to the REG position when using the DC wall supply This is the default mode of operation and should not need to be changed for most applications It is possible to bypass the regulated power supplies for any of the voltages by removing the jumper from the appropriate power selection header and connecting an external voltage supply to the center pin of that selection header The third configuration for the power selection headers is the EXT position This is a special mode of operation and cannot be used while connected to the CRD USB Master control board Placing the power selection headers in the EXT position while connected to the CRD USB Master will prevent the board from operating The unpopulated header J3 is also designed for a special mode that brings 12V from the control he
44. gram 3 3 Copyright 2008 Cirrus Logic DS705RD3 Installation Setup and Running First Application C RRUS LOGIC CRD49530 USB User s Manual 3 1 3 Connecting to a PC 1 Connect the end of the USB cable to P1 on the CRD USB Master Digital I O Card Connect the A end of the USB Cable to a USB 2 0 port on a notebook or PC running Win XP Windows should recognize that a new device has been attached and display a notice saying Found New Hardware i ij Found New Hardware Opal Kelly XEM3001v2 Figure 3 3 ound New Hardware Window 4 Windows will display the Found New Hardware Wizard below Select the No not at this time radio button so that Windows does not connect to Windows Update for the drivers Click Next Found New Hardware Wizard Welcome to the Found New Hardware Wizard Windows will search for current and updated software by looking on your computer an the hardware installation or on the Windows Update Web site with your permission Read our privacy policy Windows connectto Windows Update search for software CO Yes this time only Yes now and every time connect a device 9 No natthis time Click Next ta continue lt Back gt Cancel Figure 3 4 Found New Hardware Wizard Window 5 Windows will then ask whether to use automatic installation or manual installation Allow Windows to install the software automatically and cl
45. ic Descriptions CRD49530 USB User s Manual Each output of the CS42448 has an output filter that consists of an AC coupling cap 3 3 uF a pull down resistor to prevent the output from floating when not connected to a load a series resistor 470 2 to provide a voltage drop when the muting transistor is enabled and a mute transistor that will pull the output low when the mute control signal is enabled The series resistor is small enough that it does not affect the signal in normal operation assuming a load of at least 10 kQ is connected to the analog output of the board 5 2 7 Microphone Preamplifier Figure 5 7 shows the microphone preamplifier on the CRD49530 USB which has a 1 8 microphone input jack to allow direct connection to an encapsulated condenser microphone ECM Because the output of the ECM is so small a pre amplifier is needed to boost the signal to a line level voltage These specifications for the amplifier are noted on the schematic page These parameters should be considered when choosing the microphone to be connected to the CRD49503 USB Too large of a signal on the CS42448 analog input will result in distortion of the sampled signal It is important to note that although the amplifier circuit shown is non inverting the input to U12 B is the same polarity as the output from U12 C the output of an ECM is inherently inverted since it acts as an open collector device Therefore the microphone signal driven to the C
46. ick Next DS705RD3 Copyright 2008 Cirrus Logic 3 4 Installation Setup and Running First Application CRD49530 USB User s Manual CIRRUS LOGIC Found New Hardware Wizard This wizard helps wou install software for Opal Kelly sEMS001 5 If your hardware came with an installation CD n floppy disk insert it now What do you want the wizard to do 9 Install the software automatically Recommended Install fram a list or specific location Advanced Click Nextta continue Figure 3 5 Found New Hardware Wizard with Automatic Installation Option Window 6 It is possible that during the installation Windows might issue a warning that the drivers have not passed Windows Logo testing Select Continue Anyway Hardware Installation The software you are installing for this hardware Opal Kelly ve has not passed Windows Lago testing ta verity its compatibility with Windows Tell me why this testing is important Continuing your installation of this software may impair or destabilize the correct operation of your system either immediately in the future Microsoft strongly recommends that you stop this installation now and contact the hardware vendor for software that has passed Windows Logo testing Continue Anyway STOP Installation Figure 3 6 Hardware Installation Window 7 Windows should locate the correct drivers and complete the installation
47. is information as the basis for manufacture or sale of any items or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copy rights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WAR RANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY AUTOMOTIVE SAFETY OR SECURITY DEVICES LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY EXPRESS STATUTORY OR IMPLIED INCLUDING THE IM PLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER
48. istory RT Fees Update DSP Composer information Updated Figure 5 2 CS49953xx DSP on CRD49530 USB Board on page 7 Added note to Section 5 2 3 Memory on page 5 2 Removed Cirrus Corporate address information from DEC 2007 page 2 Use the URL for the Cirrus Logic Website located in the legal notice on this page to obtain the latest Cirrus Logic ontact information Replaced technical reference manual and replaced it with User s Manual to match current documentation style practices Reformatted manual into current style practices Reorganized content into September 8 Chapters with page numbers the lt chapter gt lt page number format 2008 Changed document number from DS732RDx to DS705RDx to match the numbering schema for the data sheet for the CS4953xx product 99 05705803 Copyright 2008 Cirrus Logic 6 2 Revision History CRD49530 USB User s Manual 6 3 Copyright 2008 Cirrus Logic DS705RD3 Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Cirrus Logic CRD49530 USB
49. m allowed Board comm made Extemal mem address Coefficient ramp time constant s E ternal mem size Clip hold time x heap size 3000 memory En use Y heap size memory to use Compiler message level Advanced Cancel Figure 4 10 CRD49530 Comm Mode Memory Usage 4 5 Programming the On board Serial Flash The CRD49530 is populated with 4 Mbits of serial Flash that can be used to store custom DSP firmware or run time firmware configuration options In order to emulate a system that boots the DSP from Flash the serial flash can be programmed in system with the desired DSP firmware The host the PC in this case can be used to perform a host controlled master boot HCMB to boot the 54953 A special uld file is loaded into the CS4953xx which provides the programming interface to the system host Programming then becomes a sequence of messages to the 54953 Please contact your local Cirrus representative for the Flash programming uld file and the associated application note 99 0570503 Copyright 2008 Cirrus Logic 4 8 Introduction CRD49530 USB User s Manual Chapter 5 CRD49530 USB Schematics 5 1 Introduction The schematics included in this document are the original Revision A schematics of the CRD49530 and reflect the board as it was manufactured Newer schematics may be available which incorporate feature additions or corrections and may not re
50. o Codec OM ssa Ee Ea 1 9 1 5 4 S PDIF Receiver 1 9 1 5 5 DSP Software Utility Information 1 10 2 1 Introducing the CRD49530 USB Customer Reference Kit 2 1 2 1 1 Identifying Components the CRD49530 USB 2 2 3 1 Installation Setup and Running First 3 1 3 1 1 Evaluation Software Installation nnne 3 1 3 1 2 Setting up the CS49530 USB 3 2 3 1 3 3 4 3 1 4 Running a Stereo PCM Application on 49530 05 3 6 3 1 5 Downloading Other Applications 3 6 SM MI m m 4 1 4 2 Basic Application Download and System Configuration PCM Pass through 4 1 2 NUN IE OC RR 4 3 4 2 2 Channel Remap of 54953 4 3 4 3 Changing Audio Input Source 4 4 4 3 1 OU eh m 4 4 4 3 2 Analog TENUERE UU 4 5 4 3 3 USB S Audio 4 5 4 3 4 DAI 4 6 4 4 Changing Audio Output
51. oot HCMB of custom applications from 4 Mbit serial SPI flash device Microphone input with integrated amplifier for Intelligent Room Calibration IRC evaluation e Supports all members of the 54953 and CS497xx family in the 144 pin LQFP package Copyright 2008 Cirrus Logic DS705RD3 Introducing the CRD49530 USB Customer Reference Kit C RRUS LOGIC CRD49530 USB User s Manual Note Not all features of the CS4953xx are exercised on the CRD49530 2 1 1 Identifying Components on the CRD49530 USB shows the top side of the CRD49530 The accompanying legend identifies the main components of the board POS 13 90 60 COO 114 s 0s M X 2 N Em 0 CA 4 2 JE 4 mI o ib ETN Brean z gt T Mt MA tb a EI oO O a UR ALI N lt C15 HEHEH O rettet ttt M 2 E zd 2 AE M 2 ka B1i g OG 6 GG 66 9 9 opga Pu S 26 T 75 3270 7 zi LOGIC OMOMOMNONONORC CS495313CQ4Z JP3 1 9 EK ji 415 75 7 AONO 59 MUI a OROROORO errer Wir MM P WM te t 4 VS
52. ophone input shares the AIN5 ADC with the AIN5 RCA jack When the microphone is in use the AIN5 RCA jack is ignored When analog audio is being processed the 24 576 MHz crystal for the CS4953xx must master MCLK for the system see Audio Clocking on page 1 6 for details 1 3 9 Memory The CRD49530 is populated with a 4 Mbit serial flash There are 2 footprints U11 U13 on the board for compatibility with both standard 8 pin serial flash pinouts The serial control lines are shared by both footprints Only one serial flash chip can be populated The CS4953xx can use external SDRAM U7 to implement features such as large multi channel audio delays A 64 Mbit SDRAM 166 MHz is connected to the 150 MHz memory bus of the CS4953xx There is an additional unpopulated footprint for a parallel flash U6 memory device This device was routed on the board as an example of how to route the memory bus when using a parallel flash memory Copyright 2008 Cirrus Logic DS705RD3 CRD49530 USB System Description CRD49530 USB User s Manual but Cirrus recommends using serial flash for all systems Adding a parallel flash makes the routing of the SDRAM bus much more complicated 1 3 10 Audio Clocking Clocking architecture is one of the most important aspects of an audio system The input and output clock domains of the DSP must be synchronous when delivering audio data in an isochronous fashion constant bitrate delivery even if the input output
53. ote that the pull up resistors on the SCP1 IRQ and SCP1 BSY pins are required for both SPI and control since these are open drain pins The pull ups on the SCP1 and SCP1 SDA pins are required only for I C operation The second serial control port SCP2CK SCP2 MOSI SCP2 EE CS is connected to the on board serial SPI flash chip found on the memory page of the schematic The DSP has a debug port DBDA DBCK that allows a developer to debug the DSP during normal operation This is a slave port that can be connected to an IC master or it can be simply terminated with pull up resistors The audio input pins of the CS4953xx are driven by a multiplexer U1 U2 that chooses between 125 audio from an off board source HDMI audio and the on board S PDIF RX CS8416 and audio codec CS42448 This multiplexer defaults to choose the on board audio sources The HDMI audio delivery interface is currently under development Copyright 2008 Cirrus Logic DS705RD3 Detailed Schematic Descriptions CRD49530 USB User s Manual The input and output audio clocking domains are separated This allows the DSP to accept audio in one Fs and produce output samples at a different sample rate such as 2Fs or 4Fs The CS4953xx is slave only on the input clock domain MUXED SCLK MUXED LRCLK On the audio outputs the CS4953xx is slave only for the MUXED MCLK master audio clock and master only for DSP_SCLK and DSP LRCLK which are used to shift da
54. pplication It is important to install the latest Evaluation Software cs4953x 1 kit exe BEFORE connecting the USB cable from the PC to the CRD Master USB daughter card Failure to install the evaluation software before the initial connection can result in an inability to communicate with the CRD49530 3 1 1 Evaluation Software Installation 3 1 The DSP evaluation software installation will first install the Cirrus Logic DSP evaluation software followed by the USB drivers required to communicate with the CRD USB Master 1 Run the latest DSP evaluation software installation executable cs4953x eval kit rcxx exe This executable is supplied by your Cirrus Logic representative At the Welcome screen click Next At the Licensing Agreement window select the accept the agreement radio button to agree to the terms and then select Next Select the Destination Location window Select the default location CirrusDSP and click Next Select Start Menu Folder window Select the default location C CirrusDSP and click Next The Ready to Install window indicates the selected destination location and the Start menu folder for confirmation select nstall to begin the install process which should take less than one minute After the DSP evaluation software is installed the installer will launch the Front Panel Driver Setup Wizard below Click Nextto continue the installation Copyright 2008 Cirrus Logic DS705RD3
55. rated in Figure 4 5 Double click on the Audio In block then select the SPDIF block Right clicking the SPDIF block and selecting Device Properties will display the SPDIF Rx Properties dialog SPDIF Rx Properties Input Fs HMaster Slave Master RA 0 Figure 4 5 CRD49530 S PDIF Rx Properties DS705RD3 Copyright 2008 Cirrus Logic Changing Audio Input Source CRD49530 USB User s Manual SS CIRRUS LOGIC 4 3 2 Analog Audio Input To deliver data to the DSP via 6ch ADC drag the Audio In block to the work space and select Analog as the Input Source Double click the Audio In block to see the signal flow The Device properties of the Analog element lets you select the sampling frequency of the ADC on the CS42448 CODEC The Master Slave property must always be set to Master to indicate that the ADC will master SCLK and LRCLK as described in Section 1 3 10 Audio Clocking on page 1 6 The Audio In module with Analog as the input source Is illustrated in Figure 4 6 Codec Properties Enable mic input Input Fs Master Slave Figure 4 6 CRD49530 Analog Properties This S PDIF and Analog dialog allows the user to set the following parameters Input and Output Sampling Frequency Range Select the Fs range where 1FS 32 kHz 44 1 kHz or 48 kHz Fs 64 kHz 88 2 kHz 96 kHz 4FS 128 kHz 176 4 kHz 192 kHz Master Slave settings for the SCLK amp LRCLK pins on the CS841
56. s available to it Its internal multiplexer is used to select the active source general purpose output of the CS8416 is used to generate an independent reset signal for the CS42448 audio codec Providing a separate reset line for each audio device allows the system to sequence the order in which audio devices come out of reset The CRD USB Master USB board acts as the host controller in the CRD49530 platform and is connected to the CRD49530 via J11 on page 8 of the schematics The USB Master drives the serial host control port and CS8416 RESET signals on this page 5 2 5 Audio CODEC Figure 5 5 shows the schematic for the CS42448 which is a multi channel ADC DAC that is capable of simultaneously supporting up to 6 channels of analog input and 8 channels analog output The serial host control port SCL CCLK SDA CDOUT AD1 CDIN ADO CS shares clock and data lines with the CS4953xx and CS8416 CS42448 CS line is unique to this chip and driven only when in SPI mode The pull ups required for the SCL and SDA pins are shared with the other devices on the CRD49530 board The CS42448 RST signal is a dedicated reset signal driven by a general purpose output of the CS8416 The CS42448 is a slave to the MUXED MCLK signal which is the master audio clock for the entire CRD49530 system The CS42448 masters the 58416 SCLK and 58416 LRCLK signals which are used to shift 25 data out of the CS42448 and shift 125 data into the CS4953x
57. ta out of the CS4953xx The CRD USB Master USB board acts as the host controller in the CRD49530 platform and is connected to the CRD49530 via J11 on page 8 of the schematics The CRD USB Master drives several DSP interfaces including the serial host control port SCP1 the debug port and DSP RESET The CRD USB Master also controls the multiplexer ADC HDMI SEL that selects the I S audio input lines for the CS4953xx 5 2 3 Memory Figure 5 3 shows the schematic for the SDRAM and Flash memory blocks The CRD49530 was designed with 4 Mbit of serial flash on board Both standard serial flash footprints are supported in this design and this is shown in the schematic as two different serial flash devices By default only the SST flash U13 is populated The CRD49530 is populated with a 64 Mbit 166 MHz SDRAM with a 16 bit wide data bus U7 Note that both the series termination R40 and the parallel termination R42 for SD_CLKIN are physically close to the DSP on the board Both termination options were designed into the CRD49530 but only the parallel termination is being used on this board so the series terminator R40 is populated with a O ohm resistor Note 5 is the default bank address for 16 Mbit SDRAM designs SD and SD BAO swapped in the CRD49530 USB design to allow for the evaluation of both 16 Mbit and 64 M bit designs SD BA1 and SD BAO do not need to be swapped for 64 Mbit designs The parallel flash
58. tem block in DSP Composer Select the DAO remap tab as illustrated in Figure 4 3 and click on the DAO1 Combo Box to select the internal channel to route to DAO1 channel System DAT AQ Left CADI DAT AO Right DATA Left DADO DATA Right DAO DATA2 Left 801 DATA Right XM TA Left Ah TA Right jc DAO2 DAT AO Left DAO2 DATAO Right DADS DATA Lett DAO Right E S 88 DAO2 DATA2 Left DAO2 DATAS Right DADS DATAS Lett DAO BATAS Right System PCM Reman DAO Remap 4 Schematic Figure 4 3 CRD49530 DAO Channel Remap 4 3 Copyright 2008 Cirrus Logic DS705RD3 Changing Audio Input Source C IRRUS LOGIC CRD49530 USB User s Manual 4 3 Changing Audio Input Source The active audio input to the CRD49530 is selected through the Audio In block in DSP Composer this is done by right clicking on the Audio In block and selecting Device Properties as illustrated in Figure 4 4 Audio In Properties Input source SPDIF we format 125 24 bit w Figure 4 4 CRD49530 Audio In Properties This dialog allows the user to set the following parameters for the CS4953xx e Input Source S PDIF Analog or USB Audio Data Format 12 LJ etc 4 3 1 S PDIF Audio Input The CRD49530 has four different S PDIF input jacks The active S PDIF input is selected using the SPDIF RX Device Properties dialog box in DSP Composer as illust
59. the supply is plugged into a wall outlet Possible cause CRD49530 USB Drivers not installed before connecting to PC Solution Follow these steps 1 Pull the DC power plug on the CRD49530 2 Open the device manager on the PC and search for the Opal Kelly device under USB Devices If there is a question mark next to the device right click on it and open Properties Press the Update Driver button and let Windows automatically find the driver 4 Wait 3 seconds and plug the DC power supply back in 6 1 Copyright 2008 Cirrus Logic DS705RD3 Revision History CRD49530 USB User s Manual 6 1 3 Audio is not Heard Problem Audio cannot be heard Possible cause S PDIF Source is not connected to RXO Solution Follow the instructions in Running a Stereo PCM Application on CRD49530 USB on page 3 6 If the sound still cannot be heard connect the audio source to RXO or change the S PDIF input to the appropriate connector according to the instructions in USB 125 Audio Input on page 4 5 6 1 4 Only Stereo Audio is Heard Problem Only Stereo Audio is heard even when delivering a multi channel compressed audio stream e g Dolby Digital DTS Possible cause DVD Player is not configured properly Solution DSP is auto detecting a PCM stream and playing the 2 channel PCM Navigate to the audio setup for the DVD player and set to Bitstream Out instead of PCM Out yp H
60. to determine the clock dividers needed to derive Fs in ADC only applications If this number changes then all dividers for LRCLK SCLK will change by the same ratio e g 024 576 MHz MCLK 512 1Fs LRCLK 912 288 MHz MCLK 256 1Fs LRCLK DS705RD3 Copyright 2008 Cirrus Logic Changing Audio Output Source CRD49530 USB User s Manual CIRRUS LOGIC 4 4 Changing Audio Output Source The audio output section of the CRD4930 is configured through the Audio Out block in DSP Composer this is done by right clicking on the Audio Out block and selecting Device Properties as illustrated in Figure 4 8 Audio Out Properties Data Format 25 24 bit Fs Enable SPDIF output Figure 4 8 CRD49530 Audio Out Properties This resulting dialog allows the user to set the following parameters for the CS42448 DACs Audio Data Format 125 LJ etc Output Sampling Frequency Range Select the Fs range where 1FS 32 kHz 44 1 kHz or 48 kHz 2Fs 64 kHz 88 2 kHz 96 kHz 4FS 128 kHz 176 4 kHz 192 kHz etc SPDIF Enable Checking this box configures DAO for S PDIF output rather than 125 4 4 1 DAO Output of CS4953xx The digital audio output DAO of the CS4953xx is very flexible making it compatible with a wide variety of audio devices This port can configured using the dialog box shown in Figure 4 9 Double click on the Audio Out block then select the DAO block Right clicking the DAO block an
61. x The CS42448 slaves to the DSP_SCLK and DSP LRCLK signals which are used to shift 125 data out of the CS4953xx and shift 12 data into the CS42448 The analog inputs and outputs of the CS42448 are being used in single ended mode This is evident when looking at the input and output filter circuitry on page 6 of the schematics AIN5 of the CS42448 has an internal analog multiplexer that can be used to select between single ended inputs on the AIN5 and AIN5 pins This feature is used to share AIN5 between the microphone input and RCA jack J27 The transistor connected to MUTEC Q1 provides the current drive necessary to drive all of the mute transistors see page 6 of schematic into saturation The CRD USB Master USB board acts as the host controller the CRD49530 platform and is connected to the CRD49530 via J11 on page 8 of the schematics The CRD USB Master drives the serial host control port signals shown on this schematic page 5 2 6 Input Output Filters Figure 5 6 shows the input and output filters for the CRD530 USB board Each input of the CS42448 has its own input filter that consists of a voltage divider an AC coupling capacitor 10 uF and a anti aliasing capacitor 2700 pF The voltage divider is provided to make the CRD49530 USB capable of accepting analog signals of up to 2 VRMS The CS42448 analog inputs register full scale for an input amplitude of 1 VRMS 5 3 Copyright 2008 Cirrus Logic DS705RD3 Detailed Schemat

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