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The Insider`s Guide To The Philips ARM7

1. P 18 Data Processmb a 19 Conun SIS 1 CDS carat a a 20 Copyn MUNIPIC Resistors s c ein Eo caes Sir Caen v eta dso 20 21 Modifying The Status 21 Software interrupt m m m aaas 22 M Bryce RAE 23 THUMB Instruction 24 umar 26 Chapter 2 Software Development 27 Boni M N 27 Which Compiler cr A 27 UVLIQ LE s l 28 l m l 28 Startup Code H 29 Interworking ARM THUMB 222 252222222222 31 STDIO 32 Accessino 33 Interrupt Service Foutinese EI RI EE sd E PEE 34 Exception source Constants table C function prototype 34 pe eret eden Da YR 36 Locat na Code M RAM m 36 Operating System SUpport 38 Fixing Objects At Absolute 5 2222 38 Erle ASSembIet siiis dioi 38 Hardware Debubemes 10015 39 Introduction to the LPC2000 Introduction M
2. 4 r Erase Blank Communication Filename Connected To Port MAM hex Kee Blank Check f Entire Device come Selected Sectors 5200 Use Baud Hate Upload to Flash yi afar olean 25 19200 Erase l 14 Compare Flash Manual Reset End Sector Time Out sec d Device x 9 Use DTR RTS Device E for Reset and LPEz1 24 Read Part in Freq kHz P2000 o Device ID Bootloader ID Selection Make sure the Use DTR RTS box 1s ticked Press the Read Device ID button If the board is connected ok the part ID number and bootload version will be displayed Make a note of these numbers as we will use them in the next exercise 149 Introduction to the LPC2000 5 Tutorial With Keil Tools Next select the MAM hex file from the project directory and press Upload to Flash this will program the target LPC2100 You can also use the Compare button the verify that the flash has programmed correctly If you select the buffer option the same operations can be performed along with calculation of the program signature and limited debugging options 2 LPC2000 Flash Utility Flash Buffer C 00 SF E5 OO 00 S0 E5 10 AO E1 l AO Ej j sel Load Hex File Vector Calc Upload to Flash D
3. 189 Exercise Using THUMB Codo a o bene anus 190 Exercise 4 Usine The GNU Librarie S c dieti a coco eed xoi eec tus 192 XEncIse co one MEO nerra im m eene s LA 193 Exercise 6 SOIDWare Inte EF DE 195 ADppendiceeee m 197 Appehdix A rU 197 BiplOStapny oen EMO a a a b nee 197 W CDIOSTApAY T T 197 KO em aa a 197 Tools and Software Development ies oe reto ot s da 197 Evaluation Boards And Modules ecce eee eee eee eee ee eee eee eee eee s s 197 Introduction to the LPC2000 Introduction Introduction This book is intended as a hands on guide for anyone planning to use the Philips LPC2000 family of microcontrollers in a new design It is laid out both as a reference book and as a tutorial It is assumed that you have some experience in programming microcontrollers for embedded systems and are familiar with the C language The bulk of technical information is spread over the first four chapters which should be read in order if you are completely new to the LPC2000 and the ARM7 CPU The first chapter gives an introduction to the major features of the ARM7 CPU Reading this chapter will give you enough understanding to be able to program any ARM7 device If you want to develop your knowledge further there are a number of excellent books which describe this architecture and some of these are listed in the bib
4. dd a 68 Example Program FIQ intetmiptu ba l sas 69 3 ce HO d b 70 z ATIRO lut np a Ad 71 Nea varie AMIRO Inte 72 Example Program TRO inter pt Let aad amie salsa sitis d eric T2 Non Veclorcd Intern Upis R a bserasmonasiksachnooctautesaandadtinborzenasaadencicodhamanseidants 73 Leaving A Non Vectored IRQ Interr pt niet e eer tutis gar utate Aut 73 Example Program Non Vectored 73 Nested MEUD S l 75 SUMM ARV ee 76 Chapter 4 User Peripherals ieoor a a RIS MISSE 78 OUE eesi 78 Introduction to the LPC2000 Introduction General Purpose 78 General Purpose TIDIGES iiir EE C an n D 79 YVVEMlodulutoE z ay 82 Real Time Clot K iiiter eiecit t n n n 85 Yatcudoa 68 UAR pe Da aaa a a 90 nterlaceeo m 94 SPLE aCe sn la T TC 99 Analos To Dieital Converter Ba dad 101 Digital To Analog ConverteFem 104 CAIN Controller na anana an a 105 ISOTEC err Mode ERR 105 CAN Node 00 c bbc tu lotos den oS iUd cbe UN Metis E cues 106 CAN Messac ODIe6lssde Md editi a od i ME D od o MER 107 CAN Bus ArDitbat OI adda ay ya a amad Unde a up serene 109 bilunmi m o o 110 CAN Message Tras es ab ua s 112 CAN E
5. Run to a point in the code This is a quick way of getting to an arbitrary pointing your code Select a line of code open the local menu select run to cursor This will execute code until this line is reached You can also select Set program counter This forces the PC to the current position without running any code 134 Introduction to the LPC2000 Select view disassembly to see the underlying assembler code Disassembly l 7 MOV SIMDB SUB BL E1A0CO00D E92DD870 E24CB 4 EBFFFFEA tor 333 R12 R13 R13 R4 R6 R11 R12 R14 PC 11 12 80 00000004 0 000000 0 0 000000 6 0 000000 0 000000 0 29 30 0 0000008 4 0 000000 6 sd 0 000000 6 32 LDR MOV z 0 SIR R6 R5 0 i lt 20 i E59F5030 06000 counter 5856000 bor i R5 PC 0x0030 R6 0x00000000 E1A04006 MOV counter E5950000 LDR E2800001 ADD E5850000 STR fiboCount 0 00000100 R4 R6 34 0 00000104 0 00000106 0 0000010 35 36 37 0 00000110 0 00000114 0 00000116 RO R5 RO RO 0x00000001 RD R5 Fibonacci counter 6 BL 59 3014 LDR 5830000 STR Fibonacci x 000000BD R3 PC 20x0014 RD R3 Examine program variables 5 Tutorial With Keil Tools In the C code window place the cursor on the counter variable Open the local window and select Add counter to watch window in the sub menu select
6. Must be Data Length Code reserved bit D IDE bit D RTR bit D Identifier Field Start of Frame Recessive Each message must be acknowledged by having a dominant bit inserted 1n the acknowledge field If no acknowledge is received the transmitter will continue to send the message until an acknowledge is received Standard 8 bvte Data Frame nter Frame Space lt Recessive 0 Dominant Transmitting I Intermission node transmits End of Frame Acknowledge Recessive any ACK Delimiter node that has ACK Slot seen the frame as CRC Delimiter a valid CAN All CAN frames must be acknowledged If there is no CRC Sequence RC Sequence handshake the message will Data Field frame overwrites with Dominant be re sent Data Length Code If transmitting reserved bit D node does not read back IDE bit D dominant then RTR bit D frame 15 re sent Identifier Field Start of Frame The CAN message packet also contains a 15 bit CRC which is automatically generated by the transmitter and checked by the receiver This CRC can detect and correct 4 bits of error 115 Introduction to the LPC2000 4 User Peripherals in the region from the start of frame to the beginning of the CRC field If the CRC fails and the message is rejected an error frame is placed onto the bus Standard 8 byte Data Frame Inter Frame Space Xn 1 Recessive 1 1 7 3 NN an 0
7. Set address to 0x22 Standard Frame C2TDA1 NetworkData Copy some data into first four bytes C2CMR 0x00000001 Transmit the message 113 Introduction to the LPC2000 4 User Peripherals Exercise 25 CAN Transmit This exercise configures the second CAN channel for 125K bits second and repeatedly transmits a CAN message frame 114 Introduction to the LPC2000 4 User Peripherals CAN Error Containment The CAN protocol has five methods of error containment built into the silicon If any error is detected 1t will cause the transmitter to resend the message so the CPU does not need to intervene unless there is a gross error on the bus There are three error detection methods at the packet level form check CRC and acknowledge plus two at the bit level bit check error and bit stuffing error Within the CAN message there are a number of fields that are added to the basic message On reception the message telegram is checked to see if all these fields are present If not the message 1s rejected and an error frame is generated This ensures that a full correctly formatted message has been received Standard 8 byte Data Frame nter Frame Space i l Recessive Ep lt 0 Domunant i MT Intermission End of Frame L ACK Delimiter ACK Slot Frame Check 12 Delimiter The frame check tests that a VZ4 CRC Sequence correctly formatted CAN 2 Data Field message has been received
8. This chapter contains worksheets for the practical examples that are available on the CD There are two sets of examples one for the Keil compiler and one for the GNU compiler This chapter is written for the Keil compiler If you want to use the GNU compiler you should start with Appendix A which details the non ANSI additions to the GCC compiler Appendix A also contains example worksheets for the first six exercises that deal with the specifically with GNU tools After exercise six you can rejoin this chapter and use either the GNU or Keil examples for the remaining examples Installation All the necessary software for the practical examples is on the CD that comes with this book If you place the CD in the drive on your PC the following window will appear Macromedia Flash Player 7 E ES X nml xl DEVELOPMENTTOOLS Philips LPC Seminar 2100 CD ROM Welcome to the embedded world of Hitex Application notes for the ARM processor Course notes for the ARM Tools Exercises ISP MCB2100 Information User Manuals CMX Operating System iH ui a N Install Keil GNU Compiler AL Acrobat wi Reader Setup Keil ARM uVision Developement Software 1 First it is necessary to install the Keil uVISION software this will also install the Keil compiler 2 If you wish to use the GNU compiler you will need to install this separately once uVISION is installed Next install the example set
9. Connect the PLL as the main clock source PLLCON 0x00000003 Set the VLSI peripheral bus to 30 00MHz VPBDIV 0x00000002 Compile the code and load it into the board 157 Introduction to the LPC2000 5 Tutorial With Keil Tools Run the initPLL routine and observe the results in the Peripherals PLL window This will show the true bus frequency Phase Locked Loop PLL X Control Register PLLEDN 0 03 WwW PLLE Iw PLLC Configuration Register PLLCFG 0x24 MSEL 5 PSEL 2 Status Register PLLSTAT Oxtir24 MSEL 5 T PSEL 2 T PLLE fw PLLC v PLOCK Feed Register PLLFEED 0455 Crystal Oscillator amp Processor Clock XTAL 12 000000 MHz Cristal Oscillator Fasc CLOCK 60 000000 MHz Processor Clock CELK Configuration of the PLL can be done via the Keil startup code but for this exercise this code is disabled The equivalent settings for the startup code are shown below Stack Configuration Stack Sizes in Bytes PBDTY Setup MSEL PLL Multiplier Selection PSEL PLL Divider Selection MAM Setup oll x S 158 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 11 Fast Interrupt In this exercise we will configure an the external interrupt to be handled as an FIQ This code was used in exercise 5 to show the C handling of an interrupt function This time we will see how to configure the hardware for an FIQ interrupt Open the project i
10. DEVELOPMENTTOOLS THE INSIDER S GUIDE TO THE PHILIPS ARM BASED MICROCONTROLLERS An Engineer s Introduction To The LPC2100 Series Trevor Martin BSc hons CEng MIEE www hitex co uk arm Introduction to the LPC2000 Introduction Published by Hitex UK Ltd ISBN 0 9549988 1 First Published February 2005 First Reprint April 2005 Hitex UK Ltd Sir William Lyons Road University Of Warwick Science Park Coventry CV4 7EZ Credits Author Trevor Martin Illustrator Sarah Latchford Editors Alison Wenlock amp Michael Beach Cover Michael Beach Acknowledgements The author would like to thank Kees van Seventer and Chris Davies of Philips Semiconductors for their assistance in compiling this book Hitex UK Ltd 21 04 2005 All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical or photocopying recording or otherwise without the prior written permission of the Publisher 2 Introduction to the LPC2000 Introduction Introduction to the LPC2000 Introduction IntEOOUCHOH Gri EE ro EHE D Io ceo MN s e NM NI E 8 Chapter Ts Tne ARMY CPU Core ass 10 Sor UN 10 The PICMG sche cess C l na 10 IRG GISUCES E 11 Current Program Status 12 Exception Modis aito e rc be IEEE a 13 ARM 7 IDSEEUCUOTSS OL t RE 16
11. 0 delay lt 0x000100000 delay t simple delay loop IOSETII i Set the next led t 1s also possible to declare individual functions as either ARM or THUMB functions by using the following declarations on the function prototype int ARM FUNCTION int my var THUMB int THUMB FUNCTION int my var THUMB Exercise 3 Interworking The next exercise demonstrates setting up a project which interworks ARM and THUMB code STDIO Libraries The high level formatted IO functions in the STDIO library such as printf and scanf are directed at UARTO on the LPC2000 It is up to the programmer to initialise the UART to the correct BAUD rate Once this is done it is possible to use these high level functions to stream data to a terminal program on a PC for example The STDIO functions use two low level drivers to send and receive a single character to the conio the UART in this case The two functions are called putchar and getchar and the source for them is available in serial c in the Keil lib directory By adding this file to your project the default library version is 32 Introduction to the LPC2000 2 Software Development ignored and the code in serial c is used in its place So by rewriting the putchar and getchar routines the high level printf and scanf function can be redirected to any IO device you want to use such as an LCD and keypad Bear in mind that the high level STDIO functions ar
12. Arg D x 8000 Finally the THUMB instruction set does contain a SWI instruction which works in the same way as in the ARM instruction set but it only contains 8 unused bits to give a maximum of 255 SWI calls 25 Introduction to the LPC2000 1 The ARM7 CPU Core Summary At the end of this chapter you should have a basic understanding of the ARM7 CPU Please see the bibliography for a list of books that address the ARM7 in more detail Also included on the CD is a copy of the ARM7 user manual 26 Introduction to the LPC2000 2 Software Development Chapter 2 Software Development Outline In this book we will be using an Integrated Development Environment from Keil Electronic This IDE is called uVISION pronounced MicroVision and versions already exist for other popular microcontrollers including the 8051 and the Infineon C16X family uVISION successfully integrates project management editor compiler and debugger in one seamless front end Although we are concentrating on the LPC2000 family in this book the Keil ARM tools can be used for any other ARM based microcontroller Which Compiler The uVISION development environment can be used with several different compiler tools These include the ARM ADS compiler the GNU compiler and Keil s own ARM compiler In this book the examples are based on the Keil CA ARM compiler However a parallel set of examples is also included for the GNU compiler and Appendix A details
13. Fr 54 fo Node B UST dT n Node C m ua deae Node B loses Node C loses CAN arbitrates its messages by a method called non destructive bit wise arbitration In the diagram above three messages are pending transmission Once the bus 1s idle and they are synchronised by the start bit they will start to write their identifiers onto the bus For the first two bits all three messages write the same logic and hence read back the same logic so each node continues transmission However on the third bit node A and C write dominant bits and node B writes recessive At this point node B wrote recessive but reads back dominant In this case it will back off the bus and start listening Node A and C will continue transmission until node C write recessive and node A writes dominant Now node C stops transmission and starts listening Now node A has won the bus and will send its message Once A has finished nodes B and C will transmit and node C will win and send its message Finally node B will send its message If node A is scheduled again it will win the bus even though the node B and C messages have been waiting In practice the CAN bus will transmit the message with the lowest value identifier 109 Introduction to the LPC2000 4 User Peripherals Bit Timing Unlike many other serial protocols the CAN bit rate is not just defined by a baud rate prescaler The CAN peripheral contains a Baud rate prescaler but it is used to generate a
14. If you program the PLL with interrupts enabled it is conceivable that an interrupt could occur after the first word of the sequence is written and the new PLL settings would not become effective To set up the PLL you must write the values for P and M to the PLLCFG register Then using the PLLCON register the PLL is enabled This starts up the PLL but there is a finite startup time before it is stable enough to be used as the Cclk source The startup of the PLL can be monitored by reading the LOCK bit in the PLLSTATUS register Once the lock bit 1s set the PLL can be used as the main clock source Alternatively an interrupt can be generated when the PLL 61 Introduction to the LPC2000 3 System Peripherals locks so that you can carry out other tasks while the PLL starts Once the PLL has locked as a stable clock source it can replace the external oscillator as the source for Cclk This 1s done via the PLLC bit in the PLLCON register The PLL setup sequence is performed by the Keil compiler startup code and you just need to provide values for M and P An interrupt is also generated when the PLL locks This can be used to replace the polling of the lock bit to achieve maximum startup performance Has PLL Locked Care should be taken with the values stored for the constants in the PLLCFG register The values written to the register for the constants are P 1 and M 1 which ensures that the values of P and M in the PLL are never zer
15. Mux P PVVM2 Additional circuitry on the match output channels allov s the generation of six channels of single edge PWM Math2 Bing eda modulation or three channels of dual edge PWM modulation PWM SEL 2 i aen a PWM ENA 3 PWM Control Register This arrangement of SR flip flop and multiplexers allows the PWM modulator to produce either single edge or dual edge controlled PWM channels The multiplexer is controlled by the PWMSEL register and can configure the output stage 1n one of two configurations The first arrangement is for single edge modulation Reset timer counter PWM 1 Match 1 The multiplexer can be programmed to use Single Edge PWM Match 0 to set the external pin at the beginning of a cycle the remaining match channels are used to modulate each PWM channel PWM 2 Match 2 83 Introduction to the LPC2000 4 User Peripherals Here the multiplexer is connecting Match 0 to the S input of each flip flop and each of the remaining channels are connected to the R input With this scheme Match is set up to count to total cycle period At the end of the cycle it will reset the counter and set match 0 high This causes all the flip flops to be set at the beginning of the cycle The output Q goes high raising all the output pins high Modulation of the PWM signal is done with the remaining match channels Each PWM channel has an associated match channel which is connected
16. PC PC PC PC PC PC PC m x l1a T x l1a m x l1a 20200151 0 00185 PC PC Ox0FFO PC PC 0 0018 0 50000040 0250000324 0250000320 02500005312 0250000315 0200000000 0250000314 0250000310 If you single step off the reset vector you will jump to 0x80000040 and start running code from the external Flash device 155 Introduction to the LPC2000 5 Tutorial With Keil Tools The ULINK JT AG can also be used to program external flash devices This can be achieved as follows Open the options for target utilities window and add the file flash ini as shown below Options for Target phyCore LPC229x Device Target Dutput Listing C Asm L Misc L Locate Debug Utilities Configure Flash Menu Command f Use Target Driver for Flash Programming ULINK ARM Debugger Settings W Update Target before Debugging Irit File AFlash ini El Edit Use External Tool for Flash Programming Command Lett mil Arguments HH Cancel Defaults This is a script file that is used by the ULINK JTAG to configure the necessary chipselects to allow code to be programmed into the external flash and as such should reflect the values used in the startup code Next select the settings button and you can add the flash algorithm to match the external device used Flash Download Setup r Download Function RAM for Algorithm Logo Erase Ful Ehip jw Progra
17. Parameter DARMP DLL pLPC21x3 TARMP DLL pLPC21x3 Cancel Defaults Select OK to complete the target options In the project browser expand the targetl root node to show the source group 1 folder Z xl ESQ Target i Eg Source Group 1 130 Introduction to the LPC2000 5 Tutorial With Keil Tools Highlight the source group 1 folder open the local menu with a right click and select Add files to source group source groupl 2 15 Target 1 Select Device Far Target Target 1 Options for Group Source Group 1 Open File 19 Build target F7 Translate File Stop build Add Files to Group Source Group 1 Manage Components Remove Group Source Group 1 and it s Files Include Dependencies In the Add files to group dialog add the file blinky c and serial c Add Files to Group Source Group 1 2 Look in work cr E3 File name Files of type Ic Source file c Close 2 Change the Type of file filter to ASM and add the file startup s These are all the source files necessary for the project so select Close Notes 1 You can view the source code contained in a file by double clicking on the file name in the project browser window 11 The manage components project components option also allows you to customise your project by adding extra source groups and different b
18. Running from on chip FLASH is a performance bottleneck for all ARM7 implementations Philips have added a Memory Accelerator Module which greatly enhances the performance of the ARM7 CPU FLASH Q d Introduction to the LPC2000 3 System Peripherals One of the main constraints in designing a high performance single chip microcontroller based on the ARM7 is the access time to the on chip FLASH memory The ARM CPU is capable of running up to 830MHz however the on chip FLASH has an access time of 50 5 Consequently just running out of the FLASH would limit the execution speed to 20MHz a quarter of the possible clock rate of the processor There are a number of ways round this problem The simplest is to load the critical sections of your program into RAM and run out of RAM As the RAM has a much faster access time our overall performance will be greatly increased The down side is that on chip RAM is a finite and precious resource Using it to hold program instructions greatly limits the size of application code which we could run Another approach would be to have an on chip cache A cache is a small region of memory placed between the processor and memory store which stores regions of recently referenced main memory In a well designed cache the processor will use the cache memory whenever possible thus reducing the bottleneck imposed by slow memory However a full cache 1s a complex peripheral which demands a high num
19. This calculation has a lot of unknowns If we assume that we want to reach a bit rate of 125K with a 60 MHz Pclk and a sample point of about 70 here is how the BRP calculation is performed The total number of time quanta in a bit period is given by 1 Tseg1 Tseg2 If we call this term QUANTA and rearrange the equation in terms of the baud rate prescaler BRP Pclk Bit rate x QUANTA 110 Introduction to the LPC2000 4 User Peripherals Using our known values BRP 60 MHz 125K x QUANTA Now we know that we can have between 8 and 25 time quanta in the bit period so using a spreadsheet we can substitute in integer values between 8 and 25 for QUANTA until we get an integer value for BRP In this case when QUANTA 16 BRP 30 Then 16 Quanta 1 Tseg1 Tseg2 So we can adjust the ratio between Tsegl and Tseg2 to give us the desired sample point Sample point QUANTA x 70 100 Hence 16 0 7 11 2 This gives Tseg 1 10 Tseg2 5 and the sample point 68 8 The value for the synchronous jump width may be calculated via the following rule of thumb Tseg2 gt 5 Tq then program SJW to 4 Tseg2 5 Tq then program SJW to Tseg2 1 Tq In this case SJW 4 111 Introduction to the LPC2000 4 User Peripherals CAN Message Transmission In the LPC2000 each CAN controller has a number of status and control registers plus three transmit buffers and a receive buffer CAN CAN MOD Controls Operating Mo
20. if val 0x80 MAMCR 0 MAMTIM 0x03 MAMCR 0x02 else MAMCR 0x0 for delay 0 delay lt 0x100000 delay t simple delay loop 1 ChangeGPIOPinState FLASHer FLASHer ELASHer l if FLASHer amp 0x01000000 FLASHer 0x00010000 void ChangeGPIOPinState unsigned int state TOCLRI IOSETI clear output pins set output pins state state 49 set the state of the ports shift the active led Increment FLASHer led and test for overflow Introduction to the LPC2000 3 System Peripherals FLASH Memory Programming Although the internal FLASH is arranged as two interleaved banks you will be relieved to know that to the user it can be treated as one contiguous memory space and no special tools are required to prepare the code prior to programming the chip In terms of programming the FLASH to the user it appears as a series of 8K sectors which can be individually erased and programmed There are several methods which can be used to program the on chip FLASH The easiest is by the built in bootloader which allows your code to be downloaded via UART 0 into RAM and then be programmed into the FLASH It is also possible to use a JT AG development tool to program the memory This is useful during development because it can be done from the debugging environment without the need to keep switching between debugger and bootloader Also the JTAG connection can be very
21. in the next section The code below demonstrates how to receive a CAN message int main void VPBDIV 0x00000001 Set PClk to 60MHz TODIRI 0 00 0000 set all ports to output PINSEL1 0x00040000 Enable Pin 0 25 as CANI RX 1 0x00000001 Set CAN controller into reset 1 0x001C001D 5et bit timi g to 125k C1IER 0x00000001 Enable the Receive interrupt VICVectCntl10 0x0000003A select a priority slot for a given interrupt VICVectAddrO0 unsigned CANIIRQ pass the address of the IRQ finto the VIC slot VICIntEnable 0x04000000 enable interrupt AFMR 0x00000001 Disable the Acceptance filters 1 0x00000000 Release CAN controller while 1 118 Introduction to the LPC2000 4 User Peripherals void CANIIRQ void irg TOCLRI C1RDA clear output pins 1 CIRDA set output pins CICMR 0x00000004 release the receive buffer VICVectAddr 0x00000000 Signal the end of interrupt Acceptance Filtering While the receive example shown above will work perfectly well it suffers from two problems Firstly it receives every message transmitted on the bus In a fully loaded CAN bus this could mean a message would be received every 72us As the LPC2000 has up to 4 CAN controllers the CPU would have to spend a lot of time just managing the CAN busses Secondly once the message has been received the CAN controller would have to read a
22. time quanta i e a time slice A number of these time quanta are added together to get the overall bit timing L L L I CAN bit timing Unlike other serial protocols the CAN bit period is constructed as a number of segments that allow you to tune the CAN data transmission to the channel being Bit Time _ used f Sync Sample Seg Point The bit period is split into three segments First is the sync segment which is fixed at one time quanta long The next two segments are Tsegl and Tseg2 where the user defines the number of time quanta in each region The minimum number of time quanta in a bit period is 8 and the maximum is 25 The receiving sample point is at the end of Tsegl so changing the ratio of Tsegl to Tseg2 adjusts the sample point This allows the CAN protocol to be tuned to the transmission channel If you are using long transmission lines the sample point can be moved backwards If you have drifting oscillators you can bring the sample point forward In addition the receivers can adjust their bit rate to lock onto the transmitter This allows the receivers to compensate for small variations in the transmitter bit rate The amount that each bit can be adjusted 1s called the synchronous jump width and may be set to between 1 4 time quanta and 1s again user definable To calculate the bit timing the formula is given by Bit rate Pclk BRP x 1 Tsegl Tseg2 Where BRP Baud rate prescaler
23. 0x00000001 Disable the Acceptance filters StandardFilter 0 0x20012002 Setup the standard filter table StendardErltcerlil1 0x20032004 Lend 5539 amp 4 SEF 0x00000000 Set start address of Standard table SFF sa 0x00000008 Set start address of Standard group table EFF sa 0x00000008 Set start address of Extended table EFF sa 0x00000008 Set start address of Extended group table ENDofTable 0x00000008 Set end of table address AFMR 0x00000000 Enable Acceptance filters 1 0x00000000 Release CAN controller Exercise 26 CAN Receive Like the last exercise this example configures the CAN peripheral for 125Kbits sec and sets the acceptance filters to receive one of three message frames Summary This chapter is a bit of a moving target The LPC2000 is a rapidly growing family with new variants being released on a regular basis Check the CD that came with this book for a PDF update to this chapter or keep an eye on the web at http www hitex co uk arm Ipcbook If you have worked through this and the proceeding chapters you should now have a firm grasp of the LPC2000 family the ARM7 CPU and the necessary development tools Appendix B lists further reading and web resources for the ARM7 and the LPC2000 in particular 122 Introduction to the LPC2000 4 User Peripherals 123 Introduction to the LPC2000 5 Tutorial With Keil Tools Chapter 5 Keil Tutorial
24. 2 RAM ei 5 RAM 7 3 RAM 71 H5 RAM vil Cancel Defaults Help In the LA Locate tab make sure that the Use memory layout from target dialog box is ticked 129 Introduction to the LPC2000 Options for Target Interworking 2 x Device Target Output Listing C Asm LA Misc LA Locate Debug Utilities V Use Memory Layout from Target Dialog Reserve C DATA 0x40000000 0x40003FFF x classes CODE f x x3FFFF CONST Dx0 Ox3FFFF E User classes User A Segments Linker T Thumb1 n control CASE string Cancel Defaults 5 Tutorial With Keil Tools In the debug tab select make sure the use simulator radio button is checked along with the Load application at startup and Go till main Options for Target Simulator Device Target Output Listing Asm LA Misc LA Locate Debug Utities Use Simulator Settings ULINK ARM Debugger Settings M Load Application at Startup NV Go till main Load Application at Startup Go til mainf Initialization File Initialization File Restore Debug Session Settings Restore Debug Session Settings Breakpoints v Toolbox M Breakpoints M Toolbox M Watchpoints amp PA Watchpoints M Memory Display M Memory Display CPU DLL Parameter Driver DLL Parameter SAR M DLL cLPC2100 SAR M DLL Dialog DLL Parameter Dialog DLL
25. ARM7 CPU All of the LPC2000 peripherals are connected to these two interrupt lines as we shall see later You should be careful when programming these two bits because in order to disable either interrupt source the bit must be set to 1 not as you might expect Bit 5 is the THUMB bit The ARM7 CPU is capable of executing two instruction sets the ARM instruction set which is 32 bits wide and the THUMB instruction set which is 16 bits wide Consequently the T bit reports which instruction set is being executed Your code should not try to set or clear this bit to switch between instruction sets We will see the correct entry mechanism a bit later The last five bits are the mode bits The ARM7 has seven different operating modes Your application code will normally run in the user mode with access to the register bank RO R15 and the CPSR as already discussed However in response to an exception such as an interrupt memory error or software interrupt instruction the processor will change modes When this happens the registers R R12 and R15 remain the same but R13 LR and R14 SP are replaced by a new pair of registers unique to that mode This means that each mode has its own stack and link register In addition the fast interrupt mode FIQ has duplicate registers for R7 R12 This means that you can make a fast entry into an FIQ interrupt without the need to preserve registers onto the stack Each of the modes except user
26. Alarm Minute Alarm Hours Hour Alarm l The RTC is a clock calendar with Interrupt available Day of month Day of month Alarm alarm valid up until 2099 on increment of register value Day of week Day of week Alarm Day of year Day of year Alarm Month Month Alarm Year Year Alarm Interrupt on match The RTC clock runs on a standard 32 7KHz clock crystal frequency In order to derive this frequency the Pclk is connected to the reference clock divider In effect this 1s a prescaler whicht can accurately divide any Pclk frequency to produce the required 32KHz frequency PCLK 32 768 RTC Prescaler RTC Clock Logic The RTC watch crystal frequency may be derived from any value of Pclk PREINT PREFRAC To ensure that the RTC clock can be accurately derived from any Pclk the prescaler is more complicated than the general purpose timer prescalers The prescaler is programmed by two 85 Introduction to the LPC2000 4 User Peripherals registers called PREINT and PREFRAC As their name implies these hold integer and fractional divisor values The equations used to calculate the load values for these registers are as follows PREINT int pclk 32768 1 PREFRAC pclk PREINT 1 x 32768 So for a 30MHz Pclk PREINT int 30 000 000 32768 1 914 Then PREFRAC 30 000 000 91441 x 32768 17280 These values can be programmed directly into the RTC prescaler registers and the RTC is then ready to run
27. CONST z 0 7FFFF User ERAM O 40000000 0 40000F FF classes User sie Segments Linker TO interrupt x control CODE string Cancel Defaults Help The compiler does not check if your RAM function is calling functions or library functions which are not also stored in the RAM So if your fast RAM function makes calls to a maths routine stored in the FLASH memory you may not get the performance you were expecting This method of locating functions in RAM is not only simple and easy to use it has the added advantage that the linker knows where the function will finally end up and can place the debug symbols at the correct address This will give you not only a ROMable image which will run standalone but also an image which can be debugged Inline Functions It is also possible to increase the performance of your code by inlining your functions The inline keyword can be applied to any function as shown below void NoSubroutine void inline When the inline keyword is used the function will not be coded as a subroutine but the function code will be inserted at the point where the function is called each time it is called This removes the prologue and epilogue code which is necessary for a subroutine making its execution time faster However you are duplicating the function every time it is called so it is expensive in terms of your FLASH memory 37 Introduction to the LPC2000 2 S
28. Configure match 1 pin to clear on Match It is also set high for the first cycle TOEMR 0x00000042 In the interrupt set Match 1 output pin High TOEMR l 0x00000002 Compile and download the code into the debugger Run the code and observe the activity on GPIO pin 0 5 with an oscilloscope 167 Introduction to the LPC2000 5 Tutorial With Keil Tools Again we can see the configuration of the timer in the peripherals window x Prescaler Timer Interrupt Register 00000001E 000000001 E TCR t H IR ox00000000 PC 0 00000009 TC 0 00000000 Reset Match Channels Match on 0x10 MCR 0 00000003 EMR 0 00000042 MRO 0 00000010 MR1 0 00000008 2 0 00000000 MR3 000000000 v InteruptonMRO nterrupt on MRT InterruptonMR2 Interrupt on MR3 JV Reset on MRO Reset on MA1 Reset on MR2 Reset on l Match on 0x08 Stop on MRO Stop on MR1 Stop on MR2 Stop on MR3 Generate interrupt and reset EMCO Nothing EMCI Clear EMC2 Nothing EMC3 Nothing ExternalMatchO V External Match 1 EstemalMatch2 External Match 3 MRO Interrupt MET Interrupt MH2 Interrupt MF3lnterrupt Capture Ehannels CCR 0 00000000 CRO 0400000000 Chil 0 00000000 CR2 000000000 000000000 Rising Edge 0 Rising Edge 1 Rising Edge 2 Rising Edge 3 Falling Edge 0 Falling Edge 1 Falling Edge 2 Falling Edge 3 Int
29. Device Target Output Listing E Asm LA Misc LA Locate Debug Utilities W Use Memory Layout from Target Dialog The RESERVE command oo makes sure the first 64 bytes of on chip flash are C DATA 0 40000000 0 40003 Ox81000000 0 811FFFFF unused allowing the classes 0 80000000 CONST 0 80000000 external vector table to be mapped in The user User segments table allows E specific routines to be mapped on chip User m 0x40 Segments Linker TO Sim Hello control PRINT Sim Halla map CASE string Cancel Defaults Exercise 9 External Bus Interface This exercise shows the necessary changes to the project we set up in exercise 1 so that it will boot and run from external memory Phase Locked Loop The Phase Locked Loop is used to take an external oscillator frequency from between 10 MHz 25MHz from a fundamental crystal and multiply this frequency up to a maximum of 60MHz to provide the on chip clocks for the ARM7 CPU and peripherals This allows the LPC2000 to run at its maximum frequency with a low value external oscillator thus minimising the EMC emissions of the LPC2000 The PLL output frequency can also be changed dynamically allowing the device to throttle back its execution speed in order to conserve power when it 1s idling 10MHz 25 MHz 10MHz 60 MHz The PLL is used to CCLK multiply the external crystal frequency up to the
30. GB l OxFFFF FFFF AHB Peripherals 3 75GB OxF000 0000 VPB Peripherals 3 5 GB OxE000 0000 3 0 GB OxC000 0000 Reserved for External Memory The memory map of the LPC2000 includes regions for on chip flash memory user SRAM a pre 2 0 GB Boot Block 0x8000 0000 programmed bootloader external bus and user peripherals Reserved for On Chip Memory 1 0 GB 0x4000 0000 Ox3FFF 8000 Reserved for On Chip Memory 0 0 GB 0x0000 0000 The on chip flash 15 fixed at 0x00000000 upwards with the user RAM fixed at 0x4000000 upwards The LPC2000 is pre programmed at manufacture with a FLASH bootloader and the ARM real monitor debug program These programs are placed in the region 0x 7FFFFFF 0x8000000 The region between 0x8000000 and OxEO000000 is reserved for external memory Currently the LPC22xx devices are capable of addressing external memory via four chipselects each with a 16 Mbyte page System Control Block OxFFFF FFFF AHB Peripherals OxFFEO 0000 as Al the user peripherals are located on hoe oe the VLSI peripheral bus Each peripheral has a 16K address range for its s HE OxF000 0000 GPIO registers OxEFFF FFFF RTC 0xE020 0000 VPB Peripherals 01 0000 0xE000 0000 VVatchdog Timer Reserved The user peripherals located on the VPB are all mapped into the region between OxE000000 and OxE020000 and each peripheral is allocated a 16K memory
31. However in the ARM instruction set the top four bits of the operand are compared to the condition codes in the CPSR If they do not match then the instruction is not executed and passes through the pipeline as a NOP no operation 31 28 Every ARM 32 bit instruction is conditionally executed The top four bits are ANDed with the CPSR condition codes If they do not match the instruction is executed as a NOP COND So it 1s possible to perform a data processing instruction which affects the condition codes in the CPSR Then depending on this result the following instructions may or may not be carried out The basic assembler instructions such as MOV or ADD can be prefixed with sixteen conditional mnemonics which define the condition code states to be tested for 16 Introduction to the LPC2000 m i a m 2 clear 5 29 iun c C clear un Hd V clear aet and Z clear un GC clear and Z sel N equals V nat equal t Vv i I 5 5 a Z clear AMD M equals V Z s t OH M not equal to V ignored So for example EQMOV RI 0x00800000 equal nit equal unsigned higher or same unsigned lower negative or zero overflow na overflow unsigned higher unsigned lower or same greater or equal less than greater than less than or equal always 1 The ARM7 CPU Core Each ARM 32 bit instruction can be prefixed by
32. IRQ interrupt to allow further interrupts and switch to the system mode remember system mode is user mode but the MSR and MRS instructions work In system mode the new link register must again be preserved because it may have values which are being used by the background user mode code so this register is pushed onto the system stack also the user stack Once this 1s done we can run the ISR code and then execute a second macro that reverses this process The second macro restores the state of the link register Disables the IRQ interrupts and switches back to IRQ mode finally restores the SPSR irq and then the interrupt can be ended The two macros that perform these operations are shown below define IENABLE Nested Interrupts Entry asm MRS LR SPSR Copy SPSR irg to LR n asm STMFD SP LR Save SPSR_irg asm MSR CPSR c 0x1F Enable IRQ Sys Mode asm STMFD SP LR Save LR define IDISABLE Nested Interrupts Exit asm LDMFD SP LR Restore LR x asm MSR CPSR c 0x92 Disable IRQ IRQ Mode asm LDMFD SP LR Restore SPSR irg to LR asm MSR SPSR cxsf LR Copy LR to SPSR irq 75 Introduction to the LPC2000 3 System Peripherals The total code overhead 1s 8 instructions or 32 Bytes for ARM code and execution of both macros takes a total of 230 nSec This scheme allows any interrupt to interrupt any other interrupt If you need
33. R9 RIO R10 R13 is used as the stack pointer R14 is the link register R15 is the Program Counter R15 PC Current Program Status Register CPSR 1 Introduction to the LPC2000 1 The ARM7 CPU Core Current Program Status Register In addition to the register bank there 1s an additional 32 bit wide register called the current program status register CPSR The CPSR contains a number of flags which report and control the operation of the ARM7 CPU 31 30 29 28 27 8765 43 2 1 N Z C V Fir h 4131211 Interrupt enable Operating mode Condition code flags IRO FIO Negative FIO IRO Q Thumb instruction set Q Zero System Carry User oVerflow Undefined instruction The Current Program Status Register contains condition code flags which indicate the result of data processing operations and User flags which set the operating mode and enable interrupts The T bit is for reference only The top four bits of the CPSR contain the condition codes which are set by the CPU The condition codes report the result status of a data processing operation From the condition codes you can tell if a data processing instruction generated a negative zero carry or overflow result The lowest eight bits in the CPSR contain flags which may be set or cleared by the application code Bits 7 and 8 are the I and F bits These bits are used to enable and disable the two interrupt sources which are external to the
34. SPCCR 0x000000FF S SPCR 0x000000A0 Kick off an SPI transfer SPI_write output_buffer 8 Use a case statement for each state of the transaction case 0x01 Send Write opcode SOSPDR 0x00000005 status 0x02 set next state break Compile the code and start the simulator Set a breakpoint on the switch statement in the SPI ISR Run the code and examine the state of the virtual EEPROM memory and the debug output in the message window 176 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 23 Analog To Digital Converter In this exercise we will configure the A D in hardware mode and do an 8 bit conversion on channel 0 The results are modulated onto the LED pins Open the A to D project in C work EX20 AtoD Program the ADCR to give hardware conversion on channel zero 8 bits resolution Adjust the A D clock for a PcIk of 30 MHz ADCR 0x00270601 Test the done bit in ADDR to find a finished conversion while val amp 0x80000000 0 Compile the code and load it into the debugger If you are using the target board turning the potentiometer will change the analogue value analogue channel 0 If you are using the simulator the peripheral window will allow you to simulate external voltages A D Converter x A D Control ADCR 0x01 270601 SEL Ox jv PDN v BURST CLKS 8clk 7bi v cp ox0e EDGE START Now A D Rate 4285714 A D Data ADDR 10 00004 00 CHW n
35. Target menu In the CC tab uncheck the use THUMB code box and the default instruction set will be ARM Options for Target MAM Ak x 31 xl Device Target Output Listing C Asm LA Misc LA Locate Debug Utilities Preprocessor Symbols Define Undefine Code Optimization Warnings waminglevel 2 Level 7 Common tail merging V treat plain char as unsigned Emphasis l d r Era v Use Thumb Mode double precision floating point Bits to round for float compare 3 Include Paths LJ Misc PO Controls Compiler OPTIMIZE SIZE BROWSE DEBUG TABS 4 control string xl v Alias checking on pointer accesses Cancel Defaults Introduction to the LPC2000 2 Software Development In addition the programmer can force a given function to be compiled as ARM or THUMB code This is done with the two programming directives Pragma ARM and pragma THUMB as shown below The main function is compiled as ARM code and calls a function called THUMB function No prizes for guessing that this function is compiled in the 16 bit instruction set pragma ARM Switch to ARM instructions int main void while 1 THUMB_function Call THUMB function pragma THUMB Switch to THUMB instructions void THUMB function void unsigned long i delay for i 0x00010000 i lt 0201000000 21 i lt lt 1 LED FLASHer for delay
36. Text start as select the linker file RAM Id In the debug tab make sure the Use Simulator radio button is active Also make sure Load Application at Startup and Go till main are checked Options for Target Simulator Device Target Output Listing C Asm L Misc LA Locate Debug Utilities Use Simulator Settings C Use Settings Iv Load Application at Startup v Go till mainf Load Application at Startup Go til maini Initialization File Initialization File gil Edit i Edit Restore Debug Session Settings r Restore Debug Session Settings Breakpoints iw Toolbox Breakpoints iv Toolbox lv w atchpaints amp PA Watchpoints v Memory Display W Memory Display CPU OLL Parameter Driver DLL Parameter SARM DLL cL PC21 00 SARM DLL Dialog DLL Farameter Dialog DLL Farameter DARMP DLL TARMP DLL pLPC21 3 Cancel Defaults Select OK to complete the target options In the project browser expand the Targetl root node to show the Source group 1 folder z xi 1 253 Target 1 E sg Source Group Highlight the Source Group 1 folder open the local menu with a right click and select Add Files to group Source Groupl E Target 1 3 source Group 1 Select Device For Target Target 1 Options for Group Source Group 1 Open File Build ta
37. VICVectAddr 0x00000000 Compile the code and start the debugger Run the code and check that the interrupt is entered correctly and that it only runs once for each press of the EINTI button pin 0 14 If you are using the simulator open the GPIO Port 0 peripheral window The interrupt can be triggered by bringing pin 0 14 low Alternatively open the toolbox and use the Generate EINTI button In the simulator use the cycle counter in the register window calculate how long the device takes to enter to the first line of your code in the interrupt routine 162 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 14 Nested Interrupts In this exercise we will setup two interrupt sources First timerO which sets a port pin high for the duration of the interrupt and secondly external interrupt one which also sets a second port pin high for the duration of the interrupt Under normal operation both interrupts would block each other while they are running However by adding the appropriate macros to the External interrupt routine we can allow the timer interrupt to interrupt the external interrupt routine so it will be guaranteed to run every 10ms This can be observed on the LEDS on theMCB2100 or in the logic analyser of the simulator Open the project in EX14 Interrupt Non Vectored work In Main c complete the two IENABLE and IDISABLE macros define IENABLE Nested Interrupts Entry asm MRS LR SPSR Lr Copy SPESE Lr
38. a very simple program to run in the ARM 32 bit instruction set and call a 16 bit thumb function and then return to the 32 bit ARM mode Open the project in C work EX3 Thumb code In main c complete the function declarations for the main function and thumb function as follows void main void arm void thumb function void thumb Nb use double underscore Again in the file browser select the root target Flash and in the local menu options for target In the C tab you can select the global instruction set by checking or unchecking the use thumb mode box It 1s also possible to define the instructions set to be used for a C module by checking or unchecking the same flag in the local C options menu for the C module Options for Target Interworking E i x Device Target Output Listing C Asm L Mise LA Locate Debug Utilities Preprocessor Symbols Detine Lindefine r Code Optimization Level Loop strength reduction Emphasis Favor execution speed W Use Thumb Made Warnings waminglevel 2 v treat plain char as unsigned char double precision floating point v Alias checking on pointer accesses Include 20 1 Paths E Misc Controls Compiler OPTIMIZE 7 SPEED BROWSE DEBUG TABS 4 control string x Cancel Defaults Help Compile and download the code into the debugger Open the disassembly window and single step throu
39. and the chipselect gated with A23 to provide a chipselect for each half of the memory page 55 Introduction to the LPC2000 3 System Peripherals 0x81000000 CS0 A23 Four devices with 2 M x16 bit can be arranged as a linear 4M x 32 bit address space The address line A23 and CSO 0 80800000 are used to decode between the two different banks C50 A23 0x80000000 The RAM is interfaced to the address bus in a similar fashion using Chipselectl except the devices are 1 Mbyte in size so we are using A2 to A21 Further devices can be mapped in by multiplexing A22 and A23 with the chipselect line As this is a RAM device and we may want to access it word half word or byte wide we can use the byte lane pins to allow access to the upper and lower bytes in each device J400 2 Finally the boot pins D26 and D27 must be pulled low if we want to boot from the external device 56 Introduction to the LPC2000 3 System Peripherals Using The External Bus Interface Each chipselect has a fixed address range and has a dedicated bus configuration register BCFGO0 BCFG3 The address range of each chipselect is shown below 8000 0000 80FFF FFFF 8100 0000 81FFF FFFF 8200 0000 82FFF FFFF 8300 0000 83FFF FFFF In our hardware example above we have mapped the FLASH onto chip select O at Ox80000000 and the ram onto chipselect 1 at 0 81000000 Before we can use the external memory we must setup the chipselect configuration
40. enable the MAM so that all sequential code is fetched from it but branches and constant data stored in the FLASH are accessed directly from the FLASH Finally the MAM may be fully enabled so that it fetches all FLASH memory accesses from the MAM The reason for these modes 15 that like a cache code running from the MAM is not deterministic so we have the option to switch it off or reduce its impact if we need to guarantee the run time of our application code However even in its full operating mode the impact of the MAM is not as great as a cache It 1s possible to predict runtime performance particularly with the use performance analysis features in development tools To help with this analysis and also to gauge the effectiveness of the MAM there are a group of statistical registers which can be used to measure the MAM s performance Statistical Status Register The MAM has some statistics registers Counter which show the number of accesses to the FLASH and the number of accesses to the MAM so the effectiveness of the MAM can be calculated All code amp data present in latches Flash Access Counter Statistical Control Register Introduction to the LPC2000 3 System Peripherals The Statistics registers are based around two counters which record the accesses made to the FLASH and the accesses made to the MAM buffers The statistical control register can further refine the type of access which will cause the counte
41. fast up to 400Kbytes sec download so in large applications particularly those using external FLASH memory it can be the best method of production programming Finally it is also possible to reprogram sections of the FLASH memory under command of the application already on the chip This in application programming can use any method to load the new code onto the chip SPI CAN I2C and then load it into a given section of FLASH So there is an easy to use mechanism which allows field updates to your application Memory Map Control Before looking at the operation of the bootloader we must first understand the different memory modes available on the LPC2100 As we have seen the ARM7 interrupt vector table and its constants table take up the first 64 bytes of memory In the LPC2000 these first 64 bytes may be mapped from a number of locations depending on the mode set in the MEMM AP register It is important to note that these modes have nothing to do with the ARM7 operating modes The MEMMAP register allows you to select between boot mode FLASH mode RAM mode and External memory mode When selected a new vector table will be mapped into the first 64 bytes of memory So for the RAM mode the contents of 0x4000000 0x400003F will be mapped to the start of memory This allows a program to be loaded into RAM starting at 0x4000000 and the vector table can then be redirected thus allowing the program and its interrupts to run in RAM This mode is norm
42. fiq language extension Before exiting the ISR the peripheral flag is cleared VO TIE Vordi nd 1 OxOOFF0000 Set the LED pins EXTINT 0x00000002 Clear the peripheral interrupt flag Exercise 11 FIQ interrupt This exercise sets up the VIC to respond to an external interrupt line as a FIQ exception 69 Introduction to the LPC2000 3 System Peripherals Vectored IRQ If we have one interrupt source defined as an FIQ interrupt all the remaining interrupt sources must be connected to the remaining IRQ line To ensure efficient and timely processing of these interrupts the VIC provides a programmable hardware lookup table which delivers the address of the C function to run for a given interrupt source The VIC contains 16 slots for vectored addressing Each slot contains a vector address register and a vector control register Vector Address Default Vector Address Vector Address 0 For a Vectored IRQ the VIC provides a hardware lookup table for the address of each ISR The interrupt priority Vector Address 15 of each peripheral may also be controlled Vector Control 0 Vector Control 15 The Vector Control Register contains two fields a channel field and an enable bit By programming the channel field any interrupt channel may be connected to any given slot and then activated using the enable bit The priority of a vectored interrupt is given by its slot number the lower the slot number the more im
43. for the compiler you plan to use Finally install the Philips ISP flash programming tool Once the software has been installed you are ready to start the tutorial exercises 124 Introduction to the LPC2000 5 Tutorial With Keil Tools Using the Keil UVISION IDE This section will cover the development tools that can be used to develop code for the LPC2000 In this book all the example are written for the Keil ARM toolset The Keil toolset comprises of the UVISION IDE which contains an editor and project manager an ARM7 Compiler and linker and a Software simulator The simulator will simulate the ARM7 core and the LPC2000 peripherals so it is possible to see the full operation of the chip by just using the simulator An evaluation version of the toolset is available free from the Keil website at www keil com or on the CD supplied with this book It 1s also possible to purchase a starter kit which contains an evaluation board and JT AG debugger that allows you to develop code on a real target device The Keil ARM compiler allows us to write in the C language and compile code to run on the LPC2000 devices In order to cope with the microcontroller architecture the compiler has a number of non ANSI extensions that allow us to handle features such as interrupts ARM Thumb interworking and accessing device peripherals Before we start its worth looking at a simplified memory map of an LPC2000 so we can understand how to build a project OxXFFFF FF
44. hazards such as read before write seen in pipelines with more stages The pipeline has hardware independent stages that execute one instruction while decoding a second and fetching a third The pipeline speeds up the throughput of CPU instructions so effectively that most ARM instructions can be executed in a single cycle The pipeline works most efficiently on linear code As soon as a branch is encountered the pipeline is flushed and must be refilled before full execution speed can be resumed As we shall see the ARM instruction set has some interesting features which help smooth out small jumps in your code in order to get the best flow of code through the pipeline As the pipeline 1s part of the CPU the programmer does not have any exposure to it However it 1s important to remember that the PC is running eight bytes ahead of the current instruction being executed so care must be taken when calculating offsets used in PC relative addressing For example the instruction 0x4000 LDR PC PC 4 10 Introduction to the LPC2000 1 The ARM7 CPU Core will load the contents of the address PC 4 into the PC As the PC 1s running eight bytes ahead then the contents of address Ox400C will be loaded into the PC and not 0x4004 as you might expect on first inspection Registers The ARM is a load and store architecture so in order to perform any data processing instructions the data has first to be moved from the memory store into a central se
45. if you are running from external FLASH you are stuck with the access time of the external FLASH One trick is to boot the executable code into fast RAM and then run from this RAM This means that you need to compile position independent code which can be copied into the RAM or compile code so that it runs in the RAM and is loaded by a separate bootloader program Both of these solutions will work but require extra effort to develop Fortunately the Keil compiler has a directive which defines a function as a RAM function The startup code will copy the function into RAM and the linker will resolve all calls to it as being located in the defined RAM area The function declaration is shown below int RAM FUNCTION int my VAR _ ram j It is also necessary to define which section of memory will be used to hold these functions This is done by declaring a section of the RAM as executable RAM or ERAM This declaration makes use of the classes directive to allocate a region of RAM to contain all the executable RAM functions 36 Introduction to the LPC2000 2 Software Development The basic syntax is shown below ERAM 0x40000000 0x40000FFF This entry should be made in the LA Locate dialogue of the options for target menu Device Target Output Listing i Asm LA Mise LA Locate Debug Utilities v Use Memon Layout from Target Dialog Feserve C DATA 0 40000000 0 40007 x classes CODE Ox0 0x7FFFF
46. in text files The script used to simulate the pulse is shown below signal void Toggle void PORTO PORTO 0x4000 twatch 200 PORTO PORTO 0x4000 KILL BUTTON 5 DEFINE BUTTON GenerateEINT1 Toggle This script is stored in the file signal ini and is added to the project in the debug window For more details on the scripting language see the uVISION documentation 194 Introduction to the LPC2000 6 Tutorial With GNU Tools Exercise 6 Software Interrupt In this exercise we will define an inline Assembler function to call a software interrupt and place the value 0x02 in the calling instruction In the software interrupt SWI we will decode the instruction to see which SWI function has been called and then use a case statement to run the appropriate code Open the project in EX6 SWINwork In main c add the following code As the first instruction 1n main add the assembler define which calls the swi instruction define SoftwareInterrupt2 asm swi 02 In the SWI ISR complete the register definition to access R14 register unsigned link ptr asm rli4 Complete the code to pass value of the SWI ordinal into the temp variable temp link ptr 1 amp OxOOFFFFFF Compile and download the code into the debugger Step the code and observe the SWI being serviced In the disassembly window the first SWI instruction has been encoded with the value 1 at location 0x0000015C 42 sattwarelInterrupt
47. instruction In the SWI ISR routine we can examine the SWI instruction with the following code pseudo code switch R14 4 amp OxOOFFFFFF roll back the address stored in link reg by 4 bytes Mask off the top 8 bits and switch on result case SWI 1 Depending on your compiler you may need to implement this yourself or it may be done for you in the compiler implementation 22 Introduction to the LPC2000 1 The ARM7 CPU Core MAC Unit In addition to the barrel shifter the ARM 7 has a built in Multiply Accumulate Unit MAC The MAC supports integer and long integer multiplication The integer multiplication instructions support multiplication of two 32 bit registers and place the result in a third 32 bit register modulo32 A multiply accumulate instruction will take the same product and add it to a running total Long integer multiplication allows two 32 bit quantities to be multiplied together and the 64 bit result is placed in two registers Similarly a long multiply and accumulate 1s also available Mnemonic MUL MULA UMULL UMLAL SMULL SMLAL Meaning Multiply Multiply accumulate Unsigned multiply Unsigned multiply accumulate Signed multiply Signed multiply accumulate 23 Resolution 32 z 64 64 64 64 DIE pit pit DIE pit Dic result result result result result result Introduction to the LPC2000 1 The ARM7 CPU Core THUMB Instruction Set Although the ARM7 i
48. interrupt is generated and 0x28 will be in the status register if the transfer was successful If it failed and had a NACK the code will be 0x20 and the byte must be sent again So as each byte is transferred an interrupt is generated the status code can be checked and the next byte can be sent Once all the bytes have been sent the stop condition can be asserted by writing to the I2C control register and the transaction is finished The I2C interrupt is really a state machine which examines the status register on each interrupt and performs the necessary action This is easy to implement as a switch statement as shown below 96 Introduction to the LPC2000 4 User Peripherals void I2CISR void I2C interrupt routine switch L29TAT Read result code and switch to next action case 0x08 Ji Stare bit IZCONCLR 0x20 Clear start bit I2DAT I2CAddress Send address and write bit break case 0x18 Slave address W ACK I2DAT I2Cdata Write data to tx register break case 0x20 Slave address W Not ACK I2DAT I2CAddress Resend address and write bit break case 0x28 Data sent Ack I2CONSET 0x10 Stopb condition break default break T2CONCLR 0x08 Clear 12C interrupt flag VICVectAddr x00000000 Clear interrupt in j This example sends a single byte but could be easily modified to send multiple bytes Additional case statements may be added to handle a master request for data
49. is a IM by 16 bit static RAM Both these devices are designed for low power applications and the programming algorithm is supported by the ULINK JTAG interface The FLASH is connected to Chipselect 0 and the RAM is connected to Chipselect 1 The schematic for each Chipselect is shown below VDD_V3V3 A D14 D15 A 1 R301 WP ACC F NC P017 1 1300 J1X2 J37 default open Two of the 29LV320DT devices are arranged as 16 bit wide memories to give a 2M page of 32 bit wide FLASH memory The byte pin is pulled high on each device to enable the 16 bit mode The FLASH device is designed to be a boot sector device and consequently has an option to protect the top and bottom sectors so that they cannot be corrupted This feature 1s enabled by pulling the IWP ACC pin low Since we do not want this feature the pin is pulled high allowing us to reprogram any sector of the FLASH memory We are also not using the Ready Busy output so this 1s also tied high The remaining control signals reset Output enable OE Write Enable WE and Chip Enable are connected directly to the processor As the memory is to be arranged word wide 32 bits we need to be able to address it every quad bytes hence AO and A1 are not used If it is necessary to add more memory onto this chipselect the 29L V320 can be replaced with a XXX to give a 4M page of word wide memory To access the full 16 Mbyte address range a duplicate pair of devices can be added
50. mode has an additional register called the saved program status register If your application is running in user mode when an exception occurs the mode will change and the current contents of the CPSR will be saved into the SPSR The exception code will run and on return from the exception the context of the CPSR will be 12 Introduction to the LPC2000 1 The ARM7 CPU Core restored from the SPSR allowing the application code to resume execution The operating modes are listed below System amp User FIQ Supervisor Abort IRQ Undefined Ro FP RO RO RO RO R1 R1 R1 R1 R1 2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 RA R4 R4 R4 R4 R4 The ARM CPU has six operating modes R5 R5 R5 R5 R5 R5 which are used to process exceptions The Re R6 ifu IT 00 Re Re 1 shaded registers are banked memory that is I Bum switched in when the operating mode changes The register is used to save a R8 R8 R amp Re R8 copy of the CPSR when the switch occurs RQ R9 Ra Rta iq RIS PC R15 CPSR CPSR CPSR 1 lt SPSF a Exception Modes When an exception occurs the CPU will change modes and the PC be forced to an exception vector The vector table starts from address zero with the reset vector and then has an exception vector every four bytes Each operating mode has an associated interrupt ve
51. page Finally the Vector Interrupt Unit is located at the top of the address range at OxFFFFFOOO 44 Introduction to the LPC2000 3 System Peripherals If your user code tries to access memory outside these regions or non existent memory within them an abort exception will be produced by the CPU This mechanism is hardwired into the design of the processor and cannot be changed or switched off Register Programming Before we start our tour through the system block it is worth noting how Special Function Registers SFR are programmed on ARM chips As a general rule all Special Function Registers originating from ARM are controlled by three registers a Set Status Clear and Status register NB To clear bits you must write a logic Set 1100 SFR 1 to the relevant bit in the clear EL register Clear Each underlying SFR is controlled by three user registers A Set register which is used to set bits a Clear register which is used to clear bits by writing a logic 1 to the bits you wish to clear and a Status register which is used to read the current contents of the register The most common mistake made when new to the LPC2100 is to write zero into the Clear register which has no effect Memory Accelerator Module The Memory Accelerator Module MAM is the key to the high instruction execution rate of the LPC2100 family The MAM is present on the local bus and sits between the FLASH memory and the ARM7 CPU 7
52. registers AT MW BM WP WP ERR BUSS ERR WST2 RBLE WST1 IDCY Se IDCY Controls the minimum number of idle cycles between read and write operations WSTI Controls the length or read accesses RBLE 0 for byte wide devices drives BLS signals high for 16 32 bit devices drives BLS signals low WST2 Controls the length of write accesses WPERR Setif software attempts to write to a memory bank WP Write protect once set write protects a bank BM Enables memory bank as a Burst ROM MW Detines the width of the data bus AT BUSS ERR ERR Not used Each of the chipselects in use must be programmed with the correct parameters to match the external device connected on to it In the case of the FLASH memory it has a 90ns read cycle so at 60M Hz with a cycle time of 16 ns we need 6 Cclk read waitstates with one idle cycle The FLASH is accessed word wide so RBLE is set to zero to disable the byte laning Each Chipselect may be configured 8 Bit with a busvvidth of 8 16 or 32 bits 16 Bit 32 Bit Reserved Introduction to the LPC2000 3 System Peripherals During normal operation the FLASH will not be written to so WST2 is set to zero Also the write protect may be set to detect accidental writes to the FLASH bank but during development it may be wise to set it to zero and disable write protect in case it interferes with the FLASH programming algorithm of the ULINK Finally the bus width is set to 32 bits This gives a configuratio
53. select the root target FLASH and in the local menu options for target 190 Introduction to the LPC2000 6 Tutorial With GNU Tools In the CC tab tick the enable APCS option and the support calls between THUMB and ARM Options for Target Flash T x Device Target Dutput Listing CC Assembler Linker Debug Utilities r Preprocessor Symbols Define Undetine Code Generation 7 Enable APCS ARM Procedure Call Standard Optimization lt defaut gt gi Generate Stack Check Code Warnings No Warnings v V Support Calls between ARM and THUMB Instruction Set Strict ANSI Compile Thumb Code Include Paths d Misc Controls Compiler control string c mcpuzarm tdmi gdwarf 2 MD w mapcs frame mthumb interwork C sKeil amp RMNINCSPhilipss 070 zi Cancel Defaults Help Compile and download the code into the debugger Open the disassembly window and single step through the code using the F11 key Observe the switch from 32 bit to 16 bit code and the THUMB flag in the CPSR El CPSA Ox 60000010 PA 36 thumh funstiogt 2 C 1 mrs V n 0200000198 000000 BL 000001 enn n Ox0O000019C EAFFFFFC B 0200000194 A F n 2000001 59 0 LDR Riz PC Es T n 0 12 1 BX Rl M 510 The processor is running in ARM 32 bit mode the T bit is clear and the instruct
54. set MATI pin high for first cycle TOTCR 0x00000001 Enable timer VICVectAddr4 unsigned T isr Set the timer ISR vector address VICVectCntl4 0x00000024 Set channel VICIntEnable 0x00000010 Enable the interrupt while 1 l Introduction to the LPC2000 4 User Peripherals void TOisr void LEG TOEMR 0x00000002 Set MAT1 high for beginning of the cycle TOIR 0x00000001 Clear match 0 interrupt VICVectAddr 0x00000000 Dummy write to signal end of interrupt Exercise 17 Timer Match This second timer exercise uses two match channels to generate a PWM signal there is some CPU overhead in the timer interrupt routine PWM Modulator At first sight the PWM modulator looks a lot more complicated than the general purpose timers However it is really an extra general purpose timer with some additional hardware The PWM modulator is capable of producing six channels of single edge controlled PWM or three channels of dual edge controlled PWM PWM1 The PWM module is a third general purpose time with additional hardware for dedicated PWM generation External Match Register Latch Enable Register Capture Control Register Capture Register O 4 Interupt Match 0 6 Capture 0 3 n the general purpose timers when a new value is written to a match register the new match value becomes effective immediately Unless care is taken in your software thi
55. should be used Exception source Constants table C function prototype Undefined Instruction Undef Handler A void Undef Handler void __ abort Prefetch Abort PAbt_Handler A void Pabt_Handler void __ abort Data Abort DAbt_Handler A void Dabt_Handler void __ abort Fast Interrupt FIQ Handler A void FIQ Handler void fig The SWI and IRQ exceptions are special cases as we will see later The A is used to tell the linker that the corresponding function should be compiled with the ARM instruction set T is used for the THUMB instruction set Only the IRQ and FIQ interrupt sources can be disabled The protection exceptions Undefined instruction Prefetch Abort and Data abort 34 Introduction to the LPC2000 2 Software Development are always enabled Consequently these exceptions must always be trapped If you do not declare a corresponding C function for these interrupt sources then the compiler will default to using a tight loop to trap any entry to these exceptions Pabt Handler Default handling of exceptions for B Pabt Handler which no C function has been declared Exercise 5 Exception Handling In this exercise we configure a C routine to be a simple interrupt and see it working in the debugger Later on we will see how the LPC2000 hardware is configured to service interrupts 35 Introduction to the LPC2000 2 Software Development Software Interrupt The Software Interrupt exception is a special case As we
56. table should contain the instruction to read the VIC vector address as follows Vectors LDR PC Reset_Addr LDR PC Under Addr LDR PC sw Adar LDR BC EADIE Addr LDR PC DAbt Addr NOP LDR PC IPC O0x0FFO Vector from VicVectAddr LDR PC FIQ Addr The C routines to enable the VIC and sever the interrupt are shown below void main void TODIRI 0x000FF000 Set the LED pins as outputs PINSELO 0x20000000 Enable the EXTINT1 interrupt VICVectCnt10 0x0000002F Select a priority Slot for a Given Interrupt VICVectAddrO unsigned EXTINTVectoredIRQ pass the address of the IRQ into Che VIC S Lort VICIntEnable 0x00008000 enable interrupt while 1 void EXTINTVectoredIRQ void irq TOSET1 Ox000FF000 Set the LED pins EXTINT 0x00000002 Clear the peripheral interrupt flag VICVectAddr 0x00000000 Dummy write to signal end terrupt 72 Introduction to the LPC2000 3 System Peripherals Exercise 12 Vectored interrupt This exercise uses the same interrupt source as in exercise 11 but this time the VIC is configured to respond to it as a vectored IRQ exception Non Vectored Interrupts The VIC is capable of handling 16 peripherals as vectored interrupts and at least one as an FIQ interrupt If there are more than 17 interrupt sources on the chip any extra interrupts can be serviced as non vectored interrupts The non vectored interrupt sources are served by a si
57. the differences between the Keil and GNU compilers This does beg the question of which compiler to use First of all the GNU compiler is free can be downloaded from the internet and is also included on the CD which comes with this book So why use an expensive commercial compiler Well before you embark on a full project it is worth looking at the table of benchmarks comparing some of the most popular C compilers available for the ARM CPU Dhrystone V2 1 Compiler Parameter Keil CA GNU ARM ADS BETA LEBE LEN Execution Speed uSeconds 15 8 Dhrystones sec 5g 382 4 Total Code Size bytes 2 266 Stack Size bytes 608 Total Data Size bytes 10 256 All tests were performed under identical conditions using the Keil pvision Simulator The ARM device used was a Philips LPZ2284 running at 60MHz in Thumb Mode Whetstone Compiler Parameter Keil CA GNU ARM ADS 2 LB Execution Speed seconds 0 195306 2 461430 0 268623 Whetstone KWIPS 3 846 Total Cade Size bytes 28 515 Stack Size bwtes 710 Total Data Size bytes 76 All tests were performed under identical conditions using the Keil pvision Simulator The ARM device used was a Philips LPC2294 running at 60MHz in Thumb Made 27 Introduction to the LPC2000 2 Software Development We can see from this simple analysis that the commercial compilers are streets ahead of the GNU tools in terms of code density and speed of execution The reasons
58. the values for PREINT and PREFAC Next enable the Seconds increment interrupt CHR 0x00000001 Set the Seconds alarm register for 3 seconds and enable the seconds alarm in the alarm mask register ALSEC 0x00000003 Program the Clock control register to start the RTC running CCR x00000001 In the interrupt routine test the interrupt location register to determine the cause of the RTC interrupt seconds increment or alarm if ILR amp O0X00000001 increment if ILR 42 0x00000002 Alarm In either case make sure the interrupt flag 1s cleared before exiting the interrupt ILR x00000001 increment ILR x00000002 Alarm Using either the simulator or the MCB2100 hardware prove the code works correctly Remember the simulator 1s not realtime and you have to use the Internal Sec counter in the register window to get timing information 172 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 20 UART In this exercise we will configure UARTI to transmit at 19200 baud 8 bits no parity on stop bit We will use the UART to echo characters sent to it from the simulator terminal window Open the project in EX13 UART work Configure the UART for 9600 Baud 8 N 1 with pelk 30MHz The actual achievable baud rate 1s 9664 1 LCR 0x00000083 1 DLL 0x000000C2 UART1 LCR 0x00000003 In getchar and putchar add the code to monitor the line status register a For Putchar while 14UART1 LSR amp
59. to an 12 EEROM 98 Introduction to the LPC2000 4 User Peripherals SPI Interface Like the I2C interface the SPI interface is a simple peripheral engine which can write and read data to the SPI bus but is not intelligent enough to manage the bus It is up to your code to initialise the SPI interface and then manage the bus transfers SPI Register Interface SCK Slave Select VPB SPI Us Daa O Periferal MISO Clock Counter MOSI Interrupt Flag SPI Interrupt The SPI peripheral has four external pins a serial clock pin slave select pin and two data pins master in slave out and master out slave in The serial clock pin provides a clock source of up to 400Kbits sec when in master mode or will accept an external clock source when in slave mode The SPI bus is purely a serial data connection for high speed data transfer and unlike I2C does not have any addressing scheme built into the serial transfer An external peripheral is selected by a slave select pin which is a separate pin Typically if the LPC2000 is acting in master mode it could use a GPIO pin to act as slave select chip enable for the desired SPI peripheral When the SPI peripheral is in slave mode it has its own slave select input which must be pulled low to allow an SPI master to communicate with it The two data transfer pins master in slave out and master out slave in are connected to the remote SPI device and their orientation depends o
60. to prioritise interrupt nesting then the macros would need to block low priority interrupts by disabling the lower priority interrupt sources in the VIC Exercise 14 Nested Interrupts OK one last interrupt exercise This exercise demonstrates setting a timer to generate a regular periodic interrupt which must run It also configures an interrupt which is triggered by Eint1 The external interrupt uses the above technique to allow the timer interrupt to run even if the external interrupt routine is active Summary This is the most important chapter in this book as it describes the system architecture of the LPC2000 family You must be familiar with all the topics in this chapter in order to be able to successfully configure the LPC2000 for its best performance and to avoid many of the common pitfalls which trap people new to this family of devices 76 Introduction to the LPC2000 4 User Peripherals 77 Introduction to the LPC2000 4 User Peripherals Chapter 4 User Peripherals Outline This chapter presents each of the user peripherals in turn The examples show how to configure and operate each peripheral Once you are familiar with how the peripherals work the example code can be used as the basis for a set of low level drivers General Purpose I O On reset the pin connect block configures all the peripheral pins to be general purpose I O GPIO input pins The GPIO pins are controlled by four registers as shown be
61. to the R input of the flip flop When the match is made the flip flop is reset and the PWM pin is set low This allows modulation of the PWM signal by changing the value of the dedicated match channel Match 0 Timer counter reset Match 1 PVVM2 Double Edge PVVM Match 2 Match 0 controls the period of the PVVM cycle Two match channels are used to modulate the pulse rise and fall times for each PVVM channel By reprogramm ng the multiplexer the output stage of the PVVM modulator can be configured to dual edge controlled modulation In this configuration Match O is not connected to any output and is used solely to reset the timer at the end of each PWM period In this configuration the S and R inputs to each flip flop have a dedicated Match channel At the beginning of a cycle the PWM output is low The rising edge of the pulse is controlled by the Match channel connected to the S input and the falling edge is controlled by the Match channel connected to the R input The example below illustrates how to configure the PWM module for dual edge PWM void main void PINSELO 0x00028000 Enable pin 0 7 as PWM2 PWMPR 0x00000001 Load prescaler 0x0000404 PWM channel 2 double edge control output enabled PWMMCR 0x00000003 On match with timer reset the counter PWMMRO 0x00000010 set cycle rate to sixteen ticks PWMMR1 0x00000002 set rising edge of PWM2 to 2 tick
62. 002 set 00000009 Set 00000000 Nothing 00000000 Nothing 00000000 Nothing 00000000 Nothing Selected Channel wv nterupt on MAD MRO 0x00000070 22 P EMCO Nothing gt v Match 0 Latch F Reset on MAO Extemal Match D MAO Interrupt Stop on MAO 15557 MCR 10400000003 10 00000280 LER 10400000007 10 00000404 The logic analyser can also be used to examine the activity on the PWM 1 pin This time the mask should be set to 0x00000080 Min Time Time Range Grid oor Code Export 0 002667 ms 10 35253 ms 10 00000 s 0 500000 us In Out Al Sel Show Oy port 00 gt gt 020 ps 10 34300 ms I i 1 I i I i 1 I I 1 I I 10 35200 ms 10 34800 ms 171 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 19 Real Time Clock In this exercise we will use all the major features of the real time clock The first step is to configure the reference clock to give 32 768 KHz We can then configure the counter increment registers to give an interrupt every second and the alarm registers to give an interrupt at 10 seconds External oscillator 12 00MHz Cclk 60 000MHz Pclk 30 000M Hz Calculate the value of PREINT using PREINT int pclk 32768 1 Answer 0x392 Calculate the value of PREFAC using PREFRAC Pclk PREINT 1 x32768 Answer 0x4380 Open the project in ex 16 RTC work In main c enter
63. 0x20 This line is used twice b For Getchar while UARTI_LSR amp 0 01 Compile and download the code into the debugger If you are using the MCB2100 hardware connect UARTI to the serial port of a PC and start Hyperterminal When you run the code enter characters in Hyperterminal and see them echoed back to the screen If you are using the simulator use the built in serial window to simulate a terminal serial window 2 173 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 21 I2C interface This exercise will demonstrate using the I2C interface to write and read back from a serial EEPROM of the type see the CD for the full datasheet Because the MCB2100 evaluation board is not fitted with such a memory a script file is used to simulate the EEPROM so we can test our routines and have them ready as soon as the hardware becomes ready Open the project in C work I2C The script file is in I2C 1ni and this is added to the project in Options for Target Debug Add the following lines to the C code Build the code and start the simulator Open the peripherals I2C window The I2C Hardware tab shows the configuration of the peripheral and the I2C communication tab will show all the bus transactions In this code the I2Ctransfer function starts the I2C bus transaction which 1s then handled by the I2C interrupt function The interrupt function is a state machine in the form of a case statement By setting a
64. 1 i30 To Line for sil Insert Remove Breakpoint 1 Jf Enable Disable Breakpoint 7707 7 Clear complete Code Coverage Info for fi 1 Add counter ba Wabkch Window count E m fiboCount Fibonacci counter In the Watch and call stack window counter 135 select the Watch 1 tab to view the contents of Introduction to the LPC2000 5 Tutorial With Keil Tools le lx Examine memory locations Open the memory window with view memory window Set the start of the memory window to 0x40000060 the address of the counter variable xi Ln Address 10 40000060 0 40000060 6 OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO Ox400000 2 OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO Ox40000084 OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO Ox40000096 OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO 0 400000 6 00 OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO Uz400000BA 00 OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO Ox400000CC OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO 0 4000000 OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO 0x400000F0 OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO Ox40000102 00 Ux40000114 View the device peripherals Open some of the windows under the Peripherals menu OF Reset CPU ectored Interrupt Controller VIC IntEnable System Control Black ra ve
65. CR 0x00000002 Configure capture channel 0 to capture on the rising edge TOCCR 0x00000005 Enable the timer TOTCR 0x00000001 In the interrupt routine copy the capture value into a dummy variable Value TOCRO Compile and load the code into the debugger Run the program and check the following Test the capture interrupt is working by setting a breakpoint on the timer ISR and running the code In the simulator a script has been added to the toolbox to generate a pulse on 0 02 If you are using the MCB2100 you need to pull the port pin up to Vcc via a 10K resistor 165 Introduction to the LPC2000 5 Tutorial With Keil Tools In the simulator check that the timer is incrementing at the required rate by single stepping until the timer increments and measuring the time interval with the clock in the register window Timer count TCR 0x0 v Enable Te 0 0003914F Reset Interrupt Register IR 000000010 Match Channels MCR 000000000 EMR 000000000 MRO ox00000000 MRT 000000000 MR2 o 00000000 MR3 0 00000000 Interrupt on MRO Reset on MRO Stop on MRO EMCO Nothing Interrupt on MR1 Reset on MA1 Stop on MR1 EMC1 Nothing Interrupt on MR2 Reset on MA2 Stopon MR2 EMC2 Nothing Interrupt on MR3 Reset on MR3 Stop on MR3 EMC Nothing External Match 0 External Match 1 MRO Interrupt ExternalMatch2 Extern
66. D R13 R11 R12 R14 PC R12 0000 l Ox000000FC E24CB004 SUB R11 R12 40x00000004 13 5 D 37 initFiq Initi R14 LR 38 R15 PC s 0x00000100 000011 BL initFiq 0x0000014C CPSR 39 while 1 8 m ee oso aS nala ee 0 00000104 20 MOV R3 DMOD 0xE0000000 id F id Fast intemupt ub b 0x00000108 E283390A ADD R3 R3 0x00028000 R8 0 000 0 00000100 E3A028FF MOV R2 40x00FFUO00 0000 Main Program Loop 41 IOCLR1 0 00 0000 RI 0000 R12 x0 R13 SP 400 int main void R14 LR 0 000 SPSR 000 nlerrupt initFiq FIQ Interrupt Service Routine 1 R14 0x000 51 void EXTintFIQ void 2 SPSR 000 Dipeiisd 0x00000110 E583201C STR R2 R3 40x001C Abort 0 00000114 EAFFFFFD B 0x00000110 Undefned 52 Internal 53 PC 0400 ox00000118 E92D000C STMDB R13 R2 R3 Mode Uset t States 52 Sec 0 0000 min manc A Dis lkembi Include N Archive Arm ARM CoursM Imege mb mea x IMAP 0x40000000 Ox4000ffff READ WRI ir 0 4000 58 6F AO BS FO FF 1F ES 18 FO Bile Disable BreakEnable BreakKi 50x 00000j 9E ES 58 00 00 00 40 00 00 00 pus Bux i Command Find in Fies Bunu 0 00000000 18 FO 9F ES 18 FO 9F E5 18 FO Command Line CPU Registers Memory Window Watch Window The code will
67. Dominant End Tm automaticaly genera End of Frame automatically generated which all previous bits ACK Delimiter 255 5 is a weighted polynomial stuff bits are not ene balda checksum that provides error CRC is calculated using detection and correction across included CRC Sequence the message packet Data Field Each message Data Length Code frame includes a reserved bit D 15 bit CRC i IDE bit D checksum RTR bit D Identifier Field Start of Frame Once a node has won arbitration it will start to write its message onto the bus As during arbitration as each bit 1s written onto the bus the CAN controller 1s reading back the level written onto the bus As the node has won arbitration nothing else should be transmitting so each bit level written onto the bus must match the level read back If the wrong level 1s read back the transmitter generates an error frame and reschedules the message The message 15 sent in the next message slot but must still go through the arbitration process with any other scheduled message Standard 8 byte Data Frame Inter Frame Space T 1 Recessive ENX N A N 0 Dominant Transmitting Intermission node expects bus End of Frame Bit check error state to be the 1 ACK Delimiter Once the arbitration has same as the state AC ACK Slot finished the write and read 7 0 CRC Delimiter back mechanism is use for 27v v777 CRC Sequence bitvvise error checking allow m
68. EINTI button pin 0 14 If you are using the simulator open the GPIO Port 0 peripheral window The interrupt can be triggered by bringing pin 0 14 low or use the Generate EINTI button in the toolbox Open the VIC peripheral window in the debugger and get familiar with its layout and how the VIC 1s configured Channel Source Name Type Vector ntEnable Rawint 4 5 Timer 1 IRG 00000000 E IRG 00000000 T 1 IRG 00000000 B Pu IRG 00000000 g 2 IRG 00000000 10 520 IR Each VIC slot is shown here 11 SPI IRG 00000000 12 PLL Lack PLOCK IRG 00000000 1 13 IRG 00000000 14 External Interrupt EINTU IAG 00000000 5 External Interrupt 1 iL 0 000001 20 1 1 16 External Interrupt EINT2 IRU 00000000 t t Selected Interrupt External Interrupt 1 e e OE m WiCWectAddd 0400000120 Details of the selected slot 4 Rawlnt are shown here VID ect amp ddr 000001 20 VILIntSelect o 00000000 0 00009000 WiCSoftint 0x00000000 ViEIntEnable p nonosoD0 viCIRGStatus 0 00008000 Global registers are shown VICES aftintClear 0 00000000 VICIntE nClr Jox00000000 VICFIO Status h t n t n here 160 Introduction to the LPC2000 5 Tutorial With Keil Tools In the simulator use the cycle counter in the register window calculate how long the device takes to en
69. Ext In serial c complete the putchar function so it writes a single character to the serial port n putbchar dint ch if ch anit while UOLSR amp x20 UOTHR CR while 1 UOLSR 8 x20 return UOTHR ch Compile the code and download it to the development board or simulator Connect COMO on the board to PC comm Port 1 and start hyperterminal with the configuration file in the exercise directory If you are using the simulator select view serial window 1 This opens a terminal window within the simulator that displays the UARTO output Run the code and check that the message appears on the terminal window 144 Introduction to the LPC2000 5 Tutorial With Keil Tools M4 printf p ision3 Serial 1 laj xj si File Edit View Project Debug Flash Peripherals Tools SVCS Window Help 81 xi Std 35 EEA X Qal uls lallmi li em m Hello World well its traditional 000000000 000000000 000000000 000000000 000000000 0x40003b70 000000000 000000000 Ux alas x DOO00030 H SPSR 0 00000000 User System Fast Interrupt Interrupt Supervisor Abort Undefined Internal 04000001 FE User States 1229123 Sec 0 02048752 B aju 199 18 X x x x Restricted Version with 16384 Byte Code Size Limit xse Currently used 1844 Bytes 11 x BS Nmain 44 31 ASSIGN BreakDisable BreakEnable BreakKill BreakList Bre
70. F I LI I Control Register LSB MSB X XxX The SPI data transmission can be configured to match the characteristics of any SPI device Control Register Each of these configuration features has a configuration bit in the control register and you must program these bits to match the SPI peripheral you are trying to communicate with Once the bit rate has been set and the control register configured then communication can begin To communicate with the SPI memory shown above first set the GPIO pin to enable the memory for communication Then writing to the SPI data register will send a byte of data and reading from the register will collect any data sent from the external peripheral The actual data format used in the transaction will depend on the SPI device you are trying to communicate with Exercise 22 SPI This exercise demonstrates how to configure the SPI peripheral and communicate with an external EEROM on the SPI bus 100 Introduction to the LPC2000 4 User Peripherals Analog To Digital Converter The A D converter present on some LPC2000 variants is a 10 bit successive approximation converter with a conversion time of 2 44 uSec or just shy of 410 KSps The A D converter has either 4 or 8 multiplexed inputs depending on the variant The programming interface for the A D converter is shown below Ain 0 ADCR A D Analogue to digital converter The converter is Ain 7 available with 4 or 8 channels of 10 bit re
71. FF Peripherals OxE000 000 0x4000 FFFF The memory map of the LPC21xx is a linear 40 GB address space with regions for on chip flash static Static Ram ram and peripherals 0x4000 0000 Flash 0x00001 FFFF Memory 0 Since the reset and exception vector table are located from zero upwards the on chip flash memory is located from zero for up to 256K The on chip SRAM starts at 0 40000000 for up to 64K and the on chip peripherals are mapped from OxE0000000 to the top of memory Before we begin to look at the compiler in detail I will run through a step by step tutorial on how to set up a UVISION project compile the code and run the debugger This does not cover all the features of uVISION but once you have a basic understanding of the IDE feel free to explore If you copy the example from the CD onto you hard disk the source files referred to below can be found in C examples ex1 first project Ok lets build our first project 125 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 1 Using the Keil Toolset This example 1s based on the source code that can be found in C Work EX1 first program In this first exercise we will spend some time defining a first project building the code and downloading it into the simulator for debugging We will then cover the basic debugging functions of the Keil simulator y Double click on the Keil Uvision3 icon to start the IDE Else g k sem petet pend Flas
72. I2Stat 0x08 Ox40 0x50 0x50 58 I2C master TX This bus transaction demonstrates a DATA DATA master to slave write transaction In the case of a master receive the start condition will be the same but this time the address written on to the bus will have the R W bit cleared When the acknowledge is received after the slave address 1s sent it will be followed by the first byte of data from the slave so the master does not have to do anything However in the case statement we can set the acknowledge bit so that an ACK is generated as soon as the byte has been transferred As each byte is transferred the data can be read from IDCDAT When all the bytes have been received the stop condition can be asserted and the transaction ends 977 Introduction to the LPC2000 4 User Peripherals The same I2CtransferByte function can be used to start a read transaction and the additional case statements required in the interrupt are shown below Case 0x40 Slave Address R ACK I2CONSET 0x04 Enable ACK for data byte break case 0x48 Slave Address R Not Ack I2CONSET 0x20 Besend Start condition break case 0x50 s Data Received ACK message I2DAT I2CONSET 0x10 OTOP On ET lock 0 Signal end of I2C activity break case 0x58 Data Received Not Ack I2OONSET 0x20 lI Resend Start condition break Exercise 21 12 This exercise demonstrates how to use the 2C interface to communicate
73. In THUMB mode we cannot program the high registers directly but we can move low registers to high registers hence we can move the contents of R2 directly into the program counter and initiate the requested In Application Programming routine When the TAP routine has finished it will return to your application code using the value stored in the link register which 1s the next instruction in the function which called our void IAP function You should also note that the In Application functions return in ARM mode not THUMB The IAP functions require the top 32 bytes of on chip RAM so you must either locate the stacks to start below this region so it 53 Introduction to the LPC2000 3 System Peripherals is unused or if you need all the RAM place the IRQ stack at the top of memory and disable interrupts before you enter the IAP routines Using a pointer you can now copy the top 32 bytes of on chip SRAM into a temporary array and then restore them once you return from the IAP functions This way you will not risk corrupting any stacked data External Bus Interface The LPC22xx variants have an External Memory Controller EMC When enabled the EMC provides four chipselects from 0x80000000 Each chipselect has a fixed 16Mbyte address range and a programmable wait state generation and can be programmed as an 8 16 or 32 bit wide bus As well as allowing additional memory and peripheral devices to be interfaced to the LPC22xx devices it 1s
74. Introduction to the LPC2000 2 Software Development describes the GNU version of the exercises up to exercise 6 After exercise 6 you can use the exercise descriptions in the main text As you read through the rest of the book at the end of each section there will be an exercise described in the tutorial section which illustrates what has been discussed The best way to use this book 1s to read each section then jump to the tutorial and do the exercise This way by the time you have worked through the book you will have a firm grasp of the ARM its tools and the LPC2000 microcontroller Exercise 1 Configuring A New Project The first exercise covers installing the uVISION software and setting up a first project Startup Code In our example project we have a number of source files In practice the c files are your source code but the file startup s is an assembler module provided by Keil As its name implies the startup code is located to run from the reset vector It provides the exception vector table as well as 1nitialising the stack pointer for the different operating modes It also initialises some of the on chip system peripherals and the on chip RAM before it jumps to the main function in your C code The startup code will vary depending on which ARM7 device you are using and which compiler you are using so for your own project it is important to make sure that you are using the correct file The startup code for the Keil c
75. Just enable the clock in the clock control register and the time counters will start PREINT 0x00000392 Set RTC prescaler for 30 000 MHz Pclk PREFRAC 0x00004380 CCR 0x00000001 Start the RTC There are eight time counter registers each of which contains a single time quantity which can be read at any time In addition there are a set of consolidation registers which present the same time quantities in three words allowing all the time information to be read in just three operations Consolidation 0 DOW Hours Seconds The RTC consolidation registers allow all the clock calendar m information to be read in three Consolidation 1 Year Month words Consolidation 2 As well as maintaining a clock the RTC can also generate alarm events as interrupts There are two interrupt mechanisms You can program the RTC to generate an interrupt when any time counter register is incremented so you could generate an interrupt every second when the second counter is updated or once a year when the year counter is incremented The counter increment interrupt register allows you to enable an increment interrupt for each of the eight time counter registers The second method for generating an RTC interrupt is with the alarm registers Each time counter register has a matching Alarm register If the matching Alarm register is unmasked it is compared to the time counter register If all the unmasked alarm registers match the time counter registers
76. LPC2000 1 The ARM7 CPU Core Chapter 1 The ARM7 CPU Core Outline The CPU at the heart of the LPC2000 family is an ARM7 You do not need to be an expert in ARM7 programming to use the LPC2000 as many of the complexities are taken care of by the C compiler You do need to have a basic understanding of how the CPU is working and its unique features in order to produce a reliable design In this chapter we will look at the key features of the ARM7 core along with its programmers model and we will also discuss the instruction set used to program it This 15 intended to give you a good feel for the CPU used in the LPC2000 family For a more detailed discussion of the ARM processors please refer to the books listed in the bibliography The key philosophy behind the ARM design is simplicity The ARM7 is a RISC computer with a small instruction set and consequently a small gate count This makes it ideal for embedded systems It has high performance low power consumption and it takes a small amount of the available silicon die area The Pipeline At the heart of the ARM7 CPU 1s the instruction pipeline The pipeline is used to process instructions taken from the program store On the ARM 7 a three stage pipeline is used Instruction Fetch The ARM three stage pipeline has independent fetch decode and execute stages Decode Execute A three stage pipeline is the simplest form of pipeline and does not suffer from the kind of
77. M7 CPU Core cases First of all consider the SWI instruction In this case the SWI instruction 1s executed the address of the next instruction to be executed is stored in the Link register and the exception is processed In order to return from the exception all that is necessary is to move the contents of the link register into the PC and processing can continue However in order to make the CPU switch modes back to user mode a modified version of the move instruction is used and this is called MOVS more about this later Hence for a software interrupt the return instruction 1s MOVS RIS R14 Move Link register into the PC and switch modes However in the case of the FIQ and IRQ instructions when an exception occurs the current instruction being executed is discarded and the exception is entered When the code returns from the exception the link register contains the address of the discarded instruction plus four In order to resume processing at the correct point we need to roll back the value in the Link register by four In this case we use the subtract instruction to deduct four from the link register and store the results in the PC As with the move instruction there 1s a form of the subtract instruction which will also restore the operating mode For an IRQ FIQ or Prog Abort the return instruction 1s SUBS R15 R14 4 In the case of a data abort instruction the exception will occur one instruction after execution of the instructi
78. Microcontroller with Tk f 1 2129 256KB on chip Flash ROM with In System Programming ISP and In amp pplic 3 LPC2194 16KB RAM Vectored Interrupt Controller External Bus Controller z Two UARTs I2C serial interface 2 SPI serial interfaces J LPC2212 Two timers 7 capture compare channels d LPC2214 PWM unit with up to 5 PWM outputs P ER 8 channels 10bit ADC 2 CAN channels 3 LPC2294 Real Time Clock Watchdog Timer General purpose 1 0 pins a l 80 87 51 2 CPU clock up to 60 MHz On chip crystal oscillator and On chip PLL f P80 P87C52x2 3 P90 P97 54X2 3 P80 P87C58x2 3 PB C557E4 a o Cancel 185 Introduction to the LPC2000 6 Tutorial With GNU Tools In the project browser highlight the Targetl root folder and select the local menu by pressing the right mouse button In this menu select Options for Target mi GENE o Options For Target Target 1 Ben File Translate File GOO Files tu troup stzl v EET In the Target tab set the simulation frequency to 12 000 MHz Options for Target Target 1 In the Linker tab select the linker file flash ld and tick the Garbage collection and do not use standard startup files boxes m m kt ki Introduction to the LPC2000 6 Tutorial With GNU Tools Note To build the project so it will run within the on chip RAM of the LPC2100 device configure the
79. Next highlight the startup s file right click and select Options for file and select the ASM tab 153 Introduction to the LPC2000 5 Tutorial With Keil Tools Enter the EXTERNAL MODE symbol in the control directives box as shown below Options for File Startup s Properties Asm Conditional assembly control Symbols TERNAL MODE Reset Macra processa WM Standard Include Paths Misc Controls Assembler control string Iv Case sensitive symbols ESTERMAL MODE DEBUG PRINT physStartup lsr EP Cancel Defaults This will ensure the startup code is correctly built for an external boot Next in the graphical display of the startup code add the parameters necessary for the chipselect configuration Externa Memory Controller EMC Bank Configuration BCFGO IDCY Idle Cycles WST1 Wait States 1 WSTz Wail States 2 RBLE Read Byte Lane Enable WP Write Protect BM Burst ROM Mi Memory width Bank Configuration 1 1 IDCY Idle Cycles WST1 Wait States 1 WSTz Wail States 2 RBLE Read Byte Lane Enable WP Write Protect BM Burst ROM Pw memory Width Build the code and start the simulator 154 G TI 3 ni T m 3 X 7 32 bit Introduction to the LPC2000 In the disassembly window the PC 15 set to address 0x00000000 and no meaningful code has be
80. OPON os b s E 40 Even More mpomanru al maa eva bi guest dei iua dug ddabs 40 xuuibaMe t 40 Chapter 3 System Peripherals sc sccccsssssssesccosssesesescscsesessssnscossevessoscossseses 42 Cufinec M 42 Dus SUPUICOU EC c M 42 Memory WIAD mr Y 44 lest ruld cU uj 45 Memory Accelerator Module ee s s o rene SALAR a orae Paar a a eo eo eua p o rane E aera a eese erase 45 Example NIAM COBEISUE OUO m 49 FLASH Memory Propgrammlilpnj eeesuees e oes eue aa Ra Pee 50 Memory MI CONTO hyns recente daaa a datus oan aaa 50 51 Ehsan a 52 InApplicaton Programming EREE EDE DN M ne 53 External Bus Inter a3ce 2 9 2 270002 10 2 208 69 69022601 000200 SEE 54 External MemiOry MINES EET TM 54 Usine The External us Intenace A o rip e aia a o ie etta tont 57 From ROM eet m 58 AES kocked MB E n n 60 VLSI Peripheral Bus Diyider s l a 62 Example Code PLL And VPB 63 POWEE C OnD UOL E ni oii 64 LPC2000 eco reel soo eaa 66 Pin onnect DIOSR uci m m 66 External inferripiPins E ORE ue E uda 66 liitereupt DS CHU CCTs n E Retos pp eus Rid xD 67 ELO inicrir ptuuza TRES 68 I eavang An PIO
81. PIO pins A group of pins will be set as outputs and then each will be flashed sequentially Open the project in EX12 GPIONwork Add the include file for the LPC21xx SFR s include lt LPC21xx H gt Program the data direction register to enable pins 1 16 1 23 as output TODIRI OxOOFFO0000 Complete the ChangeGPIOPinState function to clear and set the relevant pins IOGLDRI IOSETI State state Compile the code and download it into the debugger Run the code on the MCB2100 to see the LED chaser If you are using the simulator step through the code and check it works by examining the state of the IO pins via the GPIO peripheral window 164 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 16 Timer Capture In this exercise we will use timer in a simple compare mode to measure the time between starting the timer and getting a rising edge on pin 0 02 Because the MCB2100 does not have a button on a capture channel to generate the pulse this exercise 1s based on the Simulator A target version is included but you would need to modify the MCB2100 hardware and observe the output on an oscilloscope Pclk 30 MHz Pclock tick 0 033MHz Open the project in EX18 Timer capture work In main c complete the code as follows Enable pin 0 2 as capture channel 0 PINSELO 0x00000020 Load prescaler with 1 micro second tick value TOPR 0x0000001E Reset timer counter and prescaler counter registers TOT
82. S instructions These instructions are disabled when the CPU is in MRS USER mode CSPR SPSR R15 The MSR and MRS instructions will work in all processor modes except the USER mode So it 1s only possible to change the operating mode of the process or to enable or disable 21 Introduction to the LPC2000 1 The ARM7 CPU Core interrupts from a privileged mode Once you have entered the USER mode you cannot leave it except through an exception reset FIQ IRQ or SWI instruction Software Interrupt The Software Interrupt Instruction generates an exception on execution forces the processor into supervisor mode and jumps the PC to 0x00000008 As with all other ARM instructions the SWI instruction contains the condition execution codes in the top four bits followed by the op code The remainder of the instruction is empty However it is possible to encode a number into these unused bits On entering the software interrupt the software interrupt code can examine these bits and decide which code to run So it is possible to use the SWI instruction to make calls into the protected mode in order to run privileged code or make operating system calls 31 28 27 24 23 The Software Interrupt Instruction forces the CPU into SUPERVISOR mode and jumps the PC to the SWI vector Bits 0 28 are unused and user defined numbers can be encoded into this space The Assembler Instruction SWI 3 Will encode the value 3 into the unused bits of the SWI
83. This allows any CAN controller to assert an error onto the bus as soon as the error is detected without having to wait until the end of a message Internally each CAN controller has two counters Reset and Configuration Error Active m Error counters The CAN controller moves betvveen a REC 127 or Ne number of error states that allovv a node to a REC 127 amp 128 x 11 recessive bits fail in an elegant fashion vvithout blocking the bus Error Passive 7 5 Bus Off r TEC gt 255 A REC Recessive Error Counter TEC Transmit Error Counter These are a receive error counter and a transmit error counter These counters will count up when receiving or transmitting an error frame If either counter reaches 128 then the CAN controller will enter an error passive mode In this mode it still responds to error frames but if it generates an error frame it writes recessive bits in place of dominant bits If the transmit error counter reaches 255 then the CAN controller will go into a bus off condition and take no further part in CAN communication To restart communication the CPU must intervene to reinitialise the controller and put it back onto the bus Both these mechanisms are to ensure that if a node goes faulty it will fail gracefully and not block the bus by continually generating error frames The LPC2000 CAN controllers have a number of error detection mechanisms First of all the current count of the transmit a
84. a to lR asm STMFD SE 41 Save SPSR irq asm MSR CPSR c 0x1F Enable IRQ Sys Mode asm STMFD SPI LR Save LR define IDISABLE Nested Interrupts Exit asm LDMED SP LR Restore LR asm MSR CPSR_c 0x92 Disable IRQ IRQ Mode asm LDMFD SP LR Restore SPSR Arg to LR _ asm MSR SPSR_cxsf LR 74 Copy to SPORLDISQ Add the two macros to the External interrupt service routine vOd EXINTOI ISR Cvyoud ord BX TENT 2 Clear EINT1 interrupt flag TENABLE allow nested interrupts 1 0x00010000 Switch on an LED delay 0x500000 wait a long time TO EEL 0x000 100003 FI Switch Off the LED disable interrupt nesting VICVectAddr 0 Acknowledge Interrupt Build the project and download it to the debugger If you are using the MCB2100 run the code at full speed One LED will flash for the period it is in the timer interrupt Press the INT1 button and the second led will illuminate for the longer period it is in the External interrupt routine However the timer led will continue to flash because the interrupt is not blocked If you are using the simulator the same behaviour can be observed using the logic analyser Remove the IDISABLE and IENABLE macros and observe the new behaviour 163 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 15 General purpose IO pins In this exercise we will use the G
85. able or disable this filter entry Finally the top three bits associates this filter entry with a particular CAN controller 31 29 26 16 Q Controller 25 Lower Identifier Bound Controller E Upper Identifier Bound The group standard identifier table uses the same format but two entries are used to define the upper and lower identifier address range for messages that are allowed to pass through the acceptance filter 31 29 28 g Controller Identifier The individual extended identifier table uses four bytes per entry as shown above The first 29 bits define the message identifier to be passed through the acceptance filter and the top three bits associates the filter entry with a particular CAN controller The group extended identifier table uses two words in the same format as the individual extended table to build up a start and end identifier values in the same fashion as the standard message group table 121 Introduction to the LPC2000 4 User Peripherals The following code shows how the acceptance filters may be configured for the basic CAN mode unsigned int StandardFilter 2 at xE0038000 Declare the standard acceptance filter table unsigned int GroupStdFilter 2 0xE0038008 Next the standard Group filter table unsigned int IndividualExtFilter 2 xE0038010 Nov the extended filter table unsigned int GroupExtFilter 2 at 0OxE0038018 Finally the Group extended filter table AFMR
86. access to all registers in the register file All data processing instructions have access to RO R7 these are called the low registers In the THUMB programmers model all instructions have access to RO R7 Only a few Low Registers instructions may access R8 R12 High Registers Restricted Access CcPSR 24 Introduction to the LPC2000 1 The ARM7 CPU Core However access to R8 R12 the high registers is restricted to a few instructions MOV ADD CMP The THUMB instruction set does not contain MSR and MRS instructions so you can only indirectly affect the CPSR and SPSR If you need to modify any user bits in the CPSR you must change to ARM mode You can change modes by using the BX and BLX instructions Also when you come out of RESET or enter an exception mode you will automatically change to ARM mode Reset BLX After Reset the ARM7 will execute ARM 32 bit instructions The instruction set can be exchanged at any time using BX or BLX If an exception occurs the exception execution is automatically forced to ARM 32 bit end of exception BX The THUMB instruction set has the more traditional PUSH and POP instructions for stack manipulation They implement a fully descending stack hardwired to R13 Push Ho H3 Pop Ho H3 Ro The THUMB instruction set has dedicated PUSH and POP instructions which implement a descending stack using R13 as a stack pointer
87. ady to use the ULINK JTAG in place of the simulator If you are in the JTAG debugger or simulator you must halt any running code and quit the debugger before you can rebuild the code or quit the project 139 Introduction to the LPC2000 5 Tutorial With Keil Tools Important Note for the following exercises All the following exercises have builds to be debugged in either the Keil Simulator or to be downloaded onto the MCB2100 target hardware and debugged via the ULINK JTAG debugger The root folder of the project will be named Simulator for the simulation version or Flash for the version built to be debugged on the hardware Only the debug options in the project are changed To switch between the two versions make the project workspace the active window right click and select manage components Components Environment and Books Project Components Folders E tensions Books Project Target 173 XIA G Groups LK tT Fies Flash C Source code Assembler Source code Set as Current Target Add Files tee In the project components tab select the project target you want either Simulation or Flash and click the Set as current target button In a real project this feature of uVISION allows you to setup several different builds of a project or have several different programs in a project which are part of one larger application 140 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 2 St
88. akSet BreakAccess COVERAGE DEFINE DIR fw rr a aij gt Ready 145 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 5 Simple interrupt In this exercise we will setup a basic FIQ interrupt and see it serviced Open the project in C work EX5 Interrupt In main c complete the definition of the FIQ Handler function to define it as the FIQ interrupt service routine void FIQ Handler void fiq In startup s complete the vector constants table to define EXTintFIQ as the FIQ ISR Startup PROC CODE32 Vectors LDR PC Reset Addr LDR PC Undef_Addr LDR PC SWI_Addr LDR PC PAbt_Addr LDR PC DAbt_Addr NOP Reserved Vector LDR PC PC 4 0OxOFF0 LDR PC FIQ Addr han em The FIQ interrupt vector the instruction loads the 775 a 25 address of the c routine into the PC Undef Addr DD Undef Handler SWI_Addr DD SWI Handler PAbt Addr DD PAbt Handler DAbt Addr DD DAbt Handler DD 0 Reserved Address IRQ Addr DD IRQ Handler FIQ Addr DE FIQ Handler A The constants table holds the address of the FIQ C routine Compile the code and download it onto the board Step through the code until you reach the while loop Set a breakpoint in the FIQ Handler function Press F5 to set the program running On the MCB2100 board press the INT button to generate the interrupt 146 Introduction to the LPC2000 5 Tutorial With Keil Tools If you want to see the entry and exit mechanisms to the exception it is best t
89. al Match 3 MET Interrupt MR2 Interrupt MR3 Interrupt Capture Channels CCR 000000005 Tim er va l ue at CRO o 000881 AF 1 0400000000 CR2 0400000000 CR3 0 00000000 b v Rising Edge Rising Edge 1 Cap ture event Falling Edge 0 Falling Edge 1 Rising Edge 2 Rising Edge 3 Falling Edge 2 Falling Edge 3 v Interrupt on Event 0 Interrupt on Event 1 Interrupton Event 2 Interrupt on Event 3 Jv CAPO O VT CAPUA v CRO Interrupt CR1 Interrupt CR2 Interrupt CR3 Interrupt 166 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 17 Timer Match In this exercise we will configure the timer to generate a single edge PWM signal using two match channels Match zero will be used to generate the total PWM period On match it will be used to reset the timer and generate an interrupt Match one will be used to create the duty cycle On match it will clear the external match one pin At the beginning of the cycle the interrupt will set the external match one pin high Open the project in EX18 Timer Match work In Main c complete the timer initialising code as follows Configure the pin connect block with P0 5 as MATI PINSELO I 0x00000800 Set match zero to reset the counter and generate an interrupt TOMCR 0x00000003 Set the PWM period to 16 msec TOMRO 0x00000010 Set the Match 1 to give a 50 duty cycle TOMRI 0x00000008
90. allows programming of the BAUD rate generators Word length select Stop bit select Parity enable Parity select Break control Divisor latch access bit In our example the character format is set to 8 bits no parity and one stop bit In the LCR there is an additional bit called DLAB which is the divisor latch access bit In order to be able to program the baud rate generator this bit must be set 90 Introduction to the LPC2000 4 User Peripherals The baud rate generator is a sixteen bit prescaler which divides down Pclk to generate the UART clock which must run at 16 times the baud rate Hence the formula used to calculate the UART baud rate is Divisor Pclk 16 x BAUD In our case at 30MHz Divisor 30 000 000 16 x 9600 approx 194 or xC2 This gives a true baud rate of 9665 Often it is not possible to get an exact baud rate for the UARTs however they will work with up to around a 5 error in the bit timing So you have some leeway with the UART timings if you need to adjust the Pclk to get exact timings on other peripherals such as the CAN bit timings The divisor value is held in two registers Divisor latch MSB DLM and Divisor latch LSB DLL The first eight bits of both registers holds each half of the divisor as shown below Finally the DLAB bit in the LCR register must be set back to zero to protect the contents of the divisor registers 16 owe UART baud rate Th
91. ally only used for debugging small programs FLASH mode leaves the first 64 bytes of user FLASH unchanged and is the normal mode for user applications Boot mode replaces the first 64 bytes of FLASH with the vector table for the bootloader and places a jump to the on chip bootloader on the reset vector 1 2 3 0 0x40 0x00000040 0x40000040 0 80000040 00 00000040 0x00000000 0x40000000 0 80000000 ONCHIP USER RAM EXTERNAL BOOTLOADER FLASH FLASH MODE FLASH MODE MODE MODE 50 Introduction to the LPC2000 3 System Peripherals Bootloader Every time the LPC2000 comes out of reset its memory map will be in boot mode so the instruction on the reset vector will cause it to jump into the bootloader code entry point at Ox7FFFFFFF This can be the bane of new users 1f they load their code into FLASH with a JT AG reset and single step the first instruction only to find that the program counter is at some wild high address If this happens you need to program the MEMMAP register to 0x00000002 to force the chip into FLASH mode and return the user vector table Once the bootloader code has been entered it will perform a number of checks to see if the FLASH needs to be programmed First the watchdog is checked to see if the processor has had a hard reset of a soft reset If it is a hard reset the logic level on pinl 4 will be tested If it 1s low then the bootloader command handler will be entered If it 1s a soft reset 1e watchd
92. an be used to build very efficiently coded programs or to give a compiler designer nightmares An example of a typical ARM instruction is shown below if Z 1 R1 R2 R3x4 Can be compiled to EQADDS R1 R2 R3 LSL 2 19 Introduction to the LPC2000 1 The ARM7 CPU Core Copying Registers The next group of instructions are the data transfer instructions The ARM7 CPU has load and store register instructions that can move signed and unsigned Word Half Word and Byte quantities to and from a selected register Mnemonic Meaning LDR Load Word LDRH Load Half Word LDRSH Load Signed Half Word LDRB Load Byte LRDSB Load Signed Byte STR Store Word STRH Store Half Word TR H Store Signed Half Word SIRB oLore Byte STRSB Store Signed Half Word Since the register set is fully orthogonal it is possible to load a 32 bit value into the PC forcing a program jump anywhere within the processor address space If the target address is beyond the range of a branch instruction a stored constant can be loaded into the PC Copying Multiple Registers In addition to load and storing single register values the ARM has instructions to load and store multiple registers So with a single instruction the whole register bank or a selected subset can be copied to memory and restored with a second instruction Ro Mo The load and store multiple instructions allow you to save or restore the entire register file or any subset of registers in the
93. and receiving CAN messages In order for a CAN network to work we need a minimum of two nodes Fortunately the LPC2194 has two independent CAN controllers which are brought out to two D Type connectors on the evaluation board For our examples we will connect the two channels together and send data from one channel to the other Setup the evaluation board with the JTAG debugger and connect Pin 2 CAN low of socket P3 to pin 2 of socket P4 Do the same with pin7 CAN High Open the project in c examples work EX22 TXCAN Calculate the bit timing values for 125 Mbit sec withPclk 60 MHz Complete the lines of code in the example Program the bit timing register C2BTR 0 001 0010 To transmit data set the Data length code to four bytes 2 1 0x00040000 Set the address to message 22 and a standard 11 bit identifier C2TIDI 0x00000022 Copy the A D result into the first byte of the TX buffer C2TDAI val Schedule the message for transmission C2CMR 0x00000001 Build the code and start the debugger Once the code is running the A D conversion will be transmitted from the CAN2 module and received by CANI The received data is then written to the GPIO to modulate the LED s In the simulator the two CAN channels are looped back by a script file and the CAN traffic may be observed in the Peripherals CAN communication window 179 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 26 Receivi
94. anding of the underlying machine code is very important in developing efficient programs Before we start our overview of the ARM7 instructions it is important to set out a few technicalities The ARM7 CPU has two instruction sets the ARM instruction set which has 32 bit wide instructions and the THUMB instruction set which has 16 bit wide instructions In the following section the use of the word ARM means the 32 bit instruction set and ARM7 refers to the CPU The ARM is designed to operate as a big endian or little endian processor That is the MSB is located at the high order bit or the low order bit You may be pleased to hear that the LPC2000 family fixes the endianess of the processor as little endian 1 e MSB at highest bit address which does make it a lot easier to work with However the ARM7 compiler you are working with will be able to compile code as little endian or big endian You must be sure you have it set correctly or the compiled code will be back to front MSB LSB Little endian Bit 31 Bit O The ARM7 CPU is designed to support code compiler in big endian or little endian format The Philips silicon is fixed as little endian LSB MSB Big endian Bit 31 Bit One of the most interesting features of the ARM instruction set 1s that every instruction may be conditionally executed In a more traditional microcontroller the only conditional instructions are conditional branches and maybe a few others like bit test and set
95. artup Code The startup code used in the GNU project is different in that the Keil Assembler has different directives and naming conventions However it 1s performing the same operations It is up to the programmer to edit the vector table as discussed in the section on the Keil compiler startup code The graphical editor allows you to configure the processor stacks and system peripherals in the same way as the Keil compiler startup code Interworking ARM THUMB Code The GCC compiler also supports the ARM procedure calling standard and allows interworking between the ARM and THUMB instruction sets However unlike the Keil compiler it is not possible to select individual functions as ARM or THUMB In the GCC compiler all ARM code must be in one module or modules and the THUMB code must be in separate modules These modules are compiled as ARM or THUMB as required and then linked together This process is described in example 3 in this section Accessing Peripherals The Keil and GNU compilers can use the same include files to access the on chip SFR registers Interrupt Service Routines The GCC compiler has a set of non ANSI extensions which allow functions to be declared as interrupt routines The general form of the declaration is shown below vord IRQ Routine void attribute interrupte LRO The following keywords are available to define the exception source required FIQ IRQ SWI UNDEF This function declaration is o
96. artup code In this exercise we will configure the compiler startup code to configure the stack for each operating mode of the Arm7 we will also ensure that the interrupts are switched on and that our program is correctly located on the interrupt vector Open the project in C work EX2 startup Open the file Startup s and using the graphical editor configure the operating mode stacks as follows ily Stack Configuration ME 0 4000 4000 Undefined Mod xt 0080 Supervisor Made 00000 0080 Abort Made 0 0000 0080 Fast Interrupt Mode 00000 0050 Interrupt Mode 0 0000 0050 4 User System Mode Ox0000 0400 fe PLL Setup v Now Compile the code Start the simulator and when the PC reaches main examine the contents of each R13 register Examine the flags in the CPSR to determine the operating mode and instruction set being used At last entry in the register window is the Internal Mode this gives additional information including timing information if you are in the simulator Project Workspace Register Current User System Fast Interrupt Each stack is allocated a space of 0x80 The Interrupt i user stack is 0x400 bytes so user data will start a at 0x40003d80 0x400 0200000514 14 LR 0 00000000 SPSA 0200000000 Abort Undefined Internal B 141 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 3 Using THUMB code In this example we will build
97. at is to say the features which are used to control the performance and functional features of the device This includes the on chip flash and SRAM memory the external bus interface which is present on the LPC22xx devices the phase locked loop which is used to multiply the external oscillator in order to provide a maximum of 60M Hz processor clock and the power control features Finally we will take a look at the simplest user interrupt source the external interrupt pins before going on to look at the exception system in detail in the next section Bus Structure To the programmer the memory of all LPC2100 devices is one contiguous 32 bit address range However the device itself is made up of a number of buses The ARM7 core is connected to the Advanced High performance Bus AHB defined by ARM As its name implies this is the fastest way of connecting peripheral devices to the ARM 7 core Connected to the AHB 1s the vector interrupt controller and a bridge to a second bus called the VLSI peripheral bus VPB Since the Interrupt vector controller is responsible for managing all the device interrupt sources it is connected to the ARM core by the fastest bus All the remaining user peripherals are connected to the VPB The VBP bridge contains a clock divider so the VPB bus can be run at a slower speed than the ARM7 core and the AHB This is useful for two reasons Firstly we can run the user peripherals at a slower clock rate than the main p
98. ay be directly controlled Changes in modem status can also generate a UART interrupt Loopback These additional features allow optimal connection to a modem with an interrupt generated each time there is a change in the modem status register Exercise 20 UART In Exercise 4 we saw how to use the STDIO library with the UARTs In this example we look at how the UARTs are initialised to run at a specific baud rate 93 Introduction to the LPC2000 4 User Peripherals I2C Interface As Philips were the original inventors of the I2C bus standard it is not surprising to find the LPC2000 equipped with a fully featured I2C interface The I2C interface can operate in master or slave mode up to 400K bits per second and in master mode it will automatically arbitrate in a multi master system SDA Typical I2C bus configuration The bus consists of separate clock SCL and data lines with a pull up resistor on each line The two external devices used in the example are port expander chips PCA 8574 PCA 8574 LPC 2100 Rp 50 D Number of Devices D Rp inKQ A typical I2C system is shown above where the LPC2000 is connected to two external port expander chips As with the other peripherals the Serial Clock SCL and Data SDA lines must be converted from GPIO pins to I2C pins via the pin connect block 12CCONSET 12 STAT I2C peripheral registers 12 DAT The programmers interface includes two sina timing registe
99. be generated with two characters left in the FIFO These remaining characters will cause a character time out indication CTI interrupt The CTI interrupt occurs when there are one or more characters in the FIFO and no FIFO activity has occurred for 3 5 4 5 character times 02 Introduction to the LPC2000 4 User Peripherals The transmit FIFO will also generate interrupts when the transmit holding register is empty and when the transmit shift register is empty UART Transmit FIFO Like the RX FIFO the TX FIFO is 16 bytes deep and can generate an interrupt when empty and when it has finished 16 Bytes transmitting THR empty THR empty El amp TSR empty UARTI has the same basic structure as UARTO however it has additional support for modem control This consists of additional external pins to support the full modem interface CTS DCD DSR DTR RLRTS there are two additional registers the modem control register and the modem status register and an additional interrupt source to provide a modem status interrupt DCD RI DSR vecas CTS ki Delta DCD It Tradmy edge EI T oon Sheid mee R m Delta DSR lo 2 Modem Status register m nan 020 i n ga MEINE ty i n zs i e c r pr PLI arial our eh pee UART1 Modem registers n Tu za Finda E Ts Atenu UART1 has additional support Pap ENa for modem interfacing The b DTR and RTS signals m
100. be loaded into the simulator and executed from the reset vector until it reaches main The project browser is replaced by a register window that allows you to view the contents of the CPU registers Here you can View the registers in each of the different operating modes Open the SPSR and CPSR registers to view the flags View the internal mode to the simulated cycle count and timestamp Change the contents of a register by triple clicking on its value and then entering a new value 133 Introduction to the LPC2000 5 Tutorial With Keil Tools From main single step the code Use F11 to step a line of code Use F10 to block step lines of code and functions Use F5 to run the code at full speed Use Esc to halt the code Note For the single step commands to work a source code window must be the active window To set a breakpoint Select a line of code right click for the local menu and select insert remove breakpoint Now press F5 to run to the breakpoint E while 1 n 1 fibo fihl fibz fibl fib2 E Unde fibZ fibo C Redo i db Cut returnifiboj copy ir Paste ES mainivoid b Toggle Bookmark is Show Disassembly ak x8 Set Program Counter for ee Insert include EP TIS H 1 counter 0 fl Run to Cursor line for 1 1 2 1 To Line countert fl Insert Remove Breakpoint fihotount Fihi gm Enable Disable Breakpoint Clear complete Code Coverage Info
101. be used by the interrupt I2CData Data I2CONCLR 0x000000FF Clear all I2C settings I2CONSET 0x00000040 Enable the I2C interface I2CONSET 0x00000020 Start condition The slave address and data to be sent are placed in global variables so that they can be used by the I2C interrupt routine The address is a seven bit address with the LSB set for write and cleared for read The routine next clears the I2C control flags enables the I2C peripheral and asserts a start condition Once the start condition has been written onto the bus an interrupt is generated and a result code can be read from the I2C status register Stat 0x08 0x18 0x28 0x28 0x20 I2C status Register For each bus A event an interrupt is generated a condition code is returned in the status register This code is used to 2 U within the I2C peripheral If the start condition has been successful this code will be 0x08 Next the application software must write the slave address and the R W bit into the I2Cdata register This will be written on to the bus and will be acknowledged by the slave When the acknowledge is received another interrupt 15 generated and the status register will contain the code 0x18 if the transfer was successful Now that the slave has been addressed and is ready to receive data we can write a string of bytes into the I2C data register As each byte is written it will be transmitted and acknowledged When it is acknowledged an
102. been received 119 Introduction to the LPC2000 4 User Peripherals CAN Controller 1 TA CAN message received SS Full CAN mode In full can mode the CAN RAM may also be configured as additional 2 Scan ID against acceptance tables receive buffers which store incoming data for the CPU to read as required Acceptance Filter with Identifier Look up Table The CPU id 3 On Match transfer message to unique 1e CPU can read the message objects at any time message buffer The acceptance filter also has a full CAN mode In this mode the messages are received and scanned against the table of permissible identifiers If a match is made the message is stored not in the CAN controller receive buffer but in a dedicated message buffer within the acceptance filter memory In this mode each message has its own unique message buffer at a fixed location making all the CAN data easily accessible from the CPU Configuring The Acceptance Filter The acceptance filter is configured by seven registers Control of the filter is via the mode register The various ID tables are configured by the next five registers and the seventh register is an error reporting register Before configuration of the acceptance filter can start it must be disabled This 1s done by setting the AccOff bit and clearing the AccBP bit in the acceptance filter mode register If the CAN controller is run with this configuration then all messages
103. ber of gates and consequently a large portion of the LPC200 die area This flies in the face of the ARM7 design which has simplicity as its watchword Another downside of a full cache is that the runtime of code using the cache is no longer deterministic and could not be used by any application which required predictability and repeatability The Memory Accelerator Module is a compromise between the complexity of a full cache and the simplicity of allowing the processor to directly access the FLASH memory Bank 0 Bank x 128 unit The FLASH memory is arranged as two 25 128 128 interleaved banks of 128 bit wide memory One T flash access from the MAM loads four ARM instructions or eight THUMB instructions which bg MAM can be executed by the ARM7 CPU Like a cache the MAM attempts to have the next ARM instruction in its local memory in time for the CPU to execute First of all the FLASH memory is split into two banks which are 128 bits wide and can be independently accessed This means that a single FLASH access can load four ARM instructions or eight THUMB instructions User code is interleaved between the two banks so during sequential code execution the code fetched from one bank into the MAM is being executed while the next 128 bits of instructions from the second bank is being perfected This ensures that it will be ready for execution once the last 128 bits has been executed This technique works particularly wel
104. breakpoint on the initial switch statement we can run the code and observe the activity on the I2C bus Uu v O93 void I2CISR void irq 084 0195 Joss switch 1235TAT 0597 t After running the code the transactions on the I2C bus will look as follows I2C Interface HE Hardware 12C Communication Mode Address Direction Data f ACK 1 NACKI Masher 20 Transmit 00 01 02 03 04 Master 20 Transmit l Master 20 Fecere 01 02 03 04 Introduction to the LPC2000 5 Tutorial With Keil Tools The Simulated EEPROM memory is mapped into an unused section of the processor address range In this case 0x00030000 to 0x000300FF As the code is run you can view data as it 1s written and read from the memory this can be a great aid to debugging your drivers 175 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 22 SPI Like the I2C example this example uses the SPI interface to communicate to a serial EEPROM and demonstrates how to write and read data to such a device Since the MCB2100 is not fitted with such a memory this example uses the simulator with a script file to simulate the EEPROM Open the project in C work EX16 SPI The script file is in SPI ini and this is added to the project in Options for Target Debug The script maps some memory for the SPI EEPROM at 0x700000 0x7000FF In Main c add the following lines of Code Configure the operation mode and bit timing S
105. c T 1 311 1 irra zu a3 meet c 33 IOCLRi1 x FF DOJ00 P 34 1 pattern heee 1 25 1 7 F 1 jum M 0 13 Supervisor mode 148 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 7 Memory Accelerator Module This exercise demonstrates the 1mportance of the memory accelerator module Initially the PLL is set to 60MHz operation but the MAM is disabled A simple LED flashing routine is used to illuminate the LEDs on the target board in sequence This shows the sort of performance you can expect from and ARM7 running directly from on chip FLASH memory When the value of the potentiometer is changed the MAM ss enabled and the code will run faster making the LEDs flash faster This increase in performance caused solely by the MAM which is why it 1s so important to this kind of small single chip microcontroller In this example we will use the bootloader to load the code into the flash in place of the JTAG Open the project in exercises EX7 MAM In main c complete the code to enable the MAM In Options for target output tick the generate hex box Build the code Connect the PC serial port to COMO on the target board Apply power to the board Start the Philips ISP Utility to get the screen shown below E LPC2000 Flash Utility HE xi File Buffer Help LPC2000 Flash Utility V2 2 0 Flash Fragramrming
106. caler values have been calculated However the simulator can only take you so far and sooner or later you will need to take some inputs from the real world This can be done to a certain extent with the simulator scripting language but eventually you will need to run your code on the real target The simulator front end can be connected to your hardware by the Keil ULINK interface The ULINK interface connects to the PC via USB and connects to the development hardware by the LPC2000 JTAG interface The JTAG interface is a separate peripheral on the ARM7 which supports debug commands from a host By using the JTAG you can use the uVISION simulator to have basic run control of the LPC2000 device The JTAG allows you to download code onto the target to single step and run code at full speed to set breakpoints and view memory locations Tutorial Included with this book is a demonstration version of the Keil uVISION IDE The installation comes with two compilers the Keil ARM compiler and the GNU tools The tutorial section talks you through example programs illustrating the major features of the LPC2000 These examples can be run on the simulator or if you have the starter kit they can be downloaded and run on the MCB2100 evaluation board There are two sets of examples on the CD one for the Keil compiler and one for the GNU The main text concentrates on the Keil compiler However Appendix A describes how to use the GNU compiler and also 28
107. cken and egg situation In order to be able to program the external FLASH the chipselect must be configured but to do this we must have code running on the chip One solution would be to place a configuration program into the on chip FLASH boot from this and use it to configure the chipselects However some LPC variants are available without on chip FLASH Fortunately the ULINK JTAG can run a script file to setup the chipselects as required and then program the external memory In addition it is possible to use the on chip FLASH in conjunction with the external FLASH on chipselect In this case you can make best use of the on chip flash by placing your interrupt functions in it Since these will be coded in the ARM instruction set you will want them to run as fast as possible However you must be careful when locating code into the on chip FLASH If you are booting from external FLASH the interrupt vector table will be mapped into the first 64 bytes of internal memory This means that you must locate any on chip code from location 0x00000040 upwards Anything located below 0x00000040 will be programmed into the FLASH memory but will be mapped out during normal program 59 Introduction to the LPC2000 3 System Peripherals operation As a result your code will crash probably in quite a spectacular fashion In the Keil compiler this can be achieved by reserving the vector table bytes as shown below Options for Target Simulator LPC279x
108. code is to interwork the ARM and THUMB instruction sets In order to allow this interoperability ARM have defined a standard called the ARM THUMB Procedure Call Standard ATPCS The ATPCS defines among other things how functions call one another how parameters are passed and how stacks are handled The APCS adds a veneer of assembler code to support various compiler features The more you use the larger these veneers get In theory the APCS allows code built in different toolsets to work together so that you can take a library compiled by a different compiler and use it with the Keil toolset Parameter Passing The ARM procedure call standard defines how the user CPU registers should be used by compilers Adhering to this standard allows interworking between different manufacturers tools Local Variables Scratch Register Stack Register Link Register Program Counter The APCS splits the register file into a number of regions RO to R3 are used for parameter passing between functions If you need to pass more than 16 bytes then spilled parameters are passed via the stack Local variables are allocated R4 R11 and R12 is reserved as a memory location for the intra call veneer code In the Keil compiler all code is built for interworking and the global instruction set is the THUMB so all code will be compiled as THUMB instructions except for interrupt code which defaults to ARM This global default can be changed in the Options for
109. creased Prior to a conversion the resolution of the result may be defined by programming the CLKS field The A D has a maximum resolution of 10 bits but can be programmed to give any resolution down to 3 bits The conversion resolution is equal to the number of clock cycles per conversion minus one Hence for a 10 bit result the A D requires 11 ADCLK cycles and four for a 3 bit result Once you have configured the A D resolution a conversion can be made The A D has two conversion modes hardware and software The hardware mode 101 Introduction to the LPC2000 4 User Peripherals allows you to select a number of channels and then set the A D running In this mode a conversion is made for each channel in turn until the converter is stopped At the end of each conversion the result is available in the A D data register 31 Done Overun V Vdda 0 AD data register The data register contains the conversion result channel overrun error and conversion done flag At the end of a conversion the Done bit is set and an interrupt may also be generated The conversion result is stored in the V Vdda field as a ratio of the voltage on the analogue channel divided by the voltage on the analogue power supply pin The number of the channel for which the conversion was made is also stored alongside the result This value is stored in the CHN field Finally if the result of a conversion is not read before the next result is due it will be overwritt
110. ction to the LPC2000 3 System Peripherals void NonVectoredIRQ void irq if VICIRQStatus amp 0x00008000 Test for the interrupt source IOSETI x00FF0000 Set the LED pins EXTINT 0x00000002 Clear the peripheral interrupt flag update t VICVectAddr 0x00000000 Dummy write to signal end of interrupt Exercise 13 Non Vectored nterrupt This final exercise with the VIC demonstrates how to handle a non vectored interrupt It is included for completeness since this mode will not normally be required Within the VIC it 1s possible for the application software to generate an interrupt on any given channel through the VIC software interrupt registers These registers are nothing to do with the software interrupt instruction SWD but allow interrupt sources to be tested either for power on testing or for simulation during development Software Interrupt Register It is possible to simulate an interrupt source via the software interrupt set and clear registers in the VIC Interrupt Channel Interrupt Source In addition the VIC has a protected mode which prevents any of the VIC registers from being accessed in USER mode If the application code wishes to access the VIC it has to enter a privileged mode This can be in an FIQ or IRQ interrupt or by running a SWI instruction Typical latencies for interrupt sources using the VIC are shown below In the case of the non vectored interrupts use the late
111. ctor When the Reset Supervisor 0x00000000 processor changes mode the PC will Undefined instruction Undefined 0x00000004 jump to the associated vector Software interrupt SWI Supervisor 0x00000008 NB there is a missing vector at Prefetch Abort instruction fetch memory abort Abort 0x0000000C 0x00000014 Data Abort data access memory abort Abort 0x00000010 IRQ interrupt IRQ 0x00000018 FIQ fast interrupt FIQ 0x0000001C 13 Introduction to the LPC2000 1 The ARM7 CPU Core NB There is a gap in the vector table because there is a missing vector at 0x00000014 This location was used on an earlier ARM architecture and has been preserved on ARM7 to ensure software compatibility between different ARM architectures However in the LPC2000 family these four bytes are used for a very special purpose as we shall see later Bee Each of the exception sources has a fixed priority The on Data Abort chip peripherals are served by FIQ and IRQ interrupts Each peripheral s priority may be assigned within these FIQ groups Prefetch Abort Undefined instruction If multiple exceptions occur then there is a fixed priority as shown below When an exception occurs for example an IRQ exception the following actions are taken First the address of the next instruction to be executed PC 4 1s saved into the link register Then the CPSR is copied into the SPSR of the exception mode that is about to be entered i e SPSR_irq The PC is t
112. ctored Interrupt Controller Watchdog WDIMT T IRG 00000000 D D Timer 4 IRG 00000000 Hu Timer 1 5 180 00000000 D D PIO LIARTU E IRG 00000000 D LIART 1 7 IRO 00000000 SPI Interface Pli B IRO 00000000 SPI 10 IRG 00000000 D Timer PLL Lock PLOCE 12 IRG 00000000 0 Pulse width Modulator HIC 13 IRGO 00000000 0 see redd External InteruptO EIMTU 14 00000000 External Interrupt E MNT 15 IRG 00000000 0 Watchdog External Interupt2 EINT2 16 IRG 00000000 0 t Selected Interrupt IntSelect IntEnable Rawlnt Vectored IAG Elat Enable VIV ectCnt Jox00000000 ViCVectAddr 10400000000 Channel VitVect4ddrl n t0000000 YiEDeh ectAddr Jox00000000 VIE Pratectian 10400000000 elect 10400000000 VICR awl mtr ox00000000 VI Snftint ox00000000 ViElntEnahle ox00000000 VICIRG Status ox00000000 VICS oft ntClear 000000000 VICIntEnClr 10400000000 Status 0400000000 136 Introduction to the LPC2000 5 Tutorial With Keil Tools The debugger has many mode functions but the above debugging tools will allow you to run the course exercises The simulator can also be replaced by a JTAG debugger and the same front end can be used to debug real hardware 157 Introduction to the LPC2000 5 Tutorial With Keil Tools Using The ULINK Hardware Debugger The JTAG debugger included with the starter kit
113. d into Idle mode where the CPU is halted but the peripherals are still operational Any interrupt from a peripheral will wake up the CPU and processing will resume Idle mode stops the clock to the CPU but Tmero SPI the peripherals are still running and any interrupt will restart the CPU Watchdog RTC System Control Pin Connect Block PCON 64 Introduction to the LPC2000 3 System Peripherals The ARM can also be placed into a power down mode which halts both the CPU and the peripherals In this mode only a reset or an interrupt generated by the external interrupt pins will cause the chip to wake up In power down mode the oscillator is shut down All the internal states of the processor registers and on chip SRAM are preserved as are the static logic levels on the I O pins On wake up from power down the clock source is the external oscillator and the PLL must be reconfigured Arm 7 TDMI Ext Int in Power down mode halts the processor and the peripheral clocks The external interrupts can be imp used to restart the processor and peripherals Timer 1 UART GP10 PwMo Watchdog C 12 0 System Control PCON MANIN 007 Pin Connect Block The LPC2000 has an internal wake up timer which ensures the external oscillator is stable and the on chip memory and peripherals have initialised before the CPU starts to execute instructions From wake up the osci
114. de Control CAN CMR Command Register Register CAN GSR Global Status Register CAN ICR Interupt Status CAN IER Interrupt Enable Rx Buffer CAN BTR Bit Timing Register CAN EWL Error Warning Limit Tx1 Buffer CAN SR Status Register Tx2 Buffer Tx3 Buffer In order to configure CAN controller we must program the bit timing register However the bit timing register is a protected register and may only be written to when the CAN controller is in reset Bit zero of the mode register is used to place the CAN controller into reset th d xb 40 o4 c Er y BRP The CAN bit timing is defined by 5 separate parameters 31 23 22 19 15 14 3 Sampling TSEG2 Timing Segment 2 TSEGI Timing Segment 1 SJW synchronous Jump Width BRP Baurate Prescaler We can use the values calculated above to initialise one of the CAN controllers to 125Kbit sec It is important to note that the values stored in the register are the calculated values minus This ensures that no timing segment is set to zero Once the CAN controller has been initialised it is possible to transmit a message by writing to a transmit buffer Each transmit buffer 1s made up of four words 112 Introduction to the LPC2000 4 User Peripherals CANT Fix Transmit Frame Info CANT iDx Transmit Identifier CAN TDAx Transmit Data 1 4 CAN TDBx Transmit Data 5 8 Two words are used to hold the 8 bytes of data and one word holds the message identifier The final regist
115. duction to the ARM7 TDMI processor and the LPC2000 microcontroller architecture The content 1s based on a series of one day seminars held for professional engineers interested in learning how to use the LPC2000 family as quickly as possible Topics covered in this book include Introduction to the ARM7 processor Software development tools LPC2000 system architecture LPC2000 peripherals In addition a comprehensive tutorial is included that takes you through practical exercises to reinforce the topics discussed in the main text By reading this book and performing the accompanying exercises you will quickly become well versed in the ARM7 processor and the LPC2000 microcontroller The CD accompanying the book includes an evaluation version of the popular uVISION3 IDE and compiler from Keil Elektronik plus all the example exercises for both the Keil CARM and the GCC ARM compilers www hitex co uk arm DEVELOPMENT TOOLS ISBN 0 9549988 1 2 a E T a 7809541998813 x ur Hitex UK Ltd Sir William Lyons Road Science Park Coventry UK CV4 7EZ Tel 44 0 2476 692066
116. e quite bulky and should only be used if your application 1s very I O driven Exercise 4 STDIO This exercise demonstrates the low level routines used by printf and scanf and configures them to read and write to the on chip UAHT Accessing Peripherals Once we have built some code and got it running on an LPC2000 device it will at some point be necessary to access the special function registers SFR in the peripherals As all the peripherals are memory mapped they can be accessed as normal memory locations Each SFR location can be accessed by hardwiring a volatile pointer to its memory location as shown below define SFR volatile unsigned long OxFFFFFO000 The Keil compiler comes with a set of include files which define all the SFR s in the different LPC2000 variants Just include the correct file and you can directly access the peripheral SFR s from your C code The names of the include files are LPC21xx h LPC22xx h LPC210x h 33 Introduction to the LPC2000 2 Software Development Interrupt Service Routines In addition to accessing the on chip peripherals your C code will have to service interrupt requests It is possible to convert a standard function into an ISR as shown below vord Thine VOU tid IOSET1 x00FF0000 Set the LED pins EXTINT 0x00000002 Clear the peripheral interrupt flag The keyword __ fiq defines the function as a fast interrupt request service routi
117. e UART clock frequency must be 16 times the requlred BAUD rate This is derived by dividing Pclk by a 16 bit divisor register DLAB 1 Once the UART is initialised characters can be transmitted by writing to the Transmit Holding Register Similarly characters may be received by reading from the Receive Buffer Register In fact both these registers occupy the same memory location writing a character places the character in the transmit FIFO and reading from this location loads a character from the Receive FIFO The two routines shown below demonstrate handling of transmit and receive characters int putchar int ch Write character to Serial Port if ch mni while U1LSR amp x20 1 CR 7 output CR while ULLSR amp 0x20 return UlTHR ch int getchar void Read character from Serial Port x while U1LSR amp 0x01 return U1RBR 91 Introduction to the LPC2000 4 User Peripherals The putchar and getchar functions are used to read write a single character to the UART These low level drivers are called by the Keil STDIO functions such as printf and scanf So if you want to redirect the standard I O from the UART to say an LCD display and a keypad rewrite these functions to support sending and receiving a single character to your desired I O devices Both the putchar and getchar functions read the Link Status Register LSR to check on UART error co
118. ectAddr 0x00000000 Exercise 19 Real Time Clock This exercise configures the RTC and demonstrates both the alarm and increment interrupts Set channel Enable the interrupt Ls tor RTC counter ainterrupt read the current state of the IO pins Clear the illuminated LED Set the idle LED Clear the interrupt register 4 Set LED Qu elear the interrupt register Dummy write to signal end of interrupt 87 Introduction to the LPC2000 4 User Peripherals Watchdog In common with many microcontrollers the LPC2xxx family has a watchdog system to provide a method of recovering control of a program that has crashed Watchdog Register Interface Mode E NA The on chip watchdog can force a Reset processor reset or interrupt In the case Watchdog of a watchdog reset a flag is set so your Counter code can stop a soft reset Feed Interup Current Value The watchdog has four registers as shown above The watchdog timeout period is set by a value programmed into the Watchdog Constant Register WDTCR The timeout period is determined by the following formula Wdperiod Pclk x WDTC x 4 The minimum value for WDTC is 256 and the maximum is 2 32 Hence the minimum watchdog period at 60M Hz is 17 066us and the maximum is just under 5 minutes Once the watchdog constant is programmed the operating mode of the watchdog can be configured The Watchdog mode register contains three enable bits contr
119. eil ARM Tools C Cygnus V Use GNU Tools 0 1 Keil Root Folder LNKeiNARMV 0 CAKeil amp RM Reali C Program 5 1 2 5 Use ARM Tools eaiviow Folder Keil Root Folder C Keil 4AMS Cancel Defaults Help 7 Double click on the Keil Uvision3 icon to start the IDE Im IAP p iien L v ARUM Phiips ercaengles AP apit R xi Po b gn f bo b TT R escag um ney Sears i uomen xd UR uu MEN n n 0 Q n 0 0 0 0 0 0 ViOVecifiniin Eovonnonoon MCVecihdd 150000000 MCDeNecilulde 10 00060000 ViCRaie 20001000 eer MODOODUDO Bonon Introduction to the LPC2000 6 Tutorial With GNU Tools From the menu bar select Project New Project Import pvisiond Project pr iH Open Project In the New Project dialog navigate to your desired project directory Save in Z First program q t ex E3 File name First Save as type Project Files uv2 Cancel 2 In the New Project dialog name project first uv2 and select Save A select new device for target dialog will appear Navigate through the device data base and select the Philips LPC2129 folder and select OK Select Device for Target Target 1 2 xl cPU Vendor Philips Device LPC2292 Family ARM Data base Description EA LPC2124 ABM TDM S based high performance 32 bit RISC
120. en by the fresh result and the OVERUN bit is set to one The example below demonstrates use of the A D converter in hardware mode int main void VPBDIV 0x00000002 Set the Pclk to 30 MHz IODIRI x00FF0000 P1 16 23 defined as Outputs ADCR 0x00270607 Setup A D 10 bit AINO 4 3MHz VICVectCntlO 0x00000032 Jconmneot A D to slot 0 VICVectAddrO0 unsigned AD ISR pass the address of the IRQ into the VIC slot VICIntEnable 0x00040000 enable interrupt vhile 1 void AD ISR void unsigned val chan Static unsigned result 4 val ADCR val val gt gt 6 6 Ox03FF Extract the A D result chan ADCR gt gt 0x18 amp 0x07 result chan val The A D has a second software conversion mode In this case a channel 1s selected for conversion using the SEL bits and the conversion is started under software control by writing 01 to the START field This causes the A D to perform a single conversion and store the results in the ADDR in the same fashion as the hardware mode The end of conversion can be signalled by an interrupt or by polling the done bit in the ADDR In the software conversion mode it is possible to start a conversion when a match event occurs on timer zero or timer one Or when a selected edge occurs on P0 16 or P0 22 the edge can be rising or falling as selected by the EDGE field in the ADCR 102 Introduction to the LPC2000 4 User Periphe
121. en loaded 0200000000 0200000004 0200000005 0200000002 0200000010 0200000014 0200000015 0 200000012 0200000020 0200000024 02000000285 0200000022 02000000530 0200000034 0200000036 0 00000032 0200000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEUQ ANDEQ ANDEUQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ RU RU RU RO RO RO RO RO RO RO RO RO RO ROU RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ROU RO RO RO RO RO RO RO RO ROU RO RO RO RO RO RO RO RO RO RO 5 Tutorial With Keil Tools Open the peripherals system control block memory mapping control Memory Mapping Control Memory Mapping Control 0201 Switch from User Flash Mode to Ext Flash Mode This will map the first 64 bytes of chipselect Zero into address 0x00000000 upwards This is our vector table that is located in the external flash Ox 00000000 0200000004 0200000005 020000000 0200000010 0200000014 0200000015 0200000012 0200000020 0200000024 0200000025 020000002 0200000030 0200000034 0200000035 020000003 016 EL FF 16 016 59 016 ESSFF U18 1 00000 ESIFFFFU ESSFF U18 80000040 80000524 80000520 80000512 80000516 00000000 80000514 80000510 PC PC PC
122. ength code CAN message packet The message packet is formed by the CAN controller the application software provides the data bytes the message identifier and the RTR bit Tne message packet starts witn a aominant oit to mark tne start or trame Next comes the message identifier which may be up to 29 bits long The message identifier 1s used to label the data being sent in the message packet CAN is a producer consumer protocol A given message is produced from one unique node and then may be consumed by any number of nodes on the network simultaneously It is also possible to do point to point communication by making only one node interested in a given identifier Then a message can be sent from the producer node to one given consumer node on the network In the message packet the RTR bit is always set to zero This field will be discussed shortly The DLC field is the data length code and contains an integer between 0 and 8 which indicates the number of data bytes being sent in this message packet So although you can send a maximum of 8 bytes in the message payload it is possible to truncate the message packet in order to save bandwidth on the CAN bus After the 8 bytes of data there 1s a 15 bit cyclic redundancy check This provides error detection and correction from the start of frame up to the beginning of the CRC field After the CRC there is an acknowledge slot The transmitting node expects the receiving nodes to assert an acknowledge i
123. er 1s the frame information register FF ATA DLC PRIO The parameters of each CAN message are defined in each message buffer 31 23 19 18 7 FF Frame Format DTR Remote Transmit Request DLC Data Len gth Code Prio Priority This register holds the values of the DLC and the RTR bit In addition there is a frame format FF bit that defines whether the message has an 11 bit or 29 bit identifier As there are three TX buffers it is possible to define an internal priority for each TX buffer If several buffers are scheduled simultaneously the CAN controller will use internal arbitration to decide which is transmitted first This can be done in one of two ways if the TPM bit in the MODE register is Zero the transmit buffer with the lowest value identifier will be sent first If TPM is high then arbitration will use the values stored in the PRIO field in the Tx Frame Information register and the buffer with the lowest PRIO value is sent first Once the buffer has been filled with a message transmission can be started by setting the Transmit request bit TR in the COMMAND register The code below shows some code fragments to initialise the CAN peripheral and transmit a message C2MOD 0x00000001 Set CAN controller into reset 2 0x001C001D J See bit timing to 125k C2MOD 0x00000000 Release CAN controller if C2SR amp 0x00000004 See if Tx Buffer 1l is free C2TFI1 0x00040000 Set DLC to 4 bytes C2TID1 0x00000022
124. erand must be a register but the second can be a register or an immediate value OP code Operands bit shift The general structure of the data processing instructions allows for conditional execution a Cond S Ri R2 R3 sit logical shift of up to 32 bits and the data operation all in the one cycle asandan Enable condition code flags In addition the ARM core contains a barrel shifter which allows the second operand to be shifted by a full 32 bits within the instruction cycle The S bit is used to control the condition codes If it is set the condition codes are modified depending on the result of the instruction If it is clear no update is made If however the PC R15 is specified as the result register and the S flag is set this will cause the SPSR of the current mode to be copied to the CPSR This is used at the end of an exception to restore the PC and switch back to the original mode Do not try this when you are in the USER mode as there 1s no SPSR and the result would be unpredictable Mnemonic Meaning AND Logical bitwise AND EOR Logical bitwise exclusive OR SUB Subtract RSB Reverse Subtract ADD Add ADC Add with carry SBC Subtract with carry RSC Reverse Subtract with carry TST Test TEQ Test Equivalence CMP Compare CMN Compare negated ORR Logical bitwise OR MOV Move BIC Bit clear MVN Move negated These features give us a rich set of data processing instructions which c
125. erial interfaces 23 LPC2212 Two timers 7 capture compare channels LPC221 4 PWM unit with up to 6 PWM outputs 2207 8 channels 10bit ADC 2 CAN channels EJ LPC2294 Real Time Clock Watchdog Timer General purpose 0 pins EJ PSO PB7C51 2 CPU clock up to 60 MHz On chip crystal oscillator and On chip PLL 3 80 87 5242 P80 P87C54x2 P80 P87C58x2 3 P80C557E4 i eg P80C557E6 128 Introduction to the LPC2000 5 Tutorial With Keil Tools In the project browser highlight the Targetl root folder and select the local menu by pressing the right mouse button In this menu select options for target Target 1 Select Device For Target Target 1 Options For Target Target 1 Qpen File LE Build target F7 Translate File Stop build Gdd Files to Group Manage components Remove Iten m Include Dependencies In the Target tab set the simulation frequency to 12 000 MHz Also make sure the Use on chip Rom and Use On chip Ram boxes are ticked Options for Target Intervvorking E Device Target Output Listing C Asm LA Misc L Locate Debug Utilities Philips LPC2232 T V Big Endian Xtal MHz ipa g V Use On chip ROM z Q 3FFFF Operating system None V Use On chip RAM 0x40000000 0 40003FFF External Memory Start Size Start Size 1 RAM ei 44 RAM
126. errupt on Event Interrupt on Event 1 Interrupt on Event 2 Interrupt on Event 3 V GAP CAPO 60 2 V GAP0 3 CRO Interrupt CR1 Interrupt CR2 Interrupt CR3 Interrupt The simulator also includes a logic analyser window that can display a graphical trace of activity on a pin over time The logic analyser is used as follows Open the logic analyser window with view logic analyser In the top left hand corner press the setup button Add an new signal called PORTO set the mask to 0x00000020 and set the display type to bit Logic Analyzer b X Current Logic Analyzer Signals 3 Clear the match1 pin PORTO tH Display Type Bit Color a Min Value oxo Max Value o Mask p 00000020 Shift Aight jo Export Import Add new signal Export Signal Definitions Import Signal Definitions 168 5 Tutorial With Keil Tools Introduction to the LPC2000 IC ll be recorder into the log in wi 169 tivity on the matchl p Now as you run the code any ac analyser window Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 18 Dual Edge Symmetrical PWM Generation In this exercise we will use the PWM module to generate a single channel of symmetrically modulated PWM signal This will use the MATO channel to generate to total signal period and will be configured to reset the timer MATI will be user to generate the turn on of
127. ersion time is 1 uSec but it is only able to deliver 350 uA However the total settling time is also dependent on the external impedance Figures for the impedance of the DAC have not yet been released Exercise 24 Digital to Analog converter This exercise simulates a sine wave which is sampled by the Analogue to digital converter These values are loaded straight into the Digital to Analogue converter to regenerate the sine wave The two sine waves can be compared in the logic analyser window 104 Introduction to the LPC2000 4 User Peripherals CAN Controller Variants of the LPC2000 are available with up to 4 independent CAN controllers on board the chip The CAN controllers are one of the more complicated peripherals on the LPC2000 In this section we will have a look at the CAN protocol and the LPC2000 CAN peripherals The Controller Area Network CAN Protocol was developed by Robert Bosch for Automotive Networking in 1982 Over the last 22 Years CAN has become a standard for Automotive Networking and has had a wide uptake in non automotive systems where it is required to network together a few embedded nodes CAN has many attractive features for the embedded developer It is a low cost easy to implement peer to peer network with powerful error checking and a high transmission rate of up to 1 Mbit sec Each CAN packet is quite short and may hold a maximum of eight bytes of data This makes CAN suitable for small embedded networ
128. es how to build a project to use the external bus It 1s necessary to link the code so it is located in an external flash device configure any chipselect that is used Because the MCB2100 evaluation board uses a true single chip device this example uses the simulator to demonstrate the external bus interface The project is built to place code in flash at 0x80000000 which is the boot chipselect and RAM at 0x81000000 which is chipselect one On real hardware the boot method is determined by the state of the two external boot pins in the simulator we use a script file to set the correct condition However we will also look at configuring the JTAG to program external flash memory so this example can be used on real hardware Open the project in C work ebi In the Options for target menu select the device tab and select the LPC2294 Next select the Target tab and fill in two regions of external memory and uncheck the Use on chip ROM as shown below Options for Target phyCore LPC229x Device Target Output Listing C Asm LA Misc LA Locate Debug Utilities Philips LPC2294 Xtal MHz 12 0 Big Endian Use On chip ROM 0x0 Ox3FFFF Operating system None x M Use On chip RAM 040000000 40003 External Memory Start Size Start Size ROM 0 80000000 0 00400000 x a 2 RAM 0 81000000 0400200000 ahami 1 3 RAM sms Cancel Defaults
129. ete User s Guide Selection GNU C Compiler D GNU C Run Time Libraries AS GNU C Utilities GNU C Assembler E Device Data Books Ge User Manual E E m 127 Introduction to the LPC2000 5 Tutorial With Keil Tools uVISION and the CARM compiler is found under Complete Users Guide Selection Once you have added the datasheet click the OK button to continue defining the project From the menu bar select Project new Project d prisionz Ble Edt view File Edit View Debug Flash Peripherals Tools 5925 Window Help Bas Import pivisiont Project le zz x 24 bee Open Project In the New project dialog navigate to your desired project directory Save in First program ei q t ex E3 File name First Save as type Project Files uv2 Cancel 2 In the new project dialog name the project first uv2 and select Save A select new device for target dialog will appear Navigate through the device database and select the Philips LPC2129 folder and then OK Select Device for Target Target 1 2 xl CPU Vendor Philips Device LPC2292 Family ARM Data base Description LPC2124 1 5 based high performance 32 bit RISC Microcontroller with Th 4 LPC2129 256KB on chip Flash ROM with In System Programming ISP and In amp pplic 3 LPC2194 TEKB RAM Vectored Interrupt Controller External Bus Controller Two UARTs I2C serial interface 2 SPI s
130. f and MATS will generate the turn off point The PWM duty cycle can then be modulated by the keys in serial window 2 Open the project in C work EX20 PWMModule In main c complete the code as follows Enable pin 0 7 as PWM2 PINSELO 0x00008000 Configure PWM channel two to double edge control output enabled PWMPCR 0x0000404 Configure Timer reset to the counter PWMMCR 0x00000003 Set the reload values of matl and mat2 to give an initial spike which is gradually broadened in the main loop as the code runs PWMMRO 0x000000FF PWMMRI 0x00000080 PWMMR2 0x00000080 enable shadow latch for match 0 2 PWMLER 0x00000007 Reset counter and prescaler and enable PWM mode PWMTCR 0x00000002 enable timer with PWM enabled PWMTCR 0x00000009 In the main while loop enable the shadow latch to update the match registers when a new values are available PWMLER 0x0000006 170 Introduction to the LPC2000 5 Tutorial With Keil Tools Compile and download the code into the debugger Run the code and check that it 1s correct with the simulator Again the peripheral window can be user to view the configuration of the PWM module Pulse Width Modulator PWM Frescaler FR 00000001 iE n t0000000 Match Channels Timer TCR 10 00000009 Counter Enable l Reset TL 10 00000000 Pw Enable Interrupt Register IR 10 00000000 0000011 OH Nothing 00000
131. g OxB8A06F58 Program signature LDR PC IRQ Addr LDR PC FIQ Addr 51 Introduction to the LPC2000 3 System Peripherals Philips ISP Utility If there is a valid program signature or pin 0 14 is held low after reset the LPC2000 will start the bootloader Before handing over to the command handler it enters an auto baud routine This routine listens on UART for a synchronisation character When this is sent by the host the LPC2000 measures the bit period and adjusts the Uart O baud rate generator to match the host Once this 1s done some further handshaking and configuration takes place and then control is passed to the command handler The Bootloader command handler takes commands from UARTO in ASCII format The command set is shown below and allows you full programming control of the FLASH In addition the GO command is a simple debugging command which can be used to start execution of code loaded into RAM A full description of the bootloader communication protocol 1s given in the LPC2000 datasheet Unlock U Unlock Code Set Baud Rate B Baud Rate stop Echo A Setting Write to RAM W start address number of bytes Read Memory R address number of bytes When the bootloader has been entered it will accept commands as ASCI characters Copy RAM to Flash C Flash address RAM address gt number of bytes on serial port 0 Prepare sector s for write operation P start sector number e
132. gh the code using the F11 key 142 Introduction to the LPC2000 5 Tutorial With Keil Tools Observe the switch from 32 bit to 16 bit code and the THUMB flag in the CPSR 32 bit ARM code thumb function CPSA SB D D T 00000013C 59 000 LDR R12 PC UN Ox00000140 E12FFF1C BX R12 5 0200000144 00000149 DD DxD0000149 5 4 46 for i 0z00010000 i lt Dz010000 i i lt lt 1 eee y 47 1 e 46 u x 0 00000148 4806 LDR RO PC 40x 0018 1 0 0000014 007 B Oxoo00015 MT b T The processor is running in ARM 32 bit mode the T bit 1s clear and the instructions are 4 bytes long A call to the THUMB function is made which executes a BX instruction forcing the processor into THUMB mode 16 bit 143 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 4 Using STDIO libraries In this exercise we will look at tailoring the Printf function to work with the LPC2100 UART We will look at the registers of the UART s in more detail later Open the project in EX4 printf work n main c add a message for transmission to the printf statement while 1 printf Your Message Here n Call the prinfF function j Add the file serial c in the work directory to the project E t Printf 11 4 4 C source code 1 El main c be a Ipe2tex h 1 4 o E E serial c 121 4 Assembler startup code Startup s 21 Documentation a abstract
133. h Papam De gecs Hm tie l ciel eR 2 Als Sia serm BEER s gr Sl v WIE A alz defie apis s NG Target 1 ie Sy Source Group l ilinrluiz LPCILOw H 3 cina r b lin npi h 41 Ini wold clock vrid R t dee LLChS end i 1 f FLL to give 8 RE J durmmm 5 P yr nt Lip jer TLECDM hl iy Ennhis the FLL I ZLFETD A fi Update TEL pegisters LLID Imh5h iile I PELTTAT feel teat Lack bit LMT fA nun mere if this im necsanury LLFEFD s x55 E ENTS mn 160 R m MT T5 DOLE 2 DNT b iR Inno Sakin The Keil UVISION a k a uVISION IDE is designed to support several compilers the Gnu C compiler The ARM development suite and the Keil ARM compiler Before compiling make sure you have the GNU compiler selected This is done by activating the project workspace right clicking and selecting manage components In this dialog select the Components Environment and Books EE Project Components Folders Extensions Books Development T ool Folders V Use Settings from TOOLS INI Tool Base Folder c NKeil amp R M BIN JO Keil ARMABINS eee LIB Default File Extensions C Source fe C Source cpp Asm Source xa Object Library 2 Document htnc Sees Regfile Select AAM Development Tools
134. have seen it is possible to encode an integer into the unused portion of the SWI opcode define SWICall2 asm swi 2 However in the Keil CA ARM compiler there is a more elegant method of handling software interrupts A function can be defined as a software interrupt by using the following non ANSI keyword adjacent to the function prototype int Syscall2 int pattern svi 2 In addition the assembler file SWI_VEC S must be included as part of the project Now when a call is made to the function an SWI instruction is used causing the processor to enter the supervisor privileged mode and execute the code in the SWI VEC S file This code determines which function has been called and handles the necessary parameter passing This mechanism makes it very easy to take advantage of the exception structure of the ARM processor and to partition code which is non critical code running in user mode or privileged code such as a BIOS or operating system In the tutorial section we will take a closer look at how this works Exercise 6 Software Interrupt The SWI support in the Keil compiler is demonstrated in this example You can easily partition code to run in either the user mode or in supervisor mode Locating Code In RAM As we shall see later the main performance bottleneck for the ARM7 CPU is fetching the instructions to execute from the FLASH memory The LPC2000 has special hardware to solve this problem for the on chip FLASH However
135. hen filled with the address of the exception mode interrupt vector In the case of the IRQ mode this is 0x00000018 At the same time the mode is changed to IRQ mode which causes R13 and R14 to be replaced by the IRQ R13 and R14 registers On entry to the IRQ mode the I bit in the CPSR is set causing the IRQ interrupt line to be disabled If you need to have nested IRQ interrupts your code must manually re enable the IRQ interrupt and push the link register onto the stack in order to preserve the original return address From the exception interrupt vector your code will jump to the exception ISR The first thing your code must do is to preserve any of the registers RO R12 that the ISR will use by pushing them onto the IRQ stack Once this is done you can begin processing the exception USER IRQ Save PC into link register When an exception occurs the CPU will change 2 Save CPSR into modes and jump to the associated interrupt vector SPSR excep SR code pushes registers R13 R14 onto stack R15 Exception Vector Address t Once your code has finished processing the exception it must return back to the user mode and continue where it left off However the ARM instruction set does not contain a return or return from interrupt instruction so manipulating the PC must be done by regular instructions The situation 1s further complicated by there being a number of different return 14 Introduction to the LPC2000 1 The AR
136. in the Interrupt Select Register will enable multiple FIQ interrupt sources If this is the case on entry the interrupt source can be determined by examining the VIC FIQ Status register and the appropriate code executed Clearly having several FIQ sources slows entry into the ISR code Once you have selected an FIQ source the interrupt can be enabled in the VIC interrupt enable register As well as configuring the VIC the peripheral generating the interrupt must be configured and its own interrupt registers enabled Once an FIQ interrupt is generated the processor will change to FIQ mode and vector to 0x0000001C the FIQ vector You must place a jump to your ISR routine at this location in order to serve the interrupt Leaving An FIQ Interrupt As we have seen declaring a C function as an FIQ interrupt will make the compiler use the correct return instructions to resume execution of the background code at the point at which it was interrupted However before you exit the ISR code you must make sure that any interrupt status flags in the peripheral have been cleared If this is not done you will get continuous interrupts until the flag 1s cleared Again be careful as to clear the flag you will have to write a logic 1 not a logic At the end of an interrupt the interrupt status flag must Clear gt Peripheral Interrupt Register be cleared Failure to do this will result in continuous interrupts 68 Introduction to the LPC2000 3 Sys
137. ional hardware support for he on chip peripheral interrupts Without the VIC he interrupt response time would be very slow AHB nFIQ nIRQ Vector Interrupt Controller The VIC 1s a component from the ARM prime cell range of modules and as such 1s a highly optimised interrupt controller The VIC is used to handle all the on chip interrupt sources from peripherals Each of the on chip interrupt sources is connected to the VIC on a fixed channel your application software can connect each of these channels to the CPU interrupt lines FIQ IRQ in one of three ways The VIC allows each interrupt to be handled as an FIQ interrupt a vectored IRQ interrupt or a non vectored IRQ interrupt The interrupt response time varies between these three handling methods FIQ is the fastest followed by vectored IRQ with non vectored IRQ being the slowest We will look at each or these interrupt handling methods in turn 67 Introduction to the LPC2000 3 System Peripherals FIQ qq The VIC provides three levels of interrupt service and on chip interrupt sources ARM7 TDMI Vectored Ing RS may be allocated into each group Non Vectored IRA TARE FIQ interrupt Any interrupt source may be assigned as the FIQ interrupt The VIC interrupt select register has a unique bit for each interrupt Setting this bit connects the selected channel to the FIQ interrupt In an ideal system we will only have one FIQ interrupt However setting multiple bits
138. ions are 4 bytes long A call to the THUMB function is made which executes a BX instruction forcing the processor into THUMB mode 16 bit The THUMB bit is set and on entry to the THUMB function a PUSH instruction is used to preserve registers on to the stack 191 Introduction to the LPC2000 6 Tutorial With GNU Tools Exercise 4 Using The GNU Libraries In this exercise we will look at tailoring the GNU Printf function to work with the LPC2100 UART We will look at the registers of the UARTS in more detail later Open the project in EX4 printf work n main c add a message for transmission to the printf statement while 1 printf Your Message Here Mn Call the prinfF function Add the file syscalls c in the work directory to the project EX Flash Source Group 1 E f main c E serial c 5 Startup s E Syscalls c In syscalls c add modify the write function as follows Complete the for loop statement so it runs for the length of the printf string len Inside the for loop add the putchar statement to write a single character to the stdio channel putchar ptr Increment the pointer to the character string ptr int write int file char ptr int len int i for 1 0 nos len 1tt purchar 7DLET D return len Compile the code and download it to the development board Run the code and observe the output within hyper terminal If you are using the simulator selec
139. is the Keil ULINK This connects to the JT AG port on MCB2100 P5 and then connects to the PC via USB To switch from using the simulator to using the ULINK follow the steps below Setting up the ULINK JTAG hardware debugger Connect the ULINK to the MCB2100 as shown below and plug the USB connection into the PC Power should also be connected to the MCB2100 6 5 V emoum Lll a FEE ULINK Configure UVISION to use the ULINK in place of the simulator First open the utilities menu in the Options for target dialogue Select the use target device for Flash programming radio button and select the ULINK ARM7 debugger from the drop down menu Also tick the update target before debugging box Device Target Output Listing CC Assembler Linker Debug Utilities Configure Flash Menu Command Use Target Driver for Flash Programming ULINK ARM Debugger Settings IV Update Target before Debugging Irit File E Edit C Use External Tool for Flash Programming Command LPC210x_ISP EXE Arguments HH x D 1 3600 1 iz Hun Independent Cancel Defaults 138 Introduction to the LPC2000 Configure the flash algorithm 5 Tutorial With Keil Tools Next click the setting button Set the start address for the RAM at 0x40000000 with a size of 0x400 Click the add button and select the flash algorithm for the device you are using then click OK to quit C
140. ise TA Nested interiubt m Aa D 163 Introduction to the LPC2000 Introduction Exercise I5 General purpose TO PINS aeons 164 Exercise 16 Der laete De D 165 Exercise 5 mer Mite uide cra tot 167 Exercise 18 Dual Edge Symmetrical PWM Generation 170 Exercise 19 Rear TIME 172 Exercise 20 EP bl aa a 173 Exercise 2 E T2C interiasecc istae AR een ated tedio aoa eda aie du eara 174 Eu l b ban pt 175 Exereisc o O nn 176 Exercise 23 Analog To Digital 177 Exercise 24 Digital to Analogue Converter essere 178 Exercise 25 Transinitting CAN Data cii a a Ee dM 179 Exercise 20 Recertvinp CAN Dat o su tipa re eon Dust IUNII USE acacia 180 Chapter 6 Tutorial With GNU 2222 22 182 Initia me s d s y 182 GUC Startup Code m EE HII NEM ide 182 Interworking ARM THUMDB Code ia 182 ACCESSING Peripherals ios eain e iet da EI MEI Ete Rd HE E OU 182 Interrupt SEFVICE ROUTINES e 182 DOLD abe 183 TUS QUII RII 183 Exercise 1 Using The Keil Toolset With The GNU Compiler 184 Exercise 2 startup Code e re erase
141. ks which have to reliably transfer small amounts of critical data between nodes ISO 7 Layer Model In the ISO seven layer model the CAN protocol covers the layer two data link layer 1 e forming the message packet error containment acknowledgement and arbitration Object layer Application Lay er Prioritizer Message Handling Acceptance filtering Presentation Layer Transfer Layer Session Laver Fault confinement Error detection Acknowledgement Message framing Arbitration Transport Layer Network Layer Physical layer Data Link Layer Bit representation Transter rate Physical Laver Signal level and timing os Transmission medium CAN does not rigidly define the layer Physical layer so CAN messages may be run over many different physical mediums However the most common physical layer is a twisted pair and standard line drivers are available The other layers in the IOS model are effectively empty and the application code directly addresses the registers of the CAN peripheral In effect the CAN peripheral can be used as a glorified UART without the need for an expensive and complex protocol stack Since CAN is also used in Industrial Automation there are a number of software standards that define how the CAN messages are used to transfer data between different manufacturers equipment The most popular of these application layer standards are CANopen and Device net The sole purpose of these standards is to p
142. l with the ARM instructions which can use the condition codes to iron out small branches in order to keep the code flow largely linear In the case of small loops and jumps the MAM has branch and trail buffers that hold recently loaded instructions which can be re executed if required 46 Introduction to the LPC2000 3 System Peripherals The complexities of the MAM are transparent to the user and it is configured by two registers the timing register and the control register There are some additional registers to provide runtime information on the effectiveness of the MAM The timing register 1s used to control to relationship between the CPU clock and the FLASH access time By writing to the first three bits of the timing register you can specify the number of CPU clock cycles required by the MAM to access the FLASH As the FLASH has an access time of 20 MHz and the CPU clock can be set to a maximum of 60MHz the number of cycles required to access the FLASH is 3 So for each three CPU cycles we can load four instructions which keep the MAM ahead of the game The MAM configuration register is used to define the operating mode of the MAM Fully Enabled Sequencial Code Branches amp Code Data MAM Disabled Instruction prefetch enabled All code amp data present in latches Instruction prefetch enabled On reset the MAM is disabled and all access to code and constant data are made directly to the FLASH It is possible to partially
143. liography Chapter Two is a description of how to write C programs to run on an ARM7 processor and as such describes specific extensions to the ISO C standard which are necessary for embedded programming In this book a commercial compiler is used in the main text however the GCC tools have also been ported to ARM Appendix A details the ARM specific features of the GCC tools Having read the first two chapters you should understand the processor and its development tools Chapter Three then introduces the LPC2000 system peripherals This chapter describes the system architecture of the LPC2000 family and how to set the chip up for its best performance In Chapter Four we look at the on chip user peripherals and how to configure them for our application code Throughout these chapters various exercises are listed Each of these exercises are described in detail in Chapter Five the Tutorial section The Tutorial contains a worksheet for each exercise which steps you through an important aspect of the LPC200 All of the exercises can be done with the evaluation compiler and simulator which come on the CD provided with this book A low cost starter kit is also available which allows you to download the example code on to some real hardware and prove that it does in fact work It is hoped that by reading the book and doing the exercises you will quickly become familiar with the LPC2000 Introduction to the LPC2000 Introduction Introduction to the
144. llator will start to resonate When its cycles become strong enough to drive the chip the wake up timer will count 4096 cycles before initialising the FLASH memory and resuming program execution This ensures the minimum restart delay after a power down or chip reset It 1s also possible to power down an individual peripheral if it is not being used via its power control bit in the PCONP register A few peripherals cannot be powered down these are the Watchdog GPIO pin connect block and the system control block Your code can optimise the configuration of the LPC2000 for minimum power consumption for a given application Some unofficial power consumption figures are given below LPC2106 60MHz 30mA Power down 10 15uA LPC2129 60MHz 55mA 60MHz VPBDIV 4 40mA During development it is likely you will be using a JTAG development tool connected to the ARM7 via a dedicated serial link If you place the CPU into Idle or Power Down mode no further debugging will be possible until the CPU is woken up 65 Introduction to the LPC2000 3 System Peripherals LPC2000 Interrupt System In the C code section we saw how to deal with ARM 7 exceptions for an undefined instruction a memory abort and a SWI instruction In this section we will look at the remaining two exception sources the General Purpose Interrupt IRQ and Fast Interrupt FIQ These two exceptions are used to handle all the interrupt sources external to the ARM7 CPU In the case
145. low GPIO PIN Each GPIO pin is controlled by a bit in each of the four GPIO registers These bits are data direction set and clear vol and pin status The IODIR pin allows each pin to be individually configured as an input 0 or an output 1 If the pin is an output the IOSET and IOCLR registers allow you to control the state of the pin Writing a 1 to these registers will set or clear the corresponding pin Remember you write a 1 to the IOCLR register to clear a pin not a 0 The state of the GPIO pin can be read at any time by reading the contents of the IOPIN register A simple program to flash the LED on the evaluation board is shown below int main void unsigned int delay unsigned int flasher 0x00010000 define locals TODIRI x00FF0000 set all ports to output while 1 for delay 0 delay lt 0x10000 delay t simple delay loop 7 TOCLRI flasher clear output pins IOSET1 flasher set the state of the ports flasher flasher 1 shift the active led if flasher amp 0x01000000 flasher 0x00010000 Increment flasher led and test for overflow 78 Introduction to the LPC2000 4 User Peripherals Exercise 15 GPIO This simple exercise demonstrates using the GPIO as an LED chaser program General Purpose Timers The LPC2000 have a number of general purpose timers The exact number will vary depending on the variant but there are at least t
146. m fe Erase Sectors M Verify Start Ox4 0000000 Size Ox0800 C DonotErase T Reset and Run gt Programming Algorithm Device Size Address Range AM23 SUUBT Dual Flash Est Flash 32 bit eM 60000000 S TFFFFFH With this configuration using the debugger with the JTAG and external flash becomes seamless 156 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 10 Phase Locked Loop In this exercise we will configure the operation of the PLL to give maximum speed of operation for the ARM 7 core for a 12 00MHz oscillator We will also configure the VLSI bus to run at half the speed of the ARM7 core Using Cclk M x OSC calculate the maximum integer value for M given that OSC 12 00 MHz and Cclk 2 60 MHz Using celk x 2 x P calculate a suitable value for P using the result for Celk calculated above and were 156 MHz Fcco 320MHz Using the results for M and P calculate the value for PLLCFG answer M 5 and P 2 Calculate the value for VPBDIV to set Pclk at half the frequency of Cclk Open the project in C work EX7 PLL Complete the code in main as follows Set multiplier and divider of PLLin PLLCFG to give 60 00 MHz PLLCFG 0x00000024 Enable the PLL in PLLCON PLLCON 0x00000001 Update the internal PLL registers with the feed sequence PLLFEED PLLFEED X Q0000AA 0x00000055 Test the Lock bit in PLLSTAT until the PLL is stable while PLLSTAT amp 0x00000400
147. maximum 60 MHz It is controlled by the constants M and P 60 Introduction to the LPC2000 3 System Peripherals Within the PLL are two constants which must be programmed in order to determine the clock for the CPU and AHB This clock is called Cclk The first constant is a straightforward multiplier of the external crystal The output frequency of the PLL is given by Cclk M x Osc In the feedback path of the PLL is a current controlled oscillator which must operate in the range 156MHz 320 MHz The second constant acts as a programmable divider which ensures that the CCO is kept in specification The operating frequency of the CCO is defined as Feco Cclk x 2 x P On our development board there is a 12MHz oscillator so to reach the maximum CPU frequency of 60MHz M Cclk Osc 60 12 5 And then for P 156 lt 320 60 x 2 xP By inspection P 2 The programming interface for the PLL is shown below PLL Register The PLL control registers can be programmed at any time but the new values will not take effect until a correct feed sequence has been written to PLL FEED PLL FEED The values written to the user SFRs are not transferred to the internal PLL registers until a feed sequence is written to the PLL feed register Once you have updated the PLLCON and PLLCFG registers you must write X000000AA followed by 0x00000055 the PLLFEED register These values must be written on consecutive cycles
148. mor COM Ae iesene m n n 115 CAN Message RECEptlOn pets orna ER a A a 118 Acceptance TION O enar E E E Aq 119 Conneurne The AcceptanCe Ferid n dtes erede p eI EUR 120 U M 122 Chapter Keil LUutortal asoioreseee eoe aenea adea eue dea da epa auo 124 Installation E M audi 124 Usuie the Kew UU VISION TDE ed setup taie b aad eti dog emacs 125 Exercise I Usine tne Keil 06166 Ioa ieee C edito 126 LOS ra The Dro pondus 133 Using The ULINK Hardware 2522 22 138 Setting up the ULINK JT AG hardware debug get ee 138 Exercise 141 Exercise e Usme 142 Exercise 4 Using S DDIO xalama ret bes dus metus 144 Exercise 2 3 Imiple 146 Exercise G SOltw are Inte tPupL edet aote ent de ivi ea etes En ih Yaa Late dida 148 Exercise 7 Memory Accelerator 12 149 Exercise 8 In Application 152 Exercise 9 External BUS Interface i oen won raise ta e teres 153 Exercise TU Phase Locked EO0pzidssen ee ie Mus tideba abore sl 157 Exercise 11 East Interr pt iae ce Re m aldada 159 Exercise 12 Vectored Interr pt 22er obo da 160 Exercise 15 2 Nom Vectored Menu pt acneei i do o ai 162 Exerc
149. n EX12 Interrupt vectored work Configure the external interrupt as an FIQ by programming the IntSelect register VICIntSelect 0x00008000 Compile the code and start the debugger and check the interrupt works as in exercise 5 The name of the FIQ ISR must match the name in the vector constant table in startup s The default name given by Keil is FIQ Handler If you are using the simulator the interrupt can be triggered by setting pin 0 14 low in the peripherals GPIO window or by using the Generate EINTI button in the toolbox 159 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 12 Vectored Interrupt In this exercise we will configure a IRQ source to be handled as a vectored interrupt by the VIC We will use the same external interrupt as exercise 9 but this time it will have its own dedicated ISR to give faster servicing of the interrupt request Open the project in C work EX11 Interrupt vectored Configure slot 0 in the VIC to service the EINTI interrupt VICVectCnt10 0x0000002F Place the address of the dedicated external interrupt routine in the correct vector address register VICVectAddrO unsigned EXTINTVectoredIRQ Complete the code in the EXTINTVectored to cancel the interrupt EXTINT 0x00000002 VICVectAddr 0 00000000 Compile the code and start download it into the debugger Run the code and check that the interrupt is entered correctly and that it only runs once for each press of the
150. n a single cycle Exception LDA PC PC OxFF 0 As we are on the IRQ we know the address is 0x00000018 8 for the pipeline If we deduct OxFFO from this it wraps the address round the top of the 32 bit address space and loads the contents of address OXFFFFFF020 the Vector Address Register 0x00 IRQ Interrupt Vector 0x0000 0018 When an IRQ exception occurs the CPU LDR PC PC FFO Load Contents of Location executes the instruction LDA PC PC z OxFFO0 0x18 FFO PC into PC which loads the contents of the vector address register into the PC forcing a jump to the ISR OxFFFF 020 Vector Address Register OxFFFF FFF 71 Introduction to the LPC2000 3 System Peripherals Leaving An IRQ Interrupt As in the FIQ interrupt you must ensure that the interrupt status flags are cleared in the peripheral which generated the request In addition at the end of the interrupt you must do a dummy write to the Vector Address Register This signals the end of the interrupt to the VIC and any pending IRQ interrupt will be asserted Write gt Vector Address Register At the end of a vectored IRQ interrupt you must make a dummy write to the Vector Address Register in addition to clearing the peripheral flag to clear the interrupt Clear gt Peripheral Interrupt Register Example Program IRQ interrupt This example is a repeat of the FIQ example but demonstrates how to set up the VIC for a vectored RQ interrupt The vector
151. n also directly control the logic level on the match pin by directly writing to the first four bits in the register EMR Contact Bits External Motel U 00 Do Nothing 01 Clear Pin 10 Set Pin 11 Toggle Pin External Matcl 3 The external match register contains a configuration field for each match channel Programming this field decides the action to be carried out on the match pin when a match event occurs In addition each match pin has a bit that can be directly programmed to change the logic level on the pin The example below demonstrates how to perform simple pulse width modulation using two match channels Match channel zero is used to generate the period of the PWM signal When the match event occurs the timer is reset and an interrupt is generated The interrupt is used to set the Match 1 pin high Match channel is used to control the duty cycle When the match 1 event occurs the Match 1 pin is cleared to zero So by changing the value in the Match 1 register it is possible to modulate the PWM signal int main void VPBDIV 0x00000002 Configure the VPB divi PINSELO 0x00000800 Matchl as output TOPR 0x0000001E Load presaler TOTCR 0x00000002 Reset counter and presale TOMCR 0x00000003 On match reset the counter and generate an interrupt TOMRO 0x00000010 Set the cycle time 1 0x00000008 Set 505 duty cycle TOEMR 0x00000042 On match clear MATI and
152. n the project in C work EX8 IAP Add the following lines of code to main c command 0 0x36 lap command result OX7FFFFFFO Add the following lines to API c pragma asm Mow TLSE move entry address into PC pragma endasm Now make sure that main is compiled as ARM code and API is built as Thumb code Build the code and start the debugger Run the code up to the first call to the TAP function Set a breakpoint on the line of code after this function Step into the IAP function Look at the contents of RO R2 These registers should contain the addresses of the command table the results table and the entry address of the bootloader functions Also R14 should contain the return address to the main function Step the line of assembly code which will jump you to Ox7FFFFFFF This 15 the entry to the bootloader code Now run the code at full speed it will execute the bootloader function called and return to the address held in R14 the next line in main c When the code hits the breakpoint examine the CPSR to see which instruction set is now being used Take a look at the result table and read the PartID number returned by the bootloader Compare this to the value returned in the previous example Run the next call to the Bootloader API and check that the correct bootloader version 1s returned 152 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 9 External Bus Interface This exercise demonstrat
153. n this slot within the transmitting CAN packet In practice the transmitter sends a recessive bit and any node which has received the CAN message up to this point will assert a dominant bit on the bus thus generating the acknowledge This means that the transmitter will be happy if just one node acknowledges its message or if 100 nodes generate the acknowledge So when developing your application layer care must be taken to treat the acknowledge as a weak acknowledge rather than confirmation that the message has 107 Introduction to the LPC2000 4 User Peripherals reached all its destination nodes After the acknowledge slot there is an end of frame message delimiter It is also possible to operate the CAN bus in a master slave mode A CAN node may make a remote request onto the network by sending a message packet which contains no data but has the RTR bit set The remote frame is requesting a message packet to be transmitted with a matching identifier On receiving a remote frame the node which generates the matching message will transmit the corresponding message frame Remote Transmit request The RTR frame is R Identifier RTR DLC CRC ACK EOF used to request message packets from the network as a master slave transaction As previously mentioned the CAN message identifier can be up to 29 bits long There are two standards of CAN protocol the only difference being the length of the message identifier 2 0A Has an 11 bit ide
154. n value for Chipselect zero of 0x20000000 In the case of the RAM it has a 70ns read and write time Consequently at 60M Hz the read and write waitstate WSTI and WST2 should be set to 5 Cclk cycles with IDCY set to one cycle As the RAM is a byte partitioned device the byte lane control must be enabled by setting RBLE to one And again the bus width must be set to 32 bits This gives us a chipselect configuration value of 0x20001440 These values can be configured with the graphical editor in the Keil startup code Stack Configuration Stack Sizes in Bytes PLL Setup Setup External Memory Controller EMC Bank Configuration 0 BCFGD T IDCY Idle Cycles a VEST Wait States 1 WST2 Wait States 2 RBLE Read Byte Lane Enable WP Write Protect BM Burst ROM i MMV memor Width El Bank Configuration 1 61 IDC Idle Cycles VEST Wait States 1 VEST Wait States 2 gt RBLE Read Byte Lane Enable WP Write Protect _ BM Burst ROM i MM Memory Width El Bank Configuration 2 2 UIS 11877 4611112774444 E Bank Configuration 3 BCFG3 Booting From ROM By default the LPC22xx devices will boot from their internal FLASH memory and can access the external memory once the chipselects are configured However if the external bootpins are pulled low the chip will boot from external memory In this case Chipselect zero will be enabled in the bus width selected by the boot pi
155. n whether the device is operating in master or slave mode The diagram below shows a typical configuration for connecting to an EEROM device Mode Fault Transfer Complete SPI EEROM peripheral This diagram shows how to interface 25AAT60N IOSI an external EEROM onto the SPI bus eb m of the LPC2000 It should be noted Tm 2 that pins PO 7 and P0 20 must be 54 pulled high to enable the SPI peripheral as a master SPI Master Slave Selection J620 J1X2 The programmers interface for the SPI peripheral has five registers The clock counter register determines the baud rate Pclk is simply divided by the value in the clock counter to give the SPI bit rate This register must hold a minimum value of eight The control register 99 Introduction to the LPC2000 4 User Peripherals is used to configure the operation of the SPI bus Because of the simple nature of the SPI data transfer and the wide range of SPI peripherals available the SPI clock and data lines can be configured to operate in several different configurations Firstly the polarity and phase of the clock must be defined The polarity can be active high or active low as shown below and the clock phase can be edge or centre aligned Ul Ul L se C POL 0 CPMA 1 J bo Finally the data orientation may also be defined as the most significant bit transferred first or the least significant bit transferred first LSB
156. ncy for the vectored interrupt plus the time taken to read the IRQstatus register and decide which routine to run FIQ Interrupt Sync Worst Case Instruction execution Entry to first Instruction FIQ Latency 12 cycles 200 nS 60MHz IRQ Interrupt sync worst case instruction execution Entry to first instruction Nesting IRQ Latency 25 cycles 416nS 60MHz 74 Introduction to the LPC2000 3 System Peripherals Nested Interrupts The interrupt structure within the ARM7 CPU and the VIC does not support nested interrupts If your application requires interrupts to be able to interrupt ISRs then you must provide support for this in software Fortunately this is easy to do with a couple of macros Before discussing how nested interrupts work it is important to remember that the IRQ interrupt is disabled when the ARM7 CPU responds to an external interrupt Also on entry to a C function that has been declared as an IRQ interrupt routine the LR isr is pushed onto the stack IRQ Mode System Mode Two macros can be used to allow nested interrupt processing in the LPC2000 for a very small code and time overhead Once the processor has entered the IRQ interrupt routine we need to execute a few instructions to enable nested interrupt handling First of all the SPSR_irq must be preserved by placing it on the stack This allows us to restore the CPSR correctly when we return to user mode Next we must enable the
157. nd decode the message identifier in order to decide what to do with the message In order to overcome these problems the LPC2000 CAN controllers have a sophisticated acceptance filtering scheme The acceptance filter 1s used to screen messages as they come in from the CAN bus The acceptance filter can be programmed to pass or block message identifiers before they enter the CAN controller for processing This prevents unwanted messages entering the CAN receive buffer and consequently greatly reduces the overhead on the CPU The acceptance filter has 2K of RAM 512 x 32 which may be allocated into tables of identifiers This allows ranges of messages and individual messages to be able to enter into the CAN receive buffer 5 If enabled generate and Rx IRQ IRQ Can message 15 received Acceptance filters 3 On Match load the message utet TOE CAN TOOU ES ONEAN 0 D UAM into the RX buffer Se which is used to set up filter tables to efficiently handle high bus loadings without overloading the CPU 4 Load the INDEX value 2 Scan against Acceptance into the RFS register tables As a message passes through the acceptance filter it is assigned an ID Index This is an integer number that relates to the message ID s offset in the acceptance filter table This number is stored in the RX Frame Status register So rather than decode the raw message ID it is easier and faster to use the index value to decide what message has
158. nd receive error counters can be read in the Global Status Register Also in this register are two error flags the Bus Status flag will be set when the maximum error count is reached and the CAN controller is removed from the bus The second error flag 1s the Error Status flag which is set when the CAN error counters reach a warning limit This warning limit is an arbitrary value that is set by writing a value into the Error Warning limit register The default value in this register 1s 96 Like the bit timing registers the EWL 117 Introduction to the LPC2000 4 User Peripherals register may only be modified when the CAN controller is in reset In addition the Interrupt Capture Register provides extensive diagnostics for managing events on the CAN bus The CAN controller has the following interrupt sources ud dic Transmit interrupt one for each buffer Receive interrupt Error Warning Data overrun Wake up Error Passive Arbitration lost Bus error ID ready CAN Message Reception Once initialised the CAN controller 1s able to receive messages into its receive buffer This is similar in layout to the transmit buffers CAN RFS Reciever Frame Status CAN RID Recieved Identifier CAN RDA Recieved Data 1 4 CAN RDB Recieved Data 5 8 The Rx Frame Status register is analogous to the Tx Frame information register However it has two additional values These are the ID Index and the BP bit and these will be explained
159. nd sector number G address Mode Erase sector s E start sector number end sector number Blank check sector s start sector number end sector number Read Part ID x IS Read Boot code version M address address2 number ofbytes gt Philips provide a ready made FLASH In System Programming utility for the PC which can be used to program the development board This tool automatically calculates and adds the program signature to your code to ensure that your program will run If you are using this tool to program the FLASH your code should have a NOP instruction on the unused vector for this tool to work correctly Exercise 7 Memory Accelerator Module and Flash programming Utility This exercise describes the use of the Philips Flash programming tool to load a simple program into the LPC2000 This program runs without the MAM switched on By adjusting the A D value the MAM is enabled so we can see the performance increase caused by this important peripheral 52 Introduction to the LPC2000 3 System Peripherals In Application Programming It is also possible to reprogram the FLASH memory from within your program All of the bootloader commands are available as an on chip API and can be called by your code To access the bootloader functions you must set up a table in RAM which contains a command code for the function you want to use followed by its parameters The start add
160. nditions and to check the status of the receive and transmit FIFOS Keceive Data ready Overrun error Parity error Framing error UART Line Status Register The LSH contains flags which indicate Transmitter holding register empty events within the UART It may be Transmitter empty polled or should be read after a Eror in Rx FFO UART interrupt is generated Break interrupt The UART has a single interrupt channel to the VIC but three sources of interrupt UART interrupts can be generated on a change in the Receive line status So 1f an error condition occurs an interrupt is generated and the LSR can be read to see what is the cause of the error The remaining two interrupt sources are receive and transmit interrupts The receive interrupt is triggered by characters being received into the RX FIFO The depth at which the interrupt is triggered is set in the UART FIFO control register UAHT RX FIFO Each UART has a sixteen byte A receive FIFO which can be programmed to 8 generate an UART interrupt at various trigger Lossesewotarta levels The character timeout interrupt can be used 16 Bytes dii to read bytes which do not reach a trigger level trigger level 4 1 Y The receive interrupt can be set to trigger after it has received 1 4 8 or 14 characters So if the interrupt is set to trigger when eight characters are in the buffer and a total of 34 characters are sent then four interrupts will
161. ne and so will use the correct return mechanism Other types of interrupt are supported by the keywords IRQ SWI ABORT As well as declaring a C function as an interrupt routine you must link the interrupt vector to the function Vectors LDR PC Reset Addr LDR PC Undef Addr LDR PC SWI_Addr LDR PC PADt Adar LDR PC DADE Adar NOP Reserved Vector LDR PC TRO ACE LDR PC PC Ox0FFO Vector from VYicVectAddr LDR PC FIQ Addr Reset_Addr DD Reset Handler Undef Addr DD Undef Handler A SWI Addr DD SWI Handler A PAbt Addr DD PAbt Handler A DAbt Addr DD DAbt Handler A DD 0 Reserved Address IRQ Addr DD IRQ Handler A FIQ Addr DD FIQ Handler A The vector table is in two parts First there is the physical vector table which has a Load Register Instruction LDR on each vector This loads the contents of a 32 bit wide memory location into the PC forcing a jump to any location within the processor s address space These values are held in the second half of the vector table or the constants table which follows immediately after the vector table This means that the complete vector table takes the first 64 bytes of memory The Keil startup code contains predefined names for the Interrupt Service Routines ISR You can link your ISR functions to each interrupt vector by using the same name as your C function name The table below shows the constants table symbols and the corresponding C function prototypes which
162. ng any code which is on the chip will be run as normal Once the ULINK gets back control of the chip it performs a soft reset by forcing the PC back to address zero However the on chip peripherals are no longer in the reset condition ie peripherals will be initialised interrupt enabled etc You must bear this in mind if the application you are developing could be adversely affected by this A quick solution is to place a simple delay loop in the startup code or at the beginning of main After a reset occurs the CPU will be trapped in this loop until the ULINK regains control of the chip None of the application code will have run leaving the LPC2000 in its initialised condition Summary So by the end of this section you should be able to set up a project in the Keil uVISION IDE select the compiler and LPC2000 variant you want to use configure the startup code be able to interwork the ARM and THUMB instruction sets access the LPC2000 peripherals and write C functions to handle exceptions With this grounding we can now have a look at the LPC2000 system peripherals 40 Introduction to the LPC2000 2 Software Development 41 Introduction to the LPC2000 3 System Peripherals Chapter 3 System Peripherals Outline Now that we have some familiarity with the ARM7 core and the necessary development tools we can begin to look at the LPC2000 devices themselves In this section we will concentrate on the system peripherals th
163. ng the external interrupts can only trigger on a logic zero level If the power down mode is being used the EXWAKE register can enable an interrupt to wake up the CPU So to set up a simple interrupt source program configure the EINTI interrupt to be level sensitive and then connect it to the processor pin via the pinselO register 66 Introduction to the LPC2000 3 System Peripherals The external interrupt pins are an easy to configure interrupt source when first experimenting with the LPC2000 interrupt structure Power Control PINSEL Interrupt Structure The ARM7 CPU has two external interrupt lines for the fast interrupt request FIQ and general purpose interrupt IRQ request modes As a generalisation in an ARM7 system there should only be one interrupt source which generates an FIQ interrupt so that the processor can enter this mode and start processing the interrupt as fast as possible This means that all the other interrupt sources must be connected to the IRQ interrupt In a simple system they could be connected through a large OR gate This would mean that when an interrupt was asserted the CPU would have to check each peripheral in order to determine the source of the interrupt This could take many cycles Clearly a more sophisticated approach is required In order to handle the external interrupts efficiently an on chip module called the Vector Interrupt Controller VIC has been added The VIC provides addit
164. ng CAN Data This 1s the same code as in the previous example but this time it 1s presented from the receive point of view Open the project in C work EX24 CANRX In main c add the following lines to configure the acceptance filter to receive messages Declare an array in the filter memory unsigned int StandardFilter 2 xE0038000 Configure the standard message filter table AFMR 0x00000001 StandardFilter 0 0x20012002 StandardFilter 1 Ux 20032004 SFF_sa 0x00000000 SFF GRP sa 0x00000008 Release the receive buffer before leaving the ISR CICMR 0x00000004 Build the code and start the debugger Run the code as far as initialising the CAN peripherals Examine the Acceptance filter memory in peripherals CAN Acceptance filter This view shows you which messages may be received by the CAN peripherals Continue to run the code and receive a message Check that the message ID matches the Index assigned in the Acceptance filter 180 Introduction to the LPC2000 5 Tutorial With Keil Tools 181 Introduction to the LPC2000 6 Tutorial With GNU Tools Chapter 6 Tutorial With GNU Tools Intoduction The following tutorial demonstrates how to setup a project in uVISION for the GNU compiler Exercises 1 6 are repeated to show the non ANSI aspects of the GNU compiler Once you are familiar with these exercises you can rejoin the main tutorial but use the exercise examples in the GCC directory GCC St
165. ngle ISR The address of this ISR is stored in an additional vector address register called the default vector address register If an interrupt is enabled in the VIC and is not configured as an FIQ or does not have a vectored interrupt slot associated with it then it will act as a non vectored interrupt When such an interrupt is asserted the address in the default vector address is loaded into the vector address register causing the processor to jump to this routine On entry the CPU must read the IRQ status register to see which of the non vectored interrupt sources has generated the exception Default Vector Address Exception The non vectored interrupt has one vector address slot that will jump all 51 non vectored interrupt sources to one Vector Address default ISR Leaving A Non Vectored IRQ nterrupt As with the vectored IRQ interrupt you must clear the peripheral flag and write to the vector address register Example Program Non Vectored Interrupt void main void TODIRI 0x000FF000 Set the LED pins as outputs PINSELO 0x20000000 Enable the EXTINTO interrupt VICDefVectAddr unsigned NonVectoredIRQ pass the address of the IRQ into the VIC slot VICIntEnable 0x8000 Enable EXTINTO in the VIC while 1 Vectors LDR PC Reset Addr LDR PC Undef Addr LDR PC SWI Adar LDR PC PAbt_Addr LDR PC DAbt_Addr NOP LDR PC PC 2 0 0 Vector from VicVectAddr LDR PC FIQ Addr 73 Introdu
166. nly required on the function prototype and should not be used on the main body of the function An interrupt service routine is shown in example 5 182 Introduction to the LPC2000 6 Tutorial With GNU Tools Software Interrupt There is no real software interrupt support in the GCC compiler To generate a software interrupt you must use inline Assembler as shown below define SoftwareInterrupt2 asm swi 02 This will place a SWI instruction encoded with the value 2 in your code Next it is possible to declare a pointer to a CPU register using the non ANSI register keyword as shown below bequster Unsigned Line ptr asm r14 This allows us to read the contents of the link register when we enter the ISR When the SWI instruction is executed the CPU will enter supervisor mode and jump to the SWI vector The address of the SWI instruction plus four will be stored in the link register On entry to the software interrupt ISR the following line of code is executed temp link ptr 1 amp OxOOFFFFFF The address stored in the link register 1s rolled back by one instruction word wide pointer i e four bytes so that it 1s pointing at the address of the SWI instruction which generated the exception The top eight bits of the SWI instruction are masked off and bits 0 23 are copied into the temp variable This in effect loads the number 2 into the temp variable A switch statement can now be used to run the desired code This meth
167. ns Its waitstate parameters will default to 34 Cclk cycles for WSTI and WST2 and 16 CcIk cycles for the IDCY This ensures that the accesses on Chipselect zero will be slow enough to interface with any external device When booting from an external device is selected the value in the MEMMAP register will be set to 0x3 boot from external FLASH and the first 64 bytes of external memory on Chipselect will appear at Zero This means that you must build your 58 Introduction to the LPC2000 3 System Peripherals code so that the interrupt vector table and the constants table are located from address 0x80000000 In practice this means changing the start address to 0x80000000 instead of 0x0000000 In the Keil startup code this is done by an assembler directive which is used to relocate the CODE BASE segment containing the vector table SIF EXTERNAL MODE CODE BASE EQU 0x80000000 SELSE CODE BASE EQU 0x00000000 SENDIF AREA OIARILUPLCODE CODE AT CODE BASE READONLY ALIGN 4 PUBLIC startup The define EXTERNAL_MODE is declared in the assembler local options menu as shown below Properties Asm Conditional assembly control Symbols E MIEXTERNAL M DE Macro processor Standard Case sensitive symbols Include Paths Misc Controls Assembler SET EXTERNAL MODE DEBUG PRINT sphysStartup Ist EP A control string xl Once we have our program ready to run from external FLASH there is a slight chi
168. nterrupts are switched on and that our program is correctly located on the interrupt vector Open the project in EX2 Startup work Open the file Startup s and using the graphical editor configure the operating mode stacks as follows ily Stack Configuration T p of Stack Address Ox4000 4000 Ox0000 0050 0 0000 0050 0 0000 0050 0 0000 0050 0 0000 0050 0 0000 0400 T Supervisor Mode Abort Made 2 Fast Interrupt Mode Interrupt Made m User System Mode rr PLL Setup Compile the code v Start the simulator and when the PC reaches main examine the contents of each R13 regi ster 68 0 00000000 7 R3 0 00000000 ZEE R10 40003880 77 R11 000000000 hiz 000000000 oe 13 5 Os40003d80 em 14 112 00000000 E m Fast Interrupt ei 0 00000000 1 RS 000000000 7 7 R10 0 00000000 EE R11 0 00000000 ul Ox00000000 2 2 FT315P 04000300 Each stack is allocated a space of 0x80 The user stack is 0x400 77 RTAILR DXODUUDUQU bytes so user data will start at 0 40003080 0x400 OBL SPSR 000000000 E m Interrupt 13 5 Ou0003e80 oe AIA 0400000000 EH SPSR 000000000 E zd Supervisor oe 13 5 0 40003200 ve AIA LR 0400000000 Be SPSR 0 00000000 El Abort ve 13 5 024000380 AIALA 0400000000 SPSR 0 00000000 Start of stack space at the top of on chip memory Fl Undefined oe 13 5 Os40004000 ven 614 0400000000 199 ps SPSR 0 00000000 Introduction t
169. ntifier 2 0B Passive Has an 11 bit identifier 2 0B Active Has a 29 bit identifier It is possible to mix the two protocol standards on the same bus but you must not send a 29 bit message to an 2 0A device Frame with Frame with 11 bit ID 29 bit ID V2 0B Active Tx Rx OK Tx Rx OK CAN Module 575 75 V2 0B Pass ve CAN Module Tx Rx OK Ignored V2 0A CAN Module Bus ERROR 108 Introduction to the LPC2000 4 User Peripherals CAN Bus Arbitration If a message is scheduled to be transmitted on to the bus and the bus is idle it will be transmitted and may be picked up by any interested node If a message 1s scheduled and the bus is active it will have to wait until the bus is idle before it can be transmitted If several messages are scheduled while the bus is active they will start transmission simultaneously once the bus becomes idle being synchronised by the start of frame bit When this happens the CAN bus arbitration will take place to determine which message wins the bus and is transmitted Node X AAAA Node A A NodeB 4 22 ULEELTITTITIITI Node C A CZYVVTTTTTTTTITI CAN arbitration Message arbitration guarantees that the most important message 122222 Arbitration phase of message frame will win the bus and be sent CLILITIIID Remainder of message frame without any delay Stalled A messages will then be sent in E LE haz order of priority lovvest value S identifier first Nod A 74
170. o Also the value for M is 5 bits long so the value for P is not on an even nibble boundary If you make a simple mistake setting up the PLL the whole chip may be running out of specification If the chip enters power down mode the PLL is switched off and disconnected A wakeup from power down does not restore the PLL so the sme startup sequence must be followed each time the chip exits the power down setting VLSI Peripheral Bus Divider The external oscillator or the output of the PLL is used as the source for the Cclk which is the clock source for the ARM7 CPU and the AHB bus The peripherals are on the separate VPB bus 10 Mhz 60 Mhz Processor clock CCLK The Output from the PLL is called Cclk and provides the clock for the CPU and AHB bus The VLSI bus clock is called Pclk and is derived from Cclk by the VPB divider Fosc 10 Mhz 25 Mhz Processor clock PCLK 2 5 60 Mhz 62 Introduction to the LPC2000 3 System Peripherals The clock on the VPB bus is called Pclk This clock is derived from Cclk via the VPB bridge The VPB bridge contains a divider which can divide down the Cclk by a factor of 1 2 or 4 The VPB divider register can be programmed by your application at any time At reset it is set to the maximum value of four so the Pclk is running at a quarter of the Cclk value at startup Currently all the peripherals on the LPC2000 derivatives can run at the full 60MHz so the VPB divider is principally used fo
171. o the LPC2000 6 Tutorial With GNU Tools Exercise 3 Using THUMB Code In this example we will build a very simple program to run in the ARM 32 bit instruction set and call a 16 bit THUMB function and then return to the 32 bit ARM mode Open the project in EX3 THUMB code work In the files browser select thumb c open the local menu right click and select options for thumb c 2 4 4 Flash 25 23 5 Source Group 1 26 extern void thumb function void Exterr Eee Ral fb Options For File thumb c h Open thumb c E Build target xi Translate C V Work ARMYPhilips Course Imageacc SRM ExercisesiEx3 Thumb Codetsalutienthumb c 7 di Manage Components Remove File thumb c Include Dependencies Select the CC tab and in the misc controls add mthumb or tick the compile thumb code box and click OK Options for File thumb c Properties Preprocessor Symbols Define Undefine Code Generation 7 Enable APCS ARM Procedure Call Standard Optimization lt default gt 2 7 Generate Stack Check Code Wamings default v F7 Support Calls between ARM and THUMB Instruction Set Strict ANSIC v Compile Thumb Code Include Paths E Misc Controls Compiler mepu arm7tdmi mthumb gdwarf 2 MD w 0 mapcs frame mthumb interwork control IC AKeilNARMNINCSFhilipss o thumb o string Cancel Defaults Again in the file browser
172. o use the simulator and single step in the disassembly window This way you can watch the program flow and the actions on the CPU registers To control the interrupt in the simulator open the peripherals GPIO port 0 window If you set the program running unchecking the Pin1 4 box will generate the interrupt You must raise the pin high again to stop interrupts General Purpose Input Output 0 GPIO 0 IPIE oino 0 00000000 E FT EHE osET0 0 o0000000 FTTTTTTT FTTTTTTT FTTTTTTT FTTTTTTT acmo oooog FTTTTTTT TTTTTTTT TTTTTTT FTTTTTTT Bis JOPINO 000004000 zi EP EE ER i epi pz eri eileen TONTSISTAISTSTS 1 1 421 1 1 Pins Ox00004000 Bae TTTTTITTTI Alternatively in the toolbox there is a Generate EINTI button This button will gene rate a simulated pulse onto the interrupt pin Toolbox with user Toolbox button configurable scripts Update windows Generate EINT 1 Within uVISION there is a full scripting language that allows you to simulate external events These scripts based on the C language and are stored in text files The script used to simulate the pulse is shown below signal void Toggle void PORTO PORTO 0x4000 twatch 200 PORTO PORTO 0x4000 KILL BUTTON DEFINE BUTTON GenerateEINT1 Toggle This script is stored in the file signal ini and is added to the project in the debug window For more details on the
173. od of handling software interrupts is shown in example 6 Inline Functions Within the GNU compiler functions may be declared as inline functions as follows inline int fast ftunction char param 183 Introduction to the LPC2000 6 Tutorial With GNU Tools Exercise 1 Using The Keil Toolset With The GNU Compiler This example is based on the source code which can be found in C Exercise Work EX1 first program In this first exercise we will spend some time defining a first project building the code and downloading it into the Simulator for debugging We will then cover the basic debugging functions of the Keil simulator The Keil uVISION IDE is designed to support several compilers the GNU C compiler the ARM development suite and the Keil ARM compiler Before compiling make sure you have the GNU compiler selected This is done by activating the project workspace right clicking and selecting manage components In this dialog select the Folders extensions tab and make sure the GNU tools box is selected Components Environment and Books 4 Project Components Folders Extensions Books Development Tool Folders Default File Extensions Use Settings from TOGLS INI k Tool Base Folder e Ms Iz MU Foe BIN CAKES RMNBINS El 77 INC Ea Object obi LIB Ezi Library lib Redfile A b l Document KANN Select ARM Development Tools Use K
174. of the LPC2100 these are the user peripherals In order to examine the LPC interrupt structure we need a simple interrupt source For this we can use the external interrupt pins which are the easiest peripheral to configure and EINTI is connected to a switch on the development board which allows us to trigger an interrupt at will and observe the results with the debugger Pin Connect Block All of the I O pins on the LPC2000 are connected to a number of internal functions via a multiplexer called the pin select block The pin select block allows a user to configure a pin as GPIO or select up to three other functions Pinsel 0 0 GP10 The Pinselect module allows each I O pin to be TXD multiplexed between one of four peripherals PWM 1 Reserved On reset all the I O pins are configured as GPIO The secondary functions are selected through the PINSEL registers The EINTI interrupt line shares the same I O pin as GPIO 0 14 and a UARTI control line So in order to use EINTI we must configure the pin select register to switch from the GPIO function to EINTI External Interrupt Pins The external interrupts are controlled by the four registers shown below The EXMODE register can select whether the interrupt is level or edge sensitive If an external interrupt is configured as edge sensitive the EXPOL register is used to qualify whether the interrupt is triggered on the rising or falling edge In the case of level sensitive triggeri
175. oftware Development Operating System Support If you are using an operating system for the LPC2000 the OS is likely to take care of the system stacks and context switching To avoid duplicating this by the compiler it is possible to declare a function as a task within the operating system This causes the compiler to just translate the code within the function and not to add the normal prologue and epilogue code which saves and restores registers to the stack A function may be declared as a task as shown below void AnalogueSample void task Fixing Objects At Absolute Locations The compiler also allows you to fix any C object such as a variable or a function at any absolute memory location The compiler has an extension to the C language as shown below int checksum at 0x40000000 Variables declared using this keyword cannot be initialised by the startup code You must also be careful to fix variables on the correct boundaries or you will get a memory abort For example 1f an integer is located at an uneven memory address Inline Assembler The compiler also allows you to use ARM or THUMB Assembler instructions within a C file This can be done as shown below asm mov r15 r2 This can be useful if you need to use features which are not supported by the C language for example the MRS and MSR instructions 38 Introduction to the LPC2000 2 Software Development Hardware Debugging Tools Phili
176. og timeout or pin 1 4 1s high then there is no external request to reprogram the FLASH However before handing over to the user application the bootloader will check to see if there is a valid user program in FLASH In order to detect if a valid program is present every user program must have a program signature This signature is a word wide number that is stored in the unused location in the ARM7 vector table at 0x00000014 The program signature is the two s compliment of the checksum of the ARM7 vector table FIQ UNUSED FQ IRQ UNUSED ABORT s UNDEF RESET SS gt Checksum E a The program signature is calculated as the two s compliment of the checksum of the vector table This signature must be stored in the unused vector at 0x00000014 or your j program will not run Zero When this value is summed with the program signature the result will be zero for a valid program If a valid program is detected the memory operating mode is switched to FLASH which restores the user vector table the program counter is forced to zero and the user application starts execution If there is no valid program then the bootloader enters its command handler So without the program signature your code will never run The program signature can be added to your startup code as shown below RESET LDR PC Reset_Addr LDR PC Undefined_Addr LDR PC SWI_Addr LDR PC Prefetch_Addr LDR PC Abort_Addr Lon
177. olling whether the watchdog generates an interrupt whether it generates a reset and a final bit which is used to enable operation of the watchdog Overflow Feed error Watchdog Timeout The watchdog mode register allows configuration the watchdog action on underflow reset or interrupt Reset Interrupt The Mode register also contains two flags the WDTOF is set when the watchdog times out and is only cleared after an external hard reset This allows your startup code to detect if the reset event was a power on reset or a reset due to a program error The Mode register also contains the watchdog interrupt flag This flag is read only but it must be read in order to clear the watchdog interrupt If you need to debug code with the watchdog active you should 88 Introduction to the LPC2000 4 User Peripherals not enable the reset option as this will trip up the JTAG debugger when the watchdog times out Once the watchdog timer constant and mode registers have been configured the watchdog can be kicked into action by writing to the feed register This needs a feed sequence similar to the PLL To feed the watchdog you must write OxAA followed by 0x55 If this sequence is not followed a watchdog feed error occurs and a watchdog timeout event 1s generated with its resulting interrupt reset It is also important to note that although the watchdog may be enabled via the watchdog mode register it does not start running until the fir
178. ompiler may be found in C keil ARM startup and for the GNU use the files in CAKkeilNGNUNstartup First of all the startup code provides the exception vector table as shown below EXTERN CODE32 Undef Handler A Declare the external C EXTERN CODE32 SWI Handier A EXTERN CODE32 PAbt Handler A CXC eption I outines EXTERN CODE32 DAbt Handler A P EXTERN CODE32 IRQ Handler A The suffix A denotes an EXTERN CODES FIG adlara ARM routine Vectors LDR PC Reset Addr LDR PC Undef Addr LDR PC SWI_Addr LDR PC PAbt_Addr I ETE M E LDR PC DAbt_Addr Unused vector this will become important later LDR PC IRQ Addr LDR PC FIQ Addr Reset Add DD Reset Handler Undef Addr DD Undef Handler A masada di s e TO SWI Addr DD SWI Handler A Constants table for ISR 000 E a d d re SS DAbt Add DD DaAhbt Handler A DD Reserved Address IRQ Addr DD IRQ Handlet FIQ Addr DD FIQ Handlet The vector table is located at 0x00000000 and provides a jump to interrupt service routines ISR on each vector To ensure that the full address range of the processor is available the LDR Load Register instruction is used This loads a constant from a table stored immediately above the vector table The vector table and the constants table take up the first 64 bytes of memory On the LPC2000 this first 64 bytes can be mapped from several 20 Introduction to the LPC2000 2 Software Development sources de
179. on the bus will be received e v v The Acceptance filter mode register provides global control of the 41 0 acceptance filter AccOFF ENABLE DISABLE ACCEPTANCE FILTER AccBP eFCAN ENABLES FULLCAN MODE 120 Introduction to the LPC2000 4 User Peripherals Once the acceptance filter is disabled each of the four filter tables may be configured The four tables are as follows Individual standard identifiers 11 bit ID Groups of standard identifiers 11 bit ID Individual Extended identifiers 29 bit ID Groups of extended identifiers 29 bit ID The acceptance filter RAM starts at OXE0038000 Each of the tables must be defined and fixed at absolute locations in the filter RAM The start address of each table should then be written into the relevant acceptance filter register The tables should start at the beginning of RAM and use the memory contiguously Finally the address of the last used location of RAM should be written into the End of Table register To enable the Acceptance filter set the ACCoff bit to logic one and AccBP bits to zero Each of the tables 1s constructed as follows 31 29 26 16 10 0 15 13 Controller Dis not Identifier able used The Individual Standard identifier table allows you to define individual 11 bit identifiers that will pass through the acceptance filter Each definition takes two bytes the first 11 bits contains the message identifier to be passed This is followed by a bit to dynamically en
180. on which caused the exception In this case we will ideally enter the data abort ISR sort out the problem with the memory and return to reprocess the instruction that caused the exception In this case we have to roll back the PC by two instructions Le the discarded instruction and the instruction that caused the exception In other words subtract eight from the link register and store the result in the PC For a data abort exception the return instruction is SUBS R15 R14 8 Once the return instruction has been executed the modified contents of the link register are moved into the PC the user mode 1s restored and the SPSR is restored to the CPSR Also in the case of the FIQ or IRQ exceptions the relevant interrupt is enabled This exits the privileged mode and returns to the user code ready to continue processing CPSR is restored trom USER IRQ the SPSK excep 2 The PC 1s restored from At the end of the exception the CPU returns to the Link register user mode and the context is restored by moving the SPSR to the CPSR R13 R ISR code restores R14 registers rom stack R15 15 Introduction to the LPC2000 1 The ARM7 CPU Core ARM 7 Instruction Set Now that we have an idea of the ARM7 architecture programmers model and operating modes we need to take a look at its instruction set or rather sets Since all our programming examples are written in C there is no need to be an expert ARM7 assembly programmer However an underst
181. ond to an I2C interrupt Next the pinselect block is configured to connect the I2C data and clock lines to the external pins Lastly we must set the bit rate by programming 125 and I2SCLL In both of these registers only the first 16 bits are used to hold the timing values The formula for the I2C bit rate is given as Bit Rate Pclk I2SCLH I2CSLL In the above example the PLL is not enabled and the external crystal is 14 7456MHz Hence the I2C bit rate 1s Bit Rate 14 7456 B 8 8 937500 Once configured the LPC2100 can initiate communication with other bus devices to read and write data as a bus master or receive and reply to requests from a bus master The contents of the I2C control register are shown below Remember this register 1s controlled by the CONSET and CONCLR registers 31 0 X NOU The control registers are used to r m ET 1 LL Dun awe bsc xui ess an aaa enable the I2C peripheral and interrupt denagem SEE UNSURE ACER See as well as controlling the I2C bus start stop and ack conditions 31 y x 0 I2CONCLR We will first look at the bus master mode To enter this mode the I2C peripheral must be enabled and the acknowledge bit must be set to zero This prevents the I2C peripheral acknowledging any potential master and entering the slave mode In the master mode the LPC2000 device 1s responsible for initiating any communication During a I2C bus transfer a number of bus event
182. one instruction Ris Mx 16 20 Introduction to the LPC2000 1 The ARM7 CPU Core Swap Instruction The ARM instruction set also provides support for real time semaphores with a swap instruction The swap instruction exchanges a word between registers and memory as one atomic instruction This prevents crucial data exchanges from being interrupted by an exception The swap instruction allows you to exchange the contents of two registers This takes two cycles but is treated as a single atomic instruction so the exchange cannot be corrupted by an interrupt This instruction is not reachable from the C language and is supported by intrinsic functions within the compiler library Modifying The Status Registers As noted in the ARM7 architecture section the CPSR and the SPSR are CPU registers but are not part of the main register bank Only two ARM instructions can operate on these registers directly The MSR and MRS instructions support moving the contents of the CPSR or SPSR to and from a selected register For example in order to disable the IRQ interrupts the contents of the CPSR must be moved to a register the I bit must be set by ANDing the contents with 0x00000080 to disable the interrupt and then the CPSR must be reprogrammed with the new value MSR _ CSPR SPSR The CPSR and SPSR are not memory mapped or part of the central register file The only instructions which R15 operate on them are the MSR and MR
183. one of 16 condition codes Hence each instruction has 16 different variants will only move 0x00800000 into the R1 if the last result of the last data processing instruction was equal and consequently set the Z flag in the CPSR The aim of this conditional execution of instructions 1s to keep a smooth flow of instructions through the pipeline Every time there is a branch or jump the pipeline is flushed and must be refilled and this causes a dip in overall performance In practice there is a break even point between effectively forcing NOP instructions through the pipeline and a traditional conditional branch and refill of the pipeline This break even point is three instructions so a small branch such as H f x 100 x r would be most efficient when coded using conditional execution of ARM instructions The main instruction groups of the ARM instruction set fall into six different categories Branching Data Processing Data Transfer Block Transfer Multiply and Software Interrupt 17 Introduction to the LPC2000 1 The ARM7 CPU Core Branching The basic branch instruction as its name implies allows a jump forwards or backwards of up to 32 MB A modified version of the branch instruction the branch link allows the same jump but stores the current PC address plus four bytes in the link register B 0x8000 0x400 PC 0x8000 LDA R2 10 0x8000 The branch instruction has several forms The branch ins
184. onfigure Flash Download x MV Erase M Verify Download Function v Program Reset and Run 54 RAM for Algorithm Start 1040000000 Size 0 0400 Programming Algorithm LPC2000 128kB Flash On chip Flash Start 0x00000000 Address Range 00000000 0001DFFFH Size o 0001 2000 Add Remove Help OK Switch from the simulator to the JTAG debugger Again open the options for target dialogue and select the debugger menu On the right hand side of the menu select the ULINK ARM7 Debugger from the dropdown menu and tick the Use radio button Options for Target Interworking D Asm LA Misc LA Locate Debug Utilities Device Target Output Listing C x C Use Simulator Settings Use ULINK ARM Debugger Settings v Load Application at Startup M Go till main Initialization File map ini E dit Restore Debug Session Settings V Breakpoints v Toolbox v wWatchpoints amp PA V Memory Display CPU DLL FARM DLL Parameter Dialoq DLL Parameter DAR MP DLL pLPC2232 V Load Application at Startup v Go till main Initialization File ELEM Restore Debug Session Settings V Breakpoints Watchpoints V Memory Display v Toolbox Driver DLL FARM DLL Parameter Dialoq DLL Parameter TARMP DLL pLPC2292 Cancel Defaults Help UVISION is now re
185. onitor can be used to provide on the fly updates as your code is running This process is pseudo real time in that the real monitor code interrupts your code and uses some processor time to read and communicate debug information to the PC 39 Introduction to the LPC2000 2 Software Development Important The JT AG and ETM tools simply provide a fairly dumb serial debug connection to the ARM7 core A generic ARM JTAG tool does not have any understanding of the overall LPC2000 architecture This means that a generic tool will always enter the bootloader after reset because it does not write the program signature into the FLASH this feature is discussed later and consequently will never run your code If you are new to the LPC2000 this 1s likely to catch you out and be very frustrating Since the Keil tools are developed for ARM7 based general purpose microcontrollers MicroVision uV STON understands the LPC2000 memory architecture and will debug the device seamlessly Even More Important As mentioned above the JTAG port is a simple serial debug connection to the ARM7 device It is very important to understand its behaviour during reset If the ARM7 CPU is reset all of the peripherals including the JTAG are reset When this happens the ULINK debugger loses control of the chip and has to re establish control once the LPC2000 device comes out of reset This will take a finite number of clock cycles While this is happeni
186. ownload Flash Save Hex File Fill Buffer Code Execution Address Range Fill Value FF sHOD000000 Selected Range Start amp HODDDD000 Run from Address 14 00000000 Thumb ARM Entire Buffer End amp HODDOD2DF LPC2000 Flash Utility Once the Target LPC2100 has been programmed the chip will automatically be rebooted and start to run your code Turn the potentiometer fully clockwise Reset the code and the LED s will start to sequence If you turn the potentiometer anticlockwise the mam will be enabled and you can see the LPC2000 turbo kick in In the ISP utility under the buffer option you can view a HEX dump of you program In this view the calculated program signature is also shown 150 Introduction to the LPC2000 5 Tutorial With Keil Tools If you reconnect the JTAG and start the debugger without downloading the program you can examine the interrupt vector table As we have programmed the flash with the Philips ISP tool the program signature has been added in location 0x00000014 which exists as a NOP in the startup code 151 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 8 In Application programming This example demonstrates how to call the bootloader API from within your application programs The code makes a call into the bootloader functions to run the Read Part ID function This example has only been built to work with the MCB2100 evaluation board Ope
187. pending on the operating mode of the LPC2000 This is discussed more fully later on The NOP instruction is used to pad out the vector table at location 0x00000014 which 1s the location of the missing vector Again this location 1s used by the LPC2000 bootloader discussed again later You are responsible for managing the vector table in the startup code as it is not done automatically by the compiler The startup code is also responsible for configuring the stack pointers for each of the operating modes Setup Stack for each mode LDR R Stack Enter Undefined Instruction Mode and set its Stack Pointer Switch mode and disable interrupts gt MSR CPSRc Load address into the stack pointer MOV 0 The six on chip stack pointers R13 are initialised at the top of on chip memory Care must be taken to allocate enough memory for the MSR CPSR lt maximum size of each stack MOV SP RO SUB R RO Calculate start address of next stack p SUB Enter Abort Mode and s t FIQ IRQ and supervisor stacks Enter User Mode and set its Stack Pointer MSR CPSR c Mode USR MOV SP RO Enter the C code LDR R0 C INIT TST RO 0 set INIT is Thumb Load an Exit address into the link register _____ LDREQ LR exit A ARM Mode Jump to the C init routine LDRNE LR exit T Thumb Mode BX RO Since each operating mode has a unique R13 there are effec
188. portant the interrupt Vector Control n Channel 0 Channel 4 Slot n l nna Each vector address slot may be assigned to any peripheral interrupt channel the lower the number of the vector address the higher its priority Channel 15 The other register in the VIC slot 1s the Vector Address Register As its name suggests this register must be initialised with the address of the appropriate C function to run when the interrupt associated with the slot occurs In practice when a vectored interrupt is generated the interrupt channel is routed to a specific slot and the address of the ISR in the slot s Vector Address Register is loaded into a new register called the Vector Address Register So whenever an interrupt configured as a vectored interrupt is generated the address of it s ISR will be loaded into a fixed memory location called the Vector Address Register 70 Introduction to the LPC2000 3 System Peripherals _ Say Vector Address When an interrupt occurs the vector address slot associated with the interrupt channel will transfer its contents to the vector address register 15 While this is happening in the VIC unit the ARM7 CPU is going through its normal entry into the IRQ mode and will vector the 0x00000018 the IRQ interrupt vector In order to enter the appropriate ISR the address in the VIC Vector Address Register must be loaded into the PC The assembly instruction shown below does this i
189. possible to boot the chip from external FLASH memory located on chip select zero External Memory Interface The External Memory Interface of the LPC22xx devices is shown below CSO CS3 DO D31 AO A23 OE BLSO 3 WE The data bus uses port 2 GPIO pins 2 0 2 31 and the address bus uses Port 3 GPIO pins 3 0 3 23 The remainder of port 3 is used for the Chipselects 1 3 the bytelane select pins and the write enable signal The remaining signal Chipselect O and output enable are on port 1 The two boot pins are multiplexed with the databus pins D26 and D27 Depending on the state of these pins at reset the LPC22xx variants can boot from internal FLASH or any width of memory connected to Chipselect zero The table below shows the states the pins should be held in to boot from a particular device These two pins are fitted with weak internal pull up resistors which ensure the device will boot from internal FLASH in its default condition 8 Bit 01 16 Bit 10 32 Bit Internal FLASH 54 Introduction to the LPC2000 3 System Peripherals The LPC22xx datasheet shows basic schematics for the most common memory interfacing options However we will consider a practical example of interfacing external FLASH and static RAM onto a 32 bit bus The FLASH memory we will use is the AMD AM29LV320DT This is a 32 megabit FLASH memory which can be arranged as 4M by 8 bits or 2M by 16 bits For the RAM we will use a K6F1616U6A which
190. ps have designed the LPC2000 to have the maximum on chip debug support There are several levels of support The simplest is a JTAG debug port This port allows you to connect to the LPC2000 from the PC for a debug session The JT AG interface allows you to have basic run control of the chip That is you can single step lines of code run halt and set breakpoints and also view variables and memory locations once the code is halted VOC 3 3 VCC 3 3 RM u Debug support on the LPC2000 includes a JTAG port for Flash programming and basic run control debugging d o cgo b n In addition Philips has included the ARM embedded trace module The embedded trace module provides much more powerful debugging options and real time trace code coverage triggering and performance analysis toolsets In addition to more advanced debug tools the ETM allows extensive code verification and software testing which is just not possible with a simple JTAG interface If you are designing for safety critical applications this is a very important consideration 8 ETM Trace Trigger JAG LOL ARM 7 Interface In addition to the JTAG port Philips have included the ARM ETM module for high end debugging tools The final on chip debug feature 1s the Real Time Monitor This is a kernel of code which is resident in a reserved area of memory During a debug session the debugger can start the real monitor via the JTAG port The real m
191. r power saving by running the VPB clock at the slowest speed acceptable for your application Example Code PLL And VPB Configuration The code below demonstrates how to configure the PLL to give 60M Hz Cclk and 30 MHz Pclk with an external crystal of 12MHz void init_PLL void PLLCFG 0x00000024 Set multiplier and divider of PLL to give 60 00 MHz PLLCON 0x00000001 Enable the PLL PLLFEED x000000AA Update PLL registers vith feed sequence PLLFEED 0x00000055 while PLLSTAT amp 0x00000400 test Lock bit PLLCON 0x00000003 Connect the PLL PLLFEED x000000AA Update PLL registers PLLFEED 0x00000055 VPBDIV 0x00000002 Set the VLSI peripheral bus to 30 000MHz Exercise 10 Phase Locked Loop In this exercise we configure the PLL to generate a Cclk of 60MHz and a Pclk of 2 63 Introduction to the LPC2000 3 System Peripherals Power Control Power consumption on all well designed microcontrollers is a direct relationship with the number of gates and the switching speed The LPC2000 is no exception The simplicity and low gate count of the ARM7 core contributes to its low power consumption Intelligent use of the PLL and VPB divider can contribute to reducing the runtime switching speed In addition the LPC2000 has additional dedicated power control features The ARM7 CPU has two power down modes controlled by the first two bits of the PCON register The CPU may be place
192. rals Halted Start Now PO 16 The A D may be started by a software event PO 22 or it may be started by several hardware MAT 0 1 triggers MAT 0 3 MATT 1 0 MAT 1 1 The simplest method of using the A D converter is shown below VPBDIV 0x02 Set the Pclk to 30 MHz IODIRI x00FF0000 P1 16 23 defined as Outputs ADCR 0x00270601 Setup A D 10 bit AINO 3MHz ADCR 0x01000000 Start A D Conversion while 1 do val ADDR Read A D Data Register Exercise 23 Analog To Digital Converter This exercise uses the A D to convert an external voltage source and modulate a bank of LEDs with the result 103 Introduction to the LPC2000 4 User Peripherals Digital To Analog Converter The LPC2132 2138 variants have a 10 bit Digital to Analogue converter This is an easy to use peripheral as it only has a single register The DAC is enabled by writing to bits 18 and 19 of PINSEL1 and converting pin 0 25 from GPIO to the AOUT function It should also be noted that a channel of the analogue to digital converter also shares this pin BINS Value The DAC is controlled by a single register 15 6 The value to be converted 15 written here 31 0 Once enabled a conversion can be started by writing to the VALUE bits in the control register The conversion time is dependant on the value of the BIAS bit If it is set to one the conversion time is 2 5uSec but it can drive 700 uA If it is zero the conv
193. res a 32 bit number The current value of the timer counter is compared against the match register When the values match an event is triggered This event can perform an action to the timer reset stop or generate interrupt and also affect an external pin set clear toggle VVhen the timer counter equals po the value stored in the match Reset Tc _ register it can trigger a timer St event and also affect an external op Tc External Match Register match pin Interrupt Match Register To configure the timer for a match event load the match register with the desired value The internal match event can now be configured through the Match Control Register In this register each channel has a group of bits which can be used to enable the following actions on a match event generate a timer interrupt reset the timer or stop the timer Any 80 Introduction to the LPC2000 4 User Peripherals combination of these events may be enabled In addition each match channel has an associated match pin which can be modified when a match event occurs As with the capture pins you must first use the pin connect block to connect the external pin to the match channel The match pins are then controlled by the first four bits in the external match register External Match 3 External Match 2 Extemal Mateli 1 The EMR register defines the action applied to the match pin when a match is 31 0 made on its channel The CPU ca
194. ress of this table 1s stored 1n RO The start address of a second table which contains the status code and function results is stored in R1 Command Code P TAM Command icd parameter table 1 bootloader functions can be accessed to perform In application programming Commands are passed via two tables in memory The start addresses for each table are stored in RO and H1 Result 0 Command result 1 result table ARM Register rO ARM Register r1 The IAP entry point 15 at OxX7FFFFFFO if you wish to call the functions from a THUMB function or at OX7FFFFFF1I if you wish to enter from an ARM function The return address is expected to be stored in the link register This convention is designed to work within the ARM procedure call standard A method of calling the IAP routines through function pointers is detailed in the datasheet An alternative method is shown below and both methods are used in the example program If you are short of program space you can experiment with both methods to see which is the most efficient in your compiler If we define a THUMB function with three parameters as shown below void iap unsigned cmd unsigned rslt unsigned entry j aemi mov tiorro We can pass the start address of a command and result array and by the APCS convention these values will be stored in RO and R1 We can also store the address of the entry point to the IAP routines in the next available parameter register R2
195. rget Ez Translate File Stop build Add Files to Group Source Group 1 Manage Components Remove Group Source Group 1 and it s Files I Include Dependencies 187 Introduction to the LPC2000 6 Tutorial With GNU Tools In the Add files to Group dialog add the file blinky c and serial c Add Files to Group Source Group 1 2 xj Lookin Owa vefertEM File name Files of type c Source file Close 2 Change the Type of file filter to ASM and add the file startup s These are all the source files necessary for the project so select close You can view the source code contained in a file by double clicking on the file name in the project browser window Once you have added all the source files the project can be built via the program menu or by the build button on the toolbar Start debugger Make project Ele Edt View Project Debug Flash Peripherals Tools SVCS Window Help ASUS zo Once the code is built you can start the simulator by pressing the debugger button The use of the simulator and JTAG debugger are detailed in Exercise One in the Tutorial and are the same for the GNU compiler 188 Introduction to the LPC2000 6 Tutorial With GNU Tools Exercise 2 Startup Code In this exercise we will configure the compiler startup code to configure the stack for each operating mode of the ARM7 We will also ensure that the i
196. rocessor to conserve power Secondly it gives Philips the option of adding a slower peripheral to the LPC2000 family without it becoming a bottleneck on the AHB bus Currently all the on chip peripherals are capable of running at 60MHz so the VPB bus can be set to the same speed as the AHB bus It is important to note that after reset the VPB divider 1s set to divide down the AHB clock by four so all the on chip peripherals will be running at 1 4 the CPU clock frequency Finally there 1s a third local bus which is used to connect the on chip Flash and RAM to the CPU Connection of the program code and data store to the ARM7 CPU via the AHB bus is possible but this introduces some execution stalls because of contention on the bus Using a separate local bus removes the possibility of these stalls to give the best processor performance 42 Introduction to the LPC2000 3 System Peripherals Local Bus Vectored Interrupt AZAL Although the LPC2000 has a linear Advance High Performance Bus address space there are several internal buses It is important to be aware of the difference between them and how the performance of the processor is affected AHB VPB Bridge Program Code Data VLSI Peripheral Bus ON Chip Peripherals 43 Introduction to the LPC2000 3 System Peripherals Memory Map Despite the number of internal buses the LPC2000 has a completely linear memory map The general layout is shown below 4 0
197. rogram running On the MCB2100 board press the INT button to generate the interrupt If you want to see the entry and exit mechanisms to the exception it is best to use the simulator and single step in the disassembly window This way you can watch the program flow and the actions on the CPU registers 193 Introduction to the LPC2000 6 Tutorial With GNU Tools To control the interrupt in the simulator open the peripherals GPIO port 0 window Pin 0 14 is set high by the map ini startup script If you set the program running unchecking the Pin1 4 box will generate the interrupt You must raise the pin high again to stop interrupts General Purpose Input Output 0 GPIO 0 I E GPIOU 21 Bits 24 23 Bits 16 15 Bits B Y Bits opmo ooxo0000 TTTTTTTT FTTTTTTT TTT T T TTTTTTTT 0 00000000 FTTTTTTT TTTTTTT FTTTTTTT inc 0000000 FTTTTTTT TT TT T l PiNt xt t z t FTTTTTTT TTTTTTTT FTTTTTTT TTTTTTTT Pins 0400004000 rT Tt ER L ELEL EL B T L L LLB L L L Alternatively in the toolbox there is a Generate EINTI button This button will generate a simulated pulse on to the interrupt pin Toolbox Toolbox button Fa Toolbox with user configurable scripts d Generate EINT 1 Within uVISION there 1s a full scripting language which allows you to simulate external events These scripts are based on the C language and are stored
198. rovide interoperability between different OEM equipment If you are developing your own closed system you do not need these application layer protocols and are free to implement you own proprietary protocol which is what most people do 105 Introduction to the LPC2000 4 User Peripherals CAN Node Design A typical CAN node is shown below Each node consists of a microcontroller and a separate CAN controller The CAN controller may as in the case of the LPC2000 be fabricated on the same silicon as the microcontroller or it may be a stand alone controller in a separate chip to the microcontroller The CAN controller is interfaced to the twisted pair by a line driver and the twisted pair is terminated at either end by a 120 Ohm resistor The most common mistake with a first CAN network is to forget the terminating resistors and then nothing works Microcontroller CAN node hardware A typical CAN node has a microcontroller CAN controller physical CAN Controller layer and is connected to a twisted pair terminated by 120 Ohm resistors TXO TXI 0 RXI UNO CAN Transcetver CANL CANH R I One important feature about the CAN node design is that the CAN controller has separate transmit and receive paths to and from the physical layer device So as the node is writing on to the bus it 1s also listening back at the same time This is the basis of the message arbitration and for some of the error detection The two logic le
199. rs set and clear registers for 12 ADR the control register an address register to SDA hold the node address when in slave mode 12 SCLH and a data register to send and receive bytes of data 12 SCLL 12 CONCLR The I2C peripheral interface is composed of seven registers The control register has two separate registers which are used to set and clear bits 1n the control register IZCONSET I2CONCLR The bit rate is also determined by two registers T2SCLH I2SCLL The status register returns control codes which relate to different events on the bus The data register 1s used to supply each byte to be transmitted or as data is received it will be transferred to this register Finally when the LPC2000 is configured as a slave device its network address 1s set by programming the I2ADR register In order to initialise the I2C interface we need to run the following lines of code VICVectCntl1 0x00000029 select a priority slot for a given interrupt VICVectAddrl1 unsigned I2CISR pass the address of the IRQ into the VIC slot VICIntEnable 0x00000200 enable interrupt PINSELO 0x50 Switch GPIO to 12C pins I2SCLH 0x08 Set bit rate to 57 6KHz DSCLL 0x08 94 Introduction to the LPC2000 4 User Peripherals The I2C peripheral must be programmed to respond to each event which occurs on the bus This makes it a very interrupt driven peripheral Consequently the first thing we must do is to configure the VIC to resp
200. rs to increment By configuring the statistical control register we can differentiate between code constant and instruction fetches so it 1s possible to determine the instruction or data hit rate or the combined instruction and data hit rate These metrics can give us some information on the efficacy of the MAM with our application On the CD there is a simple example which demonstrates the use of the MAM its statistical registers and demonstrates how vital it 1s to the overall performance of the LPC2000 family 46 Introduction to the LPC2000 Example MAM Configuration 3 System Peripherals The example code shown below starts the LPC2000 with the PLL set to 60MHz and the MAM disabled The code FLASHes each LED in sequence with a delay loop between each increment An A D conversion is also done and if the result 1s above 0x00000080 the code enables the MAM for maximum execution speed The effect of the MAM can be seen on the update rate of the LEDs In the next section we will look at burning the code into the FLASH to observe its operation int main void unsigned int delay unsigned int FLASHer 0x00010000 f define Locals IODIR1 OxOOFF0000 set all ports to output VPBDIV 0x02 ADCR 0x00270601 Setup A D 10 bit AINO 3MHz ADCR 0x01000000 Start A D Conversion while 1 do val ADDR Read A D Data Register while val amp x80000000 0 val val gt gt 6 amp
201. s PWMMR2 0x00000008 set falling edge of PWM2 to 8 ticks PWMLER 0x00000007 enable shadow latch for match 0 2 PWMEMR 0x00000280 Match 1 and Match 2 outputs set high PWMTCR 0x00000002 Reset counter and prescaler PWMTCR 0x00000009 enable counter and PWM release counter from reset while 1 main loop 775777 Modulate PWMMR1 and PWMMR2 One important line to note 1s that the PWMEMR register 1s used to ensure the output of the match channel is logic 1 when the match occurs If this register is not programmed correctly the PWM scheme will not work Also the PWM modulator does not require any interrupt to make it work unlike the basic timers 84 Introduction to the LPC2000 4 User Peripherals Exercise 18 Centre Aligned PWM This exercise configures the PWM unit to produce a centre aligned PWM signal without any CPU overhead Real Time Clock The LPC2xxx Real time clock RTC is a clock calendar accurate up to 2099 Like all the other peripherals the RTC runs off the PCLK so an additional external oscillator is not required The RTC is designed to be an ultra low power peripheral and through use of the LPC2xxx low power modes is suitable for running off batteries As well as providing a clock calendar the RTC has a set of alarm registers that can be used to trigger a particular date and time or on a specific value held in a time count register Reference Clock Divider Seconds Seconds
202. s a 32 bit processor it has a second 16 bit instruction set called THUMB The THUMB instruction set is really a compressed form of the ARM instruction set The THUMB instruction set is essential for archiving the necessary code density to make small single chip ARM7 micros usable ARM Instruction Decoder 16 bit Instruction Thumb code e This allows instructions to be stored in a 16 bit format expanded into ARM instructions and then executed Although the THUMB instructions will result in lower code performance compared to ARM instructions they will achieve a much higher code density So in order to build a reasonably sized application that will fit on a small single chip microcontroller it is vital to compile your code as a mixture of ARM and THUMB functions This process is called interworking and is easily supported on all ARM compilers By compiling code in the THUMB instruction set you can get a space saving of 30 while the same code compiled as ARM code will run 40 faster The THUMB instruction set is much more like a traditional microcontroller instruction set Unlike the ARM instructions THUMB instructions are not conditionally executed except for conditional branches The data processing instructions have a two address format where the destination register 1s one of the source registers ARM Instruction THUMB Instruction ADD RO RO RI ADD RO RI RO RO R1 The THUMB instruction set does not have full
203. s may be part way through a PWM cycle If you are updating several channels the new PWM values will take effect at different points in the cycle and may cause unexpected results The PWM modulator has an additional shadow latch mechanism which allows the PWM values to be updated on the fly but the new values will only take effect simultaneously at the beginning of a new cycle Match Reg 0 Shadow Reg 0 The PWM shadow latches allow the match registers to be updated thought the PWM cycle but the new values will only become effective at the beginning Match of a cycle Latch Enable Register Introduction to the LPC2000 4 User Peripherals The value in a given match register may be updated at any time but it will not become effective until the bit corresponding to the match channel is set in the Latch Enable register LER Once the LER is set the value in the match register will be transferred to the shadow register at the beginning of the next cycle This ensures that all updates are done simultaneously at the beginning of a cycle Apart from the shadow latches the PWM modulator match channels function in the same way as the timer match registers The second hardware addition to the PWM modulator over the basic timers is in the output to the device pins In place of the match channels directly controlling the match output pin are a series of SR flip flops Match PVVM1 PWM ENA 1 PVVM SEL
204. s must occur Typical I2C transaction A I2C bus transaction is 0 Write T 1 Read characterised by a start il pon condition slave address data exchange and stop condition with acknowledge handshaking in Bytes Acknowledge Acknowledge SDA low A Not Acknowledge SDA high S START condition P STOP condition El From Master to Slave From Slave to Master The bus master must first signal a start condition To do this the I2C clock line is pulled high and the data is pulled low The address of the slave which the master wants to talk to is then written onto the bus followed by a bit which states if a read or write 1s being requested If the slave has received this preamble correctly it will reply with an acknowledge Then data can be transferred as a series of bytes and acknowledges until the master terminates the transaction with a stop condition The I2C peripheral on the LPC2000 series 1s really a I2C engine It controls all the bus events but has no intelligence This means that the ARM7 CPU has to micro manage the I2C bus for each transaction Fortunately this is easy to do 95 Introduction to the LPC2000 4 User Peripherals and is centred around the I2C interrupt Once the I2C peripheral is initialised in master mode we can start a write data transfer as follows void I2CTransferByte unsigned Addr unsigned Data I2CAddress Addr Place address and data in Globals to
205. scripting language see the uVISION documentation 147 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 6 Software Interrupt In this exercise we will define an inline assembler function to call a software interrupt and place the value 0x02 in the calling instruction In the Software interrupt SWI we will decode the instruction to see which SWI function has been called and then use a case statement to run the appropriate code Open the project in C work EX6 SWI Add the file SWI VEC S to the project In Main c declare the two function as SWI functions as follows void SWI Calll int pattern svi 8 void SWI Call2 void svi 89 Compile and download the code into the debugger Step the code and observe the SWI being serviced In the disassembly window we can see the call to the first function This passes the parameter and generates an SWI which is packed with the integer 8 In the register window we can read the CPSR which shows we are in user mode el CPSA 0240000030 D n SWI Calll pattern 5 1 1 pius 0 0200000132 4807 LIE RU PC U0x001C if us 0 T 1 Branch to function is replaced by an M zl User mode swi instruction Once we have generated the software interrupt the chip will change modes run the code in vectors s and then enter our number 8 SWI function E e CPSF 080000063 30 void SWI Callliint pattern _ swii
206. solution V 3A ADDH VSSA The A D control register establishes the configuration of the converter and controls the start of conversion The first step in configuring the converter is to set up the peripheral clock As with all the other peripherals the A D clock is derived from the PCLK This PCLK must be divided down to equal 4 5MHz This is a maximum value and if PCLK cannot be divided down to equal 4 5MHz then the nearest value below 4 5MHz which can be achieved should be selected 31 Edge Start Test PDN CLKS Burst CLKDIV SEL 0 AD Control register The control register determines the conversion mode channel and resolution PCLK is divided by the value stored in the CLKDIV field plus one Hence the equation for the A D clock is as follows CLKDIV PCLK Adclk 1 As well as being able to stop the clock to the A D converter in the peripheral power down register the A D has the ability to fully power down This reduces the overall power consumption and the on chip noise created by the A D On reset the A D is in power down mode so as well as setting the clock rate the A D must be switched on This is controlled by the PDN bit in ADCR Logic one in this field enables the converter Unlike other peripherals the A D converter can make measurements of the external pins when they are configured as GPIO pins However by using the pinselect block to make the external pins dedicated to the A D converter the overall conversion accuracy is in
207. st correct watchdog feed sequence is encountered Once fully started the watchdog must receive regular feed sequences in order to stop the watchdog counter reaching zero and timing out The final Watchdog register 1s the Watchdog Timer Value Register which allows you to read the current value of the watchdog timer 89 Introduction to the LPC2000 4 User Peripherals UART The LPC2xxx devices currently have two on chip UARTS They are both identical to use except UARTI has additional modem support Both peripherals conform to the 550 industry standard specification Both have a built in baud rate generator and 16 byte transmit and receive FIFOs Interrupt Enable Sheild Interrupt ID FIFO Control Line Control Line Status Scratch Pad Divisor Latch LSB Divisor Latch D D 02 Ul Initialisation of the UARTO is shown below void init serial void Initialize Serial Interface PINSELO 0x00050000 Enable RxD1 and TxD1 n 0x00000083 I 8 bits no Parity L Stop bit mum 0x000000C2 9600 Baud Rate 30MHz VPB Clock E 0x00000003 DLAB 0 First the pinselect block must be programmed to switch the processor pins from GPIO to the UART functions Next the UART line control register is used to configure the format of the transmitter data character UART Line control register The LCR configures the format of transmitted data Setting the DLAB bit
208. t M A 3 3000 M ACA pet 30 Analog Inputs AINO 1 0000 AINT 0 0000 AIN2 0 0000 AIN3 0 0000 A new simulation script has been added that allows you to change the A D voltage via buttons in the toolbox 177 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 24 Digital to Analogue Converter In this exercise we will setup the A D to make a conversion every 50uSec 20 KHz by using a timer match channel to trigger the conversion As soon as the conversion is made the converted value is fed into the Digital to Analogue converter If you have access to a signal generator and a scope you can compare the input and output waveforms or use the simulator and the Logic analyzer Open the AtoD project in C work EX20 AtoD Configure the A D so it is triggered by timer0 match channel Copy the A D result into the DAC register Build the project and start the debugger If you are using the MCB2100 connect a signal generator to the A D input channel and an oscilloscope to the output Run the code and compare the two waveforms Vary the input frequency and find the frequency at which aliasing occurs If you are using the simulator an input script is provided in the toolbox and the input output signals can be compared in the logic analyser window 178 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 25 Transmitting CAN Data In the next two exercises we are going to look at transmitting
209. t of registers the data processing instruction has to be executed and then the data is stored back into memory Mov Mi Ri The ARM7 CPU is a load and store architecture All data Add Ra Ri Re Ra R processing instructions may only be carried out on a central register file Mov M Re Mov Ra Ms The central set of registers are a bank of 16 user registers RO R15 Each of these registers is 32 bits wide and RO R12 are user registers in that they do not have any specific other function The Registers R13 R15 do have special functions in the CPU R13 is used as the stack pointer SP R14 1s called the link register LR When a call is made to a function the return address is automatically stored in the link register and is immediately available on return from the function This allows quick entry and return into a leaf function a function that is not going to call further functions If the function 15 part of a branch i e it is going to call other functions then the link register must be preserved on the stack R13 Finally R15 is the program counter PC Interestingly many instructions can be performed on R13 R15 as if they were standard user registers The central register file has 16 word wide registers plus an additional CPU register called the current program status register RO R12 are user registers R13 R15 have special functions 15 User registers PC RO R6 R8
210. t view serial window 1 This opens a terminal window within the simulator which displays the UARTO output 192 Introduction to the LPC2000 6 Tutorial With GNU Tools Exercise 5 Simple Interrupt 1 In this exercise we will setup a basic FIQ interrupt and see it serviced 2 Open the project in EX5 Interrupt work 3 In main c complete the definition of the EXTintFIQ function prototype to define it as the FIQ interrupt service routine void EXTIntEIO void attribute interrupt FIQ In startup s complete the vector constants table to define EXTintFIQ as the FIQ ISR qlobal EXITHLEIQ Declare the name of the C ISR function as a global global _startup func _startup _ startup Vectors LDR PC Reset_Addr LDR PC Undef_Addr LDR PC SWI_Addr LDR PC PAbt_Addr Vector Table LDR PC DAbt_Addr long OxB8A06F58 LDR PC PC 0xFFO LDR PC FIQ Addr Reset_Addr Word Reset Handler Undef Addr Word Undef Handler SWI Addr Word SWI Handler Constants table PAbt Addr Word PAbt Handler DAbt Addr Word DAbt Handler word 0 IRQ Addr Word IRQ Handler FIQ Addr word EXTintFIQ Insert the name of the C ISR function in the constants table 5 Compile the code and download it onto the board 6 Step through the code and observe the following using the disassembly window and the registers window Step through the code until you reach the while loop c Set a breakpoint in the EXTintFIQ function Press F5 to set the p
211. tem Peripherals Example Program FIQ Interrupt This function sets up the external interrupt as an FIQ interrupt then sits in a loop void main void IODIR1 x00FF0000 Set the LED pins as outputs PINSELO x20000000 Select the EINTI function in the pin connect block VICIntSelect 0x00008000 Enable a Vic Channel as FIQ VICIntEnable 0x00008000 Enable the EINT1 interrupt in the VIC TOCLRI 0x00FF0000 Clear the LED s while 1 Loop here forever In the startup code the FIQ interrupt routine must be added to the vector table The address of the FIQ interrupt routine 1s suffixed with A to demote the routine as an ARM 32 Bit instruction set routine EXTERN CODESZ Lrfqginte A Startup PROC CODE32 Vectors LDR PC Reset_Addr LDR PC Under Addr LDR PC SWI_Addr LDR PC PAbt_Addr LDR PC DADE Adar NOP Reserved Vector 7 7 LDR PC PC 4 0OxOFF0 LDR PC F LO Addr Load the address of the FIQ routine into thePC from the constants table Reset Addr DD Reset Handler Undef Addr DD Undef Handler SWI Addr DD SWI Handler PAbt Addr DD PAbt Handler DAbt Addr DD DAbt Handler DD 0 Reserved Address IRQ Addr DD IRQ Handler FIQ Addr DD figint A The address of the FIQ routine 15 stored here When the INT1 button is pressed on the MCB2100 the FIQ interrupt is generated and the code will vector to the fiqint routine The routine is declared as an interrupt routine by using the
212. ter to the first line of your code in the interrupt routine 161 Introduction to the LPC2000 5 Tutorial With Keil Tools Exercise 13 Non Vectored Interrupt In this exercise we will use the Vector interrupt unit to generate the slowest form of interrupt response a non vectored interrupt We will use External interrupt one EINT1 to generate an interrupt The VIC will respond to this interrupt event by providing the address of a general purpose ISR for the processor to jump to On entry to this routine the ISR must calculate the source of the interrupt take appropriate action and then correctly exit the ISR and resume normal processing Open the project in EX9 Interrupt Non Vectored work In Startup s add the correct assembly code to the IRQ interrupt vector PC PCy q 0xERO n main c configure the Pin Connect Block to enable PO 14 as an External interrupt PINSELO 0x20000000 Place the address of the NonVectored ISR into the Default vector address register Note in C this can be done as follows VICDefVectAddr unsigned lt Name of ISR routine Enable the External interrupt channel in the VIC VICIntEnable 0x8000 In the interrupt routine check the IRQ status register to find the source of the interrupt if VICIRQStatuss0x00008000 At the end of the ISR clear the interrupt flag in EINTO register and perform dummy write to the correct register in the VIC to clear the interrupt source EXTINT 0x00000002
213. then an interrupt is generated So it is possible to set an alarm between now and 2099 with one second s accuracy The Alarm Mask register controls which alarm registers are used in the compare As both the increment and alarm events can generate an RTC interrupt it is necessary to distinguish between them from within the interrupt The Interrupt location register provides two flags which can be interrogated to see what caused 86 Introduction to the LPC2000 4 User Peripherals the RTC interrupt Again remember that these flags must be cleared to cancel the interrupt An RTC program which sets the clock and uses both styles of interrupt is shown below int main void VPBDIV 0x00000002 TODIRI OxOOFF0000 1 1 Ox00020000 PREINT 0x00000392 PREFRAC 0x00004380 CIIR 0x00000001 ALSEC 0x00000003 AMR 0 000000 7 set LED pores to output Set RTC prescaler for 30MHz Pclk Enable seconds counter interrupt Set alarm register for 3 seconds Enable seconds Alarm CCR 0x00000001 Start the RTC VICVectAddr13 unsigned RTC isr Set the timer ISR vector address VICVectOontlds e 0x0000002D VICIntEnable 0x00002000 while 1 void RTC_isr void unsigned led if ILR amp 0x00000001 led IOPINI 1 led amp 0x00030000 1 led amp 0x00030000 ILR 0 00000001 if ILR 6 0x00000002 IOSET1 0x00100000 ILR 0x00000002 VICV
214. tively six stacks in the ARM7 The strategy used by the compiler 1s to locate user variables from the start of the on chip RAM and grow upwards The stacks are located at the top of memory and grow downwards The startup code enters each different mode of the ARM 7 and loads each R13 with the starting address of the stack Finally switch to USER mode and enable interrupts Check for ARM or Thumb mode Stack Configuration Stack Sizes in Bytes Undefined Made 0 0000 0004 Supervisor Mode Ox0000 0004 Abort Mode 0 0000 0004 Fast Interrupt Mode 0 0000 0004 Interrupt Made 0 0000 0060 User System Mode 020000 0400 fal PLL Setup v is MAM Setup v s External Memory Controller EMC v Like the vector table you are responsible for configuring the stack size This can be done by editing the startup code directly however Keil provide a graphical editor that allows you to more easily configure the stack spaces In addition the graphical editor allows you to configure some of the LPC2000 system peripherals We will see these 1n more detail later but remember that they can be configured directly in the startup code Exercise 2 Startup code The second exercise in the tutorial takes you through allocating space for each processor stack and examines the vector table 30 Introduction to the LPC2000 2 Software Development Interworking ARM THUMB Code One of the most important things that we need to do in our application
215. tl 0200000152 000001 sw 0200000001 On entry to the ISR the supervisor link register contains the value 0x00000160 614 42 Ox00000160 The calculation for temp is temp link ptr 1 82 0x00FFFFFF or 164 4 word wide pointer remember which is 15C which points to the instruction which generated the SWI The top 8 bits are masked off which yields a value of 1 This is used in the case statement to run the required code 195 Introduction to the LPC2000 6 Tutorial With GNU Tools 196 Appendices Appendix A Bibliography ARMTTDMI datasheet ARM LPC2119 2129 2194 2292 2294 User Manual Philips ARM System on chip architecture Steve Furber Architecture Reference Manual David Seal ARM System developers guide Andrew N Sloss Domonic Symes Chris Wright MicroC OS II Jean J Labrosse GCC The complete reference Arthur Griffith Webliography Reference Sites http www arm com http www philips com http www lpc2000 com Tools and Software Development http ww hitex co uk http www keil co uk http www ucos ii com http www ristancase com http gcc gnu org onlinedocs gcc Evaluation Boards And Modules http www phytec co uk http www embeddedartists com 197 198 The LPC2000 family from Philips semiconductors is the first of a new generation of microcontrollers based on the ARM7 TDMI 16 32 bit RISC processor This book 15 written as both an intro
216. to use each of the given compilers can be summed up as follows if you want the fastest code and standard tools use the ARM compiler for best code density use the Keil if you have no budget or a simple project use the GNU Since we are writing code for a small single chip microcontroller with limited on chip resources the obvious choice for us is the Keil ARM compiler When deciding on a toolset it is also important to examine how much support is given to a specific ARM7 implementation Although a toolset may generate code for an ARM7 it may not understand how the ARM7 is being used in a specific system 1 e LPC2000 Using a raw ARM7 will generate code which will run on the LPC2000 but you will have to spend time writing the start up code and struggle with a debugger which will not understand the LPC peripherals This can lead to fighting the development tools which needless to say can be very frustrating uVISION IDE uVISION also includes two debug tools Once the code has been compiled and linked it can be loaded into the uVISION simulator This debugger simulates the ARM7 core and peripherals of the supported micro Using the simulator is a very good way of becoming familiar with the LPC2000 devices Since the simulator gives cycle accurate simulation of the peripherals as well as the CPU it can be a very useful tool for verifying that the chip has been correctly initialised and that the correct values for things such as timer pres
217. trol register can configure if a rising or falling edge or both on this 79 Introduction to the LPC2000 4 User Peripherals pin will trigger a capture event When the capture event occurs the current value in the timer counter will be transferred into the associated capture register and if necessary an interrupt can be generated The code below demonstrates how to configure a capture channel This example sets up a capture event on a rising edge on pin 0 2 Capture 0 0 and generates an interrupt int main void VPBDIV 0x00000002 Set pclk to 30 MHz PINSELO 0x00000020 Enable pin 0 2 as capture channel0 TOPR 0x00007530 Load prescaler for 1 Msec tick TOTCR 0x00000002 Reset counter and prescaler TOCCR 0x00000005 Capture on rising edge of channel0 LOTCE 0x00000001 enable timer VICVectAddr4 unsigned TOisr Set the timer ISR vector address ViCcvectCntl4 0x00000024 Set channel VICIntEnable 0x00000010 Enable the interrupt while 1 void T riSr void static int value value TOCRO read the capture value TOIR 0x00000001 Clear match 0 interrupt VICVectAddr 0x00000000 Dummy write to signal end of interrupt Exercise 16 Timer Capture This exercise configures a general purpose timer with a capture event to measure the width of a pulse applied to a capture pin Each timer also has up to four match channels Each match channel has a match register which sto
218. truction will jump you to a destination address The BL 0X8000 0x400 branch link instruction jumps to the destination and PC 0x8000 stores a return address in R14 R14 0x400 4 LDA R2 10 0x8000 So the branch link instruction is used as a call to a function storing the return address in the link register and the branch instruction can be used to branch on the contents of the link register to make the return at the end of the function By using the condition codes we can perform conditional branching and conditional calling of functions The branch instructions have two other variants called branch exchange and branch link exchange These two instructions perform the same branch operation but also swap instruction operation from ARM to THUMB and vice versa BLX 08000 0x400 PC 0x8000 lm LDA R2 10 0X8000 The branch exchange and branch link exchange instructions perform the same jumps as branch and branch link but also swap instruction sets from ARM to THUMB and vice versa BLX 0X8000 Ox400 PC 0x8000 Lm H14 0x400 4 LDAR2 10 OX8000 This is the only method you should use to swap instruction sets as directly manipulating the T bit in the CPSR can lead to unpredictable results 18 Introduction to the LPC2000 1 The ARM7 CPU Core Data Processing Instructions The general form for all data processing instructions is shown below Each instruction has a result register and two operands The first op
219. uild options such as build for RAM debugging or Flash debug in the simulator or with the JTAG Build the code by selecting the Project build target menu or the F7 key Build Icons are also available on the toolbar Introduction to the LPC2000 5 Tutorial With Keil Tools Start debugger Make project Fle Edt Wiw Project Debug Flash Peripherals Tools 525 Window Help asig ihe oi e hz Jalajala emere si i xl For the rest of the tutorial the projects will be defined but relevant bits of code will be missing A complete copy of the exercise can be found in the solution directory All the example code is included on your CD 132 Introduction to the LPC2000 5 Tutorial With Keil Tools Using The Debugger Launch the debugger by selecting the debugger start stop debugger session menu or the button on the toolbar Debugger Toolbar source Window Disassembly Window K FIR TAL N He Edt view Prox Flash Peripherals Tools SVCS Window Help asugomh ococrinhkwEE s HORT ego AAs sem jesaja serm Register Value gt Curent RO 000 R1 0x400 R2 x400 R3 0x400 ded 000 Function R5 04000 s 0x000 Es Example Interrupt pr for LPC2100 0 000 Demonstrates configuring a function as an ISR R10 0x400 e Ox000000F4 1 M V R12 R13 AN 0490 25 55 10 000000 8 9200800 STM
220. ultiple Data Field Data Length Code messages with 7 D the same ID RTR bit D Identifier Field Start of Frame This leads to one of the golden rules in developing a CAN network In a CAN network every identifier must be uniquely generated So you must not have the same identifier sent from two different nodes If this happens it 1s possible that two messages with the same ID are scheduled together both messages will fight for arbitration and both will win as they have the same ID Once they have won arbitration they will both start to write their data onto the bus At some point this data will be different and this will cause a bit check error Both messages will be rescheduled win arbitration and go into error again Potentially this deadly embrace can lock up the network so beware 116 Introduction to the LPC2000 4 User Peripherals At the bit level CAN also implements a bit stuffing scheme For every five dominant bits in a TOW a recessive bit is inserted Arbitration Data n 622 qar na n7 Bit Stuffing For every five bits of one logic in a row a stuff bit of the opposite logic is inserted The error frame breaks this rule by CAN Bit Stream MR LN being six dominant bits in a row n nl n2 n3 n n 7 This helps to break up DC levels on the bus and provides plenty of edges in the bit stream which are used for resynchronisation An error frame in the CAN protocol is simply six dominant bits in a row
221. v Use Keil ARM Tools Cygnus Folder E Conus Keil Root Folder Sei ARM Use GNU Tools RealView Folder Froarem Files WARM ADSV1_2 P Use ARM Tools Keil Root Folder ei AA MA Introduction to the LPC2000 5 Tutorial With Keil Tools Folders extensions tab and make sure the Keil ARM tools box 1s selected Next click on the Books tab Components Environment and Books Project Components Folders Extensions Books General Books 12 9X Tool Specific C3 XX 7 Device Specific 3 X 4 Release Notes User Manual Complete User s Guide Selection GNU C Compiler GNU C Run Time Libraries GNU C Utilities GNU C Assembler Default Root Default Root Default Root CAKeih EAKeiNARMN C ES Change Book Cancel Highlight the UserManual entry and press the Change Book button Add Change Book Item Book Title User Manual Book Path CW ork WAM Philips Course Image Lser ManualssLEPEZ11 Now change the path to point to the LPC2000 user manual which can be found on the CD in the User Manuals directory You can now add any other documentation you wish through these menus Once the project has been fully configured the on line documentation can be accessed through the Books tab in the project workspace window The full Keil documentation for Project Workspace x Tools User s Guide e Release Mates Compl
222. vels are written onto the twisted pair as follows a logic one is represented by bus idle with both wires held half way between and Vcc A logic Zero is represented by both wires being differentially driven V Recessive Dommant Recessrve 5 CAN Physical layer signals On the CAN bus logic zero is represented by a maximum voltage difference called Dominant and logic one by a bus idle state called recessive A dominant bit will overwrite a recessive bit 106 Introduction to the LPC2000 4 User Peripherals In CAN speak a logic one is called a recessive bit and a logic zero is called a dominant bit In all cases a dominant bit will overwrite a recessive bit So if ten nodes write recessive and one writes dominant then each node will read back a dominant bit The CAN bus can achieve bit rates up to a maximum of 1 Mbit sec Typically this can be achieved over about 40 metres of cable By dropping the bit rate longer cable runs may be achieved In practice you can get at least 1500 metres with the standard drivers at 10 Kbit sec CAN Message Objects The CAN bus has two message objects which may be generated by the application software The message object is used to transfer data around the network The message packet is shown below Field 5 29 Bit Identifier 0 8 Bytes Data f R Remote transmit request C Arbitration Field ontrol DATA Field Error control and end of frame Data l
223. wo timers All of the general purpose timers are identical in structure but vary slightly in the number of features supported The timers are based around a 32 bit timer counter with a 32 bit prescaler The clock source for all of the timers is the VLSI peripheral clock PCLK Reset Enable The two timers and the PWM module have the same basic timer structure A 32 bit timer counter with a 32 bit prescaler The tick rate of the timer is controlled by the value stored in the prescaler register The prescale counter will increment on each tick of Pclk until it reaches the value stored in the prescaler register When it hits the prescale value the timer counter is incremented by one and the prescale counter resets to zero and starts counting again The Timer control register contains only two bits which are used to enable disable the timer and reset its count In addition to the basic counter each timer has up to four capture channels The capture channels allow you to capture the value of the timer counter when an input signal makes a transition Timer Counter Pin Each capture channel has a capture pin This pin can trigger a capture Capture Register event on a rising or falling edge When an event occurs the value in the timer counter is latched into an associated capture register Capture control register Each capture channel has an associated capture pin which can be enabled via the pin connect block The Capture con

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