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[IONIROL PROCESOR

1. Register Field Register Field 25 The Configuration Register Field and the Data Register Field are used by the ICE Logic to recreate the output TABLE III functionality of G0 G1 G2 and G3 For each G Port pin that is recreated the modified COPS outputs one Configuration Register bit and one Data Register bit These two bits allow 30 the ICE Logic to support the various types of output figurations available on the modified COP8 see Table ID POUT Pin When pin is configured for simple 1 the modified COP8 OUTPUT Pin Signals Signals PC simply outputs an image of its internal Configuration and 35 Data Register bits For pins that are configured to use an FETCH PL PU Status Field Alternate Function the modified COP8 outputs the appro 22 2 priate Configuration and Data Register bit pattern to reflect FLAG REPLACEMENT SLOT1 SLOT2 ACTION the output value of the function 0 0 0 0 No Action PC Frozen TABLE 0 0 1 0 PC Incremented COPS Output Port Driver Configurations 0 1 0 0 PCL Replaced Configuration Data Output Driver 0 1 0 d pits ot PEH Register Bit Register Bit Configuration gt Replaced 0 0 Tri state output 0 1 1 1 Lower 4 bits of PCH 0 1 Wear pull up Replaced 1 0 Push pull zero output 1 1 Push pull one output 1 N A X 0 PC Incremented 50 1 N A X 1 Interrupt In Slot 3 through Slot 6 the POUT pin shifts out the Configuration Register bits least significant bit LSB first Ns Not
2. WR ENABLE CLEAR ena CLT_ADR 7 0 0x00 SYNC1 CMD WAITING d CMD_WAITING SYNC1 CMD WAITING clk CLK CMD WAITING ena RSLOT3 SYNC1 CMD WAITING clr ENABLE CLEAR SYNC2 CMD WAITING d SYNC1_CMD_ WAITING SYNC2 CMD WAITING clk CLK SYNC2 CMD WAITING ena RSLOTS SYNC2 CMD WAITING clr ENABLE CLEAR SYNC1 HW CMDd HW CMD 5 HW CMD clk CLK SYNC1 HW CMD ena RSLOT3 SYNC1 HW CMD clr ENABLE CLEAR SYNC2 HW CMD d 1 HW CMD SYNC2 HW CMD clk CLK SYNC2 HW CMD ena RSLOTS SYNC2 HW CMD clr ENABLE CLEAR 8 4 3 Enabling Code Logic 404 48 404 49 404 50 404 51 404 52 404 53 404 54 404 55 404 56 404 57 404 58 404 59 404 60 404 61 404 62 404 63 404 64 404 65 404 66 404 67 404 70 404 71 404 72 404 73 404 74 ENABLE BYTEO 7 0 0x09 ENABLE 7 0 ENABLE_BYTE2 7 0 0x47 ENABLE CNTR S ENABLE CNTR 5 0 clk ENABLE 5 0 ena STOP CODE ENABLE 5 0 clr ENABLE CLEAR STOP CODE OUT_FLAGS4 ENABLE CODE ENABLE CNTR 0x08 AND ENABLE 0 OR ENABLE CNTR 0x09 AND ENABLE BYTE01 0 d ENABLE CNTR 5 0 1 ENABLE CNTR 0x0A AND ENABLE 02 ENABLE CNTR 0x0B AND ENABLE ENABLE CNTR
3. FLAGS3 403 43 POUT_FLAGSO SLOT 403 44 POUT_FLAGS1 SLOT2_ 8 3 5 Explanation of Logic Equations The data output on the POUT pin is used to recreate the pins that are used in the interface Each recreated pin has two register bits CONFIG and DATA that are used to determine its output structure The CONFIG register bits are output first during Slot 3 to Slot 6 and are stored in TG CONFIG 3 0 lines 403 2 to 403 17 The DATA register bits come out next during Slot 7 to Slot 10 and are stored in TG DATA 3 0 lines 403 18 to 403 33 Both TG CONFIG 3 0 and TG DATA 3 0 are output to Rec reated Ports block block 405 where the pins output struc tures are actually recreated The POUT pin also outputs two flags that are used primarily to recreate the COP8 program counter as it executes These flags are captured in two D flops lines 403 34 to 403 41 and are output to the Emulator Core as the POUT flag bus POUT_FLAGS 1 0 lines 403 43 and 403 44 8 4 Input Pin Block 404 Logic Equations and Explanation 8 4 1 COPS Interface 4041 90 INPUT 404 2 INPUT RSLOT10 AND SYNC2 CMD _ WAITING AND NOT INP_HW_BRK_CMD 404 3 RSLOT1 AND SYNC2_CMD_ WAITING 404 4 RSLOT2 AND NOT SYNC2__CMD_ WAITING AND TG INPO 404 5 RSLOT2 AND SYNC CMD VAITING AND CMD BUFFERO 404 6 RSLOT3 AND NOT SYNC2 WAITING TG INP1 404 7 RSLOT
4. 0 o bus data e Instruction skipped D 7 previous cycle contains interna ion State Reset D 7 0 contains no valid data ion State Type 4 Type 3 Reset D 7 0 contains no valid data US 6 829 727 B1 15 16 5 3 GI POUT The interrupt activity and PC activity information is used The G1 POUT pin outputs instruction source PC update in combination with the Fetch Flag and PC replacement activity and the data that allows the ICE Logic to recreate the tatus of the OUTPUT pin this data the ICE Loei output state of the four G Port digital I O pins used in this 22 LANA AD asas d ix interface This pin uses only Type 3 and Type 4 waveforms 5 The POUT pin breaks the 10 slot COPS machine cycle recreated PC can be stored in a Trace Memory in the ICE into three fields see FIG 11 the PC Status Field the Logic to provide the User with a snapshot of his program s Configuration Register Field and the Data Register Field execution history recreates the PC as it executes the User s program This FIG 11 POUT Pin Field Layout dS COPS Machine Cycle Slot 1 Slot 2 Slot 3 Slot 6 Slot 7 24 97 4 Slot 10 f Naf PR eu OL eub CLK Pin PC Status Field Configuration Data
5. digital pins are modified to allow data status and control to 714 33 27 703 28 be exchanged between the COP8 s CPU and the emulation base These modified COPS pins recreated by the emu 56 References Cited lation base so that emulation occurs with the COPS s full U S PATENT DOCUMENTS complement of I O The content of the signals shared between the COPS and the emulation base allows for a full S 3 1994 Pawloski 703 28 range of emulation capabilities The 8 device is emu A d io ndun 2 lated in situ on the printed circuit board providing accurate A 1 EE al 14 operation of precision peripherals and environmental vari 5 960 190 A 9 1999 MacKenna 703 28 5964890 10 1999 Inui et al 714 28 ables The signals shared with the emulation base are routed 6 094 729 A 7 2000 714 25 to a standard simple connector The connector is configured 6 167 365 12 2000 Karthikeyan et al 703 28 so that the printed circuit board can be easily switched 6 233 673 5 2001 Higashida 712 227 between a development system and a production system 6 516 428 B2 2 2003 Wenzel et al es 714 28 6 523 148 2 2003 Junghans 714 797 39 Claims 10 Drawing Sheets TARGET SYSTEM MODIFIED 8 FLASH DEVICE TARGET VCC ICE LOGIC IN CIRCUIT EMULATOR U S Patent Dec 7 2004
6. then to a logic 0 again The 0 to 1 transition followed by a 1 to 0 transition causes the modified COPS to exit the Power Saving mode push the PC on the stack and then vector to the ICE Monitor US 6 829 727 B1 19 Summary of the INPUT Pin G0 TABLE V 20 Valid Slot Waveform Combinations SI0 Sl S2 S3 S4 55 86 87 S8 S9 Meaning 0 0 TGO TG1 TG2 TG3 Hardware Break Request Recreated Port Input data from Target 0 1 1 D2 D3 D4 D5 D6 D7 Monitor Data Command D 7 O load into ICEDATA register 1 0 TGO TG1 TG2 TG3 Recreated Port Input Recreated Port Input data from Target 1 1 Data Invalid 18 6 0 Details of Enabling the Ice Hooks Mode continued STANDARD 2x7HEADER p The ICE Hooks mode described in this patent is enabled R o c oi 2 20 TAGET RESET in the modified COPS by inputting a specific bit pattern 4 key on the modified COPS s GO pin during the initial TARGET OL O gt 6 E assertion of external Reset TARGETG2 89 AMT O9 100 ee lon 10 TARGET G3 When external Reset is asserted the modified COP8 s G0 25 EE RUN 5 100mik 1t L 2 L and G2 Port pins are configured with a weak pull up With 100 mil external Reset still asserted the ICE Logic outputs a clock on OUTPUT G2 The ICE Logic then synchronously outputs the key on INPUT G0 The ICE Logic keeps externa
7. 0 oe ADR 7 0 0x05 RD SECOND SKIP US 6 829 727 B1 23 continued 401 118 ADR 7 0 0x06 AND NOT CIT 8 1 7 Explanation of Logic Equations There is a tremendous about of decoding that the ICE Logic must do with the OUTPUT and POUT signals This decoding is completely dependent on the ICE Logic running synchronously with the modified COPS Synchronization is accomplish by the sync bits of the OUTPUT signal that allows the ICE Logic to identify Slot 1 of the modified COPS s machine cycle every machine cycle The whole sequence of events starts with the ICE Logic determining if the current slot contains a sync bit or not Note The Slots in the ICE Logic are referred to as Recreated Slots or RSLOT decode if the current slot has a sync bit the logic levels of the OUTPUT pin on both edges of CLK have to be examined If they are different the slot contains a sync bit First the logic level at the negative clock edge is captured in a D flop lines 401 5 and 401 6 If the logic level at the positive clock edge is the same the slot does not contain a sync bit and this is captured in a D flop lines 401 7 and 401 8 The sync bit that defines Slot 1 is decoded at the end of Slot 1 and is used to start the timing chain beginning with Slot 2 RSLOT2 lines 401 9 to 401 11 Once Slot 2 has been asserted the t
8. 8 bit multiplexed address and data bus The Read N CTL RD and Write N WR control lines control bi directional data flow WhenN WR is asserted the Control Processor is writing data to the ICE Logic lines 407 1 and 407 2 Conversely when CTL RD is asserted the Control Processor is reading data from the ICE Logic lines 407 3 and 407 4 The address is captured off the bus using the Address Latch Enable ALE control line lines 407 5 and 407 6 The Read and Write control lines as well as a free running clock are buffered and output to the ICE Logic core The Break state is output from the ICE Logic to the Control Processor as a status signal line 407 10 Those skilled in the field of the present invention and having the benefit of this disclosure will recognize that the terms pin and pins as used herein may refer to a connection terminal and the circuitry associated with that connection terminal Such terminology is common and well understood in this field Furthermore those skilled in this field and having the benefit of this disclosure will recognize that the terms pin and pins are often used to refer to the connection terminals of a packaged integrated circuit Other types of connection terminals including but not limited to lands solder balls and solder bumps may also be used to provide signal pathways between an integrated circuit and one or more external circuit elements The present invention may
9. Applicable In Slot 7 through Slot 10 the Data Register bits are shifted X Dont care out LSB first The ICE Logic shifts in this POUT data and 55 at the end of Slot 10 synchronously outputs the new output state to its recreated output pins which are connected to the As shown in Table during non fetch cycles Fetch User s target system Flag 0 the PC can stay the same increment or have various The PC Status field is used to provide the ICE Logic with parts replaced These actions represent the complete set of itor ible PC acti ilable to the COPS instructi information on the source of instructions Flash or Monitor the possible FL actions avatlable to the ROM interrupt activity and activity When the Fetch set This allows the ICE Logic to faithfully recreate the PC Flag is asserted on the OUTPUT pin the logic value on the and track the instruction flow accurately During a fetch POUT pin during Slot 1 determines the source of the cycle the PC is either incremented or an interrupt is being instruction logic value of 0 specifies that the instruction 65 processed If the ICE Logic decodes an interrupt it forces is being fetched from the Flash Memory A logic value of 1 the interrupt vector OxOOFF into its recreated PC to mimic specifies an instruction fetch from the Monitor ROM the actions of the modified COP8 US 6 829 727 B1 17 Summary of the POUT Pin G1 TABLE IV 18 Valid
10. CONFIGO d POUT 403 3 TG_CONFIGO clk CLK 4034 TG CONFIGO ena RSLOT3 403 5 CONFIGO clr RESET ACTIVE 403 6 CONFIG1 d POUT 403 7 TG_CONFIG1 clk CLK 4038 CONFIG1 ena RSLOT4 4030 TG CONFIG1 clr RESET ACTIVE 403 10 TG CONFIG2 d POUT 403 11 TG CONFIG2 clk CLK 403 12 CONFIG2 ena RSLOTS 403 13 CONFIG2 clr RESET ACTIVE 403 14 TG CONFIG3 d POUT 403 15 CCNFIG3 clk CLK 403 16 CONFIG3 ena RSLOT6 403 17 CONFIG3 clr RESET ACTIVE 403 18 DATAO d POUT 403 19 DATAO clk CLK 403 20 TG DATAO ena RSLOT7 403 21 TG_DATAC clr RESET ACTIVE 403 22 DATAZ d POUT 403 23 TG_DATA1 clk CLK 403 24 TG_DATA1 ena RSLOTS 403 25 TG_DATA1 clr RESET ACTIVE 403 26 TG DATA2 d POUT 03 27 DATA2 clk CLK 03 28 DATA2 ena RSLOT9 03 29 DATA2 clr RESET ACTIVE TG DATA3 d POUT TG DATA3 clk CLK TG DATA3 ena RSLOT10 TG DATA3 clr RESET ACTIVE P p p p p o 8 3 3 Pin Flag Capture 403 34 403 35 403 36 403 37 403 38 403 39 403 40 403 41 SLOT1_POUT d POUT SLOT1_POUT clk CLK SLOT1 POUT ena SLOT SLOT1_POUT clr RESET ACTIVE SLOT2_POUT d POUT SLOT2__POUT clk CLK SLOT2 51072 SLOT2_POUT clr RESET ACTIVE 10 15 20 25 30 35 40 45 50 55 60 65 26 8 3 4 Emulator Core Interface 403 42 RESET ACTIVE
11. Control Processor is waiting to receive a byte of data from the ICE Monitor it uses a sequence of two Skip flags to detect that the data is available in the ICE Logic to read see Section 4 2 The sequence of two Skip flags is detected by the FIRST SKIP lines 410 99 to 401 1 01 and the SECOND SKIP lines 401 102 to 401 104 flops When the Control Processor is expecting a byte it will first clear these flops by writing 1 to the CLR FLAGS register lines 401 105 to 401 107 and then writing a 0 to it The Control Processor will then poll the SECOND 5 flop by reading address 0x06 waiting for the status bit to become asserted When the SECOND 5 flop is asserted the Control Processor knows that the ICE Monitor has output the data and it has been captured in the READ _ BUFFER lines 401 108 to 401 114 The Control Processor then reads the READ BUFFER by reading address 0x05 lines 401 115 and 401 116 8 2 Reset Pin Block 402 Logic Equations and Explanation 8 2 1 COPS Interface 402 1 N RESET NOT RESET COP8 402 2 NOT BREAK AND NOT DISABLE RST NOT TRESET 402 3 OR START TRST AND NOT N_TRESET 8 2 2 Control Processor Interface 402 4 RESET COP amp d DATA3 402 5 RESET COP amp clk N WR 402 6 RESET COP amp ena ADR 7 0 0x00 402 7 DISABLE RST d CTL_DATA4 402 8 DISABLE RSTclk N
12. FIELD eMe Men mmm mH DATA eene FIGURE 7 TYPE 1 WAVEFORM sor CLK PIN OUTPUT PIN FIGURE 8 TYPE 2 WAVEFORM sor CLK PIN OUTPUTPIN FIGURE9 TYPE 3 WAVEFORM sor Xn OUTPUT PIN ul U S Patent Dec 7 2004 Sheet 9 of 10 US 6 829 727 B1 FIGURE 10 TYPE 4 WAVEFORM sor CLK PIN OUTPUT PIN FIGURE 11 POUT PIN FIELD LAYOUT 4071 SLOT 2 SLOT 3 SLOT 6 SLOT PC STATUS FIELD lw CONFIGURATION gt DATA REGISTER FIELD REGISTER FIELD FIGURE 12 INPUT PIN FIELD LAYOUT E SLOT 1 91072 SLOT 3 COMMAND FIELD x DATAO DATAI DATA INPUTDATAFIELD US 6 829 727 B1 Sheet 10 of 10 Dec 7 2004 U S Patent 301 NO 1 1 15 29 8409 0 JOA YAQVSH Z X 6 GBEVONVIS 390914 9 ANNOYS ZO 19 18 1 09 1 18538 I3OHVI DOA US 6 829 727 B1 1 IN CIRCUIT EMULATION OF SINGLE CHIP MICROCONTROLLERS BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to the in circuit emulation of microprocessors specifically to an improved method of emulating COP8 microcontrollers 2 Related Art It is generally recognized that real time in circuit emula tors ICE are a desirable and
13. SYNC TG CONFIG 3 0 clr RESET ACTIVE 405 21 SYNC TG DATA 2 0 d TG DATA 2 0 405 22 SYNC DATA 2 O clk CLK 405 23 SYNC DATA 2 0 ena RSLOT10 405 24 SYNC TG DATA 2 0 clr RESET ACTIVE 8 5 3 Recreated Port Input Register 405 25 TG INP 3 0 d G 3 0 405 26 TG_INP 3 O clk CLK 405 27 TG INP 3 O ena RSLOTI 8 5 4 Emulator Core Interface 405 28 RESET ACTIVE OUT FLAGS3 8 5 5 Explanation of Logic Equations The Recreated Ports Target Interface lines 405 1 to 405 16 supports the four configurations of each port pin independently Each port pin is recreated using two output buffers both of which can be tri stated One of the buffers the data buffer is used to output the data value of the port The other buffer the weak pull up buffer is used to enable a weak pull up resistor To recreate a port that is outputting a data value the output enable of the data buffer is asserted lines 405 2 405 6 405 10 and 405 14 with the data value on the buffer s input lines 405 1 405 5 405 9 and 405 13 When a data value is being output the weak pull up buffer is tri stated To recreate a weak pull up port the output enable of the data buffer is de asserted and the output enable of the weak pull up buffer is asserted lines 405 4 405 8 405 12 and 405 16 The weak pull up buffer s input lines 405 3 405 7 405 11 and 405 15 is tied to Vcc to enable it to source current thr
14. Sheet 1 of 10 US 6 829 727 B1 101 S gt 105 104 1 FIGURE 1 das 101 iceMASTER WA FIGURE 1b U S Patent Dec 7 2004 Sheet 2 of 10 US 6 829 727 1 TARGET SYSTEM MODIFIED COP8 FLASH DEVICE LD a RECREATED PORTS COPE INTERFACE T TAR G3 GO N_TAR_RESET TAR TARGET VCC ICE LOGIC CONTROL PROCESSOR CONTROL PROCESSOR IN CIRCUIT EMULATOR FIGURE 2 US 6 829 727 1 Sheet 3 of 10 Dec 7 2004 U S Patent 901 OIHNOO3 104 fr e 3138 300230 YOLINOW yya MISNI 4 i I T f 1 1 1 1 1 1 1 I 1 i t 1 1 1 1 I I 1 4 8 e EUN usa THINS HLN mv HSV14 Wve lt SLYOd U S Patent Dec 7 2004 Sheet 4 of 10 US 6 829 727 1 CLK N 423 CA Z T nm 2 oL LDO 2212 2427 BREAK __ __ ak PEL RESET m C amp lt CI tu eT LL CL CUANDO 402 lt Now CLK Lg HA TG CNIG 3 0 E C
15. Slot 1 and Slot 2 Waveform Combinations 51 s2 S3 S4 55 56 57 58 59 GCI GC2 GC3 GDO 9 GD2 0 1 GCI Gc2 GC3 GDO 9 Gm 1 GCI GC2 GC3 GD GDI GD2 1 1 G GC GDO GDI GD2 5 4 GO INPUT The G0 INPUT pin inputs control command write data and the target pin data that allows the modified COPS to recreate the input state of the four G Port digital I O pins 20 used in this interface This pin uses only Type 3 and Type 4 waveforms The INPUT pin breaks the 10 slot COPS machine cycle into two fields see FIG 12 the Command Field and the Input Data Field S10 Meaning Fetch Fetch from Flash Not Fetch PC frozen last cycle Fetch Fetch from Flash Interrupt Not Fetch Full PCU replaced last cycle Fetch Fetch from ICE Monitor Not Fetch PC incremented last cycle Fetch Fetch from ICE Monitor Interrupt Not Fetch 4 LSBs of PCU replaced last cycle GD3 GD3 GD3 GD3 is used by the ICE Logic to input commands and data to the ICE Monitor It is asserted when Slot 10 contains a logic 0 and Slot 1 contains a logic 1 The Hardware Break command is used to force the execution of a Software Breakpoint instruction BRK This command is asserted when both Slot 10 and Slot 1 contain a logic 0 When the modified COPS decodes a Hardware Break command it finishes execution of the current instruc tion and skips the next if it would normally have been FIG 1
16. WR 402 9 DISABLE RST ena ADR 7 0 0x00 402 10 START TRST d DATAS 402 11 START TRST clk WR 402 12 START EN 5 ADR 7 0 0x00 402 13 START TRST lr NOT BREAK 8 2 3 Emulator Core Interface 402 14 RESET NOT RESET 8 2 4 Target Interface Block 406 402 15 TRESET N RESET 8 2 5 Explanation of Logig Equations RESET lines 402 1 to 402 3 can be asserted at any time by the Control Processor or it can be asserted as a result of a Reset assertion on the User s Target system line US 6 829 727 B1 25 402 15 under certain conditions The Control Processor can assert RESET by writing 1 to the RESET COPS register lines 402 4 to 402 6 The Control Processor can allow an assertion of the Targets TRESET signal to assert RESET during emulation mode by writing a 0 to the DISABLE RST register lines 402 7 to 402 9 And finally the Control Processor can allow an assertion of the Targe s TRESET signal to assert RESET to start an emulation by writing 1 to the START EM TRST register lines 402 10 to 402 13 When N RESET is asserted this block asserts RESET line 402 14 to be used as part of the RESET ACTIVE logic line 401 52 8 3 Pout Pin Block 403 Logic Equations and Explanation 8 3 1 COPS Interface 403 1 POUT G1 8 3 2 Recreated Port Registers 403 2
17. asserted line 404 55 the INPUT multiplexor will select the Enabling code for output The three byte Enabling code lines 404 48 to 404 50 is serialized using a 6 bit ENABLE CNTR counter lines 404 51 to 404 54 that generates 32 counts The first eight counts output a 0 in order to prime the modified COPS detection circuit The next 24 counts output ENABLE CODE lines 404 56 to 404 79 This cycle continues until STOP CODE is asserted The ENABLE CNTR is cleared by the Control Processor by it first setting and then clearing ENABLE CLEAR lines 404 29 to 404 31 register This ENABLE CLEAR register is a mirror copy ofthe ENABLE CLEAR register in Block 401 lines 401 90 to 401 92 Monitor data is input to the ICE Monitor in the modified COPS by the Control Processor first loading the data into CMD BUFFER 7 0 lines 404 18 to 404 20 The Con trol Processor then sets the WAITING flag lines 404 21 to 404 24 This flag is synchronized to the modified COPS using a two stage synchronizer SYNC1 CMD WAITING lines 404 32 to 404 35 and SYNC2 CMD WAITING lines 404 36 to 404 39 When SYNC2__ CMD_ WAITING becomes asserted the INPUT multiplexor shifts out the Monitor Data Command during Slot 10 and Slot 1 and shifts out the data in BUFFER during Slot 2 through Slot 9 The Hardware Break Request signal CMD line 404 17 is asserted by either the Attribute Memory Control Block 504 or the Control Proce
18. be implemented with various changes and substitutions to the illustrated embodiments Such changes may include but are not limited to imple menting the present invention with different codes for the instruction set changes effecting breakpoints using on chip hardware comparators instead of a break instruction storing the Monitor program in different types of memory and changing the number of I O pins that communicate with the ICE logic Importantly the present invention is not limited to use with the COPS microcontroller but may be used generally with a microcontroller which does not provide access to internal address and data busses It will be readily understood by those skilled in the art that various other changes in the details materials and arrange ments of the parts and operations which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as set forth in the claims What is claimed is 1 An in circuit emulation system comprising a a target system b an external circuit a microcontroller contained in said target system com prising US 6 829 727 B1 31 1 a processing unit can 2 a plurality of ports that interface to circuits on said target system d a memory from which said microcontroller executes a program e means for one or more of said I O ports to be recon figured to interface wi
19. in circuit emulation system of claim 23 wherein said microcontroller further comprising a monitor memory executing control routines based on a sixth data input on said reconfigured I O ports from said external circuit 29 The in circuit emulation system of claim 16 wherein said first connector and said second connector on said target system comprising 1 said first connector is patterned on said target system as a first row of connections 2 said second connector is patterned on said target system as a second row of connections 3 said first row of connections and said second row of connections are placed parallel to each other a prede termined distance apart 4 the connections of said first row and said second row are aligned in such a manner so as the connection of a recreated port is directly opposite the connection of the reconfigured I O port that 1t recreates whereby shorting opposing connections of the parallel rows of connections reconfigures said in circuit emulation system into a production system 30 The in circuit emulation system of claim 16 wherein said connector on said target system comprises a wireless interface 10 15 20 25 30 35 40 45 34 31 A method of emulating a microcontroller in a target system comprising a providing means of communication between said microcontroller and an external circuit b providing means of reconfiguring ports of said microcontroller to
20. in many cases a necessary tool for engineers involved in designing applications that use an embedded microprocessor An ICE allows the engineer to exercise direct control over the execution of his application program being run on the microprocessor This control enables the engineer to determine if a program is performing as expected and in the case where it is not the ICE makes it much easier to debug the program An ICE typically has some type of probe that replaces the actual microprocessor on the engineer s application printed circuit board Through an interface usually hosted on a standard Personal Computer an engineer can use the ICE to view and modify the microprocessor s internal state start his program at specific locations stop his program at specific locations or events or view a snapshot of his program s execution history An ICE is designed around the address and data bus of the microprocessor It monitors and controls the flow of addresses and data on the microprocessor s busses and thereby provides the features used by the engineer to control test and debug a program However a special case arises with a class of embedded microprocessors called single chip microcontrollers such as the National Semiconductor COP8 family There is no address and data bus These microcon trollers execute their program out of an internal non volatile code memory such as a ROM EPROM or Flash To provide the advantages of an ICE to
21. 06 gt The byte lt 06 gt is the command value that is decoded by the command decoder In executing this command the ICE Monitor calls the low level ISP mass erase routine that is part of the Monitor ROM The ISP routine erases the complete flash memory implemented in the microcontroller When the ISP routine is done erasing the flash memory it returns to this command routine This routine then exits through a common end of command routine and returns to the idle loop to await the next command 4 1 7 Emulation Reset Command The EMULATION RESET command is used to start execution of the user s program from a reset This command is four bytes long and is of the form lt 07 gt X B lt A gt The byte lt 07 gt is the command value that is decoded by the command decoder The X is the value for the X register The B is the value for the B register The A is the value for the A register In executing this command the ICE Monitor restores the X B and A registers to the values that were previously set by the user s program The PSW register is not restored since it is initialized by a Reset After restoring the last register this routine stays in a loop waiting for the modified COPS to be Reset When the ICE Logic asserts Reset to the microcontroller s RESET pin the Break state signal is cleared After Reset is de asserted the modified COPS will start execution at address 0000 of the flash memory user s program
22. 0x0C AND ENABLE BYTEO04 ENABLE CNTR 0 00 AND ENABLE BYTEOS ENABLE CNTR 0x0E ENABLE BYTEO06 ENABLE CNTR 0x0F AND ENABLE BYTEO7 ENABLE CNTR 0x10 ENABLE BYTE10 ENABLE CNTR 0x11 AND ENABLE BYTE11 ENABLE CNTR 0x12 ENABLE BYTE12 OR ENABLE CNTR 0x13 AND ENABLE BYTE13 ENABLE CNTR 0x14 ENABLE BYTE14 ENABLE CNTR 0x15 ENABLE 15 OR ENABLE CNTR 0x16 AND ENABLE BYTE16 ENABLE CNTR 0x17 ENABLE BYTE17 ENABLE CNTR 0x18 ENABLE BYTE20 ENABLE CNTR 0x19 ENABLE BYTE21 ENABLE CNTR 0x1A AND ENABLE BYTE22 ENABLE CNTR 0x1B AND ENABLE BYTE23 ENABLE CNTR 0 1 AND ENABLE BYTE24 10 15 20 25 30 35 40 45 50 55 60 65 28 continued 404 77 OR ENABLE CNTR 0x1D AND ENABLE BYTE25 ENABLE CNTR 0x1E AND ENABLE BYTE26 OR ENABLE CNTR 0x1F AND ENABLE 27 404 78 404 79 8 4 4 Explanation of Logic Equations The INPUT pin is used to input the ICE Hooks enabling code commands command data and the Recreated Port pins input values The INPUT multiplexor lines 404 2 to 404 16 determines what is shifted out of the ICE Logic onto the modified COP8 INPUT pin line 404 1 If STOP CODE is not
23. 1 waveform FIG 8 shows a Type 2 waveform FIG 9 shows a Type 3 waveform FIG 10 shows a Type 4 waveform FIG 11 shows the POUT pin field layout 15 FIG 12 shows the INPUT pin field layout FIG 13 shows the signal layout on the ICE Logic connector DETAILED DESCRIPTION In the following description numerous specific details are set forth to provide an understanding of the present inven tion It will be apparent however to those skilled in the art and having the benefit of this disclosure that the present 25 Invention may be practiced with apparatus and processes that vary from those specified herein Reference herein to one embodiment embodiment means that a particular feature structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention The appearance of such phrases herein are not necessarily all referring to the same embodiment Furthermore various particular features structures or char acteristics may be combined in any suitable manner in one or more embodiments 30 35 1 0 COPS Architecture Machine Cycle and Timing The COPS is an 8 bit accumulator based Harvard archi tecture microcontroller with a maximum program memory space of 32 Kbytes As a microcontroller all of its program memory and data memory resides on chip It has no external bus The program memory of all COPS versions used with th
24. 2 INPUT Pin Field Layout COPS Machine Cycle Slot 10 Slot 1 Slot 2 Slot 3 Slot 9 CLK Pin A Z Na Wu N 22 CAES Nu N Z Command Field Data0 Datal Fy 7 Data7 Command Field can contain three different com mands and the Input Data Field can contain two different types of data see Table V The Input Data Field can contain either 8 bits of ICE Monitor data or 4 bits of Target pin data ICE Monitor data is used when the ICE Logic is inputting to the ICE Monitor a command to decode or the data required by a previously sent ICE Monitor command As the 66X20 ICE Monitor data is input to the modified COPS it is shifted into the ICE Monitor s receive buffer ICEDATA register After all eight bits are shifted in a received byte status flag Is asserted that is readable by the ICE Monitor The Target pin data is used to allow the modified COPS to recreate the input functionality of the four G port pins used in this interface The ICE Logic samples its recreated G 0 3 port pins that are connected to the User s target at the end of Slot 1 When Input Data Field contains the Target pin data the ICE Logic shifts in GO during Slot 2 G1 during Slot 3 G2 during Slot 4 and G3 during Slot 5 The modified COPS uses these shifted in values in place of the pins normal input buffer values Slot 6 through Slot 9 are don t cares and are ignored by th
25. 3 AND SYNC CMD WAITING AND CMD_BUFFER1 404 8 RSLOT4 AND NOT SYNC2_CMD_ WAITING AND TG_INP2 404 9 RSLOT4 AND SYNC_CMD_WAITING AND CMD_BUFFER2 404 10 RSLOTS AND NOT SYNC2 CMD WAITING AND TG_INP3 404 11 RSLOTS AND SYNC_CMD_ WAITING AND CMD_BUFFER3 404 12 RSLOT6 AND CMD_BUFFER4 404 13 RSLOT7 AND CMD_ BUFFERS 404 14 RSLOT9 AND BUFFER 404 15 RSLOT9 AND CMD_BUFFER7 404 16 STOP CODE AND ENABLE CODE 404 17 INP HW CMD SYNC2 HW CMD OR HW BP 8 4 2 Control Processor Interface and Synchronizing Logic 404 18 404 19 404 20 CMD BUFFER 7 0 d DATA 7 0 CMD BUFFER 7 0 clk N CTL WR CMD_ BUFFER 7 O ena CTL_ADR 7 0 0x01 CMD WAITING d CTL_DATA1 CMD WAITING clk WR CMD WAITING ena ADR 7 0 0x00 CMD WAITING clr SYNC2_CMD_ WAITING HW CMD d CTL_DATA2 404 21 404 22 404 23 404 24 404 25 04 26 04 27 04 28 04 29 04 30 04 31 04 32 04 33 04 34 04 35 04 36 04 37 04 38 04 39 04 40 04 41 404 42 404 43 404 44 404 45 404 46 404 47 F amp amp 4 R U US 6 829 727 B1 27 continued HW CMD cdk N WR HW CIL 7 0 0x00 HW CMD clr BREAK ENABLE CLEAR d CTL_DATA7 ENABLE CLEAR clk
26. DATAO ena NOT RSLOT1 OR RSLOT2 RSLOT2 RSLOT2 RSLOT2 RSLOT2 RSLOT2 RSLOT2 RSLOT2 8 1 5 Mode Enabling Logic 401 90 401 91 401 92 401 93 401 94 401 95 401 96 401 97 401 98 ENABLE CLEAR d DATA7 ENABLE CLEAR clk WR ENABLE CLEAR ena ADR 7 0 0x00 CLK DETECI 2 0 d DETECT 2 0 1 CLK DETECI 2 O clk CLK DETECT 2 0 clr ENABLE CLEAR STOP CODE VCC STOP CODE clk NOT CLK DETECT2 STOP ENABLE CLEAR 8 1 6 Control Processor Read Buffer Logic 401 99 401 100 401 101 401 102 401 103 401 104 401 105 401 106 401 107 401 108 401 109 401 110 401 111 401 112 401 113 401 114 401 115 401 116 401 117 FIRST SKIP d VCC FIRST SKIP clk SKIP FIRST SKIP clr CLR FLAGS SECOND SKIPd FIRST SKIP SECOND SKIPcIk SKIP SECOND SKIPclr CLR FLAGS CLR FLAGS CTL_DATAO CLR_FLAGS clk WR CLR FLAGS ena ADR 7 0 0x00 READ BUFFER 7 0 d OUT DATA 7 0 READ BUFFER 7 O clk CLK READ BUFFER 7 0 ena READ CNTR 2 0 0x2 AND RSLOT1 READ CNTR 2 0 d READ CNTR 2 0 1 READ CNTR 2 O clk CLK READ CNTR 2 0 ena FIRST SKIP AND NOT READ CNTR2 AND RSLOT10 READ CNTR 2 O clr NOT FIRST SKIP DATA 7 0 READ BUFFER 7 0 DATA 7
27. If the decremented Count value is not zero it increments the Starting Address value reads the value at the new address outputs it to the ICE Logic and decrements the Count value again This continues until the Count value is equal to zero When the Count value is zero this routine exits through a common end of command routine and returns to the idle loop to await the next command 4 1 2 Data Memory Write Command The DATA MEMORY WRITE command is used to input byte values from the ICE Logic and write the values to the modified COPS internal data memory and its special func tion registers This is a variable length command and is of the form lt 02 gt Starting Address Count Byte 1 gt Byte 2 gt Byte n US 6 829 727 B1 7 The first byte lt 02 gt is the command value that is decoded by the command decoder The Starting Address is the address of the first location to be written The Count is the number of bytes remaining to be sent in the command as well as the number of locations to be written Byte 1 Byte 2 gt Byte gt are the values to be written In executing this command the ICE Monitor inputs Byte 1 from the ICE Logic and writes it to the starting address It then decrements the Count value If the decremented Count value is not zero it increments the Starting Address value inputs the next byte from the ICE Logic writes this value to the new address and decrements the Co
28. L LE 403 OUT FIAGS A O 4 Pour TG INP 3 0 GO PLOT 7 INPUT PIN INTERFACE 404 OUT_FLAGS 4 0 az POUT OUT DATA T O FIGURE 4a US 6 829 727 1 Sheet 5 of 10 Dec 7 2004 U S Patent 405532084 1041102 CPRD PWR DATA P CP BREAK How 407 N_TAR_RESET 330K 582 78 25 w UIN FIGURE 4b US 6 829 727 1 Sheet 6 of 10 Dec 7 2004 U S Patent ZJ i JI lI CU 1 09 Hd N Smg T yu dg Jd 031734238 e ui FIGURE 5a U S Patent Dec 7 2004 Sheet 7 of 10 US 6 829 727 B1 N CIL WR CTL RD N TM RD CTL_ADRI7 0 CL OMA LO 5 POUT TM 16 0 OUT_FLAGS 4 0 2 RSLOT 10 1 e E BREAK 58 14 0 TON TON 2 RD gt amp LE NMWI D me AM 40 5 2 zm AM DATA 3 0 1 8 CIL DATA T O OUT FLAGS 4 0 RSLOTTIO 1 T BREAK 04 O FIGURE 5b U S Patent Dec 7 2004 Sheet 8 of 10 US 6 829 727 B1 FIGURE 6 OUTPUT PIN FIELD LAYOUT 401 so som 90710 STATUS STATUS2 DATAO DATA STATUS
29. P d FETCH AND OUTPUT SKIP clk CLK SKIP ena RSLOT2 SKIP clr RESET ACTIVE PC_REPLACE d NOT FETCH AND OUTPUT PC_REPLACE clk CLK PC REPLACE ena RSLOT2 PC REPLACE clr RESET ACTIVE RESET ACTIVE set RESET RESET 4 NOT LEVEL NEG _ EDGE XOR OUTPUT RESET ACTIVE clk CLK RESET ACTIVE ena RSLOT1 RESET ACTIVE clr RSLOT2 OUT FLAGSO FETCH OUT FLAGSI SKIP OUT FLAGS2 REPLACE OUT FLAGS3 RESET ACTIVE OUT FLAGS4 STOP CODE BREAK d LEVEL CLK EDGE XOR OUTPUT BREAK clk CLK 10 15 20 25 30 35 40 45 50 55 60 65 401 64 401 65 22 continued BREAK ena RSLOT2 BREAK clr RESET ACTIVE 8 1 4 Output Pin Data Register OUT DATA7 d OUTPUT DATA7 clk CLK OUT DATA7 ena NOT RSLOT1 OR OUT OUT DATA7 DATA6 clk CLK DATA6G ena NOT RSLOT1 OR OUT DATAS d OUT DATA6 OUT DATAS clk CLK DATAS ena NOT RSLOTI OUT DATA4 d OUT DATAS OUT DATA4 clk OUT DATA4 ena NOT RSLOT1 OR DATA3 d OUT DATA4 DATA3 clk CLK DATA3 ena NOT RSLOT1 OR OUT DATA2 d OUT DATA3 DATA2 clk CLK OUT DATA2 ena NOT RSLOT1 OUT DATA1 d OUT DATA2 DATA1 clk CLK DATA1 ena NOT RSLOT1 DATAO d DATA1 OUT DATAO clk CLK OUT
30. PL replacement What part of the PC is actually replaced is signaled by the POUT pin see section 5 3 A special case of PL PU replacement is an interrupt The POUT Pin is also used to signal that an interrupt is being processed Data Field Slots to 10 Data The data is shifted out from a COPS internal data bus using only Type 3 or Type 4 waveforms Summary of the OUTPUT Pin G2 TABLE I Valid Slot Waveform Combinations Slot 1 Slot 2 53 54 55 56 57 58 S9 510 Meaning pe Type 1 DO D2 pe Type 2 DO D2 D3 Type Type 3 DO D2 Type Type 4 DO D2 Type 2 Type 1 DO D1 D2 D3 Type 2 Type 2 D1 D2 D3 2 3 D0 D1 D2 D3 Type 2 4 D0 D1 D2 D3 3 3 D4 D4 D4 D4 D4 D4 D4 D4 D5 D6 D7 Nota Fetch Break State D 7 0 o bus data Nol D 7 Not a Fetch Emulation State D 7 0 o bus data previous cycle contains internal D5 D6 D7 a Fetch Break State 0 of previous cycle contains PC data D5 D6 D7 previous cycle contains internal D5 D6 D7 D 7 0 o Fetch Break 0 o a Fetch Emulation State previous cycle contains PC data DS D6 D7 State previous cycle contains interna DS D6 D7 Break 0 o bus data State Instruction skipped previous cycle contains interna D5 Emulation State 0 o bus data D6 D7 previous cycle contains interna DS D6 D7 Emulation Sta
31. SP flash memory page erase routine This low level ISP routine requires the fol lowing registers to be set up before it is called ISPADHI High byte of the starting address of the page to be erased ISPADLO Low byte of the starting address of the page to be erased The low level ISP erases a page of flash memory starting at the lt ISPADHI gt lt ISPADLO gt page boundary Before the PROGRAM MEMORY PAGE ERASE com mand is sent to the ICE Monitor the ICE Logic loads the appropriate values in the ISPADHI and ISPADLO registers using the DATA MEMORY WRITE command This command is one byte long and is of the form lt 05 gt The byte lt 05 gt is the command value that is decoded by the command decoder In executing this command the ICE Monitor calls the low level ISP page erase routine that is part of the Monitor ROM The ISP routine erases a page of flash memory starting at the specified page boundary When the ISP routine is done erasing the flash memory it returns to this command routine This routine then exits through a common end of command routine and returns to the idle loop to await the next command 4 1 6 Program Memory Mass Erase Command The PROGRAM MEMORY MASS ERASE command is used to erase the complete flash memory up to 32 Kbytes implemented in the modified COPS The flash memory has to be erased before new values can be written to it US 6 829 727 B1 9 This command is one byte long and is of the form lt
32. This command can be abort before Reset is asserted If the ICE Monitor receives a byte from the ICE Logic while it is looping it will fall through the loop and exit through a common end of command routine and return to the idle loop to wait for a new command 4 1 8 Emulation Go Command The EMULATION GO command is used to start execu tion of the user s program at a specific address The address where execution will begin is on the top of the software stack in the modified COPS internal data memory This command is five bytes long and is of the form lt 08 gt X B lt PSW gt lt A gt The byte 08 is the command value that is decoded by the command decoder The X is the value for the X register The B is the value for the B register The lt PSW gt is the value for the PSW register The A is the value for the A register Before the EMULATION GO command is sent to the ICE Monitor the ICE Logic loads the address where the user wants his program to begin executing This address is placed on the top of the software stack using the DATA MEMORY WRITE command In executing this command the ICE Monitor restores the X B PSW and A registers to the values that were previously set by the user s program This routine then executes a instruction that clears the Break state signal and pops an address off the software stack and loads it into the program counter Execution of the user s program in flash memory begins a
33. a United States Patent US006829727B1 10 Patent No US 6 829 727 B1 Pawloski 45 Date of Patent Dec 7 2004 54 IN CIRCUIT EMULATION OF SINGLE CHIP 6 571 356 B1 5 2003 Mehr et al 714 28 MICROCONTROLLERS 6 598 176 7 2003 Tago 24 714 28 2002 0007264 1 1 2002 Swoboda 703 28 75 Inventor Martin B Pawloski Scottsdale AZ 542 A A TRE et al 1 05 Ong cited by examiner 73 Assi Metalink Corp Chandler AZ US 73 SONUS S Primary Examiner Robert Beausoliel Notice Subject to any disclaimer the term of this Assistant Examiner Yolanda L Wilson patent is extended or adjusted under 35 57 ABSTRACT U S C 154 b by 329 days An in circuit emulation system consisting of an emulation 21 Appl No 09 759 577 base and a slightly modified flash based COPS architecture microcontroller In addition to the flash memory where the 22 Filed Jan 12 2001 User s program resides the COPS device includes a small Gi dit CI note aD 11 00 ROM area with a monitor program that is used to commu nicate commands and data with the emulation base Two 52 U S 714 28 714 31 714 33 new instructions are added one for entering the ROM area 703 28 and one for exiting it A small set of the COP8 device s 58 Field of Search 714 28 40 31
34. ard headers manufactured by 3M part number 2380 5121TN or Molex part number 10 88 1801 are accept able When the User is using the emulator during development a mating connector from the emulator is placed on the header The signals from the modified COPS are connected to the ICE Logic through one side of the header The ICE Logic s recreated ports and target reset signal are connected to the User s system through the other side of the header When the User wants to test his system without the emulator he can simply short the pins across the header using standard shorting blocks This connects the target system logic directly to the pins of the modified COPS For production the header need not be inserted and the PCB can then be assembled with shorting wires connecting adjacent holes 1 to 2 3 to 4 etc in the header pattern An alternative that simplifies production would be to lay out the PCB with traces connecting adjacent holes During development the engineer would cut the traces before inserting the 2x7 header In production with the adjacent holes already shorted no further assembly work on the header is required 8 0 Details of the Core Ice Logic 8 1 Output Pin and Clock Pin Block 401 Logic Equations and Explanation 8 1 1 COPS Interface 401 1 401 2 CLK G3 OUTPUT G2 US 6 829 727 B1 continued 401 3 G2 401 4 G2 oe STOP CODE 8 1 2 Machine Cycle Synchron
35. breakpoints triggers and other actions based on said recreated program counter 8 The in circuit emulation system of claim 1 wherein said microcontroller further comprising 1 a data memory 2 a plurality of registers 9 The in circuit emulation system of claim 8 further comprising means for said external circuit to recreate a first data contained in said data memory as said program executes 10 The in circuit emulation system of claim 8 further comprising means for said external circuit to recreate a second data of one or more of said registers as said program executes 11 The in circuit emulation system of claim 8 further comprising a second trace memory to capture said first data and said second data 12 The in circuit emulation system of claim further comprising a second control circuit coupled to said external circuit providing breakpoints triggers and other actions based on said first data and said second data 13 The in circuit emulation system of claim 1 wherein said microcontroller further comprising a monitor memory containing means for executing commands from said exter nal circuit 14 The in circuit emulation system of claim 1 wherein means for coupling between said microcontroller and said external circuit comprising 1 a pattern on said target system with two parallel rows of connections 10 15 20 25 30 35 40 45 50 55 60 65 32 2 a first row of said connect
36. bytes into the flash memory starting at address lt ISPADHI gt lt ISPADLO gt Before the PROGRAM MEMORY WRITE command is sent to the ICE Monitor the ICE Logic loads the appropriate values in the ISPADHI ISPADLO and COUNT registers using the DATA MEMORY WRITE command This command is two bytes long and is of the form lt 04 gt Buffer Address The first byte lt 04 gt is the command value that is decoded by the command decoder The Buffer Address is the starting address of the buffer in the modified COPS internal data memory where the bytes to be written to the flash memory are stored In executing this command the ICE Monitor stores the Buffer Address in the X register It then calls the low level ISP write routine that is part of the Monitor ROM The ISP routine reads the number of bytes requested from the inter nal data memory buffer starting at the address contained in X and writes them to the flash memory starting at the address specified When the ISP routine is done writing the flash memory it returns to this command routine This routine then exits through a common end of command routine and returns to the idle loop to await the next command 4 1 5 Program Memory Page Erase Command The PROGRAM MEMORY PAGE ERASE command is used to erase a page of the flash memory A page is typically 64 or 128 bytes in size The flash memory has to be erased before new values can be written to it This command uses the low level I
37. cikg Z N FIG 9 Type 3 Waveform they are used to synchronize the ICE Logic and COP8 on a machine cycle instruction cycle and state basis The four 45 OUTPUT Pin XXXX ________ XXXX waveforms are defined as follows Type 4 waveform HIGH voltage at negative CLK edge HIGH voltage level at positive CLK edge LOW voltage at positive CLK edge s Decoded by the ICE Logic as a 1 logic value Type 1 waveform HIGH voltage at negative CLK edge FIG 10 Type 4 Waveform Decoded by the ICE Logic as a Sync bit with a 0 logic value Slot me 27 Pv a FIG 7 Type 1 Waveform OUTPUT Pin XXXX XXXX 60 se Status1 Slot 1 Information Machine and Instruction CLK Pin _ N 7 synchronization The OUTPUT signal in Slot 1 is used to synchronize the ICE Logic to the modified COP8 on both machine cycle and instruction cycle basis During normal 65 execution this slot will always contain either Type 1 or a Type 2 waveform Since there are no Sync bits in the Data Field of the OUTPUT signal the first slot with a Sync bit OUTPUT Pin XXXX N XXXX US 6 829 727 B1 13 following a slot with no Sync bit identifies it as Slot 1 machine synchronization The type of Sync bit Type 1 or Type 2 identifies whether or not this is the first cycle of an instruction instruction synchronization A Type 2 wave form signals the first cycle of an instruction and is defined as a Fetch flag The ICE Lo
38. e modified COPS The three commands available in the Command Field are the Hardware Break command the Monitor Data command and the Recreated Port Input command The Recreated Port Input command is the default command and is asserted when Slot 10 contains a logic 1 and Slot 1 contains a logic 0 The Monitor Data command is used only in Break state It 45 50 55 60 65 skipped pushes the PC on the stack and then vectors to the ICE Monitor When the Command Field contains a Hard ware Break command the Input Data Field always contains Port Input data The Hardware Break command is disabled if the modified COPS is already in the Break state However if the modified COPS is in the Break state and the Hardware Break com mand is asserted and remains asserted as the ICE Monitor executes the Return to Flash instruction RETF the modi fied COPS will execute one instruction and then vector back to the ICE Monitor The INPUT pin can also be used to force the execution of a Software Breakpoint instruction even if the modified COPS is in either Idle or Halt mode Power Saving modes When the modified COPS is in one of its Power Saving modes the CLK pin is not toggling As a result the Hardware Break command cannot be input In order to force the modified COPS to exit from the Power Saving mode and execute a Software Breakpoint instruction the ICE Logic drives the INPUT pin to a logic 0 then to a logic 1 and
39. econd data 37 The method of claim 31 further providing means for storing said first data and said second data in a second trace memory 38 The method of claim 31 further providing means for performing breakpoints triggers and other actions based on said first data and said second data 39 The method of claim 31 further providing means for said target system to be used either as an in circuit emulation System or a production system
40. ect of the invention is to allow emulation of microcontrollers with integrated high per formance analog peripherals without degrading the ana log performance 3 An object of one aspect of the invention is to allow emulation of the COP8 in the actual environment in which it is going to be used without having to ruggedize the emulator to handle hostile conditions 4 An object of one aspect of the invention is to allow the user s target system to be easily switched by means of a standard simple connector between a development sys tem that interfaces to the emulator and a final production system that can be shipped to a customer US 6 829 727 B1 3 5 An object of one aspect of the invention is to provide circuitry in a modified COPS to allow a range of emula tors 6 An object of one aspect of the invention is to require a minimal number of modified COPS pins needed to inter face to the emulator to allow for small pin count micro controllers 7 An object of one aspect of the invention is not to rely on an external clock as a timing source and be clocking scheme independent 8 An object of one aspect of the invention is to be able to detect internal Resets so as to allow emulation of COP8 microcontrollers without an external Reset pin 9 An object of one aspect of the invention is the ability to recreate the COPS digital pins that interface to the emu lator and that these pins can have multiplexed functionality not j
41. gic also uses the absence of Sync bits to decode internal resets If there hasn t been a Sync bit in the last 10 CLK periods AND external Reset has been de asserted the ICE Logic will decode this as the modified COPS is resetting internally Status2 Slot 2 Information State and Status This slot is used to pass the current state Break or Emulation instruction status skipped or not and PC replacement status replace part of the PC or not The exact meaning of the Status information in this slot depends on the information decoded in Slot 1 See Table I for a complete listing of all Slot 1 and Slot 2 combinations The presence or absence of a Sync bit in this slot determines the State information If a Sync bit is present the modified COPS is in Break state If there is no Sync bit the modified COPS is in Emulation state 10 15 20 14 Decoding Slot 2 logic value information depends on the presence or absence of a Slot 1 Fetch flag If Slot 1 contains a Fetch flag the logic value of this slot is used to specify whether or not the current instruction is being skipped A logic value of 1 Type 2 or Type 4 waveform specifies that the current instruction is being skipped If Slot 1 does not contain a Fetch flag the logic value of this slot is used to specify whether or not the lower byte PL or the upper 7 bits PU of the program counter PC had been replaced in the previous cycle A logic value of 1 specifies a PU
42. he ICE Monitor and returns to emulating the user s program see sections 4 1 7 EMULATION RESET COMMAND and 4 1 8 EMULA TION GO COMMAND After outputting the four registers the ICE Monitor program in accordance with one embodiment of the present invention then enters a loop idle loop waiting for a command byte from the ICE Logic Once a command byte is received the ICE Monitor decodes the command executes it and then returns to the idle loop awaiting the next command Commands are available to read and write the data memory RAM the special function registers and the flash program memory In addition commands are used to return the modified COPS into emulation mode where it executes the User s program which is stored in flash memory 4 1 Details of the Ice Monitor Commands 4 1 1 Data Memory Read Command The DATA MEMORY READ command is used to read byte values from the modified COPS internal data memory and its special function registers and output the values to the ICE Logic This command is three bytes long and is of the form 01 Starting Address Count The first byte lt 01 gt is the command value that is decoded by the command decoder The Starting Address is the address of the first location to be read Count is the number of locations to be read In executing this command the ICE Monitor reads the value at the starting address and outputs it to the ICE Logic It then decrements the Count value
43. ich the SP is again incremented Next the contents of the data memory location referenced by the SP are transferred to the PCL The return address has now been retrieved from the stack in data memory RAM The CPU then starts executing the program in the flash memory at the return address 10 15 20 25 30 35 40 45 50 55 60 65 6 4 0 Details of the Ice Monitor In one embodiment of the present invention the ICE Monitor is a program of approximately 512 bytes in length that is physically implemented as a non programmable Read Only Memory ROM logically located outside the standard 32 Kbyte COPS program memory space The ICE Monitor program receives and executes commands that are sent to it by the ICE Logic The ICE Monitor program may be stored in a ROM of any suitable design Furthermore the present invention is not limited to the particular type of storage medium in which the ICE Monitor program is stored Execution of the ICE Monitor begins when the modified COPS detects a breakpoint and jumps to the ICE Monitor entry point after pushing the current program counter onto the stack The first instructions of the ICE Monitor are used to output the A PSW B and X registers to the ICE Logic These registers are used by the ICE Monitor in executing its commands and this initial action preserves their values as used in the user s program context These values are restored to the registers before the system exits t
44. iming chain continues through Slot 3 to Slot 10 and then Slot 1 RSLOT3 to RSLOT10 RSLOTI lines 401 12 to 401 39 The timing chain will stay in Slot 1 until another sync bit is detected and Slot 2 is asserted The FETCH flag lines 401 40 to 401 43 is decoded every cycle based on a sync bit in Slot 1 The SKIP flag lines 401 44 to 401 47 is decoded every time FETCH is asserted and there is 1 logic level on the OUTPUT pin during Slot 2 The PC REPLACE flag lines 401 48 to lines 401 51 is decode every non FECTH cycle when there is a 417 logic level on the OUTPUT pin during Slot 2 The RESET ACTIVE flag lines 401 52 to 401 56 is asserted whenever RESET is asserted on the modified COPS s N RESET pin lines 402 1 to 402 3 and 402 14 or when ever the timing chain is in Slot 1 and the modified COPS doesn t output a sync bit These flags are grouped together with the STOP CODE flag see below as the bus OUT _ FLAGS 4 0 lines 401 57 to 401 61 and are available to the other blocks of the ICE Logic The BREAK flag lines 401 62 to 401 65 is decoded every cycle based on a sync bit in Slot 2 The data that is available on the OUTPUT pin is captured every cycle using an eight stage shift register lines 401 66 to 401 89 The LSB of the data is initially captured in OUT DATA during Slot 3 During the next seven Slots the next least significant bits are captured in OUT DATAT7 while the previously captured bits are shifted through the
45. interface with said external circuit c providing a memory from which said microcontroller will execute a program d providing means for said external circuit to load said program in said memory providing means for said external circuit to control where said microcontroller will start and stop executing said program f providing means for the reconfigured I O ports of said microcontroller to be recreated by said external circuit g providing means for the recreated I O ports to replace said reconfigured I O ports on said target system whereby said microcontroller will be emulated in said target system while maintaining all functionality of its said I O ports and excluding dedicated ports to interface to said external circuit 32 The method of claim 31 further providing means for said external circuit to recreate the program counter of said microcontroller 33 The method of claim 32 further providing means for capturing said program counter in a first trace memory 34 The method of claim 32 further providing means for performing breakpoints triggers and other actions based on said program counter 35 The method of claim 31 further providing means for said external circuit to recreate one or more locations of a data memory of said microcontroller creating a first data 36 The method of claim 31 further providing means for said external circuit to recreate one or more registers of said microcontroller creating a s
46. ions connecting to said reconfigured I O ports of said microcontroller 3 a second row of said connections connecting to said recreated port functionality of said external circuit 4 the connections of said first row and said second row are aligned in such a manner so as the connection of the recreated port is directly opposite the connection of the reconfigured I O port that it recreates whereby shorting opposing connections of said parallel rows of connections reconfigures said in circuit emulation system into a production system 15 The in circuit emulation system of claim 1 wherein said means for coupling between said microcontroller and said external circuit comprises a wireless interface 16 An in circuit emulation system comprising a a target system b an external circuit c a microcontroller contained in said target system com prising 1 a processing unit 2 a plurality of I O ports that interface to circuits on said target system d a memory from which said microcontroller executes a program a first connector on said target system for coupling one or more of said I O ports to said external circuit f said external circuit outputs a predetermined pattern to said I O ports causing said microcontroller to recon figure one or more of said I O ports to interface with said external circuit g said microcontroller outputs a first data on the recon figured I O ports to enable said external circuit to rec
47. is invention is implemented as flash memory 40 45 addition to memory different versions of the COP8 also have different amounts and types of peripherals on chip Some common examples of these on chip peripherals include timers digital I O ports an interrupt controller and A D converters 50 The COPS basic machine cycle consists of ten clock periods Each clock period is referred to as a Slot So a machine cycle consists of Slot 1 through Slot 10 The instruction set consists of one byte two byte and three byte instructions The shortest instructions execute in one machine cycle The longest instruction executes in seven machine cycles The instruction set is composed of arithmetic logical memory transfer and transfer of control instructions The arthmetic and many of the logical instructions use the accumulator as the destination operand Several of the logical instructions either skip or execute the next instruc tion depending on the result There are different transfer of control instructions with a 31 byte range a 2 Kbyte page range or a 32 Kbyte range For a more detailed description of the COPS refer to National Semiconductor s COP8 Family User s Manual US 6 829 727 B1 5 2 0 Modified COPS Core In one aspect of the present invention the standard COPS architecture was modified First a small amount of read only memory ROM was added beyond the 32 K program memory address space This ROM contains the in sy
48. ization and Timing 401 5 LEVEL AT NEG CLK EDGE d OUTPUT 401 6 LEVEL AT NEG EDGE k CLK 4017 A SYNC BIT d NOT LEVEL NEQ EDGE XOR OUTPUT 401 8 NOT A SYNC BIT clk CLK 401 9 RSLOT2 d NOT A SYNC AND LEVEL NEG EDGE XOR OUTPUT 401 10 RSLOT2 clk CLK 401 11 RSLOT2 clr RESET 401 12 RSLOT3 d RSLOT2 401 13 RSLOT3 clk CLK 401 14 RSLOT3 clr RESET 401 15 RSLOT4 d RSLOT3 401 16 RSLOT4 clk CLK 401 17 RSLOT4 clr RESET 401 18 RSLOTS d RSLOT4 401 19 RSLOTS clk CLK 401 20 RSLOTS clr RESET 401 21 RSLOT6 d RSLOTS 401 22 RSLOT 6 clk CLK 401 23 RSLOT 6 clr RESET 401 24 RSLOT7 d RSLOT6 401 25 RSLOT7 clk CLK 401 26 RSLOT7 clr RESET 401 27 RSLOTS d RSLOT7 401 28 RSLOTS8 clk CLK 401 29 RSLOT9 clr RESET 401 30 RSLOT9 d RSLOTS 401 31 RSLOTO clk CLK 401 32 RSLOT9 clr RESET 401 33 RSLOT10 d RSLOT9 401 34 RSLOT10 clk CLK 401 35 RSLOT10 clr RESET 401 36 RSLOTI set RESET 401 37 RSLOT1 d RSLOT10 RSLOT1 401 38 RSLOT1 clk CLK 401 39 RSLOT1 clr RSLOT2 EN o p p p p p 8 1 3 Output Pin Flag Decodes FETCH d LEVEL_AT_NEG_CLK_EDGE XOR OUTPUT FETCH clk CLK FETCH ena RSLOTI1 FETCH clr RSLOT10 SKI
49. l Reset asserted and continually inputs the key until it detects transitions on the CLK G3 pin which it decodes as CLK being active and the modified COP8 in ICE Hooks mode The ICE Logic then tri states the clock it is outputting on OUTPUT disables the key output on INPUT and de asserts external Reset In order to minimize the chance of an accidental enabling of ICE Hooks mode in a non development environment the length of the key should be fairly long gt 16 bits An example of an implementation that uses a 24 bit key would be the following pattern Ox47CF09 The modified COP8 does not start shifting in the key until its internal initializa tion is complete Once ICE Hooks is enabled the only way to exit from the mode is to completely remove power from the modified COPS 7 0 Details of the Mechanical Connection to the Emulator The physical connection between the modified COP8 and the ICE Logic is accomplished with a standard 2x7 header To use the emulator with the modified COPS soldered on the target system PCB the User would design his PCB with a 2x7 header pattern located next to the G Port of the modified COPS The connections to this pattern are shown below in FIG 13 FIG 13 Signal layout on ICE Logic connector 40 45 50 55 65 The preferred implementation of the connector uses a 2x7 header with 100 mil 0 1 spacing between all pins Each pin is a 25 mil square pin with a 230 mil insertion length Stand
50. microcontroller Anew Bond Out is required for each new functional variation While a new Bond Out chip is not needed if the new variation of the microcontroller is simply less memory or fewer IO pins it is required whenever new on chip peripherals or new I O interfaces are added or when there are architectural enhancements This can get particularly burdensome when one considers that usually two to four new functionally different microcontrollers are introduced every year for common and popular microcontroller architectures These different functional variations also impact the ICE manufacturer since a new ICE Probe has to be designed for each new Bond Out chip In addition to the development costs involved it also delays the availability of the ICE for many months while the ICE system with the new Probe is debugged tested and released to production This prevents early users of the microcontroller from being able to develop their applications with the aid of an ICE Since many design engineers will not use a microcontroller unless there is an ICE available for it this delay can also slow the acceptance of a new microcontroller SUMMARY OF THE INVENTION Objects of the Invention 1 An object of one aspect of the invention is to provide circuitry in a modified COPS to allow real time in circuit emulation without the need of an address data bus or Bond Out chip by using the standard production micro controller 2 An object of one asp
51. mming the flash memory in circuit Those skilled in this field and having the benefit of the present disclosure will understand that although the term pin is used the present invention is not limited to use with microcontrollers having pins but may be used with any type of mechanism by which electrical connection is made to a packaged semiconductor device including but not limited to solder bumps solders balls and lands The system and method allow a user sitting at his Personal Computer to use the system as a fully functional real time in circuit emulator The user will be able to load and patch his program in the on chip flash of the COPS run the program or single step through it set breakpoints view and change the state of any user visible memory or register In addition optional functions can be added to provide addi tional debugging capabilities such as code trace and hard ware attributes BRIEF DESCRIPTION OF THE DRAWINGS FIG 1 is a pictorial view of the emulation system including the ICE the COP8 and an application printed circuit board FIG 2 is a block diagram of the emulation system including the ICE the COPS and the application 4 FIG 3 is a block diagram of a microcontroller in accor dance with the present invention FIG 4 is a block diagram of the core ICE Logic FIG 5 is a block diagram of the extended features ICE Logic FIG FIG 6 shows the OUTPUT pin field layout 7 shows a Type
52. ng ICE Monitor FIG 8 Type 2 Waveform COPS executing in Emulation mode running User program 10 Status signals Slot CLK Pin A Skipped Instruction current instruction is being skipped PL PU replacement when a program transfer occurs Internal data signals Internal data bus 15 OUTPUT Fin XXXX IT OUTPUT breaks the 10 slot 8 machine cycle into two fields see FIG 6 the Status Field and the Data Field COPS internal data is always output in the Data Field The remaining synchronization state and status information Type 3 waveform LOW voltage at negative CLK edge is encoded in the two slots of the Status Field LOW voltage at positive CLK edge FIG 6 OUTPUT Pin Field Layout PE COP8 Machine Cycle Slot 1 Slot 2 Slot 3 Slot 4 Slot 10 Nae a Status1 Status2 Data0 Data1 254 7 75 Data7 Status Field ap Hae ei eae Data Field gt gt 35 four waveform types that used to encode the Decoded by the ICE Logic as a 0 logic value information in the Status Field These waveform types are referred to as Type 1 Type 2 Type 3 and Type 4 waveforms 1 and Type 2 waveforms bi phase signals and are 40 only found in the Status Field of the OUTPUT signal A Slot Type 1 or Type 2 waveform is also called a Sync bit since
53. on system of claim 20 further comprising a first control circuit coupled to said external circuit wherein said first control circuit compares said rec reated program counter to supplied values providing breakpoints triggers and other actions US 6 829 727 B1 33 23 The in circuit emulation system of claim 16 wherein said microcontroller further comprising 1 a data memory 2 a plurality of registers 24 The in circuit emulation system of claim 23 further comprising said microcontroller outputting a fourth data on said reconfigured I O ports to enable said external circuit to recreate said data memory as said program executes 25 The in circuit emulation system of claim 23 further comprising said microcontroller outputting a fifth data on said reconfigured I O ports to enable said external circuit to recreate one or more of said registers as said program executes 26 The in circuit emulation system of claim 23 further comprising a second trace memory whereby said external circuit writes the recreated data memory and one or more of the recreated registers into said second trace memory 27 The in circuit emulation system of claims 23 further comprising a second control circuit coupled to said external circuit wherein said second control circuit compares one or more locations of said recreated data memory and one or more said recreated registers to supplied values providing breakpoints triggers and other actions 28 The
54. onfigured to output the CPU clock G2 is reconfigured to output synchronizing state status and internal data information G1 is reconfigured to output the program counter update status and the output state of the four G Port pins used in this interface GO is reconfigured to input control target pin data command and write data information 5 1 G3 CLK The G3 CLK pin outputs a clock of the same frequency as that used by the modified COP8 CPU This pin outputs 10 clocks per machine cycle All information passed on this interface except external Reset is done synchronously to this clock This pin is always clocking except when the modified COP8 is in HALT mode IDLE mode or the CKI clock has been lost The signal on this pin is referred to as CLK in the following descriptions 5 2 G2 OUTPUT The G2 OUTPUT pin outputs synchronizing state status and internal data information There is a significant amount of information that is transferred on this pin to the ICE Logic The following list summarizes by group the transferred information US 6 829 727 B1 11 12 Synchronizing signals Type 2 waveform LOW voltage at negative CLK edge Machine cycle synchronization First clock of machine HIGH voltage level at positive CLK edge cycle Decoded by the ICE Logic as a Sync bit with a 1 logic Instruction cycle synchronization Fetch signal first byte value of an instruction 9 State signals COPS executing in Break mode runni
55. ough a 330 Kohm resistor to simulate the COPS s weak pull up port structure To recreate an input port the output enables of both buffers are de asserted The Recreated Port data that is shifted out by the modified COPS on the POUT pin and captured in the POUT Interface Block 403 are clocked into the Recreated Configuration and Data registers lines 405 17 to 405 24 These registers are used to control the data and weak pull up output buffers These Recreated Port registers are asynchronously cleared whenever Reset is asserted line 405 28 The data values on the Recreated Port target pins are clocked into an Input register lines 405 25 to 405 27 and are fed to the INPUT Pin Interface Block 404 which inputs the data to the modified COPS 10 15 20 25 30 35 40 45 50 55 60 65 30 8 6 Control Processor Interface Block 407 Logic Equa tions and Explanation 8 6 1 Emulator Core Interface DATA 7 0 CP DATA 7 0 DATA 7 0 oe NOT N WR 407 3 DATA 7 0 DATA 7 0 407 4 DATA 7 RD 407 5 ADR 7 0 d CP DATA 7 0 407 6 ADR 7 0 clk ALE 4077 RD CPRD N WR N CPWR CTL CIK CP CP BREAK BREAK 407 9 407 10 8 6 2 Explanation of Logic Equations The Control Processor interface uses a conventional microprocessor interface with an
56. reate port functionality of said reconfigured I O ports h a second connector on said target system for coupling the recreated port functionality to said target system 1 said external circuit outputs a second data to said reconfigured I O ports causing said microcontroller to write said second data into said memory J said external circuit outputs a third data to said recon figured I O ports causing said microcontroller to execute instructions from said memory whereby said microcontroller contained in said target system will be emulated while maintaining all the functionality of its said I O ports and excluding dedicated ports to interface to said external circuit 17 The in circuit emulation system of claim 16 wherein said memory is integrated on chip with said microcontroller 18 The in circuit emulation system of claim 16 wherein said memory is a non volatile memory 19 The in circuit emulation system of claim 16 wherein said external circuit comprises an FPGA 20 The in circuit emulation system of claim 16 further comprising said microcontroller outputting a third data on said reconfigured I O ports to enable said external circuit to recreate the program counter of said microcontroller as said program executes 21 The in circuit emulation system of claim 20 further comprising a first trace memory whereby said external circuit writes the recreated program counter into said first trace memory 22 The in circuit emulati
57. register At the end of Slot 10 data bit 0 is in OUT DATAO data bit 1 in DATAL etc This data is held in the OUT DATA register during Slot 1 and Slot 2 and beginning in Slot 3 the capture cycle is repeated Inputting the Enabling Code into the modified COPS to put it into ICE Hooks mode is under the control of the Control Processor The Enabling Code is input to the modi fied COPS whenever the signal STOP lines 401 96 to 401 98 is de asserted With STOP CODE de asserted the G2 signal from the modified COPS which is normally input is enabled as an output lines 401 3 and 401 4 to allow outputting of the enabling clock Before starting the ICE Logic to input the Enabling Code the Control Processor first writes 1 to the ENABLE CLEAR lines 401 90 to 10 15 20 25 30 35 40 45 50 55 60 65 24 401 92 register to clear de assert STOP CODE and the ICE Hooks detection logic The Control Processor then writes a 0 to the ENABLE CLEAR register to allow the detection of the modified COPS in ICE Hooks mode The ICE Logic detects that the modified COPS is in ICE Hooks mode by the presence of a clock signal on the G3 signal This clock signal is detected by using it to clock a 3 bit counter CLK DETECT 2 0 lines 401 93 to 401 95 When this counter overflows it causes STOP CODE to be asserted which disables the inputting of the Enabling Code to the modified COPS When the
58. s gt is the starting address of the buffer in the modified COPS internal data memory where the read flash memory bytes are stored In executing this command the ICE Monitor stores the lt Buffer Address gt in the X register It then calls the low level ISP read routine that is part of the Monitor ROM The ISP routine reads the number of bytes requested starting at the flash memory address specified and stores them in the internal data memory buffer starting at the address contained in X When the ISP routine is done reading the flash memory it returns to this command routine This routine then exits through a common end of command routine and returns to the idle loop to await the next command 4 1 4 Program Memory Write Command The PROGRAM MEMORY WRITE command is used to write byte values to the modified COPS flash program memory from a buffer located in the modified COPS internal data memory This command uses the low level ISP flash memory write routine This low level ISP routine requires the following registers to be set up before it is called 10 15 20 25 30 35 40 45 50 55 60 65 8 ISPADHI High byte of the starting address ISPADLO Low byte of the starting address COUNT Number of bytes to write X Starting address in RAM of the write buffer The low level ISIP routine reads lt COUNT gt bytes from the buffer in the modified COPS internal data memory starting at address X and writes the
59. so sets the Break state signal in the modified COP8 The jump to the Monitor ROM and the setting of the Break state only occurs if the modified COP8 is in ICE Hooks mode see section 6 0 Details of Enabling the ICE Hooks mode During the execution of the BRK instruction the contents of the PCL lower 8 bits of the program counter are transferred to the data memory location referenced by the SP stack pointer The SP is then decremented followed by the contents of PCU upper 7 bits of the program counter being transferred to the new data memory location referenced by the SP The return address is now saved on the stack in data memory RAM Then the SP is decremented again to set up the stack reference for the next subroutine Next the program counter is loaded with a fixed address that is the entry point into the Monitor ROM The CPU then starts executing the program in the Monitor ROM at that address 3 2 RETF Return from Subroutine to Flash The return to flash instruction RETF opcode 0x63 pops the return address from the stack in data memory and then begins execution at the return address in the flash memory standard program memory address space The execution of this instruction also clears the Break state signal in the COPS During the execution of the RETF instruction the SP is first incremented The lower seven bits of the byte at the data memory location referenced by the SP are then transferred to the PCU after wh
60. ssor The Control Processor asserts this signal by setting the HW BRK CMD flag 404 25 to 404 28 This flag is synchronized to the modified COP8 using a two stage synchronizer SYNC1_HW__BRK_CMD lines 404 40 to 404 43 and SYNC2_HW_BRK_CMD lines 404 44 to 404 47 When SYNC2 HW CMD becomes asserted the INPUT multiplexor shifts out the Hardware Break Request Command during Slot 10 and Slot 1 8 5 Recreated Ports Block 405 Logic Equations and Expla nation 8 5 1 Target Interface 405 1 G0 SYNC TG DATAO 405 2 G0 oe SYNC TG CONFIGO 405 3 60 WPoe VCC 405 4 G0 WEoe NOT SYNC TG CONFIGO SYNC TG DATAO 405 5 1 SYNC TG 405 6 Gl oe SYNC CONFIGI1 405 7 G1 WP 405 9 G1 WP oe NOT SYNC TG CONFIG1 AND SYNC TG DATA1 US 6 829 727 B1 29 continued 405 9 405 10 405 11 405 12 G2 SYNC TG DATA2 TAR_G2 0e SYNC TG CONFIG2 TAR G2 WP VCC G2 WP oe NOT SYNC TG CONFIG2 AND SYNC TG DATA2 G3 TG DATA3 TAR G3 oe SYNC TG CONFIG3 G3 WP VCC G3 NOT SYNC TG CONFIG3 AND DATA3 405 13 405 14 405 15 405 16 8 5 2 Recreated Port Output Registers 405 17 SYNC TG CONFIG 3 0 d TG CONFIG 3 0 405 18 SYNC TG CONFIG 3 01 CLK 405 19 SYNC CONFIG 3 0 RSLOT10 405 20
61. stem programming ISP flash memory read write routines and a monitor ICE Monitor program that interfaces to the ICE Logic This ROM is called the Monitor ROM Second two new instructions were added to the COPS instruction set The first instruction is a software breakpoint instruction assembly code mnemonic BRK This instruc tion pushes the current program counter PC onto the stack and jumps to the ICE Monitor The second instruction is a return to flash instruction assembly code mnemonic RETF This instruction pops the PC from the stack and starts executing in the flash memory standard program memory address space Third four digital I O pins were re configured to interface to the ICE One of these four pins outputs a clock This clock is of the same frequency as that used by the COPS CPU information passed on the other three pins is done synchro nous to this clock Two of the remaining three pins are used to output cycle and instruction synchronization flags state status internal data and port recreation information The last of the four pins is an input pin that is used by the ICE to input control recreated port command and write data informa tion 3 0 Details of the New Instructions 3 1 BRK Software Breakpoint The software breakpoint instruction BRK opcode 0x62 pushes the return address onto the stack in data memory and then jumps to a fixed address in the Monitor ROM The execution of this instruction al
62. t this new value in the program counter 4 2 Ice Monitor and Ice Logic Synchronization The COPS in a user s application can run at any arbitrary frequency up to the maximum permitted by the device specification The ICE Logic runs at a fixed speed If the modified COPS is running at a relatively low frequency the 10 15 20 25 30 35 40 45 50 55 60 65 10 ICE Logic can input data to the ICE Monitor faster than it can process it If the modified COP8 is running at its maximum frequency the ICE Monitor can output data faster than the ICE logic can process it Because of this wide range of operating conditions the ICE Monitor and ICE Logic must synchronize the data transfers between them Whenever the ICE Monitor is waiting for data from the ICE Logic it is executing a small loop polling a received byte status flag In this loop no instructions are skipped When a byte sent from the ICE Logic has been loaded into the ICE Monitor s receive register the ICE Monitor detects the received byte status flag is asserted and skips an instruc tion which causes the modified COPS to output a Skip Flag on the OUTPUT pin see Section 5 2 The ICE Logic detects this Skip Flag and knows that the byte was received Once the ICE Monitor has read the byte from its receiver register it again skips an instruction When the ICE Logic detects a second Skip Flag after sending a byte it knows that the ICE Monitor has consumed the b
63. th said external circuit f means for coupling the reconfigured I O ports to said external circuit g means for said external circuit to recreate port func tionality of said reconfigured I O ports h means for coupling the recreated port functionality to said target system 1 means for said external circuit to load said program into said memory j means for said microcontroller to execute said program under the control of said external circuit whereby said microcontroller excludes dedicated ports to interface to said external circuit and said microcontroller will be emulated in said target system while maintaining all the functionality of its said I O ports 2 The in circuit emulation system of claim 1 wherein said memory is integrated on chip with said microcontroller 3 The in circuit emulation system of claim 2 wherein said memory is a non volatile memory 4 The in circuit emulation system of claim 1 wherein said external circuit comprises an FPGA 5 The in circuit emulation system of claim 1 further comprising means for said external circuit to recreate the program counter of said microcontroller as said program executes 6 The in circuit emulation system of claim 5 further comprising a first trace memory coupled to said external circuit to capture the recreated program counter 7 The in circuit emulation system of claim 5 further comprising a first control circuit coupled to said external circuit providing
64. their customers microcontroller manufacturers generally develop a special version of the single chip microcontroller called a Bond Out chip A Bond Out chip disables the internal code memory of the single chip microcontroller and brings out the internal address and data bus on extra pins Using extra pins allows the address and data bus to be available to the ICE while at the same time preserving the chip s I O that the user s application is using These Bond Out chips are made avail able to ICE manufacturers so they can develop an ICE for the chip While a Bond Out chip allows an ICE to be built for a single chip microcontroller it nonetheless has several dis advantages First because of the extra pins needed it is packaged in a larger package than the standard production microcontroller This means that it cannot be used in the site that the production part will occupy on the target system Rather the Bond Out chip is placed on an ICE Probe or resides in the ICE base unit and the pin signals are connected to the target system through a cable or an adapter Not operating in the actual application board site causes severe degradation of analog signals and often limits the environ mental parameters e g temperature in which the system can be emulated and debugged Asecond disadvantage of the Bond Out chip is its higher cost which in some cases can be as high as ten times the cost of the production microcontroller Several factors con
65. tribute to the cost of a Bond Out chip One is the relatively low 10 15 20 30 40 45 50 55 60 65 2 volume of the part While a typical microcontroller in production can run in the millions of units per year Bond Out chip consumption typically numbers in the tens to hundreds of units per year Also cost is added to the Bond Out chip by its use of larger packaging and special test flow due to the extra pins and associated functionality This results in a more expensive emulator and a higher cost of repair the most common failure in an ICE system is the Bond Out chip A third disadvantage is that over the lifetime of the product it is not unusual for the Bond Out chip s operating parameters and functionality to diverge from the production part The production part is always the focus of improve ments through bug fixes yield improvements and die shrinks The Bond Out due to its limited use often doesn t share in these improvements This most commonly happens in cases where the Bond Out is physically a separate die although it can also happen where the Bond Out is a package option due to limitations on test development resources When this divergence occurs the ICE becomes less useful as a real time emulator A fourth disadvantage is that a new Bond Out chip is required when the semiconductor manufacturer decides to add new functionality to a microcontroller by designing and producing new versions of the
66. unt value again This continues until the Count value is equal to zero When the Count value is zero this routine exits through a common end of command routine and returns to the idle loop to await the next command 4 1 3 Program Memory Read Command The PROGRAM MEMORY READ command is used to read byte values from the modified COPS flash program memory and write them to a buffer located in the modified COPS internal data memory This command uses the low level ISP flash memory read routine This low level ISP routine requires the following registers to be set up before it is called ISPADHI High byte of the starting address ISPADLO Low byte of the starting address COUNTHI High byte of the number of bytes to read COUNTLO Low byte of the number of bytes to read X Starting address in RAM of the read buffer The low level ISP routine reads lt COUNTHI gt lt COUNTLO gt bytes of the flash memory starting at address lt ISPADHI gt lt ISPADLO gt and stores the bytes in the modified COPS internal data memory starting at address lt X gt Before the PROGRAM MEMORY READ command is sent to the ICE Monitor the ICE Logic loads the appropriate values in the ISPADHI ISPADLO COUNTHI and COUNTLO registers using the DATA MEMORY WRITE command This command is two bytes long and is of the form lt 03 gt lt Buffer Address gt The first byte lt 03 gt is the command value that is decoded by the command decoder The lt Buffer Addres
67. ust simple digital I O 10 An object of one aspect of the invention is to allow the use of on chip flash memory and allow in system pro gramming during emulation 11 An object of one aspect of the invention is to provide for communication between the emulator and an on chip monitor program to allow full visibility to the state of the microcontroller Briefly the present invention provides a system and method of providing real time in circuit emulation of a COPS microcontroller using the standard production device directly soldered or otherwise connected on the application s printed circuit board The system of the present invention as shown in FIG 2 contemplates three major blocks The first block is a flash memory based microcontroller 201 having a slightly modified COPS architecture The second block is the emulator logic the ICE Logic 202 and the third block is the Control Processor 203 that interfaces between the ICE Logic and the user interface running on a standard Personal Computer One embodiment of a method of the present invention uses four digital pins of a flash memory based COPS micro controller that are reconfigured in emulation mode to output clock status and data to the ICE Logic and an input pin to input commands and data from the ICE Logic The input pin s data communicates with a small ROM based monitor in the COPS and provides a means of inputting and output ting the internal state of the machine as well as progra
68. yte and it is safe to send another byte This Skip Flag synchronization prevents the ICE Logic from overrunning the ICE Monitor s receive register Whenever the ICE Monitor is prepared to send data to the ICE Logic it waits in a loop until it gets a signal from the ICE Logic that it is ready to receive the byte The ICE Logic signals its readiness by sending a byte to the ICE Monitor The value of the byte is superfluous It is the action of sending the byte that gates the ICE Monitor Upon receiving the byte the ICE Monitor throws it away skips an instruction outputs the pending data to the ICE Logic and skips another instruction If the ICE Monitor has more data to send it again loops waiting for the ICE Logic to send the gating byte When the ICE Logic detects the first Skip Flag in this sequence it knows that the ICE Monitor has seen its signal and is preparing to output its data Upon detecting the second Skip Flag the ICE Logic knows that the ICE Monitor has output its pending data and is ready to send another byte The ICE Logic can then read the transferred byte from its receiver buffer This gating byte synchroniza tion prevents the ICE Monitor from overrunning the ICE Logic s receive buffer 5 0 Details of the Reconfigured Digital IO Four of the modified COPS digital I O pins are reconfig ured to interface to the ICE Logic The four pins are the lower four bits of the G Port commonly referred to as GO G1 G2 and G3 G3 is rec

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