Lesson 11 Interrupt
Contents
1. RO OR mask to set bit 20 other bits unchanged RO AND mask to clear bit 21 other bits unchanged R2 Address of PINSEL register set bit 20 clear bit 21 write back to PINSEL4 register Setup Mode to be edge in EXTMODE register R2 Address of EXTMODE register force bit 1 for edge write back to EXTMODE register Setup Polarity to be rising edge in EXTPOLAR register R2 Address of EXTPOLAR register force bit 1 for rising edge write back to EXTPOLAR register Step 2 Enable interrupt for peripheral EINT in ISERO reigster RO OR mask to set bit 18 other bits unchanged R2 Address of ISERO register force bit 18 1 to enable interrupt for EINT write back to ISER register Step 3 Setup priority for peripheral EINT default ok Step 4 Enable global interrupt bit default ok return Step 5 ISR for EINTO void __asm EINT _IRQHandler void Save registers r4 r12 if used in ISR Processing increment a count in count RO address of count in data RAM increment count Clear EINT interrupt flag in EXTINT register RO address of EXTINT register clear EINT flag by writing 1 to bit Pull registers r4 r12 if used in ISR Return from ISR 102. Set the Priority Level for EINTO optional By default all interrupts are set at level 0 which is the highest priority This default priority is good to use in programs so you don t have to do anything However if you want to set the priority of EINTO to another level you will need to Step 4 Enable the Global Interrupt Bit optional By default the processor is configured to recognize any interrupts that are enabled e g in step 2 It means that you don t have to do anything to enable this bit This is indicated by bit 0 of the PRIMASK register If this bit 0 all interrupts can be activated if enabled in step 2 If this bit is 1 all exceptions except NMI are disabled Recall that you can use the following instructions to enable or disable the global interrupt bit Step 5 Develop an Interrupt Service Routine ISR for EINTO In order for the processor to jump to right code for EINTO interrupt the ISR must be named as 7 The first task the ISR should perform is to save the contents of all the registers r4 r12 that will be used in this subroutine For example if your subroutine uses r4 and r5 as temporary storage you should save these registers by The next step is to process the interrupt request This is an application dependent step For example we can write an application to keep a count of the number the INTO pushbutton is pressed The next step is very important clearing the interrupt flag If your ISR retur
3. in the figure below For example if we want to create an ISR for EITNO then the name for the ISR should be EJNTO_IRQHandler The compiler will place the memory address 31 32 35 37 39 40 41 42 43 45 46 47 49 0x78 0x7C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C OxA0 OxA4 OxA8 OxAC OxBO OxB4 OxB8 OxBC 0xcC0 0xC4 0xC8 SSPO SSP 1 PLLO Main PLL RTC External Interrupt External Interrupt External Interrupt External Interrupt ADC BOD USB CAN GPDMA PS Ethernet Repetitive Interrupt Timer Motor Control PWM Quadrature Encoder PLL1 USB PLL Tx FIFO half empty of SSPO Rx FIFO half full of SSPO Rx Timeout of SSPO Rx Overrun of SSPO Tx FIFO half empty Rx FIFO half full Rx Timeout Rx Overrun PLLO Lock PLOCKO Counter Increment RTCCIF Alarm RTCALF Extemal Interrupt 0 EINTO Extemal Interrupt 1 EINT1 Extemal Interrupt 2 EINT2 Extemal Interrupt 3 EINTS3 Note EINT3 channel is shared with GPIO interrupts A D Converter end of conversion Brown Out detect USB_INT_REQ LP USB_INT_REQ_HP USB_INT_REQ DMA CAN Common CAN 0 Tx CAN 0 Rx CAN 1 Tx CAN 1 Rx IntStatus of DMA channel 0 IntStatus of DMA channel 1 irq dmareq1 dmareq2 WakeupIint Softint TxDoneint TxFinishedint TxErrorint TxUnderrunint RxDoneint RxFinishedint RxErrorint RxOverrunint RITINT IPER 2 0 IPW 2 0 ICAP 2 0 FES INX_Int TIM_Int VELC_Int DIR_I
4. BTO 10 11 12 13 23 24 25 26 27 28 29 0x58 0x5C 0x68 0x70 0x74 UART1 UART 2 UART 3 PWM1 CO C1 202 SPI Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI Modem Control Change End of Auto Baud ABEO Auto Baud Time Out ABTO Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI End of Auto Baud ABEO Auto Baud Time Out ABTO Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI End of Auto Baud ABEO Auto Baud Time Out ABTO Match 0 6 of PWM1 Capture 0 1 of PWM1 SI state change SI state change SI state change SPI Interrupt Flag SPIF Mode Fault MODF From Table 50 in the LPC17xx User manual NXP Semiconductors 2010 4 14 15 16 17 18 19 21 23 24 25 27 28 88 Note that the ISR can reside anywhere in the code memory ROM so how do we manage the memory space so that the processor can point to the right address for the correct ISR From a programming perspective we can write the ISR as regular subroutine but with specific names These predefined ISR names are provided in the startupLPC17xx s file provided with the Keil uvision software A screenshot of the startupLPC17xx s showing some of the predefined ISR names is shown
5. Lesson 11 Interrupt 1 Overview In this lesson we introduce the general concepts about interrupts supported by the Cortex M3 processor We will then discuss a specific interrupt example that utilizes an external triggered signal 2 General Concepts of an Interrupt One of the methods to read an input from an I O port is using the polling technique as you did in lab 1 Polling is a technique to monitor an I O port and to trigger an appropriate action when a change is detected The general idea is that the processor periodically reads the I O port and determines if there is a change If there is a change the processor will execute the subset of code to deal specifically with this change Otherwise the processor will continue with normal operations Another more efficient way to read and input for an I O port is using an interrupt Interrupt based program allows the processor to continue processing the main task without periodically checking for a change at an I O pin Interrupt is an exception caused by an explicit request signal from a peripheral or hardware device An interrupt cause the automatic transfer of software execution outside of the normal programmed sequence e g to provide service to the peripheral When a peripheral or a hardware device needs service form the processor typically e It asserts an interrupt request to the processor e The processor completes the current instruction then it suspends the current task and jumps
6. continuous ISR execution endless loop After the ISR provides the necessary service it will return to the main program by executing the BX LR instruction In the vector interrupt system each source or each peripheral or hardware device of interrupt has an associated 32 bit vector that points to the address of the first instruction in the ISR that handles the exception These vectors are stored at the beginning of the ROM Table 50 shown below in the LPC 7xx User Manual contains the interrupt vector location for different interrupt source peripheral Note that the Vector Offset value is the offset number from the beginning of the memory space ROM starts at address 0xO0000000 When an interrupt occurs the processor determines which exception number is activated then calculates the starting address of the ISR The address is then used to update the PC For example if an External Interrupt 0 EINTO requests an interrupt the processor calculates the PC as Interrupt Exception Vector Number Offset 16 0x40 Flag s Watchdog Interrupt WDINT 17 18 19 20 0x44 0x48 0x4C 0x50 Match 0 1 MRO MR1 Capture 0 1 CRO CR1 Match 0 2 MRO MR1 MR2 Capture 0 1 CRO CR1 Match 0 3 Capture 0 1 Match 0 3 Capture 0 1 0x54 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI End of Auto Baud ABEO Auto Baud Time Out A
7. dler Se Se Se Se Ye Ye Ye Se Ye Se Ye Se Ye Se Ye Ys Top of Stack Reset Handler NMI Handler Hard Fault Handler MPU Fault Handler Bus Fault Handler Usage Fault Handler Reserved Reserved Reserved Reserved SVCall Handler Debug Monitor Handler Reserved PendSV Handler SysTick Handler 16 Watchdog Timer 17 Timer0 8 Timeri 19 Timer2 20 Timer3 21 UARTO 22 UART1 23 UART2 24 UART3 25 PWM1 26 I2C0 27 I2C1 28 I2C2 29 SPI 30 SSPO 31 SSP1 32 PLLO Lock Main PLL 33 Real Time Clock 34 External Interrupt 35 External Interrupt 36 External Interrupt 37 External Interrupt 38 A D Converter 39 Brown Out Detect WN ke oO Example of an Interrupt EINTO External Interrupt Let s look at an example of an interrupt The peripheral that we will use in this example is the External Interrupt 0 EINTO Step 1 Setup the peripheral EINTO Since this peripheral shares the same pin with other functions e g GPIO P2 10 we will first need to set it up to function as an External Interrupt 0 Pin This is done by 6 Next we will need to set the pin to detect rising edge changes for this example at the pin These edges will cause interrupts This can be achieved by Step 2 Enable EINTO Interrupt By default all external interrupts are disabled So we need to enable specific interrupt so that the processor can service the peripheral when requested We can enable EINTO interrupt by Step 3
8. fault Programmable Memory management fault Memory Protection Unit MPU violation or access to illegal locations 5 Bus fault Programmable Bus error occurs when Advanced High Performance Bus AHB interface receives an error response from a bus slave also called prefetch abort if it is an instruction fetch or data abort if it is a data access 6 Usage fault Programmable Exceptions resulting from program error or trying to access coprocessor the Cortex M3 does not support a coprocessor 7 10 Reserved NA 11 SVC Programmable Supervisor Call 12 Debug monitor Programmable Debug monitor breakpoints watchpoints or external debug requests 13 Reserved NA 14 PendSV Programmable Pendable Service Call 15 SYSTICK Programmable System Tick Timer From The Definitive Guide to ARM Cortex M3 and Cortex M4 Processors Joseph Yiu Elsevier 3 ed 2014 3 The priority level for the peripheral is configured properly in the Interrupt Priority Registers 7PRn registers In order for this interrupt to occur this priority level must be higher than or the same as the priority level set in BASEPRI register Note that the lowest number is the highest priority By default the priority level is 0 in BASEPRI register Also by default the priority level is zero for all peripherals It means that default values for these registers are ok to use in your program without an modifications 4 The global interrupt bit is enabled bit 0 in PRIMASK reg
9. ister 0 By default bit 0 of PRIMASK is 0 enabled In general you won t need to modify this register but if necessary you can use the following instructions to enable or disable the global interrupt bit You can also use the MRS instructions to enable disable disable the global interrupt bit For example or 5 The peripheral asserts the interrupt request which sets the interrupt flag Once an interrupt request has been asserted by the peripheral and recognized by the processor the processor needs to service the peripheral which causes the following conditions 1 Suspension of the main program e Current instruction is completed e Suspend execution and push 8 registers RO R3 R12 LR PC PCR on the stack e LR set to OXFFFFFFF9 which indicates interrupt return e IPSR set to interrupt number PC set to ISR address 2 The ISR is executed e Process the interrupt request by the peripheral e Clears the flag that requested the interrupt e Exit ISR by executing BX LR 3 Resume normal operation e Pulls 8 registers RO R3 R12 LR PC PCR from the stack e Return to the next instruction in the previously suspended task Interrupt Service Routine ISR is a subroutine that is executed when an interrupt request occurs Generally each potential source of interrupt would have a specific ISR In most cases except for the SysTick interrupt the ISR must clear the flag that caused the interrupt Failing to clear the flag will trigger
10. ns without clearing the interrupt flag the interrupt will endlessly occur infinite loop For EINTO we can clear the interrupt flag by Before returning to the main program your subroutine should restore all the temporary registers r4 r12 that are used in the ISR For example if registers r4 and r5 are pushed on the stack at the beginning of the ISR these registers should be popped as The last instruction of the should be Exercise Write code to setup EINTO interrupt Keep a count of the number of interrupt occurrences Notes about debugging with interrupts e Cannot use single step e Use breakpoints and run option instead 4 References 1 Joseph Yiu The Definitive Guide to ARM Cortex M3 and Cortex M4 Processors Elsevier 3 ed 2014 2 Jonathan Valvano Introduction to ARM Cortex M Microcontroller A ed 2013 3 ARMv7 M Architecture Reference Manual ARM Limited 2010 4 LPC17xx User manual NXP Semiconductors 2010 5 Cortex M3 Technical Reference Manual ARM Limited 2010 include LPC17xx h Device header include LED h void __asm EINT _IRQHandler void void _ asm EINT Init void Reserve a 32 bit word at address 0x10000000 Main Initialize int main void count LED _Init Initialize LEDs EINTO_ Init Initialize EINT interrupt a endless loop do nothing wait for interrupt void __asm EINTO_Init void Setup pin to be EINTO in PINSEL4 register
11. nt ERR_Int ENCLK_Int POSO_Int POS1_Int POS2_Int REV_Int POSOREV_Int POS1REV_Int POS2REV_int PLL1 Lock PLOCK1 USB Activity Interrupt USB_NEED_CLK CAN Activity Interrupt CAN1WAKE CAN2WAKE From Table 50 in the LPC17xx User manual NXP Semiconductors 2010 of this ISR in the appropriate offset in the vector table 0x88 in this case 2 startup UPctrexs 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 El 92 93 a 95 96 97 98 99 100 3 7 Vector Table Mapped to Address 0 at Reset __ Vectors AREA RESET DATA READONLY EXPORT Vectors DCD __initial_sp DCD Reset_Handler DCD NMI Handler DCD HardFault_ Handler DCD MemManage Handler DCD BusFault_Handler DCD UsageFault_Handler DCD o DCD 8 DCD i DCD o DCD SVC_Handler DCD DebugMon_Handler DCD 0 DCD PendSV_ Handler DCD SysTick_ Handler External Interrupts DCD WDT_IRQHandler DCD TIMERO IRQHandler DCD TIMER1 IRQHandler DCD TIMER2 IRQHandler DCD TIMER3_IRQHandler DCD UARTO_IRQHandler DCD UART1i_IRQHandler DCD UART2_IRQHandler DCD UART3_IRQHandler DCD PWM1_IRQHandler DCD I2C0_IRQHandler DCD I2C1_IRQHandler DCD I2C2_IRQHandler DCD SPI_IRQHandler DCD SSPO_IRQHandler DCD SSP1_IRQHandler DCD PLLO_IRQHandler DCD RTC IRQHandler DCD DCD EINT1_IRQHandler DCD EINT2_IRQHandler DCD EINT3_IRQHandler DCD ADC _IRQHandler DCD BOD IRQHan
12. to an Interrupt Service Routine ISR to service the peripheral e Then the processor resumes the previously suspended task The Cortex M3 processor supports vector interrupts It means that when an interrupt occurs the program jumps to a specific memory location indicated by the Nested Vectored Interrupt Controller NVIC This controller provides an efficient way to handle different exceptions Exceptions numbers 1 15 are system exceptions as shown in the table below Exceptions of number 16 or above are peripheral driven We will mainly discuss these types of exceptions in class Parts of the NVIC are discussed in this lesson In order for the processor to recognize an interrupt request form a peripheral the peripheral and processor must be initialized and configured properly to enable the interrupt triggering mechanism In general the following conditions must be true for an interrupt to occur 1 The peripheral is configured properly This step varies based on the peripheral We will discuss a specific example later in this lesson EJNTO 2 The interrupt enable bit for the peripheral in the Interrupt Set Enable Registers ISERn registers is set By default all interrupt enable bits are cleared disabled Number Exception Type Priority Description 1 Reset 3 Highest Reset 2 NMI 2 Nonmaskable interrupt external NMI input 3 Hard fault 1 All fault conditions if the corresponding fault handler is not enabled MemManage
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