Home

R PowerPC 603/604 Reference Design Technical

1. HOIOSNNOO H3 wv3ds DV L 5 m 5 HOIO3NNOO _ 5 ga Re oa Y i J H m m ns 000000000000000000 00000000000 0000000000 ERS gas n n n n n 0900000 00000000 n 0006 ada 0 1 E E 5 gt a gt 8 Tm sng us nnn n e i RE a H3110H1NOO ps nononono 0000 3SnOW QHVOHA3M 2708 5 ya E 58 0 b x 5 RIMIS EM 0000000000 UD ap YOLOSNNOO INVHS s 9 ee 8 5 a n 0000 EN Bm 7 Gees 5 3 0000 555 a So B 5 ont no g HOLO3NNOO SNE 128 ug 5 YOLOANNOD HOLVMOSIMH 588 s 8 z ne E n 8 ifs m NN1S HOSS390Hd X09 LL E Bo 8L B E 2 130A 9 2 2 2 8 5 2 88 IN 854253 EPC S3 mpina ES of 0 mo ee LLL _ Laod 3snon 0 EC H 1808 QHVOSASM 046244 79929 2 320432 110A 52 9784868 TALNI JOY1N09 390188 136 HOLO3NNOO H3MOd OIS HOLO3NNO2 H3MOd 59928 12 Wal S13N09 NO H3MOd dn 390188 43 HOLIMS H3MOd SXAY
2. Data Address X Buffers L2 SRAM ISA Expansion Module gt PP Slots 5 Speaker Se AS TagRAM ISA Bus HH i Contol C C B H ege Address IBM27 82664 SIO Controller ISA Bus 60X Bus PCI Bus IBM27 82663 PCI Expansion Buffer Slots 3 PD Control DRAM Module DRAM Module AddressData 5v to 3 3 DRAM Modul v to 3 3v odule Regulator Flash ROM DRAM Module 29F040 Figure 1 603 604 Reference Design Block Diagram 1 3 4 System Memory The reference design memory subsystem can support up to 128M of 70ns DRAM memory on four 72 pin modules via sockets Each SIMM socket can support an 8M or 32M 72 pin SIMM The DRAM subsystem is 72 bits wide 64 data bits and eight parity bits One parity bit is generated for each byte of data written The 660 Bridge can also be configured to per 20 MPRH01TSU 02 PowerPc Introduction form ECC memory data checking and correction using standard parity DRAM modules Or it can be configured to disable DRAM parity checking for systems using non parity DRAM The 660 Bridge also provides DRAM refresh and supports EDO hyper page mode DRAM Memory access performance from the CPU bus at 66MHz with 70ns DRAM is typically Pipelined burst read 4 4 4
3. PCI_GNT OUT PCI_GNT_IN_ MASK PCI_GNT 176 MPRH01TSU 02 PowerPc Errata 13 4 660 Bridge Revision 1 1 Errata 8 9 95 Release This section contains a subset of the 8 9 95 release of the 660 bridge revision 1 1 errata summary The errata summary contains generic example PALs which are not identical to those used on the reference design The function of the two sets of PALs is identical only the parsing of the logic among the devices is different Section 13 4 1 describes the invididual 660 bridge errata and their associated worka rounds Section 13 4 2 contains the logic design files of the PALs chosen to implement the worka round logic Section 13 4 3 describes the installation of the PLDs in a generic system 13 4 1 Individual 660 Bridge Errata The following sections contain a detailed breakdown of individual 660 Bridge Errata All equations are shown in PALASM format INVERT is OR is and AND is The term performance refers to the number of clock cycles required to complete an operation Advisory 1 NCR 53C810 SCSI Controller Date 6 21 95 Functional On certain PCI configuration writes to the SCSI controller the 664 will wait several 3 PCI clocks before asserting IRDY Under these conditions the SCSI controller appears to latch in t
4. END OF FILE MPRHO1TSU 02 185 ABB DEL ABB CPU AO DBB for Errata 6 for Errata 11 Delay granting PCI to the CPU when a CPU to PCI cycle is pipelined over the data tenure of the previous cycle 5 5 7 Errata Errata Errata 6 Errata Errata Errata 13 4 2 3 Broom PAL Design File TITLE BROOM1 PATTERN none REVISION 1 0 COMPANY IBM DATE 08 02 95 CHIP 1 PALCF16V8 Predefined PIN 1 CPU_CLK PIN 10 GND PIN 11 REG PIN 20 Inputs PIN 2 _ 3 PCI GNT IN_ PIN 4 ABB PIN 5 _ 6 SRAM _ PIN 7 8 9 Outputs PIN 13 COMB PIN 14 COMB Internal Registers PIN 12 DEL ABB _ REG PIN 15 MASK BG3 REG PIN 16 MASK 7A REG PIN 17 MASK 7B REG PIN 18 TA CNTO REG PIN 19 TA CNT1 REG PowerPc CLOCK GROUND OUTPUT ENABLE FOR REGISTERED OUTPUTS INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT COMBINATIONAL COMBINATIONAL REG REG REGISTERED REGISTERED 186 MPRH01TSU 02 PowerPc Errata Output enables for Comb logic Reg OE s controllered by pin 11 Equations for internal registers DEL _ ABB_ k k k k k k k K K K K K K K KOK K e K KOK K k He KO K K KO K K KOK K K KOK K K K KO KOK K RO KOK K K K Below is fix fo
5. m 0 e 8080 0801 Vendor Identification 8080 0802 Device Identification 8080 0803 Device Identification 8080 0804 Command ee ee ae MPRH01TSU 02 111 Setup PowerPc Table 33 Combined Register Listing Continued ree Mode Addr Mode Addr 6 4 3080 0805 Command 00 8080 0806 Rw SIO 80800807 RW 80800808 Identification 1 IRW SIO 80800840 IPCIContol 80800841 PCI Arbiter Control RW 00 SIO 80800842 PCIArbiterPrortyContol R CPC Arbiter Priority Control Extension R W 00 50 MEMCS Contol R W 00 50 MEMCS Bottom of Hole RW 10 _________ 5 Top of Hole 7 nw SIO MEMCS TopofMemory RW 00 ISAAddressDecoderControl nw F1 50 SA Address Decoder ROM Block RW 00 _________ Address Bottom of Hole R W 10 50 lSAAddressTopofHole Rw OF Controller Recovery Timer 56 50 lSAClckDivisor R W 10 8080084E UitiltyBusChipSelectA R W 07 SIO 8080084F UiiyBusChipSelectB IP 80800854 7 MEMCSi Attribu
6. he e he e ke Freeze Clock Logic Refer to the Motorola 088107970 PLL Clock Driver Specification for information Freeze Data protocol Freeze Clock Logic contains a 12 Bit serial shift register 5 Decode the low order CLKFF 7 0 on addresses 0860 0861 Decode the high order CLKFF 12 8 on addresses 0862 0863 CLK FF_STRB 7 5 6 amp 5 amp 4 amp 3 amp 2 amp GPCSO CLKFF_WR CLKFF_STRB amp XIOW CLKFF_SELL CLKFF_STRB amp A 1 CLKFF_SELH CLKFF_STRB amp 1 CLKFF 12 0 prn VCC CLKFF 12 0 clrn RESET CLKFF 12 0 ena START SHIFTFF q CLKFF WR CLKFF 12 0 clk ISA CLE if START SHIFTFF q then Shift with wraparound CLKFF 11 0 d CLKFF 12 1 q CLKFF 12 d CLKFF 0 q else if CLKFF SELL then 5 Write to CLKFF 7 0 CLKFF 7 0 d XD 7 0 CLKFF 12 8 d 8 q else if CLKFF SELH then CLKFF 7 0 d CLKFF 7 0 q Write to CLKFF 12 8 CLKFF 12 8 d XD 4 0 else CLKFF 12 0 d CLKFF 12 0 q Do nothing
7. 29 oO no 5 8080 0800 8080 0801 8080 0802 8080 0803 8080 0804 8080 0805 8080 0806 8080 0807 8080 0808 8080 0840 8080 0841 8080 0842 8080 0843 8080 0844 8080 0845 8080 0846 8080 0847 8080 0848 8080 0849 8080 084 8080 084 8080 084 8080 0840 8080 084 8080 084F 8080 0854 8080 0855 8080 085 8080 085 8080 086 8080 0861 8080 086 8080 086 lt endor Identification endor Identification evice Identification evice Identification Command Command Device Status Device Status Revision Identification PCI Control PCI Arbiter Control Arbiter Priority Control Arbiter Priority Control Extension MEMCS Control MEMCS Bottom of Hole MEMCS Top of Hole MEMCS Top of Memory SA Address Decoder Control SA Address Decoder ROM Block SA Address Bottom of Hole SA Address Top of Hole SA Controller Recovery Timer SA Clock Divisor Utility Bus Chip Select A Utility Bus Chip Select B MEMCS Attribute Register 1 MEMCS Attribute Register 2 MEMCS Attribute Register 3 Scatter Gather Relocation Base PIRQ Route Control 0 PIRQ Route Control 1 PIRQ Route Control 2 PIRQ Route Control 3 unused 8080 0880 BIOS Timer Base Address 8080 0881 BIOS Timer Base Address If the entry in this column is blank then the boot firmware does not write to this register D O N e ALO oO oj e N oj oj
8. PowerPC 603 604 Reference Design Technical Specification Release 2 1 This document provides a detailed technical description of the PowerPC 603 604 Reference Design It is in tended as a first source of information for both hardware and software de signers Where appropriate other documents are referenced Document Number MPRHO1TSU 02 August 9 1995 m LE e ic PowerPc International Business Machines Corporation 1995 Printed in the United States of America 8 95 All Rights reserved IBM Microelectronics PowerPC PowerPC 601 PowerPC 603 PowerPC 603e PowerPC 604 RISCWatch and AIX are trademarks of the IBM corporation IBM and the IBM logo are registered trademarks of the IBM corporation Other company names and product identifiers are trademarks of the respective companies This document contains information which is subject to change by IBM without notice IBM assumes no re sponsibility or liability for any use of the information contained herein Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties The products described in this document are not intended for use in implantation or other direct life support ap plications where malfunction may result in physical harm or injury to persons NO WARRANTIES OF ANY KIND INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNES
9. no N EE 8080 0801 8080 0802 8080 0803 8080 0804 8080 0805 8080 0806 8080 0807 8080 0808 8080 0840 8080 0841 8080 0842 8080 0843 8080 0844 8080 0845 8080 0846 8080 0847 8080 0848 8080 0849 8080 084A 8080 0848 8080 084C 8080 084D 8080 084E 8080 084F 8080 0854 8080 0855 N D D D D D D D D D D Dy Dy gt D d D D D d d D D 106 MPRH01TSU 02 PowerPc Setup 9 4 PCI Configuration Scan The reference design enables the software to implement a scan to determine the comple ment of PCI devices present This is because the system returns all ones rather than an error when no PCI device responds to initialization cycles The software may read each possible PCI device ID to determine devices present Table 32 Configuration Address Assignments Device _______ IDSEL Line 60X Address PCI Address ISA bus bridge SIO A D 11 8080 08XXh 080 08XX PCI Slot 1 A D 12 8080 10XXh 080 10XX PCI Slot 2 A D 13 8080 20XXh 080 20XX PCI Slot 3 A D 14 8080 40XXh 080 40XX Note This address is independent of contiguous I O mode Software must use only the addresses specified Using any addresses that causes more than one IDSEL to be asserted high can cause bus contention because multiple PCI age
10. Electromechanical PowerPc 11 4 Enclosure The Reference Design Board has a standard BabyAT form factor It will fit within enclosures manufactured by a variety of companies The keyboard mouse connector type should be considered when selecting a enclosure Additional cooling options may be required The following venders supply enclosures Olson Metal Products Company Inc Attn Michelle Seay 1903 N Austin Street Seguin Texas 78155 1 800 951 9517 or 210 379 7000 AT Desktop model number CC300249 Medium Tower model number CC400000 Altex Electronics 11342 IH 35 North San Antonio Texas 1 800 531 5367 or FAX 210 637 3264 Mini Tower model number 5 05 Medium Tower model number 5 08 Full Tower model number STC 16 Mega Tech Marketing Inc 3900 D Drossett Dr Austin Texas Mini Tower model number A6601 Full Tower model number A5561 Note IBM makes no recommendations regarding vendors of any components In planning the layout of an enclosure the height of the items in Table 57 should be consid ered Table 57 Height Considerations SIMM eate 2 SRAM SIMM seated 160 MPRH01TSU 02 PowerPc Physical Design Section 12 Physical Design Guidelines 12 1 General Considerations These guidelines are given to aid designers with the physical design phase of their Pow erPC reference design board The guidelines are not intended to replace good physical de sign practices for the signal ty
11. ol oO O O O O O O O O O X X lt lt lt X active Blank inactive Byte enables would normally represent contiguous dresses This table shows what would happen for all cases 40 MPRH01TSU 02 PowerPc PCI Bus 3 3 Bus Arbitration Logic The reference design uses the Intel SIO as the PCI bus arbiter The PCI arbiter sees the 660 bridge as one of several PCI agents The order of priority for PCI arbitration is program mable and is initially set to be 1 660 bridge the SIO normally parks the bus on the 660 bridge 2 PCI slot 1 3 PCI slot 2 4 PCI slot 3 For more information on arbitration see section 9 on reference design initialization and see the PCI Arbitration Controller section of the SIO data book See the reference design schematics for the connection of the various PCI requests and grants There may be concurrency of cycles on the ISA bus caused by DMA or ISA masters with PCI or CPU transactions as long as the ISA bus operations are not forwarded to the PCI bus Forwarding of ISA bus operations must wait for the ISA bridge to grant the PCI bus to its ISA interface 3 4 Other PCI Considerations The reference design motherboard presents from 7 to 10 PCI loads to the bus and at least three additional PCI compliant agents loads can be added to the PCI bus witho
12. 146 Table 47 3 3V Power Connector J5 Pin Assignments 147 Table 48 Power Connector J4 Pin Assignments 147 Table 49 AUX5 ON OFF Connector Pin Assignments 148 Table 50 PCI Connector Pin Assignments 148 Table 51 ISA Connector Pin Assignments 150 Table 52 SIMM Connector Pin Assignments 152 Table 53 Power Switch Connector Pin Assignments 154 Table 54 Power Up Configuration Connector Pin Assignments 154 Table 55 L2 SRAM Module Connector Pin Assignments 155 Table 56 RISCWatch Connector Pin Assignments 157 Table 57 Height Considerations 160 Table 58 Clock Net Lengths 7 lt a lt 10 165 Table 59 CPU Bus Nets i 165 Table 60 Timing Critical Nets 166 Table 61 PCI Bus Nets 167 Table 62 Noise Sensitive Nets 167 Table 63 PowerPC 603 604 Reference Design Roadmap 170 Table 64 603e Bill of Materials 189 Table 65 604 Bill of Materials 194 14 MPRH08TSU 02 PowerPc About This Book Notice The 603 version of the PowerPC
13. 87 Table 28 Rearranged 4 Byte Transfer Information 88 Table 29 Mapping of PCI Memory Space Part1 95 Table 30 Summary of SIO Register Setup Configuration Address 8080 08xx 104 Table 31 Summary of SIO Configuration Registers 106 Table 32 Configuration Address Assignments 107 Table 33 Combined Register Listing 108 Table 34 660 Bridge Indexed Listing 114 Table 35 Compatible ISA Ports Not on Reference Board 116 Table 36 Power Supply Specification 137 Table 37 Approximate Power Consumption 137 Table 38 Specifications for 3 3V Regulator on the Motherboard 138 Table 39 Specifications for 2 5V Regulator on the Motherboard 138 Table 40 Keyboard Connector Pin Assignments 144 Table 41 Mouse Connector Pin Assignments 144 MPRHOSTSU 02 13 PowerPc Table 42 Speaker Connector Pin Assignments 145 Table 43 Power Good LED Connector 145 Table 44 HDD LED Connector 145 Table 45 Reset Switch Connector 146 Table 46 Fan Connector Pin Assignments
14. 4 1 74016237 SSOP48 16 BIT TRANS LATCH FCT162373 3CTPV F_BEAD BEAD 26F4865 FB1 FB2 FB4 FB6 HF50ACB 1206 FERRITE BEAD 321611T MPRHO1TSU 02 185 BOM P2werPc Table 65 604 Bill of Materials Continued Part Name Part Ref Des Qty Manufac Manufac JE Part Description Number turer DEC TYPE Part Number 50 IBM82663 SMD 94G0235 1 BM 27 QFP240 5MM DATA MAPPING 8 BUFFER 82663 1 IBM82664 SMD 94G0232 1 BM 27 QFP208 5MM SYSTEMS amp MEMORY 82664 CONTROLLER 52 10 71216 1 DT DT71216 QFP80_ TAG RAM IDT71216 DO_NOT_POP S 10 PF 65MM 2M 53 IDT71216 05H1054 1 D DT71216 QFP80_ TAG RAM IDT71216 IDT71216 S 10 PF 65MM 2M IRFZ44 SMD 03G9500 Q6 Q7 2 RFZ44 TO220X TRANSISTOR 50V 35A 5 LT1431REG 31 2428 LINEARTECH LT1431CS8 VOLT REGULATOR 6 LT1431REG 3172428 1 LINEARTECH LT1431CS8 8 VOLT REGULATOR DO_NOT_POP 7 881 970 05 1509 1 MOTOROLA MC88LV QFP52_65MM CLOCK CHIP 970FA 8 MTGHOLE MH1 MH3 MH5 MH 157TOOLS DO_NOT_POP 7 MH8 OSCLR 87F5263 Y 1 EPSON SG 615P OSCSMT4 OSCLR 14 3181MHZ 14 31818 MC OSCLR 24 0MHZ 87F5265 Y 1 EPSON SG 615P OSCSMT4 OSCLR 24 0000MC 1 PALCE16V8_SKT 19G5840 M6 M7 822014 3 20 20 5 SKT PLCC32SKT SMD 10G7624 821977 1 PLCC32SKT 32 PIN PLCC SOCKET 3 POLYSWITCH SMD 3463113 RAYCHEM SMD100 POLYSWITCH TAPE RESISTOR
15. 1 1 1 Ke he he he he e he he he he he k k k k S UNFREEZE Flip Flop is cleared asynchronously when the UNFREEZE signal makes a low to high transition It is set once shifting has been enabled The CHANDRA ignores the UNFREEZE signal if the 601 PCLK clocks are not frozen S5 ke ke e e e e e e he ke he e e e se he e he e he KKK he he SUN FREEZEFF prn SNC_SHIFT_ENFF q amp RESET UNFREEZEFF clrn VCC UNFREEZEFF SHIFT_ENFF q UNFREEZEFF d CLKFF 0 q CLKFF 1 UNFREEZEFF clk UNFREEZE MPRHO01TSU 02 63 EPLD PowerPc he k he he he e he e ke This signal is the UNFREEZE Flip Flop synchronized to the ISA clock he he e he e e SNC_UNFREEZE prn SNC_UNFREEZE clrn VCC SNC UNFREEZE d UNFREEZEFF q SNC UNFREEZE clk ISA CLK he
16. K Below is fix for Errata 7B 11 13 TA_CNTO TA_CNTO TA_ TA_CNTO DBB_ TA_ TA_CNTO TA_ TA_CNT1 DBB_ TA_CNT1 MASK BG3 TA_CNTO TA_CNT1 SRAM DBB_ ERR 13 ABB SRAM DBB ERR 7B PCI IN DBB ERR 11 MASK 7A ABB DEL ABB DBB ERR 7A MASK 7B ABB DEL ABB DBB ERR 7A 2 ERRATA 7 fix for Async caches MASK 7B feeds wires to CPUPAL MASK BG3 input to be included in BG equation shown below BG OUT BG IN 2 MASK BG2 for Errata 5 P MASK BG1 Errata 5 ABB DEL ABB Errata 7 MASK BG3 DBB for Errata 7 Asych cache fix MASK 7 PCI _ DEL_ABB_ MASK_7B MASK_7A _ DEL_ABB_ 7B DEL ABB 2
17. 80000806 8004 0008 HDD Light 080C 8000 0800 8004 0000 Equipment Present 0 L2 Cache Status Reg 0814 L2 Flush System Control 81C Memory Controller Misc 082A 8000 082A 8004100A Power Mgmt Control Reg1 82 8000 082B 8004100B Power Mgmt Control Reg2 840 8000 0840 8004 2000 Memory Parity Error Status 84 8000 0842 8004 2002 12 Error Status 843 8000 0843 8004 2003 L2 Parity Read amp Clear 84 Unsupported Transfer Error 0850 8000 0850 Map 852 80000852 80042012 Board 860 Freeze Clock Reg Low 86 Freeze Clock Reg High 0880 SIMM Presence Detect Slot 1 2 881 SIMM Presence Detect Slot 3 4 8000 OCF8 PCI BCR Configuration Address 8000 OCFC PCI BCR Configuration Data 8080 08 PCI Type 0 Configuration Addr 8080 0800 Vendor Identification C s r ko o E CD 8 E R CD ojo wj no 2 21212 32 2 2 Z Z 2 2 2 2 2 Z O u 5 E Fosic 0827 82 ojo UJ m
18. 36 Table 8 Mapping of PCI Memory Space 2 37 Table 9 Mapping of PCI Master I O Transactions 38 Table 10 Active CAS Lines PCI to Memory Writes BE or LE Mode 40 Table 11 DMA Assignments 46 Table 12 DRAM Module Presence Detect Bit Encoding 48 Table 13 Planar ID Encoding 48 Table 14 DRAM Module Presence Detect Bit Encoding 49 Table 15 External Register Support 51 Table 16 Signal Descriptions 54 Table 17 Supported DRAM Modules 67 Table 18 12 Configuration Implementation 73 Table 19 Endian Mode Byte Lane Steering 78 Table 20 Endian Mode 6 3 604 Address Translation 78 Table 21 Memory in BE 81 Table 22 Memory in EE Mode 82 Table 23 PCI in BE Mode 82 Table 24 POl EE Mode gt sa nuw uusha 83 Table 25 Two Byte Transfer Information 85 Table 26 Rearranged 2 Byte Transfer Information 85 Table 27 4 Byte Transfer Information
19. 0 RUPEE NATA 212 MOR CEU pitas Bags DPI apana D RIO ERE 2 2 System Response by CPU Bus Transfer Type 23 System Response by CPU Address Range 2 3 1 Address Mapping for Non Contiguous 2 3 2 Address Mapping for Contiguous I O 2 3 3 PCI Final Address Formation 2 4 CPU to Memory Transfers 2 4 1 a 25 CPU to PCI Transactions 2 5 1 GPU To POlead 25 2 CPU to m Foi arbo d arb ndo 2 5 21 Eight Byte Writes to the PCI Memory I O 2 5 3 CPU to PCI Memory Transactions 2 5 4 CPU to PCI I O Transactions 2 5 5 CPU to PCI Configuration Transactions 2 5 5 1 Preferred Method of Generating PCI Configuration Transactions MPRH08TSU 02 5 PowerPc 2 5 5 2 650 Bridge compatible 32 2 5 6 CPU to PCI Interrupt Acknowledge Transaction 33 EN OU os Se dl drm a SMO 33 2 6 CPU to HOM Transfers S em exe Ire 33 2 6 1 CPU t ROM Read 34 2 02 GPUt ROM sette vera Sic RES RES 34 25 2 ROM Write Protection eoo spei eon el
20. 2 3 4 5 6 7 8 9 111213 14 15 16 Figure 58 2x8 RISCWatch Connector Table 56 RISCWatch Connector Pin Assignments 11 3 21 Battery Connector BT2 The battery type is CR2032 3 Volt Insert the battery with side up MPRHO1TSU 02 157 PowerPc Electromechanical 11 3 22 Reference Design Board Connector Footprint 1 1 5 37905 S E 0 194139 XZ qum vo 5 3003 dvNvTd 92070 20710 X9 De Xo 65 ed 4779 XZ NIW 6 X2 1 2 5 19d 941909 Xo 5070 960 0Z Eb D XZ We IXE 7572 Ko o o o o DD o o O 9 o o 9 9 o O O oo D ee S 2 TE 520 02 3100 wg 90 0 I 161 S gt 5100 z Dj 16 5 22 69764 5522 24779 VO 78 MPRH01TSU 02 4272 997 6 2 19130 Xv 88756 5781 790 00 89719 5070 Sir QUA A a 0 00 0 0 0 0 0 0 0 0 0 0 0 8 400000009900000 00 4 6 0 000 0000 000 00644 G 960 0 52 56 77720 viv rS r LO 6 141935 YSI V X
21. E 8 Go N 8 5 Go O ol ol 5 Go e eo co 0096 8000 0096 09 009C 8000 009C 09 8000 009 8000 00A0 8000 5000 OA 000 04 0 8000 8000 600 8000 0005 8000 6005 DMA2 CH3 Base and Current Cnt R 8000 0002 8000 6012 DMA2 Soft Request w 004 80000004 80006014 DMA2 Write Single W 0006 O 181 OJO O TD eo gt E oo gt E 5 5 X MPRH01TSU 02 109 Setup PowerPc Table 33 Combined Register Listing Continued Mode Addr Mode Addr 6 4 0058 80000008 80006018 DMAZClearBye Pointer ODA 8000 00DA 8000 601A_ DMA2 Master Clear 8000 0006 80006016 DMA2ClearMask RW
22. 1 OF Of n 0 0 0 3 1 1 1 1 1 1 1 2 1 1 2 2 2 1 4 4 4 3 5 5 5 2 6 6 6 1 1 7 7 7 k i S rp ol pa p wW UNMUNGE 2 Notes At the CPU side 0 1 set to 00 for all PCI transactions except I O cycles MPRHO1TSU 02 83 Endian Modes PowerPc 7 7 Two Byte Transfers Figure 18 gives an example of double byte write data ab at address XXXX Big Endian Little Endian 603 604 Swap Off Memory 603 604 Swap On Memory Figure 18 Double Byte Write Data ab at Address XXXX XXX0 Table 25 and Table 26 illustrate all cases that can occur The columns of Table 25 have these meanings The first column indicates target address e g the address of the byte coded into a store half word instruction The next two columns show the state of the address pins for BE mode The next two columns show the state of the address pins for the same target data when the machine is in LE mode The remaining columns show the CASs and the PCI byte enables associated with the target data The notes indicate which combinations either do not occur at the 603 pins because of internal exceptions or are not supported externally 84 MPRH01TSU 02 PowerPc Endian Modes For 2 byte transfers Table 25 holds Table 25 Two Byte Transfer Information BE MODE LE MODE BE OR LE BE OR LE B
23. 90 MPRH01TSU 02 PowerPc Endian Modes 6 Set the CPU state and the motherboard to LE see Figure 22 Note that CPU is now in LE mode All instructions must be in LE order 7 Putinterrupt handlers and CPU data structures in LE format 8 Enable caches 9 Enable Interrupts 10 Start the LE operating system initialization Figure 22 shows the instruction stream to switch endian modes x mfspr 2 1008 Load the HDO register Instructions to set the Little Endian bit in R2 0 sync sync sync mtspr 1008 R2 Moves to HIDO register Sync Sync Sync Sync Store to external Endian control 8000 0092 above instruction must be a double word boundary So the following instruction is executed first due to pipeline 24 eieio To this point all instructions are in Big Endian format The following instructions look the same in either Endian mode 28 X38010138 26 38010138 Enough of these instructions must be executed to guarantee the above store has occurred before any memory or I O cycles are listed XX X38010138 Figure 22 Instruction Stream to Switch Endian Modes MPRHO1TSU 02 91 Endian Modes PowerPc 7 12 Summary of Bi Endian Operation and Notes When the 603 604 CPU is in BE mode the memory is in BE mode and data flowing on the PCI is in BE order so that it is recorded on the media in BE order Byte 0 is the most significant byte When the 603 604 processor is in LE mode the memory i
24. 97 9 IS 89 BEI lt T EJ 520709 7572 dAl 8070 I ve es Eg vS 6 Electromechanical 11 3 23 Reference Design Board Connector Footprint 2 PowerPc 20 81 C 1514 SSE 0 5 1 2 6 0 lt 610 21 y D 4 S lt r1 19968 oov O O 2 ME re 88 55 8706 i NA oj gt olx 0 150 dAL 5710 S alg Em 960 OS 50 581 vv lt 70 25 66 9v 96270 eS 70 0 p gr 0 207129 X091 1671 Xc Ol 26 pe Y ve Oll LO 36 78712 31925 1 2 37925 1 2 119130 1 2 39428 PM PESE E 19139 92670 11914 MINE 11752 ioo gt E 82771 670 08 10 20 X21 ca X9 10766 5 b 4 9 24 26 SP PSN 1 X51 T 20710 1271 gt 670 0 590 XZ gl 66 0 5971 59716 eg 0g E 96 V o 61 18
25. Firmware 136 PowerPc MPRH01TSU 02 Y al P amp Electromechanical Section 11 Electromechanical 11 1 Electrical 1111 Power Requirements This section sets out the power supply requirements for the motherboard They are achiev able with low cost PC power supplies see Table 36 for specifications and Table 37 for approximate power consumption Table 36 Power Supply Specification cc Maximum Fipple PP 110 9 ia0 mV 5 1 10 10 120 mV 327 2 15 4 Table 37 Approximate Power Consumption 5V 12V 12V 5V 3 3V pom mm amen me running typical code 8M DRAM standby refresh each 32 standby refresh each 016 0 i 256K SRAM L2 Cache m Main Power Connector at 2 0 amp pin 20 amp DC return 1 5vis not used on the planer but it is routed from the power supply connector to the ISA slots 2 3 3v to the PCI bus slots comes from the power supply connector The 3 3v for the CPU and the 660 bridge is a separate supply generated from the 5v supply by a linear regulator 3 These power requirements are allocated by the system designer The currents specified per slot in Table 37 are also the maximum currents which may be consumed by the bus Because of this the total currents for all the cards used for either the PCI slot or the ISA slot must not exceed the amounts listed in Table 37
26. IRQ1 Set Keyboard 1 latch on rising edge of IN1 INT1FF clrn RESET amp CLRINT1 IRQ1_OUT INT1FF q RTC_ALE I O address 0070 ALE 2 1 0 ECS 2 ECS 1 8 ECSEN 8 XIOW address 0071 RTCWR 2 amp A 1 amp 0 ECS 2 8 ECS 1 8 ECSEN amp XIOW RTCDS I O address 0071 RTCDS 2 1 6 0 amp ECS 2 8 ECS 1 6 ECSEN amp XIOR 50 address 0074 50 A 2 6 1 6 0 8 ECS 2 8 ECS 1 8 ECSEN 6 XIOW 51 address range 0075 AS1 A 2 amp A 1 6 0 amp ECS 2 8 ECS 1 8 ECSEN amp XIOW address 0077 NVRAMWE 2 6 A 1 0 8 ECS 2 amp ECS 1 8 ECSEN 8 XIOW address range 0077 NVRAMOE A 2 6 A 1 A O 8 ECS 2 amp ECS 1 8 ECSEN 8 XIOR 5 DRAM PD_RD1 enables Present Detect address range 0880 DRAM PD_RD1 A 7 amp 6 amp 5 amp 4 amp 3 amp 2 amp A 1 amp 0 8 GPCSO 8 XIOR MPRH01TSU 02 61 EPLD PowerPc DRAM PD_RD2 enables Present Detect I O address range 0881 DRAM_PD_RD2 A 7 amp 6 amp 5 amp 4 amp A 3 amp 2 amp A 1 amp 0 amp GP
27. Signal SWTOR P SWITCH GD 11 3 18 Power Up Configuration Connector J7 Figure 56 1x2 Power Up Configuration Connector Pins are assigned as shown in Table 54 Table 54 Power Up Configuration Connector Pin Assignments PinNo _ Signal pmo 2 Pw oF 154 MPRH01TSU 02 Y al P amp Electromechanical 11 3 19 L2 Cache Data SIMM Connector J3 Top view 124 122 Figure 57 L2 SRAM Module Connector Pins are assigned as shown in Table 55 Table 55 L2 SRAM Module Connector Pin Assignments oo ol a ol SOF O CT ST ol N A ol ol NJ S m 2 a N oaol rl ol ol o N OY AY o 97 E A PT PT PT N N m ol ol ol NI 1 ol m MPRH01TSU 02 155 7 al Electromechanical Power Table 55 L2 SRAM Module Connector Pin Assignments Continued wl ol A ol ol 4 51 ol ol at o oy 156 MPRHO01TSU 02 P Electromechanical Table 55 L2 SRAM Module Connector Pin Assignments Continued 11 3 20 RISCWatch Connector J19 Top view
28. This signal is the FREEZE Flip 1 synchronized to the ISA clock k k k k k k ke he he e e SNC_FREEZE prn SNC_FREEZE clrn VCC SNC_FREEZE d FREEZEFF q SNC_FREEZE clk ISA_CLK he he e he e This signal is the FREEZE Flip Flop double synchronized to the ISA clock K KKK k DOUBLE_FRZ prn DOUBLE_FRZ clrn VCC DOUBLE_FRZ d SNC FREEZE q DOUBLE FRZ clk ISA CLK SHIFT ENFF s CLKFF SELH Start shifting upon write to 862 SHIFT ENFF r GND SHIFT ENFF prn DOUBLE SNC q amp DOUBLE FRZ SHIFT ENFF clrn GEN STOP BITFF q 6 RESET Clr when it reaches 15 6 rst SHIFT ENFF clk XIOW SNC SHIFT ENFF d SHIFT ENFF q One clock after SHIFT_ENFF SNC SHIFT ENFF ena RESET SNC SHIFT ENFF clrn RESET SNC SHIFT ENFF clk ISA CLK CNTR clk ISA CLK CNTR clrn RESET Counter resets to zero 64 MPRH01TSU 02 PowerPc EPLD If SNC SHIFT ENFF q Then Count
29. 11 3910 Fan Connector IO MESA Eten era t 11 3 11 3 3V Power Connector J5 11 3 12 Power Connector J4 epe 11 3 13 AUX5 ON OFF Connector J6 11 3 14 PCI Connectors J25 J26 and J27 11 3 15 ISA Connectors J29 J30 J31 J32 and J33 11 3 16 SIMM Connectors J21 J22 J23 and J24 11 3 17 Power Switch Connector 8 11 3 18 Power Up Configuration Connector J7 11 3 19 L2 Cache Data SIMM Connector 11 3 20 RISCWatch Connector J19 1103 21 Battery Connector BT2 Su pet ne nid 11 3 22 Reference Design Board Connector Footprint 1 11 3 23 Reference Design Board Connector Footprint 2 11 4 Enclosure Section 12 Physical Design Guidelines 12 1 General Considerations 12 1 1 Construction MPRHOSTSU 02 127 133 134 135 135 137 137 137 138 138 139 139 139 140 140 141 141 142 143 144 144 145 145 145 146 PowerPc 12 1 2 General Wiring Guidelines 164 122r Cloe KNE c tue tupa ste acer eene Dic dE I su 164 12 9 CPU BUS NEIS tetto Syn 165 12
30. 2 so 8000 0422 8002 1002 2 E 8000 0424 8002 1004 E 8000 0426 8002 1006 E 8000 0428 8002 1008 SO 42 2 SO ELA ELA EES RISE ojo CD 0 0 O N O E 420 2 2 42F 8000 042F 8002 100F 3 435 8000 0435 43 0437 8000 0437 43 0439 8000 0439 o O O O 110 MPRH01TSU 02 PowerPc Setup Table 33 Combined Register Listing Continued Mode Addr Mode Addr 043A CH6 Scatter Gather Pointer 43B CH6 Scatter Gather Pointer 43C CH7 Scatter Gather Pointer CH7 Scatter Gather Pointer 043E CH7 Scatter Gather Pointer CH7 Scatter Gather Pointer 481 2 High Page 8 DMA CH3 High Page 8 1 High Page 487 80000487 80024007 DMA High Page 48 8000 0489 80024009 DMA CH6 High Page 048A 8000 048A 8002 400A DMA CH7 High Page 8000 048 8002 4008 DMA CH5 High Page 0400 8000 0400 80026010 Interrupt Control 1 4D 8000 04D1 8002 6011 Interrupt Control 2 406 8000 0406 8002 6016 DMA2 Extended Mode
31. 47 4 6 1 Control Signal Decodes 47 4 6 2 Keyboard Mouse Controller 47 46 3 Real Time Clock RTC 47 4 6 4 X PCI Adapter Card Presence Detect Register 47 4 6 5 L2 SRAM Identification Register 46 4 6 6 Planar ID Detection Register 48 4 6 7 DRAM Presence Detection 49 4 6 7 1 DRAM SIMM 1 2 Memory ID Register 49 4 6 7 2 DRAM SIMM 3 4 Memory ID Register 49 4 7 MiscellaneouS 50 4 7 1 Speaker 31 sat Z b uapa sama aa basa 60 Section 5 System EPLD 51 5 1 System Register Support 51 MPRH08TSU 02 PowerPc 5 1 1 External Register Support 5 1 2 Internal Registers 5 1 2 1 Storage Light Register 5 1 2 2 Power Management Control Register 1 5 1 2 3 Power Management Control Register 2 5 1 2 4 Freeze Clock Register FCR Low 5 1 2 5 Freeze Clock Register FCR High 5 2 Signal Descriptions 5 3 Design Equations
32. 5 MASK BG2 for Errata 5 MASK BG3 Errata 7 CPU_AO GND for Errata 6 BR OUT BR IN _ MASK BR for Errata 8 174 MPRH01TSU 02 PowerPc 6 13 3 4 HBROOM Reference Design Workaround PAL TITLE HBROOM pds PATTERN none REVISION 1 0 COMPANY IBM DATE 08 07 95 CHIP PALCE16V8 Predefined PIN 1 CPU_CLK CLOCK 10 GND GROUND PIN 11 REG_OE OUTPUT ENABLE FOR REGISTERED OUTPUTS PIN 20 Inputs PIN 2 INPUT PIN 3 PCI_GNT_IN_ INPUT PIN 4 ABB INPUT PIN 5 INPUT PIN 6 INPUT PIN 7 DBB_ INPUT PIN 8 _ 9 SRAM OE INPUT PIN 16 MASK PCI GNT INPUT Outputs PIN 17 PCI GNT OUT COMB COMB Internal Registers PIN 12 DEL ABB REG REG PIN 13 MASK 7A REG REGISTERED PIN 14 MASK 7B REG REGISTERED PIN 15 MASK BG3 REG REG PIN 18 TA CNTO REG PIN 19 TA CNT1 REG MPRHO1TSU 02 175 Erai PowerPc Output enables for Comb logic Reg OE s controllered by pin 11 Equations for internal registers k k k k k k k k k k k k k k k k k k k _ _ k k k k I k k k k k k k k k k k k k k k k k k k k k k k k k k k k K k
33. 604 Bill of Materials Continued Part Name Part Ref Des Qty Manufac Manufac JE Part Description Number turer DEC TYPE Part Number RESISTOR 98F1737 R352 R358 7 ERJ6GVJ SMC0805 RESISTOR 5 6K 5 562S 87 RESISTOR 4170331 118 245 2 PANASONIC ERJ6GVYJ 5 0805 RESISTOR 510 5 5115 88 RESISTOR 0909165 R66 R78 R244 14 PANASONIC ERJ 3VKF SMC0603 RESISTOR 54 9 1 54895 RESISTOR 61F2960 R63 1 PANASONIC ERJ6GVJ SMC0805 RESISTOR 620 5 621S 515 75 5 61F2961 R79 R359 R361 PANASONIC ERJ6GVJ 5 0805 RESISTOR 750S 91 RESISTOR 4006887 1 PANASONIC 6 5 RESISTOR 80 6 1 8096 92 RESISTOR R116 R117 R121 34 NONE NONE SMC0805 RESISTOR DO_NOT_POP5 R146 R149 R152 R168 R170 R172 R179 R185 R186 R189 R191 R193 R198 R382 R383 R385 R417 R419 R422 R424 R427 R440 R441 R443 R447 R466 R467 R477 R478 RLS4148 SOIC 87F4920 C ROHM RLS4148 MELF 40V 1A SCHTK REC 94 24_1 33 5 RP1 RP3 RP7 RP9 CMD 110 QSOP24 RESISTOR RP10 2433 ROJ 82378ZB SMD 82G6542 INTEL 58237828 QFP208 5MM PCI TO ISA BRIDGE CONT R2 XTAL 16 50MHZ 89G3833 A 1 ECLIPTEK ECX 2900 CLP XTAL 16 5 MHZ CRYSTAL 16 500MHZ A U7 2 XTAL DO NOT POP NONE 3 NONE NONE CLP XTAL NONE m 6 1 4 6 X PART CPUHSINK 11H6666 X 1 SANYO REMP5412 XLOOSE FAN H2026 X PART H604C 8185187 X 1 AMD PALCE16V8 XPLCC20 PROG
34. CLKFF SELL CLKFF 12 q amp CLKFF SELH TRI D 5 XD TRI OE CLKFF 5 q amp CLKFF SELL TRI D 6 XD TRI OE CLKFF 6 q amp CLKFF SELL TRI D 7 XD TRI OE PWR REG2 2 q amp PWR REG2 STRB CLKFF 7 q amp CLKFF SELL 66 PowerPc MPRH01TSU 02 P2werPc Memory Section 6 Memory Systems The reference design contains four distinct memory systems system memory DRAM L2 cache memory SRAM and tagRAM ROM for boot and POST code and NVRAM 6 1 DRAM The reference design has slots for up to 128M of system memory DRAM arranged as four industry standard 72 pin SIMMs see Table 17 When using more than one pair of 32MB SIMMs however it is necessary to insert a buffer on the WE 1 0 and MA 11 0 lines between the SIMMs and the 664 in order to drive the increased capacitive load presented by the 32MB SIMMs The reference design does not buffer these signals and does not pro vide circuit board patterns for such buffers 70ns 4 data bytes plus 1 parity bit per byte 72 pin SIMM presence detect bits Table 17 Supported DRAM Modules Size Organization IBM Part Number DRAM Data Sheet 1M x 36b IBM11E1360BA MMDS14DSU 00 2Mx36b IBM11E2360BA MMDS22DSU 00 16MB 4Mx36b IBM11E4360B MMDS26DSU 00 32MB 8Mx36b IBM11E8360B MMDS27DSU 00 611 Refresh The memory controller in the 660 bridge provides a flexible refresh capability for the refer ence design The ISA bus bridge provides the IS
35. Double Synchronized FREEZE BEGINS S CHANDRA uses 510 5 General Purpose Register Decode 0 Software sets to 800 8FF to enable the following decoded signals GPCSO LCELL 5 2 amp 5 1 amp 5 0 amp ECSEN Hard Disk Light address range 0808 LIGHT STRB 7 8 6 5 4 3 8 A 2 1 amp A 0 8 50 HDD LEDFF s XD 0 amp LIGHT STRB HDD LEDFF r XD 0 amp LIGHT STRB HDD LEDFF clk GLOBAL XIOW HDD LEDFF clrn RESET HDD LED HDD LEDFF q 5 Equipment present Read Command 1 1 0 address range 080 PRSNT_RD A 7 amp A 6 amp A 5 amp A 4 amp A 3 amp A 2 amp A 1 8 0 8 GPCSO 8 XIOR Equipment present Read Command 2 I O address range 080D L2_STATUS_RD 7 amp 6 amp 5 amp 4 amp 3 6 2 amp 1 8 0 8 GPCSO 8 XIOR External Internal Planar ID I O address range 0852 PLANAR ID RD 7 amp 6 8 5 6 A 4 8 3 8 2 amp 1 0 8 GPCSO 8 XIOR 60 MPRH01TSU 02 PowerPc EPLD Keyboard Chip Select I O address range 0060 0062 0064 0066 KYBD_CS 5 2 amp 5 1 amp 5 0 amp ECSEN Keyboard interupt INT1 Clear KBD_CS qualified with XIOR CLRINT1 ECS 2 amp ECS 1 amp 5 0 amp ECSEN amp XIOR INT1FF d VCC INT1FF clk
36. FFFF FFFO FFFFFFFO Flash Write W 660 FFFFFFF1 FFFF FFF1 Flash Lock Out WOT 660 1 The first 5 hex digits in the contiguous and non contiguous mode columns represent the memory page number for which the protection attributes may be set in contiguous mode That is devices having the same first five digits in this column will have the same attributes in the memory page table 2 Port 94 may be used by certain video controllers e g Weitek 9100 The SIO chip pos itively decodes this port Therefore bus contention may arise when both devices claim the PCI cycle to this port address Bus contention results in invalid data and possibly harm to the hardware 3 The control signals for these ports are partially decoded by the SIO The System EPLD completes the decodes and issues control signals to the registers which are usu ally X bus buffers 4 KBD Keyboard Mouse Controller RTC Real Time Clock also known as the TOD Time Of Day clock NVR Non Volatile RAM in the same package as the 660 The 660 Bridge 5 Not used 6 Inthe Set To column a long dash means that the initialization firmware does not write to this register The register is either not used not written to or the value of it depends on changing circumstances If the word Memory appears please refer to the System Memory section of the 660 User s Manual 7 Set register 81C to COh if an
37. and the Illegal Transfer Error register is set 8 2 7 Error Status Registers Error status registers in the 660 Bridge may be read to determine the types of outstanding errors Errors are not accumulated while an error is outstanding however there will be one TEA or MCP for each error that occurs For example if an illegal transfer error causes a TEA a memory parity error can occur while the CPU is processing the code that handles the TEA The second error can occur before the error status registers are read If so then the second error status is not registered but the from the memory parity error is as serted 8 2 8 Reporting Error Addresses One register holds the address for any memory parity error multi bit ECC error or illegal transfer error when either the CPU or a PCI agent reads memory It is also loaded on CPU cycles that cause the Illegal Transfer Error register to be set See the System Error Address BCR information in the Bridge Control Registers section of IBM27 82660 PowerPC to PCI Bridge User s Manual for more information 8 2 9 Errant Masters Either PCI or ISA masters can access certain motherboard and ISA bridge registers For example various control registers such as the I O Map Type register mode bit the Memory Control registers etc are accessible Faulty code in the PCI or ISA masters can defeat password security read the NVRAM and cause the system to crash without recovery
38. and the initiator master aborts the cycle The initiating bus master must be programmed to notify the system of master aborts as needed The system logic does not notify the CPU MPRHO1TSU 02 97 Exceptions P 2 c 8 2 5 No Response on CPU to PCI Cycles Master Abort The 660 bridge master aborts if no agent responds with DEVSEL within eight clocks after the start of a CPU to PCI cycle The cycle is ended with a TEA response to the CPU all 1 s datais returned on reads the Illegal Transfer Error register is set and the Error Address register is held The 660 bridge also checks for bus hung conditions If a CPU to PCI cycle does not termi nate within approximately 60 usec after the PCI is owned by the CPU the cycle is termi nated with This is true for all CPU to PCI transaction types except configuration transactions This feature may be disabled via a 660 bridge control register In the case of configuration cycles that do not receive a DEVSEL no device present at that address the PCI cycle is master aborted and normal response is returned Write data is thrown away and all 1 s are returned on read cycles No error register is set and no address is captured in the error address register 8 2 6 CPU to PCI Cycles That Are Target Aborted When any CPU to PCI cycle of any sort receives a Target Abort from its target PCI agent the CPU cycle is terminated with a TEA the Error Address register is held
39. code atthe vector location requests a single byte read of memory address BFFF FFFOh 5 Inresponse to the read the 660 bridge arbitrates for the PCI bus and then generates an interrupt acknowledge transaction on the PCI bus 6 The ISA bridge decodes and claims the PCI interrupt acknowledge transaction and returns the 8 bit vector which has been preprogrammed for the active interrupt and then negates the interrupt output whichever of INT REQ or NMI_REQ that it as serted 7 The 660 bridge accepts the interrupt vector on the PCI bus and returns it to the CPU If the ISA bridge signalled the interrupt via INT_REQ the 660 bridge asserts TA to terminate the CPU transfer normally However if the interrupt was signalled via NMI_REQ the 660 bridge terminates the CPU transfer with TEA Since the CPU does not require that the interrupt signal INT_CPU be deactivated be tween interrupts another interrupt is allowed to occur as soon as software sets the MSR EE bit back to 1 For this reason software should enable interrupts as soon as pos sible after receiving the vector Note that the load instruction that fetches the interrupt vector is subject to out of order execution in the same way as any other load instruction After servicing the interrupt execute a return from interrupt RFI instruction to return to the pro gram that was interrupted For more information on interrupts see the Exceptions chapters of the PowerPC 603 User s Manu
40. nect as shown in the 603 604 Reference Design Power Management Guide RWD0 96 Power management controller serial read write data bit 24mA No connect or connect as shown in the 603 604 Refer ence Design Power Management Guide UNFREEZE 82 Unfreeze No connect connect as shown in the 603 604 Reference Design Power Management Guide Other Signals HDD_LED O Hard disk drive activity light EPLD asserts this signal while bit 0 of the storage light register port 0808 is 1 This signal normally indicates hard disk drive activity RESET System reset Used by EPLD to reset internal state ma chines and internal registers V 18 19 43 5V 44 68 69 93 94 CC GND 12 13 37 GROUND 38 62 63 87 88 56 MPRH01TSU 02 PowerPpc 5 3 EPLD Design Equations 5 3 1 Fit File MAX plus II Compiler Fit File Version 5 0 8 5 94 Compiled 05 05 95 14 44 22 BEGIN DEVICE EPM5130WC 1 AQ Al A2 A3 A4 A5 A6 AT CMD STATE ECSEN ECSO ECS1 ECS2 EXT ACTVTY 01 IRQ12 ISA CLK PROC RDY RESET UNFREEZE XIOR XIOW ACTIVITY AS0 AS1 DRAM_PD_RD1 DRAM_PD_RD2 FRZ DATA OUT HDD LED IO_STROBE IRQ1_OUT KYBD_CS L2 STATUS RD NVRAMOE NVRAMWE PLANAR ID RD PRSNT RD MPRHO01TSU 02 57 INPUT PIN INPUT PIN INPUT PIN IN
41. o O O E o o 80000408 8002 0006 DMAT Extended Mode 410 8000 0410 80020010 CHO Scatter Gather Command W 11 80000411 8002 0011 CH1 Scatter Gather Command W 8000412 8002 0012 ScaterGatherCommand W 0413 8000 0418 80020013 CHS ScatterGather Command W 8000 0415 80020015 CH5 Scater GatherCommand W 0416 8000 0416 8002 0016 CHE Scatter Gather Command W 80600417 80020017 CH7 Scater GatherCommand W 21 8000 0418 80020018 0 ScatierGainer Saus R 419 80000419 80020019 CH1 ScaterGaerStaus F 041A 8000 041A 8002 001A CH2 ScaterGatherStaus R 8000 0418 8002 0018 CHS ScatterGather Status R Bd EB NN ojlo 5 o o o g o O O O E P E EL FEE EE ELE END ELE RED o 041D ES 41F oer 420 8000 0420 8002 1000 Scatter Gather Pointer RW 50 zS E TUER d E EM N
42. ou zd ea RS RE I 182 134 2 2 Design File EM wet 184 13 4 2 3 Broom PAL Design File 186 13 4 8 Workaround PAL Installation 188 Section 14 Bill of Materials 189 14 1 6036 604 Reference Design Bill of Materials 189 14 1 1 603e Bill of Materials bie ad eB kee ee 189 14 1 2 604 Bill of Materials 194 Section 15 Schematics 199 15 1 Reference Board Component Placement 200 Section 16 Selected Component Data Sheets MPRHOSTSU 02 III PowerPc Figures Figure 1 603 604 Reference Design Block Diagram 20 Figure 2 Non Contiguous PCI Address Transformation 29 Figure 3 Non Contiguous PCI Address Translation 29 Figure 4 Contiguous PCI Address Translation 30 Figure 5 Typical External Register 51 Figure 6 DRAM Bank Organization 68 Figure 7 Synchronous SRAM 256K L2 69 Figure 8 Synchronous SRAM 512K L2 70 Figure 9 Synchronous SRAM 1M L2 70 Figure 10 Async
43. release 2 1 of the reference design requires the 604 to be actively cooled A fan sink was chosen to satisfy this requirement A high quality model with a larger than necessary thermal mass was chosen This will tend to reduce the rate and range of temperature changes of the 604 package once thermal management is implemented A Sanyo 109P5412H2026 was chosen and is bonded to the 604 package with thermally conductive adhesive Similar devices are expected to perform in a similar manner 11 2 1 1 604 Fan Sink Installation Fan Sink Se s lt Adhesive dot 604 Substrate Thermostrate Figure 40 604 Heat Sink Assembly The procedure for bonding the fan sink to the 604 package is as follows see Section 1 4 for a list of materials and resources 1 Dispense Loctite 384 dots on the 604 substrate using four dots located at the four ners ofthe flat pack see Figure 40 Maximize these dots but make sure that the Loctite does not contact the chip or the substrate leads 2 Place the Thermostrate material on the chip 3 Brush the activator onto the Loctite dots and within 15 20 seconds place the fan sink onto the flat pack Note that once the activator is applied to the 384 it will set up within 15 to 30 seconds Normally the activator is applied to the mating surface and not directly to the 384 However applying the activator directly onto the 384 ensures that the activa tor and the 384 are well mixed and that there
44. 0000h to 001F FFFFh Write or Write ROM Address Space Lockout Remote ROM PCI Memory Transaction to I O Bus 1G 2M to 1G 2 Bridge 3FE0 0000h to 3FFF FFFFh System memory can be cached Addresses from 2G to 4G are not cacheable Memory does not occupy the entire address space Registers do not occupy the entire address space Each page in the 8M CPU bus address range maps to 32 bytes in PCI I O space Registers and memory do not occupy the entire address space Accesses to un occupied addresses result in all one bits on reads and no ops on writes 6 A memory read of BFFF FFFOh generates an interrupt acknowledge transaction on the PCI bus Notes for Table 4 ool e 2 3 1 Address Mapping for Non Contiguous Figure 2 shows the address mapping that the 660 Bridge performs in non contiguous mode The I O map type register address 8000 0850h and the bridge chip set options 1 register index BAh control the selection of contiguous and non contiguous In non contiguous mode the 8M address space of the 60X bus is compressed into 64K of PCI ad dress space and the 60X CPU cannot create PCI addresses from 64K to 8M In non contiguous mode the 660 Bridge partitions the address space so that each 4K page is remapped into a 32 byte section of the O to 64K ISA port address space so that 60X CPU protection attributes can be assigned to any of the 4K pages This provides a flex 28 MPRH01TSU 02 P2
45. 3 4 5 6 7 Oo 61 2 3 5 REGHSINK DIP e MPRHO1TSU 02 Ref Des Ev U2 C109 110 1 C1 C2 C7 C11 C17 C22 C27 C38 C56 C112 C116 C121 C122 C165 C166 C170 C171 C175 C183 C187 C201 C207 C232 C234 C244 C249 2 1 FB1 FB2 FB4 FB6 6 4 5 4 38 37 Q6 Q7 DO NOT 22 23 6 1 2 4 U U U U U P U U U 1 5 MH7 MH8 Y 6 7 J 5 1 6 M 191 Manufac NONE DALLAS KEMET ALTERA DK BM BM 2 AAVID Manufac turer Part JE DEC_TYPE Number Part Description 2 SPRAGUE 293D107X9 SMC2816 CAPACITOR 6 R3D2T T491D336M O16AS B 5130 XQFP100 W 128 MACROCELLS QC 100 1 1 BERG 79282 516 CONN 2X8 PIN HEADER CONN 42F6867 1 IDT 74FC16237 SSOP48 16 BIT TRANS LATCH 5 HF50ACB 3 6 FERRITE BEAD 21611T 27 QFP240 5MM DATA MAPPING 8 BUFFER 82663 27 QFP208_5MM SYSTEMS amp MEMORY 82664 CONTROLLER DT71216S QFP80_ TAG RAM IDT71216 10 PF 65MM 2M 07712165 QFP80 TAG RAM IDT71216 10 PF 65MM 2M RFZ44 TO220X TRANSISTOR 50V 35A LINEARTECH LT1431CS8 VOLT REGULATOR LINEARTECH LT1431CS8 VOLT REGULATOR MOTOROLA 881 970 52 65MM CLOCK CHIP FA 14 31818M 0 1 SG 615P OSCSMT4 OSCLR 24 0000MC 2071 PLCC32SKT 32 PIN PLCC SOCKET RAYCHEM SMD100 POLYSWITCH TAPE RESISTOR 1 MOLEX
46. 603 604 Reference Designis no longer supported It is replaced by the 603e version of the 603 604 PowerPC Reference Design In this document the term 603 also refers to the Pow erPC 603e RISC microprocessor unless otherwise specified Power management is beyond the scope of this document Audience This reference design is designed for engineers and system designers who are interested in implementing PowerPC systems that are compliant with the PowerPC Reference Platform Specification The material re quires a detailed understanding of computer systems at the hardware and software level Reference Material Understanding of the relevant areas of the following documents is required for a good understanding of the reference design PowerPC 604 User s Manual IBM document MPR604UMU 01 PowerPC 604 Hardware Specification IBM document MPR604HSU 01 PowerPC 603 User s Manual IBM document MPR603UMU 01 PowerPC 603e Hardware Specification IBM document MPR603EHS 01 PowerPC 603e Technical Summary IBM document MPR603TSU 04 IBM27 82660 PowerPC to PCI Bridge User s Manual IBM document number MPR660UMU 01 PCI Local Bus Specification Revision 2 1 available from the PCI SIG PowerPC Reference Platform Specification Version 1 1 IBM document MPRPRPPKG The Power PC Architecture second edition Morgan Kaufmann Publishers 800 745 7323 IBM document MPRPPCARC 02 Intel 82378ZB System I O SIO Data Book Intel order number 2
47. Configuration Menu 10 4 3 2 Rum a Program ao e RR Gee tee eee dae ek AONE 10 4 3 3 Reprogram Flash 10 4 3 4 Exit Options 10 4 4 Default Configuration Values Section 11 Electromechanical 11 1 Electrical 11 1 1 Power Requirements 11 1 2 Onboard 3 3V Regulator ii 11 1 3 Onboard 2 5V Regulator mer ex wee RE US Rer 11 2 Thermal 11 2 1 Thermal Requirements for the 603 604 Processor 11 2 1 1 604 Fan Sink Installation 11 2 1 2 604 Fan Sink Experimentation 11 2 1 3 Thermal Requirements for the 3 3V Regulator 11 3 Mechanical 11 3 1 Reference Design Board 11 3 2 Connector Locations 11 3 3 Connector Locator Diagram 11 3 4 Keyboard Connector J14 1115229 Mouse Connector E MERI 11 3 6 Speaker Connector J13 11 3 7 Power Good LED KEYLOCK Connector J12 11 3 8 HDD LED Connector J11 1 2 Berg 11 39 Reset Switch Connector J10 1 x 2 Berg
48. DRAM Module Presence Detect Bit Encoding SRAM ID 2 0 SRAM Module Identification Ls o o 066 Ls o oe ee 6 3 8 L3 o 4 6 6 Planar ID Detection Register Revision information on the planar motherboard is buffered onto the X bus by U18 under control of the system I O EPLD 0852 lpzlpslpslpxlpslpzlprlpsl se ID Bits 7 0 Table 13 Planar ID Encoding Planar CPU CPU Internal Clock ID 7 0 CPU Bus Clock PCI Bus Clock 66 66 33 MPRHO2SCU 01 00 6036 99 66 33 MPRH02SCU 01 132 66 33 MPRH02SCU 01 48 MPRH01TSU 02 PowerPc ISA Bus 4 6 7 DRAM Presence Detection DRAM module presence and identification data is hard coded into the pinout of the SIMM or DIMM by shorting particular pins to ground or no connecting them on the SIMM itself The reference design uses U17 and 040 to buffer the presence detect bits from the DRAM sockets onto the X bus under control of signals from the system EPLD This information appears as the DRAM SIMM 1 2 Memory ID Register and the DRAM SIMM 3 4 Memory ID Register 4 6 7 1 DRAM SIMM 1 2 Memory ID Register 0880 Read Only This register indicates the ID bits associated with SIMMs 1 and 2 ioz os os o oo oe o oo ise SEHE MSB ID Bits 7 0 Bits 7 4 SIMM 2 ID bits See Table 14 Bits 3 0 SIMM 1 ID bits See Table 14 4 6 7 2 DRAM SIMM 3 4 Memory ID Registe
49. MNO 5 3 1 Fit File 5 3 2 TDF File Section 6 Memory Systems 61 DRAM 6 1 1 Refresh 6 1 2 DRAM Presence Detection 6 1 3 Organization 6 2 L2Cache 6 2 1 SRAM 6 2 2 TagRAM 02 3 12 Cache Configuration x ee eo Ct PE ie en 63 ROM 6 4 GPU ROM Transfers E x OA 6 4 1 OPUSC ROM Read OM 6 4 2 CPU to ROM Write 6 4 2 1 ROM Write Section 7 Endian Mode Considerations 7 1 What the 603 604 CPU Does 7 2 What the 660 Bridge BDOeSt a Gh 7 3 Bit Ordering Within Bytes 7 4 Byte Swap Instructions i 7 5 603 604 CPU Alignment Exceptions LE Mode 7 6 Single Byte Transfers s ln de ps 77 Two Byte Transfers 78 Four Byte Transfers 7 9 Three byte Transfers 7 10 Instruction Fetches Endian Modes 7 11 Changing Mode iios wes thes sace ea 7 12 Summary of Bi Endian Operation and Notes Section 8 Exceptions 8 1 Interrupts 8 1 1 System Interrupt Handler 8 1 2 Interrupt Handling MPRHOSTSU 02 PowerPc 8 1 3 Interrup
50. NI o gt lt gt n o gt gt i gt gt gt N AT a 150 MPRH01TSU 02 7 al P amp Electromechanical Table 51 ISA Connector Pin Assignments Continued a Be jso pa mw kb LIL NN CC mr s ED sm mr e p e C13 SD 10 013 DRQ6 S os rs De C17 0 14 017 MASTER j e MPRH01TSU 02 151 7 Electromechanical PowerPc 11 3 16 SIMM Connectors J21 J22 J23 and J24 Figure 54 SIMM Connector Pins are assigned as shown in Table 52 Table 52 SIMM Connector Pin Assignments 152 MPRHO01TSU 02 7 al P amp Electromechanical Table 52 SIMM Connector Pin Assignments Continued board Pin ol A AL 3 gt 8 J T N z 0 A o N lt EI MPRHO1TSU 02 153 Electromechanical Power Table 52 SIMM Connector Pin Assignments Continued 11 3 17 Power Switch Connector J8 Figure 55 1x2 Power Switch Connector Table 53 Power Switch Connector Pin Assignments
51. Net Lengths 7 lt a gt 10 Pe J evonRue Reference Board Tolerance neh or 2 sm L esre a s 660 s wek s erPerek a s ISAGHK Bs Shaves posse 12 3 CPU Bus Nets 1 The CPU bus nets shown in Table 59 are to be daisy chained Stubs and star fanouts are not allowed 2 The wiring order is U4 U33 U32 U5 U37 U38 and J3 3 Route nets so as to minimize noise reception Make these nets as short as possible Table 59 CPU Bus Nets D lt 63 0 gt DP lt 7 0 gt _60 ARTRY_60X BR_60X BG_60X SHD_6014 TS_60X XATS_60X TT lt 4 0 gt TSIZ lt 2 0 gt TBST_60X GBL_60X MPRHO1TSU 02 165 Physical Design Table 59 CPU Bus Nets Continued PowerPc DRTRY_60X TA_60X TEA_60X 12 4 Timing Critical Nets The timing of the nets shown in Table 60 is critical Make these nets as short as possible to reduce board delays as much as possible Table 60 Timing Critical Nets CKSTP_OUT_60X INT_60X DPE_60X MCP_6034 SMI_6034 ESP_TMS_60X ESP_TCK_60X ESP_TDI_60X ESP_TDO_60X HALTED RUN_NSTOP SRAM_ADS ADDRO SRAM_CNT_EN ADDR1 SRAM ALE SRAM WE SRAM_OE TAG_MATCH TAG_WE TAG_VALID TAG_CLEAR 166 MPRH01TSU 02 PowerPc Physical Design 12 5 PCI Bus Nets 1 The PCI bus nets shown in Table 61 are to be daisy chained Stubs and star fanouts are not allowed 2 The wiring o
52. Take care when writing device drivers to prevent these events 98 MPRH01TSU 02 PowerPc Exceptions 8 2 10 Special Events Not Reported as Errors MPRHO1TSU 02 99 A PCI to memory cycle at any memory address above that programmed into the top of memory register The 660 bridge ignores this cycle and the initiator master aborts No data is written into system memory on writes and the data returned on reads is indeterminate The bus master must be programmed to respond to a target abort by alerting the host CPU to PCI configuration cycles to which no device responds with a DEVSEL sig nal within 8 clocks no device at this address The data returned on a read cycle is all 1 s and write data is discarded This allows soft ware to scan the PCI at all possible configuration addresses and it is also consistent with the PCI specification A CPU read of the IACK address having a transfer size other than 1 or having other than 4 byte alignment These conditions return indeterminate data The ISA bridge requires the byte enables CBE 3 0 to be 1110 in order to place the data on the correct byte lane 0 Accesses other than one byte at the address BFFF FFFOh are undefined A read of the IACK address when no interrupt is pending A DEFAULT 7 vector is returned in this case This is the same vector that is returned on spurious interrupts Parity error in Flash ROM Parity is not stored in the Flash ROM Therefore the memory parity error
53. a 1M L2 is shown in Figure 14 16k x 15 TagRAM CPU ADDR 13 26 Address CPU ADDR 2 12 Data TAG_VALID Valid Match MATCH ic Figure 13 Synchronous TagRAM 512K L2 16k x 15 TagRAM CPU ADDR 13 26 Address CPU ADDR 2 11 Data TAG VALID 4 Valid Match TAG_MATCH CS Match Figure 14 Synchronous TagRAM 1M L2 72 MPRH01TSU 02 P2werPc Memory 6 2 3 12 Cache Configuration To implement the desired L2 configuration on the reference design refer to Table 18 Table 18 L2 Configuration Implementation Configuration Component Values Pus Tes em 8s ne 9 w 168 09 no pop R 169 no pop NT Q x R171 I 009 mm I 0 0 0 MPRHO1TSU 02 73 PowerPc 6 3 ROM The reference design uses an AMD AM29F040 120 Flash ROM to contain the POST and boot code It is recommended that Vital Product Data VPD such as the motherboard speed and native I O complement be programmed into in this device It is possible to pro gram the Flash before or during the manufacturing process 6 4 CPU to ROM Transfers The PowerPC Reference Platform Specification allocates the upper 8M of the 4G CPU ad dress space as ROM space The reference design implements
54. additional cooling and or additional space for I O cards The reference design is intended to help companies develop their own products using the PowerPC architecture The reference design may be used As a baseline system in order to gauge the effects of changes on the design To test new boot code To test operating systems and or applications For performance measuring The reference design is Acompliant implementation of the PowerPC Hardware Reference Platform Specifi cation version 1 1 Tested for functionality to the level of software available at the time of shipping Aprototype of a system under development which may have prototype ASICs erra ta and or wiring changes The reference design is not complete market ready design Tested for compliance to FCC and other regulatory requirements MPRH01TSU 02 PowerPc Introduction 1 3 Reference Design Overview This section contains an overview of the reference design The block diagram of the refer ence design is shown in Figure 1 The reference design is compliant with the PowerPC Reference Platform Specification Ver sion 1 1 The core of the system is the PowerPC 603 or PowerPC 604 RISC microprocessor The IBM27 82660 Bridge chipset 660 Bridge interfaces the CPU to the DRAM memory and provides L2 cache control for the tagRAM and SRAM components that are located on the CPU bus The 660 Bridge also inter
55. corresponding errata Release 2 1 has full functionality and is intended for limited release The schematic and the BOM match the actual release 2 1 reference board while the functional specification describes the expected operation of the final design The errata section describes the errata and wor karounds required for the release 2 1 reference board and details the differences between the actual operation of the release 2 1 board and the expected operation of the final design Release 3 0 of the reference design contains version 2 0 of the 660 Bridge chipset requires no workarounds and contains no errata Release 3 0 has full functionality has been guard band tested and is intended for general release The schematic and the BOM and the func tional specification all match the final release 3 0 reference board This document contains several references to the 603 604 Reference Design Power Man agement Specification which was not available at the date of printing of the reference de sign documentation 170 MPRH01TSU 02 PowerPc Errata 13 2 Release 2 1 Board Level Errata 13 2 1 Driving 32MB 72 pin DRAM SIMMs Release 2 0 of the reference design documentation incorrectly stated that up to 128MB of DRAM could be installed on the reference board To do so requires the use of four 32 72 pin devices which presents a greater load to the memory controller than is supported To drive four 32MB SIMMS requires the installation of buff
56. five thousand dollars 25 000 00 or its equivalent in your local currency and is without regard to the number of items in the Reference Design that caused the damage This limitation will apply except as otherwise stated in this Section regardless of the form of the action including negligence This limitation will not apply to claims by you for bodily injury or damages to real property or tangible personal property Inno event will IBM be liable for any lost profits lost savings or any incidental damages or economic consequential dam ages evenif IBM has been advised of the possibility of such damages or for any damages caused by your failure to perform yourresponsibi lities In addition IBM will not be liable for any damages claimed by you based on any third party claim Some jurisdictions do not allow these limitations or exclusions so they may not apply to you RISK OF LOSS You are responsible for all risk of loss or damage to the Reference Design upon its delivery to you IBM TRADEMARKS AND TRADE NAMES This Agreement does not give you any rights to use any of IBM s trade names or trademarks You agree that should IBM determine that any of your advertising promotional or other materials are inaccurate or misleading with respect to IBM trademarks or trade names that you will upon written notice from IBM change or correct such materials at your expense NO IMPLIED LICENSE TO IBM INTELLECTUAL PROPERTY Notwithstanding the fact that IB
57. for Contiguous I O In contiguous I O mode CPU addresses from 2G to 2G 8M generate a PCI I O cycle on the PCI bus with PCI AD 29 00 unchanged The low 64K of PCI I O addresses are for warded to the ISA bus unless claimed by a PCI agent Memory page protection attributes may only be assigned by 4K groups of ports rather than by 32 port groups as in the non contiguous mode This is the power on default mode Figure 4 gives an example of contiguous partitioning ISA I O 60X Address 8000 0000 8000 0001 8000 0002 8000 8000 Contiguous 603 604 addresses No gaps 8000 8000 FFFE EFEFEF Figure 4 Contiguous PCI I O Address Translation 23 3 PCI Final Address Formation The 660 Bridge maps 60X CPU bus addresses from 2G to 4G as PCI transactions error address register reads or ROM reads and writes The 660 Bridge manipulates 60X bus addresses from 2G to 4G to generate PCI addresses as follows e PCI_AD 31 30 are set to zero e PCI_AD 2 0 are unmunged if little endian mode is selected e After unmunging PCI_AD 1 0 are set to 00b except for PCI I O cycles 2 4 CPU to Memory Transfers The system memory address space is from 0 to 2G Physical memory does not occupy the entire address space When the CPU reads an unpopulated location the 660 Bridge re turns all ones and completes the transfer normally When the CPU writes to an unpopulat ed location the Bridge signals normal transfer completion to the CPU but does n
58. is greatly simplified and the multi processor capabilities of the 660 bridge are not used The remaining arbitration on the CPU bus is between the CPU and the snoop broadcasting logic in the 660 bridge Since the 660 bridge parks the CPU bus on CPU1 whenever the bus is idle CPU latency is mini mized One level of address bus pipelining is supported and most data writes are posted Precise exceptions are reported via TEA and imprecise exceptions are reported via MCP PIO or programmed transactions XATS type are not supported 2 1 1 603e CPU The 603e version of the reference design operates the 603e in 64 bit data bus mode The reference design is initially configured for DRT RY mode and can be reconfigured to no DRTRY mode by populating R440 0 ohm In DRTRY mode data is assumed to have been speculatively presented to the CPU and so is held for one clock in an internal CPU latch before being presented to the CPU data consumers In no DRTRY mode the data is assumed to be good when TA is sampled active so it is immediately forwarded without the delay cycle Use of this mode mainly speeds up reads from the L2 The 603 version of the reference design runs 81 3 2 6036 internal clock to bus clock ratio at 99MHz 66MHz CPU PLL_CFG 0 3 is set to 1100 On the 603e version of the reference board the following are populated R425 and R426 with 1k ohm resistors and R423 and R424 with with 10k ohm resistors The following are
59. is stored or fetched at the address presented on the PCI bus in either endian mode 78 MPRH01TSU 02 PowerPc Endian Modes The way the 660 Bridge implements the endian mode logic is conceptualized in Figure 15 Byte Swap Address and Unmunge 1 DO 0 PASS LE Mode Bit Port 92 Figure 15 Endian Mode Block Diagram 7 3 Bit Ordering Within Bytes The BE LE discussion in this section applies only to the ordering of bytes The LE conven tion of numbering bits the least significant bit having the lowest number within that byte is followed throughout the 603 604 Board schematics including the PCI bit numbering The only exception isthe CPU data and address buses these are numbered with BE nomencla ture The 603 604 CPU buses are connected to the 663 buffer buses with the significance ofthe bits maintained so that MSb connects to MSb and so on Note that the pin numbering convention on the 660 Bridge chip is BE at the CPU side and LE at the memory and PCI sides 7 4 Byte Swap Instructions The Power PC architecture defines both word and half word load store instructions that have byte swapping capability Programmers will find these instructions valuable for deal ing with the BE nature of this architecture For example if a 32 bit configuration register of a typical LE PCI device is read in BE mode the bytes will appear out of order unless the load word with byte swap instruction is used The byte
60. k MASK BR CLK PCI FRAME 664 OWN PCI for Errata 8 MPRHO1TSU 02 183 Errata 13 4 2 2 C3 PAL Design File TITLE C pds PATTERN none REVISION 1 0 COMPANY IBM DATE 07 31 95 CHIP _C2 PALCE16V8 Predefined PIN 1 CPU_CLK PIN 10 GND PIN 11 REG PIN 20 Inputs PIN 2 BG IN PIN 3 ABB PIN 4 BR PIN 5 MASK BG2 PIN 6 MASK 1 PIN 7 MASK BR PIN 8 DBB PIN 9 PCI GNT IN PIN 17 MASK BG3 outputs PIN 12 CPU 0 PIN 13 BR OUT PIN 18 PCI OUT PIN 19 BG OUT Internal Registers PIN 14 MASK PCI GNT PIN 15 DEL ABB PIN 16 DEL BG COMB COMB COMB COMB CLOCK GROUND PowerPc OUTPUT ENABLE FOR REGISTERED OUTPUTS INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT COMBINATIONAL COMBINATIONAL COMBINATIONAL COMBINATIONAL REG REGISTERED REGISTERED 184 MPRH01TSU 02 PowerPc EQUATIONS Output enables for Comb logic Reg OE s controllered by pin 11 CPU AO TRST ABB DEL ABB Equations for internal registers DEL BG BG IN DEL ABB ABB MASK PCI GNT MASK PCI GNT DBB PCI GNT OUT PCI GNT IN MASK PCI GNT BG OUT BG MASK 1 for MASK BG2 for MASK BG3 for CPU AO GND for BR OUT BR IN _ MASK BR for
61. mapped look aside level 2 cache that caches the low 1G of CPU memory space The reference design is initially configured to use a 512K synchronous SRAM module but can be configured to use 256K 512K or 1M module populated with either synchronous or asynchronous SRAM The L2 supplies data to the CPU bus on write hits and snarfs the data updates the data while the memory controller is accessing DRAM memory on read write misses It snoops PCI to memory transactions Typical synchronous SRAM read performance with 9ns SRAM is 3 1 1 1 followed by 2 1 1 1 on pipelined reads Typical asynchronous SRAM read performance with 15ns SRAM is 3 2 2 2 followed by 3 2 2 2 on pipelined reads For more information on the operation and capabilities of the L2 see the 660 Bridge User s Manual 6 2 1 SRAM As initially configured Figure 8 the reference design features a 512K synchronous SRAM SIMM A synchronous 256K SRAM module is shown in Figure 7 A synchronous 1M SRAM module is shown in Figure 9 It is also possible to use asynchronous SRAM modules with the reference design Figure 10 shows a 256K asynchronous SRAM module Figure 11 shows a 512K asynchro nous SRAM module Figure 12 shows a 1M asynchronous SRAM module 32k x 18 SRAM CPU ADDR 14 28 CPU DATA 0 63 CPU DPAR O0 7 Address Data Data CS CS Figure 7 Synchronous SRAM 256K L2 MPRH01TSU 02 69 Po
62. on reset state for the posted write buffer is disabled It is required that the posted write buffer be enabled Note that PCI burst transactions are not supported by the SIO For burst transactions the SIO will always target abort after the first data phase The system will not allow the CPU to burst to the SIO or any other PCI agent No PCI master should be programmed to at tempt burst transactions to the SIO The SIO defaults after power on reset to the slow sampling point bits 4 3 of the PCI Con trol Register for its subtractive decode Of the three choices for the sampling point slow 5 PCI cycles typical 4 PCI cycles and fast 3 PCI cycles one should be chosen that is one clock after the slowest I O device on the PCI bus If the PCI agents are all memory mapped above 16M Byte and all I O mapped above 64K then the fast sampling point for the subtractive decode can be chosen This insures that no other PCI agent except the SIO will claim these addresses Configure PCI agents in this manner to improve performance The SIO automatically inserts a 4 ISA clock cycle delay between PCI originated back to back 8 and 16 bit cycles to the ISA bus In addition the ISA Controller Recovery Timer Register configuration register address offset 4Ch enables a number of additional ISA clock cycles of delay to be inserted between these types of back to back I O cycles The ISA Controller Recovery Timer Register defaults after power on res
63. ply connector not by 030 Table 38 Specifications for 3 3V Regulator on the Motherboard Output Voltage 3 3 V 396 Output Current 0 01 Ato 5 A Input voltage 4 75 V to 5 25 V Pass element maximum case temperature 110 C In regulation lt 1ms after 5 reaches 4 75V No current mi feature 11 1 3 Onboard 2 5V Regulator There is an uninstalled 2 5 volt regulator 034 on the reference design to support possible future 604ev installation See Table 39 Table 39 Specifications for 2 5V Regulator on the Motherboard Specification Value Output Voltage 2 5 V 3 Output Current 0 01 Ato 5 A Input voltage 3 V to 5 25 V Pass element maximum case temperature 110 C In regulation lt 1ms after 5 reaches 4 75V No current imi feature 138 MPRH01TSU 02 Y al P amp Electromechanical 11 2 Thermal The most thermally active components are outlined in this section Designers should verify that the temperature limits of all component are not exceeded in their application 11 2 1 Thermal Requirements for the 603 604 Processor When the motherboard is operated in an open environment for testing a fan should be placed so that there is a good air flow over the 603 604 CPU at all times Enclosure design is up to the manufacturer It is likely that a fan will be required near the 603 604 CPU in order to meet the requirements of operating junction temperature equal to or less than 105 C Under some conditions
64. presence detect registers 9 6 ISA Bus Register Suggestions The following port assignments are designed to be compatible with the reference design firmware and Super I O type chips These registers and functions are not implemented on the reference design motherboard Table 35 Compatible ISA Ports Not on Reference Board ss Mode Addr Mode Addr 00001 000FO10 IOEPaa 800001F1 8000 F011 IDE EorFeatures faw 800001F2 80002012 IDE Sector Count 01F3 800001F3 8000 FOTS lDESecorNumbe 8000 01F4 8000 FO14 1 faw 6000 0125 8000 2015 IDECyinderHigh 0156 800001F6 8000FO16 DEDrveHead RW 800001F7 8000017 IDEStatusCommand faw 116 MPRH01TSU 02 PowerPc Setup Table 35 Compatible ISA Ports Not on Reference Board Continued Mode Addr Mode Addr 0279 80000279 80013019 Paraon T 27A 8000027A 8001301A ParalelPot2 278 80000278 8001301B ParalelPot2 27C 8000 0270 8001 301C ParalelPot2 8000027D 8001301D ParalelPot2 800002F8 80017018 SeralPon2 17 2F9 800002F9 80017019 SeralPot2 _ 8000 02FA 8001701A SeralPot2 7 2FB 800002FB 8001701B SeralPot2 8000 2 80017016 SerialPot2 8000 02FD 8001 7010 SerialPort2 CC pee o qe m p
65. swap instructions e hbrx load half word byte reverse indexed e wbrx load word byte reverse indexed sthbrx store half word byte reverse indexed e stwbrx store word byte reverse indexed The byte reverse instructions should be used in BE mode to access LE devices and in LE mode to access BE devices MPRHO1TSU 02 79 Endian Modes PowerPc 7 5 603 604 CPU Alignment Exceptions In LE Mode The CPU does not support a number of instructions and data alignments in the LE mode that it supports in BE mode When it encounters an unsupportable situation it takes an in ternal alignment exception machine check and does not produce an external bus cycle See the latest 603 604 CPU documentation for details Examples include e L MW instruction STMW instruction Move assist instructions LSWI LSWX STSWI STWX Unaligned loads and stores 7 6 Single Byte Transfers Figure 16 is an example of byte write data a at address XXXX Big Endian Little Endian 603 604 Swap Off Memory 603 604 Swap On Memory LSB Unmunge On Figure 16 Example at Address XXXX 80 MPRH01TSU 02 PowerPc Endian Modes Big Endian Little Endian 603 604 Swap Off Memory 603 604 Swap On Memory Figure 17 Example at Address XXXX XXX2 Figure 17 is an example of byte write data a at address XXXX XXX2 For single byte accesses to memory in BE mode Table 21 applies Table 21 Memory in BE Mode 603 603 603 663 604 6
66. the clocks to another clock driver output Cut these nets between the 664 and everything else Then connect the PALs to each side of the cut as shown For example cut the PCI FRAMEZ net at the 664 connect only the 664 PCI pin to the 664 FRAME pin of the HPP1 PAL and connect all other devices on the FRAME net to the PCI FRAME pin of the HPP1 PAL CPU CLK BROOM PAL 664 SRAM_OE SRAM_OE PCI_GNT_IN DBB ABB MASK_BG3 ABB MASK_BG3 DBB DBB AO AO C3 PAL BR BR_IN BR_OUT CPU_REQ1 BG BG_OUT BG_IN CPU_GNT1 PCI Arbiter CPU_GRANT PCI GNT INZ PCI_GNT_OUT PCI MASK BR MASK BG1 MASK BG2 PCI Bus PCI IN BR IRDY IRDY BG1 TRDY TRDY MASK BG2 STOP STOP FRAME PCI_FRAME 664_FRAME PCI_FRAME PCI CLK HPP1 PAL Tie p11 low on each PAL Figure 63 Generic Implementation PAL Installation 188 MPRH01TSU 02 P2werPc BOM Section 14 Bill of Materials 14 1 603 604 Reference Design Bill of Materials 14 1 1 603 Bill of Materials Table 64 603e Bill of Materials Part Name Part Ref Des Qty Manufac JE Part Description Number turer DEC_TYPE Part Number 10MQ040 SOIC 87F4917 CR1 CR7 SANKEN SFBP 54YL 40V 1A SCHTK REC 2 29F040ROM 8286496 1 A
67. the next partition in the chained list of partitions The last parti tion in the list is indicated with a system indicator value of zero in the second entry of its partition table MPRHO1TSU 02 121 Because of the DOS format limitations for a device partition a partition which starts at location beyond the first 1 gigabyte is located by using an enhanced format shown in Figure 27 Partition Begin 1 1 1 Partition End Sys Ind 1 1 1 Beginning Sector 32 bit start RBA zero based LE Number of Sectors 1 32 bit RBA count one based LE 1 All ones in the field Relative Block Address units of 512 bytes Figure 27 Partition Table Entry Format for an Extended Partition 10 3 1 3 PowerPC Reference Platform Partition Table Entry The Power PC Reference Platform partition table entry see Figure 28 is identified by the 0x41 value in the system indicator field All other fields ignored by the firmware except for the Beginning Sector and Number of Sectors fields The CV Compatible Value not shown fields must contain PC compatible values i e acceptable to DOS to avoid confus ing PC software The CV fields however are ignored by the firmware Partition Begin Sector Cyl Partition End Sys Ind Head Sector Cyl Beginning Sector 32 bit start RBA zero based LE Number of
68. transaction and supplies the 1 byte interrupt vector There is no physical interrupt vector BCR in the bridge Other PCI bus mas ters can initiate interrupt acknowledge transactions but this may have unpredictable ef fects 2 5 7 PCI Lock The 660 Bridge does not set PCI locks when acting as the PCI master The PCI LOCK signal in the 660 Bridge supports resource locking of one 32 byte cache sector block of system memory Once a PCI lock is established the block address is saved Subsequent accesses to that block from other PCI bus masters or from the CPU bus are retried until the lock is released The bridge generates a flush sector snoop cycle on the CPU bus when a PCI bus master sets the PCI lock The flush sector snoop cycle causes the L1 and L2 caches to invalidate the locked block which prevents cache hits on accesses to locked blocks If the L1 contains modified data the PCI cycle is retried and the modified data is pushed out to memory Note The 60X processors do not have bus locking functions Instead they use the oad reserve and store conditionalinstructions Iwarx and stwcx to implement exclusive access To work with the lwarx and stwcx instructions the 660 Bridge generates a flush sector op eration to the CPU in response to the PCI read that begins a PCI lock 2 6 CPU to ROM Transfers The PowerPC Reference Platform Specification allocates the upper 8M of the 4G CPU ad dress space as ROM space The reference design imp
69. 0172 C174 C208 C215 217 220 6227 C231 C233 C235 C243 C245 C248 251 279 ERG 1X2 100MIL HEADER VERTICAL 1X4 100MIL HEADER VERTICAL BERGSTICK 1X5 CAPACITOR ERG 9 BERG1X5 DIP CAPACITOR 0 001UF 20 104345 3 08055C102 KAT2A BERG1X5 SMC0805 2 CAPACITOR 0 01UF 20 0805X103M 2B05 SMC0805 CAPACITOR 22 CAPACITOR 0 1UF 20 23 CAPACITOR 10UF 20 CAPACITOR 2200PF 20 i Es Ea E E s CONN 41F0316 C43 C91 C92 C94 C100 C222 71F7911 C221 42G3220 C32 C83 C85 C123 MURATA C125 KYOCERA 0805Y104Z 1B05 TESVEC1C 106M12R GRM40XTR 222J050AD SMC0805 CAPACITOR 71F7911 CAPACITOR SMC0805 CAPACITOR z gt m lt 9 2 lt 194 MPRH01TSU 02 P2werPc BOM Table 65 604 Bill of Materials Continued Part Name Part Ref Des Qty Manufac Manufac JE Part Description Number turer DEC_TYPE Part Number 4 25 CAPACITOR 62G4724 C87 C90 KYOCERA 08055A680 5 68 20 2 C10 C16 C66 C98 16 NONE NONE 5 0805 DO_NOT_ POP 20 C99 C111 C149 150 152 154 156 216 226 27 CHANDRA SMD M 1 ALTERA 100 QFP 100QFP GTP W 128 MACROCELLS SOCKET 28 CONNDIN5 J14A 1 ONE NONE CONN_5DIN AT KEYBOARD DO CONNMDIN6 15F6890 J14 J15 2 MP 749180 1 CONN_ 6 POS CIRCU
70. 04 B BYTE MEM BYTE CAS YTE A31 30 29 add LANE LANE ACTIVE NOT Note At the CPU side MPRHO1TSU 02 81 Endian Modes PowerPc For single byte accesses to memory in LE mode Table 22 applies Table 22 Memory in LE Mode 604 604 BYTE BYTE MEM BYTE CAS A31 30 29 add LANE LANE LANE ACTIVE 0 0 0 0 0 MSB 0 7 0 1 6 0 0 2 5 1 5 3 al 5 2 6 1 6 2 4 3 2 1 1 1 Note At the CPU side For single byte accesses to PCI in BE mode Table 23 applies Table 23 PCI in BE Mode 604 604 BYTE BYTE PCI BYTE A D BE A31 30 29 add LANE LANE LANE 210 3210 O active byt nable 0 0 0 0 a O ol lt n 1 0 1 O 1 Qi 010 1 Q3 1 1 1 9i dq a 0 100 1110 1 5 ejo s m 4 af 1 RIO n wW Co NOT MUNGE NOT UNMUNGE Note At the CPU side 0 1 set to 00 for all PCI transactions except I O cycles 82 MPRH01TSU 02 PowerPpc For single byte accesses to PCI in LE mode Table 24 applies Endian Modes Table 24 PCI in LE Mode 603 603 663 604 BYTE BYTE PCI BYTE A D BE add LANE LANE LANE 210 3210 O active byt nable 0 lt n 00 n
71. 04 Swap Off Memory LSB LSB 6 Co 4 S h f 7 6 5 4 3 2 1 0 G 4 xx gt RO oN O O x g x x e X X h X g X f X e MSB Unmunge Off Figure 21 Wrong Instruction Read When Unmunger is used 7 11 Changing BE LE Mode There are two BE LE mode controls One is inside the 603 604 CPU and the other is a regis ter biton the motherboard The 603 604 CPU interior mode is not visible to the motherboard hardware The BE mode bit referred to in this document is the register bit on the mother board Itis a bitin space which is memory mapped just like other I O registers It defaults to BE mode The 603 604 CPU always powers up in the BE mode and begins fetching to fill its cache Consequently at least the first of the ROM code must be BE code It is beyond the scope of this document to define how the system will know to switch to LE mode However great care must be made during the switch in order to synchronize the internal and external mode bits to flush all caches and to avoid executing extraneous code The following process switches the system from BE to LE mode when used in this system Disable L1 caching Disable L2 caching Flush all system caches Turn off interrupts immediately after a timer tick so no timer interrupts will occur during the next set of cycles Mask all interrupts peg mc
72. 1 F012 Primary Floppy Digital Output 03F5 8000 03 5 03F7 3 3 8000 03F3 8001 F013 Floppy Digital Output Also Media Sense gt 444545884 MPRHO1TSU 02 117 Setup PowerPc Table 35 Compatible ISA Ports Not on Reference Board Continued Contiguous Non Contig Description R W Mode Addr Mode Addr 03F6 8000 03F6 8001 F016 IDE Alt Status Device Ctl 03F7 800003F7 8001 F017 IDE Drive Address R 03F8 8000 03F8 8001 F018 Serial Port 1 8000 03FA 8001 Serial Port 1 000 03F 03FD 8000 03FD sss SFB 8000 8001 FO1B SeralPot ge ian 1 This is preferred location for this function 118 MPRH01TSU 02 PowerPc Firmware Section 10 System Firmware 10 1 Introduction The firmware on the PowerPC 603 604 reference board handles three major functions Test the system in preparation for execution Load and execute an executable image from a bootable device and Allow user configuration of the system Section 10 2 briefly discusses the power on system test function Section 10 3 details a structure for boot records which can be loaded by the system firm ware Section 10 4 describes the system configuration utility To obtain a copy of the commented source code of the firmware on diskette contact you
73. 1 is implemented by using the corrected revision of the SCSI controller Errata 3 is not applicable since no CPU bus targets are used Errata 4 workaround is implemented by not executing ECIWX or ECOWX instructions Errata 9 workaround is implemented as suggested depending on the CPU family For 604 boards TT 2 connects between the CPU bus and the 664 and has no pull down resistors For 603e boards TT 2 is cut by not populating a jumper between the CPU and the 660 TT 2 CPU is pulled down using a 500 ohm resistor TT 2 660 is pulled down using a 500 ohm resistor 5 Errata 12 is not applicable since the 2 1 reference design uses revision 1 0 of the 663 which does not require the 100 ohm series resistor 6 Errata 14 is implemented in 604 designs by not installing pullup resistors on TT 0 4 On 603e reference designs TT 2 is connect as described in errata 9 and TT 0 1 3 4 have no pull up resistors 7 Errata 15 workaround is not comprehensive and involves changing ROM accesses from 1 byte reads to 4 byte reads Other workarounds are TBD 8 Errata 16 workaround is to not use PCI LOCKZ 9 Three PALs implement the remaining workarounds for the 660 bridge PAL HPP1 is located at M6 PAL is located at M7 PAL HBROOM is located at 8 Note that this set of PALs is used for both the 603e and 604 versions of the reference de sign 13 3 2 HPP1 Reference Design Workaround PAL This PAL is i
74. 12K throughout the ROM space Location 0 of the 512K ROM is mapped to CPU bus addresses 4G 2M 4G 1 5M 4G 1M and 46 5 The Flash is located on the PCI bus physically but not logically and is 8 bits wide This re quires the 660 Bridge to decode Flash address run 8 cycles to PCI bus without activating FRAME accumulate the 8 single bytes of read data into an 8 byte group and generate a TA and an to complete the cycle The CPU can also read the ROM using bursts but it receives the same 2 instructions from the ROM on each beat of the burst For more information see the 660 Bridge User s Manual Software can lock out the ROM using a 660 bridge BCR When the CPU writes to any ROM location while the ROM is locked out the bridge signals normal transfer completion to the CPU but does not write the data to the ROM The CPU bus write to the locked flash bit in the 660 bridge error status 2 register bit 0 in index C5h is set 2 6 2 to ROM Write Writing to Flash is another very specialized cycle Only one address FFFF FFFO is used for writing data to Flash The Flash address and data are both encoded into four bytes and written using a 4 byte write transfer Eight byte and burst transfers to the ROM are not sup ported See the 660 Bridge User s Manual Writes to Flash may be performed in either BE or LE mode The data byte swapper in the 660 Bridge is gated according to endian mode Writes in BE mode occur in natural se quen
75. 13 4 Note that due to physical design constraints the PALs used to implement the workarounds on the reference design are slightly different than those used to implement the workarounds on the generic system discussed in section 13 4 although the resulting logical function of both sets of PALs is identical Section 13 4 is exerpted from the 8 9 95 release of the 660 Bridge Revision 1 1 Errata Sum mary This section describes each of the 660 bridge errata the suggested workarounds and sample logic design files for PALs to implement the workarounds in a generic system 13 1 PowerPC 603 604 Reference Design Roadmap Table 63 shows the release roadmap for the reference design There are three releases expected for the 603 604 Reference Design 2 0 2 1 and 3 0 Each release consists of both a reference design consisting of the intangible design and the documentation thereof see section 1 1 and a reference board which consists of the actual populated circuit board Each release of the reference design contains functional specifications that describe the intended behavior of the final release 3 0 design the schematic and BOM of the current release and an errata section that details the functional and implementation differences between the current level and the final level MPRH01TSU 02 169 Errata PowerPc Table 63 PowerPC 603 604 Reference Design Roadmap Reference Board Level Circuit Board Level Release 2 0 2 0 Release
76. 1TSU 02 145 7 Electromechanical PowerPc 11 3 9 Reset Switch Connector J10 1 x 2 Berg Figure 47 1x2 Reset Switch Connector Table 45 Reset Switch Connector Pinno Sona Name 1 close to reset GROUND 11 3 10 Fan Connector J9 Figure 48 1x2 Fan Connector Table 46 Fan Connector Pin Assignments Pino Signal Name 12 VOLTS GROUND 146 MPRH01TSU 02 Y al P amp Electromechanical 11 3 11 3 3V Power Connector J5 plastic tabs Figure 49 1x6 3 3V Power Connector J5 Table 47 3 3V Power Connector J5 Pin Assignments me em OS 2 3 sr 00000 om E 6 _ 11 3 12 Power Connector J4 Top view 4 1 1 P2 plastic tabs Figure 50 1x12 Power Connector Table 48 Power Connector J4 Pin Assignments 6 feewp RUND T ON MPRHO1TSU 02 147 Y al Electromechanical Powerpe 11 3 13 AUX5 ON OFF Connector J6 Figure 51 AUX5 ON OFF Connector Table 49 AUX5 ON OFF Connector Pin Assignments Sonia O OS 11 3 14 PCI Connectors J25 J26 and J27 Figure 52 PCI Connector Pins are assigned as shown in Table 50 Table 50 PCI Connector Pin Assignments MPRH01TSU 02 I 7 al P amp Electromechanical Table 50 PCI Connector Pin Assi
77. 2 1 2 1 Release 3 0 3 0 IBM27 82664 Controller Level 1 0 1 1 1 2 IBM27 82663 Buffer Level 1 0 1 0 2 0 IBM27 82660 Chipset Level 1 0 1 1 2 0 Reference Board Function Limited Full Full Errata Quantity Significant Limited None Intended Customer Availability Reference Design Documentation Level IBM Internal Use Release 2 0 Limited Release 2 1 General Release 3 0 3 0 2 0 Reference Board Release 2 0 Errata and Workarounds 3 0 2 1 Reference Board Release 2 1 Errata and Workarounds Functional Spec Level BOM and Schematic Level Errata Section Content Release 2 0 of the reference design contains version 1 0 of the 660 Bridge chipset and requires a significant quantity of workarounds for the corresponding errata Release 2 0 has limited functionality and is intended for IBM internal use The schematic and the BOM match the actual release 2 0 reference board while the functional specification describes the expected operation of the final design The errata section describes the errata and wor karounds required for the release 2 0 reference board and details the differences between the actual operation of the release 2 0 board and the expected operation of the final design Likewise release 2 1 of the reference design contains version 1 1 of the 660 Bridge chip set and requires a limited quantity of workarounds for the
78. 245 2 PANASONIC ERJ6GVYJ 5 0805 RESISTOR 510 5 511S 88 RESISTOR 09G9165 R66 R78 R244 14 PANASONIC ERJ 3VKF SMC0603 RESISTOR 54 9 1 54R9S RESISTOR 61F2960 R63 1 PANASONIC ERJ6GVJ SMC0805 RESISTOR 620 5 621S RESISTOR 75 5 61F2961 R79 R359 R361 PANASONIC ERJ6GVJ SMC0805 RESISTOR 750S 1 RESISTOR 40G6887 1 PANASONIC ERJ 6VNF 0805 RESISTOR 80 6 1 80R6S RESISTOR R121 R146 R149 35 NONE NONE SMC0805 RESISTOR DO_NOT_POP5 R152 R168 R170 R172 R179 R185 R186 R189 R191 R193 R198 R382 R383 R385 R417 R419 R422 R427 R428 R440 R441 R443 R447 R466 R467 R477 R478 93 RLS4148 SOIC 87F4920 ROHM RLS4148 MELF 40V 1A SCHTK REG 94 RPAC24_1 33 5 RP1 RP3 RP7 RP9 CMD PRN 110 QSOP24 RESISTOR RP10 2433 ROJ 95 S82378ZB SMD 82G6542 1 INTEL S82378ZB QFP208 5MM PCI TO ISA BRIDGE CONT XTAL 16 50MHZ 89G3833 1 ECLIPTEK 2900 CLP_XTAL 16 5 MHZ CRYSTAL 16 500MHZ TAL DO NOT POP NONE NONE NONE CLP XTAL NONE PART CPUHSINK 6567199 THERMAL 2330B XLOOSE CPU HEAT SINK LOY 604 8185187 1 AMD PALCE16V8 XPLCC20 PROGRAMMED PAL H 5 PLCC20 100 X PART HPP 8185187 1 AMD PALCE16V8 XPLCC20 PROGRAMMED PAL H 5 PLCC20 101 THERMOSTRATE 1 POWER AL 079 079 DEVICES HEAT SINK INTERFACE MATERIAL MPRHO1TSU 02 193 BOM 14 1 2 604 of Materials Manufac turer on Pc Power Pr Table 65 604 Bill of Materials P
79. 27 Firmware PowerPc System Information The system configuration option shows the hardware configuration of the system at power up including processor installed options and firmware revision level A sample screen is shown in Figure 33 PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved System Configuration System Processor PowerPC 604 Installed Memory 8 MB Second Level Cache Not Installed Upgrade Processor Not Installed Boot Firmware Revision 1 0 Go to Previous Menu Press to select item Press Enter to perform action Figure 33 System Information Screen 128 MPRH01TSU 02 PowerPc Firmware Configure I O Devices The configure I O devices option allows the customization of system I O ports and the sys tem console The menu is shown in Figure 34 Options are highlighted by using the up and down arrow keys on the keyboard and are changed with the left and right arrow keys Op tions on the menu are discussed below PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved Device Configuration Select Console Device S3 Video Keyboard Set Serial Port 1 Speed 9600 Baud Set Serial Port 2 Speed 9600 Baud Go to Previous Menu Press T to select item Press to change item Figure 34 Device Configuration Screen Any changes made device configuration a
80. 3 PANASONIC ERJ 6GVYJ 5 RESISTOR 2 7K 5 272 75 RESISTOR 4096920 R459 1 PANASONIC ERJ 6VNF 5 RESISTOR 200 1 2000S 76 RESISTOR 22 5 9851736 R5 R6 R8 R10 R17 37 PANASONIC ERJ6GVYJ2 5 RESISTOR R33 R44 R88 R101 20S R109 R111 R113 R 175 R177 R178 R19 5 R197 R208 R511 4 0 77 RESISTOR 6122952 2 1 ERJ6GVJ22 5 RESISTOR 220K 5 s 8 RESISTOR 40G7233 R437 1 PANASONIC ERJ6VNF24 5 RESISTOR 249 1 90 9 RESISTOR 4203067 R120 1 PANASONIC ERJ6GVYJ3 5 RESISTOR 3 9K 5 92 RESISTOR 98F1674 R103 R106 R180 15 ROHM MCR10EZH 5 0805 RESISTOR 300 5 R181 R183 R225 MJW301 R236 R241 R251 R281 R286 192 MPRH01TSU 02 P2werPc BOM Table 64 603e Bill of Materials Continued Part Name Part Ref Des Qty Manufac Manufac JE Part Description Number turer DEC_TYPE Part Number 81 RESISTOR 33 5 41F0327 R83 R84 R86 R104 12 PANASONIC ERJ6GVYJ3 SMC0805 RESISTOR R105 R114 R226 30S R229 R243 R250 82 RESISTOR 33 603 09G9165 R187 R188 2 PANASONIC ERJ 3VKF 5 0603 RESISTOR 54R9S RESISTOR 41F0336 R231 R235 R273 15 PANASONIC ERJ 6GVJ 5 0805 RESISTOR 4 7K 5 R279 R460 R462 472S R469 84 RESISTOR 4067034 864 1 PANASONIC ERJevNF 5 0805 RESISTOR 4 99K 1 4991S RESISTOR 03G9709 R124 1 ROHM MCR10 SMC0805 RESISTOR 470K 5 EZHLJW47 4 RESISTOR 98F1737 R352 R358 7 PANASONIC ERJ6GVJ SMC0805 RESISTOR 5 6K 5 562S 87 RESISTOR 4170331 R118 R
81. 4 CPU bus clocks 16 CPU clocks for 32 bytes of data Pipelined burst write 5 4 4 4 CPU bus clocks 17 CPU clocks for 32 bytes of data Memory access performance from the PCI bus at 33MHz with 70ns DRAM is typically Read bursts 5 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 e Write bursts 5 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 3 5 PCI Bus The 660 Bridge includes the interface between the PCI bus and the rest of the system The reference design allows CPU to PCI access and PCI bus master to memory access with snooping and handles all PCI related system memory cache coherency issues Three PCI expansion slots are provided The reference design also supports memory block locking types 0 and 1 configuration cycles and ISA master access to system memory thru the ISA bridge 1 3 6 Flash ROM The reference design uses an AMD AM29F040 120 Flash ROM to contain the POST and boot code It is recommended that Vital Product Data VPD such as the motherboard speed and native I O complement be programmed into in this device It is possible to pro gram the Flash before or during the manufacturing process After power on the initial code fetched is supplied from this device The 660 Bridge man ages ROM access and control The reference design supports a 512K Flash 1 3 7 ISA Bus The ISA bridge function is provided by an Intel 82378ZB chip SIO It provides a PCI to ISA bus bridge
82. 4 Timing Critical Nets a 5 VERE ORMeD LE QI 166 12 5 IPGI BUS NETS n entr a I 167 12 6 Group 2A Noise Sensitive Wires 167 12 7 8mm Tape Contents and Extract Instructions 168 12 71 Download Instructions REID OPERIS 168 12 7 2 Cadence Version 168 12 753 Tape Contents oe sac sy furi e peers DES 168 Section 13 Errata for Reference Design Release 2 1 169 13 1 PowerPC 603 604 Reference Design Roadmap 169 13 2 Release 2 1 Board Level Errata 171 13 2 1 Driving 32MB 72 DRAM SIMMs 171 13 2 2 CPU Data Bus 33 Ohm Series Resistors 171 13 3 Reference Design Errata for Revision 1 1 of the 660 Bridge 172 13 3 1 Workaround Implementation 172 13 3 2 HPP1 Reference Design Workaround PAL 172 13 3 3 HCn Reference Design Workaround PAL 173 13 3 4 HBROOM Reference Design Workaround PAL 175 13 4 660 Bridge Revision 1 1 Errata 8 9 95 Release 177 13 4 1 Individual 66 Bridge Errata 177 13 4 2 PAL Design FileS RE EEE 182 19 4 2 T HAPPI Design
83. 5 RESISTOR 12 7 1 1272 72 RESISTOR 98F1671 R123 1 ROHM MCR10EZH 5 RESISTOR 150 5 MJW151 RESISTOR 1K 5 41F0333 R20 R51 R62 R100 20 PANASONIC ERJ6GVJ SMC0805 RESISTOR R173 R230 R239 102S R280 R386 R393 R418 R425 R426 R428 R435 R451 R464 R470 R479 R505 74 RESISTOR 0969748 R3 R261 R272 13 PANASONIC ERJ 6GVYJ 5 RESISTOR 2 7K 5 272 75 RESISTOR 4096920 R459 1 PANASONIC ERJ 6VNF 5 RESISTOR 200 1 2000S RESISTOR 22 596 98F1736 R5 R6 R8 R10 R17 38 PANASONIC ERJeGVYJ 5 RESISTOR R33 R44 R88 R101 220S R109 R111 R113 R175 R177 R178 R195 R197 R208 R511 77 RESISTOR 61F2952 R122 1 PANASONIC ERJ6GVJ 5 0805 RESISTOR 220K 5 224S ESISTOR 40G7233 R437 1 ERJ6VNF SMC0805 RESISTOR 2490S ESISTOR 42G3067 R120 1 PANASONIC ERJeGVYJ 5 RESISTOR 9K 5 392S RESISTOR 98F1674 R103 R106 R180 15 SMC0805 RESISTOR 300 5 R181 R183 R225 R236 R241 R251 R281 R286 81 RESISTOR 33 5 41F0327 R83 R84 R86 R104 12 PANASONIC ERJeGVYJ 5 RESISTOR R105 R114 R226 330S R229 R243 R250 2 83 09G9165 R187 R188 2 PANASONIC ERJ 3VKF SMT0603 RESISTOR 54R9S RESISTOR 41F0336 R231 R235 R273 15 PANASONIC ERJ 6GVJ 5 RESISTOR 4 7K 5 R279 R460 R462 472 469 84 RESISTOR 4097034 R64 1 PANASONIC ERJ6VNF SMC0805 RESISTOR 4 99K 1 4991S 85 RESISTOR 0369709 R124 1 ROHM MCR10 SMC0805 RESISTOR 470K 5 EZH LJW474 MPRHO1TSU 02 197 BOM P2werPc Table 65
84. 5 oz Fiberglass lt Epoxy 777771 Resin BAI dimensions in inches to ground impedance 70 10 0 Finished signal trace width 0 00425 Overall thickness 0 060 after plating 0 062 PPlating 7070 Figure 61 PowerPC 603 604 Board Fabrication MPRHO1TSU 02 163 Physical Design PowerPc 12 1 2 General Wiring Guidelines 1 Apower ground or voltage plane split occurs where there is a discontinuity in the plane As shown Figure 62 route wires across splits in a power plane in the most perpendicu lar manner possible Do not run wires parallel to the split in close proximity to the split Figure 62 Power Plane Split 2 Minimize the number of wires on the top surface of the board that cross under the clock generator Do not run any wires close to the crystal connections 3 If a wire is routed near a via which is part of a clock net there must be at least one vacant wiring channel between the wire and the clock via 4 Several groups of nets require special attention to ensure correct system operation They are listed below in order of the importance of meeting the design rules that are sug gested for that group For example ensuring that the clock nets are routed according to the design rules suggested in section 12 2 is more important than ensuring that the PCI bus nets are routed according to the design rules suggested in section 12 5 The ideal system design will
85. 50 C Atthe spe cified maximum current of 5A the heat sink assembly combination provided results in an assembled of 2 44 C watt Assembled 8 is such that in operation the case of the pass element must be maintained at or below 110 C under any use condition combination of ambient temperature altitude air flow or system configuration Any change in heat sink type style manufacturer or bonding technique epoxy glue etc may alter the and should be investigated to insure that the specified operating case temperature of 110 C is not exceeded 140 MPRH01TSU 02 Y al P amp Electromechanical 11 3 Mechanical 11 3 1 Reference Design Board Mechanical elit 8X 23 99 0 Ge 8 60 212 75170 66 o 6 0 0 5 697 0 dAl66 l s C 3E 99711 Dle Are HI E t 8 e Sie Hw S S iD 4 2 a HG H H H H BH Fd 1 D 33 1 5 e 24 p 3 1 E Ol lt HI H 2 wl 2 uh LD m ps2
86. 6 C66 C98 14 NONE NONE SMC0805 CAPACITOR C99 C111 C149 150 152 154 C156 C216 C226 1 ALTERA 100 QFP 100QFP GTP W 128 MACROCELLS SOCKET 1 NONE NONE CONN 5DIN AT KEYBOARD CONNECTOR 1 MOLEX 15 48 0212 CONN 1 12 0 156 CL FRET LCK 55X8085 HDR 1 BURNDY GTC6R 1 CONN 1X6 1X6 0 156 CL FRET LCK HDR 1 BURNDY ELP2X80S CONN_ 160 PIN CELP CONN C3Z48 DIMMSRA 645169 4 ISA2X49 2X49 ISA CONNECTOR 646255 1 PCI2X605V 2X60 32 BIT PCI CONNECTOR 822032 4 SIMM72 72 PIN SIMM CONNECTOR 1 EPSON 405 XTALSMT1 CRYSTAL 32 768KHZ 6PF ONE NONE XTALSMT2 CRYSTAL 190 MPRH01TSU 02 J4 5 3 gt lt lt Y DO_NOT Y POP 3 2 S6 S4 S3 PowerPc BOM Table 64 603e Bill of Materials Continued Part Name Part Number DO NOT POP_ PLCC28 PLCC28 DS1385 SMD 70G6764 ELCAP 100UF 75G8253 10 16 ELCAP 33UF 57G9281 20 16V EPM5130FP SMD ESP_CONN CONN 42F6867 162373 162373 F_BEAD BEAD 26F 4865 IBM82663 SMD 94G0235 IBM82664 SMD 94G0176 IDT71216 DO POP IDT71216 05H1054 IDT71216 IRFZ44 SMD 03G9500 LT1431REG 31F2428 LT1431REG 31F2428 DO_NOT_POP MC88LV970 DIP 05H1509 DO_NOT_POP OSCLR 87F5263 14 3181MHZ OSCLR 24 0MHZ 87F5265 PALCE16V8 SKT 19G5840 SKT PLCC32SKT SMD 10G7624 POLYSWITCH SMD 3493113 POWER1X3 DIP 65G3724 NONE 42 43 4 46 7 8 0 2
87. 60 0 3970 62 97 791 gt 99 5 22 171 GSE 9 227216 MPRHO1TSU 02 141 Y al Electromechanical PowerPc 11 3 2 Connector Locations Seg 8 lle 2 8 28 Ole 52178 9g 7902 0717 6v 1 07177 vec 281 6 6 F 122911 87776 50 T 1721 EA 8 8 K C H he gt luaa T ga 1 2113 gt 5 mo INN JI G aeea x Hd s es m jl lt al 10 e I ajo m X 3 5 5 gt CN r ml 59 5870 7688 Sl 12 62 5671 e x3 SS 6 G 58 69 SS 21706 29677 907921 29 75 827971 295 9 17991 5077 10 61 poll 115130 76 181 68177 97281 Sh Z 2 691 5877 142 MPRH01TSU 02 Y al P Electromechanical 11 3 3 Connector Locator Dia
88. 60 bridge enables its PCI AD drivers and drives the address onto the PCI AD lines for one PCI clock before it asserts PCI FRAME Predriving the PCI AD lines for one clock before asserting PCI_FRAME allows the IDSELs to be resistively connected to the PCI 0 31 0 bus at the system level The transfer size must match the capabilities of the target PCI device for configuration cycles The reference design supports 1 2 3 and 4 byte transfers that do not cross a 4 byte boundary Address unmunging and data byte swapping follows the same rules as for system memory with respect to BE and LE modes of operation Address unmunging has no effect on the CPU address lines which correspond to the IDSEL inputs of the PCI devices 2 5 5 1 Preferred Method of Generating PCI Configuration Transactions The preferred method for generating PCI configuration cycles is via the 660 Bridge indexed Bridge Control Registers This configuration method is described in section 4 of the 660 User s Manual The IDSEL assignment and their respective PCI AD lines are shown in Table 5 The addresses used for configuration are assigned as shown in Table 5 2 5 5 2 650 Bridge compatible method If itis not possible to use indexed BCRs to generate PCI configuration cycles they can be generated by an alternate method known as the 650 bridge compatible method CPU ac cesses to the address range 2G 8M to 2G 16M cause the bridge to arbitrate for the PCI bus and then to e
89. 705 43 003 POWER1X3 AUX POWER 7 CONNECTOR 533402B 21552 REGHSINK HEATSINK VOLTREG BOM P2werPc Table 64 603e Bill of Materials Continued Part Name Part Ref Des Qty Manufac Manufac JE Part Description Number turer DEC TYPE Part Number RESISTOR 0 5 98F1665 R18 R21 R32 R45 40 PANASONIC ERJ8GVJO 5 RESISTOR R46 R52 60 R171 R R207 R438 R439 R444 R446 R448 R449 R463 R465 R474 R476 R482 R484 67 RESISTOR 98F1741 R436 1 ROHM MCR10EZH 5 0805 RESISTOR 1 5K 5 LJW152 RESISTOR 10 596 58F1831 R82 R85 R87 R89 7 PANASONIC ERJ6GVYJ1 5 RESISTOR R96 R97 R429 00S RESISTOR 41F0328 R176 R238 R240 10 PANASONIC ERJ6VJ101 5 RESISTOR 100 5 R472 S 3 RESISTOR 41F0337 R1 R2 R4 R7 R19 182 PANASONIC ERJ6GVJ10 5 RESISTOR 10K 5 R47 R50 R61 R80 S R81 R90 R93 R95 R102 R107 R108 R119 R138 R145 R147 R148 R155 R166 R174 R237 R253 R255 R257 R260 R287 R351 R364 R368 R376 R378 R381 R384 R387 R392 R394 R397 R399 R401 R403 R416 R423 R424 R430 R434 R452 R461 R468 R471 R473 R475 R488 R495 R497 R510 71 RESISTOR 40G7066 R65 1 PANASONIC ERJ 6VNF 5 RESISTOR 12 7 1 1272 RESISTOR 98F1671 R123 1 ROHM MCR10EZH SMC0805 RESISTOR 150 5 MJW151 RESISTOR 1K 5 41F0333 R20 R51 R62 R100 19 PANASONIC ERJ6GVY SMC0805 RESISTOR R173 R230 R239 272S R280 R386 R393 R418 R425 R426 R435 R451 R464 R470 R479 R505 74 RESISTOR 0969748 R3 R261 R272 1
90. 90473 004 The following documents are useful as sources of tutorial and supplementary information about the reference design PowerPC System Architecture Tom Shanley Mindshare Press 800 420 2677 IBM27 82650 PowerPC to PCI Bridge User s Manual IBM document number MPR650UMU 01 Document Conventions Kilobytes megabytes and gigabytes are indicated by a single capital letter after the numeric value For exam ple 4K means 4 kilobytes 8M means 8 megabytes and 4G means 4 gigabytes The terms DIMM and SIMM are often used to mean DRAM module Hexadecimal values are identified where not clear from context with a lower case letter h at the end of the value Binary values are identified where not clear from context with a lower case letter b at the end of the value In identifying ranges of values from and to are used whenever possible The range statement from 0 to 2M means from and including zero up to but not including two megabytes The hexadecimal value for the range from 0 to 64K is 0000h to FFFFh The terms asserted and negated are used extensively The term asserted indicates that a signal is active logically true regardless of whether that level is represented by a high or low voltage The term negated means that a signal is not asserted The symbol at the end of a signal name indicates that the active state of the signal occurs with a low voltage level MPRHOSTSU 02 15 PowerPc MPRHOSTSU 02 PowerPc Introductio
91. AL goes to from PCI bus PIN 13 664 FRAME COMB COMBINATIONAL goes to from Kauai PIN 19 MASK BR COMB COMBINATIONAL goes to H603C PAL Internal Registers PIN 14 664 OWN PCI REG REGISTERED PIN 15 DEL PCI FRAME REG REGISTERED PIN 16 MASK BGO REG REGISTERED goes to H603C PAL PIN 17 MASK BG2 REG REGISTERED goes to H603C PAL PIN 18 MASK 1 REG REGISTERED 182 MPRH01TSU 02 PowerPc Biati EQUATIONS Output enables for Comb logic 5 controllered 11 PCI_FRAME_ TRST 664_OWN_PCI 664 FRAME TRST 664 OWN PCI Combinational and registered equations DEL PCI FRAME FRAME 664 OWN PCI PCI PCI FRAME IRDY 664 OWN PCI PCI FRAME IRDY PCI FRAME 664 FRAME Errata 2 664 FRAME PCI FRAME PCI DEL PCI FRAME Errata 2 k k k k k k k k k eee k k k k k MASK BG2 PCI FRAME IRDY TRDY STOP_ Errata 5 MASK 2 MASK 5 BG2 5 MASK 1 PCI FRAME IRDY TRDY STOP_ Errata 5 MASK BG2 MASK 1 MASK BGO MASK 1 MASK BGO BGO PCI FRAME IRDY TRDY STOP_ Errata 5 MASK BG2 MASK BGO MASK 1 MASK BGO k k k k k k k k k k k
92. A_REFRESH signal to refresh ISA bus memory Refer to the SIO data book for more information 6 1 2 DRAM Presence Detection The reference design includes a method for software to detect and identify installed DRAM modules using the presence detect bits PD 15 0 See section 4 6 7 MPRHO1TSU 02 67 PowerPc GND Presence Detect Bits 00 31 2 SIMM 2 PD3 CASO CAS1 CAS2 CAS3 WE Data amp Par Data amp Par D 32 64 Figure 6 DRAM Bank Organization 6 1 3 Organization The 4 byte DRAM modules SIMMs are arranged in pairs to form 8 byte memory banks as shown in Figure 6 Each socket supports a 32 bit non parity or a 36 bit 4 data bytes plus 4 parity bits DRAM SIMM Bank 0 is composed of SIMM 1 and SIMM 2 Bank 1 is com posed of SIMM 3 and SIMM 4 The 2 SIMMs in each bank must be the same size Combining the internal organization of the SIMMs found the respective data sheets with the bank organization of Figure 6 shows that each parity bit is accessed with the associated data byte The 660 bridge uses this standard organization for either parity or ECC mode operation 68 MPRH01TSU 02 P2werPc Memory 6 2 L2 Cache The reference design supplies an L2 cache controller located inside the 660 Bridge chip set The motherboard provides a socket for an SRAM module and the L2 tag RAM two 16K x 15 synchronous devices is supplied installed on the board The L2 is a unified write thru direct
93. CO w O O 8 5 2 lt gt 5 5 2 lt B z lt X 5 108 MPRH01TSU 02 PowerPc Setup Table 33 Combined Register Listing Continued Mode Addr Mode Addr To 6 007A m 078 80000078 8000 301B BIOSTimer SSC RW 080 W 081 80000081 80004001 DMA Channel 2 Register RW W 80000083 8000 4003 DMA Channel 1 Register RW 8000 0084 8000 4004 W 85 80000085 8000 4005 DMA Register Reserved RW 86 8000 0086 80004006 Register Reserved RW 087 8000 0087 8000 4007 WI 088 80000088 8000 4008 DMA Page Register Reserved RW 8000 0089 8000 4009 wl 8000 008A 8000 400A Channel 7 Page Register RW 0088 8000 0088 4008 W 08C 8000 0080 8000 4000 Register Reserved 080 8000 0080 8000 4000 WI 08E 8000008 8000 400E DMA Page Register Reseved RW 08F 8000 008F 8000 400F W 90 80000090 80004010 Page Register Reseed RW 092 8000 0092 wl 5000 0094 8000 4014 Register Reserved RW ELM s med s ELM r ko o
94. CSO amp XIOR S he he KKK he he he he he k k he he e e lt Write Power Control Register 1 1 0 address 082 MSB Bits 7 5 Reserved Bit 4 Strobe Key W O Bits 3 1 Data Command B 3 1 to 83C750 W O LSB Bit 0 830750 DO R W S he he he he he lt S5 830 08 1 7 6 8 A 5 8 4 8 3 8 2 A 1 8 GPCSO PWR REG1 STRB 830 CS amp AO0 5 Write ZERO to 83C750 RWD0_STRB PWR REG1 STRB amp XIOW amp XD 0 RWDO TRI GND RWDO STRB 83C750 I O Strobe Key 5 IO STROBE XD 4 amp PWR REG1 STRB amp XIOW amp PROC RDY amp 83CX RESET IO CHRDY TRI GND IO STRB he he he he he he e e Write Power Control Register 2 1 0 address 082B MSB Bit 7 CPU1 ROM Completed R
95. Disk Active Light W R Read Power Control Register 1 address 082 MSB Bits 7 1 Reserved LSB Bit 0 83C750 W R Read Power Control Register 2 I O address 082B MSB Bit 7 CPU1 ROM Completed Reset by RESET R W Bit 6 Reserved Bit 5 Bit 4 Reserved Bit 3 IRQ12 Mask Reset by RESET W R Bits 2 1 158 Bit 0 83C750 Status R O lt he he he he he ke k k S XD TRI LIGHT STRB PWR STRB REG2 STRB CLKFF_STRB amp XIOR 0 TRI D 0 XD TRI OE D 0 HDD LEDFF amp LIGHT STRB RWDO amp PWR STRB PROC RDY amp CMD STATE amp PWR REG2 STRB CLKFF 0 q amp CLKFF SELL CLKFF 8 q amp CLKFF SELH MPRHO01TSU 02 65 EPLD XD 1 D 1 XD 2 D 2 XD 3 D 3 XD 4 D 4 XD 5 D 5 XD 6 D 6 XD 7 D 7 END TRI D 1 XD TRI OE CLKFF 1 q amp CLKFF SELL CLKFF 9 q amp CLKFF SELH TRI D 2 XD TRI OE CLKFF 2 q amp CLKFF SELL CLKFF 10 q amp CLKFF SELH TRI D 3 XD TRI OE PWR REG2 1 q amp PWR REG2 STRB CLKFF 3 q amp CLKFF SELL CLKFF 11 q amp CLKFF SELH TRI D 4 XD TRI OE CLKFF 4 q amp
96. E OR LE 603 604 X or 110 Target CAS 0 7 PCI CBE ADDR add a29 31 Add a29 31 bytes 0 7 AD2 3210 0 0 000 110 0 1 0011 1111 J E E 1001 1111 010 100 2 3 1100 1111 0011 2 3 1110 0111 0 7 0 4 0 5 1E 3E 1E 0 1 1 5 1111 1001 5 6 6 110 000 6 7 1111 1100 0011 7 N E NNNN NNNN Notes N not emitted by 60X because it crosses 8 bytes transforms to 2 singles in BE machine CH in LE P not allowed on PCI crosses 4 bytes E causes exception does not come out on 603 604 bus in LE mode Table 26 contains the same information as found in Table 25 but it is arranged to show the CAS and PCI byte enables that activate as a function of the address presented at the pins of the 603 604 and as a function of BE LE mode Table 26 Rearranged 2 Byte Transfer Information 2 BYTE XFERS BE BE LE LE 60X ADDRESS PINS CAS 0 7 PCI CBE CAS 0 7 PCI CBE 0 000 0011 1111 1100 11 1100 0 0 E NNNN NNNN 1100 1111 0 O11 1110 0111 0 4 1 1111 0011 1 1 1 1111 1001 1001 10 0111 110 1111 1100 0011 011 111 NNNN NNNN 1 1 1 0 0 0 0 Notes N not emitted by 60X because it crosses 8 bytes transforms to 2 singles in BE machine CH in LE P not allowed on PCI crosses 4 bytes E causes exception does not come out on 603 604 bus in LE mode MPRH01TSU 02 85 Endian Modes PowerPc 7 8 Four Byte Transfers Figure 19 gives an ex
97. ITOR DO 20 27 CHANDRA SMD NONE M1 8 5 NONE 14 DO_NOT_POP 9 CONNMDING 1556890 15 2 749180 1 CONN_ 6 POS CIRCULAR MINI CONNMDIN6 15F6890 DIN CONNPOWER DIP 55X8085 CONNPOWER2 DIP NONE DIMMS J RAM160 DIP 3 CONN_ISA DIP 6137473 J29 J33 CONN PCI DIP 7260316 J25 J27 CONN SIMM72 NoNE 4 4 DIP 36 CRYSTL 03G9527 32 768KHZ 37 CRYSTL DO_NOT_POP DO NOT POP 14 14 DO NOT POP 16 16 NONE DO NOT POP_24W 24W DO NOT POP PLCC20 PLCC20 PowerPc Table 64 603e Bill of Materials Continued Part Ref Des Manufac Manufac JE Part Description Number turer turer DEC TYPE Name Part Number KAT2A 98F1292 23 C26 C96 C97 48 5 0805X103M 5 2805 4170313 C3 C6 C8 C9 C12 2 C15 C18 C21 C28 C31 C33 C37 C39 C40 C42 C46 C55 57 65 67 75 77 82 84 86 C93 C95 117 120 6157 164 167 169 172 174 6208 C215 C217 C220 227 231 6233 235 243 245 248 251 279 5 KYOCERA 0805Y104Z 5 0805 CAPACITOR 1B05 5 41F0316 C43 C91 C92 C94 C222 71F7911 C221 1 NEC TES 71F7911 CAPACITOR VEC1C106 M12R 42G3220 C32 C83 C85 C123 MURATA GRM40XTR 5 0805 CAPACITOR C125 222J050AD 6204724 C87 C90 KYOCERA 08055A680 SMC0805 CAPACITOR KAT2 C10 C1
98. L2 is installed else leave at reset value MPRHO1TSU 02 113 Setup PowerPc 9 5 2 Indexed BCR Summary Table 34 contains a summary listing of the indexed BCRs Access to these registers is de scribed in the 660 Bridge User s Manual Table 34 660 Bridge Indexed BCR Listing BrdgeConmoiRegister Bes Sete Now 112070 n 2 2 meo RIT Standard Programming 1 R 0 n PCI Built in Self Test BIST Control IndexoF R 1 Pomme fhe Fomerpm 200 mes Posne 1 PCI Disconnect Counter Index 42 R W a i PCI Special Cycle Address BCR Index 44 45 Memory Bank 0 Starting Address Memory Bank 1 Starting Address Memory Bank 2 Starting Address Memory Bank 3 Starting Address 2 B 114 MPRHO01TSU 02 PowerPc Table 34 660 Bridge Indexed BCR Listing Continued Setup Bridge Contrai Rediser hew RW Byes Nove Memory Bank 5 Ext Ending Address Index 9D Memory Bank 6 Ext Ending Address Index 9E Memory Bank 7 Ext Ending Address Memory Bank Enable Memory Timing 1 Memory Timin
99. LAR MINI CONNMDIN6 1556890 DIN 0 CONNPOWER DIP 55X8085 44 1 OLEX 15 48 0212 CONN_ 1X12 0 156 CL FRET LCK 55X8085 HDR CONNPOWER2 DIP NONE URNDY GTC6R 1 CONN_1X6 1X6 0 156 CL FRET LCK HDR CONN_DIMMS J3 1 BURNDY CELP2X80S CONN_ 160 PIN CELP CONN RAM160 DIP C3Z48 DIMMSRA CONN ISA DIP 6137473 J29 J33 AMP 645169 4 ISA2X49 2X49 ISA CONNECTOR CONN PCI DIP 7260316 J25 J27 3 646255 1 PCI2X605V 2X60 32 BIT CONNECTOR CONN_SIMM72 J21 J24 224 SIMM72 72 PIN SIMM CONNECTOR DIP CRYSTL 03G9527 1 EPSON 405 XTALSMT1 CRYSTAL 32 768KHZ 32 768KHZ 6PF 37 CRYSTL DO NOT NONE NONE XTALSMT2 CRYSTAL zou DO NOT POP POP Ea 1 40 DO NOT s 1 NONE NONE SO24W DO NOT POP POP_24W 24W 41 DO NOT POP_ 51 55 2 NONE NONE PLCC20 DO NOT POP PLCC20 PLCC20 DO NOT POP_ 2 1 PLCC28 DO NOT POP PLCC28 PLCC28 ELCAP 75G8253 C109 110 2 SPRAGUE 293D107X SMC2816 CAPACITOR 100UF 10 16V 96R3D2T ELCAP 33UF 57G9281 C1 C2 C7 C11 C17 49 KEMET T491D336M CAP33UF3SMT CAPACITOR 20 16V C22 C27 C38 C56 O16AS 112 116 6121 C122 C165 C166 C170 C171 C175 C183 C187 C201 C207 C232 C234 C244 C249 46 EPM5130FP SMD X2 1 ALTERA 5130 XQFP100 GTP W 128 MACROCELLS QC 100 1 47 ESP_CONN CONN 42F6867 J2 1 BERG 79282 516 2X8 PIN HEADER CONN 42F6867 48 01162378
100. LC43 CLKFF9 LOCATION LC93 CLKFF10 LOCATION LC92 CLKFF11 LOCATION 1 CLKFF12 LOCATION LC112 CNTRO LOCATION LC111 CNTR1 LOCATION LC110 CNTR2 LOCATION LC109 CNTR3 LOCATION LC108 DOUBLE FRZ LOCATION LC90 DOUBLE SNC LOCATION LC107 FREEZEFF LOCATION LC106 GEN STOP BITFF LOCATION LC105 GPCSO LOCATION LC89 PWR REG21 LOCATION LC80 IRQ12 MASK PWR REG22 LOCATION LC79 SHIFT ENFF LOCATION LC103 PIN 89 SNC FREEZE LOCATION LC99 PIN 83 SNC SHIFT ENFF LOCATION LC98 PIN 82 SNC UNFREEZE LOCATION LC101 PIN 85 START SHIFTFF LOCATION LC100 PIN 84 UNFREEZEFF LOCATION LC97 PIN 81 END 58 MPRHO01TSU 02 PowerPc EPLD 5 3 2 TDFFile he he he he he he he he he AHDL SOURCE CODE FOR SIO XBUS INTERFACE CONTROL dede ded ked k dk k k k Fe e e he e he he he he SUBDESIGN chandra DEFINE PRIMARY INPUTS AND OUTPUTS A 7 0 INPUT 7 is MSB and AO is LSB 2 0 INPUT ECS2 is MSB and 50 is LSB INPUT XIOR XIOW INPUT INPUT CMD
101. LK is high and a PCI busmaster is accessing memory Impact This workaround has negligible impact on performance but may affect the maximum op erating frequency of the CPU bus Errata 9 603 Snoop on PCI Busmaster Write Date 6 27 95 Functional The snoop operation that the 664 broadcasts on the CPU address bus when a PCI bus master begins a write to memory is Write with Kill 00110b For a 603 snoop is sup posed to be Write with Flush 00010b Workaround In 603 603e designs cut the TT 2 signal between the 664 and the CPU bus Pull both both signals 664_TT 2 and CPU_TT 2 down with 500 ohm resistors This workaround is not required in 604 designs Impact This workaround has no effect on performance or maximum operating frequency Errata10 CPU to PCI Bus Clocks at 3 1 Date 7 21 95 Functional If the CPU PCI clocks are running at a frequency ratio of 3 1 and a CPU to memory data tenure is pending then PCI busmaster to memory accesses hang Workaround Do not operate the CPU PCI bus clocks at 3 1 Impact This workaround has no effect on performance or maximum frequency MPRH01TSU 02 179 Errata Workaround Workaround PowerPc PCI Bus Hang On Pipelined CPU to PCI Master Abort 8 08 95 Normally when a CPU initiates a transfer to the PCI bus and the 660 bridge initiates the PCI transaction before the CPU data tenure be
102. M is hereby providing design information for your convenience you expressly understand and agree that exceptforthe rights granted under sections 1 and 2 above no right or license of any type is granted expressly or impliedly under any pat ents copyrights trade secrets trademarks or other intellectual property rights of IBM Moreover you understand and agree that in the eventyouwishtobe granted any license beyondthe scope ofthe expressly stated herein you will contact IBM s Intellectual Property Licens ing and Services Office currently located at 500 Columbus Avenue Thornwood N Y or such other IBM offices responsible for the licens ing of IBM intellectual property when you seek the license YOUR ASSUMPTION OF RISK You shall be solely responsible for your success in designing developing manufacturing distributing and marketing any product s or portion s where use of all or any part of the Reference Design is involved You are solely responsible for any claims warranties represen tations indemnities and liabilities you undertake with your customers distributors resellers or others concerning any product s or por tion s of product s where use of all or any part of the Reference Design is involved You assume the risk that IBM may introduce other Reference Design that are somehow better than the Reference Design which is the subject of this Agreement Furthermore you accept sole responsibility for yourdecision to selectand u
103. MP AM29F040 XPLCC32 512 8 FLASH ROM MECH MECH 120JC 2N7002 SMD 31F2311 MOTOROLA 2N7002 SOT23 3 PIN FET TRANSISTOR 26H4196 25 QFP240 603e 100MHZ 5 7406 SMD 17F7776 U3 U28 74F08 SMD 61X9236 U1 U29 NATL 7 74F11 SMD 17F7745 74F125 SMD 68X2888 NATL 74F125 1450 742125 BUFFERS 3 STATE 74F244 SMD 6480438 U10 U11 U17 U20 7 PHILIPS 74F244 SO20W OCTAL BUFF DRIVER U40 0 74F245 SMD 55 8091 1 PHILIPS 74 245 SO20W OCTAL TRANSCEIVER 11 74F74 SMD 61X9238 U21 NATL F74 14SO DUAL D FF W CLEAR 8 PRESET 74HCT14 SMD 37F9034 U2 PHILIPS 74HCT14 14SO 74HCT14 SCHMT TRIGGER INV 8042H SMD 1054195 U27 INTEL 8042H PLCC44 KEYBOARD CONTROLLER eat a 4 8G4756 SMD 08G4756 MOTOROLA MMBD914L SOT23 70V 200MA SWC DIODE T1 BATTERY_CONN 19G2441 SONY CR2 032Q CONN_ BATTERY HOLDER CONN 19G2441 6 MECH 15F8409 1 SONY CR2 032Q PART BATTERY 3 0V MECH 17 BERG1X2 DIP 6181127 J1 J8 J11 J35 BERG 69190 502 BERG1X2 1X2 100MIL HEADER VERTICAL 18 BERG1X4 DIP 6359315 J13 1 BERG 69190 504 BERG1X4 1X4 100MIL HEADER VERTICAL 19 BERG1X5 DIP 8804908 104345 3 BERG1X5 BERGSTICK 1X5 x En En MPRHO1TSU 02 189 BOM Part Name 20 E E 4 CAPACITOR 0 001UF 20 CAPACITOR 0 01UF 20 22 CAPACITOR 0 1UF 20 23 CAPACITOR 10UF 20 24 CAPACITOR 2200PF 20 25 CAPACITOR 68PF 20 CAPAC
104. NDI TIONS IF YOU DO NOT AGREE WITH THEM YOU SHOULD PROMPTLY RETURN THE PACKAGE UNOPENED TO YOUR IBM SALES OFFICE International Business Machines Corporation IBM agrees to provide you a PowerPC 603 604 Reference Design Reference Design in return for your promise to use reasonable efforts to develop a system based on the technology in the Reference Design The Reference Design contains documentation and software listed below Documentation PowerPC 603e RISC Microprocessor Hardware Specification PowerPC 603e RISC Microprocessor Technical Summary PowerPC 603 604 RISC Microprocessor Hardware Specification PowerPC 603 604 Reference Design Technical Specification IBM PowerPC 603 604 Reference Board Design Files on 8mm tape IBM PowerPC 604 Reference Board Mfg Data Files in Gerber format IBM14N1372 Data Sheet IBM11D4360B Data Sheet Motorola MPC970 Data Sheet Altera 5130 Data Sheet Integrated Device Technology IDT71216 Data Sheet LICENSE TO SOFTWARE The software is licensed not sold IBM or the applicable IBM country organization grants you a license for the software only in the country where you received the software Titleto the physical software and documentation notthe information contained in such documentation transfersto you upon your acceptance of these terms and conditions Theterm software means the original and all whole or partial copies of it including modified copies or portions merged into other programs IBM ret
105. P not allowed on PCI crosses 4 bytes E causes exception does not come out on 603 604 bus in LE mode MPRHO1TSU 02 87 Endian Modes PowerPc Table 28 contains the same information as found in Table 27 but it is arranged to show the CAS and PCI byte enables that activate as a function of the address presented at the pins of the 603 604 and as a function of BE LE mode Rearranging Table 27 for 4 byte transfers Table 28 Rearranged 4 Byte Transfer Information 60X ADDRESS PINS 5 0 7 CAS 0 7 PCI CBE 1000 0111 E NNNN NNNN 1100 0011 1110 0001 E NNNN NNNN E NNNN NNNN 0 0000 1111 N E 1000 0111 N E 1100 0011 N E 1110 0001 NNNN NNNN NNNN NNNN 0 0 0 1 1 1 1 1 1 1 it NNNN NNNN Notes N not emitted by 60X because it crosses 8 bytes transformed into 2 bus cycles P not allowed on PCI crosses 4 bytes E causes exception does not come out on 603 604 bus in LE mode X not supported in memory controller crosses 4 byte boundary 7 9 Three byte Transfers There are no explicit Load Store three byte instructions however three byte transfers oc cur as a result of unaligned four Dyte loads and stores as well as a result of move multiple and string instructions The TSIZ 3 transfers with address pins 0 1 2 3 4 or 5 may occur BE All of the other TSIZ and address combinations produced by move multiple and string operati
106. PCI 7 BE Mode Note SE does not work in SIO PCI 2 ISA Clock Divisor Config 408 4 LE Enable IRQ12 M Mouse Support oi TET m ISA Clock Divisor Config 4Dh 3 LE This bit should be set to 1 before chang PCI 4 BE ing or loading the PCI ISA Clock Divisor value Setting this bit to 1 will assert the RSTDVR signal which resets the System EPLD and any devices on the ISA bus slots All these devices will require reconfi guration after this bit has been asserted Software must guarantee that RSTDVR be asserted for a minimum of 1 ms after the clock divisor value is set ISA Clock Divisor Config LE Set this field to 000b divisor 4 If PCI PCI IE 7 BE is slower than 33 MHz then this field 0016 divisor 3 Utility Bus Select 4Eh 4 LE Disable generation of ECSADDR 2 0 and Config PCl 4 BE UBUSOE for the IDE and Floppy decode Utility Bus Chip Select A 4Eh 1 LE Enable keyboard addresses 60h 62h Config PCl 6 BE 64h 66h Utility Bus Chip Select A 4Eh 0 LE Enable TOD Addresses 70h 71h Config PCl 7 BE Utility Bus Chip Select B 4Fh 7 LE Enable access to the motherboard regis Config PCl 0 BE ters in the 0800 08 address range Utility Bus Chip Select B 4Fh 6 LE 1 1 Enable Port 92h access Config PCl 1 Utility Bus Chip Select 4Fh 5 4 LE 11 Disable generation of default address for Config PCl 2 3 Parallel Port 104 MPRH01TSU 02 Po
107. POWER1X3 DIP 65G3724 J 1 MOLEX 705 43 POWER1X3 AUX POWER 0037 CONNECTOR 5 REGHSINK DIP 533402 REGHSINK HEATSINK VOLTREG B22552 RESISTOR 0 5 98F1665 R18 amp R21 R32 R45 43 PANASONIC ERJ8GV SMC0805 RESISTOR 846 852 860 8110 JOR R125 R171 R207 R377 R438 R439 8444 8446 8448 8449 8463 8465 R474 R476 R482 R484 67 RESISTOR 98F1741 R436 1 ROHM MCR10EZH 5 RESISTOR 1 5K 5 LJW152 RESISTOR 10 5 58F1831 R82 R85 R87 R89 7 PANASONIC ERJ6GVYJ1 SMC0805 RESISTOR R96 R97 R429 00S RESISTOR 41F0328 R153 R154 R176 10 PANASONIC ERJ6VJ SMC0805 RESISTOR 100 5 R190 R192 R194 101S R238 R240 R472 R485 ala U U U U U U U 8 7 2 3 2 5 4 3 3 2 2 6 1 5 1 6 196 MPRH01TSU 02 P2werPc BOM Table 65 604 Bill of Materials Continued Part Name Part Ref Des Qty Manufac Manufac JE Part Description Number turer turer DEC TYPE Name Part Number 81 70 RESISTOR 41F0337 R1 R2 R4 R7 R19 1 PANASONIC ERJ6GVJ10 5 RESISTOR 10 5 R47 R50 R61 R80 3S R81 R90 R93 R95 R102 R107 R108 R119 R138 R145 R147 R148 R155 R166 R174 R237 R253 R255 R257 R260 R287 R351 R364 R368 R376 R378 R381 R384 R387 R392 R394 R397 R399 R401 R403 R416 R423 R430 R434 R452 R461 R468 R471 R473 R475 R488 R495 R497 R510 71 RESISTOR 40G7066 R65 1 PANASONIC ERJ 6VNF
108. PUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN INPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN OUTPUT PIN 60 59 22 21 16 72 71 70 67 66 65 64 61 89 36 20 83 10 82 58 50 49 57 56 90 100 99 86 98 54 53 52 41 EPLD LC8 LC3 LC103 LC38 LC99 LC98 LC72 LC56 LC55 LC71 LC70 LC104 LC120 LC119 LC102 LC118 LC68 LC1 LC67 LC66 LC49 PowerPc EPLD RTC ALE OUTPUT PIN 48 LC54 RTCDS OUTPUT PIN 51 LC65 RTCWR OUTPUT PIN 35 LC37 83CX RESET OUTPUT PIN 91 LC113 RWDO BIDIR PIN 96 LC116 XDO BIDIR PIN 95 LC115 XD1 BIDIR PIN 34 LC36 XD2 BIDIR PIN 74 LC82 XD3 BIDIR PIN 73 LC81 4 BIDIR 92 4 XD5 BIDIR PIN 33 LC35 XD6 BIDIR PIN 32 4 XD7 BIDIR PIN 31 LC33 CLKFFO LOCATION 8 CLKFF1 LOCATION LC96 CLKFF2 LOCATION LC95 CLKFF3 LOCATION LC94 CLKEE47 LOCATION LC47 CLKFF5 LOCATION LC46 CLKFF6 LOCATION LC45 A 7 LOCATION LC44 8 LOCATION
109. RAMMED PAL H 5 PLCC20 100 X PART HPP 8185187 X 1 AMD PALCE16V8 XPLCC20 PROGRAMMED PAL H 5 PLCC20 101 THERMOSTRATE X 1 POWER AL 079 079 HEAT SINK INTERFACE DEVICES MATERIAL 198 MPRH01TSU 02 P CF P c Schematics Section 15 Schematics This section contains the schematics of the reference design and a component placement drawing of the reference board The schematics are numbered separately from the rest of the reference design technical specification MPRHO1TSU 02 199 Power HOLIMS 13534 78 18917 A1dd MPRH01TSU 02 93149009 H3MOd WYYAN OLY 5971 SY TIYO 15 1 Reference Board Component Placement Schematics
110. S FOR A PARTICULAR PURPOSE ARE OFFERED IN THIS DOCUMENT Contacts USA and Canada Japan IBM Microelectronics Division IBM 1580 Route 52 Bldg 504 800 Ichimiyake Hopewell Junction NY 12533 6531 Yasu cho Yasu gun Tel 800 PowerPC Shiga ken Japan 520 23 Fax 800 PowerFax Tel 81 775 87 4745 Fax 81 5 Europe Europe IBM IBM La Pompignane BP 1021 Informations Systeme GmbH 34006 Montpellier France Laatzener Str 1 Tel 33 6713 5757 Francais 30539 Hannover Germany 33 6713 5756 Italiano Tel 49 511 516 3444 English Fax 33 6713 5750 49 511 516 3555 Deutsche Paris add 16 Fax 49 511 516 3888 ESD Warning The motherboard and memory cards contain CMOS devices which are very susceptible to ElectroStatic Discharge ESD DO NOT remove them from the antistatic bags until you have connected yourself to an acceptable ESD grounding strap Work in a static free envi ronment and be sure any person or equipment coming into contact with the cards do not have static charge The cards are particularly susceptible until they are placed a prop erly designed enclosure Bench work should be done by persons connected to ESD grounding straps 8 50 02 PowerPc IBM POWERPC 603 604 REFERENCE DESIGN AGREEMENT BEFORE READING THE REST OF THE DOCUMENT YOU SHOULD CAREFULLY READ THE FOLLOWING TERMS AND CONDITIONS OPENING THE PACKAGE INDICATES YOUR ACCEPTANCE OF THESE TERMS AND CO
111. Sectors 6 32 bit RBA count one based LE RBA Relative Block Address in units of 512 bytes LE Little Endian Figure 28 Partition Table Entry for PowerPC Reference Platform The 32 bit start RBA is zero based The 32 bit count RBA is one based and indicates the number of 512 byte blocks The count is always specified in 512 byte blocks even if the physical sectoring of the target devices is not in 512 byte sectors 122 MPRH01TSU 02 PowerPc 10 3 2 Loading the Load Image This section describes the layout of the PowerPC 0x41 type partition and the process of loading the load image Firmware PC Compatibility Block Entry Point Offset LE Load Image Load Image Length LE Flag Field OS ID Partition Name Reserved1 OS Specific Field Optional Code Section of the Load Image Reserved2 512 516 520 521 522 554 1024 RBA Count 512 Figure 29 PowerPC Reference Platform Partition The layout for the 0x41 type partition is shown in Figure 29 The PC compatibility block in the boot partition may contain an x86 type program When executed on an x86 machine this program displays a message indicating that this partition is not applicable to the current system environment The second relative block in the boot partition contains the entry point offset load image length flag field operating system ID field ASCII partition na
112. _STATE INPUT PROC_RDY INPUT EXT_ACTVTY INPUT IRQ1 INPUT IRQ12 INPUT Freeze Clock ISA CLK INPUT UNFREEZE INPUT PLANAR ID RD OUTPUT PRSNT RD OUTPUT L2 STATUS RD OUTPUT DRAM PD RD1 OUTPUT DRAM PD RD2 OUTPUT KYBD CS OUTPUT IRQ1 OUT OUTPUT RTC ALE OUTPUT RTCDS OUTPUT RTCWR OUTPUT ASO OUTPUT AS1 OUTPUT NVRAMWE OUTPUT NVRAMOE OUTPUT HDD LED OUTPUT 83CX RESET OUTPUT ACTIVITY OUTPUT IO STROBE OUTPUT FRZ DATA OUT OUTPUT XD 7 0 BIDIR XD7 is MSB and XDO is LSB RWDO BIDIR VARIABLE Misc Variables GPCSO NODE HDD LEDFF SREF D 7 0 NODE XD TRI OE NODE LIGHT STRB NODE INT1FF DFF Keyboard interput latch CLRINT1 NODE Power Management Variables MPRH01TSU 02 59 EPLD PowerPc PWR REG1 STRB NODE PWR REG2 STRB NODE PWR REG2 2 0 SRFF 83CX_CS NODE RWDO STRB NODE IRQ12 MASK NODE Freeze Clock Variables CLKFF 12 0 DFFE SHIFT ENFF SRFF CNTR 3 0 DFF SNC_SHIFT_ENFF DFFE START SHIFTFF SRFF CLKFF WR NODE CLKFF STRB NODE CLKFF SELL NODE CLKFF SELH NODE GEN START BIT NODE GEN STOP BITFF DFF STOP SHIFT NODE UNFREEZEFF DFFE Unsynchronized UNFREEZE SNC_UNFREEZE DFF Synchronized UNFREEZE DOUBLE_SNC DFF Double Synchronized UNFREEZE FREEZEFF DFFE Unsynchronized FREEZE SNC_FREEZE DFF Synchronized FREEZE DOUBLE_FRZ
113. a 2M ROM space from 4G 2M to 4G The actual ROM is 512K device located at 4G 2M The ROM is attached to the 660 bridge via the PCI AD lines This mode is required when using the Intel SIO ROM device writes and write protect commands are supported See the 660 Bridge User s Manual for more information The ROM device attaches to the 660 bridge by means of control lines and the PCI AD 31 0 lines When a CPU bus master reads from the ROM the bridge masters a BCR transaction during which it reads the ROM and returns the data to the CPU CPU writes to the ROM and ROM write protection operations are also forwarded to the ROM device Although connected to the PCI AD lines the ROM is not a PCI agent The ROM and the PCI agents do not interfere with each other because the ROM is under bridge control and the bridge does not enable the ROM except during ROM cycles The bridge accesses the ROM by means of BCR transactions Other PCI devices cannot read or write the ROM be cause they cannot generate BCR transactions 6 4 4 CPU to ROM Read At power on the 603 604 CPU comes up in BE Mode with the L1 cache disabled and be gins fetching instructions using 8 byte single beat reads at address FFFO 0100 4G 1M 100h The reference design logic also resets to BE mode The system ROM address space is from 4G 2M to 4G Since the size of the installed ROM is less than 2M 512K it is mirrored every 512K throughout the ROM space Location 0 of th
114. able and status registers are relocatable via a configuration register in the ISA bridge The termination of an operation may be signaled to the software by configuring any or all of the SG channels to use IRQ13 or by configuring the channel to signal end of pro cess aka Terminal Count to the DMA device See the SIO data book for details 46 MPRHO01TSU 02 PowerPc ISA Bus 4 6 X Bus The X bus is a utility bus an 8 bit buffered version of the ISA bus implemented on the refer ence board to support the native I O devices that are located on the reference board X bus data transceiver U12 is controlled by the ISA bridge via XDIR UBUSTR and XDEN UBUSOE Various devices are located on the X bus 4 6 1 Control Signal Decodes The System I O EPLD Chandra is a programmable logic device that uses the X bus sig nals and the partial decode signals from the ISA bridge to decode chip selects for various components For more information on the System I O EPLD see that data sheet 4 6 2 Keyboard Mouse Controller The reference design uses an Intel 8042AH as a keyboard and mouse controller which resides on the X bus The code used is the same version as used in IBM Personal System 2 machines This microcode may differ from other 8042 type keyboard controllers These dif ferences are usually only significant when porting AIX to the system for more information contact your IBM representative This device contains several registers See th
115. ains title to the software IBM owns or has licensed from the owner copyrights to the software provided under this agreement The terms of this Agreement apply to all of the hardware software and documentation provided to you as part of the Reference Design With regard to the software provided hereunder it is understood and agreed that you intend to use the software solely for the purpose of designing PowerPC compatible products testing your designs and making your own independent determination of whether you wish to eventually manufacture PowerPC compatible products commercially In accordance with this understanding IBM hereby grants you the rights to a use run and copy the software but only make such number of copies and run on such number of machines as are reasonably necessary for the purpose of designing PowerPC compatible products and testing such designs and b copy the software for the purpose of making one archival or backup copy With regard to any copy made in accordance with the foregoing license you must reproduce any copyright notice appearing thereon With regard to the software provided hereunder you may not a use copy modify or merge the software except as provided in this license b reverse assemble or reverse compile it or c sell sublicense rent lease assign or otherwise transfer it In the eventthat you no longer wish to use the software you will return it to IBM LICENSE TO DESIGN DOCUMENTATION With rega
116. al terminal The example screens shown in this section show the S3 video keyboard inter face When using a serial terminal the configuration utilities will prompt for numeric input for each prompt instead of using the arrow keys All choices and options are the same as for the screen oriented menus The configuration of the reference board as shipped is set for S3 video Keyboard console In the case that either the video adapter or the keyboard fails the power on test the system console will default to serial port 1 The baud rate for the serial console is specified in the configuration menus The value as shipped is 9600 baud 10 4 2 System Initialization The logo screen shown in Figure 30 is displayed at power on The logo screen is active while the system initializes and tests memory and performs ascan of the SCSI bus to deter mine what SCSI devices are installed PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved HEHEHEH 4 HHH HEHHEHE HEHEHE HO HEHHE HEHHE WH gg d EOS HEHE HH PowerPC 603 604 Reference Board Press C during memory test for configuration utilities Testing 8192K of memory 8192 KB OK Figure 30 System Initialization Screen MPRHO1TSU 02 125 While the logo screen is displayed pressing the C key on the console will ente
117. al and of the PowerPC 604 User s Manual Note that other PCI bus masters can initiate interrupt acknowledge transactions but this may have unpredictable effects 94 MPRH01TSU 02 PowerPc 8 1 3 Interrupt Assignments In general program ISA interrupts are edge sensitive Program PCI interrupts as level sen sitive Interrupts are assigned to priority levels per ISA conventions Table 29 shows inter rupt assignments IRQ 0 7 connect to the master controller and IRQ 8 15 connect to the cascaded controller Figure 24 shows the connection of the PCI interrupts Exceptions Table 29 Mapping of PCI Memory Space Part 1 mpm 1 SysUOEPLD 2 2 __ 810 Eea 3 ISA IRQ6 14 SA Ls Assignment or Comment Timer 1 Counter 0 Internal to 510 Keyboard Cascade from controller 2 COM 2 or COM 4 COM 1 or COM 3 Parallel LPT 1 or 2 Floppy Parallel LPT 2 or 3 TOD aka Real Time Clock smog EL 1 5 ISAIROI5 Audio 5 ISAIRQ5 1 ms PET SSS 12M ulled up Also see section 13 Errata Mouse P IDE 1 2 3 4 ISA IRQ4 5 10 11 15 PIRQ2 Figure 24 PCI Interrupt Connections 8 1 4 Scatter Gather Interrupts Where possible set up the scatter gather function to use the ISA bridge end of process EOP output indicator for the termination of ISA bus DMA in which
118. ample of Word 4 Write of Oa0bOcOdh AT ADDRESS XXXX XXXA Big Endian Little Endian 603 604 Swap Off Memory 603 604 Swap On Memory Figure 19 Word 4 Byte Write of 0a0b0c0dh at Address XXXX XXX4 86 MPRHO01TSU 02 PowerPc Endian Modes Table 27 and Table 28 illustrate the cases that can occur The columns of Table 27 have these meanings The first column indicates the target address e g the address of the byte coded into a store word instruction The next two columns show the state of the address pins for BE mode The next two columns show the state of the address pins for the same target data when the machine is in LE mode e The remaining columns show the CASs and the PCI byte enables associated with the target data The notes indicate which combinations either do not occur at the 603 604 pins be cause of internal exceptions or are not supported externally For 4 byte transfers Table 27 holds Table 27 4 Byte Transfer Information PROG BE MODE LE MODE BE OR LE BE OR LE BE OR LE TARG 603 604 BE X or w 100 Target CAS 0 7 PCI CBE ADDR add a29 31 add a29 31 bytes 0 7 AD2 3210 1 E 1 4 1000 0111 0 PPPP 2 1100 0011 0 3 3 6 1110 0001 11 4 1 1 1 1 2 3 4 100 000 4 1111 0 0000 5 5 E NNN NNNN NNNN E N 6 6 NNN E NNN N N NNNN NNNN E 7 7 NNN E NNN N N NNNN NNNN 1E N Notes N not emitted by 60X because it crosses 8 bytes transformed into 2 bus cycles
119. art Part Name Part Ref Des Qty Manufac JE Part Description Number DEC_TYPE Number 2 29F040ROM _ 82G6496 X3 1 AMD AM29F040 XPLCC32 512KX8 FLASH ROM imeen d Q1 033 3 2N7002 SMD 3122311 MOTOROLA 2N7002 SOT23 3 PIN FET TRANSISTOR 4 604FP SMD 50H5239 1 IBM IBM25 PPC QFP304 5 604 132MHZ IN QFP 604 F X 133 X 5 7406 SMD 17F7776 U3 U28 7406 14SO HEX INVERTER OC 74F08 SMD 61X9236 U1 U29 NATL 1450 QUAD 2 INPUT AND GATE 7 74F11 SMD 17F7745 NATL 14SO TRI 3 INPUT AND GATE 74F125 SMD 68X2888 NATL 74F125 14SO 74F125 BUFFERS 3 STATE 74F244 SMD 6480438 U10 U11 U17 U20 PHILIPS 74F244 SO20W OCTAL BUFF DRIVER U 10 74F245 SMD 55X8091 1 PHILIPS 74F245 SO20W OCTAL TRANSCEIVER 11 74F74 SMD 61X9238 1 NATL F74 1450 DUAL D FF W CLEAR 8 PRESET 74HCT14 SMD 37F9034 PHILIPS 1054195 74HCT14 1450 74HCT14 SCHMT TRIGGER INV 8042H PLCC44 KEYBOARD CONTROLLER MMBD914 SOT23 LT1 CR2 032Q CONN_ 834 19G2441 CR2032 PART 69190 502 BERG1X2 69190 504 4 0 1 8042H SMD 7 NTEL 14 8G4756 SMD 6 70V 200MA SWC DIODE ONY 4 U2 U2 U2 CR 5 BATTERY HOLDER 1 BATTERY 3 3V 1 15 8409 7 BERG1X2 DIP 6181127 J1 J8 J11 J35 98F 1292 C23 C26 C96 C97 30 KYOCERA C129 C148 C202 C205 41F0313 03 06 08 09 012 142 KYOCERA C15 C18 C21 C28 C31 C33 C37 C39 C40 C42 C46 C55 57 65 67 75 77 82 84 86 C93 095 0117 64 0167 0169
120. bits during memory writes and checking correcting the data during memory reads ECC can be imple mented using normal parity DRAM See the 660 Bridge User s Manual for more informa tion Note that for each memory read operation eight bytes of memory are read and parity on eight bytes is checked regardless of the transfer size Therefore all of memory must be initialized at least up to the end of any cache line that can be accessed The reference design does not generate or check CPU bus address parity 8 2 1 1 CPU to Memory Writes During CPU to memory writes the CPU drives data parity information onto the CPU data bus Correct parity is then generated in the 660 and written to DRAM memory along with the data The L2 SRAM is updated when required with the data and the parity information that the CPU drove onto the CPU data bus During CPU to memory writes the 660 bridge checks the data parity sourced by the CPU and normally reports any detected parity errors TEA 8 2 1 2 CPU to Memory Reads When the CPU reads from memory the data and accompanying parity information can come from either the L2 SRAM or from DRAM memory If the data is sourced from the L2 the parity information also comes from the L2 If the data is sourced by memory the parity information also comes from memory The L2 SRAM is updated when required using the data and parity from memory During CPU to memory reads the 660 bridge samples the DPE outpu
121. c to which the CPU agent might respond Note that PCI to memory transactions cause the 660 bridge to broadcast snoop operations on the CPU bus HIDO bit 0 Master Checkstop Enable defaults to 1 which is the enabled state Leave it in this state so that checkstops can occur Reference design errors are reported through the 660 bridge by way of the TEA and MCP pins Because of this the bus error checking in the CPU must be disabled by setting HIDO bits 2 and 3 to zero in the 604 enable L1 cache parity checking by setting HIDO 1 to 1 MPRHO1TSU 02 101 Setup 9 2 PowerPc 660 Bridge Initialization Before DRAM memory operations can begin the software must 1 2 3 Read the SIMM presence detect and SIMM type registers Set up and check the memory related registers in the 660 bridge see the 660 Bridge User s Manual Program the timer in the ISA bridge register which controls ISA refresh timing In SIO compatible bridges it should be programmed to operate in Mode 2 with an interval of approximately 15 usec Make sure 200 usec has elapsed since starting the refresh timer so that sufficient refresh cycles have occurred to properly start the memory This will be hidden if approximately 120 Flash accesses occur after the timer is started and before the memory initialization starts Initialize all of memory so that all parity bits are properly set The CPU may cache unnecessary data hence all of memory must be initia
122. ce However address unmunging in LE mode has no effect on the cycle because the addresses are ignored Therefore software must reverse the byte significance of the data and address encoded into the store instructions for LE mode writes to the ROM 2 6 2 1 ROM Write Protection Flash write protection must be implemented within software Port FFFF FFF1 can be used to lock out all Flash writes Writing any data to this port address locks out all Flash writes until the 660 Bridge is hardware reset In addition the Flash itself has means to permanent ly lock out changing certain sectors by writing control sequences Consult the Flash Specifi cation for details 2 6 3 to BCR Transfers The 660 Bridge can be extensively programmed by means of the Bridge Control Registers BCR See the 660 Bridge User s Manual for a description of the operation and program ming of the 660 bridge BCRs 34 MPRHO01TSU 02 PowerPc PCI Bus Section 3 PCI Bus The reference design includes a 32 bit PCI bus at frequencies up to 33MHz The PCI bus is compatible with the PCI Specification revisions 2 0 and 2 1 The power supply voltage is 3 3v and the reference design components have 5v tolerant I O Up to three PCI cards may be added to the system which provides full hardware and software support for PCI 2 0 and 2 1 compliant PCI agents The PCI bus can be run an one third one half or the same frequency as the 60X CPU bus and is initially configured to
123. ced on the PCI bus by the ISA bridge on behalf of an ISA master are forwarded to system memory at the corresponding address 0 16M If ISA masters are utilized and the SIO is programmed to forward their cycles to the PCI bus then no other PCI device e g video is allowed to be mapped at the same addresses because contention would result The SIO chip contains registers to control which ranges of ISA addresses are forwarded to the PCI bus ISA masters cannot access any PCI memory For more information on the handling of ISA bus master operations see the 660 Bridge User s Manual and the SIO data book 3 2 PCI Transaction Details Details of the reference design implementation of various PCI transactions including se quencing timing and interactions with the CPU bus are found in the 660 Bridge User s Manual 38 MPRH01TSU 02 PowerPc PCI Bus PCI bus masters are not able to access the boot ROM the BCRs in the 660 bridge or the CPU bus 3 2 1 Bus Snooping on PCI to Memory Cycles Each time a PCI or ISA bus master accesses memory and once again for each time a PCI burst crosses a cache block boundary the 660 bridge broadcasts a snoop operation on the CPU bus If the CPU signals L1 snoop hit by asserting ARTRY the 660 bridge retries the PCI transaction The ISA bridge then removes the grant from the PCI agent who according to PCI protocol releases the bus for at least one cycle and then arbitrates again Meanwh
124. che status register read strobe EPLD asserts this signal to read X bus port 080D NVRAMOE NVRAMWE PLANAR_ID_RD 52 PRSNT_RD 41 RTC_ALE 48 RTCDS 51 RTCWR 35 Interrupt Signals IRQ1 NVRAM output enable read strobe EPLD asserts this signal to read X bus port 0076 This normally causes a read of the NVRAM data stored at the location contained in the NVRAM address register NVRAM data write strobe EPLD asserts this signal to write to X bus port 0076 This normally causes the data associated with this write to be written into the NVRAM location contained in the NVRAM address register Planar ID read EPLD asserts this signal to read X bus port 0852 Equipment present register read EPLD asserts this signal to read X bus port 080C Real time clock address latch enable EPLD asserts this signal to write X bus port 0070 Real time clock read strobe EPLD asserts this signal to read X bus port 0071 Real time clock write strobe EPLD asserts this signal to write to X bus port 0071 Interrupt request 1 Latched active when IRQ1 IN is as serted Negated when KYBD_CS is asserted IRQ1 IN Keyboard interrupt EPLD is designed to intercept the keyboard interrupt between the keyboard and the ISA bus bridge Either connect IRQ1 and IRQ1 IN as shown in the reference design or disconnect both signals from the sys tem routing the keyboard interrupt to the ISA bus bridge or see the 603 604 Heference Desig
125. d by EPLD X bus port address decoders From SIO ECSEN Encoded Chip Select Enable Asserted to enable the base decoder Negated to select the option decoder Used by EPLD X bus I O port address decoders From SIO XA 7 0 address bus 7 0 Used X bus port ad dress decoders XD 7 0 X data bus 7 0 Used by EPLD to transfer data XIOW X bus Write This signal indicates that the system is writing to an X bus device Used by EPLD X bus MO port address decoders X bus Read This signal indicates that the system is reading from an X bus device Used by EPLD X bus I O port address decoders External Register Support Signals AS0 50 NVRAM address register low byte write strobe EPLD as 6mA serts this signal to write to X bus port 0074 1 49 NVRAM address register high byte write strobe EPLD 6mA asserts this signal to write to X bus port 0075 54 MPRHO01TSU 02 PowerPc EPLD Table 16 Signal Descriptions Continued Signal Name Pin External Register Support Signals DRAM PD RD1 Description DRAM SIMM presence detect read enable 1 EPLD as serts this signal to read X bus port 0880 PD_RD2 DRAM SIMM presence detect read enable 2 EPLD as serts this signal to read X bus port 0881 KYBD_CS L2_STATUS_RD Keyboard chip select EPLD asserts this signal to read X bus ports 0060 0062 0064 and 0066 L2 ca
126. d by the situation MPRHO1TSU 02 45 ISA Bus PowerPc 4 5 DMA The DMA controller in the ISA bridge consists of the functionality of two 82C37A DMA con trollers with 32 bit addressability extensions and enhanced functionality The DMA request grant lines are connected on the reference design as shown in Table 11 Table 11 DMA Assignments 4 5 1 Supported DMA Paths DMA operations can be performed only From ISA I O mapped devices to ISA memory mapped devices and From ISA mapped devices to system memory via the PCI bus In these trans fers the system memory address must be mapped to the PCI address range 0 to 2G see section 4 4 The source device can be located on the X bus If the target is ISA memory mapped it can also reside on the X bus ISA DMA to PCI I O devices is not allowed ISA to PCI memory devices is not allowed ISA from ISA memory mapped devices 15 not allowed 4 5 2 Timing The DMA controller runs compatible cycles for all ISA to ISA DMA transfers Type A type B and type F timing is available only for ISA I O to system memory via the PCI DMA trans fers 4 5 3 Scatter Gather The reference design permits the use of independent scatter gather SG operations on DMA channels 0 3 and 5 7 This operation chains together a number of DMA transfers to different memory locations so that they appear as one DMA transfer The SG command descriptor t
127. d to be in big endian BE order when the most signif icant part of the number is in the lowest numbered storage location and less significant parts are in successively higher numbered locations AIX is an example of an operating system that stores data in memory and on media in BE order A number is said to be in little endian LE order when it is stored with the order of bytes reversed from that of BE order WindowsNT is an example of an operating system that uses LE order in memory and on media The endian order of data never extends past an 8 byte group of storage 7 1 What the 603 604 CPU Does The 603 604 CPU assumes that the significance of memory is BE When it operates in in ternal LE mode it internally generates an effective address the same as the LE code would generate Since it assumes that the memory is stored with BE significance it transforms munges the three low order addresses when it activates the address pins For example in the 1 byte transfer case address 7 is munged to 0 6 to 1 5 to 2 and so on The data transfer occurs on the byte lanes identified by the address pins and transfer size TSIZ pins in either BE or LE mode The CPU shifts the data to the correct byte lane s Note that if the TSIZ is 1 and the address pins 000b then byte lane 0 cpu data lines 0 7 must be used for the data transfer in either mode For a 4 byte transfer to add 4 in LE mode the CPU munges the add to 0 and drives the data onto byt
128. dentical to the HPP1 PAL described in section 13 4 172 MPRH01TSU 02 PowerPc Biati 13 3 3 HCn Reference Design Workaround PAL TITLE HC pds PATTERN none REVISION 1 0 COMPANY IBM DATE 08 07 95 CHIP _ PALCE16V8 Predefined PIN 1 CPU_CLK CLOCK PIN 10 GND GROUND PIN 11 OUTPUT ENABLE FOR REGISTERED OUTPUTS PIN 20 Inputs PIN 2 BG IN INPUT PIN 3 ABB INPUT PIN 4 BR IN INPUT PIN 5 MASK BG2 INPUT PIN 6 MASK BG1 INPUT PIN 7 MASK BR INPUT PIN 8 DBB INPUT PIN 9 MASK BG3 INPUT PIN 9 PCI IN _ INPUT outputs PIN 12 CPU AO COMB COMBINATIONAL PIN 13 BR OUT COMB COMBINATIONAL PIN 17 PCI OUT COMB COMBINATIONAL PIN 19 BG OUT COMB COMBINATIONAL Internal Registers PIN 14 PIN 15 DEL ABB REG REGISTERED PIN 16 DEL BG _ REG REGISTERED PIN 18 MASK PCI GNT REG REG MPRHO1TSU 02 173 Erai PowerPc EQUATIONS Output enables for Comb logic 5 controllered by 11 CPU AO TRST ABB DEL ABB _ for Errata 6 Equations for internal registers DEL BG_ BG_IN_ DEL ABB ABB MASK PCI GNT ABB DEL ABB CPU AO DBB_ For Errata 11 MASK PCI GNT DBB Delay granting PCI to the CPU when a CPU to PCI GNT OUT PCI GNT IN PCI cycle is pipelined MASK PCI over the data tenure of the previous cycle BG OUT BG IN MASK BG1 for Errata
129. der require IBM to disclose any busi ness planning information to you You agree to comply with all applicable government laws and regulations Any changes to this Agreement must be in writing and signed by the parties 4 MPRHOSTSU 02 PowerPc Table of Contents Section 1 Introduction 1 1 IBM Reference Products 1 1 1 eese 11 2 Beference Board s ul wats iad sa ru T E REX ba Rae a 1 0 Reference us iod a ea a ee 1 124 Reference SySEHSIW RR LE ERE EA 1 3 Reference Design Overview The Pto cos a Sitter curat re Evo anh ak t UM 1 3 2 IBM27 82660 Bridge t33 QUT IU EN 1 34 System Memory secus extr eh et e IRE Eee tts M lu SS PODBUS c ric duce sr ere Fd 13 62 FlashiROM EE EE EE US rS 1 3 8 Time of Day Clock 1 3 9 PS 2 Compatible Keyboard Mouse Controller 13 10 System Glocks 0 oi System OU EPI paket et 1 4 Quickstart Peripheral List 2h 228 hase ance ee axe oe Waste mews 1 5 Reference Design Level Section 2 CPU and CPU 2 1 B s Masters uui SDR xai rada wen ed Xa eee ek 60 GPA
130. e 512K ROM is mapped to CPU bus addresses 4G 2M 4G 1 5M 4G 1M and 46 5 Flash is located the PCI bus physically but not logically is 8 bits wide This quires the 660 Bridge to decode Flash address run 8 cycles to PCI bus without activating FRAME accumulate the 8 single bytes of read data into an 8 byte group and generate a TA and an AACK to complete the cycle The CPU can also read the ROM using bursts but it receives the same 2 instructions from the ROM on each beat of the burst For more information see the 660 Bridge User s Manual Software can lock outthe ROM using a 660 bridge BCR When the CPU writes to any ROM location while the ROM is locked out the bridge signals normal transfer completion to the CPU but does not write the data to the ROM The CPU bus write to the locked flash bit in the 660 bridge error status 2 register bit 0 in index C5h is set 6 4 2 CPUto ROM Write Writing to Flash is another very specialized cycle Only one address FFFF FFF0 is used for writing data to Flash The Flash address and data are both encoded into four bytes and 74 MPRH01TSU 02 P2werPc Memory written using a 4 byte write transfer Eight byte and burst transfers to the ROM are not sup ported See the 660 Bridge User s Manual Writes to Flash may be performed in either BE or LE mode The data byte swapper in the 660 Bridge is gated according to endian mode Writes in BE mode occur in natural se quence How
131. e 7 CPU byte lane 1 Memory byte lane 1 PCI lane 1 Memory Byte lane 6 PCI lane 6 CPU byte lane 2 Memory byte lane 2 PCI lane 2 Memory byte lane 5 PCI lane 5 Note n this table PCI byte lane 3 0 refers to the data associated with PCI C BE 3 0 when the third least significant bit of the target PCI address is Ob as coded in the instruction PCI byte lane 7 4 refers to the data associated with PCI c BE 3 0 when this bit is b1b Since the reference design logic maintains the memory in BE mode during BE operation and in LE mode during LE mode operation no address translations are necessary in BE mode However the CPU addresses must be unmunged in LE mode This is accomplished in the 660 Bridge by applying the same XOR function mentioned above whenever the CPU accesses either PCI or memory The munge effect nullifies the address translation that oc curs within the CPU For example if the CPU executes a one byte load coded to access byte 0 of memory in LE mode it will emit address 7 The 660 Bridge will change the external address to 0 This is summarized in Table 20 Table 20 Endian Mode 6 3 604 Address Translation Effective Address at Memory or PCI No change Same address as coded Unmunge Address emitted Transform to same address as coded When a PCI master accesses memory the bridge chip set does not make any address translations in the address fields affected by endian mode in either endian mode In other words data
132. e PowerPC Reference Platform boot partition and its location in the media The layout of the boot record must be designed as shown in Figure 5 The first 446 bytes of the boot record contain a PC compatibility block the next four 16 byte entries make up a partition table totalling 64 bytes and the last 2 bytes contain a signature 0 0 PC Compatibility Block 0x1BE 446 Partition Entry 1 0x1CE 462 Partition Entry 2 0x1DE 478 Partition Entry 3 494 Partition Entry 4 0x1FE 510 0x55 0xAA Figure 25 Boot Record 10 3 1 1 PC Partition Table Entry support media interchange with the the PowerPC Reference Platform defines the formatofthe partition table entry based onthatforthe PC This section describes the format of the PC partition table entry which is shown in Figure 26 0 Partition Begin 4 Boot Ind Head Sector Cyl Partition End 8 Sys Ind Head Sector Cyl Beginning Sector 12 Low Word LE High Word LE Number of Sectors Low Word LE High Word LE LE Little Endian Figure 26 Partition Table Entry 120 MPRH01TSU 02 PowerPc Firmware Partition Begin The beginning address of the partition in head sector cylin der notation e Partition End The end address of the partition in cylinder head sector notation Beginning Sector The number of sectors preceding the partition on the disk That is the zero based relativ
133. e block address of the first sector of the partition Number of Sectors The number of sectors allocated to the partition The subfields of a partition table entry are defined as follows Boot Ind Boot Indicator This byte indicates if the partition is active If the byte contains 0x00 then the partition is not active and will not be considered as bootable If the byte contains 0x80 then the partition is considered active Head An eight bit value zero based Sector A six bit value one based The low order six bits are the sector value The high order two bits are the high order bits of the 10 bit cylinder value Cyl Cylinder The low order eight bit component of the 10 bit cyl inder value zero based The high order two bits of the cyl inder value are found in the sector field Sys Ind System Indicator This byte defines the type of the partition There are numerous partition types defined For example the following list shows several 0x00 Available partition 0x01 DOS 12 bit FAT 0x04 DOS 16 bit FAT 0x05 DOS extended partition 0x41 PowerPC Reference Platform partition 10 3 1 2 Extended DOS Partition The extended DOS partition is used to allow more than four partitions in a device The boot record in the extended DOS partition has a partition table with two entries but does not con tain the code section The first entry describes the location size and type of the partition The second entry points to
134. e data sheet for more information 4 6 3 Real Time Clock RTC The reference design uses a Dallas Semiconductor DS1385S to provide the real time clock TOD or RTC function This device is PC compatible and resides on the X bus It fea tures an additional 4K of NVRAM and a replaceable battery This device contains several registers See the data sheet for more information 4 6 4 PCI Adapter Card Presence Detect Register The reference design uses U20 to buffer the PCI adaptor card presence detection bits onto the X bus under control of the system I O EPLD These bits report in pairs and do not con tain any information about the identity of the card They merely report on its presence SA Pot 0806 lpzpslpslpxlpslpzlrlpal ise PCI Slot 0 Detect PCI Slot 1 Presence Detect PCI Slot 2 Presence Detect Reserved Bits 7 6 Reserved Bits 5 4 PCI Slot 2 Presence Detect 00 Present 11 No PCI card installed Bits 3 2 PCI Slot 2 Presence Detect 00 Present 11 No PCI card installed Bits 1 0 PCI Slot 2 Presence Detect 00 Present 11 No PCI card installed MPRH01TSU 02 47 ISA Bus PowerPc 4 6 5 12 SRAM Identification Register The reference design uses U19 to buffer the SRAM identification presence detect bits from the SRAM socket onto the X bus under control of the system EPLD 07 06 05 04 03 02 01 60 8 EST MSB SRAM ID 2 0 Reserved Table 12
135. e lanes 0 through 7 The 603 604 performs the following munge operation in LE mode TSIZ 8 0 gt None TSIZ 4 gt 603 Internal Address 29 31 with 100b gt address at pins of CPU TSIZ 22 gt 608 Internal Address 29 31 XOR with 110b gt address at pins of CPU TSIZ 1 gt 603 Internal Address 29 31 with 111b gt address at pins of CPU MPRHO1TSU 02 77 Endian Modes PowerPc 7 2 What the 660 Bridge Does Data is stored in system memory in the same endian mode as the mode in which the CPU operates Thatis the byte significance in memory is BE in BE mode and it is LE in LE mode Because of this hardware is included in the 660 bridge to steer the data bytes to the correct byte lanes according to mode and to unmunge the addresses coming from the 603 604 CPU in LE mode This unmunge merely applies the same transformation to the three low order address lines as the 603 604 CPU reversing the effect of the munge that occurs within the 603 604 CPU The hardware cannot tell the endian mode of the CPU directly There is a control bit located in ISA I O space port 0092 that the CPU can write to in order to set the endian mode of the motherboard This signal is applied to the 660 Bridge which performs the operations shown in Table 19 Table 19 Endian Mode Byte Lane Steering CPU Byte Lane BE Mode Connection LE Mode Connection CPU byte lane 0 MSB Memory byte lane 0 PCI lane 0 Memory byte lane 7 PCI lan
136. ed in a device other than the EPLD As shown in Figure 5 the EPLD supplies control signals to the external registers based on a decode of the address and control lines of the X bus or ISA bus In response to the signals from the EPLD the exter nal register either reads or writes data to the X bus X bus or ISA External Register AC D or Device Address Strobes Possible Other Circuitry Control Figure 5 Typical External Register MPRHO01TSU 02 51 EPLD PowerPc For the external registers that the EPLD supports Table 15 shows the external register the ISA I O port address and the supplied control signal s Table 15 External Register Support ISA Port Register Read Register Strobe or Address Write Location Function Keyboard Controller R W Keyboard KBD_CS as Address Decode Registers Controller serted for an ac cess to any of these addresses 0071 RTC Data RTC Write strobe Address Decode Address Decode 0077 NVRAM Data Write Write Strobe Read Strobe Read Strobe 0880 DRAM Presence Detect 1 2 DRAM_PD_RD1 Read Strobe 0881 DRAM Presence Detect 3 4 DRAM_PD_RD2 Read Strobe 5 1 2 Internal Registers EPLD contains a group of internal registers which are accessed via the ISA bus MO port address shown for each register 5 1 2 1 Storage Light Register ISA Port 0808 Read Write Reset to xxxx xxx0 This register controls the HDD_LED output of the EPLD This signal normally co
137. ee 34 2 6 3 CPU to BCR Transfers sooo ect ata Acla cda dos 34 Section 3 PCI BUS 7 35 3 1 PCI Transaction Decoding 35 3 1 1 PCI Transaction Decoding Bus Command 36 3 1 2 PCI Memory Transaction Decoding By Address Range 36 3 1 3 PCI I O Transaction Decoding 38 3 1 4 ISA Master Considerations 38 3 2 PCI Transaction Details 38 3 2 1 Bus Snooping on PCI to Memory Cycles 39 3 2 2 PClto PCI Peer Transactions 39 3 2 3 PCI to System Memory Transactions 39 35 Bus Arbitration dre o QS a 41 3 4 Other PCI Considerations 41 Section 4 ISA Ee 43 eet y Pn 43 4 2 Address Ranges Oe 44 4 3 ISA Bus Concurrency 44 4 4 ISA Bus Masters and IGN PCI AD31 44 45 uma Late ot 46 4 5 1 Supported DMA Paths 46 4 5 2 ange See ee and ers a ua 46 4 5 3 Scatter Gather 46 e pto a s Eu ras van
138. eine R W gt 0 0 T ojo s gt TI 0 TI m 5000 02FE F 0370 8000 0370 57 m 372 8000 0372 8001 2012 Secondary Floppy Digital Output 37 8000 0373 8001 2013 Secondary Floppy Digital Output 374 8000 0374 8001 8014 Secondary Digital Output 37 0376 8000 0376 37 3 0377 8000 0377 37 379 8000 0379 8001 8019 IParalelPot1 37A 8000 037 8001 ParalelPot1 0378 80000378 8001 018 ParalelPot1 So 370 8000 0370 8001 8010 ParllelPot 0370 8000 0370 8001 BO1D PamllelPoti 398 8000 0398 8001 0018 5 Index Address 399 8000 0399 8001 0019 5 Data 0066 SBC 8000 03BC 8001 0010 ParalelPot3 8000 0380 8001 DO1D Parallel Pot3 Wg ojo 4 N gt e D D D D D D D EEEEEEEEEEEEEEEEEEEEEEEEEEEEE 4 0 20 3B 8000 OSBE 8001 DO1E Parallel Port 3F 8000 OSFO 8001 F010 Primary Floppy Digital Output Media Sense ojo 03 1 8000 0381 8001 F011 Primary Floppy Digital Output 8000 03 2 800
139. en they detect a PCI parity error During CPU to PCI reads the 660 bridge checks the data parity and asserts PCI PERR if it detects a data parity error 8 2 2 Illegal CPU cycles Whenever a CPU transfer which is not supported for memory or for the PCI is detected the cycle is terminated with a TEA and the illegal transfer register is set No memory or PCI cycle is initiated Read data returnedis all 1 s The CPU address is captured in the Error Address Register 8 23 SERR I O Channel Check and NMI Logic The PCI bus defines a signal called SERR which any agent can pulse This signal is to report error events within the devices not bus parity errors The signal is wired to the ISA bus bridge The ISA bus signal IOCHCK is also wired to the ISA bridge If either of these lines activate the ISA bridge asserts NMI to the 660 bridge unless the condition is masked by a register within the ISA bridge The NMI signal causes the 660 bridge to generate an interrupt to the CPU and to assert MCP to the CPU The ISA bridge contains status regis ters to identify the NMI source Software may interrogate the ISA bridge and other devices to determine the source of the error No address is associated with this type of error therefore the contents of the error address register are not defined 8 2 4 Out of Bounds PCI Memory Accesses PCI bus master runs a cycle to a system memory address above the top of physical memory no one will respond
140. ers on the WE 1 0 and MA 11 0 lines These buffers are not supplied on the reference board 13 2 2 CPU Data Bus 33 Ohm Series Resistors Due to a change in the recommended implementation of the 660 bridge 33 ohm series re sistors have been added to the reference design These resistors are placed between the 663 buffer and all other connections to the CPU data and parity bus These resistors will remain in place for the final version of the reference design MPRHO1TSU 02 171 Eon PowerPc 13 3 Reference Design Errata for Revision 1 1 of the 660 Bridge Release 2 1 of the reference design uses revision 1 1 of the 660 bridge 663 rev 1 0 and 664 rev 1 1 This section describes the workarounds associated with 660 bridge errata and gives the logic design files for the PALs that were chosen to implement the worka rounds The connectivity of these PALs is shown in the schematics in section 15 Descrip tions of the individual errata can be found in section 13 4 Note that due to physical design constraints the PALs used to implement the workarounds on the reference design are slightly different than those used to implement the workarounds on the generic system dis cussed in section 13 4 although the resulting logical function of both sets of PALs is identi cal 13 3 1 Workaround Implementation The following items were implemented on the reference design to work around the errata associated with revision 1 1 of the 660 bridge Advisory
141. eset by RESET W R Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 IRQ12 Mask Reset by RESET W R Bits 2 1 Reserved LSB Bit O Reset 83C750 W O S k k k k ke he he he he PWR REG2 STRB 83CX CS amp AO PWR_REG2 1 XD 3 amp PWR_REG2_STRB PWR_REG2 1 r XD 3 8 PWR REG2 STRB PWR_REG2 1 clrn RESET PWR_REG2 2 s XD 7 8 PWR REG2 STRB PWR REG2 2 r XD 7 amp PWR REG2 STRB PWR REG2 2 clrn RESET PWR REG2 0 s XD 0 amp PWR REG2 STRB PWR REG2 0 r XD 0 amp PWR REG2 STRB 62 MPRH01TSU 02 PowerPc EPLD VCC GLOBAL XIOW PWR REG2 0 q PWR REG2 1 q PWR REG2 0 clrn REG2 clk 83CX RESET IRQ12 MASK he he he he k S This output should NORed with 1801 and EXTACTIV signals externally tos provide a real Activity Alert to the 87C350 because of restriction of 5 pins k k K ACTIVITY IRQ1 IRQ12 MASK amp IRQ12 EXT ACTVTY
142. ess is presented in the 660 Bridge User s Manual Table 8 gives a more detailed breakdown of the reference design response to PCI memory transactions in the 0 to 2G range Note that the preferred mapping of PCI memory so that it can be accessed both by the CPU and by PCI bus masters is from 16M to 1G 2M Table 8 Mapping of PCI Memory Space Part 2 PCI Bus Address Target Resource System Memory Address Snoop Address 2G to 4G System memory 1 0 to 2G 0 to 2G 1G 2M to 2G Reserved 2 No system memory access No snoop The 660 bridge ignores PCI 16M to 10 2 PCI Memory memory transactions in this 0 to 16M PCI ISA Memory 3 range Notes 1 The 660 bridge maps PCI bus master memory transactions in the 2G to 4G range to sys tem memory and the CPU is unable to initiate PCI memory transactions to this address range so do not map devices to this PCI memory address range 2 The CPU thru the 660 bridge can not access the 1G 2M to 2G address range so do not map PCI devices herein unless the CPU will not access them 3 Transactions initiated on the PCI bus by the ISA bridge on behalf of an ISA bus master only IGN PCI AD31 asserted for an SIO are forwarded to system memory and broad cast snooped to the CPU bus from 0 to 16M If this is not an ISA bus master transaction then the 660 bridge ignores it Note that the 660 bridge will also forward PCI transactions from 16M to 2G if IGN PCI 031 is asserted during an ISA bridge mas
143. et to 2 additional ISA clock cycles of delay making the total delay equal to 6 ISA clock cycles for both the 8 and 16 bit I O recovery times Since none of the native I O devices on the reference design re quire such long recovery times the additional cycles specified by the ISA Controller Timer Register can be disabled If an ISA card requiring a long recovery time is supported the driver should insure that the recovery time is met Disable scatter gather mode and GAT mode Do not attempt to access DMA channel 4 address and byte count registers MPRHO1TSU 02 103 Setup PowerPc Always enable the ISA master and DMA buffers In order to isolate slow ISA Bus devices from the PCI bus the DMA controller uses the DMA ISA master Line Buffer This buffer can operate in single transaction or in 8 byte mode Bits 0 LE 7 BE and 1 LE 6 BE of the PCI Control register configure the line buffer for DMA and ISA masters separately It is required that the 8 byte mode be enabled for both Bits 1 1 The registers in Table 30 must be set in order for the reference design I O hardware to oper ate properly Vendors use LE bit nomenclature and nomenclature within CPU registers is BE Table 30 Summary of 510 Register Setup Configuration Address 8080 08xx MN EC o DN To Value 5 5 p We 6 BE PCI Control Register 40h _ 0 LE 1 Enable DMA Line Buffer 222222 poe Disable GAT Guaranteed Access Time
144. ever address unmunging in LE mode has no effect on the cycle because the addresses are ignored Therefore software must reverse the byte significance of the data and address encoded into the store instructions for LE mode writes to the ROM 6 4 2 1 ROM Write Protection Flash write protection must be implemented within software Port FFFF FFF1 can be used to lock out all Flash writes Writing any data to this port address locks out all Flash writes until the 660 Bridge is hardware reset In addition the Flash itself has means to permanent ly lock out changing certain sectors by writing control sequences Consult the Flash Specifi cation for details MPRHO1TSU 02 75 PowerPc 76 MPRHO01TSU 02 PowerPc Endian Modes Section 7 Endian Mode Considerations The 603 and 604 normally operate with big endian BE byte significance They have a mode of operation designed to more efficiently process code written with little endian LE byte significance The reference design supports this ability and can operate with BE oper ating systems such as AIX or LE operating systems such as WindowsNT When the system is in BE mode data is stored in memory with BE ordering When the sys tem is in little endian mode data is stored in memory with LE ordering The 660 Bridge has hardware to select the proper bytes in the memory and on the PCI and to steer the data to the correct CPU data lane A number represented in storage is sai
145. f the transfer as shown in Table 4 The transfer type decoding shown in Table 3 combines with the target decoding to produce the following System memory reads and writes e PCI I O reads and writes PCI configuration reads and writes PCI interrupt acknowledge reads PCI memory reads and writes System ROM reads and writes Various bridge control register reads and writes 26 MPRH01TSU 02 P2werPc CPU Table 3 TT 0 3 Transfer Type Decoding by 660 Bridge 60X Bus 660 Bridge Operation For CPU to 660 Bridge Operation For CPU to TT 0 3 60X Operation Transaction Memory Transfers PCI Transactions Clean block or Iwarx Address only Asserts AACK No other response No PCI transaction Write with flush SBW 1 Memory write operation PCI write transaction or burst Flush block or stwcx Address only Asserts No other response No PCI transaction 0011 Write with kill SBW or burst Memory write operation L2 invalidates PCI write transaction addressed block sync or tlbsync Address only Asserts No other response No PCI transaction 0101 Read or read with no SBR 1 Memory read operation PCI read transaction intent to cache or burst 0110 Kill block or icbi Address only Asserts 12 invalidates Asserts AACK No other response addressed block Read with intent to Memory read operation PCI read transaction modify 1000 Address only A
146. faces the CPU to the PCI bus On the motherboard the ISA bus bridge is located on the PCI bus The boot ROM is also physically located on the PCI bus but is accessed using a special protocol PCI devices are unable to activate the ROM and ROM operations do not interfere with the PCI bus protocol The reference design also provides three PCI slots by which major subsystems such as SCSI and video adaptors can be connected to the system The reference design also provides five ISA slots The motherboard is designed to an industry standard BabyAT 8 6 in by 13 in form factor It requires 5 to power most of the components The motherboard also requires 4 12 V to support some of the peripheral features Components that require 3 3V such as the PCI bus agents are supported using a regulator mounted on the motherboard to convert 5 to 3 3 1 3 1 The CPU The reference board can be configured with either the 603e or the 604 implementation of the PowerPC architecture Only one CPU may be installed at a time These CPUs use a CPU bus clock and are in general capable of running their internal clock at several different multiples of the bus clock frequency The reference design runs the PCI bus clock at a fixed frequency multiple of one half of the CPU bus clock frequency The CPU bus clock frequency is adjustable and is nominally 66MHz The reference design supports bi endian operation and is equipped with an ESP connec tor to su
147. firm ware 8 1 Interrupts 8 1 1 System Interrupt Handler There are two 8259 type interrupt controllers located in the ISA bridge These controllers receive and prioritize reference design interrupts which can be asserted by motherboard logic PCI devices or ISA devices The interrupt controller then asserts an interrupt to the 660 bridge The interrupt controller handles both ISA and PCI interrupts using the correct protocols under software control Much of the operation of the interrupt controller is programmable See the SIO data book for more information MPRHO1TSU 02 93 Exceptions P CF 2 c 8 1 2 Interrupt Handling INT_CPU ISA INT_REQ Interrupts 660 e PCI Bridge Interrupts CPU Bus Figure 23 Interrupt Handling As shown in Figure 23 the reference design interrupts are routed to the interrupt controller located inside the ISA bridge When a device signals an interrupt which is not masked in the interrupt controller 1 The ISA bridge asserts either INT_REQ or NMI_REQ to the 660 bridge 2 660 bridge asserts INT_CPU to the CPU 3 The CPU recognizes the interrupt signal INT immediately or as soon as the MSR EE interrupt enable bit in the CPU is set to 1 saves its state and then takes a precise external interrupt exception branching to either 500h or FFF0 0500h depend ing upon the Exception Prefix EP bit in the MSR The MSR EE bit is automatically set to 0 at this time 4
148. for those slots 4 ISA slot information is taken from IEEE P996 MPRHO1TSU 02 137 Electromechanical PowerPc Other requirements are 1 Overshoot on any voltage must be less than 1096 of nominal and must decay to within the regulation band within 50 msec 2 In any failure situation the power supply must shut down before the 5v output reaches 6 5V to give the motherboard a reasonable chance of surviving howev er damage may occur at any voltage above 5 5V 3 Power Good Signal Requirements e The signal must be at a TTL down level when power is applied until 2100 msec to 500 msec after the 5V supply has reached its minimum regulation level andat TTL high level thereafter as long as outputs are within regulation At turn off the Power Good signal must drop to a TTL low level before any output drops below its regulation limits The driver must be capable of driving 400 microamps or sinking 5 milliamps The rise time fall time must be less than 1 usec 10 90 4 5V rise time 1096 9095 shall be msec to 100 msec with a maximum slope of 0 75 volts msec for voltages above 1 5 volts for all loadings 5 All supply voltages shall track within 50 msec of each other measured at the 5096 point 11 1 2 Onboard 3 3V Regulator There is a 3 3 volt regulator 030 on the reference design to support the CPU and the 660 Bridge See Table 38 Note that the 3 3v on the PCI bus slots is sourced via the power sup
149. g 2 Memory Bank 0 amp 1 Addressing Mode Memory Bank 2 amp 3 Addressing Mode ae RW Mem PW E E PW E E Texas Index A1 R Index A4 R Memory Bank 4 amp 5 Addressing Mode Index A6 W 1 Memory Bank 6 amp 7 Addressing Mode Index A7 Rw 1 Games mes 00 ReteshTnerB5 Notused seetraereaBCROO 1 RAS WatchdogTimer 3 000 ar FW RW RW 3 MPRH01TSU 02 115 Setup PowerPc Table 34 660 Bridge Indexed BCR Listing Continued Bridge Contrai Regiser hew RW Byes wow pom Eee exc Eesen em 6 oer mec RT lerswss mee RW 3 ICPuplEreraess Single BECO Emre ore merpvsg on Suspend reren tme lmeepsceslawlsl 3 990309 1 In this column a long dash means that the initialization firmware does not write to this register The register is either not used not written to or the value of it depends on changing circumstances If the word Memory appears please refer to the System Memory section of the 660 User s Manual 2 The initialization firmware sets these registers depending on the information reported by the DRAM
150. g By Address Range When a PCI bus master transaction is decoded by bus command as a system memory read or write the 660 bridge checks the address range Table 7 shows the mapping of PCI bus master memory accesses to system memory This is the mapping that the 660 bridge uses when it decodes the bus command to indicate a system memory access Table 7 Mapping of PCI Memory Space Part 1 PCI Bus Address Other Conditions Target Cycle Decoded Target Address 0 to 2G IGN PCI AD31 Not Decoded N A No Response Deasserted IGN PCI AD31 System Memory 0 to 2G Snooped by caches Asserted 2G to 4G System Memory Snooped by caches Note Memory does not occupy this entire address space Accesses to unoccupied space are not decoded Unless the IGN PCI AD31 signal is asserted PCI memory accesses in the 0 to 2G dress range are ignored by the 660 Bridge There is no system memory access no snoop 36 MPRH01TSU 02 PowerPc PCI Bus cycle and the 660 bridge does not claim the transaction When the IGN PCI AD31 signal is asserted the 660 Bridge maps PCI memory accesses from 0 to 2G directly to system memory at 0 to 2G PCI memory accesses from 2G to 4G are mapped to system memory from 0 to 2G PCI memory access that are mapped to system memory cause the 660 bridge to claim the transaction access system memory and arbitrate for the CPU bus and broadcast a snoop operation on the CPU bus A detailed description of the snoop proc
151. gins the CPU bus is pipelined the FRAMEZ is held asserted more than the usual 2 PCI CLKs until the CPU data tenure begins However if the 660 bridge detects a PCI master abort condition due to no DEV SEL 4 before the CPU data tenure begins then the 660 bridge will hang the PCI bus The CPU bus transfer will complete normally Note that if the PCI target watchdog timer is enabled then the busses will not hang since the hung PCI data phase will cause the PCI cycle to terminate after 2000 PCI clocks However ifthe CPU attempts to again access the PCI bus before this point then the CPU cycle will be lost terminated on the CPU bus without executing on the PCI bus Separate the PCI GNT signal from the PCI arbiter to the 664 by a PAL Deassert PCI GNT to the 664 from the time the CPU starts a cycle to the PCI until the CPU is no longer pipelined DBB goes inactive This workaround has negligible impact on performance but may affect the maximum op erating frequency of the CPU bus 663 Memory Read 7 24 95 Under certain conditions CPU_RDL_OPEN goes low before MEM RD SMPL goes low during a CPU to memory read transfer the 663 may supply corrupted data to the CPU bus on CPU DATA 1 3 5 Add a 100 ohm series resister to the CPU RDL signal to slow its falling edge This workaround is still under analysis This workaround has no effect on performance but may affect the maximum operating frequency of the CPU bu
152. gnments Continued en mm s z 23 3 1 w fseg e OET pe EE a p E pou pu 8 pue ESI pcm pur 4 Fuss Eo sl LONE __ ON NN sss Eg eo as ET ow sssi E p por sss Ew i e s A20 B20 A21 B21 A22 B22 A23 B23 A24 B24 A25 B25 A26 B26 A27 B27 A28 B28 A29 B29 A30 B30 1 B31 A32 B32 A33 B33 A34 B34 A35 B35 A36 B36 A37 B37 A38 B38 A39 B39 A40 B40 A41 B41 A42 B42 A43 B43 A44 B44 A45 B45 A46 B46 A47 B47 A48 B48 A49 B49 A50 B50 A51 B51 A52 B52 A53 B53 A54 B54 A55 B55 A56 B56 A57 B57 A58 B58 MPRH01TSU 02 149 7 al Electromechanical PowerPc Table 50 PCI Connector Pin Assignments Continued REQ64 B60 ACK64 Notes The two card type bits B9 and B11 are connected on the riser Int A D A6 A7 B7 and B8 are connected together on the riser 11 3 15 ISA Connectors J29 J30 J31 J32 and J33 Figure 53 ISA Connector Pins are assigned as shown in Table 51 Table 51 ISA Connector Pin Assignments r Al IO CHCK 1 ROUND PE I I CS 21 ol N gt gt gt 2 2
153. gram slots Figure 41 Connector Location Diagram MPRH01TSU 02 143 7 al Electromechanical PowerPc 11 3 4 Keyboard Connector J14 The keyboard connector uses a 6 pin miniature DIN connector see Figure 42 Pins are assigned as shown in Table 40 as viewed from the back of the machine Figure 42 The Keyboard Connector Table 40 Keyboard Connector Pin Assignments RESERVED EE ww fow S N amp CLOCK LOC 11 3 5 Mouse 15 The mouse connector uses 6 pin miniature DIN connector see Figure 43 Pins 5 signed as shown in Table 41 as viewed from the back of the machine Figure 43 The Mouse Connector Table 41 Mouse Connector Pin Assignments Signal Name DATA RESERVED 144 MPRH01TSU 02 Y al P amp Electromechanical 11 3 6 Speaker Connector J13 Figure 44 1x4 Speaker Connector Table 42 Speaker Connector Pin Assignments Signal Name MINUS INPUT TO SPEAKER NO CONNECT 3 11 3 7 Power Good LED KEYLOCK Connector J12 Figure 45 1 5 Power Good LED Table 43 Power Good LED Connector Pinno Sonar Name 11 3 8 HDD LED Connector J11 1 2 Berg Figure 46 1x2 HDD LED Connector Table 44 HDD LED Connector Pino Sona Nam 1 LED VOLTAGE HDD LED drive signal low to drive LED MPRH0
154. he k he he he he e he ke This signal is the UNFREEZE Flip Flop double synchronized to the 199 40 k he e he lt DOUBLE_SNC prn RESET DOUBLE_SNC clrn VCC DOUBLE_SNC d SNC UNFREEZE q DOUBLE SNC clk ISA CLK he he he e he e ke FREEZE Flip Flop is cleared asynchronously when the UNFREEZE signal makes a high to low transition It is set once shifting has been enabled The CHANDRA ignores the UNFREEZE signal if the 601 PCLK clocks are already frozen e e he e he e e FREEZEFF prn SNC_SHIFT_ENFF q 5 RESET FREEZEFF clrn VCC FREEZEFF ena SHIFT_ENFF q FREEZEFF d CLKFF 0 q amp CLKFF 1 q FREEZEFF clk UNFREEZE k k ke he he he he he he ke
155. he Reprogram the Flash Memory screen is shown in Figure 39 To reprogram the flash enter the file name in the Specify Image Filename field and select the Reprogram the Memory option PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp A11 Rights Reserved Reprogram Flash Memory Image Filename Reprogram the Memory Go to Previous Menu Press to select item Enter data at cursor Figure 39 Reprogram the Flash Memory Screen 134 MPRH01TSU 02 PowerPc Firmware 10 4 3 4 Exit Options The two exit options at the bottom of the main menu leave the system configuration utility The two options are e Save and Exit Exit without Saving Saves any changes made in the Configure I O Devices and Set Boot Devices screens and restarts the system Proceeds with the boot process as if the configuration utility had not been entered Any changes made in Configure Devices or Set Boot Devices are lost 10 4 4 Default Configuration Values When the PowerPC 603 604 reference board is shipped from the factory it has the follow ing default configuration Console Device Serial Port 1 Serial Port 2 Boot Devices S3 Video Keyboard 9600 Baud 9600 Baud Device 1 Floppy 1 Device 2 SCSI ID 6 Device 3 IDE Drive 0 These default values also take effect whenever the system configuration in system nonvol atile RAM becomes corrupted MPRHO1TSU 02 135
156. he write data when it asserts TRDY even if IRDY is not yet as serted The manufacturer states that this problem exists on NCR part number 609 0391399 but that it has been corrected on later parts starting with part number 609 1391635 Workaround Use part number 609 1391635 or later Impact None Errata1 MIO Test Date 6 09 95 Functional The 664 MIO test function is incorrect Workaround None Impact None This errata only affects chip level testing Errata 2 Busmaster Timing Date 6 19 95 Functional When a PCI busmaster accesses system memory the 664 CPU bus arbiter samples FRAME AD 31 30 and C BE 3 0 on CPU clock edges rather than on PCI clock edges If these signals are switching at the time of sampling then the PCI bus may hang the 664 may not assert TRDY Workaround Option 1 Setthe CPU bus frequency below 50Mhz to ensure thatthe signals are not sampled while switching MPRHO1TSU 02 177 Errata PowerPc Option 2 Separate the FRAME signal to the 664 from the rest of the PCI bus by a PAL When Workaround a PCI busmaster runs a cycle hold FRAME as an input to the 664 deasserted until the second low half ofthe PCI clock so that the 664 samples it active on the rising edge of PCI CLK Option 1 affects maximum operating frequency Option 2 has no effect on performance but may affect the maximum operat
157. hronous SRAM 256K L2 71 Figure 11 Asynchronous SRAM 512K L2 71 Figure 12 Asynchronous SRAM 1M L2 72 Figure 13 Synchronous TagRAM 512K L2 72 Figure 14 Synchronous TagRAM 1M L2 72 Figure 15 Endian Mode Block Diagram 79 Figure 16 Example at Address XXXX XXXO 80 Figure 17 Example at Address XXXX XXX2 81 Figure 18 Double Byte Write Data ab at Address 84 Figure 19 Word 4 Byte Write of 0a0b0c0dh at Address XXXX XXX4 84 Figure 20 Instruction Alignment Example 89 Figure 21 Wrong Instruction Read When Unmunger is used 90 Figure 22 Instruction Stream to Switch Endian Modes 91 Figure 23 Interrupt Handling 94 Figure 24 PCI Interrupt Connections 95 Figure 25 Boot Record 120 Figure 26 Partition Table Entry 120 Figure 27 Partition Table Entry Format an Extended Partition 122 Figure 28 Partition Table Entry for PowerPC Reference Platform 122 Figure 29 PowerPC Reference Platform Partition 123 Figure 30 S
158. ile the 660 bridge grants the CPU bus to the CPU allowing it to do a snoop push Then the PCI agent again initiates the original transaction During the transaction the 660 bridge L2 cache is monitoring the memory addresses The L2 takes no action on L2 misses and read hits If there is an L2 write hit the L2 marks that block as invalid does not update the block in SRAM and does not affect the PCI transac tion L2 operations have no effect on PCI to memory bursts 3 2 2 PCI to PCI Peer Transactions Peer to peer PCI transactions are supported consistent with the memory maps of Table 6 Table 7 Table 8 and Table 9 which together show the ranges of different bus command transactions that are supported 3 2 3 PCI to System Memory Transactions PCI to system memory transactions are described in detail in the 660 Bridge User s Manu al Single and burst transfers are supported Bursts are supported without special software restrictions That is bursts can start at any byte address and end on any byte address and can be of arbitrary length Also the arbitration logic insures that the PCI does not monopo lize the PCI bus As per the PCI specification the byte enables are allowed to change on each data phase This has no practical effect on reads but is supported on writes The memory addresses linearly increment by 4 on each beat of the PCI burst All PCI devices must use only linear burst incrementing Table 10 shows which CAS line
159. ing frequency of the PCI bus TA Not Tristated for CPU Bus Targets 6 09 95 The 664 fails to tristate when a cycle is claimed using BUS CLAIM Z by a CPU bus target and the CPU bus is not pipelined and the L2 is enabled Disable the L2 when using a CPU bus target Other workarounds TBD ECIWX ECOWX and TBST 6 09 95 If an ECIWX or ECOWX bus operation is run with TBST active then the 664 incorrectly treats the cycle as a burst by providing four assertions However when an ECIWX or ECOWX bus operation is run the and TSIZE do not actually define the tranfer size the size is always 4 bytes Do not execute ECIWX or ECOWX instructions This workaround has no effect on performance or maximum frequency PCI Busmaster Disconnect on Refresh 6 19 95 The 664 asserts spurious when PCI busmaster read from memory is target dis connected due to a memory refresh request while a CPU to PCI address tenure is out standing Separate the BG1 and BG2 if MP signal between the 664 and the CPU by a PAL When a PCI busmaster access to memory is target disconnected deassert BG1 and BG2 for six PCI CLKs This workaround has negligible impact on performance but may affect the maximum op erating frequency of the CPU bus PCI Busmaster Hang 6 19 95 PCIto memory reads hang when the PCI busmaster initiates the transaction while a CPU to memory data tenure is outstanding and a CPU to PCI address te
160. is Agreement is governed by the laws of the Province of Ontario otherwise this Agreement is governed by the laws of the country in which you acquired the Reference Design All obligations and duties which by their nature survive termination or expiration of this Agreement shall remain in effect beyond termination or expiration of this Agreement and shall bind IBM you and your successors and assigns If any section or paragraph of this Agreementis found by competent authority to be invalid illegal or unenforceable in any respectfor any reason the validity legality and enforceability of any such section or paragraphin every other respect andthe remain der of this Agreement shall continue in effect so long as it still expresses the intent of the parties If the intent of the parties cannot be pre served the parties will attemptto renegotiate this Agreement andfailing renegotiation this Agreementwillthenbe terminated The headings inthis Agreement shall not affect the meaning or interpretation of this Agreement in any way No failure by IBM in exercising any right power or remedy under this Agreement shall serve as a waiver of any such right power or remedy Neither this Agreement nor any activities here under will impair any right of to develop manufacture use or market directly or indirectly alone or with others any products or services competitive with those offered orto be offered by you nor will this Agreement or any activities hereun
161. is a good cure over the large gap between the fan sink and the substrate normally the Loctite does not cure well with a gap of over 0 020 inch 4 Place a 5 6 lb weight on top of the fan sink substrate assembly for at least five minutes taking care that the fan sink remains parallel to the substrate 5 Remove the weight and allow the assembly to sit undisturbed for at least another five min utes The Loctite takes about 10 minutes to fully set up It then takes 24 hours at room temper ature to cure fully but the assembly can be handled after the initial 10 minute setup time MPRHO1TSU 02 139 7 Electromechanical PowerPc 11 2 1 2 604 Fan Sink Experimentation Some experimentation may be required to determine the best placement and size of the adhesive dots required to attach the fan sink to the 604 The following experimental proce dure is recommended 1 Dispense Loctite 384 dots on the substrate using four dots located at the four corners of the substrate 2 Place a piece of mylar over the flat pack a piece of overhead projection material works well 3 Place the fan sink in position 4 Remove the fan sink and look at how the dots spread out 5 Remove the mylar and wipe the excess Loctite from the flat pack 11 2 1 3 Thermal Requirements for the 3 3v Regulator The 3 3v voltage regulator is assembled with a heat sink on the pass element which must be maintained at an operating junction temperature equal to or less than 1
162. issues The reference design contains this reference design Technical Specification Gerb er format physical design files on an 8mm tape electrical device model files in Cadence format system firmware guidelines schematics contact information for commented boot ROM source code and such other device and system information as is deemed helpful 1 1 2 Reference Board The PowerPC 603 604 Reference Board reference board is the physical implementation of the motherboard part of the reference design It includes the reference design the popu lated motherboard the boot ROM and other components as appropriate 1 1 3 Reference Firmware The PowerPC 603 604 Reference Firmware reference firmware is described in the refer ence design and consists of the commented source code of the software contained in the boot ROM This is available from IBM as discussed in section 10 1 MPRHO1TSU 02 17 Introduction PowerPc 1 1 4 Reference System The PowerPC 603 604 Reference System reference system consists of a complete 603 604 PowerPC computer system including the motherboard enclosure power supply cooling devices and such other adaptors and peripherals as are described in the detailed product offering 1 2 Purpose The reference design is aimed at the market for low cost desk top PowerPC personal com puters The motherboard is sized to fit within a BabyAT form factor enclosure although the enclosure may need to be modified to provide
163. ld work satisfactorily see Table 1 for a list of peripherals and materi als Reference boards do not come with the all of the required peripherals cables speak er indicator LEDs switches and such that are needed to configure a properly working sys tem Table 1 outlines the generic requirements for peripherals and gives examples of some de vices that have been used for testing It is not a recommendation of any particular vendor The purpose of this table is to outline at least one set of peripherals that may be used to begin testing Table 1 does not include cables for a parallel port indicators a switch or a speaker An IBM 3101 asynchronous terminal or equivalent is required for testing with the bring up driver BUD code Settings are 8 bit no parity one stop bit and 9600 baud VT100 or VT52 emulator terminals may be acceptable It is desirable to also have a video monitor for BUD tests The boot code will boot with either an async console a video on motherboard or both 1 5 Reference Design Level This documentation supports the release 2 1 version of the 603 604 reference design and reference board Except as noted the information herein is believed to be correct for the release 3 0 version of the reference design once all of the errata are cured see section 13 Errata for the reference design roadmap The reference board schematics are of the release 2 0 reference board and correctly show the workarounds that are ins
164. lements a 2M ROM space from 4G 2M to 4G The actual ROM is 512K device located at 4G 2M The ROM is attached to the 660 bridge via the PCI AD lines This mode is required when using the Intel SIO ROM device writes and write protect commands are supported See the 660 Bridge User s Manual for more information The ROM device attaches to the 660 bridge by means of control lines and the PCI AD 31 0 lines When a CPU bus master reads from the ROM the bridge masters a BCR transaction during which it reads the ROM and returns the data to the CPU CPU writes to the ROM and ROM write protection operations are also forwarded to the ROM device Although connected to the PCI AD lines the ROM is not a PCI agent The ROM and the PCI agents do not interfere with each other because the ROM is under bridge control and MPRHO1TSU 02 33 CPU P2werPc the bridge does not enable the ROM except during ROM cycles The bridge accesses the ROM by means of BCR transactions Other PCI devices cannot read or write the ROM be cause they cannot generate BCR transactions 2 6 1 CPU to ROM Read At power on the 603 604 CPU comes up in BE Mode with the L1 cache disabled and be gins fetching instructions using 8 byte single beat reads at address FFFO 0100 4G 1M 100h The reference design logic also resets to BE mode The system ROM address space is from 4G 2M to 4G Since the size of the installed ROM is less than 2M 512k it is mirrored every 5
165. letes 2 5 2 1 Eight Byte Writes to the PCI Memory and I O The 660 Bridge supports 1 byte 2 byte 3 byte and 4 byte transfers to and from the PCI The 660 Bridge also supports 8 byte memory and writes writes only not reads to the PCI bus This enables the use of the 604 store multiple instruction to PCI devices When an 8 byte write to the PCI is detected it is not posted initially Instead the CPU waits until the first 4 byte write occurs then the second 4 byte write is posted If the PCI retries on MPRHO1TSU 02 31 CPU P2werPc the first four byte transfer or a PCI master access to system memory is detected before the first 4 byte transfer then the CPU is retried If the PCI retries on the second 4 byte transfer then the 660 Bridge retries the PCI write 2 5 3 CPU to PCI Memory Transactions CPU transfers from 3G to 4G 2M are mapped to the PCI bus as memory transactions 2 5 4 CPU to PCI I O Transactions CPU transfers from 2G 16M to 3G 8M are mapped to the PCI bus as I O transactions In compliance with the PCI specification the 660 Bridge master aborts all transactions that are not claimed by a PCI agent 2 5 5 CPU to PCI Configuration Transactions The reference design allows the CPU to generate type 0 and type 1 PCI configuration cycles The CPU initiates a transfer to the appropriate address the 660 bridge decodes the cycle and generates a request to the PCI arbiter in the SIO When the PCI bus is acquired the 6
166. lized The 660 bridge does not require reconfiguration when port 4Dh in the ISA bridge is uti lized to reset the native I O and the ISA slots 102 MPRHO01TSU 02 PowerPc Setup 9 3 ISA Bridge SIO Initialization The reference design uses an Intel 82378ZB SIO as the ISA bridge The following informa tion applies to SIO compatible ISA bridges The SIO chip should be configured prior to any other PCI bus agent The SIO PCI arbiter is automatically enabled upon power on reset During power on reset the SIO drives the A D 31 0 3 0 and par signals on the PCI bus The system EPLD uses the decode circuits in the SIO that produce the signals EC SADDR 2 0 and UBUSCOE to decode the motherboard register addresses For this rea son utility bus A and B decode registers must be initialized as shown in Table 30 The ISA clock divisor must be set as indicated prior to running any CPU to PCI transactions If the configuration information is stored in Flash this should pose no problem The SIO must be programmed so that interval timer 1 operates in mode 2 with a period of approximately 15 microseconds This timer controls the ISA refresh interval It must be pro grammed at least 200 microseconds before any access to ISA DRAM is attempted PCI memory write cycles destined for ISA can use a 32 bit posted write buffer in the SIO Bit 2 ofthe PCI control register controls the enabeling of the posted write buffer The default power
167. me field and the reserved1 area The 32 bit entry point offset little endian is the offset into the image of the entry point of the PowerPC Reference Platform boot program The entry point offset is used to MPRHO1TSU 02 123 Firmware PowerPc allocate the Reserved1 space The reserved1 area from offset 554 to Entry Point 1 is re served for implementation specific data and future expansion The 32 bit load image length little endian is the length in bytes of the load image Theload image length specifies the size of the data physically copied into the system RAM by the firmware The flag field is 8 bits wide The MSb in the field is allocated for the Open Firmware flag If this bit is set to 1 the loader requires Open Firmware services to continue loading the operating system The second MSb is the endian mode bit If the mode bit is 0 the code in the section is in big endian mode Otherwise the codes is in little endian mode The implication of the en dian mode bit is different depending on the Open Firmware flag If the Open Firmware flag is set to 1 the mode bit indicates the endian mode of the code section pointed to by the load image offset and the firmware has to establish the hardware endian mode according to this bit Otherwise this bit is just an informative field for firmware The OS ID field and partition name field are used to identify the operating system located the partition The OS ID field has the nume
168. meet all of the suggested design rules but this information is included to guide the designer in case some tradeoffs have to be evaluated Clock nets CPU bus nets and timing critical nets PCI bus nets Noise sensitive nets Other nets 12 2 Clock Nets 1 Clock nets are the most critical wiring on the board Their wiring requirements should be given priority over the requirements of other groups of signals Clock nets are to have a minimum number of vias No clock wires may be routed closer than one inch to the edge of the board Clock nets with more than two nodes devices connected to them are to be daisy chained Stubs and star fanouts are not allowed 164 MPRH01TSU 02 PowerPc Physical Design 5 Clock nets are to be routed as much as possible on internal signal planes 6 Where series termination resistors are required place them as close as possible to the clock generator 7 Route a ground trace as a shield in the adjacent wiring channel on both sides of the clock trace It is a good practice to periodically every inch or so connect these shield traces to the ground plane Completely surround the clock trace with shield traces 8 Table 15 shows the length and tolerances of the clock nets All dimensions are shown in inches The Design Rule column shows the guideline and the Reference Board col umn shows the actual length of the net on the reference board Table 58 Clock
169. n Section 1 Introduction This document provides a detailed technical description of the PowerPC 603 604 Refer ence Design and is intended to be used by hardware software test simulation and other engineers as a first source of information Software developers should read through the entire document because pertinent facts may be located in hardware sections The focus of this document is mainly the motherboard electronics and firmware Where ap propriate this document references detailed information in other documents Consult other documents for information on specific MO devices such as hard drives CD ROMs L2 cache cards video cards etc that comprise a total system Recommendations for memory mappings software implementations and the like are only recommendations and may or may not represent the algorithms implemented in boot code or operating systems Note This document contains several references to the 603 604 Reference Design Power Management Specification however the specification was not yet available at the date of printing 1 1 IBM Reference Products IBM offers several different PowerPC reference products for a given PowerPC system 1 1 1 Reference Design The PowerPC 603 604 Reference Design reference design is composed of both the in tangible design and the documentation describing that design The reference design docu mentation addresses the motherboard electronics firmware and various system related
170. n the reference design supports 8 byte CPU to PCI writes that are aligned on an 8 byte boundary The bridge does not sup port CPU bursts to the PCI bus When the 660 bridge decodes a CPU access as targeted for the PCI the 660 bridge re quests the PCI bus Once the SIO grants the PCI bus to the 660 bridge the bridge initiates the PCI cycle and releases the bus CPU to PCI transactions that the PCI target retries cause the 660 Bridge to deassert its PCI REQX the Bridge follows the PCI retry protocol The Bridge stays off of the PCI bus for two PCI clocks before reasserting _ or FRAME if the PCI bus is idle and the PCI GNT to the Bridge is active 2 5 1 CPU to PCI Read If the CPU to PCI cycle is a read a PCI read cycle is run If the PCI read cycle completes the data is passed to the CPU and the CPU cycle is ended If the PCI cycle is retried the CPU cycle is retried If a PCI master access to system memory is detected before the PCI read cycle is run then the CPU cycle is retried and no PCI cycle is generated 2 5 2 CPU to PCI Write If the CPU to PCI cycle is a write a PCI write cycle is run CPU to PCI writes are not posted as per the PCI Local Bus Specification version 2 1 If the PCI transaction is retried the Bridge retries the CPU CPU to PCI memory writes are posted so the CPU write cycle is ended as soon as the data is latched If the PCI cycle is retried the Bridge retries the cycle until it comp
171. n Power Manage ment Guide System Clock Interface Signals FRZ DATA OUT 90 ISA CLK Interrupt request 12 input Connect to system IRQ12 the mouse interrupt Also see the 603 604 Reference Design Power Management Guide Freeze data out Serial data stream to MPC970 clock chip See MPC970 data sheet ISA clock Used to clock the freeze serial data stream to the MPC970 clock chip See the MPC970 data sheet Also see the 603 604 Reference Design Power Manage ment Guide Power Management Signals not used in release 2 0 or 2 1 MPRHO01TSU 02 55 EPLD PowerPc Table 16 Signal Descriptions Continued Signal Name Pin Description Power Management Signals not used in release 2 0 or 2 1 83CX_RESET Power management controller reset No connect or con nect as shown in the 603 604 Reference Design Power Management Guide ACTIVITY Activity No connect or connect as shown in the 603 604 Reference Design Power Management Guide CMD_STATE 8 Power manangement controller command state No con nect or connect as shown in the 603 604 Reference De sign Power Management Guide EXT_ACTVTY 3 External activity No connect or pull low or connect as shown in the 603 604 Reference Design Power Manage Guide IO_STROBE 99 O strobe No connect or connect as shown in the 6mA 603 604 Reference Design Power Management Guide PROC_RDY 83 Power management controller ready No connect
172. not populated R421 R422 R427 and R428 R377 MPRHO1TSU 02 25 CPU P2werPc 2 1 2 604 CPU The reference design is initially configured for DRTRY mode and can be reconfigured to no DRTRY mode by populating R440 0 ohm The 604 version of the reference design is initially configured to run at 2 1 604 internal clock to bus clock ratio at 132MHz 66MHz CPU PLL CFG 0 3 is set to 0100 The 604 can be configured to run with different internal to bus clock ratios as described in the 604 User s Manual The clock generator can be configured to produce different frequencies Some examples are shown in Table 2 Table 2 Example Clock Generator Frequencies CPU Internal Clock MHz CPU Bus Clock MHz PCI Bus Clock MHz Crystal Y2A MHz On the 604 version of the reference board the following are populated R423 10k and R425 R426 and R428 with with 1k ohm resistors and R377 with 0 ohm The following are not populated R421 R422 R424 and R427 2 2 System Response by CPU Bus Transfer Type All access to the rest of the system is provided to the CPU by the 660 Bridge Table shows the 660 Bridge decoding of CPU bus transfer types Based on TT 0 3 the 660 Bridge re sponds to CPU bus master cycles by generating a read transaction a write transaction or an address only response The 660 Bridge ignores TT 4 when it evaluates the transfer type The bridge decodes the target of the transaction based on the address range o
173. ntrols the hard disc drive activity LED 07 06 05 04 03 02 01 60 8 5 Hard Disk Activity Light Reserved Bit 0 Hard Disk Activity Light 0 Turn light off negate HDD_LED 1 Turn light on assert HDD_LED 52 MPRH01TSU 02 PowerPc EPLD 5 1 2 2 Power Management Control Register 1 SA Pon 082A 0505 4 009 oo ee Data Bit Command to 87C750 I O Strobe Key Reserved This register is part ofthe power management system For a detailed functional description of the operation of this register see the 603 604 Reference Design Power Management Specification 5 1 2 3 Power Management Control Register 2 SA Pot 0828 i os os o 95 009 oo so E MSB Reset PM Controller Status Reserved IRQ12 Mask Reserved Reserved Reserved CPU1 ROM Completed This register is part of the power management system For a detailed functional description of the operation of this register see The 603 604 Reference Design Power Management Specification 5 1 2 4 Freeze Clock Register FCR Low Pot 0860 65554325155 so SES Freeze Clock Register 7 0 See section 5 1 2 5 5 1 2 5 Freeze Clock Register FCR High Pot 0862 p7 pe ps p ps pz p 00 Lss NNNM MSB Freeze Clock Register 12 8 Reserved MPRHO01TSU 02 53 EPLD PowerPc The freeze clock register FCR is a 13 bit register that is accessed by the s
174. nts will be selected 9 4 1 Multi function Adaptors The 660 Bridge supports multi function adapters It passes the address of the load or store instruction that causes PCI configuration cycle unmodified except the three low order bits are in little endian mode and the two low order address bits are set to zero in either endian mode Therefore addresses may be selected with non zero CPU address bits 21 23 corresponding to PCI bits 10 8 to configure multi function adaptors For example to configure device 3 in slot 1 use address 8000 03XXh To configure device 7 in slot 2 use address 8084 07XXh 9 4 2 PCI to PCI Bridges The 660 bridge supports both 0 and Type 1 configuration cycles MPRHO1TSU 02 107 Setup PowerPc 9 5 Reference Design Combined Register Listing 9 5 1 Direct Access Registers Table 33 contains a summary listing of the registers that are physically located in the refer ence design motherboard These registers are in general accessed using single CPU transfers There is an additional set of registers see Table 34 located in the 660 bridge which are accessed using pairs of CPU transfers Table 33 Combined Register Listing ron te Mode Addr Mode Addr To 6 4 0000 80000000 80000000 CHO and Current Adar RW so 0001 80000001 80000001 CHOBaseandCuren Cm Rw SIO 0002 80000002 80000002 DMA1CH1 Ba
175. nure is outstanding Drive CPU ADDR 0 low on the CPU bus clock following the assertion of AACK This workaround has no effect on performance or maximum frequency 178 MPRH01TSU 02 PowerPc Errata Errata 7 Bus Hang During L2 Read Hit CPU to Memory PCI to Memory Date 7 11 95 Functional If a PCI busmaster begins a system memory access while a CPU to memory address tenure is pending and an L2 read hit data tenure is pending then the CPU and PCI busses will hang and TRDY are never asserted Workaround Separate the BG1 and BG2 if MP signal between the 664 and the CPU by a PAL Deassert BG1 and BG2 on the clock following the assertion of AACK If asynchro nous SRAM is used in the L2 then also deassert BG1 and BG2 if MP while DBB is active from the time PCI GNT goes inactive until ABB has asserted twice Impact This workaround has negligible impact on performance but may affect the maximum op erating frequency of the CPU bus Errata 8 Back To Back PCI Busmaster Write Date 6 22 95 Functional The CPU and PCI busses hang if a PCI busmaster write to memory begins while the CPU is asserting BR and the CPU address bus is becoming free from the broadcast snoop caused by a previous PCI busmaster write to memory Workaround Separatethe 1 and BR2 if MP signal from the 664 to the CPU by a PAL Deassert BR1 and 2 while PCI C
176. o a CPU read assume one of the transfer types in Table 3 that produce the read response from the 660 bridge Likewise references to a CPU write refer to those transfer type that produce the write response MPRHO1TSU 02 27 CPU P2werPc 2 3 System Response by CPU Bus Address Range The 660 Bridge determines the target of a CPU bus master transaction based on the CPU bus address range as shown in Table 4 The acronym BCR means bridge control register Table 4 660 Bridge Address Mapping of CPU Bus Transactions Other CPU Bus Address Target Transaction Target Bus Address System Memory 0000 0000h to 7FFF FFFFh 0000 0000h lo pm FFFFh 2G to 2G 8M Contiguous PCI I O Transaction BCR Transaction 0 to 8000 0000h to 807F FFFFh Mode or 0000 0000h to pum FFFFh 4 PCI Configuration Non Contigu Type 1 Transaction 0 to 64K ous 0000 0000h to 0000 FFFFh Mode 2G 8M to 2G 16M PCI Configuration PCI Configuration Space 8080 0000h to 80FF FFFFh Type 0 Transaction 0080 0000h to 00FF FFFFh 2G 16M to 3G 8M PCI I O Transaction 16M to 1G 8M 8100 0000h to BF7F FFFFh 0100 0000h to 3F7F FFFFh 3G 8M to 3G BCR Transactions 1G 8M to 1G 3 6 BF80 0000h to FFFFh and PCI Interrupt 80 0000h 3FFF FFFFh Ack Transactions 3G to 4G 2M PCI Memory 0 to 1G 2M C000 0000h to FFDF FFFFh Transaction 0000 0000h to 3FDF FFFFh 4G 2M to 4G Direct Attach BCR Transaction 0 to 2M FFEO 0000h to FFFF FFFFh ROM Read 0000
177. on that is not initiated by one of the three possible agents besides the 660 bridge and the SIO If the PCI transaction was not initiated by the 660 bridge and if it is a memory transaction then the 660 bridge assumes that it is a system memory transaction initiated on the PCI bus by the SIO on behalf of an ISA bus master and so forwards it to the correct system memory address in the 0 to 16M range As a consequence of this design the ISA bridge must be programmed to map ISA DMA that is bound for system memory to a PCI memory transaction using the 0 to 2G address range rather than the apparently correct 2G to 4G range Since the DMA sourced PCI transaction also causes IGN PCI 4031 to be asserted during the address phase of a PCI transaction initiated by the ISA bridge the 660 bridge will not do the usual inversion of the highest order address bit but will forward the transaction to system memory in the 0 to 2G range Another consequence of the design is that the ISA bridge can not initiate peer to peer PCI memory transactions because no matter what the PCI address is it will be claimed by the 660 bridge if the address is that of a populated memory location and mapped to system memory possibly causing various inappropriate results These are the only limitations on the normal operation of the ISA bridge that are caused by the IGN PCI AD31 design and there are no implications for other PCI or ISA agents which are totally unaffecte
178. ons are the same as those produced by aligned or unaligned word and half word loads and stores Since move multiples strings and unaligned transfers cause machine checks in LE mode they are not of concern in the BE design 88 MPRH01TSU 02 PowerPc Endian Modes 7 10 Instruction Fetches and Endian Modes Most instruction fetching is with cache on Therefore memory is fetched eight bytes wide Figure 20 shows the instruction alignment Example 8 byte instruction fetch 11 12 efgh at address XXXX XXX0 Big Endian Little Endian 603 604 Swap Off Memory 603 604 Swap On Memory LSB h f 7 6 5 4 3 2 1 0 O S O 8 g e d C b a Figure 20 Instruction Alignment Example MPRH01TSU 02 89 Endian Modes PowerPc It is possible in rare cases to fetch instructions with 4 byte aligned transfers when the cache is turned off In that case the 603 604 does not munge the address in LE mode The memory controller does not differentiate between instruction and data fetches but the un munger is ineffective because the memory is always read 8 byte wide and data is pres ented on all 8 byte lanes If the unmunger were used the wrong instruction would be read The net result is illustrated in Figure 21 Example 4 byte instruction fetch 2 efgh at address XXXX XXX4 Big Endian Little Endian 603 604 Swap Off Memory 603 6
179. ontroller function of two 8259s PCI bus arbiter Functions as PCI target during programming and ISA target cycles and as bus mas ter during DMA or ISA master cycles Generates ISA_REFRESH signal to refresh ISA bus DRAM MPRHO1TSU 02 43 ISA Bus PowerPc 4 2 Address Ranges The ISA bus address ranges which may be separately enabled in the ISA bus bridge for forwarding to the PCI bus are 0 512K 512K 640K 640K 768K 768K 896K in 8 ranges of 16 each 896K 960K 1M xM where gt or 16 with the hole see the SIO data book The hole be 64K or 8M If an ISA DMA produces an address in the 0 16M range and this address is enabled in the ISA bridge for forwarding to the PCI the ISA bridge will initiate a PCI transaction which the 660 bridge will forward to system memory The 660 bridge uses medium timing when claiming ISA master originated cycles on the PCI It does not use subtractive decoding Hence ISA masters can only communicate with other ISA devices or system memory They may not communicate with PCI devices Warning The software should not map any PCI memory at PCI addresses which ISA mas ters can create those addresses between 0 16M which are programmed for forwarding from ISA to PCI This is because contention would result between the device mapped at that address and the 660 bridge Alternatively stated ISA masters should not be allowed to create acces
180. ot use PCI LOCK while in 603 1 1 mode This workaround has no effect on performance or maximum frequency 663 Parity Error Detection 8 4 95 Parity errors on the CPU and memory data busses are only reported by the 663 if there are an odd number of bytes containing parity errors All single single bit errors in the number of bytes transferred that beat are reported but double bit arrors may not be re ported even if the two errors are in different bytes TBD This errata has no effect on performance or maximum frequency 181 PowerPc Errata 13 4 2 PAL Design Files The following PAL equations describe the 660 team s implementation of the example logic equations con tained in the workarounds for the errata These are PALASM design files Note that the PAL pinouts may not match the reference design PAL pinouts 13 4 2 1 HPP1 Design File TITLE HPP pds PATTERN REVISION 1 0 COMPANY IBM DATE 06 29 95 CHIP PALCE16V8 Declarations Predefined PIN 1 PCI_CLK CLOCK PIN 10 GND GROUND PIN 11 REG_OE OUTPUT ENABLE FOR REGISTERED OUTPUTS PIN 20 Inputs PIN 2 IRDY_ INPUT from PCI bus PIN 3 TRDY_ INPUT from PCI bus PIN 4 PCI_CLK INPUT PIN 5 STOP INPUT from PCI bus PIN 6 PCI INPUT from PCI bus arbiter PIN 7 INPUT PIN 8 INPUT PIN 9 INPUT outputs PIN 12 PCI FRAME COMB CONBINATION
181. ot write the data to memory The memory select error bit in the error status 1 register bit 5 in index C1h is set in both cases All CPU to memory writes are posted and can be pipelined The 660 Bridge supports all CPU to memory bursts and all single beat transfer sizes and alignments that do not cross an 8 byte boundary which includes all memory transfers initi ated by the 603 604 CPU 30 MPRH01TSU 02 P2werPc CPU 2 4 1 LE Mode The bridge supports all transfer sizes and alignments that the CPU can create in LE mode however all loads or stores must be at natural alignments in LE mode or the CPU will take an alignment exception Also load store multiple word and load store string word instruc tions are not supported in the CPU in LE mode 2 5 CPU to PCI Transactions Since all CPU to PCI transactions are CPU memory mapped software must in general uti lize the EIEIO instruction which enforces in order execution particularly on PCI and configuration transactions Some PCI memory operations can be sensitive to order of ac cess also See the 660 Bridge User s Manual All addresses from 2G to 4G including ROM space must be marked non cacheable See the PowerPC Reference Platform Specification The reference design supports all PCI bus protocols during CPU to PCI transactions The reference design supports all CPU to PCI transfer sizes that do not cross a 4 byte boundary and to support the 604 store multiple instructio
182. ower Connector AUX5 ON OFF Connector PCI Connector ISA Connector SIMM Connector 1x2 Power Switch Connector 1x2 Power Up Configuration Connector L2 SRAM Module Connector 2x8 RISCWatch Connector Signal and Power Layers Typical Wiring Channel Top View PowerPC 603 604 Board Fabrication Power Plane Split PCI Interrupt Slot 0 Connections Generic Implementation PAL Installation PowerPc 144 Pe ey Ce 144 z Aku Qs da 145 145 a i EE 145 146 7 146 a i V i O gA 147 147 148 148 ME THER 150 2 DLP 152 a aM ue 154 7 154 ACT ee 0 155 157 161 7 162 ed 163 164 ee 7 171 oe 188 8 50 02 PowerPc Tables Table 1 Quickstart Peripheral List 23 Table 2 Example Clock Generator Frequencies 26 Table TT 0 3 Transfer Type Decoding by 660 Bridge 27 Table 4 660 Bridge Address Mapping of CPU Bus Transactions 28 Table 5 660 Bridge Address Mapping of CPU Bus Transactions 33 Table 6 Reference Design Responses to PCI C 3 0 Bus Commands 36 Table 7 Mapping of PCI Memory Space Part 1
183. p All Rights Reserved SCSI Devices None None None None None None IBM MXT 540SL H SCSI Device SCSI Device SCSI Device SCSI Device SCSI Device SCSI Device SCSI Device Ou fF N P Oo Previous Menu Press to select item Press Enter to perform action Figure 35 SCSI Devices Screen 130 MPRH01TSU 02 PowerPc Firmware Set Boot Devices The boot devices menu allows the user to select which devices are queried for boot images and in what order they are selected for boot Allowable selections are one of the two floppy disk drives any of six SCSI drive ID numbers either of two IDE disk drives or no device selected The default configuration is shown in Figure 36 In this configuration the system will attempt to find a boot image on the first floppy disk drive If this fails the system will attempt to boot from the SCSI device programmed to SCSI ID 6 If this fails the system will attempt to boot from IDE drive zero master PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved Boot Device Selection Set Boot Device Set Boot Device Set Boot Device Set Boot Device 1 Floppy 1 2 SCSI ID 6 3 IDE Drive O 4 None Go to Previous Menu Press T to select item Press amp to change item Figure 36 Boot Devices Screen If the system fails to find a valid boot image as discussed in section 10 3 on any of the
184. pes and frequencies discussed but to supplement standard practice by pointing out sensitive and critical areas Some discussion of the IBM imple mentation of the reference board is also included to establish the context for the wiring guidelines 12 1 1 Construction The general construction of the PowerPC 603 604 reference board reference board is shown in Figure 59 It is constructed with two high frequency signal layers in the center two power planes and two external general purpose signal layers Signal layer general purpose Power plane Signal layer clocks and high frequency Signal layer clocks and high frequency Power plane ground Signal layer general purpose Figure 59 Signal and Power Layers MPRHO1TSU 02 161 Physical Design PowerPc A top view of a typical wiring channel as implemented on the reference board is shown in Figure 60 all dimensions are shown in inches Minimum trace width is 006 at 1 1 and minimum space width is 004 at 1 1 Space 004 Trace 006 Wiring Channel Adjacent Wiring Channel Figure 60 Typical Wiring Channel Top View For fabrication information see Figure 61 162 MPRHO01TSU 02 PowerPc Physical Design 0 5 oz Foil vs 2 oz Foil oc 1 oz 9 Signal 1 oz Foil e 2 oz Foil oos Signal 0
185. pport RISCWatch debugging and monitor systems Consult your IBM representative for currently available choices of CPU type and operating frequency 1 3 2 IBM27 82660 Bridge The IBM27 82660 Bridge 660 Bridge chipset supplies many of the functions of the refer ence design The 660 Bridge interfaces the CPU to the L2 system memory the PCI bus the ROM and other reference design components 1 3 3 12 Cache The reference design supplies an L2 cache controller located inside the 660 Bridge chip set The motherboard provides a socket for an SRAM module and the L2 tag RAM 16K x 15 synchronous is supplied installed on the board The L2 is a unified write thru direct MPRHO1TSU 02 19 Introduction PowerPc mapped look aside cache that supports 1M of SRAM to cache the low 1G of CPU memory space The L2 supplies data to the CPU bus on write hits and snarfs the data updates the SRAM data while the memory controller is accessing DRAM memory on read write mis ses It snoops PCI to memory transactions Typical read performance with 9ms SRAM is 3 1 1 1 followed by 2 1 1 1 on pipelined reads for sync Clock Gen Power System Mgt Cntrlr EPLD Strobes 970 870750 5130 Keyboard KYBD RTC Mouse Pp gt ESP Connector DC1385 8042 Mouse Data Addr Cntrl X Bus
186. r 0881 Read Only This register indicates the ID bits associated with SIMMs 3 and 4 07 06 05 04 03 D2 01 60 8 MSB ID Bits 7 0 Bits 7 4 SIMM 4 ID bits See Table 14 Bits 3 0 SIMM 3 ID bits See Table 14 Table 14 DRAM Module Presence Detect Bit Encoding Presence Detect Bits DRAM Module Identification 1 o 0 4 1 365 70ns 1 o 1 1 8MB 2Mx36b 70ns 1 0 1 0 16MB 4Mx36b 70ns 1 1 0 1 32MB 8Mx36b 70ns MPRHO1TSU 02 49 ISA Bus PowerPc 4 7 Miscellaneous 4 7 4 Speaker Support The reference design has a connector for a small speaker The speaker output is driven by the timer 2 signal from the ISA bridge The intended speaker is a typical PC type 8 ohms and 5W 50 MPRHO01TSU 02 PowerPc EPLD Section 5 System I O EPLD Note The System I O EPLD generates system control register access signals from X bus I O port transactions supports power management and provides various other system func tions In this section the system I O EPLD is referred to as the EPLD The EPLD is a programmed Altera EPM5130QC100 electrically programmable logic de vice For timing and electrical specifications see that data sheet 51 System Register Support The EPLD supports both internal and external registers 5 1 4 External Register Support The EPLD supports a group of external registers which are latches or other devices that are physically locat
187. r Errata 7B 11 13 TA_CNTO TA_CNTO TA_ TA_CNTO DBB_ TA_ TA_CNT1 TA_CNTO TA_ TA_CNT1 DBB_ MASK BG3 TA CNTO TA_CNT1 SRAM DBB_ ERR 13 ABB SRAM DBB ERR 7B PCI IN DBB ERR 11 MASK 7A ABB DEL ABB DBB ERR 7A MASK 7B ABB DEL ABB DBB ERR 7A poke kc ke k k k k k k k k K k k K k K k K K K KO KO KO KO K e e ke ERRATA 7 fix for Async caches MASK 7B feeds wires to CPUPAL MASK BG3 input to be included in BG equation shown below BG_OUT_ BG IN MASK_BG2 Errata 5 MASK BG1 for Errata 5 ABB DEL ABB for Errata 7 MASK BG3 DBB_ for Errata 7 Asych cache fix ke He ce e ce k k k k k k k k k k k k KK k K K K k K KK k K K e k k K S k kO K K K KO He He K K KO He K e He ke KO K e KO e K K KO KK MASK_7A PCI GNT IN ABB DEL ABB MASK 7B 7A DEL ABB MASK 7B ABB DEL ABB MPRHO1TSU 02 187 PowerPc 13 4 3 Workaround PAL Installation Figure 63 shows a typical installation of the workaround PALs in a generic 603e 604 uniprocessor system PAL connections shown without an asterisk do not require any nets to be cut Merely connect the PAL pin to the an existing net eg or in the case of
188. r IBM representative This material is available free of charge with a signed li cense agreement 10 2 Power On System Test The Power On System Test POST code tests those subsystems of the reference board which are required for configuration and boot to ensure minimum operability Tests also as sure validity of the firmware image and of the stored system configuration 10 2 1 Hardware Requirements In addition to the reference board the firmware requires the following peripherals to be installed as adapter cards Serial Port 1 Address 0x3F8 COM1 Interrupt IRQ 4 Serial Port 2 Address Ox2F8 COM2 Interrupt IRQ 3 Floppy Controller Address 0x3F0 Primary Floppy Mode PC AT or PS 2 IDE Controller Address 0x1F0 Primary IDE 10 3 Boot Record Format The firmware will attempt to boot an executable image from devices specified by the user See section 10 4 for details on specifying boot devices and order MPRHO1TSU 02 119 PowerPC Reference Platform Specification details a structure for boot records which can be loaded by the system firmware This specification is described in the following sec tions 10 3 1 Boot Record The format of the boot record is an extension of the PC environment The boot record is composed of a PC compatibility block and partition table To support media interchange the PC compatibility block may contain an x86 type program The entries in the partition table identify th
189. r the system configuration utility The configuration menu will also be entered if there is no bootable de vice present or if the configuration stored in the system non volatile RAM is not initialized or is corrupt 10 4 3 Main Menu Figure 31 shows the main menu for the system configuration utility Selections on the menu are highlighted by using the up and down arrow keys on the keyboard and are chosen with the Enter key Each choice is detailed in the following sections PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved Main Menu System Configuration Menu Run a Program Reprogram Flash Memory Save and exit Exit without saving Press 4 to select item Press Enter to perform action Figure 31 Configuration Utility Main Menu 126 MPRH01TSU 02 PowerPc Firmware 10 4 3 1 System Configuration Menu Figure 32 shows the System Configuration menu which has choices to display and change the default state of the reference board on boot Each menu item is discussed in the follow ing sections PowerPC 604 Reference Board System Firmware C Copyright 1994 IBM Corp All Rights Reserved System Configuration Menu System Information Configure I O Devices View SCSI Devices Set Boot Devices Set Date and Time Previous Menu Press to select item Press Enter to perform action Figure 32 System Configuration Menu MPRHO1TSU 02 1
190. rd to the design documentation provided hereunder itis understood that you intend to use such documentation solely for the pur poseofdesigning yourown PowerPC compatible products testing yourdesigns and making yourownindependentdetermination of wheth er you wish to eventually manufacture PowerPC compatible products commercially In accordance with this understanding IBM hereby grants you the right to a use the design documentation for the purpose of designing PowerPC compatible products and testing such de signs b make derivative works of the design documentation forthe purpose of designing PowerPC compatible products and testing such designs and c make copies of the design documentation and any such derivative works but only such numbers as are reasonably neces sary for designing PowerPC compatible products and testing such designs With regard to any copy made in accordance with the forgoing license you must reproduce any copyright notice appearing thereon With regardtothe design documentation provided hereunder you may not a use copy modify or mergethe design documentation as provided in this license or b sell sublicense rent lease assign or otherwise transfer it In the event you no longer wish to use the design documentation or any derivative versions thereof you must return them to IBM DISCLAIMER OF WARRANTY IBM does not represent or warrant that the Reference Design which may contain prototype items a meets any pa
191. rder is M2 U4 U5 U7 J25 J26 and J27 3 Route these nets so as to minimize noise reception and timing delays Make these nets as short as possible Table 61 PCI Bus Nets AD lt 31 0 gt PCI PCI PCI_IRDY PCI_STOP PCI_DEVSEL PCI PERR PCI SERR PCI_C BE lt 3 0 gt PCIL_LOCK PCI PAR 12 6 Group 2A Noise Sensitive Wires These nets are noise sensitive Route them so as to minimize noise reception Make these nets as short as possible Table 62 Noise Sensitive Nets BUFF PS POWER GOOD MAN RESET R BUFF MAN RESET POWER GOOD RESET SYS RESET PCI RESET HRESET 60X SRESET 60X ESP TRST HDWR RESET ESP TRST 60X RESETDRV ISA RESET MPRHO1TSU 02 167 Physical Design PowerPc 12 7 8mm Tape Contents and Extract Instructions Part Number MPRHO7INU 01 12 7 1 Download Instructions The enclosed 8mm tape was created using the tar command First find the address of the 8mm tape drive by executing the following command isdev tape Then change the block size to 1024 by executing the following command chdev rmt0 a block size 1024 To extract the data create a directory and ensure that at least 80M of free space is avail able Use the cd command to get to the created directory and type the following tar xvf dev rmtO 12 7 2 Cadence Version Concept version 1 7 51 Allegro version 8 0 later packagerXL 12 7 3 Tape Contents The tape contains the follo
192. re saved when the Save and Exit option on the main menu is selected Exiting the system configuration utility in any other manner will cause device configuration changes to be lost Select Console Device The console selection box allows the selection of an option for the system console e Serial Port 1 or 2 Console input and output will be transmitted and received through a serial port on an adapter card Console input and output will be transmitted and received at the baud rate se lected with Serial Port Speed S3 Video Keyboard Console output will be displayed on a video monitor con nected to an S3 PCI video adapter console input will be re ceived from a keyboard connected to the keyboard connec tor on the reference board MPRHO1TSU 02 129 Set Serial Port 1 or 2 Speed The serial port speed selection box sets the speed of each serial port Baud rates for the two serial ports are independent If a serial port is used as the system console set this value to match the baud rate of the terminal View SCSI Devices The SCSI devices screen shows the devices found on the SCSI bus during power on initial ization The string shown is the SCSI device s response to the SCSI inquiry command Ac cording to the SCSI specification this data comprises the manufacturer s ID device model number and device revision level A sample screen is shown in Figure 35 PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Cor
193. ric identification value of the operating system located in the partition The 32 byes of partition name field must have the ASCII notation of the partition name The and OS ID can be used to provide to a user the identifica tion of the boot partition during the manual boot process Once the boot partition is identified by the PowerPC Reference Platform boot partition table entry the firmware Reads into memory the second 512 byte block of the boot partition Determines the load image length for reading in the boot image up to but not includ ing the reserved2 space Allocates a buffer in system RAM for the load image transfer no fixed location Transfers the load image into system RAM from the boot device the reserved2 space is not loaded The load image must be fully relocatable as it may be placed anywhere in memory by the system firmware Once loaded the load image may relocate itself anywhere within system RAM 124 MPRH01TSU 02 PowerPc Firmware 10 4 System Configuration This section describes the utilities in the system firmware which allow the system to be cus tomized These utilities allow viewing of the system configuration as well as the ability to change I O device configurations console selection boot devices and the date and time These functions are described in the following sections 10 4 1 System Console The system console can be either a screen oriented video display or a line oriented seri
194. rs 106 94 PCI Configuration Scan sc 107 9 4 1 Multi function Adaptors 107 94 2 su usu usaq 107 9 5 Reference Design Combined Register 0 108 9 5 1 Direct Access Registers 108 9 5 2 Indexed BCR Summary 114 96 ISA Bus Register Suggestions 116 Section 10 System Firmware 119 TOT nttoduetions wins 119 10 2 Power On System Test 119 10 2 1 Hardware Requirements 119 10 3 Boot Record Format 119 10 31 BootiRecord ncaa ig le ES 120 10 3 1 1 PC Partition lable Entry a 120 10 3 1 2 Extended DOS MUERE 121 10 3 1 3 PowerPC Reference Platform Partition Table Entry 122 10 3 2 Loading the Load Image 123 10 4 System Configuration EX RS 125 10 4 1 System Console 125 10 4 2 System Initialization 125 1043 Main Menu Sd aa mes DD ee Pe so 126 III MPRH08TSU 02 PowerPc 10 4 3 1 System
195. rticular requirements b operates uninterrupted c is error free is non infringing of any patent copyright or other intellectual property right of any third party IBM makes no representation or warranty regarding the performance or compatibility that may be obtained from the use of the Reference Design or that the Reference Design is adequate for any use The Reference Design may contain errors and may not provide the level of completeness functionality support performance reliability or ease of use available with other products whether or not similar to the Reference Design IBM does not represent or warrant that errors or other defects will be identified or corrected THE REFERENCE DESIGN IS PROVIDED 5 IS WITH ALL FAULTS WITHOUT WARRANTY OF ANY KIND PRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE REFERENCE DESIGN IS WITH YOU Some jurisdictions do not allow exclusion of implied warranties so the above exclusions may not apply to you 8 50 02 3 PowerPc LIMITATION OF REMEDIES IBM s entire cumulative liability and your exclusive remedy for damages for all causes claims or actions wherever and whenever asserted relating in any way to the subject matter of this agreement including the contents of the Reference Design and any components thereof is limited to twenty
196. run at one half of the CPU bus speed PCI bus activity initiated by the CPU is discussed in section 2 This section describes PCI bus transactions initiated by a non 660 bridge PCI bus master 31 PCI Transaction Decoding When a PCI bus master initiates a transaction on the PCI bus the transaction either misses and is master aborted or it is claimed by a PCI target The target can be either the 660 bridge or another PCI target MPRHO1TSU 02 35 PowerPc PCI Bus 3 1 1 PCI Transaction Decoding By Bus Command Table 6 shows the responses of the 660 bridge and other agents to various PCI bus trans actions initiated by a PCI bus master other than the 660 bridge As shown in Table 6 the 660 bridge ignores No response all PCI bus transactions except PCI memory read and write transactions which it decodes as possible system memory accesses Table 6 Reference Design Responses to PCI C 3 0 Bus Commands Initiate this Transaction the Transaction Claim the Transaction allowed to initiate intended to be the target 0100 None 0101 None 0110 0111 1000 System memory read System memory write None 1001 None Dual Address Cycle Memory Write and Invalidate 1010 None 1011 None Yes if no address conflict Yes if no address conflict 1100 System memory read 1101 1110 System memory read Memory Read Line 1111 2 System memory write 3 1 2 PCI Memory Transaction Decodin
197. s Extraneous CPU to PCI Cycle 8 8 95 Normally if a CPU to PCI memory write is pending and a PCI busmaster initiates a sys tem memory access then the CPU cycle is retried Under certain conditions however the CPU to PCI transaction is also posted inside the 660 causing the CPU to PCI trans action to be executed once by the 660 and once by the CPU Additionally the 660 executes the posted transaction with random levels on the C BE lines Separate the BG1 and BG2 if MP signal between the 664 and the CPU by a PAL Deassert BG1 and BG2 from the beginning of each CPU bus address tenure until 4 CPU CLKSs before the associated data tenure ends This be done by waiting until the 3rd TA is received for memory cycles or until one clock after AACK L2 cache hits This workaround has a less than 296 impact on performance and may affect the maxi mum operating frequency of the CPU bus 180 MPRH01TSU 02 PowerPpc Errata 14 Workaround Workaround Details Workaround MPRH01TSU 02 Errata TT 0 4 Float to ECIWX ECOWX 8 8 95 If the CPU TT 0 4 lines float to the value 1x10xb while a CPU data tenure is pending then the 664 will malfunction usually by exhibiting incorrect behavior on the TA line During a CPU bus transfer TT 0 4 are driven to a correct value and then allowed to float for up to 16 CPU clocks in certain situations The 664 incorrectly samples their value dur ing
198. s are activated when a PCI master writes memory Note that CAS 0 refers to byte addresses 0 mod 8 CAS 1 refers to byte addresses 1 mod 8 etc Forread cycles eight bytes of memory data are read on each access butthe master receives only the desired 4 bytes The bytes are read or written to memory independently of BE or LE mode the endian mode byte swappers are situated between the CPU and the rest of the system not between the PCI and the rest of the system In ECC mode PCI to memory transactions that result in less than 8 byte writes cause the memory controller in the 660 bridge to execute a read modify write operation during which 8 bytes of memory data are read the appropriate bytes are modified the ECC byte is modi fied and then the resulting 8 bytes are written to memory MPRHO1TSU 02 39 PCI Bus PowerPc Table 10 Active Lines PCI to Memory Writes BE or LE Mode Byte Enables BE Column Address Selects CAS 2 3 4 5 2 lt x x gt x a a a al A ol ol oOo oco ol O ol lt gt a clo olol of ol lt gt ol ol ol Of Of OF
199. s in LE mode and data flowing on the PCI is in LE order so that it is recorded on the media in LE order Byte 0 is the least significant byte The PCI bus is addressed in the same manner as memory is when the 603 604 CPU runs a cycle The unmunging in LE mode changes the effective low order address bits the byte enables and A D 2 On all but cycles the two low order A D lines are set to zero On PCI I O cycles A D 1 0 are also transformed by the unmunge operation No translations are made when PCI accesses memory so that the byte with address 0 on the PCI flows to byte 0 in memory 1 to 1 2 to 2 and so on For example if BE0 and 1 are active and A D 2 is a 0 then memory byte lanes 0 and 1 are addressed cas 0 and cas 1 active on writes Note that the LE devices which interpret data structures in the memory require that their control data be arranged in LE order even in BE mode For example SCSI scripts in memory must always be arranged in LE order because that is what the device expects Devices such as video may require the bytes to be swapped unless these devices have byte swap capability 92 MPRHO01TSU 02 PowerPc Exceptions Section 8 Exceptions The reference design handles two classes of exceptions interrupts and errors Interrupts are handled primarily by the interrupt controller in the ISA bridge the 660 bridge the CPU and the firmware Errors are handled primarily by the 660 bridge the CPU and the
200. scatter gather is employed The reference design is initially configured to use this scheme The EOP signal from the ISA bridge is used as the terminal count ISA_TC signal on the ISA bus MPRHO1TSU 02 95 Exceptions P CF 2 c 8 2 Error Handling There are two methods which the reference design 660 bridge uses to report errors to the CPU the TEA method and the method Errors that are detected while the CPU is running a cycle that can be terminated immediate ly are reported using TEA Errors reported in this way are a direct result of the CPU transfer that is currently in progress For example when the 660 detects a transfer size error it ter minates the CPU transfer with TEA instead of with Errors that are detected while a CPU transfer is not in progress and errors that occur be cause of a CPU transfer but which are detected too late to be reported using TEA and errors that are not a direct result of the current CPU transfer are reported using MCP For example parity errors occuring while a PCI bus master is accessing memory are reported using MCP For more information on error handing see the 660 Bridge User s Manual 8 2 1 Data Error Checking The reference design is initially configured to use parity and this documentation reflects that configuration However the 660 bridge can be programmed to execute an error check ing and correction ECC algorithm on the memory data generating ECC check
201. se and urentAdr RW so 0008 80000003 80000003 and Current Cm RW so 0004 80000004 80000004 DMA1 CH2BaseandCurentAddr RW SIO 0005 80000005 80000005 DMA1 CH2 Base and Current Cm Rw SIO 0006 80000006 80000006 DMA CH3BaseandCurentAddr RW so 0007 8000 0007 80000007 DMA1 CH3 and Current Cnt RW so 0008 80000008 80000008 DMA1 Status R CommandW RW 50 0009 8000 0009 80000009 DMATSotReqes w so 000A 8000 000A 8000 000A Write SingleMaskBt w 50 0008 80000008 80000008 DMATWrleMode so 0000 8000 0000 80000006 DMAiClearByePoier w so 0000 8000 0000 80000000 DMATMesterCear T w so 000E 8000 000E 8000000 w 50 8000 000F 1 R W Mask Register Bits 0020 8000 0020 8000 1000 INT1 Control 040 8000 0040 8000 2000 042 060 80000060 8000 3000 Reset X Bus mse IRQ12 R 0062 8000 0062 8000 3002 0064 8000 0064 80003004 Keyboard Mouse fR 0070 80000070 80003010 TOD AddrandNMIEmabe Ww 0074 8000 0074 80003014 NV RAM AddrSobeO 0075 80000075 80003015 Addr Strobet w 0077 8000 0077 0079 8000 0079 O 2
202. se the Reference Design forattainmentornon attainmentof any schedule performance cost reliability maintainability quality manufacturability or the like requirements or goals self imposed by you or accepted by you from others concerning any product s or portion s of product s or for any delays costs penalties charges damages expenses claims or the like resulting from such non attainment where use of all or any part of the Reference Design is involved GENERAL In the event there is a conflict between the terms of this Agreement and the terms printed or stamped on any item or any ambiguities with respect thereto including documentation contained in the Reference Design the terms of this Agreement control to the extent IBM is af forded greater protection thereby IBM may terminate this Agreement if you fail to comply with the terms and conditions of this Agreement Upon termination of this Agreement you must destroy all copies of the software and documentation You are responsible for payment of any taxes including personal property taxes resulting from this Agreement Neither party may bring an action hereunder regardless of form more than one 1 year after the cause of the action arose If you acquired the Reference Design in the United States this Agreement is governed by the laws of the State of New York In the event of litigations trial shall be in New York without a jury If you acquired the Refer ence Design in Canada th
203. selected boot devices or if no boot device is selected the user will be prompted to enter the configuration menu to select a valid boot device Any changes made in boot device selection is saved when the Save and Exit option on the main menu is selected Exiting the system configuration utility in any other manner will cause boot device changes to be lost MPRHO1TSU 02 131 Set Date and Time The set date and time screen allows the date and time stored in the battery backed real time clock to be updated The screen is shown in Figure 37 To change the time the left and right arrow keys are used to select the digit to modify and the digit is then typed over with the number keys The date or time will be updated when Enter or either the up or down arrow is pressed Changing the date or time is immediate and is not affected by either the Save and Exit or Exit Without Saving options on the main menu PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp A11 Rights Reserved Set Date and Time Set Date 03 01 94 Set Time 11 30 00 Go to Previous Menu Press to select item Enter data at cursor Figure 37 Set Date and Time Screen 132 MPRH01TSU 02 PowerPc Firmware 10 4 3 2 Run a Program The Run a Program option on the main menu loads and executes a program from a FAT DOS disk or from a CD ROM ISO 9660 format The program is loaded at location 0x00400000 4 MB and control is pa
204. ses to system memory using any address between 0 and 16M that is mapped to a PCI device such as video 4 3 ISA Bus Concurrency ISA bus cycles which are not enabled for forwarding including the hole remain on the ISA bus That is DMA or ISA bus master cycles on the ISA bus can run concurrently with PCI or CPU cycles 4 4 ISA Bus Masters and IGN PCI AD31 The ISA bridge supports ISA bus masters System memory accesses from an ISA bus mas ter are designed to be mapped to the 0 to 16M range and the ISA bridge forwards them to the PCI bus at the same range which is not compliant to the PowerPC Reference Plat form specification Other PCI to system memory accesses however are correctly mapped to the 2G to 4G range for system memory address range from 0 to 2G In some architec tures this problem is handled by using the ISA_MASTER signal which is active during the ISA bus master operation However the ISA bridge allows ISA masters to run posted writes to system memory with out latching in the accompanying 1 _ signal In this situation the ISA_MAS TER signal is no longer synchronized to the ISA bus master operation To overcome this challenge the reference design detects PCI memory transactions that are initiated by the SIO The reference design ANDs together GNTO GNT1 and 2 44 MPRHO01TSU 02 PowerPc ISA Bus to generate IGN PCI AD31 which is active high during the address phase of any PCI transacti
205. signal and the DPE signal are ignored during ROM reads The Flash or ROM should include CRC with software checking to insure integrity Write to Flash with TSIZ other than 4 This will cause indeterminate data to be written into the Flash at an indeterminate ad dress Caching ROM space An L1 or CB L2 cast out will cause indeterminate results Running any cycle to the PCI configuration space with an undefined address Some of these could potentially cause damage See the warning under the PCI configu ration cycle section Accessing any ISA device with the wrong data size for that device Indeterminate results will occur Exceptions 100 PowerPc MPRHO01TSU 02 PowerPc Setup Section 9 System Setup and lnitialization 9 1 CPU Initialization The 603 604 CPU exits the reset state with the L1 cache disabled and bus error checking disabled All memory pages 2G to 4G must be marked as non cacheable The Segment Register T bit bit 0 defaults to 0 which is the normal storage access mode It must be left in this state for the hardware to function Direct store PIO segments are not supported Set the bit that controls ARTRY negation HIDO 7 to 0 to enable the precharge of ARTRY It may be necessary set HIDO 7 to 1 to disable the precharge of ARTRY for ref erence design configurations having a CPU bus agent such as an added L2 that drives the ARTRY line Software must set this bit before allowing any CPU bus traffi
206. ssed with a branch to the first address All boot devices specified in the Boot Devices Menu will be searched in order for FAT and CD ROM file systems and the first matching file on a boot device will be loaded The Run a Program screen is shown in Figure 38 To run a program enter the file name in the Specify Program Filename field and select the Run the Program option PowerPC 603 604 Reference Board System Firmware C Copyright 1994 IBM Corp 11 Rights Reserved Run a Program Specify Program Filename Run the Program Go to Previous Menu Press to select item Enter data at cursor Figure 38 Run a Program Screen MPRHO1TSU 02 133 10 4 3 3 Flash Memory The PowerPC 603 604 reference board stores its system firmware in a reprogrammable flash memory on the system board The reprogram flash memory option on the main menu allows the reprogramming of the flash device with DOS formatted diskette This allows future revisions of the system firmware to be provided on diskette without the need for re moval of the device from the board If done improperly reprogramming the flash memory can cause the system to become un usable until external means are available to reprogram the device Use this option with care All boot devices specified in the Boot Devices Menu will be searched in order for FAT and CD ROM file systems and the first matching file on a boot device will be loaded T
207. sserts No other response No PCI transaction 1001 Write with flush atomic SBW Memory write operation PCI write transaction Stwcx 1010 SBW Asserts AACK and TA if the transaction is not claimed by another 60X bus device No PCI transaction No other response 1011 Reseved Asserts AACK No other response No PCI transaction TLB invalidate Address only Asserts AACK No other response No PCI transaction Read atomic Iwarx SBR or burst Memory read operation PCI read transaction 1110 External control in Address only 660 asserts all ones on the CPU data bus Asserts AACK and TA if the transaction is not claimed another 60X bus device No PCItransaction No other response 1111 Read with intent to Burst Memory read operation PCI read transaction modify atomic stwcx Note 1 5 used in this table SBR means Single Beat Read and SBW means Single Beat Write Transfer types in Table 3 that have the same response are handled identically by the bridge For example if the address is the same the bridge generates the same memory read transaction for transfer types 0101 0111 1101 and 1111 The 660 Bridge does not generate PCI or system memory transactions in response to ad dress onlytransfers The bridge does drive all ones onto the CPU bus and signals TA dur ing an eciwx if no other CPU bus agent claims the transfer References in the remainder of this document t
208. t 55 0 0 95 8 1 4 Scatter Gather Interrupts 95 Error ES eS PEPS SS SS 96 8 2 1 Data Error Checking 96 8 211 CPU to Memory Writes 96 824 2 GPU to Memory Reads T 96 8 2 1 3 PCI to Memory Parity Errors 97 8 2 1 4 CPU to PCI Transaction Data Errors 97 8 2 2 legal CPU cycles iiu esu mr eben Eb EE eh 97 8 2 8 SERR Channel Check NMI Logic 97 8 2 4 of Bounds PCI Memory Accesses 97 8 2 5 No Response on CPU to PCI Cycles Master Abort 98 8 2 6 CPU to PCI Cycles That Are Target Aborted 98 8 2 7 Error Status Reglsters EE ae xS AS 98 8 2 8 Reporting Error Addresses 98 8 29 Errant be itis 98 8 2 10 Special Events Not Reported as Errors 99 Section 9 System Setup and Initialization 101 a Sees s 101 92 660 Bridge Initialization 102 93 ISA Bridge SIO Initialization 103 9 3 1 Summary of SIO Configuration Registe
209. t of the CPU to deter mine parity errors and reports them back to the CPU via MCP The particular memory read data beat will be terminated normally with 96 MPRH01TSU 02 PowerPc Exceptions 8 2 1 3 PCI to Memory Parity Errors During PCI to memory writes the 660 bridge generates the data parity that is written into DRAM memory The bridge also checks the parity of the data and asserts PCI PERR if it detects a data parity error During PCI to memory reads the 660 bridge checks the parity of the memory data and then generates the data parity that is driven onto the PCI bus If there is a parity error in the data parity returned to the 660 bridge from the DRAM the bridge drives PCI PAR incorrectly to propagate the parity error and also reports the error to the CPU MCP The data beat with the bad parity is not target aborted because doing so would slow all data beats for one PCI clock TRDY is generated before the data is known good However if the agent is bursting and there is another transfer in the burst the next cycle is stopped with target abort protocol During PCI to memory reads the 660 bridge also samples the PCI PERR signal which other agents can be programmed to activate when they detect a PCI parity error 8 2 1 4 CPU to PCI Transaction Data Parity Errors During CPU to PCI writes the 660 bridge sources the PCI parity information and monitors PCI PERRZ which other agents can be programmed to activate wh
210. talled on that board in order to work around certain errata 22 MPRH01TSU 02 PowerPc Introduction Table 1 Quickstart Peripheral List Diamond Stealth S3 864 NCR 8100 with 609 039 1635 controller Super adaptor IDE floppy serial Acculogic sIDE 4 HP 110 00139 00 00 ports parallel ports etc Quantum LPS270 5405 Maxtor MXT 540SL IBM WDS 3200 79F4042 Internal cables floppy SCSI and Standard cables ROM Speer 606000 MPRHO1TSU 02 23 Introduction 24 PowerPc MPRH01TSU 02 P2werPc CPU Section 2 CPU and CPU Bus This section discusses topics that are directly related to the CPU including how the 660 bridge decodes CPU initiated transfers as a function of the transfer type and address range For more information refer to the 660 Bridge User s Manual The reference design supports CPU bus speeds up to 66MHz and PCI bus speeds up to 33MHz The reference design is initially configured with a CPU PCI bus speed ratio of 2 1 The CPU PCI clock ratio can be changed to 1 1 or 3 1 by reconfiguring the clock generator and the 660 bridge as long as other system considerations are handled correctly 2 1 CPU Bus Masters The reference design uses a single CPU of either the PowerPC 603e or PowerPC 604 fam ily and an external L2 cache is not allowed Thus there are only two bus masters on the CPU bus the CPU and the 660 bridge CPU bus arbitration
211. te Register 1 R W SIO sd p Cd _______ gt lt __ I i _______ sd _______ sd _______ wass O 8080 9 8080 084A 8080 0848 8080 0 8080 0840 o 8080 0855 MEMCS Attribute Register 2 SIO 8080 0856 MEMCS Attribute Register 3 WI 8080 0860 PIRG RouteComrg1 RW oF SIO 56 Scatter Gather Relocation Base PIRQ Route Control 0 8080 0862 8080 0880 O BIOS Timer Base Address KM KM BIOS Timer Base Address PCI Type 0 Configuration Adar RW PCI Type 0 Configuration Adar RW Ee a PCI Type 0 Configuration P EFFO BEFF EFFO System Error Addr R 5 0 Configuration wa 112 MPRH01TSU 02 PowerPc Setup Table 33 Combined Register Listing Continued Contiguous Non Contig Description R W Set Loc Mode Addr Mode Addr To 6 4 BFFFFFFO BFFF FFFO InterruptVector R
212. tered transac tion and that this capability is not normally used MPRHO1TSU 02 37 PCI Bus PowerPc 3 1 3 PCI I O Transaction Decoding The 660 Bridge initiates PCI I O transactions on behalf of the CPU Other PCI bus masters are also allowed to initiate PCI I O transactions Table 9 shows the reference design map ping of PCI transactions The 660 bridge ignores PCI I O transactions PCI ISA I O is mapped to PCI I O space from 0 to 64K The ISA bridge subtractively de codes these transactions and also PCI memory transactions from 0 to 16M Other devices may actively decode and claim these transactions without contention PCI I O is assigned from 16M to 1G 8M Table 9 Mapping of PCI Master I O Transactions PCI Bus Address Target Resource Other System Activity 1G 8M to 4G Reserved 1 The 660 Bridge ignores transactions initiated by PCI 16M to 1G 8M PCI VO devices 8 to 16 1 64 to 8 2 0 to 64 PCI ISA MO Notes 1 The CPU thru the 660 bridge can not access this address range so do not PCI devices herein unless the CPU will not access them 2 In contiguous mode the CPU thru the 660 bridge can create PCI I O addresses in the 64K to 8M range In non contiguous mode the CPU can only access PCI addresses from 0 to 64K 3 1 4 ISA Master Considerations Since the reference design implements IGN PCI AD31 and uses an Intel SIO memory transactions produ
213. the above conditions As long as there are no current sources operating on the TT lines during the float these lines will maintain their value due to bus capacitance Do not put put pullup or pulldown resistors TTL type inputs or any other current sources on TT O 2 3 For 603 or 603e designs only workaround 9 overrides this workaround pull down TT 2 664 TT 2 CPU as shown in errata 9 This workaround has no effect on performance or maximum frequency Spurious Set of the Flash Write Lockout Bit 8 1 95 While the 660 is configured for direct connect ROM PCI based and a ROM read cycle is pipelined over a single beat CPU to memory write to an odd memory location then the flash write lockout bit located at register address FFFF FFF1h may be inadvertantly set without a write to the aforementioned address Once written this bit can only be reset via power on reset If the bit sets the PCl based flash ROM cannot be updated A hardware workaround is TBD A possible software workaround is to prevent the above scenario possibly by adding sync cycles before the ROM reads This workaround has no effect on performance or maximum frequency PCI Lock in 603 1 1 Mode 8 1 95 While the 660 bridge is configured for 603 1 1 mode which ensures a wait state between TS and AACK the assertion of PCI_LOCK may cause a system hang This bug has only been predicted by system simulation and has not been observed in the lab Do n
214. ut exceed ing the loading parameters MPRHO1TSU 02 41 PCI Bus PowerPc 42 MPRHO01TSU 02 PowerPc ISA Bus Section 4 ISA Bus The reference design includes an ISA bus that is interfaced to the PCI bus by the ISA bus bridge Five ISA expansion slots are provided by the reference design The reference de sign uses a buffered subset of the ISA bus called the X bus to host onboard native such as the real time clock and the keyboard and mouse controller 4 1 The ISA Bridge The ISA bridge function is provided by an Intel 82378ZB chip SIO It provides a PCI to ISA bus bridge with the following major functions Bridge between PCI and ISA 8 16 bit ISA devices 24 bit addressing on ISA Partially decodes native I O addresses Unclaimed PCI memory address below 16MB forwarded to the ISA bus Unclaimed PCI I O address below 64K forwarded to the ISA bus Powers up to an open condition i e cycles may be passed to the ISA bus Generates ISA clock with a programmable divide ratio of three or four Allows ISA mastering and has programmable decodes that map ISA memory cycles to the PCI bus 32 bit posted memory write data buffer no I O buffering Seven channel ISA DMA controller e Function of two 83C37s with 32 bit extensions Supports 8 bit or 16 bit devices on the ISA bus e Supports 32 bit addressing for ISA to PCI memory transfers 8 byte bidirectional buffer for DMA data Timer block function of 82654 Interrupt C
215. werPc 64k x 18 SRAM Address CPU ADDR 13 28 CPU DATA 0 63 Data CPU DPAR O0 7 Data CS CS CS Figure 8 Synchronous SRAM 512K L2 64k x 18 64k x 18 SRAM SRAM CPU_ADDR 13 28 Address H Address CPU DATA 0 63 Data FL f CPU DPAR 0 7 Data FTT T CCC Data CS CS Figure 9 Synchronous SRAM 1 L2 70 MPRH01TSU 02 PowerPc CPU ADDR 14 28 CPU DATA 0 63 CPU DPAR 0 7 Figure 10 Asynchronous SRAM 256K L2 CPU ADDR 13 28 CPU DATA 0 63 CPU DPAR O0 7 Figure 11 Asynchronous SRAM 512K L2 MPRHO1TSU 02 32k x 9 SRAM Address Data Data CS 64k x 18 SRAM Address Data Data CS CS CS 71 PowerPc 128k x 9 SRAM Address Data CPU ADDR 12 28 CPU DATA 0 63 CPU DPAR 0 7 Data CS Figure 12 Asynchronous SRAM 1M L2 6 22 TagRAM The tagRAM pair of IDT71216S10 devices is installed on the reference board The ta gRAM configuration for a 512K L2 initially supplied on the reference design is shown in Figure 13 The tagRAM configuration for
216. werPc CPU ible mechanism to lock the I O address space from change by user state code This parti tioning spreads the ISA I O address locations over 8M of CPU address space In non contiguous mode the first 32 bytes of a 4K page are mapped to a 32 byte space in the PCI address space The remainder of the addresses in the 4K page are mirrors into the the same 32 byte PCI space Each of the 32 contiguous port addresses in each page has the same protection attributes in the CPU 31 MSB 30 29 28 27 26 25 Forced to zero 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 LSB 31 00 LSB H H w H m H Hl 6 0 X C P U A r e s s Discarded 0 0 0 gt three least significant address bits unmunged during the transformation if little endian mode is selected Figure 2 Non Contiguous PCI Address Transformation For example in Figure 3 60X CPU addresses 8000 0000h to 8000 001Fh are converted to PCI port 0000h through 001 Fh PCI I O port 00201 starts in the next page at 60X CPU address 8000 1000h ISA I O 60X Address 8000 0000 8000 0001 8000 0002 60X Addresses 8000 0020 to 8000 OFFF Are Wrapped and Should Not Be Used Figure 3 Non Contiguous PCI I O Address Translation MPRHO1TSU 02 29 CPU P2werPc 2 3 2 Address Mapping
217. werPc Setup Table 30 Summary of SIO Register Setup Configuration Address 8080 08xx Continued Register Set Reset DESCRIPTION To Value Utility Bus Chip Select B 3 2 LE 11 Disable generation of default address for Config PCl 4 5 BE Serial Port B rig Interrupt Controller 1 3 LE ICW1 PCI 4 BE Utility Bus Chip Select B 4Fh 1 0 LE Disable generation of default address for Config PCl 6 7 BE Serial Port A 20h Set Interrupt Controller 1 to edge triggered mode Interrupt Controller 1 20h 1 LE X Set Interrupt Controller 1 to cascade ICW1 PCI 6 BE mode Interrupt Controller 2 AOh 3 LE Set Interrupt Controller 2 to edge triggered ICW1 I O PCI 4 BE mode Interrupt Controller 2 AOh 5 x Set Interrupt Controller 2 to cascade ICW1 PCI 6 mode NMI Status and Control 61h 3 LE IOCHK NMI enabled 4 NMI Status and Control 611 2 LE PCI SERR enabled PCl 5 BE NMI Enable and TOD 70h 7 LE 1 NMI interrupt enabled dress I O PCI 0 Command I O PCl 081 7 LE DACK Assert Level set to low DOh 0 DMA Command PCl 081 6 LE DREQ Sense Level set to high Doh 1 BE MPRHO1TSU 02 105 Setup PowerPc 9 3 1 Summary of SIO Configuration Registers Table 31 Summary of SIO Configuration Registers Address Description 5 5 of
218. where the native I O and the ISA slots reside and it provides system ser vices such as ISA bus DMA PCI bus arbitration and interrupt control 1 3 8 Time of Day Clock The reference design uses a Dallas Semiconductor 0513855 to provide the real time clock TOD or RTC function This device is PC compatible and resides on the X bus It fea tures an additional 4K of NVRAM and a replaceable battery 1 3 9 PS 2 Compatible Keyboard Mouse Controller The reference design uses an Intel 8042AH as a keyboard and mouse controller The code used is the same version as used in IBM Personal System 2 machines This mi crocode may differ from other 8042 type keyboard controllers 1 3 10 System Clocks The primary clock generation is accomplished with a Motorola MPC970 PLL clock gener ator which uses a seed oscillator to generate the CPU and PCI clocks needed by the sys tem MPRHO1TSU 02 21 Introduction PowerPc 1 311 System EPLD The system EPLD is a programmable logic device that uses the X bus signals and the partial decode signals from the SIO to decode chip selects for various components 1 3 12 Power Management Power management hardware is included on the board however power managenent ca pability will be implemented at a later date and will be described in a separate document 1 4 Quickstart Peripheral List The reference design is intended for typical PC peripherals Products from a large number of manufacturers shou
219. while SNC SHIFT ENFF is 1 CNTR d CNTR q 1 Else CNTR d CNTR q End If GEN_START BIT CNTR 3 q 5 CNTR 2 q amp CNTR 1 q 6 CNTR O q 1 STOP_SHIFT CNTR 3 q 6 CNTR 2 q 6 CNTR 1 q 0 5 14 5 GEN STOP BITFF d STOP SHIFT Generate Stop Bit when counter is 15 GEN STOP BITFF prn VCC GEN STOP BITFF clrn RESET GEN STOP BITFF clk ISA START SHIFTFF s GEN START BIT START SHIFTFF r STOP SHIFT START SHIFTFF clrn RESET START SHIFTFF clk ISA CLK he he he S FRZ_DATA OUT is 1 when the counter 0 It is also 1 whenever 5 START SHIFTFF is 1 and CLKFF 0 is 1 and then when the counter is Fifteen to leave it in the high state e he e he he he FRZ DATA OUT CNTR 3 q 8 CNTR 2 q amp CNTR 1 q 6 CNTR 0 q GEN STOP BITFF q START SHIFTFF q amp CLKFF 0 q Ke he he he he he S Read Storage Light Status Register 1 0 address 0808 MSB Bits 7 1 Reserved LSB Bit O Hard
220. wing directories PXL e Pst files packager files e View files Allegro feedback files bom files bill of material files SCR Script files Flatlab Logic models used for this design Harley 603 603 Reference Board Schematic data Postscript plots Each page plot total ps tscr Cross reference sheets 168 MPRH01TSU 02 PowerPc Bia Section 13 Errata for Reference Design Release 2 1 This is the errata section of release 2 1 of the 603 604 Reference Design This is not the final release of this reference design This release contains errata that will be cured in sub sequent releases according to the reference design roadmap Some of these errata are due to board level errata and some are due to individual device errata Note that all of the workarounds for the errata described herein were implemented during the physical design of the board Circuitry devices and connections shown in this section are shown in the schematics in section 15 and do not need to be added to the board Section 13 1 discusses the roadmap for the reference design Section 13 2 describes board level errata and workarounds Section 13 3 describes the logic workarounds associated with 660 bridge errata and gives the logic design files for the PALs that were chosen to implement the workarounds The connectivity of these PALs is shown in the schematics in section 15 Descriptions of the individual errata can be found in section
221. xecute a type 0 PCI configuration transaction as described in the Pow erPC Reference Platform Specification and implemented by the IBM27 82650 PowerPC to PCI Bridge This is referred to as the 650 compatible configuration method This method of accessing PCI configuration space does not allow access to the PCI configuration regis ters in the bridge chip and it should not be used unless required to maintain 650 compatibility When using the 650 bridge compatible configuration method use only the specified ad dress Using certain other addresses could cause bus contention because multiple PCI slots could be selected For example using any CPU address in the range 8080 0000 to 80FF FFFF with both AD11 1 and AD12 1 causes selection of both the SIO and any device in slot 1 possibly resulting in damage 32 MPRH01TSU 02 P2werPc CPU Table 5 660 Bridge Address Mapping of CPU Bus Transactions Intel SIO 8237828 A D 11 8080 08XXh 080 08XX PCI slot 1 A D 12 8080 10XXh 080 10XX PCI slot 2 A D 13 8080 20XXh 080 20XX PCI slot 3 A D 14 8080 40XXh 080 40XX Reserved config scan A D 18 8084 00XXh 084 00XX Note This address is independent of contiguous MO mode 2 5 6 CPU to PCI Interrupt Acknowledge Transaction Reading the interrupt acknowledge address BFFF FFFOh causes the bridge to arbitrate for the PCI bus and then to execute a standard PCI interrupt acknowledge transaction The system interrupt controller in the ISA bridge claims the
222. ystem Initialization Screen 125 Figure 31 Configuration Utility Main Menu 126 Figure 32 System Configuration Menu 127 Figure 33 System Information Screen 128 Figure 34 Device Configuration Screen 129 Figure 35 SCSI Devices Screen 130 Figure 36 Boot Devices Screen 131 Figure 37 Set Date and Time Screen 132 Figure 38 Run a Program Screen 133 Figure 39 Reprogram the Flash Memory Screen 134 Figure 40 604 Heat Sink Assembly 139 Figure 41 Connector Location Diagram 143 MPRH08TSU 02 11 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Keyboard Connector The Mouse Connector 1x4 Speaker Connector 1x5 Power Good LED Connector 1x2 HDD LED Connector 1x2 Reset Switch Connector 1x2 Fan Connector 1x6 3 3V Power Connector J5 1x12 P
223. ystem via the X bus as two 8 bit registers as shown in this and the previous sections Once triggered the FCR data is shifted out as serial data on FRZ DATA OUT This function is intended for use with the MPC970 clock chip as is done in the reference design The MPC970 contains an input shift register the input of which Frz Data is con nected to FRZ DATA OUT ISA CLK is used to clock the data from the EPLD to the MPC970 EPLD will shiftthe freeze clock data out of the FCR in response to either one of two triggers 1 A write to ISA port 862 or 2 A low to high transition on the UNFREEZE input iff bit 0 and bit 1 of the FCR are high After triggering the data transfer wait at least 2 3us for the transfer to complete before accessing the FCR or retriggering the data transfer This is a one way serial data transfer between the two devices Reading the FCR returns the contents of the FCR and does not cause a read of the data in the MPC970 register A 1 in a bit position freezes the corresponding clock output of the MPC970 For details of the data transfer operation and the meaning of the data see the MPC970 data sheet 5 2 Signal Descriptions Table 16 shows the active signals of the EPLD Pins not shown should not be connected Table 16 Signal Descriptions Signal Name i Description X bus Interface Signals ECS 2 0 Encoded Chip Select 2 0 Encoded chip selects for pe ripheral devices supported by the ISA Bridge Use

R PowerPC 603/604 Reference Design Technical

Contents

Download Pdf Manuals

Related Search

Related Contents