Q7-TI8168 user manual
Contents
1. 53 SDIO DAT4 54 SDIO DAT 55 SDIO DAT6 56 57 GND 58 GND 59 1128 WS 60 SMB CLK 61 1128_RSTH 62 SMB_DAT 63 1128_CLK 64 SMB ALERTE 65 I2S SDI 66 2C CLK 67 I2S SDO 68 I2C DAT 69 THRM 70 WDTRIG 71 THRMTRIP 72 WDOUT 73 GND 74 GND 75 76 77 78 79 80 USB 4 5 OC 81 USB P5 82 USB P4 83 USB P5 84 USB P4 85 USB 2 3 OC 86 USB 0 1 OCF 87 USB P3 88 USB P2 89 USB P3 90 USB P2 91 USB CC 92 USB ID 93 USB P1 94 USB PO 95 USB P1 96 USB_PO 97 GND 98 GND 99 LVDS_A0 100 101 LVDS AO 102 103 LVDS A1 104 105 LVDS A1 106 107 LVDS A2 108 109 LVDS A2 110 111 LVDS PPEN 112 LVDS BLEN 113 LVDS A3 114 115 LVDS A3 116 117 GND 118 GND 119 LVDS A CLK 120 121 LVDS A CLK 122 123 LVDS BLT CTRL GP PWM OUTO 124 125 LVDS DID DAT GP I2C DAT 126 127 LVDS DID CLK GP I2C CLK 128 129 130 131 HDMI TMDS CLK 132 133 HDMI TMDS CLK 134 135 GND 136 GND 137 HDMI TMDS LINE1 138 139 HDMI TMDS LINE1 140 141 GND 142 GND 143 HDMI TMDS LINEO 144 145 HDMI TMDS LINEO 146 147 GND 148 GND 149 HDMI TMDS LINE2 150 HDMI CTRL DAT 151 HDMI TMDS LINE2 152 HDMI CTRL CLK 28 Q7 TI8168 User s Manual2. Pin Signal Description T O 1 2 3 CAM D2 Camera Data Bit 2 LSB in 8 Bit mode YCbCr IN 4 CAM D3 Camera Data Bit 3 IN 5 CAM D4 Camera Data Bit 4 IN 6 CAM D5 Camera Data Bit 5 IN 7 CAM D6 Camera Data Bit 6 IN 8 CAM D7 Camera Data Bit 7 IN 9 CAM D8 Camera Data Bit 8 IN 10 CAM D9 Camera Data Bit 9 MSB in 8 Bit YCbCr mode IN 11 GND Signal ground E 12 CAM SHFCLK Camera pixel clock IN 13 CAM MCLK Camera master reference clock OUT 14 CAM VSYNC Camera vertical sync IN 15 CAM HSYNC Camera horizontal sync IN 16 CAM GPIOO Camera GPIO imager reset IN OUT 17 CAM GPIO1 Camera GPIO optional PWM output IN OUT 18 CAM I2C SDA Camera I2C Data IN OUT 19 CAM I2C SCL Camera 12C Clock OUT 20 GND Signal Ground 21 COM_TXD Serial Port Transmit Data LVTTL OUT 22 COM RXD Serial Port Receive Data LVTTL IN 23 COM RTSH Serial Port Ready to send LVTTL low active OUT 24 COM CTSH Serial Port Clear to send LVTTL low active IN 25 GND Signal Ground 26 27 30 Q7 TI8168 User s Manual 28 29 30 31 GND Signal Ground E 32 33 SPI CS0 SPI chip select 0 low active OUT 34 35 SPI_SCK SPI clock OUT 36 SPI_MISO SPI master in slave out IN 37 SPI_MOSI SPI master out slave in OUT 38 GND Signal Ground z 3 3V 5 power supply tel
3. 153 HDMI HPD amp 154 155 PCIE CLK REF 156 PCIE_WAKE 157 PCIE_CLK_REF 158 PCIE_RST 159 GND 160 GND 161 162 163 164 165 GND 166 GND 167 168 169 170 171 172 173 174 175 176 177 178 179 PCIEO_TX 180 PCIEO RX 181 PCIEO TX 182 PCIEO RX 183 GND 184 GND 185 186 187 188 189 190 191 192 193 VCC RTC 194 SPKR GP PWM OUT2 195 FAN TACHOIN GP TIMER IN 196 FAN PWMOUT GP PWM OUT1 197 GND 198 GND 199 SPI_MOSI 200 SPI_CSO 201 SPI_MISO 202 SPI_CS1 203 SPI_SCK 204 MFG_NC4 205 VCC_5V_SB 206 VCC_5V_SB 207 MFG_NCO 208 MFG_NC2 209 MFG_NC1 210 MFG_NC3 211 VCC 212 VCC 213 VCC 214 VCC 215 VCC 216 VCC 217 VCC 218 VCC 219 VCC 220 VCC 221 VCC 222 VCC 223 VCC 224 VCC 225 VCC 226 VCC 227 VCC 228 VCC 229 VCC 230 VCC 29 Q7 TI8168 User s Manual 7 3 Feature Connector X2 X2 is an optional connector with extra features It s located on the top side of the module and it s power domain is CPU The following features are supported m Serial Port LVTTL EH Video capture port A serial port with hardware handshaking RTS CTS is also provided An external transceiver is necessary for RS232 for example 8 bit YCbCr video input up to 165MHz m SPI interface same SPI data lines as on Qseven conn with one separate chip select 4 wire interface with one low active chip select The Qseven module is master Type 40 pin FPC connector 0 5mm pitch Hirose FH28 40S 0 5SH
4. VOUT 24bit Gigabit Ethernet MFG_NC_0 1 2 3 4 RTC Backup Supply Version 1 1 Q7 TI8168 User s Manual 2 6 LEDs There are six onboard LEDs All of them are available as USER LEDs 10 Q7 TI8168 User s Manual 2 7 Signal description In the following tables signals are marked with the power rail associated with the pin and for input and I O pins with the input voltage tolerance The pin power rail and the pin input voltage tolerance may be different An additional label Suspend indicates that the pin is active during suspend states S3 S5 If suspend modes are used then care must be taken to avoid loading signals that are active during suspend to avoid excessive suspend mode current draw 2 7 1 PCI Express Lanes T To Power Rail ra da Description PCIEO_TX O PCle CPU AC coupled on PCI Express 1 1 Differential Transmit Pairs O DaVinci PCIEO_TX module PCIEO_RX PCle CPU Requires AC PCI Express 1 1 Differential Receive Pairs O DaVinci PCIEO_RX coupling on baseboard PCIE_CLK_REF O PCle CPU AC coupled on PCI Express Reference Clock for Lane O Clock generator PCIE CLK REF module PCIE_RST O CMOS CPU 3 3V 5k1 PD Reset Signal for external devices PCle to USB Swidge Il Q7 TI8168 User s Manual 2 7 2 Ethernet
5. Pin Signal E Power hae Type Eve Power Rail Tolerance PU PD Description Source Target GBE MDI 0 3 Input Analog Suspend Gigabit Ethernet Controller Media Dependent Interface Differential Gigabit Ethernet GBE MDI 0 3 Output Pairs 0 1 2 3 The MDI can operate in 1000 100 and 10 Mbit sec Controller modes 1000BASE T MDI configuration MDI X configuration MDI 0 BI DA MDI 0 Bl DB MDI 1 BI DB MDI 1 Bl DA MDI 2 BI DC MDI 2 Bl DC MDI 3 BI DD MDI 3 BI_DD 100BASE TX 10BASE T MDI configuration MDI X configuration MDI 0 Transmit MDI 0 Receive MDI 1 Receive MDI 1 Transmit MDI 2 unused MDI 2 unused MDI 3 unused MDI 3 unused GBE ACTA OD CMOS CPU 3 3V Gigabit Ethernet Controller activity indicator active low Logic GBE_LINK OD CMOS CPU 3 3V Gigabit Ethernet Controller link indicator active low Logic GBE_LINK100 OD CMOS CPU 3 3V Gigabit Ethernet Controller 100 Mbit sec link indicator active low Logic GBE_LINK1000 OD CMOS CPU 3 3V Gigabit Ethernet Controller 1000 Mbit sec link indicator active low Logic GBE_CTREF REF GND min Gigabit Ethernet Controller 1000MBit unconnected Unconnected 3 3V max Not required 12 Q7 TI8168 User s Manual 2 7 3 Serial ATA Pin Signal Type Laval Power Rail Remark Description SATAO TX O SATA CPU AC coupled Serial ATA Channel 0 differential transmit pair DaVin
6. Q7 TI8168 User s Manual Serial SPI PC E 2 integrated UART Controllers 1 on feature connector E integrated SPI Controller 3 slave selects 1 on feature connector E integrated IC Controller Flash Memory m NAND Flash 2GB 8Bit data bus m SPI Flash 4 MB 40 MHz SDIO Integrated 4 bit SD MMC Controller SD MMC SDHC SDIO maximum frequency 48MHz RTC RTC with I C Interface typ Power Consumption 350nA O 3V Boot sources m NAND Flash m SPI Flash m SD Card m Ethernet Power Supply 5V 4 75V 5 25V 5V 4 75V 5 25V Standby voltage 3V 1 3V 3 3V optionally for RTC U boot must be resident on the SPI Flash or the SD Card 2 2 Jumpers and switches There are no jumpers or switches on the module 2 3 Watchdog t b d 2 4 Power dissipation Mode Voltage Current Power Description lde f 5v 1 655 A 8 275W Measured at the login prompt ten minutes after booting Measured while running CPU tests fifteen minutes OPU TESIS 18234 9115W after booting LINPACK CPU test Measured while decoding HD video hardware HD video 5V ian a accelerated two minutes after rebooting Q7 TI8168 User s Manual 2 5 Block diagram MSC Q7 T18168 DaVinci SPI UART VIDEO IN C674x DSP CPU 2x SATA PCIEO USB 2 5 USB1 HOST CLIENT USBO SD CARD 4 bit SPI 12C SMB 12S
7. SPI Flash added to block diagram 11 1201 15 Added SDIO signals pull ups audio signals updated to I S 28 01 2013 18 SPI_CS1 signal not supported on Feature connector 19 Added note for JTAG signals 25 Boot options updated 31 SPI_CS1 signal removed from Feature connector 1 2 Reference Documents 1 Qseven Specification Revision 2 0 Last update September 20 2012 http www Qseven standard org Q7 TI8168 User s Manual 1 3 Signal Terminology E Signal direction Signal directions are from the module perspective For example COM TXD serial port transmit is an output from the CPU module m The symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level When is not present the signal is active at a high voltage level m Differential pairs are indicated by trailing and signs for the positive or negative signal 1 4 Introduction The MSC Q7 T18168 is part of the MSC Qseven family of Qseven CPU modules It is based on a Texas Instruments DaVinci System on a Chip SoC which incorporates a high performance ARM Cortex A8 RISC MPU together with Tl s C674x VLIW DSP core The module is fully compliant with the Qseven Specification Revision 2 0 All functionalities are listed in the Technical Information section Depending on the assembly variant different subsets are available Q7 T1I
8. kernel can be loaded from Ethernet NAND Flash or SD Card 25 Q7 TI8168 User s Manual 7 Connectors 7 1 Overview i hara ma cms of tipor aw ae aw essa fi por 5 g 0 z z ve cs Function Description Qseven edge contacts to connect to MXM connector refer to Qseven X1 Qseven Finger 230pins specification x2 Qseven Feature Connector 40pins Optional Qseven l O Connector with additional features 26 Q7 TI8168 User s Manual 7 2 PIN 1 MXM Connector X1 51 DO IFIENINIENIcIanaerandE it PISTTELELUELAPTELEL TELL ec eieieieien Pin Signal Pin Signal 1 GND GND 3 GBE MDIS 4 GBE MDI2 5 GBE MDI3 6 GBE_MDI2 7 GBE_LINK100 8 GBE LINK1000 9 GBE_MDI1 10 GBE_MDIO 11 GBE_MDI1 12 GBE MDIO 13 GBE_LINK 14 GBE_ACT 15 GBE_CTREF 16 SUS_S5 17 WAKE 18 SUS_S3 19 SUS_STAT 20 PWRBTN 21 SLP_BTN 22 LID_BTN 23 GND 24 GND KEY 25 GND 26 PWGIN 27 BATLOW 28 RSTBTN 29 SATAO TX 30 SATA1_TX 31 SATAO TX 32 SATA1_TX 33 SATA ACT amp 34 GND 35 SATAO RX 36 SATA1_RX 37 SATAO RX 38 SATA1_RX 39 GND 40 GND 41 42 SDIO_CLK 43 SDIO_CD 44 SDIO_LED 45 SDIO_CMD 46 SDIO_WP 47 SDIO_PWR 48 SDIO_DAT1 49 SDIO_DATO 50 SDIO_DAT3 51 SDIO_DAT2 52 SDIO_DAT5 27 Q7 TI8168 User s Manual
9. 18 Q7 TI8168 User s Manual 2 7 11 Input Power Pins e EE VCC Power 5V 5 Primary power input 5V 5 Voltage Regulators VCC_5V_SB Power 5V 5 Standby power input 5 0V 5 Voltage All available VCC5V0_STBY pins on the connector s shall be used Regulators Used for microcontroller and standby and suspend functions NOTE If the baseboard does not provide the VCC_5V_SB then these pins should be connected to the main VCC power supply on the baseboard VCC_RTC Power Real time clock circuit power input 3 0V 1 3V to 3 3V RTC GND Power Ground DC power and signal and AC signal return path All available GND connector pins shall be used and tied to Carrier Board GND plane 2 7 12 Manufacturing Signals Pin Signal Remark Type Level Power Tol MFG NCO Boundary Scan TCK DaVinci MFG_NC1 O CMOS CPU 3 3V Boundary Scan TDO COM TXD DaVinci Depending on MFG_NC4 the signal is either used as Boundary Scan TDO or as transmit signal for the serial debug port UART MFG_NC2 l CMOS CPU 3 3V Boundary Scan TDI COM RXD DaVinci Depending on MFG_NC4 the signal is either used as Boundary Scan TDI or as receive signal for the serial debug port UART Description Source Target MFG_NC3 CMOS CPU 3 3V Boundary Scan TMS DaVinci MFG_NC4 CMOS CPU 3 3V 4k7 PD Control Signal for multiplexer circuit DaVinci 1
10. 8168 User s Manual 2 Technical Information 2 1 Key features CPU ARM Cortex A8 processor 1 2GHz NH 32KB instruction and data caches HE 256KB L2 cache Hm 64KB RAM 48KB boot ROM C674x floating fixed point DSP operating up to 1 GHz E Up to 8000 6000 C674x MIPS MFLOPS Memory 32 bit DDR3 800MHz 1GByte Audio Video Processor HD Three HDVICP2 hardware accelerator subsystems supports resolutions up to 1080 p i with full performance of 60 fps E MPEG4 encoding amp decoding MPEG2 encoding amp decoding MPEG1 encoding amp decoding H 264 encoding amp decoding DivX 5 x and higher encoding amp decoding RV ON2 decoding AVS 1 0 encoding amp decoding WMV9 VC1 RTV encoding amp decoding JPEG MJPEG encoding amp decoding Dual Display Controller HDMI 1 3 Full HD 1080p LCD single channel 24bpp up to WXGA 1440 x 900 O 60Hz Video input 8 bit YCbCr video input up to 165MHz available on feature connector GPU SGX530 3D Graphics Engine m Delivers up to 30 MTriangles s m Direct3D Mobile OpenGLO ES 1 1 and 2 0 EH OpenVG 1 1 OpenMax API Support Ethernet Lantiq XWAY PEF7072 IEEE 802 3 compliant 10 100 1000 PCI Express One x1 PCle 1 1 port udio 12S compatible USB Integrated 2 ports USB 2 0 Controller 1x Host 1x Host Client PCle to USB Swidge for 4 additional USB 2 0 ports SATA 2 SATA 3 0 interfaces
11. Boundary Scan JTAG 0 UART 1 On some JTAG debuggers which require return clock from processor pins TCK and RCK should be connected pins 11 and 9 on Standard TI 14 pin JTAG Header This signal should have defined default logic level pull up or pull down resistor on the carrier board 19 Q7 TI8168 User s Manual 2 7 13 Power and System Management Pin Signal Level Power Rail Remark Power Tol Description Source Type PU PD Target PWRBTN I CMOS Suspend 3 3V 10k PU Power button to bring system into a power state active low Microcontroller negative pulse 6 seconds power override RSTBTN CMOS Suspend 3 3V 10k PU Reset button input Active low input System is held in hardware reset while Microcontroller this input is low and comes out of reset upon release negative pulse SUS STATH O CMOS Not supported Not supported SUS S3 O CMOS Suspend 3 3V 10k PD Indicates that the system is in Soft Off state Can be used to control an ATX Microcontroller power supply SUS_S5 O CMOS Suspend 3 3V 10k PD Indicates that the system is in Soft Off state Also known as PS ON and can Microcontroller be used to control an ATX power supply LID_BTN l CMOS Not supported Not supported SLP_BTN CMOS Not supported Not supported BATLOW CMOS Suspend 3 3V 10k PU Signal that indicates that the system battery is low Microcontroll
12. CRER a ae ns UA ERC ganas eee oe ROTA ans aa NES 8 20 BIGE GIAGIaN tena iai edit AAA e Sesi ie E ae ata date 9 BIG LEDS oir di ia UNR PIU TEE 10 2 SIGMA GASSER PON css lcanobiao in adina DE a a E aa E e Ea TEE 11 2 7 1 PCI Express Lanes iii ls 11 2 7 2 EN ii A PRA AE 12 2 7 3 Sanal ATA ci A dd aaa ra 13 2 7 4 USB e Pate e e o trae 14 2 7 5 SD lO A e ee reco es ae 15 DTG dora II iran 15 2 7 7 LVDS Flat Panel srecna aaa oa 16 2 7 8 HDMI iaa 17 2 7 9 LPG BUS IEA atid Mea ISOS REDE O a tal 17 2 12 10 SPlInlertac wits aad a Ria ata Mita Aue Hei Ning ae 18 27 11 put Power PINS ssa isso ee ee aes ed ee eee nde DO eee 19 2 7 42 Manufacturing Signals as assess pesos feast iin deine geada anidro ete atria 19 2 713 Power and System Management err nn nana c cnn nn narra nnnn nn nnnccns 20 3 ISTMO E dais 21 Sil 126 Bus Address Mapa ida 21 A Mecanica a 22 D gt rHeatspreader O A E 23 6 BOotOptiOnS 0 das 25 6 1 SD Card boot mode and SPI Flash boot mode rea 25 do CONTEO St a daa 26 Ll COVA e 26 7 2 MAMGONMECION a rectas is la si aida 27 7 3 Feature Connector X2 estoi diia 30 8 Power Domain S A tata sea EMAAR h Aana RRE Aana a a iio 32 Q7 T1I8168 User s Manual Q7 TI8168 User s Manual 1 General Information 1 1 Revision History Rev Date Pages Description 1 0 1 06 2012 All Initial Version Hardware Revision 1 0 7 Audio compatibility updated 8 Power dissipation details added 9
13. DMI CPU TMDS differential pair clock lines DaVinci TMDS_CLK HDMI_HPD l CMOS CPU 10k PD Hot plug detection signal that serves as an interrupt request DaVinci Signal can only be pulled to a logic low level HDMI_CTRL_CLK 1 0 OD CMOS CPU 3 3V 40k2 PU DDC based control signal clock for HDMI device DaVinci HDMI_CTRL_DAT O OD CMOS CPU 3 3V 40k2 PU DDC based control signal data for HDMI device DaVinci 2 7 9 LPC Bus Remark Pe Source Power Tol PU PD Description Target LPC_FRAME O CMOS CPU Not supported Not supported Not supported LPC_CLK O CMOS CPU Not supported Not supported Not supported 17 Q7 TI8168 User s Manual 2 7 10 SPI Interface see ae Power Rail Bis a PU PD Description ee SPI_MOSI O CMOS CPU 3 3V Master serial output Slave input signal CPU is master Logic SPI_MISO I CMOS CPU 3 3V Master serial input Slave output signal CPU is master Logic SPI SCK O CMOS CPU 3 3V SPI clock input Logic SPI_CSO O CMOS CPU 3 3V 5k1 PU SPI chip select 1 output active low chip select for primary device on DaVinci Qseven connector SPI_CS1 O CMOS CPU 3 3V 5k1 PU SPI chip select 2 output active low chip select for secondary device on DaVinci Qseven connector SPI_CS2H O CMOS CPU 3 3V 5k1 PU SPI chip select 3 output active low chip select for primary device on DaVinci Feature connector
14. MOS CPU 3 3V 125 Word Select output DaVinci I2S_CLK Output CMOS CPU 3 3V 128 Serial Data Clock to CODEC DaVinci 125_SDO Output CMOS CPU 3 3V Serial Data Output to CODEC DaVinci I2S_SDI Input CMOS CPU 3 3V Serial Data Input from CODEC DaVinci 15 Q7 TI8168 User s Manual 2 7 7 LVDS Flat Panel Power Remark eat Source Rail Power Tol PAD ROA Target LVDS_A 0 3 O LVDS CPU LVDS Channel A differential pairs primary channel LVDS LVDS_A 0 3 Transmitter LVDS A CLk O LVDS CPU LVDS Channel A differential clock LVDS LVDS A CLK Transmitter LVDS PPEN O CMOS CPU 3 3V LVDS panel power enable DaVinci LVDS_BLEN O CMOS CPU 3 3V 10k PD LVDS panel backlight enable DaVinci LVDS_BLT_CTRL O CMOS CPU 3 3V LVDS panel backlight brightness control DaVinci LVDS_DID_CLK O OD CMOS CPU 3 3V 1k43 PU 12C clock output for LVDS display use 12C Switch LVDS_DID_DAT O OD CMOS CPU 3 3V 1k43 PU 12C data line for LVDS display use 12C Switch 16 Q7 TI8168 User s Manual 2 7 8 HDMI Pin Type Signal Level Power Rail Remark Power Tol PU PD Description Source Target TMDS LANEO O HDMI CPU TMDS differential pair lines lane O DaVinci TMDS LANEO TMDS LANE1 O HDMI CPU TMDS differential pair lines lane 1 DaVinci TMDS_LANE1 TMDS_LANE2 O HDMI CPU TMDS differential pair lines lane 2 DaVinci TMDS_LANE2 TMDS_CLK O H
15. PRESOS maximum current 300mA 40 VCC5VO 5V 5 power supply i maximum current 300mA 31 Q7 TI8168 User s Manual 8 Power Domains Q7 T18168 LVDS LVDS vou Trasmitter HDMI REMI gt CPU ae PCIEO PCle nw Lanes Swi dge USB 2 5 gt Ethernet GEE gt SATA USB Lines Lines USB1 ai USBO el SATA x 2 gt 32 The MSC Q7 TI8168 module uses different power domains which allows for efficient power management Unused power rails can be switched off in order to reduce power consumption The diagram to the left shows all power domains green Affected functions are also shown yellow the specific signals can be found in section 2 7 The column named Power Rail reflects the power domains described in the diagram
16. User s Manual MSC Q7 TI8168 Module Texas Instruments DaVinci Rev 1 1 January 28 2013 Hardware Revision 2 0 boardsfamsc ge com www msc ge com boards Q7 T1I8168 User s Manual Preface Copyright Notice Copyright 2012 MSC Vertriebs GmbH All rights reserved Copying of this document and giving it to others and the use or communication of the contents thereof is forbidden without express authority Offenders are liable to the payment of damages All rights are reserved in the event of the grant of a patent or the registration of a utility model or design Important Information This documentation is intended for qualified audience only The product described herein is not an end user product It was developed and manufactured for further processing by trained personnel Disclaimer Although this document has been generated with the utmost care no warranty or liability for correctness or suitability for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be installed in a shielded housing If not installed in a properly shielded enclosure and used in accordance with the instruction manual this product may cause radio interference in which case the user may be required to take adequate measures at his or her owns expense Trademarks All used product names logos or trademarks are property of
17. as phase change foils gap pads and metal blocks A good thermal conductivity is required in order to transfer the heat from the hotspots to the heat spreader plate The heat spreader used for the MSC Q7 T18168 CPU module is thermally attached using phase change materials and a small aluminium block that is part of the heat spreader plate Usage of the heat spreader is obligatory but there might be applications that require additional type of cooling solution together with heat spreader passive casing heat dissipation or cooling fan In any case it is the system designer s responsibility to make sure that each device in the system operates within its specified thermal limits The cooling solution should ensure that the thermal specifications for each component are met over the full operating range of the system 23 Q7 TI8168 User s Manual Bill of Material Description MSC Q7 TI8168 01 HSP 001 Q7 Mainboard MSC Q7 TI8168 MEC Q7 COOLSTRIP ALU 70x5x5 MEC BOLT HEX M F M2 5 SW4 L5 MEC Screw Fillister Head M2 5x20 Cross 7 MEC Screw Fillister Head M2 5x6 Cross MEC NUT HEX M2 5 SW5 m2 0 12 ninio 24 Q7 T1I8168 User s Manual 6 Boot options The MSC Q7 TI8168 has several booting options 6 1 SD Card boot mode and SPI Flash boot mode SD card boot is of higher priority than SPI Flash boot If a card is present but doesn t contain a valid bootloader the CPU will skip to SPI Flash Subsequently the
18. ci SATAO TX on module SATAO RX SATA CPU AC coupled Serial ATA Channel 0 differential receive pair DaVinci SATAO RX on module SATA1_TX O SATA CPU AC coupled Serial ATA Channel 1 differential transmit pair DaVinci SATA1_TX on module SATA1_RX SATA CPU AC coupled Serial ATA Channel 1 differential receive pair DaVinci SATA1_RX on module SATA ACTH OD CMOS CPU 3 3V SATA activity indicator both channels active low Logic External Pullup has to be installed on Carrier Board 13 Q7 TI8168 User s Manual 2 74 USB USB PO Pin Type 1 0 Signal Level USB Power Rail CPU Remark Power Tol PU PD Description USB differential pair channels O Source Target DaVinci USB_PO USB_P1 1 0 USB CPU USB differential pair channels 1 DaVinci USB_P1 This port may be optionally used as USB client port USB 2 5 1 0 USB CPU USB differential pairs channels 2 to 5 PCle to USB USB 2 5 Swidge USB 0 1_OCH CMOS CPU 3 3V 1k43 PU USB over current sense USB channels 0 and 1 A pull up for this line is DaVinci present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low Do not pull this line high on the Carrier Board USB 2 3 OCH CMOS CPU 3 3V 4k7 PU USB over current sense USB channels 2 and 3 A pull up for this line is PCle to USB present on the module An open drain driver
19. ctor Device A6 A5 A4 A3 A2 A1 AO R W address 12C Switch 1 1 1 0 0101 0 x E0 Efn Available devices on Qseven on module branch Device A6 A5 A4 A3 A2 A1 AO R W address ID EEPROM 1 01 11 0 0 1010 x AO Alh RTC 1 1410 1 0 1 0100 x DO D1 8 bit address RW 21 Q7 T18168 User s Manual 4 Mechanical drawing 70 00 Qseven PCB Cooling Plate lt Y located on top and bottom sides e 6 0960 240mil Top side 5 0800 200mil Bottom side 2 6924 106mil 70 00 5 10 54 53 10 13 62 11 All measurements are in millimeters Heatspeader Qseven Module PCB Dimension is dependent on connector height used Dimension is dependent on connector height used All measurements are in millimeters All dimensions without tolerance 0 2mm Carrier Board PCB The actual height depends on the Qseven connector used on the baseboard 22 Q7 TI8168 User s Manual 5 Heat spreader The cooling solution for a Qseven module is based on a heat spreader concept The purpose of the heat spreader is to provide a standard thermal interface A heat spreader is a metal plate typically aluminium mounted on top of the module Its mechanical dimensions follow the module standard specification The connection between the metal plate and the thermal active components on the module is typically made via thermal interface materials such
20. er WAKE l CMOS Not supported Not supported THRM l CMOS Suspend 3 3V Input from off module temp sensor indicating an over temp situation Microcontroller THERMTRIP O CMOS Suspend 3 3V Active low output indicating that the CPU has entered thermal shutdown Microcontroller PWGIN 5V CMOS Suspend 5V Indicates that the external power supply is ready Microcontroller WDOUT O CMOS CPU 3 3V Output indicating that a watchdog time out event has occurred DaVinci WDTRIG l CMOS CPU 3 3V 10k PU Watchdog trigger input This signal restarts the watchdog timer DaVinci GP_TIMER_IN l CMOS Suspend 3 3V General purpose timer input Microcontroller GP_PWM_OUT1 OD CMOS Suspend 3 3V General purpose PWM output Microcontroller SPKR O CMOS CPU 3 3V 10k PD Output for audio enunciator DaVinci SMB_CLK 1 0 CMOS CPU 3 3V 10k PU System management clock line Microcontroller SMB_DAT 1 0 CMOS CPU 3 3V 10k PU System management data line Microcontroller SMB_Alert 1 0 CMOS CPU 3 3V 10k PU System management bus alert input Microcontroller 12C_CLK 1 0 CMOS CPU 3 3V 1k43 PU General purpose 12C port clock output 12C Switch 12 DAT O CMOS CPU 3 3V 1k43 PU General purpose 12C port data I O line 12C Switch SMBus covers complete address range 20 Q7 T18168 User s Manual 3 System resources 3 1 12C Bus Address Map The on board 12C switch splits the 12C bus into two branches Qseven on module 12C System I2C going to the Qseven conne
21. from a USB current monitor on Swidge the Carrier Board may drive this line low Do not pull this line high on the Carrier Board USB 4 5 OCH CMOS CPU 3 3V 4k7 PU USB over current sense USB channels 4 and 5 A pull up for this line is PCle to USB present on the module An open drain driver from a USB current monitor on Swidge the Carrier Board may drive this line low Do not pull this line high on the Carrier Board USB_ID CMOS CPU 3 3V USB ID pin High signal level configures USB Port1 and CPU as USB DaVinci Client USB_CC l CMOS CPU 3 3V USB client connect pin DaVinci 14 Q7 TI8168 User s Manual 2 7 5 SDIO Pin Type aon Power Rail alicia PU PD Description SDIO DAT 0 3 1 0 3 3V CPU 3 3V 10k PU SDIO Controller Data DaVinci SDIO_CD 3 3V CPU 3 3V SDIO Controller Card Detect DaVinci SDIO_CMD O 3 3V CPU 3 3V 10k PU SDIO Controller Command DaVinci SDIO CLK O 3 3V CPU 3 3V 10k PU SDIO Controller Clock DaVinci SDIO_PWR 1 0 3 3V CPU 3 3V 10k PU SDIO Controller Power enable Logic SDIO_LED O 3 3V CPU 3 3V 10k PD SDIO Controller transfer activity LED DaVinci SDIO_WP 3 3V CPU 3 3V SDIO Controller Write Protect DaVinci 2 7 6 Audio PS Pin Type Signal Level Power Power Rail Ea Tolerance PU PD Description Source Target 2S RSTH Output CMOS CPU 3 3V 10k PD Reset output to CODEC active low DaVinci 125 WS Output C
22. their respective owners Certification MSC Vertriebs GmbH is certified according to DIN EN ISO 9001 2000 standards Life Cycle Management MSC products are developed and manufactured according to high quality standards Our life cycle management assures long term availability through permanent product maintenance Technically necessary changes and improvements are introduced if applicable A product change notification and end of life management process assures early information of our customers Product Support MSC engineers and technicians are committed to provide support to our customers whenever needed Before contacting Technical Support of MSC Vertriebs GmbH please consult the respective pages on our web site at www mscembedded com support center for the latest documentation drivers and software downloads If the information provided there does not solve your problem please contact our Technical Support Email support boards mscembedded com Phone 49 8165 906 200 Q7 T1I8168 User s Manual Content AAA insana Kaanaan anaa ias casais a ncia sussa sad AAE 5 TA e Revision Histor Sectas titi 5 1 2 Reference Docus 5 113 Signal Terminology seni a E PE AE AEE PR PR 6 1 4 gt Introducir il alar Bakes 6 27 Technical AN tt 7 2 1 Key TOAUINCS r t ereitean rol cortes AL ti aa teens Ain eaea Dias SE ane gas nen 7 22 J mpers and SWITCHES mins Ae 8 Pas RA feto q 6 6 ii 8 2 4 Power dissipation casas aan ee eed Gra casas
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