Correction for Incorrect Description Notice RL78/G13 Descriptions in
Contents
1. AVREFM ANM target ANI pin ANI2 to ANI14 added page 1032 Incorrect 1 When AVREF AVRErP ANI0 ADREFP1 0 ADREFPO 1 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANI2 to ANI14 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss 0 V Reference voltage AVREFP Reference voltage AVrerm 0 V Parameter Conditions Resolution Notes a 10 bit resolution 1 8 V lt VpD lt 5 5V AVRerp Voo 16V Vop 5 5 V Overall error Conversion time Zero scale errorNotes 1 2 Omitted Full scale error e 1 2 Integral linearity error e Differential linearity error Note 1 Reference voltage AVREFP Analog input voltage VAIN VBGR 24V lt Vop lt 5 5 V Omitted Re Page 46 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Correct 1 When AVREF AVrerP ANIO ADREFP1 0 ADREFPO 1 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANI2 to ANI14 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage AVREFP Reference voltage AVrerm 0 V Parameter Conditions Resolution Bile i 10 bit resolution 1 8 V lt VpD lt 5 5V AVRerp Voo 16V Von 5 5 V Overall error Conversion time Zero scale errorNotes 1 2 Omitted Full2. gt Z o Ss m c Q If a reset is not generated after releasing the mask determine that a condition of Von becomes VDD gt VLVIH clear LVIMD and the MCU returns to normal operation Supply voltage VoD Vpor 1 51 V TYP VPoR 1 50 V TYP LVIMK flag set by software are Cleared by software Cleared by softw Wait for stabilization by software 400 us or 5 clocks of fiL Note 3 Normal operation LJ RESET Normal operation Save processing Normal operation Operation status LVIF flag LVISEN flag set by software LVIOMSK flag LVIMD flag Cleared by software Note 3 LVILV flag y Cleared b software Note 2 LVIRF flag LVD reset signal POR reset signal Internal reset signal LVIIF flag Page 33 of 54 RENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 After an interrupt is generated perform the processing according to figure 21 7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode 3 After a reset is released perform the processing according to figure 21 8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode Remark Vror POR power supply rise detection voltage Vppr POR power supply fall detection voltage Re Page 34 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date J
3. AVrerm 0 V Parameter Conditions Resolution Conversion time 8 bit resolution 2 4 V lt VoD lt 5 5 V Zero scale errorN s 1 2 8 bit resolution 2 4 V lt VDD lt 5 5V Integral linearity error e 8 bit resolution 2 4 V lt VDD lt 5 5 V Differential linearity error ete 1 8 bit resolution 2 4V lt VpD lt 5 5V Reference voltage VBGR Reference voltage AVREFM Analog input voltage VAN Omitted Correct 4 When AVREF Internal reference voltage ADREFP1 1 ADREFPO 0 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANIO to ANI14 ANI16 to ANI26 Ta 40 to 85 C 2 4 V Vpn lt 5 5 V Vss EVsso EVss1 0 V Reference voltage Vacr Reference voltage AVREFM 0 V HS high speed main mode Parameter Conditions Resolution Conversion time 8 bit resolution 24VxVppx5 5V Notes 1 4 8 bit resolution 24V xVpp x 5 5V Zero scale error Integral linearity error e 8 bit resolution 2 4V lt VpD lt 5 5V Differential linearity error e 1 8 bit resolution 2 4V lt Vpp lt 5 5V Reference voltage VBGR Reference voltage AVREFM Analog input voltage VAIN Omitted Re Page 52 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 14 Condition of Temperature sensor characteristics in Electrical Specifications chapter section 29 7 2 added page 1036
4. Incorrect 29 7 2 Temperature sensor characteristics Ta 40 to 85 C 2 4 V lt EVopo EVpp x Von x 5 5 V Vss EVsso EVss1 0 V Parameter Conditions Temperature sensor output voltage Vrweszs Setting ADS register 80H TA 25 C Reference output voltage Vconst Setting ADS register 81H Temperature coefficient Fvrmes Temperature sensor that depends on the temperature Operation stabilization wait time tame Correct 29 7 2 Temperature sensor characteristics Ta 40 to 85 C 2 4 V lt Voo lt 5 5 V Vss EVsso EVss 0 V HS high speed main mode Parameter Conditions Temperature sensor output voltage Vrweszs Setting ADS register 80H TA 25 C Reference output voltage Vconst Setting ADS register 81H Temperature coefficient Fvrmps Temperature sensor that depends on the temperature Operation stabilization wait time tame zu Page 53 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Issued Document History RL78 G13 Incorrect description notice issued document history Document Number TN RL A001A E Dec 5 2011 First edition issued Incorrect descriptions of No 1 to No 10 revised TN RL A001B E Jan 31 2012 Rev 2 00 issued Revisions of No 11 to No 14 incorrect descriptions added Re Page 54 of 54 sE NESAS
5. no wait mode Note Hardware trigger detection i 1 is written 0 is written to ADCS to ADCS Conversion Stabilization Conversion Conversion Conversion 7 standby Waittime operation standby 7 stopped Hardware trigger ADCS i wait mode 1 Hardware trigger 0 is written detection to ADCS Note Omitted Re Page 14 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Correct Figure 11 4 Timing Chart When A D Voltage Comparator Is Used A D voltage comparator enables operation AID voltage comparator Y aw NK Conversion Conversion Conversion Conversion a m standby MES operation standby stopped Software trigger mode i Note 1 t 1 is written 0 is written to ADCS to ADCS ADCS Conversion Trigger JL malin Conversion Conversion standby Standby operation standby 7 stopped Hardware trigger no waitmode DCS memE 10 1 is written 0 is written Conversion Conversion Conversion Conversion gt standby operation standby stopped Hardware trigger ADCS wait mode t 0 is written to ADCS Note 1 Omitted 2 The following time is the maximum amount of time necessary to start conversion ADMO Conversion FR2 Clock Software trigger mode Hardware trigger wait mode fap Hardware trigger no wait mode lol ww e o s mua a halal sue
6. 1 45 V cannot be used for the side reference voltage source Correct Figure 11 11 Format of Analog Input Channel Specification Register ADS 2 2 Address FFF31H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADS ADISS o ADS4 ADS3 ADS2 ADS1 ADSO Omitted Cautions 1 Be sure to clear bits 5 and 6 to 0 Omitted If using AVREFP as the side reference voltage source of the A D converter do not select ANIO as an A D conversion channel If using AVREFM as the side reference voltage source of the A D converter do not select ANI1 as an A D conversion channel If ADISS is set to 1 the internal reference voltage 1 45 V cannot be used for the side reference voltage source When entering STOP mode or HALT mode while the CPU is operating on the subsystem clock do not set ADISS to 1 When setting ADISS to 1 the current value of the A D converter reference voltage current laprer shown in 29 4 2 Supply current characteristics is added zu Page 23 of 54 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 7 Incorrect descriptions of maskable interrupt request acknowledgement operation revised Revised incorrect description of time from generation of maskable interrupt until servicing in Table 16 4 page 842 Incorrect 16 4 1 Maskable interrupt request acknowledgment Omitted Table 16 4 Time from Generation of Maskable Interrupt Until Servicing equest is generated j be Remark 1
7. ANIO to ANI14 ANI16 to ANI26 24V lt Von lt 5 5 V Omitted Re Page 50 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Correct 3 When AVREF Voo ADREFP1 0 ADREFPO 0 AVREF Vss ADREFM 0 target ANI pin ANIO to ANI14 ANI16 to ANI26 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage Vpn Reference voltage Vss Parameter Conditions Resolution Overall errorN tes 1 2 10 bit resolution 1 8 V lt VpD lt 5 5V 1 6V lt Vpp lt 5 5V Conversion time Zero scale error s 1 2 Omitted Full scale error 1 2 Integral linearity error e Differential linearity error Note 1 Analog input voltage ANIO to ANI14 ANI16 to ANI26 24V lt Vpp lt 5 5V HS mode Omitted Re Page 51 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Condition of 4 When AVREF Internal reference voltage AVREF AVREFM ANI1 target ANI ANIO to ANI14 ANI16 to ANI26 added page 1035 Incorrect 4 When AVREF Internal reference voltage ADREFP1 1 ADREFPO 0 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANIO to ANI14 ANI16 to ANI26 Ta 40 to 85 C 1 6 V x EVppo EVpp1 x Von x 5 5 V Vss EVsso EVss1 0 V Reference voltage Vacr Reference voltage
8. Converter Mode Register 2 ADM2 1 2 Address F0010H After reset 00H R W Symbol 7 6 5 4 lt 3 gt lt 2 gt 1 lt 0 gt ADM2 ADREFP1 ADREFPO ADREFM ADRCK awc o ADTYP ADREFP1 ADREFPO Selection of the side reference voltage source of the A D converter Supplied from Vpn Supplied from P20 AVrerr ANIO Supplied from the internal reference voltage 1 45 V Setting prohibited Omitted Note This setting value can be selected only in HS high speed main mode Omitted Re Page 40 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 input channel specification register ADS added Incorrect Figure 11 11 Format of Analog Input Channel Specification Register ADS 1 2 O Select mode ADMD 0 ADSO Analog input Input source channel P20 ANIO AVnere pin P21 ANI1 AVrerm pin Setting prohibited Temperature sensor output Internal reference voltage Other than the above Setting prohibited 1 20 24 25 30 32 pin products PO1 ANI16 pin 2 20 24 25 30 32 pin products POO ANI17 pin Correct Figure 11 11 Format of Analog Input Channel Specification Register ADS 1 2 O Select mode ADMD 0 ADSO Analog input Input source channel P20 ANIO AVnere pin P21 ANI1 AVrerm pin Omitted 1 Setting prohibited 0 Temperature sensor output 3 Internal reference voltage outp
9. Generation Option Byte LVIMDS1 LVIMDSO 1 1 Supply voltage Voo Vivi VPOR 1 51 V TYP VPpR 1 50 V TYP LVIMK flag set by software LVISEN flag rog ME LVIF flag d cleared LVIOMSK flag LVIMD flag LVILV flag LVIRF flag LVD reset signal Cleared by i Cleared by i Cleared by software software software l POR reset signal Internal reset signal Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 LVIRF flag is bit 0 of the reset control flag register RESF The LVIRF flag ma come 1 from the beginning due to the power on waveform For details of the RESF register see CHAPTER 19 RESET FUNCTION R Page 26 of 54 sKENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Correct Figure 21 4 Timing of Voltage Detector Internal Reset Signal Generation Option Byte LVIMDS1 LVIMDSO 1 1 Supply voltage VoD Vii VPoRz 1 51 V TYP VPDR 1 50 V TYP Cleared LVIF flag LVIMD flag i d 1 1 Not cleared Not cleared LVILV flag Not cleared LVIRF flag RESF register LVD reset signal Cleared by j Cleared by software i software POR reset signal Internal reset signal Re Page 27 of 54 s lt ENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Figure 21 5 Incorrect description of voltage detector internal interrupt signal generation timing revised page 896 In
10. Re Page 36 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Figure 21 7 Processing Procedure After an Interrupt Is Generated INTLVI generated i LVD reset generated Normal operation RENESAS Perform required save processing Set the LVISEN bit to 1 to mask voltage detection LVIOMSK 1 Set the LVILV bit to 0 to set the high voltage detection level VLVIH Set the LVISEN bit to 0 to enable voltage detection The MCU returns to normal operation when internal reset by voltage detector LVD is not generated since a condition of VDD becomes VoD gt VLVIH Set the LVISEN bit to 1 to mask voltage detection LVIOMSK 1 Set the LVIMD bit to 0 to set interrupt mode Set the LVISEN bit to 0 to enable voltage detection Page 37 of 54 RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Figure 21 8 Explanations of initial setting of interrupt and reset mode added When setting an interrupt and reset mode LVIMDS1 LVIMDSO 1 0 voltage detection stabilization wait time for 400 us or 5 clocks of fiL is necessary after LVD reset is released LVIRF 1 After waiting until voltage detection stabilizes 0 clear the LVIMD bit for initialization While voltage detection stabilization wait time is being counted and when the LVIMD bit is rewritten set LVISEN to 1 to mask a reset or interrupt generation by LVD Figur
11. clock 1 fc k fcuk CPU clock Correct 16 4 1 Maskable interrupt request acknowledgment Omitted Table 16 4 Time from Generation of Maskable Interrupt Until Servicing Note Maximum time does not apply when an instruction from the internal RAM area is executed Remark 1 clock 1 fc k fcu CPU clock Re Page 24 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Figure 16 9 Incorrect description of interrupt request acknowledgment timing maximum time revised page 844 Incorrect Figure 16 9 Interrupt Request Acknowledgment Timing Maximum Time 6 clocks 6 clocks i PSW and PC saved interrupt servicing CPU processing Instruction RET instruction jump to interrupt OG servicing prog xxIF MEN FRE 14 clocks Remark 1 clock 1 fcik fcu CPU clock Correct Figure 16 9 Interrupt Request Acknowledgment Timing Maximum Time 8 clocks 6 clocks A Instruction immediately PSW and PC saved Interrupt servicing SSS 16 clocks Remark 1 clock 1 fc k fcu CPU clock Re Page 25 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 8 Incorrect descriptions of voltage detector LVD timing chart revised Figure 21 4 Incorrect descriptions of timing of voltage detector internal reset signal generation revised page 894 Incorrect Figure 21 4 Timing of Voltage Detector Internal Reset Signal
12. control register 0 RTCCO If the AMPM bit value is changed the values of the HOUR register change according to the specified time system If a value outside the range is set the register value returns to the normal value after 1 period The HOUR register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 12H However the value of this register is 00H if the AMPM bit bit 3 of the RTCCO register is set to 1 after reset Correct 7 Hour count register HOUR The HOUR register is an 8 bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 decimal and indicates the count value of hours It counts up when the minute counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the minute count register overflows while this register is being written this register ignores the overflow and is set to the value written Specify a decimal value of 00 to 23 01 to 12 or 21 to 32 by using BCD code according to the time system specified using bit 3 AMPM of real time clock control register 0 RTCCO If the AMPM bit value is changed the values of the HOUR register change according to the specified time system The HOUR register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 12H However the value of this register is 00H if the AMPM bit
13. lal we 7 O jojo ola mus rr ala Remark fcLK CPU peripheral hardware clock frequency 1 1 i 1 1 1 1 1 zu Page 15 of 54 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 5 Incorrect descriptions of Table 11 3 A D Conversion Time Selection 6 8 to 8 8 when there is stabilization wait time pages 489 to 491 Incorrect Table 11 3 A D Conversion Time Selection 6 8 6 2 7 V lt VoD lt 3 6 V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 Conversion Time Selection ADMO CLK fcLk fcLkK fcLk fcLk FR2 FR1 FRO LV1 LVO 2 MHz 4 MHz 8 MHz 16 MHz 32 MHz i 54 us Setting Setting H fcu 64 Setting I prohibited prohibited Prt 54 s 27 us fax 32 Setting 54 27 135us fote 16 siga 909 prohibited 54 27 gt 35 6 75 gt orma 1 40 5us 20 25 us 10 125 us 5 0625 us fc 6 3375us 16 875 us 8 4375 us foux 5 6 75 us prohibited 54 us 27us 13 5 us HS Setting foux 2 prohibited Conversion Clock faD N Gi E o E Setting 49 50 us fouK 64 Setting ay prohibited pied prohibited 50 us am prohibite eani Setting 50 us 25 us 12 5 us fcu 16 etting Te 4 Normal prohibited prohibited s0 us 25us iii aus 2 37 5 us 18 75 us 9 375 us 4 6875 us fc W6 15 625 us 7 8125 us 31 25 us u foux 5 prohibited 50 us 25us 125ygs 6 25u
14. s prohibited Setti mee NE 9 fox 2 prohibited o Lr e a Setting Setting 38 us fcuW 64 Setting prohibited prohibited prohibited foux 32 seine oie zu 4 4 Low prohibited fcik 8 Voltage 2 feik 6 i feik 5 19 us prohibited prohibited fcuk 4 prohibited Note Omitted Re Page 20 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Correct Table 11 3 A D Conversion Time Selection 8 8 8 1 6 V lt VDD lt 1 8 V When there is stabilization wait time hardware trigger wait mode Conversion Time Selection fcLK fcLK 4 MHz 8 MHz Normal Setting x x 1 prohibited A D Converter Mode Gizl 0 Gizl Conversion Clock fan Setting i MENE Normal Setting x x x 1 _ x 2 prohibited Setting prohibited Low Voltage 1 Setting prohibited Setting prohibited Low Voltage 2 Setting prohibited Note Omitted Setting prohibited Setting prohibited Setting prohibited Setting prohibited prohibited Setting prohibited Setting prohibited RENESAS Setting prohibited prohibited prohibited Setting prohibited Setting prohibited prohibited prohibited fck 64 fcLx 64 Page 21 of 54 RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 6 Note when entering A D converter standby mode added Note on A D converter mode register 2 ADM2 added page 493 Incorrect 4 A D converter mode re
15. 5us 125ys 6 25us Setting foux 2 prohibited Settin Setting 9 42us foux 64 Setting oe prohibited prohibited 21 ii prohibited 42 us us CL Setting Wis 42 us 21 us fcud 16 prohibited 1 boul prohibited 42 us 21 us fcu 8 31 5 us fc k 6 Settin 26 25 ps Setting a fcud5 Setting prohibited prohibited 21 uS prohibited fouxl4 42 us 21 us Setting isl prohibited Setting Setting SS ps foLK 64 Setting ne prohibited prohibited 38 us 19 m prohibited i us cL Bug oe 38us 19ys fex 46 prohibited LOW prohibited 38 us 19 us feud 8 1 1 Voltage 2 cece foux 6 Setting 23 75us T Setting prohibited fork 5 po prohibited 1995 prohibited fcud4 38 us 19 us Setting um prohibited Page 19 of 54 RENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Correct Table 11 3 A D Conversion Time Selection 7 8 7 1 8V lt VpD lt 2 7V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 ADMO Conversion Time Selection fcLk fcLk fcLk fcLk fcLk fCLK o FR2 FR1 FRO tvi iv Vede 1 MHz 2 MHz 4 MHz 8 MHz 16 MHz 32 MHz Normal X X X 1 Setting prohibited Normal x X X 1 2 Setting prohibited Setti Setting 9 42us fow64 Setting prohibited prohibited Setting pone 42 us Mus ys 10416 prohibited Low prohibited 42 us 21 ps fcLk 8 Voltage 1 31 5 us fcu 6 26 25 us 42us 21us foul4 s
16. Date Jan 31 2012 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Document Category MPUIMGU No TN RL A001B E Rev 2 00 Correction for Incorrect Description Notice Information Title RL78 G13 Descriptions in the Hardware User s Manual Cat Technical Notification Rev 1 00 Changed ategory Lot No Applicable RL78 G13 Group Reference Product R5F100xxx R5F101xxx RL78 G13 User s Manual Hardware D t Rev 1 00 All lot ocument R01UH0146EJ0100 Sep 2011 This document describes misstatements found in the RL78 hardware user s manual Rev 1 00 R01UH0146EJ0100 Corrections Applicable Page Applicable Item Pages 493 496 Explanations when using temperature sensor and 523 530 i internal reference voltage 1 45 V of A D converter Explanations added i added Explanations when using temperature sensor and Pages 917 to 919 internal reference voltage 1 45 V of A D test Explanations added function in Safety functions chapter added Pages 1032 Conditions of A D converter characteristics in Electrical specifications chapter section 29 7 1 Conditions added to 1035 added Condition of Temperature sensor characteristics in Page 1036 Electrical specifications chapter section 29 7 2 Condition added added Incorrect Bold with underline Correct Gray hatched Document Improvement The above corrections will b
17. SF100LEAFC RSFI00LFAFC R5F100LGAFC R5F100LHAFC R5F100LJAFC R5F100LCABG R5F100LDABG R5F100LEABG R5F100LFABG R5F100LGABG R5F100LHABG R5F100LJABG R5F101LCABG R5F101LDABG R5F101LEABG R5F101LFABG R5F101LGABG R5F101LHABG R5F101LJABG RENESAS Page 3 of 54 RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Correct Data flash Part Number Omitted R5F100LCAFA R5F100LDAFA R5F100LEAFA R5F100LFAFA Mounted R5F100LGAFA R5F100LHAFA R5F100LJAFA R5F100LKAFA R5F100LLAFA 64 pin plastic LQFP 12x12 R5F101LCAFA R5F101LDAFA R5F101LEAFA R5F101LFAFA ot R5F101LGAFA R5F101LHAFA R5F101LJAFA R5F101LKAFA mounted R5F101LLAFA R5F100LCAFB R5F100LDAFB R5F100LEAFB R5F100LFAFB Mounted R5F100LGAFB R5F100LHAFB R5F100LJAFB R5F100LKAFB N 64 pin plastic LQFP fine pitch RSF100LLAFB R5F101LLAFB i R5F100LCABG R5F100LDABG R5F100LEABG R5F100LFABG ounte R5F100LGABG R5F100LHABG R5F100LJABG 64 pin plastic FBGA 4 x 4 i o Not R5F101LCABG R5F101LDABG R5F101LEABG R5F101LFABG mounted 10 x 10 R5F101LCAFB R5F101LDAFB R5F101LEAFB R5F101LFAFB ot R5F101LGAFB R5F101LHAFB R5F101LJAFB R5F101LKAFB mounted R5F101LGABG R5F101LHABG R5F101LJABG Re Page 4 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Pin configuration of 64 pin plastic TQFP 7 x 7 deleted page 17 Incorrect 1 3 11 64 pin products 64 pin plastic LQFP 12 x 12 64 pin p
18. Vppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage AVREFP Reference voltage AVREFM Parameter Conditions Resolution Bile i 10 bit resolution 1 8 V lt VpD lt 5 5V AVRerp Voo 1 6V lt Vpp lt 5 5V Overall error Conversion time Zero scale errorN ss 1 2 Full scale error es 1 2 Omitted Integral linearity errorNete 1 Differential linearity error 1 Reference voltage AVREFP Analog input voltage VAN 24V lt Vpp lt 5 5V HS mode Omitted Re Page 49 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Condition of 3 When AVREF VDD AVREF VSS target ANI pin ANIO to ANI14 ANI16 to ANI26 added page 1034 Incorrect 3 When AVREF Voo ADREFP1 0 ADREFPO 0 AVrer Vss ADREFM 0 target ANI pin ANIO to ANI14 ANI16 to ANI26 Ta 40 to 85 C 1 6 V lt EVppo EVpn1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage Vpn Reference voltage Vss Parameter Resolution Conditions Overall error 1 2 10 bit resolution 1 8 V lt Voo lt 5 5 V 1 6 V lt VoD lt 5 5 V Conversion time Zero scale error s 1 2 Full scale error s 1 2 Integral linearity error e Differential linearity error Omitted Analog input voltage
19. an 31 2012 Correct Figure 21 6 Timing of Voltage Detector Reset Signal and Interrupt Signal Generation Option Byte LVIMDS1 LVIMDSO 1 0 2 2 When a condition of Vop is VpD lt VLVIH after releasing the mask a reset is generated because of LVIMD 1 reset mode Supply voltage VoD ViviH Vivit Vpor 1 51 V TYP VPbR 1 50 V TYP LVIMK flag set by software Cleared by software Wait for stabilization by software 400 us or 5 clocks of fiL Normal Save gt Operation status Speraton Yerocessing RESET Normal operation RESET Save processing E Cleared LVIF flag LVISEN flag set by software 7 LVIOMSK flag LVIMD flag E Cleared by LVILV flag Software Note 3 Cleared by LVIRF flag software Note 2 LVD reset signal POR reset signal Internal reset signal INTLVI LVIIF flag Re Page 35 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 After an interrupt is generated perform the processing according to figure 21 7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode 3 After a reset is released perform the processing according to figure 21 8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode Remark Vror POR power supply rise detection voltage Vppr POR power supply fall detection voltage
20. bi prohibited prohibite Setting prohibited 108 ys fcu 32 prohibited fc k 16 Low Setting fo x 8 Voltage 1 i prohibited fc 6 Setting fetk 5 Setting prohibited fotk 4 Setting prohibited prohibited fcik 2 Setting fcLx 64 Setting prohibited Setting prohibited fcux 32 prohibited fc k 16 Setting fo K 8 prohibited fc 6 Setting P prohibited feud 5 Setting prohibited prohibited fork 4 prohibited Setting prohibited fcik 2 Note Omitted Re Page 18 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Correct Table 11 3 A D Conversion Time Selection 6 8 6 2 7 V lt VoD lt 3 6 V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 Conversion Time Selection ADMO CLK fcLk fcLK CLK fcLk FR2 FR1 FRO LV1 LVO 2 MHz 4 MHz 8 MHz 16 MHz 32 MHz i 54 us Setti Sening n i nd etting ns ibi prohibited DS 54 is 27 us feu 32 Setting 54 us 27 us fc 16 40 5us 20 25ps 10 125 us 5 0625 us fcix 6 Conversion Clock fAD 3375us 16 875 us 8 4375 us fcudb 6 75 us prohibited 54 us 27us 13 5 us HS Setting foux 2 prohibited Setting prohibited Setting Setting prohibited prohibited 29s tena Setting 50us 25us fcuk 16 etting a 375us 1875us 9 375 us 4 6875 us fax 6 3125 us 15 625 us 7 8125 us fads prohibited 50 us 2
21. bit 3 of the RTCCO register is set to 1 after reset Re Page 8 of 54 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Incorrect description of day count register DAY in real time clock deleted page 442 Incorrect 8 Day count register DAY The DAY register is an 8 bit register that takes a value of 1 to 31 decimal and indicates the count value of days It counts up when the hour counter overflows This counter counts as follows Omitted When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the hour count register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 01 to 31 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period The DAY register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 01H Correct 8 Day count register DAY The DAY register is an 8 bit register that takes a value of 1 to 31 decimal and indicates the count value of days It counts up when the hour counter overflows This counter counts as follows Omitted When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the hour count register overflows while this register is bein
22. ce voltage or higher voltage to a pin selected by the ADS register However it is no problem that a pin not selected by the ADS register is inputed voltage greater than the internal reference voltage Caution The internal reference voltage 1 45 V can be selected only in HS high speed main mode Re Page 43 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 12 Explanations of A D test function in Safety functions chapter section 22 3 8 added Explanation of Figure 22 15 A D test register ADTES added page 917 Incorrect 1 A D test register ADTES Figure 22 15 Format of A D Test Register ADTES Address F0013H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADTES1 ADTESO A D conversion target 0 0 This i ifi i log i ificati i ADS AVREFM 1 1 AVREFP Other than the above Setting prohibited Correct 1 A D test register ADTES Figure 22 15 Format of A D Test Register ADTES Address FOO13H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADTES1 ADTESO A D conversion target ANIxx This is specified using the analog input channel specification register ADS AVREFM 1 1 AVREFP Other than the above Setting prohibited Note The temperature sensor output and internal reference voltage output 1 45 V can be selected only in HS high speed main mode Re Page 44 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Incorre
23. correct Figure 21 5 Timing of Voltage Detector Internal Interrupt Signal Generation Option Byte LVIMDS1 LVIMDSO 0 1 Supply voltage Von Vivi VPOR 1 51 V TYP VPDR 1 50 V TYP LVIMK flag set by software i Cleared by Software LVISEN flag Cleared LVIF flag LVIOMSK flag LVIMD flag LVILV flag INTLVI LVIIF flag LVIRF flag LVD reset signal Cleared by software POR reset signal Internal reset signal Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 LVIRF flag is bit 0 of the reset control flag register RESF The LVIRF flag ma come 1 from the beginning due to the power on waveform For details of the RESF register see CHAPTER 19 RESET FUNCTION Re Page 28 of 54 s lt E NESAS Date Jan 31 2012 RENESAS TECHNICAL UPDATE TN RL A001B E ed 2 Oo t o t S 72 Q 5 E 0 2 Ve c wi 0 O po O o 2 0 a oO D o 2 O gt Yy o D amp He Nt N o 2 D LL 0 1 Option Byte LVIMDS1 LVIMDSO Supply voltage Von Vpor 1 51 V TYP VEDR 1 50 V TYP duezcesecuesmeuaedheuesdegecucuecqeueem ec LVIMK flag interrupt mask set by software Cleared by software LVIF flag LVIMD flag LVILV flag LVIIF flag LVD reset signal POR reset signal Internal rese
24. ct Figure 22 16 Format of Analog Input Channel Specification Register ADS 1 2 O Select mode ADMD 0 ADSO Analog input Input source channel P20 ANIO AVnere pin P21 ANI1 AVrerm pin Omitted 1 Setting prohibited 0 Temperature sensor output Internal reference voltage Other than the above Setting prohibited Notes and cautions are listed on the next page Notes 1 20 24 25 30 32 pin products PO1 ANI16 pin 2 20 24 25 30 32 pin products POO ANI17 pin Omitted Correct Figure 22 16 Format of Analog Input Channel Specification Register ADS 1 2 O Select mode ADMD 0 ADSO Analog input Input source channel P20 ANIO AVnere pin P21 ANI1 AVRerm pin Omitted 1 Setting prohibited 0 Temperature sensor output 3 Internal reference voltage output 1 45 v e Other than the above Setting prohibited Notes and cautions are listed on the next page Notes 1 20 24 25 30 32 pin products PO1 AN116 pin 2 20 24 25 30 32 pin products POO ANI17 pin 3 This setting value can be selected only in HS high speed main mode Omitted Re Page 45 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 13 Conditions of A D converter characteristics in Electrical specifications chapter section 29 7 1 added Condition of 1 When AVREF AVREFP ANIO AVREF
25. e o gt o E o c o 5 c o 7 o xe o o pn un o o Incorrect Figure 21 6 Timing of Voltage Detector Reset Signal and Interrupt Signal Generation Option Byte LVIMDS1 LVIMDSO 1 0 Supply voltage VoD LVIMK flag set by software Cleared by software Normal Normal operation operation Operation status Save processing LVIF flag LVISEN flag set by software LVIOMSK flag LVIMD flag LVILV flag LVIRF flag Cleared LVD reset signal Cleared by software Cleared by software POR reset signal Internal reset signal LVIIF flag Page 31 of 54 RENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 LVIRE flag is bit 0 of the reset control flag register RESF The LVIRE flag may become 1 from the beginning due to the power on waveform For details of the RESF register see CHAPTER 19 RESET FUNCTION Remark Vror POR power supply rise detection voltage Vppr POR power supply fall detection voltage zu Page 32 of 54 sE NESAS Date Jan 31 2012 RENESAS TECHNICAL UPDATE TN RL A001B E e oj RI o o O is En o o 2 o No e c E 0 o o ag D o O o o a o e E o gt o c E a N o ES gt 2 LL e e 1 o ip Q gt Z D Q
26. e 21 8 shows the procedure for initial setting of interrupt and reset mode Figure 21 8 Initial Setting of Interrupt and Reset Mode Power supply started Reset source Refer to Figure 21 9 Checking reset source determined Check internal reset generation by LVD circuit Set the LVISEN bit to 1 to mask voltage detection LVIOMSK 1 Voltage detection Count 400 us or 5 clocks of fiL by software stabilization wait time Set the LVIMD bit to 0 to set interrupt mode e N 0 Set the LVISEN bit to 0 to enable voltage detection p Normal operation Remark fiL Low speed on chip oscillator clock frequency Re Page 38 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 10 Added common item for all RL78 G13 products in 29 4 2 Supply current characteristics of Electrical specifications page 1005 Incorrect 4 Common to RL78 G13 all products TA 2 40 to 85 C 1 6 V x EVpbo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V Sms T wins VR WP WK UT RTC operating Notes 1 2 Ifsug 32 768 kHz Real time clock operation Lo pep 1 current Interval timer operation Watchdog timer N fiL 15 kHz 0 22 operating current A D converter otes o When conversion Normal mode AVREFP Voo 5 0 V operating at maximum Low voltage mode AVREFP Vpp 3 0 V 0 5 0 7 current speed Temperature sensor operating current LVD ope
27. e made for the next revision of the hardware user s manual around February 2012 Contact a Renesas Electronics sales department details on the publishing schedule c 2012 Renesas Electronics Corporation All rights reserved Page 1 of 54 s2ENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Corrections in the hardware user s manual Document No RO1UH0146JJ0100 RO1UH0146JJ0200 l English R01UH0146EJ0100 R01UH0146EJ0200 Incorrect descriptions of 64 pin plastic TQFP 7 x 7 deleted E ME real time clock deleted Explanations of interval timer control register ITMC added Explanations of timing chart when A D voltage comparator is used added Incorrect descriptions of A D conversion time selection there is stabilization wait time 6 8 to 8 8 revised standby mode added Incorrect descriptions of maskable interrupt request acknowledgment operation Incorrect descriptions of voltage detector LVD timing chart revised KE LVD interrupt and reset mode revised Number 4 of Supply current characteristics in Electrical specifications chapter section 29 4 2 is the same for all RL78 G13 Group products Applicable Item Rev 1 00 After Rev 2 009 No Explanations when using temperature sensor and internal reference voltage 1 45 V of A D converter added Explanations when using temperature sensor and internal reference voltage 1 45 V of A D test function in Safety functions chapter added Conditio
28. f years It counts up when the month count register MONTH overflows Values 00 04 08 92 and 96 indicate a leap year When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the MONTH register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 00 to 99 to this register in BCD code The YEAR register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Re Page 12 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 3 Caution of interval timer control register ITMC in 12 bit interval timer added Incorrect 3 Interval timer control register ITMC Omitted Cautions 1 Before changing the RINTE bit from 1 to 0 use the interrupt mask flag register to disable the INTIT interrupt servicing When the operation starts from 0 to 1 again clear the ITIF flag and then enable the interrupt servicing 2 The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit 3 Only change the setting of the ITCMP11 to ITCMPO bits when RINTE 0 However it is possible to change the settings of the ITCMP11 to ITCMPO bits at the same time as when changing RINTE from 0 to 1 or 1 to 0 Correct 3 Interval timer control register ITMC Omitted Cautions 1 Before changing
29. g us prohibited aus s us Setting Setting Setting 2 prohibited prohibited Setting Setting 2 prohibited prohibited Setting us prohibited us 54 us Setti 54us 2zps 9 prohibited Setting Setting x prohibited prohibited Setting Setting nd prohibited prohibited RENESAS Date Jan 31 2012 Conversion Clock fab fc k 64 feik 32 fcLk 16 fcLk 8 fcLk 6 fcLk 5 fcLk 4 feLk 2 fcLx 64 fcux 32 fcLk 16 fcLk 8 fcLk 6 fcLk 5 fcLk 4 feLk 2 fcLk 64 fcLk 32 fc x 16 fcLk 8 fcLk 6 feLk 5 fcLk 4 fcik 2 fcux 64 fcux 32 fc x 16 fcLk 8 fcLk 6 feLk 5 fcLk 4 fcLk 2 Page 17 of 54 RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Incorrect Table 11 3 A D Conversion Time Selection 8 8 8 1 6V lt Vpp lt 1 8V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 Conversion Time Selection ADMO fcLk fcLk fcLK FR2 FR1 FRO LV1 LVO 16 MHz 4 MHz 8 MHz ile 2 Conversion Clock fab foud64 fcik 32 foud16 Normal Setting Setting fc 8 1 prohibited prohibited prohibited prohibited prohibited prohibited fc 6 ferk 5 fcuk 4 fcu 2 feu 64 feud 32 fcuk 16 Normal Setting Setting Setting fcu 8 2 prohibited prohibited prohibited prohibited prohibited prohibited fcu 6 ferk 5 fcuk 4 fcuk 2 Setti Setting 9 M08 ps fou 64 Setting i
30. g written this register ignores the overflow and is set to the value written Set a decimal value of 01 to 31 to this register in BCD code The DAY register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 01H Re Page 9 of 54 s lt E NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Incorrect description of week count register WEEK in real time clock deleted page 443 Incorrect 9 Week count register WEEK The WEEK register is an 8 bit register that takes a value of 0 to 6 decimal and indicates the count value of weekdays It counts up in synchronization with the day counter When data is written to this register it is written to a buffer and then to the counter up to 2 clocks fRrc later Set a decimal value of 00 to 06 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period The WEEK register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Correct 9 Week count register WEEK The WEEK register is an 8 bit register that takes a value of 0 to 6 decimal and indicates the count value of weekdays It counts up in synchronization with the day counter When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Set a decimal value of 00 to 06 to this registe
31. gister 2 ADM2 Omitted Caution Only rewrite the value of the ADM2 register while conversion operation is stopped which is indicated by the ADCS bit of A D converter mode register 0 ADMO being 0 Correct 4 A D converter mode register 2 ADM2 Omitted Cautions 1 Only rewrite the value of the ADM2 register while conversion operation is stopped which is indicated by the ADCS bit of A D converter mode register 0 ADMO being 0 2 When entering STOP mode or HALT mode while the CPU is operating on the subsystem clock do not set ADREFP 1 to 1 When selecting internal reference voltage ADREFP1 ADREFPO 1 0 the current value of A D converter reference voltage current laprer shown in 29 4 2 Supply current characteristics is added Re Page 22 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Note on analog input channel specification register ADS added page 497 Incorrect Figure 11 11 Format of Analog Input Channel Specification Register ADS 2 2 Address FFF31H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 Omitted Cautions 1 Be sure to clear bits 5 and 6 to 0 Omitted If using AVREFP as the side reference voltage source of the A D converter do not select ANIO as an A D conversion channel If using AVREFM as the side reference voltage source of the A D converter do not select ANI1 as an A D conversion channel If ADISS is set to 1 the internal reference voltage
32. ister MIN The MIN register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of minutes It counts up when the second counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the second count register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 00 to 59 to this register in BCD code The MIN register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Re Page 7 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Incorrect description of hour count register HOUR in real time clock deleted page 440 Incorrect 7 Hour count register HOUR The HOUR register is an 8 bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 decimal and indicates the count value of hours It counts up when the minute counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the minute count register overflows while this register is being written this register ignores the overflow and is set to the value written Specify a decimal value of 00 to 23 01 to 12 or 21 to 32 by using BCD code according to the time system specified using bit 3 AMPM of real time clock
33. lastic LQFP fine pitch 10 x 10 64 pin plastic TQFP fine pitch 7 x 7 Omitted Correct 1 3 11 64 pin products 64 pin plastic LQFP 12 x 12 64 pin plastic LQFP fine pitch 10 x 10 Omitted Package drawings of 64 pin plastic TQFP 7 x 7 deleted page 1055 Incorrect R5F100LCAFC R5F100LDAFC R5F100LEAFC R5F100LFAFC R5F100LGAFC R5F100LHAFC R5F100LJAFC R5F101LCAFC R5F101LDAFC R5F101LEAFC R5F101LFAFC R5F101LGAFC R5F101LHAFC R5F101LJAFC 64 PIN PLASTIC TQFP 7x7 Under development Correct Applicable page deleted Re Page 5 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 2 Incorrect descriptions of count registers in real time clock deleted Incorrect description of second count register SEC in real time clock deleted page 439 Incorrect 5 Second count register SEC The SEC register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of seconds It counts up when the sub count register overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks fRTC later Set a decimal value of 00 to 59 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period The SEC register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Correct 5 Second count
34. ns of A D converter characteristics 13 in Electrical specifications chapter section 29 7 1 added Condition of Temperature sensor 14 characteristics in Electrical specifications chapter section 29 7 2 added Note Arevised hardware user s manual is scheduled to be released around February 2012 N Remarks v Corrected Items should be corrected Re Page 2 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Descriptions of related information according to discontinued development of 64 pin TOFP 7 x 7 package deleted Order information of 64 pin Incorrect lastic TQFP 7 x 7 deleted page 4 Data fash Part Number Mounted Not mounted N ot mounted Not mounted 64 pin plastic LQFP 12x12 64 pin plastic LQFP fine pitch 10 x 10 64 pin plastic TOFP fine pi x Not mounted 64 pin plastic FBGA 4 x 4 Omitted R5F100LCAFA R5F100LDAFA R5F100LEAFA R5F100LFAFA RSF100LGAFA R5F100LLAFA R5F101LCAFA R5F101LGAFA RSF101LLAFA RSF100LCAFB R5SF100LGAFB RSF 100LLAFB R5F101LCAFB R5F101LGAFB R5F101LLAFB R5F100LHAFA R5F101LDAFA RSF101LHAFA RSF100LDAFB RSF100LHAFB R5F101LDAFB RSF101LHAFB RSF 100LJAFA R5F101LEAFA R5F101LJAFA R5F100LEAFB R5F100LJAFB R5F101LEAFB R5F101LJAFB R5F100LKAFA RSF101LFAFA R5F101LKAFA RSF100LFAFB R5F100LKAFB R5F101LFAFB R5F101LKAFB RSF100LCAFC RSF100LDAFC R5
35. r in BCD code The WEEK register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH zu Page 10 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Incorrect description of month count register MONTH in real time clock deleted page 444 Incorrect 10 Month count register MONTH The MONTH register is an 8 bit register that takes a value of 1 to 12 decimal and indicates the count value of months It counts up when the day counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the day count register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 01 to 12 to this register in BCD code If a value outside the range is set the register _ value returns to the normal value after 1 period The MONTH register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 01H Correct 10 Month count register MONTH The MONTH register is an 8 bit register that takes a value of 1 to 12 decimal and indicates the count value of months It counts up when the day counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the day count register overflow
36. rating current BGO operating ipgo 2 50 1220 mA current Note Omitted Correct 4 Common to RL78 G13 all products TA 40 to 85 C 1 6 V x EVbDo EVDD1 lt VpD lt 5 5 V Vss EVsso EVss1 0 V Ere m preme eee e Eme Watchdog timer fiL 15 kHz 0 22 operating E TERME A D converter lane When conversion Normal mode AVREFP VoD 5 0V mode AVREFP VoD 5 0 V operating OE maximum Low voltage mode AVREFP VDD 3 0 V icant Io NIE A D converter ADREF reference voltage current Temperature sensor operating current LVD operating T current BGO operating ipgo 35 current Note Omitted Re Page 39 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 11 Explanations when using temperature sensor and internal reference voltage 1 45 V of A D converter added Explanation of Figure 11 7 A D converter mode register 2 ADM2 added page 493 Incorrect Figure 11 7 Format of A D Converter Mode Register 2 ADM2 1 2 Address FOO10H After reset 00H R W Symbol 7 6 5 4 lt 3 gt lt 2 gt 1 lt 0 gt ADM2 ADREFP1 ADREFPO ADREFM ADRCK awc o ADTYP ADREFP1 ADREFPO Selection of the side reference voltage source of the A D converter Supplied from Vpn Supplied from P20 AVRerp ANIO Supplied from the internal reference voltage 1 45 V Setting prohibited Omitted Omitted Correct Figure 11 7 Format of A D
37. register SEC The SEC register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of seconds It counts up when the sub count register overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks fRTC later Set a decimal value of 00 to 59 to this register in BCD code The SEC register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH RE Page 6 of 54 sKENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Incorrect description of minute count register MIN in real time clock deleted Incorrect 6 Minute count register MIN The MIN register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of minutes It counts up when the second counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the second count register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 00 to 59 to this register in BCD code If a value outside the range is set the register valu returns to the normal value after 1 period The MIN register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Correct 6 Minute count reg
38. s Setting feux 2 prohibited ES Setti Seng a e etling Wei prohibited S Teas 27 us foun 32 Settin Po 94 ys 27 ys fcu 16 Low ing prohibited 54 us 27us RE 1 prohibited vaya 40 5 us foux 6 1 Settin 33 75 us Setting g fork 5 54 27 Setting hibited prohibited ili EI S rohibite o E p prohibited 54 us 27 5 Setting foux 2 prohibited i Setting z fo 64 Setting SN prohibited 9 prohibited 50 us NES prohibited Setting Setting 50 us 25us fal 16 a E rohibited Low icone 50us 25us fcud8 1 1 Voltage 2 37 5 us fcu x6 Setting 31 25 us Setting prohibited feuk 5 9 50 25 us kinh prohibited fcLk 4 H prohibited 50 us 25us Setting foux 2 prohibited Page 16 of 54 RENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Incorrect Table 11 3 A D Conversion Time Selection 7 8 7 1 8 V lt VDD lt 27 V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 ADMO FR1 Mode FR2 FRO LV1 LVO Normal 1 Normal 2 Low Voltage 1 Low Voltage 2 Note Omitted Conversion Time Selection fCLK 16 MHz Note fCLK 8 MHz fcLK 4 MHz Setting prohibited Setting prohibited prohibited prohibited prohibited prohibited Setting Setting prohibited Setting prohibited prohibited prohibited prohibited prohibited Setting Setting prohibited prohibited Settin
39. s for A D Converter added page 530 Incorrect 11 10 Cautions for A D Converter 2 Input range of ANIO to ANI14 and ANI16 to ANI26 pins Observe the rated range of the ANIO to ANI14 and ANI16 to ANI26 pins input voltage If a voltage of Voo and AVREFP or higher and Vss and AVREFM or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In addition the converted values of the other channels may also be affected When internal reference voltage 1 45 V is selected reference voltage source for the side of the A D converter do not input internal reference voltage or higher voltage to a pin selected by the ADS register However it is no problem that a pin not selected by the ADS register is inputed voltage greater than the internal reference voltage Correct 11 10 Cautions for A D Converter 2 Input range of ANIO to ANI14 and ANI16 to ANI26 pins Observe the rated range of the ANIO to ANI14 and ANI16 to ANI26 pins input voltage If a voltage of Voo and AVrerp or higher and Vss and AVREFM or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In addition the converted values of the other channels may also be affected When internal reference voltage 1 45 V is selected reference voltage source for the side of the A D converter do not input internal referen
40. s while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 01 to 12 to this register in BCD code The MONTH register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 01H Re Page 11 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Incorrect description of year count register YEAR in real time clock deleted page 444 Incorrect 11 Year count register YEAR The YEAR register is an 8 bit register that takes a value of 0 to 99 decimal and indicates the count value of years It counts up when the month count register MONTH overflows Values 00 04 08 92 and 96 indicate a leap year When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the MONTH register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 00 to 99 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period The YEAR register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Correct 11 Year count register YEAR The YEAR register is an 8 bit register that takes a value of 0 to 99 decimal and indicates the count value o
41. scale error e 1 2 Integral linearity error e Differential linearity error Note 1 Reference voltage AVREFP Analog input voltage VAIN VEGR 2 4V lt Vpp lt 5 5V HS mode Omitted Re Page 47 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Condition of 2 When AVREF AVREFP ANIO AVREF AVREFM ANI1 target ANI pin ANI16 to ANI26 added page 1033 Incorrect 2 When AVREF AVnErFP ANIO ADREFP1 0 ADREFPO 1 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANI16 to ANI26 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage AVREFP Reference voltage AVREFM Parameter Conditions Resolution Gi 10 bit resolution 1 8 V lt VpD lt 5 55V AVRerp Voo 1 6V lt Vpp lt 5 5V Overall error Conversion time Zero scale errorNotes 1 2 Full scale error es 1 2 Omitted Integral linearity errorNete 1 Differential linearity error Reference voltage AVREFP Analog input voltage VAIN 24V lt Vop lt 5 5 V Omitted Re Page 48 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Correct 2 When AVREF AVREFP ANI0 ADREFP1 0 ADREFPO 1 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANI16 to ANI26 Ta 40 to 85 C 1 6 V lt E
42. t signal The LVIMK flag is set to 1 by reset signal generation Note Page 29 of 54 RENESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 9 Incorrect description of voltage detector LVD interrupt and reset mode revised Incorrect description of when used as interrupt and reset mode revised page 897 Incorrect 21 4 3 When used as interrupt and reset mode e When starting operation Specify the operation mode the interrupt and reset LVIMDS1 LVIMDSO 1 0 and the detection voltage Vivi ViviL by using the option byte 000C1H 010C1H Omitted ution The LVIRE flag may become 1 from the beginning due to the power on waveform For details of the RESF register see CHAPTER 19 RESET FUNCTION Correct 21 4 3 When used as interrupt and reset mode e When starting operation Specify the operation mode the interrupt and reset LVIMDS1 LVIMDSO 1 0 and the detection voltage Vivi ViviL by using the option byte 000C1H 010C1H Omitted Figures 21 6 shows the timing of voltage detector reset signal and interrupt signal generation Perform the processing according to figure 21 7 Processing procedure after an interrupt is generated and figure 21 8 Initial setting of interrupt and reset mode zu Page 30 of 54 sE NESAS Date Jan 31 2012 RENESAS TECHNICAL UPDATE TN RL A001B E eneration revised c O 2 on un o i nd c c 0 7 2 b o o o End o x
43. the RINTE bit from 1 to 0 use the interrupt mask flag register to disable the INTIT interrupt servicing When the operation starts from 0 to 1 again clear the ITIF flag and then enable the interrupt servicing 2 The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit 3 When setting the RINTE bit after returned from standby mode and entering standby mode again confirm that the written value of the RINTE bit is reflected or wait that more than one clock of the count clock has elapsed after returned from standby mode Then enter standby mode 4 Only change the setting of the ITCMP11 to ITCMPO bits when RINTE 0 However it is possible to change the settings of the ITCMP11 to ITCMPO bits at the same time as when changing RINTE from 0 to 1 or 1 to 0 zu Page 13 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 4 Added Explanations of timing chart when A D voltage comparator is used page 483 Incorrect Figure 11 4 Timing Chart When A D Voltage Comparator Is Used i A D voltage comparator enables operation ADCE A D voltage comparator Conversion stopped Conversion Conversion Conversion standby operation standby Software ancs trigger mode Note t 1 is written 0 is written to ADCS to ADCS Conversion stopped Conversion Trigger Conversion Conversion standby standby operation standby Hardware trigger ADCS
44. ut 1 45 V e Other than the above Setting prohibited Notes 1 20 24 25 30 32 pin products PO1 ANI16 pin 2 20 24 25 30 32 pin products POO ANI17 pin 3 This setting value can be selected only in HS high speed main mode Re Page 41 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Explanation of 11 7 4 Setup when using temperature sensor added page 523 Incorrect 11 7 4 Setup when using temperature sensor example for software trigger mode and one shot conversion mode Figure 11 35 Setup When Using Temperature Sensor Omitted Note Depending on the settings of the ADRCK bit and ADUL ADLL register there is a possibility of no interrupt signal being generated In this case the results are not stored in the ADCR ADCRH registers Correct 11 7 4 Setup when using temperature sensor example for software trigger mode and one shot conversion mode Figure 11 35 Setup When Using Temperature Sensor Omitted Note Depending on the settings of the ADRCK bit and ADUL ADLL register there is a possibility of no interrupt signal being generated In this case the results are not stored in the ADCR ADCRH registers Caution This setting can be used only in HS high speed main mode Re Page 42 of 54 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001B E Date Jan 31 2012 Explanation of 2 Input range of ANIO to ANI14 and ANI16 to ANI26 pins in 11 10 Caution
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