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KAF-4320 Imager Board User`s Manual
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1. 1000000 jipa 100000 LAIT 10000 UT 1000 e measured MT fit 100 96 dev from fit 10 1 ft 0 1 0 01 1 10 100 1000 10000 100000 Time msec Figure 2 Measured Performance Linearity Photon Transfer 100 xT P a gt Slope el Adu 7 87 electrons Xx Md Noise floor 2 51 counts 19 8 electrons T LVSAT 487657 electrons es gt VSAT 508709 electrons 10 10000 100000 1000000 Signal Mean Electrons Figure 3 Measured Performance Dynamic Range and Noise Floor http onsemi com 6 EVBUM2253 D CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J3 6 The emitter follower buffered CCD_VOUT signals are should be used to connect the imager board to the Timing driven from the Imager Board via the SMB connectors J3 6 Generator Board to match the series and terminating Coaxial cable with a characteristic impedance of 75 Q resistors used on these boards Table 7 J2 INTERFACE CONNECTOR PIN ASSIGNMENTS Pin Signal Pin Signal x s 3 AGND 4 AGND 5 TIMING_OUT11 6 TIMING_OUT11 7 AGND 8 AGND AGND AGND TIMING_OUT4 TIMING_OUT4 37 TIMING_OUT3 38 TIMING OUT3 39 AGND 40 AGND 41 TIMING OUT2 42 TIMING OUT2 43 AGND 44 AGND 45 TIMING OUT1 46 TIMING OUT1 VMINUS MTR TIMING OUTO
2. http onsemi com 7 EVBUM2253 D Warnings and Advisories Ordering Information ON Semiconductor is not responsible for customer Please address all inquiries and purchase orders to damage to the Imager Board or Imager Board electronics The customer assumes responsibility and care must be taken Truesense Imaging Inc when probing modifying or integrating the Truesense 1964 Lake Avenue Imaging Evaluation Board Kits Rochester New York 14615 When programming the Timing Board the Imager Board Phone 6 85 784 55 00 E mail info truesenseimaging com must be disconnected from the Timing Board before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of a an Evaluation Board Kit may at their discretion make changes to the Timing Generator Board firmware ON Semiconductor can only support firmware developed by and supplied by ON Semiconductor Changes to the firmware are at the risk of the customer ON Semiconductor reserves the right to change any information contained herein without notice All information furnished by ON Semiconductor is believed to be accurate ON Semiconductor and the Q are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrigh
3. CCD high levels are controlled by the same potentiometer R80 Controlled by AMP ENABLE control line The Min and Max values shown refer to the adjustment range of the potentiometers on the Imager Board and may not be appropriate for proper device operation For proper device operation the Nominal values should be used for all clock voltages lt lt lt lt lt lt lt lt lt CON DOr http onsemi com 3 EVBUM2253 D Reset Clock Pulse Width Alternatively the One Shot can be left unpopulated and The pulsewidth of the RESET_CCD clock can be set by bypassed by a shorting resistor In this configuration the configuring the inputs to the programmable one shot pulse width of the RESET_CCD clock is set by the P 2 0 P 2 0 can be tied either high or low to achieve the programmable logic on the Timing Generator Board This is desired pulse width by populating the resistors R192 R193 the default configuration R200 and R201 accordingly Table 5 RESET CLOCK PULSE WIDTH Set by Timing Default Generator Board Configuration Multiplexed VOUT Channel Select video output leaving the Imager Board The overall system If it is desired to utilize the 4 1 multiplexer circuit on the performance may be affected when the CCD video outputs Imager Board shorting resistors R7 R8 R18 and R25 must are connected to the multiplexer circuit first be installed to connect the CCD video outputs to the Any on
4. with a potentiometer as noted The nominal values listed in Table 3 Table 3 BIAS VOLTAGES Reset Drain VRD 20 R130 Substrate SUB 1 VDD may be switched to an alternate supply during integration see Table 4 2 VSS is set from 1 to 4 diode drops above AGND by populating 1 3 bypass resistors accordingly Each resistor populated bypasses a diode Default is 1 bypass resistor populated therefore VSS is three diode drops above AGND 3 VSUB is connected directly to AGND 4 The Min and Max values shown refer to the adjustment range of the potentiometers on the Imager Board and may not be appropriate for proper device operation For proper device operation the Nominal values should be used for all bias voltages Clock Voltages Table 4 were correct at the time of this document s The following clock voltage levels are fixed or adjusted publication but may be subject to change refer to the with a potentiometer as noted The nominal values listed in KAF 4320 device specification Table 4 CLOCK VOLTAGES lt Paarl uem e ui ee HCCD Last Gate Clock Phase 1 H1L CCD BE p XE d Fo O P i ee Horizontal CCD Clock Phase 2 H2_CCD Hinc ia ped oed eo eve cus Rd Vertical CCD Clock Phase 1 V1 CCD tow 4 8 v R57 5 8 Vertical CCD Clock Phase 2 V2 CCD Low 4 8 V R57 5 8 F a O S Lo riorum mm V1 CCD and V2 CCD low levels are controlled by the same potentiometer R57 V1 CCD and V2
5. EVBUM2253 D KAF 4320 Imager Board User s Manual Description The KAF 4320 Imager Evaluation Board referred to in this document as the Imager Board is designed to be part of a two board set used in conjunction with a Timing Generator Board ON Semiconductor offers an Imager Board Timing Generator Board package that has been designed and configured to operate with the KAF 4320 Image Sensor The Timing Generator Board generates the timing signals necessary to operate the CCD and provides the power required by the Imager Board The timing signals in LVDS format and the power are provided to the Imager Board via the interface connector J2 In addition the Timing Generator Board performs the processing and digitization of the analog video output of the Imager Board The KAF 4320 Imager Board has been designed to operate the KAF 4320 with the specified performance at 3MHz pixel clocking rate and nominal operating conditions See the KAF 4320 Device Specification for details ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL For testing and characterization purposes the KAF 4320 Imager Board provides the ability to adjust many of the CCD bias voltages and CCD clock level voltages by adjusting potentiometers on the board The Imager Board provides the means to modify other device operating parameters CCD reset clock pulse width VSS bias voltage by populating components differently on the board Certai
6. ctor These signals are translated to TTL levels before being sent to the CCD clock drivers CCD Pixel Rate Clock Drivers H1 H1L H2 amp Reset Clocks The pixel rate CCD clock drivers utilize two fast switching transistors that are designed to translate TTL level input clock signals to the voltage levels required by the CCD The high level and low level of the CCD clocks are set by potentiometers Reset Clock One Shot The pulse width of the RESET CCD clock can be set by a programmable One Shot The One Shot can be configured to provide a RESET CCD clock signal with a pulse width from 5 ns to 15 ns Alternatively the One Shot can be left unpopulated and bypassed by a shorting resistor In this configuration the pulse width of the RESET CCD clock is set by the programmable logic on the Timing Generator Board This is the default configuration CCD VCLK Drivers The vertical clock VCLK drivers consist of MOSFET driver IC s These drivers are designed to translate the TTL level clock signals to the voltage levels required by the CCD The high and low voltage rails of the vertical clocks are set by potentiometers CCD Bias Voltages The bias voltages are set by potentiometers The bias voltages are de coupled at the CCD pin Alternate VDD Circuit The CCD s output amplifier can be turned off during the integration time by lowering the CCD s VDD bias voltage This is accomplished using an amplifier enabled control line sent fro
7. diaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 TS Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2253 D
8. e of the four CCD VOUT signals can be selected multiplexer inputs The multiplexer circuit presents a and driven off the Imager Board via the multiplexed output capacitive load to the video driver amplifiers of SMB connector The VOUT channel selection is controlled approximately 200 pF This capacitive load will limit the by the MUX 1 0 control line inputs from the Timing bandwidth and slow down the transitioning of the CCD Generator Board Table 6 MULTIPLEXED VOUT CHANNEL SELECTION MUXO MUX1 VOUT MUX Notes 0 0 VOUT3 Default Setting http onsemi com 4 EVBUM2253 D BLOCK DIAGRAM AND PERFORMANCE DATA VDD BIAS VOUT 3 0 ADJUSTMENT POT _ ALTERNATE VDD SWITCH VI x DRIVER a CCD SENSOR V2 CCD BIAS VOLTAGE ADJUSTMENT POTS EMITTER FOLLOWERS VOUT 3 0 RCLK DRIVER VCLKS LEVEL ADJUST POTS E DRIVER x RCLK ESHOT ADJUST POTS H2 CLK LEVEL H2 HI HIL E ADJUST POTS DRIVER DRIVER DRIVER n a HIL CLK LEVEL ADJUST POTS LVDS TO TTL BUFFERS 15V REGULATOR LVDS RECEIVERS m BERE REGULATOR BOARD INTERFACE CONNECTOR Figure 1 KAF 4320 Imager Board Block Diagram http onsemi com 5 Signal electrons pixel Noise A D counts EVBUM2253 D KAF 4320 Linearity
9. m the Timing Generator Board CCD Image Sensor This evaluation board supports the KAF 4320 Image Sensor Emitter Follower The VOUT CCD signal is buffered using a bipolar junction transistor in the emitter follower configuration This circuit also provides the necessary 5 mA current sink for the CCD output circuit Line Drivers The buffered VOUT CCD signals are AC coupled and driven from the Imager Board by operational amplifiers in a non inverting configuration The operational amplifiers are configured to have a gain of 1 25 Multiplexed VOUT Option Each of the four CCD output signals is driven from the Imager Board independently The four CCD output signals can also be input to a 4 to 1 multiplexer circuit The output of this circuit is driven off the Imager Board as well In order to utilize the multiplexer circuit four shorting resistors R7 R8 R18 and R25 must be installed on the Imager Board Two mux control lines sent from the Timing Generator Board select which of the four CCD outputs will be driven from the Imager Board via the output of the multiplexer circuit http onsemi com 2 EVBUM2253 D OPERATIONAL SETTINGS The Imager board is configured to operate the KAF 4320 were correct at the time of this document s publication but under the following operating conditions may be subject to change refer to the KAF 4320 device specification Bias Voltages The following voltages are fixed or adjusted
10. n features of the Imager Board circuitry are provided for Truesense Imaging use only and are not supported for customer use These circuits may not be populated on the Imager Board IMAGER BOARD INPUT REQUIREMENTS Table 1 POWER REQUIREMENTS Power Supplies Kod eee D cr ee 1 VMINUS Supply 21 20 Ue j LLL Table 2 SIGNAL LEVEL REQUIREMENTS Vthreshold 18 wes Us Gomes 2 4 TIMING OUT2 0 1 2 4 H2 clock TIMING_OUTS 0 1 2 4 H2 clock TIMING_OUT4 0 1 2 4 Not Used ana ou s 9 9 r 2 v emas TIMING OUT6 0 0 1 2 4 V V1 clock Semiconductor Components Industries LLC 2014 August 2014 Rev 2 Publication Order Number EVBUM2253 D EVBUM2253 D Table 2 SIGNAL LEVEL REQUIREMENTS TIMING_OUT7 TIMING_OUT9 TIMING_OUT10 TIMING_OUT11 ARCHITECTURE OVERVIEW The following sections describe the functional blocks of the KAF 4320 Imager Board refer to Figure 1 Power Filtering and Regulation Power is supplied to the Imager Board via the J2 board interface connector The power supplies are de coupled and filtered with ferrite beads and capacitors to suppress noise Voltage regulators are used to create the 15 V 15 V and CCD VDD supplies from the VPLUS and VMINUS power supplies input to the Imager Board LVDS Receivers TTL Buffers LVDS timing signals are input to the Imager Board via the J2 interface conne
11. ts trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and Specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsi
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