56F8300 Digital Power Factor Correction using Processor Expert
Contents
1. e Input voltage value 230V and 50Hz The applications run at 230V 50Hz by default To switch to 115V 60Hz comment this line in Digital_PFC c define MILESTONE OFFSET MKS TO TICK 570L For 50 Hz 230 V And uncomment this line define MILESTONE OFFSET MKS TO TICK 1498L For 60 Hz 115 V The Digital PFC application may be used in the Manual Operating Mode The remote control functionality of the PC master software application is not implemented The application can run on e External RAM Flash 1 1 Manual Operating Mode The PFC conversion is controlled by the RUN STOP switch S3 see Figure 1 1 The green USER LED LED2 see Figure 1 2 indicates the application states When the application is ready the USER LED blinks at a 2Hz frequency 56F8300 Digital Power Factor Correction Rev 1 Freescale Semiconductor 3 Preliminary SEE V LIMIT Milea oe Gi R3 E ORE ie al Lisa isi RUN STOP Figure 1 1 RUN STOP Switch on the Daughter Card PFC_PHN wil nei i na tld PFC_2ERO_CROSE oer gen LED MOO PWNA OP LED DEC ENABLE 140708 F802 BRAKE al n ate US _ THRE P Juni DEDA ee G Tai t So p a ae at Figure 1 2 USER LED on the Daughter Card The PFC conversion can be enabled after the RUN STOP switch is moved to the RUN position The normal PFC conversion process is indicated by the green USER LED which will light continuously2. Evaluation Module Hardware User s Manual or 56F8367 Evaluation Module Hardware User s Manual 3 Phase AC BLDC High Voltage Power Stage 180W Supplied in a kit with optoisolation board as ECOPTHIVACBLDC Described in 3 Phase Brushless DC High Voltage Power Stage Optoisolation Board Supplied with 3 Phase AC BLDC High Voltage Power Stage as ECOPTHIVACBLDC or Supplied alone as ECOPT optoisolation board Described in Optoisolation Board User s Manual It is strongly recommended that optoisolation optocouplers and optoisolation amplifiers be used during development to avoid damage to the development equipment Documentation for all components can be found at http freescale com 56F8300 Digital Power Factor Correction Rev 1 Freescale Semiconductor 7 Preliminary PFC Jumper PFC Figure 2 2 Jumper JP201 on the 3 Phase AC BLDC Power Stage For detailed information see the 56F8346 Evaluation Module Hardware User s Manual 56F8357 Evaluation Module Hardware User s Manual or 56F8367 Evaluation Module Hardware User s Manual The serial cable is needed for the PC master software debugging tool only 2 1 EVM Jumper Settings To execute the Digital PFC application the daughter card requires the strap settings shown in Figure 2 3 and Table 2 1 JGI0 JG JG12 EI CI Figure 2 3 56F8300EVM Daughter Card Jumper Reference 56F8300 Digital Power Factor Correction Rev 1 8 Freescale Sem
3. To disable PFC conversion the RUN STOP switch must be moved to the STOP position 56F8300 Digital Power Factor Correction Rev 1 4 Freescale Semiconductor Preliminary PC Master Software Remote Operating Mode Table 1 1 Motor Application States Application State Digital PFC State LED State Stopped Stopped Green LED blinking Red LED off Running Spinning Green LED on Red LED off Fault Stopped Green LED off Red LED on 1 2 PC Master Software Remote Operating Mode The drive is monitored remotely from a PC through the SCI communication channel of the device via an RS 232 physical interface PC master software displays the following information e Application mode e Application status e DCBus Voltage Application Mode Project files for the PC master software are located in pcmaster sdm_external_memory pmp uses Map file to run in the small memory model of the external memory pcmaster ldm_external_memory pmp uses Map file to run in the large memory model of the external memory pcmaster sdm_pROM xRAM pmp uses Map file to run in the small memory model of the internal memory pcmaster ldm_pROM xRAM pmp uses Map file to run in the large memory model of the internal memory pcmaster sdm_xROM xRAM pmp uses Map file to run in the small memory model of the internal memory pcmaster ldm_xROM xRAM pmp uses Map file to run in the large memory model of the internal memory S
4. Digital Power Factor Correction Rev 1 12 Freescale Semiconductor Preliminary EVM Jumper Settings 5 Execute To execute the Digital PFC Application select the Project Debug command in the CodeWarrior IDE followed by the Run command For more help with these commands refer to the CodeWarrior tutorial documentation in the following file located in the CodeWarrior installation directory lt gt CodeWarrior Manuals PDF Targeting_56800E pdf If the Flash target is selected CodeWarrior will automatically program the device s internal Flash with the executable generated during Build If the External RAM target is selected the executable will be loaded to off chip RAM Once Flash has been programmed with the executable the EVM target system may be run ina stand alone mode from Flash To do this set the JG9 jumper on the 8346EVM and JG3 on the 56F8357EVM or 56F8367EVM in the 1 2 configuration to disable the parallel port and press the RESET button To enable the PFC conversion set the RUN STOP switch to the RUN position If this switch was in the RUN position before the application started move it to the STOP position first then back to the RUN position The USER LED should light continuously when the PFC conversion is enabled To disable the PFC conversion move the RUN STOP switch to the STOP position causing the USER LED to blink again 56F8300 Digital Power Factor Correction Rev 1 Freescale Semiconductor 13 P
5. Search Project Debug ProcessorE EEA CETAN EE Digital _PFC mcp sdm external memory im Y A E sdm external memory Idm external memory sdm pROM xRAM Idm pROM xRAM sdm ROM xRAM Idm xROM xRAM _ 2 ldm pROM xRAM tt rm ROM RAM Figure 3 1 Target Build Selection 56F8300 Digital Power Factor Correction Rev 1 10 Freescale Semiconductor Preliminary I EVM Jumper Settings The project may now be built by executing the Make command as shown in Figure 3 2 This will build and link the Digital PFC Application and all needed Metrowerks and Processor Expert libraries Metrowerks CodeWarrior File Edit View Search Project Debug Processor Expert Window Help Add Gpu G to Project dono Add Files Greate Group Digital _PFC mcp Greate Target Create Segment Overlay sdm external memor Create Design Files Link Order Tar Export Project as GNU Makefile Check Syntax Ctrl aS Configurations Preprocess 4 amp SERE Precompile x Qe Idmextemaln Compile Ctrl F x 2 sdmpROM xF Disassemble Gtrl Shift F7 x x 4 Idm pROM 4F e U WW e o x sdm xROM xF Bring Up To Date Ctrl U 2 Idm ROM mo Stan Rui GrrltRrealk Figure 3 2 Execute Make Command For more information about these commands see lt gt CodeWarrior Manuals PDF Targeting_56800E pdf 56F8300 Digital Power Factor Correction Rev 1 Freescale Semiconductor 11 Preliminar
6. 56F 8300 Digital Power Factor Correction using Processor Expert Targeting Document 56F8300 16 bit Digital Signal Controllers 331010 D nd z103 J D Rev 1 013722201015 e freescale com lt 2 freescale semiconductor Document Revision History Version History Description of Change Rev 0 Initial release Rev 1 Updating format adding reference to 56F8100 family and 56F8367EVM 56F8300 Digital Power Factor Correction Rev 1 Freescale Semiconductor Preliminary Manual Operating Mode Digital Power Factor Correction This application exercises simple control of the Power Factor Correction PFC without motor control on the 56F8346 56F8357 or 56F8367 EVM board and the EVM Motor Kit Applications developed for this demonstration board were not designed for the 56F8100 devices The 56F8300 demonstration board does however fully support 56F8100 software development 1 Specifications The Digital PFC application performs power factor correction for 3 Phase AC BLDC High Voltage Power Stage hardware without motor drive This demonstration evaluates the basic algorithm of power factor correction for the current hardware implementation PFC software was designed for use with motor control applications the Digital PFC application allows target memory configuration of RAM and Flash The input power line must meet the following requirements e Input voltage value 115V and 60Hz
7. enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product cou
8. iconductor Preliminary EVM Jumper Settings Table 2 1 56F8300EVM Daughter Card Jumper Settings Jumper Group Comment Connections JG1 Primary PFC 1 2 3 4 5 6 7 8 9 10 JG2 Secondary PFC NC JG3 Phase_IS Over_ 1 2 JG4 Primary Zero Crossing Encoder 2 3 5 6 8 9 JG5 Secondary Zero Crossing Encoder NC JG6 Primary Back EMF Phase IS 1 2 4 5 7 8 JG7 Secondary Back EMF Phase lS NC JG8 Fault A Monitor 1 2 3 4 5 6 JG9 Fault B Monitor 1 2 3 4 5 6 JG10 Switch 1 1 2 JG11 Switch 2 1 2 JG12 Switch 3 Run Stop 1 2 Note When running the EVM target system in a stand alone mode from Flash in the 56F8346EVM the JG9 jumper must be set in the 1 2 configuration to disable the command converter parallel port interface In the 56F8357EVM or 56F8367EVM the JG3 jumper must be set in the 1 2 configuration to disable the command converter parallel port interface 56F8300 Digital Power Factor Correction Rev 1 Freescale Semiconductor Preliminary 3 Build When building the Digital PFC Application the user can create an application that runs from internal Flash or External RAM To select the type of application to build open the digital PFC mcp project and choose the target build type see Figure 3 1 A definition of the projects associated with these target build types may be viewed under the Targets tab of the project window Metrowerks CodeWarrior File Edit view
9. ld create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part PI o 2 freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved 8300DPFCTD Rev 1 08 2005
10. reliminary 56F8300 Digital Power Factor Correction Rev 1 14 Freescale Semiconductor Preliminary EVM Jumper Settings 56F8300 Digital Power Factor Correction Rev 1 Freescale Semiconductor 15 Preliminary How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to
11. tart the PC master software window s application sdm_external_memory pmp Figure 1 3 illustrates the PC master software control window after this project has been launched 56F8300 Digital Power Factor Correction Rev 1 Freescale Semiconductor 5 Preliminary freni external_memory pmp PCMaster Ol x File Edit View Explorer Item Project Help bo E fe PI Ti ale fn SS Digital Power Factor Correction Name Unit ApplicationMode ENUM 1000 ApplicationStatus ENUM 1000 u_dc_bus 317 Y 250 Dore Neme e y Figure 1 3 PC Master Software Control Window 2 Hardware Set up Figure 2 1 illustrates the hardware set up for the Digital PFC application which requires a motor drive The 3 Phase AC BLDC High Voltage Power Stage board contains the JP201 jumper that selects the power supply device Pins 2 and 3 of the JP201 connection correspond to a simple rectifier capacitor power stage The PFC hardware set up requires closing pins 1 and 2 of the JP201 connection see Figure 2 2 56F8300 Digital Power Factor Correction Rev 1 6 Freescale Semiconductor Preliminary PC Master Software Remote Operating Mode Figure 2 1 Digital PFC Application Set up The system is comprised of the following components Warning Note Controller board for 56F8346 56F8357 or 56F8367 Supplied as 56F8346EVM 56F8357EVM or 56F8367EVM board Described in 56F8346 Evaluation Module Hardware User s Manual 56F8357
12. y 4 Projects Files The Digital PFC application is composed of the following files Project Directory Project File Name mcp application project file Project Directory Project File Name pe Processor Expert software file Project Directory Project File Name G_C Processor Expert software file Project Directory Project File Name dsk Processor Expert software file Project Directory bin xMAP map file Project Directory bin elf standard binary file Project Directory startup c h asm initialization files _ Project Directory Code adcPrimary files generated by the PE for adcPrimary bean Project Directory Code PC_M1 files generated by the PE for PC_M1 bean Project Directory Code tiAux files generated by the PE for tiAux bean Project Directory Code tmrD1 files generated by the PE for tmrD2 bean Project Directory Code Cpu files generated by the PE for the CPU used Project Directory Code Events files generated by the PE for events Project Directory Code PE_Const PE internal definitions of the constants Project Directory Code PE_Error PE internal definitions of the error constants Project Directory Code PE_Types PE internal definitions of the types Project Directory Code PESL configuration file for PESL library Project Directory Code Vectors definitions of the interrupt vectors 56F8300
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