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PCM Codec Connection to TC1130

1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 1 r 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 8 2 1 0 T T T T T SLS T T T T 0 07 0 INACT TRAIL LEAD 1 MOD L 1 1 1 r rw r rw rw rw Field Bits Typ Description LEAD 1 0 rw Slave Output Select Leading Delay 00 No Delay TRAIL 3 2 rw Slave Output Select Trailing Delay 00 No Delay INACT 5 4 rw Slave Output Select Inactive Delay 00 No Delay SLSO7MOD 8 rw SLSO7 Delayed Mode Selection 0 Normal Mode selected for SLSO7 0 7 6 r Reserved read as 0 should be written with 0 31 9 Application Note 65 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 SSCO PISEL SSCO Port Input Select Register 31 30 29 28 27 26 25 SVV Description Value 0000 0000H Reset value 0000 0000y 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 sTIP 0 SLSIS__ scis sris MEI r rw r rw rw rw rw Field Bits Typ Description MRIS 0 rw Master Mode Receive Input Select 0 MSRTA Selected SRIS 1 r Slave Mode Receive Input Select 0 MTSRA Selected SCIS 2 rw Slave Mode Clock Input Select 0 SCLKA Selected SLSIS 5 3 rw Slave Mode Select Input Selection 000 No Input Line Selected STIP 8 rw Slave Transmit Idle State Polarity 0 Not used in Master Mode 0 7 6 r Reserved read as 0 should be written with 0 31 9
2. Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description DMA_SADR03 IValue 2227722224 DMA Channel 03 Source Address Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SADR 1 1 TWR 1 1 1 L 1 Field Bits Typ Description SADR 31 0 rwh Source Start Address 0x Address set to Control_Slots address DMA DADRO3 Value FO10 0118H DMA Channel 03 Destination Address Register Reset value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DADR 1 1 mh 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Application Note 85 V 1 0 2005 01 _ Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description Field Bits Typ Description DADR 31 0 w Destination Start Address 0xF0100118 Address set to SSCO Slave Select Control Output SSOC DMA ADRCRO3 Value 0000 0708H DMA Channel 03 Address Control Register Reset value 0000 00004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SHCT pe o a rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBLD CBLS INCD DMF INCS SMF rw rw rw rw rw i rw Field Bits Typ Description SMF 2 0 rw Source Modification Factor 000 The Update Factor is 1 word 32 bits INCS 3 r Increment of
3. Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Infin n AP32072 Infineon PCM Codec Connection to TC1130 1 Abstract qd d Se k ph a e 4 2 Introduction sasi Gra ran n ao LEA 5 2 1 PCM Stream ic e e a e ibd abe 6 2 2 SSC Features aa de nara a 8 2 3 The Clock Generation aaa 9 3 HW Description aa anen 12 3 1 General ricota e Bi 4 12 3 2 Connection Example aaa 13 4 SW Description aaa anash 15 4 1 SW Architecture corr A d KiS 15 4 1 1 Clock Generation aaa 15 41 2 Data Output ce nn avi e E e a GA dre
4. Note MLIO on TC 1130 has only one pair of pins Therefore selecting port A or port B has no influence Application Note 66 V 1 0 2005 01 Infineon technologies P1_ALTSELO Port1 Alternate Select Register 0 AP32072 PCM Codec Connection to TC1130 SW Description Value 0000 0000H Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 1 r 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Typ Description Pn n rw Port 1 Pin n Alternate Output Selection 0 Normal GPIO or Alternate Select 2 see next table for P1_ALTSEL1 0 31 16 r Reserved read as 0 should be written with O Application Note 67 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description P1_ALTSEL1 Value 0000 2800y Port1 Alternate Select Register 1 Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Typ Description Pn n rw Port 1 Pin n Alternate
5. 2005 01 Chi n AP32072 ALH PCM Codec Connection to TC1130 SW Description In Link Rules Change the name of the ouput file to Project elf Set Build directory to Include Link Script target ld El Source Files Library Files Build Rules I Link Rules Build Directory Output File Loopback est elf Entry Point Target Type Executable 54 Linker tricore gcc El Link las o Tool Chain Link script target ld HighTec TriCore PAROS y tricore gcc o debug DMA o MAIN o SSCO a Debug Execute Settings Command to launch Application Debug C Execute Fdebug Figure 34 Source Navigator Build Settings Link Rules Application Note 48 V 1 0 2005 01 _ Infineon AES2D7A technologies PCM Codec Connection to TC1130 SW Description Adding Code to the Project Close all windows except the Symbols window Double click on MAIN c file Add the Slots arrays as global variables you can include it just before the main function and add a variable named i in the main function USER CODE BEGIN Main 1 unsigned int Transmit_Slots 32 __attribute__ section data2 unsigned int Control_Slots 32 __attribute__ section data2 unsigned int Receive_Slots 32 attribute__ section data2 USER CODE END svord main void sword swReturn USER CODE BEGIN Main 2 unsigned int i USER CODE END Applicatio
6. Commonly compilers provide a way to align data variables but this is often limited to 32 bytes boundaries To be able to align it to 128 bytes boundary it is needed to locate the Slots arrays in specific user defined sections In this example an extra memory segment is defined to locate the Slots arrays Once the peripherals are configured you need to initialize the Slots arrays The most important one is the Control_Slots array Please refer to previous diagrams for examples on how to initialize the array Nothing else needs to be added except your own specific handling code in the DMA service request node 0 For demo purposes you can easily create a loopback using these lines in the request node Transmit_Slots 0 Transmit_Slots 1 Receive_Slots 1 Receive_Slots 2 4 2 2 Implementation using Dave Everything needed to support PCM codec is available directly with Dave Very few lines of code need to be added by yourself to make it work Here a step by step approach is shown Note Here the GNU Toolchain and the Red Hat Source Navigator developing environment is used Configuring Project Settings In General Tab Set Compiler to GNU Settings Application Note 23 V 1 0 2005 01 e Infineon ir technologies PCM Codec Connection to TC1130 SW Description Y Project Settings Figure 11 Project Settings General Tab Application Note 24 V 1 0 2005 01 e Infineon techno
7. P9 P8 P7 P6 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Typ Description Pn n rw Port 2 Pin n Alternate Output Selection 1 Alternate Select 1 0 31 16 r Reserved read as 0 should be written with O P2 4 and P2 3 are selected as output for SCLKO and MTSRO Application Note 70 V 1 0 2005 01 Infineon technologies P2_ALTSEL1 AP32072 PCM Codec Connection to TC1130 SW Description Value 0000 0000 Port2 Alternate Select Register 1 Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Typ Description Pn n rw Port 2 Pin n Alternate Output Selection 0 Normal GPIO or Alternate Select 1 see previous table for P2_ALTSELO 0 31 16 r Reserved read as 0 should be written with 0 Application Note 71 V 1 0 2005 01 _ Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description P2_DIR IValue 0000 0000y Port2 Direction Register Reset value 0000 0018y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5
8. Setup DMA Channel 00 ROO Source is 128 bytes circular buffer DMA_CHCR 0xF0003CA4 0x00000000 0x00506020 Setup DMA Channel 01 01 for 32 bits 1 Move Triggered by SSCO_1 RIR DMA CHIC OxFO003CA8 0x00000000 0x00000000 DMA Channel 01 doesn t RO1 generate any interrupt DMA SADR OxFOOO3CBO 0x00000000 0xF0100124 Setup DMA Channel 01 01 Source Address to SSCO Receive Buffer Register DMA DADR 0xF0003CB4 0x00000000 0x Setup DMA Channel 01 01 Destination Address to Receive_Slots array Application Note 56 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 SW Description Table 1 Register Overview Register Address Mask Value Comment DMA_ADRC OxFO003CAC 0x00000000 0x00007080 Setup DMA Channel 01 RO1 Destination is 128 bytes circular buffer DMA CHCR 0xF0003CE4 0x00000000 0x00508020 Setup DMA Channel 03 03 for 32 bits 1 Move Triggered by SSCO 0 TIR DMA CHIC 0xF0003CE8 0x00000000 0x00000000 DMA Channel 03 doesn t RO3 generate any interrupt DMA SADR OxFOOO3CFO 0x00000000 0x Setup DMA Channel 03 03 Source Address to Control_Slots array DMA_DADR 0xF0003CF4 0x00000000 0xF0100118 Setup DMA Channel 03 03 Destination Address to SSCO Slave Select Control Output Register DMA_ADRC OxFOOO3CEC 0x00000000 0x00000708 Setup DMA Channel 03 RO3 Source is 128 bytes circular buffer D
9. this is SSCO 0 signal please refer to System User s Manual chapter 17 3 1 1 for more details Configure DMA Channel 00 xl DMA Control for Channel 00 Interrupt Control r Channel 00 Data width CHDw r Transfer Reload Value C 8 bit byte transfer IV Enable Channel 00 16 bit half word transfer TREL 0x020 t 32 bit word transfer r Peripheral Request Control PRSEL r Source Start Address v Enable Hardware Transaction SADROO 000000000 PRSEL Multiplexer Input 2 Selected x r Destination Start Address DADROO 0x00000000 r Operation Mode CHMODE Single mode operation Continuous operation r Pattern Select PATSEL Disabled y Figure 22 DMA Block 0 Tab DMA Channel 00 General Tab Application Note 35 V 1 0 2005 01 infi AP32072 Infineon PCM Codec Connection to TC1130 SW Description Configure Source Buffer to 128 bytes Circular Buffer Set Increment Source Buffer Address 5 Configure DMA Channel 00 n Circular Buffer is of 128 Bytes i No of Moves is 1 7 l The Address is not Modified Y The Update Factors 1 The Update Factor is 1 mi Figure 23 DMA Block 0 Tab DMA Channel 00 Control Tab Application Note 36 V 1 0 2005 01 AP32072 PCM Codec Connection to TC1130 technologies SVV Description Enable Transfer Interrupt vvhen TCOUNT r
10. 2 048 MHz clock The data output rate is then 8 kHz which is the audio quality Internally the codec uses this clock and divides it by 256 2048 256 8 Application Note 16 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description The data has to be written to the codec with an 8 kHz rate Using the DMA data is written every 2048 8 256 kHz assuming 8 bits data Therefore the interesting data has to be written every 32 words The DMA source is configured to be a 32 words circular buffer The data to be transmitted to the codec is chosen for example to be located at index O for the left channel and at index 1 for the right channel The DMA channel 0 is setup to generate an interrupt when it reaches position 15 This interrupt is used by the higher level software i e the device driver to update the data for next sample In this interrupt the input sample is also read this vvill be described later on index 0 1 2 3 x 28 29 30 31 Data Data A Left Right 0 0 0 0 0 0 Transmit Slots 32 words 32 bits wide circular buffer A a ee Tal GLK y LNLNLLLNLNLLL SL JUL gt Trigger Ch 10 Ti it Buff i MTSR 4 Pose gt Souda annel Dest gt Transmit Buffer gt Trairi H p gt p r Y Roh aX re SHK Regal a 0 1 14 15 16 34 0 1 Interrupt to CPU DMA SSC Figure 7 Constant 8
11. Bits Typ Description TREL 8 0 rw Transfer Reload Value 0x20 32 Words Tranfer PRSEL 15 13 rw Module Disable Status Bit 011 Multiplexer Input 3 selected SSCO_1 RIR BLKM 18 16 rw Block Mode 000 1 Move RROAT 19 rw Reset Request Only After Transfer 0 Each Transfer needs a trigger CHMODE 20 rw Channel Operation Mode 1 Continuous Mode Operation CHDW 22 21 rw Channel Data Width 10 32 bits words PATSEL 25 24 rw Pattern Select 00 No Pattern Detection CHPRIO 28 rw Channel Priority 0 Low Priority DMAPRIO 30 rw DMA Priority 0 Low Priority Application Note 79 V 1 0 2005 01 _ AP32072 n Infineon PCM Codec Connection to TC1130 SW Description Field Bits Typ Description 0 12 9 r Reserved read as 0 should be written with O 23 27 26 29 31 DMA_CHICRO1 Value 0000 0000y DMA Channel 01 Interrupt Control Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRP WRP IRDV INTP WRPP INTCT DE SE rw rw Wo rw w rw Field Bits Typ Description WRPSE 0 rw Wrap Source Enable 0 Wrap Source Interrupt Disabled WRPDE 1 rw Wrap Destination Enable 0 Wrap Destination Interrupt Disabled INTCT 3 2 rw Interrupt Control 00 No Interrupt is Generated WRPP 7 4 rw Wrap Pointer 0x0 Not Used INTP 11 8 rw Interr
12. P4 P3 P2 P1 PO rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Typ Description Pn n rw Port 2 Pin n Direction Control 0 Input 1 Output 0 31 16 r Reserved read as 0 should be written with 0 Here P2 4 and P2 3 are used for SCLKO and MTSRO pins so they need to be setup as output Application Note 72 V 1 0 2005 01 _ Infineon technologies AP32072 PCM Codec Connection to TC1130 4 2 6 DMA Registers DMA_CLC DMA Clock Control Register 31 30 29 28 27 26 SW Description Value 0000 0000 Reset value 0000 0000y 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FS SB SP OE WE 9 EN DISS DISR rw w rw rw r rw Field Bits Typ Description DISR 0 rw Module Disable Request Bit 0 Module Enabled DISS 1 r Module Disable Status Bit SPEN 2 rw Module Suspend Enable for OCDS 0 OCDS Module Enabled 0 3 rw Reserved returns O if read must be written with O SBWE 4 w Module Suspend Bit Write Enable for OCDS 0 OCDS Module related register unprotected FSOE 5 rw Fast Switch Off Enable 0 Fast Clock Switch Off disabled 0 31 6 r Reserved read as 0 should be written with 0 3 Application Note 73 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130
13. TC1130 technologies SVV Description Configuring SSCO In Module Clock Tab Enable the SSC Module and select normal clock divider the module clock should be by default fsys clock 73 728 MHz FI je ota 2 Module Clock Pin Selection Slave Select Pins Slave Select Control FIFO Baud Rate Interrupts Functi lt gt m Module Disable Request r Sleep Mode Enable Control J Disable the SSCO module DIS ima 2 ao r Divider Mode Control DH r Disable Clock Control m Output clock becomes inactive after initialization IDISCLK Disable module clock r Enable Hardware Clock Control i i Bit DISCLK is reset by Hw while input signal SE senate T ECEN CAN_INT_O15 is a high level ENHW Module Clock Control Required module clock MHz 73 728 Real module clock MHz 73728 Minimal module clock KHz 72 000 Percentage of deviation cca Maximal module clock MHz 73 728 Step value STEP ox3FF Figure 14 SSCO0 Module Clock Tab Application Note 27 V 1 0 2005 01 e AP32072 Infineon 5 PCM Codec Connection to TC1130 SW Description In Pin Selection Tab Select Master Mode Enable MRSTO SCLKO and MTSRO pins B High Speed Synchronous Serial Interface SSCO t No slave receive impu Slave put MTSFO PZZ selected f No slave clock inpul f Slave clock input SCLKO P24 f Mo slave trar
14. The PCM main timing diagram In this example the data to and from the codec is sampled on the falling edge of the master clock in the system MCLK There are two independent channels with separate frame sync signals FS1 respectively FS2 Application Note 7 V 1 0 2005 01 Infineon APARTA technologies PCM Codec Connection to TC1130 Introduction The codec is reading and also outputting each sample in the same manner on the PCM bus that is during the assertion of the long frame sync signal It is up the host processor to put and retrieve the samples to from the PCM bus during this interval The main frequency of the PCM bus can also vary but it will always be in an integer ratio with the 8kHz sampling rate the codec usually is extracting his internal timing for all operations from this master clock As a practical example the connection between the TC1130 and the MC145481 codec will be presented 32 slots 125us 8kHz M ns 2 048 MHz ek PULL st ooa K J Lo S2 30 slots x 3 9 us J Figure 3 Typical stereo 2 channels PCM connection S3 2 2 SSC Features The SSC of the TC1130 has the following features that make it appropriate to communicate to an external CODEC in SPI modus Eight Chip Select Outputs 2 to 16 bits programmable message length Transfer starts with MSB or LSB first shifting out on the rising or falling edge back to back transmit capability
15. ese 16 4 1 3 Chip Select Generation aaa 17 41 4 Input Handling na sowa edu aa E e ea ois 19 4 2 SW Implementation aaa 21 4 2 1 Configuration aa 21 4 2 2 Implementation using Dave aaa aaa 23 4 2 3 Results and Measurement 0 00 c cee ee eee 52 4 2 4 Register Summary auaaaaaaa anawa aaa eee ee 54 4 2 5 SS Registers adi ae an la beak peas A 58 4 2 6 DMA Registers cica sc ai bee eee ee do a nae eee ee 73 Application Note 3 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 Abstract 1 Abstract This paper describes a possible connection between an external audio PCM codec and the Serial Synchronous Channel SPI type interface of the TC1130 This type of connection is required for all the audio applications which uses a codec and also for applications where a PCM channel is used for example a Bluetooth connection The connection described here is using no external components and is intended for a cost minimization on the overall system level Application Note 4 V 1 0 2005 01 _ Infineon APARTA technologies PCM Codec Connection to TC1130 Introduction 2 Introduction For applications requiring audio streams the PCM Pulse Code Modulation channel is a handy and cheap alternative to transport digital audio data Initially invented by A H Reeves in 1937 Pulse Code Modulation PCM was developed in the seventies and is
16. kHz data throughput On this picture you can see the 32 words circular buffer This buffer uses 32 bits wide words as the SSC transmit buffer is a 32 bits register Only the 8 LSB bits are relevant in this case 4 1 3 Chip Select Generation Using the configuration above we see that the data is sent out every 8 kHz We need now a way to tell the PCM Codec that the data during this time is relevant and for 30 32 of the time irrelevant This is done using Chip Select or Frame Start on the Codec The TC1130 SSC has the possibility to generate Slave Select Outputs You can have a maximum of 8 per SSC The outputs are controlled with a specific register which is buffered the same way as the Transmit buffer This means that if you write something to this register the Slave Select Outputs will be modified on the next start of transmission Therefore you can really set those pins when you want them to be This is further detailed in the Peripheral User s Manual chapter 3 1 2 11 Application Note 17 V 1 0 2005 01 _ Infineon AFe2072 technologies PCM Codec Connection to TC1130 SW Description So to say to the Codec that the information is relevant for slots 0 and 1 we need to set the Slave Select Output register for those periods We can use for this another DMA Channel which has this register as destination The source of this channel is just using the same structure with a 32 words circular buffer Note Depending on your co
17. to 2 048 MBauds SCLK MRST MTSR pins enabled selected SLSO pins enabled for SSC operation here SLSO1 and SLSO2 SLSO pins configured for high level active depends on codec SLSO timing set to no additional delay Application Note 21 V 1 0 2005 01 _ Infineon AEO technologies PCM Codec Connection to TC1130 SW Description The DMA needs to be configured as follow Service Request node 0 enabled SSCO EBU and external EBU space Address Ranges enabled Channel 0 enabled and set to 32 bits wide transfer Transfer reload set to 32 0x20 Number of Moves set to 1 Source address set to Transmit_Slots array Source buffer is 128 bytes circular update factor of 1 increment Destination address set to SSC Transmit Buffer SSCO_TB Destination buffer without any address modification Hardware Transaction enabled and set to SSC0_0 signal which is connected to TIR see SCU configuration Continuous Operation selected Transfer Interrupt enabled and generated when TCOUNT reaches 15 Transfer Count Threshold Limit IRDV Channel 3 enabled and set to 32 bits wide transfer Transfer reload set to 32 0x20 Number of Moves set to 1 Source address set to Control_Slots array Source buffer is 128 bytes circular update factor of 1 increment Destination address set to SSC Transmit Buffer SSCO_SSOC Destination buffer without any address modification Hardware Transaction enabled and s
18. 00 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SHCT 1 r di 1 1 if 1 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBLD CBLS INCD DMF INCS SMF rw rw rw rw rw i rw Field Bits Typ Description SMF 2 0 rw Source Modification Factor 000 The Update Factor is 1 word 32 bits INCS 3 r Increment of Source Address 1 The Source Address will be Incremented DMF 6 4 rw Destination Modification Factor 000 Destination Address is not modified cf CBLD INCD 7 rw Increment of Destination Address 0 Destination Address is not modified cf CBLD CBLS 11 8 rw Circular Buffer Length Source Ox7 Buffer is 128 bytes long CBLD 15 12 rw Circular Buffer Length Source 0x0 The Destination Address is not modified SHCT 17 16 rw Shadow Control 00 Shadow Register is not used 0 31 18 r Reserved read as 0 should be written with O Application Note 78 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 DMA CHCRO1 DMA Channel 01 Control Register SW Description Value 0050 6020H Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T T T CH T T DMA CHP RRO 0 PRIO 0 RIO 0 PATSEL 0 CHDW MO AT BLKM r rw r rw r rw r rw rw rw rw i 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRSEL 0 TREL L w L r 1 L 1 L W 1 1 L Field
19. 00 1 Move RROAT 19 rw Reset Request Only After Transfer 0 Each Transfer needs a trigger CHMODE 20 rw Channel Operation Mode 1 Continuous Mode Operation CHDW 22 21 rw Channel Data Width 10 32 bits words PATSEL 25 24 rw Pattern Select 00 No Pattern Detection CHPRIO 28 rw Channel Priority 0 Low Priority DMAPRIO 30 rw DMA Priority 0 Low Priority Application Note 83 V 1 0 2005 01 _ AP32072 n Infineon PCM Codec Connection to TC1130 SW Description Field Bits Typ Description 0 12 9 r Reserved read as 0 should be written with O 23 27 26 29 31 DMA_CHICRO3 Value 0000 0000y DMA Channel 03 Interrupt Control Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRP WRP IRDV INTP WRPP INTCT DE SE rw rw Wo rw w rw Field Bits Typ Description WRPSE 0 rw Wrap Source Enable 0 Wrap Source Interrupt Disabled WRPDE 1 rw Wrap Destination Enable 0 Wrap Destination Interrupt Disabled INTCT 3 2 rw Interrupt Control 00 No Interrupt is Generated WRPP 7 4 rw Wrap Pointer 0x0 Not Used INTP 11 8 rw Interrupt Pointer 0x0 Not Used IRDV 15 12 rw Interrupt Raise Detect Value 0x0 Not Used 0 31 16 r Reserved read as 0 should be written with 0 Application Note 84 V 1 0 2005 01 _
20. 6 5 4 3 2 1 0 BR_VALUE 1 L AN 1 1 1 L 1 Field Bits Typ Description BR VALUE 0 rw Baud Rate Timer Reload Register Value 0x0011 Baudrate set to 2 048 MBauds 0 31 16 r Reserved read as 0 should be written with 0 Application Note 60 V 1 0 2005 01 Infineon technologies SSCO CON AP32072 PCM Codec Connection to TC1130 SSCO Control Register SVV Description Value 0000 4007H Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 1 r 1 1 1 1 1 15 14 13 12 11 10 9 8 TA 6 5 4 3 2 1 0 EN MS 0 BEN BEN PEN REN TEN LB PO PH HB BM rw rw r rw rw rw rw rw rw rw rw rw w w TW Field Bits Typ Description BM 3 0 rw_ Data Width Selection 111 8 Bits Width HB 4 rw Heading Control 0 LSB First PH 5 rw Clock Phase Control 0 Shift transmit data on leading edge latch on trailing edge PO 6 rw Clock Polarity Control 0 Leading Clock Edge low to high LB 7 rw Loop Back Control 0 Normal Output TEN 8 rw Transmit Error Enable 0 Ignore Transmit Errors REN 9 rw Receive Error Enable 0 Ignore Receive Errors PEN 10 rw_ Phase Error Enable 0 Ignore Phase Errors BEN 11 rw Baudrate Error Enable 0 Ignore Baudrate Errors AREN 12 rw Automatic Reset Enable 0 No action upon baudrate error Application Note 61 V 1 0 2005 01 Infineon techn
21. Application Note V 1 0 Nov 2004 AP32072 PCM Codec Connection to C1130 Microcontrollers PCM Codec Connection to TC1130 Revision History 2005 01 V1 0 Previous Version Page Subjects major changes since last revision Controller Area Network CAN License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com EE Edition 2005 01 Published by Infineon Technologies AG 81726 Miinchen Germany Infineon Technologies AG 2006 All Rights Reserved LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND INCLUDING WITHOUT LIMITATION WARRANTIES OF NON INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE
22. BLKM r rw r rw r rw r rw rw rw rw i 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRSEL 0 TREL L w L r 1 L 1 L W 1 1 L Field Bits Typ Description TREL 8 0 rw Transfer Reload Value 0x20 32 Words Tranfer PRSEL 15 13 rw Module Disable Status Bit 010 Multiplexer Input 2 selected SSCO 0 TIR BLKM 18 16 rw Block Mode 000 1 Move RROAT 19 rw Reset Request Only After Transfer 0 Each Transfer needs a trigger CHMODE 20 rw Channel Operation Mode 1 Continuous Mode Operation CHDW 22 21 rw Channel Data Width 10 32 bits words PATSEL 25 24 rw Pattern Select 00 No Pattern Detection CHPRIO 28 rw Channel Priority 0 Low Priority DMAPRIO 30 rw DMA Priority 0 Low Priority Application Note 75 V 1 0 2005 01 _ AP32072 Infineon PCM Codec Connection to TC1130 SW Description Field Bits Typ Description 0 12 9 r Reserved read as 0 should be written with 0 23 27 26 29 31 DMA_CHICROO Value 0000 F008H DMA Channel 00 Interrupt Control Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRP WRP IRDV INTP WRPP INTCT DE SE rw wo wo rw WwW rw Field Bits Typ Description WRPSE 0 rw Wrap Source Enable 0 Wrap Source Interrupt Disabled WRPDE 1 rw Wrap Destination Enable 0 Wrap Destination Interrupt Disabled INTCT 3 2 rw Interr
23. Channel 01 xl Je ota DMA Channel 01 DMA Control for Channel 01 Interrupt Control r Channel 01 Data width CHDw r Transfer Reload Value C 8 bit byte transfer IV Enable Channel 01 C 16 bit half word transfer TREL Joso20 32 bit word transfer r Peripheral Request Control PRSEL r Source Start Address IM En r SADRO1 _ 0 00000000 PRSEL Multiplexer Input 3 Selected y r Destination Start Address DADRO1 Joxoo000000 Operation Mode CHMODE Single mode operation t Continuous operation m Pattern Select PATSEL I Disabled E Figure 25 DMA Block 0 Tab DMA Channel 01 General Tab Application Note 38 V 1 0 2005 01 infi AP32072 Infineon 2 PCM Codec Connection to TC1130 SW Description Configure Destination Buffer to 128 bytes Circular Buffer Set Increment Destination Buffer Address Y Configure DMA Channel 01 o 3 The Address is not Modified No of Moves is 1 PA Circular Buffer is of 128 Bytes y The Update Factor is 1 p The Update Factor is 1 Figure 26 DMA Block 0 Tab DMA Channel 01 Control Tab Application Note 39 V 1 0 2005 01 AP32072 PCM Codec Connection to TC1130 SVV Description technologies Enable Channel 03 Set Transfer VVidth to 32 bits Set Transfer Reload Value to 32 Set Continuous Operation Select Hardyvare Tra
24. D CBLS INCD DMF INCS SMF rw rw i rw rw rw rw Field Bits Typ Description SMF 2 0 rw Source Modification Factor 000 Source Address is not modified cf CBLS INCS 3 r Increment of Source Address 0 Source Address is not modified cf CBLS DMF 6 4 rw Destination Modification Factor 000 Update Factor is 1 word 32 bits INCD 7 rw Increment of Destination Address 0 Destination Address is Incremented CBLS 11 8 rw Circular Buffer Length Source 0x0 The Destination Address is not modified CBLD 15 12 rw Circular Buffer Length Source 0x7 Buffer is 128 bytes long SHCT 17 16 rw Shadow Control 00 Shadow Register is not used 0 31 18 r Reserved read as 0 should be written with 0 Application Note 82 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 DMA CHCRO3 DMA Channel 03 Control Register SW Description Value 0050 8020H Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T T T CH T T DMA CHP RRO 0 PRIO 0 RIO 0 PATSEL 0 CHDW MO AT BLKM r rw r rw r rw r rw rw rw rw i 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRSEL 0 TREL L w L r 1 L 1 L W 1 1 L Field Bits Typ Description TREL 8 0 rw Transfer Reload Value 0x20 32 Words Tranfer PRSEL 15 13 rw Module Disable Status Bit 100 Multiplexer Input 4 selected SSCO 0 TIR BLKM 18 16 rw Block Mode 0
25. In this application the SSC is used in the master mode It means that the SSC generates both the serial clock and the CS signal and has to takes care of the communication protocol baudrate and the interplay between CS signal and SCLK signal The SSC SCLK output has the property to drive an external clock only when at least one Chip Select is activated On the other hand many external CODECs needs continuous serial clock In order to implement this requirement SSC needs to communicate one word to the targeted Chip Select and 31 words to a dummy Chip Select In this way the SCLK Application Note 8 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 Introduction is always continuously on The Chip Select configuration registers SSOC and SSOTC are shadowed This means while an ongoing transaction is taking place the configuration for the next transaction can be prepared This configuration becomes relevant automatically with the start of the next transaction The transmit buffer FIFO makes it possible to have back to back transactions without loosing any clock cycles between words Although the SSC module has a FIFO its depth is not used in this application Note The maximum shift clock frequency for an SSC module in a master mode is fsys12 SCLK MRST sLson _ _ m MTSR Invalid aX Y Invalid A A AAA Data Frame l Slave Select Output ct Note This timing e
26. Interrupt on Level 10 This is only an example in your system you should make sure that this interrupt is high priority The maximum latency for this interrupt should be less than 62 5 us The interrupt is raised on the 15th slot and the value to update is located in the first slot Therefore at a rate of 8 kHz this is 125 us 2 xi I dta Module Clock Control Memory Block 0 RequestLost Interrupts Functions Parameters Notes CPU Interrupt max 255 DMA SRN 0 Note To change the level and the group of an interrupt source click on it drag it to its new position and drop it To set an interrupt source to the non interrupting level Level 0 click on it drag it to the Level 0 list and drop it Figure 29 DMA Interrupts Tab Application Note 42 V 1 0 2005 01 AP32072 PCM Codec Connection to TC1130 SVV Description technologies In Functions Tab Enable the DMA vlnit function Enable the DMA vSetSourceAddr and DMA vSetDestAddr macros I ta Module Clock Control Memory Block 0 RequestLost Interrupts Functions Parameters Notes m Initialization Function r Source File Vv Jona vr File name DMA 0 m Function Library Part 1 r Function Library Part 2 DMA vstatTransecion Mue vsetsoucesdd 0 F DMA_ubChannel ctive Iv Jona vsetdestadhr DMA_vEnableHW Transfer IV Jua vere 0 DMA_vDisableHw Transfer in Jon veri DMA_uwReadEnFl
27. MA MEOP OxF0003C3C OxFFFFFFFF 0x00000000 Pattern detection for R DMA not used Depends on your application DMA_MEOA 0xF0003C44 OxFEBFDFFF 0x01402000 Enable DMA access to ENR EBU and SSCO module DMA_MEOA 0xF0003C48 OxFFOOOOFF OxOOFFFFOO Enable DMA access to RR internal RAM DMA_HTRE OxFO003C1C OxFFFFFFF4 0x0000000B Enable DMA Hardware Q Transaction Request for Channel 00 01 and 03 DMA SRCO OxFOOO3EFC 0x00000000 0x0000100A Enable DMA Service Request Node 00 to priority 10 This depends on your application Application Note 57 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 4 2 5 SSC Registers SSCO CLC SSCO Clock Control Register SW Description Value 0000 0000y Reset value 0000 0003y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 16 0 1 ji r 1 1 1 1 i 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FS SB E SP DIS DIS OE WE DIS EN S R rw r rw rw r rw Field Bits Typ Description DISR 0 rw Module Disable Request Bit 0 Module Enabled DISS 1 r Module Disable Status Bit SPEN 2 rw Module Suspend Enable for OCDS 0 OCDS Module Enabled EDIS 3 rw External Request Disable 0 External Clock Disable Request Disabled SBWE 4 w Module Suspend Bit Write Enable for OCDS 0 OCDS Module related register unprotected FSOE 5 rw_ Fast Switch Off Enable 0 Fast Clock Switch Off disabled 0 31 6
28. Output Selection 0 Normal GPIO 1 Alternate Select 2 Reserved read as 0 should be written with O 0 31 16 Here P1 13 and P1 11 are used for SLSO2 and SLSO1 pins You can choose different SLSO pins to connect your CODEC on Application Note 68 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description P1_DIR Value 0000 2800y Porti Direction Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 PO rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Typ Description Pn n rw Port 1 Pin n Direction Control 0 Input 1 Output 0 31 16 r Reserved read as 0 should be written with 0 Here P1 13 and P1 11 are used for SLSO2 and SLSO1 pins so they need to be setup as output Application Note 69 V 1 0 2005 01 _ Infineon technologies P2_ALTSELO Port2 Alternate Select Register 0 AP32072 PCM Codec Connection to TC1130 SW Description Value 0000 0018H Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 1 r 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10
29. SW Description DMA_EER Value 0000 0000 DMA Enable Error Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T T T T T T T T T T E E TRLINP 0 MEOINP 0 MEO MEO DER SER rw r rw r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e E E E E E E E E 0 TRL TRL TRL TRL TRL TRL TRL TRL l 07 06 05 04 03 02 01 00 r rw rw rw rw rw rw rw rw Field Bits Typ Description ETRLOn n rw Enable Transaction Request Lost for DMA n 0 7 Channel On 0 Request Lost disabled EMEOSER 16 rw Enable Move Engine 0 Source Error 0 Interrupt Disabled EMEODER 17 rw Enable Move Engine 0 Destination Error 0 Interrupt Disabled MEOINP 23 20 vv Move Engine 0 Error Interrupt Node Pointer 0x0 Errors go to Node O TRLINP 31 28 rw Transaction Lost Interrupt Node Pointer 0x0 Errors go to Node O 0 15 8 r Reserved read as 0 should be written with 0 19 18 27 24 Application Note 74 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 DMA_CHCROO DMA Channel 00 Control Register SW Description Value 0050 4020H Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T T T CH T T DMA CHP RRO 0 PRIO 0 RIO 0 PATSEL 0 CHDW MO AT
30. Source Address 1 The Source Address will be Incremented DMF 6 4 rw Destination Modification Factor 000 Destination Address is not modified cf CBLD INCD 7 rw Increment of Destination Address 0 Destination Address is not modified cf CBLD CBLS 11 8 rw Circular Buffer Length Source Ox7 Buffer is 128 bytes long CBLD 15 12 rw Circular Buffer Length Source 0x0 The Destination Address is not modified SHCT 17 16 rw Shadow Control 00 Shadow Register is not used 0 31 18 r Reserved read as 0 should be written with O Application Note 86 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description DMA MEOPR Value 0000 0000H DMA Move Engine 0 Pattern Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PATO3 PATO2 rw 2 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PATO1 PATOO TW L L L AN ji L Field Bits Typ Description PATOO 7 0 rw Pattern for Move Engine 0 PATO1 15 7 0x00 Not used here PATO2 23 16 PATO3 31 24 DMA_MEOAENR Value 0140 20004 DMA Move Engine 0 Access Enable Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw r
31. V 1 0 2005 01 Infineon ATARA technologies PCM Codec Connection to TC1130 SW Description DMA_HTREQ Value 0000 000By DMA Hardware Transaction Request Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 DCH DCH DCH DCH DCH DCH DCH DCH 07 06 05 04 03 02 01 00 r w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ECH ECH ECH ECH ECH ECH ECH ECH 07 06 05 04 03 02 01 00 w w w w w w w w Field Bits Typ Description ECHOn n w Enable Hardware Transfer Request for DMA Channel On Ox0B Enable Hardware Transaction Request for Channel 00 01 and 03 DCHOn n 16 w Disable Hardware Trasnfer Request for DMA Channel On Ox00 Don t disable any Hardware Requests 0 15 8 31 24 Reserved read as 0 should be written with 0 Application Note 89 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 SW Description DMA_SRCO Value 0000 100Ay DMA Service Request Control Register 0 Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 L r L l 15 14 13 12 11 10 9 8 Le 6 5 4 3 2 1 0 SET CLR SRR SRE 0 TOS o SRPN w w rh rw r rw r rw Field Bits Typ Description SRPN 7 0 rw S
32. ags a DMAWSRN2 0 DMA_vClearE nFlags EJ DMA MISA DMA_ubTransterlnt DMA ubyvrapDestint DMA ubyvrapSourcelnt DMA_vClearTransterlnt DMA_vClearwraplnt DMA_usReadTxCount MA vSetT xCount pi r r r r F r r r r F Figure 30 DMA Functions Tab Configuring SCU Unfortunately for now Dave doesn t support DMA Request inputs configuration within the System Control Unit SCU Therefore additional code will be included by hand This feature should be available in the next release Application Note 43 V 1 0 2005 01 _ Infineon AES2D7A technologies PCM Codec Connection to TC1130 SW Description Saving Project Generating Code and Making a new GNU Project Save your project somewhere on your harddrive Note Please be carefull as we are using the GNU Toolchain it doesn t support directory names with spaces inside and this is a valid consideration for the whole path i e C ltestiTC1130 Projects is not valid you can use something like CilteshTC1130 Projects You can generate the code by pushing the lightning icon you should then find those files in your directory DMA c DMA h MAIN c MAIN h SSCO c SSCO h TC1130Regs h Project dav Project dpt and Project asm Copy a target ld file from the Hightec directory into your project directory i e from C Hightec Tricore Examples TriBoard TC1 130 GetStart target Id You need to edit this file to include an extra se
33. annel Application Note 15 V 1 0 2005 01 _ Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description Most of PCM codecs need this clock for internal operation The audio signal coming from the DAC is based on this frequency which should be 2 048 MHZ The shift baudrate should therefore be 2 048 MBauds The TC1130 has very flexible clock and baudrate generation facilities However this 2 048MHz clock cannot be derived from any input clock The internal baudrate is defined by I sys 2 BR t1 1024 FDR Baudrate With BR Value for baudrate timer 16 bits value FDR Fractional divider reload value Fsys System clock frequency There is a limitation here if you want to generate a 2 048MHz If you use a crystal i e 20MHZ for CPU operation at 150MHz then you will get BR 1 1024 FDR 200 18 31055 4096 As BR and FDR are integer number this is impossible to realize The crystal should therefore be selected to suit the needs Here we selected a 12 288 MHz crystal with which you can easily derive a 2 048 MHz clock BR 17 0x0011 FDR 0 0x0000 The CPU frequency is chosen to be 147 456 MHz this is not described here as this is not the purpose of this appnote i e PLL is setup to multiply by 12 and the system frequency fsys is equal to half of the CPU frequency the FPI bus maximum frequency is 100 MHz 4 1 2 Data output As seen before a PCM codec needs a
34. applications the PCM interface is more used as it is somehow simpler and is already well defined in the market This application note will concentrate on the PCM type of connection Application Note 5 V 1 0 2005 01 _ Infineon APARTA technologies PCM Codec Connection to TC1130 Introduction 2 1 PCM Stream When implementing PCM the first step is to filter the analog speech signal in order to suppress the spectral components beyond 4 kHz This is followed by sampling at the rate of 8 kHz then a uniform 8 bit quantization giving out 256 quantization levels As a result the PCM yields to 64 Kbps data speed Since the uniform quantizes does not provide the best SNR the quantization is nonlinear by applying a compressor function on the analog samples which is inverted by an expander in the course of digital to analog conversion Due to the derivation of the optimal quantizes the compressor has a logarithmic characteristics There are mainly two important companding laws 1 The A law mostly used in Europe which is given by the following rule 1 log Ax 1 E ee el Trlog A 1 2 _ Ax o lt x lt 1 Y T log A SESA 2 The p law is mostly used in United States and Japan which is given by the following rule _ log l yx Jog i tu El The specific values for these companding laws are A 87 6 and y 1000 The PCM stream consists of a serial communication channel between the processor and the c
35. argets debug tricore gcc c DMA c g 02 Wall mtc13 mepuzT C1130 tricore gcc c MAIN c g 02 Wall mtc13 mepuzT C1130 tricore gec c SSCO c g 02 wall mtc13 nepu TC1130 tricore gcc o LoopbackTest elf Xlinker T Xlinker target Id DMA o MAIN o SSC0 o End Figure 35 Source Navigator Build Compiling project You can download the Project elf file to the Triboard You can connect a codec to the SSCO as described in the previous chapter If you put audio data like music or voice to the codec you should get it on the output 4 2 3 Results and Measurement The program was tested using only one codec connected to SLSO1 The input of the codec is connected to the output of a PC playing some music of course the aim is to interface an audio codec so the result will be a bad quality music The output of the codec is connected to loudspeakers The codec used for this experiment is a MC145481 from Motorola On the next picture you can see the clock which is running without any break The clock is here 2 048 MHz Signal 1 is the Frame Select Chip Select for the Left Channel codec You can see it is 8 bits long Signal 2 is the Frame Select for the Right Channel codec which is not connected here Signal 3 is the data which comes out of the SSC and Signal 4 is the data which is shifted out of the Codec Application Note 52 V 1 0 2005 01 a Chi n AP32072 ACZ PCM Codec Connection to TC1130 SW Descrip
36. dec and the way you connect it to the Slave Select Outputs you will need to set the values differently The Trigger used for this channel is of course the same as Channel 0 every time a word has been loaded in the transmit shift register The Channel selected here is Channel 3 This is due to the fact that TIR signal which should trigger the DMA can only be connected to Channel 0 or 3 For more details please refer to the System User s manual chapter 17 3 1 1 and 4 6 Example using 2 separated codecs for each left and right channel Here the Left channel codec is connected to SLSO1 and the Right channel to SLSO2 OOFF SLSOF2 1 00 02FF SLSO 2 1 10 04FF SLSO 2 1 01 Note This was chosen because those signals are located on the same connector on the Triboard but any Slave Select Output could have been chosen index 0 1 2 3 s 28 29 30 31 02FF 04FF FF FF FF FF FF FF Control Slots P index a a 2 a y 28 02 30 31 ata Data E Left Right ojo lojo Transmit Slots 32 words 32 bits wide circular buffer ee Po ee CLK p aiz z A a i p WILLI NL NI T Trigger p aos Interrupt to CPU Source Channel ds Des gt Transmit Butter gt Transmit e A Left XX Right A A Left XRight 4 Receive 31 o 1 14 18 16 31 0 1 7 S
37. dex 0 1 2 3 m 28 29 30 31 02FF 04FF FF FF FF FF FF FF Control Slots index 0 2 3 28 29 30 3 Data Data Left Right 0 0 0 0 0 0 Transmit Slots A 32 words 32 bits wide circular buffer A ATTE CLK UML NAN LILI T pe Interrupt to CPU gt M99 Channel 0 Dest gt Transmit Buffer gt gt MISR ye y AA gt Source Transmit K Lett Right E 4 5 K Left Right ai 41 0 1 2 15 16 3 0 1 Ti assi Channel 1 Source lt Receive Buffer lt scans ja MBST PY 7 S a Dest Lett X Right pa Left X Right 0 1 2 15 16 31 0 1 2 Sas SLSO1_y lave Select T gt Channel 3 Dest gt Slava Select gt Outputs gt Source Output Register p Generation SLS02_ y DMA SSC w h Ye 4 4 Figure 10 Chip Select Generation for Stereo codec Application Note 20 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description 4 2 SW Implementation The software implementation for PCM Codec support on TC1130 is fairly simple and has basically only peripheral initialization The only running software part will be an interrupt which comes every time a new sample has been sent and one received as well This makes this implementation very light for the CPU As a matter of fact if there would be a
38. eaches IRDV Set Transfer Count Threshold Limit to 15 xi el ota 2 DMA Channel 00 DMA Control for Channel 00 Interrupt Control r Wrap Interrupt Control m Transfer Interrupt Control INTCT I Enable wrap source interrupt WRPSE Transfer interrupt disabled Interrupt event when transfer counter TCOUNT matches threshold limit IRDV Transfer interrupt disabled Interrupt event when transfer counter TCOUNT is decremented J Enable wrap destination interrupt WRPDE Transfer interrupt enabled Interrupt ievent when transfer counter TCOUNT matches threshold limit IRD r Interrupt Raise Detect Value IRD W Transfer counter threshold limi fs matches threshold IME IO crono i ik Transfer interrupt enabled Interrupt C event when transfer counter TCOUNT is decremented Wrap Pointer WRPP gt Transfer Interrupt Node Pointer INTP Interrupt node pointer for Wrap Around and Pattern Match interrupt Figure 24 DMA Block 0 Tab DMA Channel 00 Interrupt Control Tab Application Note 37 V 1 0 2005 01 AP32072 PCM Codec Connection to TC1130 SVV Description technologies Enable Channel 01 Set Transfer VVidth to 32 bits Set Transfer Reload Value to 32 Set Continuous Operation Select Hardyvare Transaction from Multiplexer Input 3 this is SSCO 1 signal please refer to System User s Manual chapter 17 3 1 1 for more details Configure DMA
39. ervice Request Priority Number Ox0A Priority set to OXOA TOS 10 rw Type Of Service Control 0 Priority set to OXOA SRE 12 rw Service Request Enable 1 Service Request Node Enabled SRR 13 rh Service Request Flag CLRR 14 w Request Clear Bit SETR 15 rw Request Set Bit 0 9 8 r Reserved read as 0 should be written with O 11 31 16 Application Note 90 V 1 0 2005 01 91 http www infineon com Published by Infineon Technologies AG
40. et to SSC0_0 signal which is connected to TIR see SCU configuration Continuous Operation selected Transfer Interrupt disabled Channel 1 enabled and set to 32 bits wide transfer Transfer reload set to 32 0x20 Number of Moves set to 1 Source address set to SSC Receive Buffer SSCO_RB Source buffer without any address modification Destination address set to Receive_Slots array Destination buffer is 128 bytes circular update factor of 1 increment Hardware Transaction enabled and set to SSCO 1 signal which is connected to RIR see SCU configuration Continuous Operation selected Transfer Interrupt disabled Application Note 22 V 1 0 2005 01 _ Infineon AES2D7A technologies PCM Codec Connection to TC1130 SW Description The DMA requests inputs for Channel O 1 and 3 needs to be connected to SSCO_TIR and SSCO_RIR This is done using a multiplexor which is configured in the System Control Unit SCU Please refer to the System User s Manual chapter 4 6 for more details The SCU needs to be configured as follow SSCO 0 DMA request signal connected to TIR SEL6 set to O in SCU_DMARS SSCO_1 DMA request signal connected to RIR SEL7 set to 1 Note The logic implemented in the DMA controller to support circular buffer uses a mask approach This means that the buffers must be aligned to boundaries In this case for 128 bytes buffers they must be aligned to 128 bytes boundaries
41. gment to put the Slots arrays in This is because we need to align them to 128 bytes boundaries In target ld file You need to include a new memory to put the arrays into MEMORY ext_cram arx p org 0xa0000000 len 512K ext_dram aw xp org 0xa0080000 len 1M ext_dram2 aw xp org 0xa0180000 len 384 int_cram arx p org 0xc0000000 len 0x8000 int_dram aw xp org 0xd0000000 len 0x8000 pcp data awp x org 0xf0010000 len 32K pcp_text arxp org 0xf0020000 len 16K The size of the segment is 32 4 3 384 bytes Then you need to create a section for it at the very end of the file Optional sections that may appear regardless of relocating E boffs 0 KEEP boffs data2 data2 gt ext_dram2 Application Note 44 V 1 0 2005 01 e Infineon technologies AP32072 PCM Codec Connection to TC1130 SVV Description Open the Red Hat Source Navigator Create a nevv Project in your project directory vvhere you have generated the files Auto Create Project lol xi Q Do you want to automatically create a Source Navigator Project based on Project File Projects TC1130 Codec LoopbackTest LoopbackTest proj Add Directory y z more IV Include Subdirectories Build Cross Reference database Project Editor Cancel Figure 31 Source Navigator Creating a new project Application Note 45 V 1 0 2005 01 Inf
42. hift Register Slave Select gt lave Seleci gt Tiger hannel3 Dest Slave Select outputs Source Output Register Generation ae gt DMA SSC Figure 8 Chip Select Generation for 2 codecs configuration e Example using a single stereo codec Here the codec has a chip select connected to SLSO1 and a pin to indicate Left or Right channel connected to SLSO2 OOFF SLSOF2 1 00 02FF SLSO 2 1 10 O6FF SLSO 2 1 11 Application Note 18 V 1 0 2005 01 as Infineon owo technologies PCM Codec Connection to TC1130 SW Description index 0 1 2 3 28 29 30 31 O2FF O6FF FF FF FF FF FF FF Control Slots z me pala Pata 5 5 7 Fr ti i Transmit Slots Left Right Z 32 words 32 bits wide circular buffer ttt 1 int cik y A ILMLULLLINLINLLILN NN NUI gt Trigger P MTSR Bride Interrupt to CPU gt Source Ghahnel G Dest gt Tane Bet gt Transmit gt X Left Y Right y A K Left X Right Receive 31 0 1 4 158 16 31 0 1 Shift Register ARTE SLSO1 y lave Selec gt kimi Channel 3 Dest gt ds gt Outputs lcd P g Generation SLS02 y DMA SSC Figure 9 Chip Select Generation for Stereo codec 4 1 4 Input Handling Of course we want to be able to read from the codec as well The TC1130 can work in a full duplex mode al
43. hould be Ox0011 Y High Speed Synchronous Serial Interface SSCO I ota Figure 18 SSCO Baud Rate Tab Application Note 31 V 1 0 2005 01 e Infineon ir technologies PCM Codec Connection to TC1130 SW Description In Functions Tab Enable the SSC_vinit and SSCO_vSendData functions B High Speed Synchronous Serial Interface SSCO SSCO_vSendData M mi Ui mj EJ El a J y E Hi Figure 19 SSCO Functions Tab Application Note 32 V 1 0 2005 01 e Infineon ir technologies PCM Codec Connection to TC1130 SW Description Configuring DMA In Module Clock Tab Enable Service Request Node 0 B Direct Memory Access DMA Figure 20 DMA Module Clock Tab Application Note 33 V 1 0 2005 01 e Infineon ir technologies PCM Codec Connection to TC1130 SW Description In Memory Tab Enable SSCO EBU external EBU space Address Ranges B Direct Memory Access DMA I 60 a E a al al a mi mi E mi a a mJ v D Ej mi ao week Figure 21 DMA Memory Tab Application Note 34 V 1 0 2005 01 AP32072 PCM Codec Connection to TC1130 SVV Description technologies In Blocko Tab Enable Channel 00 Set Transfer VVidth to 32 bits Set Transfer Reload Value to 32 Set Continuous Operation Select Hardyvare Transaction from Multiplexer Input 2
44. ineon technologies AP32072 PCM Codec Connection to TC1130 Open the Build Settings Dialog Tools gt Build Settings Create a new Target named debug Set as build directory Select all C files and Add them to the build list SW Description Source Files Library Files Build Rules Link Rules Project Files Target Files gt Add Files gt Clear Clear All Import Files Directory Build Directory Target Type Executable al Tool Chain HighTec TriCore PXROS vi Figure 32 Application Note Source Navigator Build Settings Source Files 46 V 1 0 2005 01 ja AP32072 Infineon ss PCM Codec Connection to TC1130 SW Description In Build Rules double click on the C rule Set Standard Debug Report All Warnings Optimization level 2 Tricore v1 3 Select TC 1130 as target by including mcpu TC1130 as user flag Note mcpu TC1 130 is only valid from Hightec GNU v3 3 5 1 on If you have an older version you can include mall errata instead Build Rule Settings C lolx Settings Includes Defines Debug Standard Debug kd Optimization Level 2 v W amings Report All Warnings vj Code Generation TriCore v1 3 User Flags ncpu TC1130 Executable Jricore gce ks tricore gce c lt g 02 Wall mtc13 nepu TC1130 Figure 33 Source Navigator Build Settings C Rule Application Note 47 V 1 0
45. ion is to synchronize the PCM data word transfer and the second is to control the internal codec analog to digital and digital to analog conversions The term sync refers to the function of synchronizing the PCM data word onto or off the multiplexed serial PCM data bus also known as PCM highway The short frame sync has the same functionality as the long frame sync signal but its duration is just a pulse in the beginning of the transmission receiving frame In this case the short frame sync signal is used as a pre synchronization that is used to tell the internal logic of the codec to clock out the PCM data word under complete control of the data clock Note For this application only the long frame sync signal is relevant For a stereo codec two channels included on chip the frame sync signal will be generated separately for each of the channels like two independent mono codecs connected on the same PCM bus Depending on the master clock frequency the number of voice channels 8 kHz can vary For example in the case of a master clock with a frequency of 2 048 MHz the number of 8 kHz PCM channels on the PCM highway is 32 An example of the framing signals together with the data and master clock is shown in Figure 2 In this figure a connection in which the processor is the master that is it generates all the needed signals to operate the codec is described Sampling moments Figure 2
46. it FIFO Enable 0 FIFO Disable RXFFLU 1 w Transmit FIFO Flush 0 FIFO is Flushed RXTMEN 2 rw Transmit FIFO Transparent Mode Enable 0 Transparent Mode Disabled RXFITL 11 8 rw Transmit FIFO Interrupt Trigger Level 0x0 not used 0 7 3 r Reserved read as 0 should be written with 0 31 12 Application Note 63 V 1 0 2005 01 Infineon ATARA technologies PCM Codec Connection to TC1130 SW Description SSC0_SSOC Value 000000064 SSCO Slave Select Output Control Register Reset value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OEN OEN OEN OEN OEN OEN OEN OEN AOL AOL AOL AOL AOL AOL AOL AOL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Typ Description AOLn n rw Active Output Level 0x06 SLSO1 and SLSO2 high active OENn 8 n rw Output n Enable Control 0x00 SLSO1 and SLSO2 inactive 0 31 16 r Reserved read as 0 should be written with 0 Note Here SLSO1 and SLSO2 are used You can use any output you want Application Note 64 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 SSCO SSOTC SSCO Slave Select Output Timing Control Register SVV Description IValue 0000 0000H Reset value 0000 0000y
47. itecture 4 1 1 Clock Generation A PCM stream is very similar to a synchronous data transmission that you can find on most microcontrollers The main difference here which we have to carefully take care about is the fact that the clock signal which is used to shift data in and out must be constant This means that the clock must never stop running refer to chapter 1 for more details In a synchronous communication channel the clock is running only when data is transmitted therefore we need a way to create this clock continuously The SSC can be configured to generate an interrupt each time the shift register is loaded actually the interrupt is generated when the transmitter buffer is empty TIR This interrupt can be used to trigger a DMA transfer which is totally independent from the CPU This DMA will load the Transmitter buffer with some data Therefore when the SSC has finished shifting out the data it has another data ready for transmit the clock doesn t stop For further details please check the TC1130 Peripheral User s Manual chapter 3 1 2 4 The interrupt doesn t have to be serviced by the CPU only a DMA channel is triggered with this signal CLK gt LILPLILILI MTSR gt Trigger Channel 0 Dest gt Transmit Buffer Shift Register gt po X D1 X 7 X o7 X Bo X DL X DMA SSC Figure 6 Continuous SSC Clock operation with DMA ch
48. logies AP32072 PCM Codec Connection to TC1130 In System Clock Tab Set External Crystal Frequency to 12 288 MHz SW Description depends on your application you will need to adapt other settings if you choose a different crystal Set PDIV to 2 Set NDIV to 96 Set KDIV to 4 Set VCO Range to 500 600 MHz Set fcpu fsys ratio to 2 1 E Interrupt System Startup Configuration Notes Project Settings zi m External Clock Frequency External clock frequency 12 288 MHz E fp fosc 72 6 144 MHz Input divider PDIV ni PLL Bypass operation fepu fosc pin BYPASS 1 r Voltage Controlled Oscillator VCO I VCO Bypass mode VCOBYP The ratio fcpu fsys is 1 1 VCD range VCOSEL 500 MHz 600 MHz Feedback divider NDIY Gg VCO output eedback divider NDIV fco fosc P 96 583 824MHz Y FG 583 824 r Output Divider Output divider KDIY Jtepu fvco 4 147 456 MHz w MH i 47 45600000 The ratio fopu fsys is 2 1 ee Clock 372800000 z Figure 12 Project Settings System Clock Tab Application Note 25 V 1 0 2005 01 e Infineon ir technologies PCM Codec Connection to TC1130 SW Description In Interrupt System Tab Enable Interrupts Project Settings Figure 13 Project Settings Interrupt System Tab Application Note 26 V 1 0 2005 01 AP32072 PCM Codec Connection to
49. lowing output samples to be written to the codec and incoming samples to be read from it at the same time In full duplex mode the receiver shift register is shifted at the same time as the transmit shift register This means that when sending out Left Channel for example the receive shift register is also shifted and the Left incoming Channel data will then be valid on the next slot To receive the data we use another DMA Channel which is this time triggered when data has been received in the receive shift register Once the data has been received the DMA is triggered and saves the value into a third 32 words circular buffer The Channel selected here is Channel 1 This is due to the fact that RIR signal which should trigger the DMA can only be connected to Channel 1 or 4 For more details please refer to the System User s manual chapter 17 3 1 1 and 4 6 As explained before the left channel will be received in slot 1 and the right channel in slot 2 Note Of course you could setup Channel 1 to start with one step behind Channel 0 and 3 In this case you will have all samples on the same slots i e Left on Slot 0 Right on Slot 1 This is just a software issue Application Note 19 V 1 0 2005 01 AP32072 PCM Codec Connection to TC1130 SVV Description technologies The example shown here is using the 2 codec configuration index 0 i 2 3 28 29 30 31 gt 2 koli a 27 2 2 2 Receive Slots 7 in
50. mmary In the previous chapter all initialization code is automatically generated by Dave This is a very powerful tool You can extract the value of the registers which it had initialized and use it In this chapter all the registers which are needed for this application are listed and the value which should be put in is shown All registers which are not described here keep their reset value A detailed description of each register follows after Table 1 Application Note 54 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 SW Description Table 1 Register Overview Register Address Mask Value Comment SSCO_CLC 0xF0100100 0x00000000 0x00000000 Enable SSCO Module SSCO_FDR 0xF010010C 0x00000000 0x000043FF Setup SSCO Clock to 73 728 MHz SSCO BR 0xF0100114 0x00000000 0x00000011 Setup SSCO Baudrate to 2 048 MBauds SSCO_CON 0xF0100110 0x00000000 0x00004007 Setup SSCO 8 bits LSB first Rising Edge SSCO RXF 0xF0100130 0x00000000 0x00000002 Disable SSCO Receive CON FIFO SSCO TXF 0xF0100134 0x00000000 0x00000002 Disable SSCO Transmit CON FIFO SSCO_SSO 0xF0100118 0x00000000 0x00000006 Use SLSO1 and SLSO2 C as Slave Select Outputs This depends on which pin you connect the codec to SSCO SSO 0xF010011C 0x00000000 0x00000000 SLSOx pins use TC standard timing SSCO_PISE 0xF0100104 0
51. mmy data SSCO_vSendData 0x12 Main Loop while 1 Note Some code was added to initialize the Port 1 Alternate functions for the Slave Output pins This is not initialized in Dave this is a bug which will be corrected in the next release Save the MAIN c file Application Note 50 V 1 0 2005 01 e Infineon technologies AP32072 PCM Codec Connection to TC1130 SVV Description Double click on DMA c file Add the Loopback code in the DMA Service Request Node or your own specific code like a call to the device driver USER CODE BEGIN SRNO 1 extern unsigned int Transmit_Slots 32 extern unsigned int Receive_Slots 32 USER CODE END void DMA_viSRNO void t USER CODE BEGIN SRNO 2 if DMA_INTSR 6 0x0001 is it Channel 0 TCOUNT Match clear the flag DMA_INTCR 0x0001 Loopback incoming samples to output Transmit_Slots 0 Receive_Slots 1 Transmit_Slots 1 Receive_Slots 2 USER CODE END Y 11 End of function DMA_viSRNO Save the DMA c file Application Note 51 V 1 0 2005 01 Infineon ATARA technologies PCM Codec Connection to TC1130 SW Description In the Symbols window open the Build dialog Tools Build Select the debug target Click on Start Build make Source Navigator LoopbackTest oj xi File Edit History Tools Windows Help KID Build commandipnake Directory Build T
52. n Note 49 V 1 0 2005 01 technologies AP32072 PCM Codec Connection to TC1130 SVV Description Include the SCU configuration DMA Channel Setup and Slots Initialization MAIN_vInit USER CODE BEGIN Main 9 Configure SSCO 0 Dma request input to SSCO TIR Configure SSCO 1 Dma request input to SSCO RIR SCU_DMARS 0x0080 SN workaround for Dave will be corrected in next release P1 11 is used for SLSO1 P1 13 is used for SLSO2 P1_ALTSELO Ox0000 select alternate output function P1_ALTSEL1 Ox2800 select alternate output function P1_DIR 0x2800 set direction register Setup DMA for Transmit Slots DMA_vSetSourceAddr DMA CH 00 unsigned int amp Transmit_Slots DMA_vSetDestAddr DMA_CH_00 unsigned int amp SSCO_TB Setup DMA for Control Slots DMA_vSetSourceAddr DMA_CH_03 unsigned int amp Control_Slots DMA_vSetDestAddr DMA_CH_03 unsigned int amp SSCO_SSOC Setup DMA for Receive Slots DMA_vSetSourceAddr DMA CH 01 unsigned int amp SSCO_RB DMA_vSetDestAddr DMA CH 01 unsigned int amp Receive_Slots Initialize the Slots for 1 0 1 lt 32 1 Transmit_Slots i Receive_Slots i 0x0000 Control_Slots i Ox00FF Put the correct values now Control_Slots 0 Ox02FF Left Select ist CODEC on SLSO1 Control_Slots 1 0x04FF Right Select 2nd CODEC on SLSO2 Start transmission with Du
53. nsaction from Multiplexer Input 4 this is SSCO 0 signal please refer to System User s Manual chapter 17 3 1 1 for more details x ei ota 2 DMA Channel 03 DMA Control for Channel 03 Interrupt Control r Channel 03 Data width CHDW r Transfer Reload Value C 8 bit byte transfer Y Enable Channel 03 C 16 bit hali word transfer TREL 0020 32 bit word transfer r Peripheral Request Control PARSEL Source Start Address r SADRO3 0x00000000 PRSEL Multiplexer Input 4 Selected y Destination Start Address DADRO3 Joxoooo0000 r Operation Mode CHMODE Single mode operation Continuous operation m Pattern Select PATSEL Disabled m Figure 27 DMA Block 0 Tab DMA Channel 03 General Tab Application Note 40 V 1 0 2005 01 infi AP32072 Infineon PCM Codec Connection to TC1130 SW Description Configure Source Buffer to 128 bytes Circular Buffer Set Increment Source Buffer Address Configure DMA Channel 03 JAA 2 Circular Buffer is of 128 Bytes y No of Moves is 1 The Address is not Modified The Update Factor is 1 y The Update Factor is 1 E Figure 28 DMA Block 0 Tab DMA Channel 03 Control Tab Application Note 41 V 1 0 2005 01 Chi n AP32072 AA CZE PCM Codec Connection to TC1130 SW Description In Interrupts Tab Put the DMA SRNO Request Node
54. ntinuos clock for its internal timing and operation In the case of a stereo codec or in the case of two chips usage there will be three such channels two channels each with a slave select line for the chip channel selection for real audio data input output and one dummy channel used for generating the permanent clock Application Note 12 V 1 0 2005 01 y e Infineon Arete technologies PCM Codec Connection to TC1130 HW Description SLSOO SLSO1 SLSO2 TC1130 SCK JI SLSOO Enable o AA SLSO1 Enabl SLSO2 Enable Figure 4 Multiplexing Slave Select Signals 3 2 Connection Example In this paragraph a typical connection between the MC145481 PCM codec and the Serial Synchronous Channel of the TC1130 is described The connection is using the SSC Serial Synchronous Channel of the TC1130 to directly interface the MC145481 codec For the codec the framing signal of the receive line and for the transmit line are connected together This enables the codec to transmit and receive in the same time full duplex operation which is supported by the serial interface of the TC1130 The bit clock BLCK and master clock MCLK are connected also together for the codec chip thus providing the master clock clock from which all the internal timings are derived for the analog digital conversions with the same frequency as the bit symbol clock The PCMIN and PCMOUT of the codec chip are c
55. odec The PCM bus is a bidirectional synchronous bus in which all the signals are derived from a master clock In the PCM type codecs this master clock is also used for all tne analog signal processing including analog to digital conversion and digital to analog conversion and also for some transmit and receive filtering In general this master clock is an integer multiple of the 8kHz frequency used in voice applications common data rates for the master clock can be depending on the particular PCM codec 256 kHz 512 kHz 1 536 MHz 1 544 MHz 2 048 MHz etc The PCM stream consists mainly of the master clock line a special frame signal and two serial data lines one transmit and one receive line as input or output of the codec respectively the processor The framing signal is a control line which determines the moments in which the data on the data lines is valid for read write For the frame signal there are actually two versions in the PCM interface long frame sync and short frame sync 1 The words compressor and expander are often combined into the terminology compander Application Note 6 V 1 0 2005 01 _ Infin n AP32072 Infineon PCM Codec Connection to TC1130 Introduction The long frame sync is the industry name for a clocking format that controls the transfer of the PCM data words This signal the frame sync is used for two specific synchronizing functions The first synchronizing funct
56. ologies AP32072 PCM Codec Connection to TC1130 SW Description Field Bits Typ Description MS 14 rw Master Select 1 Master Mode EN 15 rw Enable Bit 1 Transmission and Reception enabled 0 31 16 r Reserved read as 0 should be written with 0 SSCO_RXFCON SSCO Receive FIFO Control Register Value 0000 0002 Reset value 0000 0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 1 r 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T T T T T T T T T RX RXF RXF 0 RXFITL 0 EN FLU EN r rw r rw w rw Field Bits Typ Description RXFEN 0 rw Receive FIFO Enable 0 FIFO Disable RXFFLU 1 w Receive FIFO Flush 1 FIFO is Flushed RXTMEN 2 rw Receive FIFO Transparent Mode Enable 0 Transparent Mode Disabled RXFITL 11 8 rw Receive FIFO Interrupt Trigger Level 0x0 not used 0 7 3 r Reserved read as 0 should be written with 0 31 12 Application Note 62 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 SSCO TXFCON SVV Description Value 0000 0002 SSCO Transmit FIFO Control Register Reset value 0000 0100y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TX 0 TXFITL 0 TM EN r rw r rw Ww rw Field Bits Typ Description RXFEN 0 rw Transm
57. on 3 HW Description 3 1 General The hardware interfacing of the TC1130 to an external PCM codec was limited due to price considerations The idea is to provide a connection without any external component between the TC1130 and the PCM codec In order to provide an efficient mean of interfacing the PCM device to the TC1130 the Serial Synchronous Channel SSC of the microcontroller was chosen The operation of the synchronous interface is to provide the shifting clock only during data transfers on the data lines one input and one output On the other side the PCM codec needs a continuos clock input at its clock input pin in order to generate the internal signals needed for conversion For the codec chip this clock acts as a master clock from which all internal timings are derived there is no other clock for the codec chip This application note demonstrates how to program the SSC of the TC1130 to provide a continuos clock signal by enabling different chip selects signals in different moments of time The core of the solution is the usage of the slave select lines built in the SSC interface to select the codec chip during the data transfers and to select a dummy device from to which to transfer dummy words during the time in which the intended codec is not selected By using this dummy device the SSC interface will continue to generate clock for shifting and therefore the PCM clock is permanent The PCM codec chip can use this now co
58. onnected to the data I O of the SSC module on the TC1130 side In this example the TC1130 is configured as master i e it will generate the clock for the PCM bus This PCM clock is in fact the serial bit clock for the data shifting of the SSC Application Note 13 V 1 0 2005 01 technologies AP32072 PCM Codec Connection to TC1130 HW Description 0 1 pF I VagRef 3 68 pF 20kQ PI 2 ANALOG IN AUDIO OUT A Um 4 R2150 PO A 5 16 1 0 uF 10 PO MUA 3V 15 Vo Vos H u FSR FST dh 8kHz dl Slave Select Se 13 PCM OUT Master Rx Slave Tx DR DT MRST 12 2 048 MHz SSC Clock e BOLKR BCLKT SSC CK RE 11 2 PDI MCLK 0 PCM IN Master Tx Slave Rx MIR TC1130 Figure 5 Typical connection of the MC145481 codec to the TC1130 Application Note 14 V 1 0 2005 01 Infineon Aaroa technologies PCM Codec Connection to TC1130 SW Description 4 SW Description To connect a PCM codec to the TC1130 the Serial Synchronous Channel peripheral is used SSC This peripheral is not meant for connecting a PCM codec and some extra software must be added to it to handle this type of connection In this case the internal TC1130 DMA controller is used to be able to support the timing constraints of a PCM stream This chapter explains how the SSC and DMA peripherals are configured for PCM operation and shows a practical implementation of it 4 1 SW Arch
59. r Reserved read as 0 should be written with 0 Application Note 58 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 SW Description SSCO_FDR Value 0000 43FFyJ SSCO Fractional Divider Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIS EN SUS SUS CLK HW REQ ACK RESULT rwh rw rh rh r rh i 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM sc SM 0 STEP rw rw w r a Field Bits Typ Description STEP 9 0 rw Step Value Ox3FF FDR 1023 Fractional Clock Divider not used SM 11 rw Suspend Mode 0 Granted Suspend Mode SC 13 12 rw Suspend Control 00 DM 15 14 rw Divider Mode 01 Normal Divider Mode RESULT 25 16 irh Result Value SUSACK 28 rh Suspend Mode Acknowledge SUSREQ 29 rh Suspend Mode Request ENHW 30 rw Enable Hardware Clock Control 0 Hardware Control Disabled DISCLK 31 rwh Disable Clock 0 Clock Enabled 0 10 r Reserved read as 0 should be written with 0 27 26 Here the SSC clock is setup for 73 728 MHz Application Note 59 V 1 0 2005 01 _ Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description SSC0_BR Value 00000011 SSCO Clock Control Register Reset value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
60. real PCM Codec interface in TC1130 the CPU load would be the same as you would receive the same interrupt when something has been sent out Here the load will not be on the CPU side but on the FPI bus side Indeed you need each time a word was sent out to reload the Slave Select Output and Transmit Buffer registers This is done using DMA which means that it needs to get access to the FPIO bus and especially EBU as the data might be in external memory for 2 bus cycles and more if the data is data is in SDRAM Then DMA will get access to FPI1 bus to put data in the SSC registers For more details about FPI busses and DMA please refer to the System User s Manual chapter 17 1 5 and 18 4 You also need another FPIO bus cycle to write the received data back to the memory In total the FPIO bus is used for 3 bus cycles here cycle means a read or a write this could be more than one CPU cycle For all configuration the CPU is assumed to be running at 147 456 MHz with an external 12 288 Mhz crystal The FPI bus and peripherals running at half the CPU frequency 73 728 MHz 4 2 1 Configuration The SSC needs to be configured as follow Using normal clock divider setup for 73 728 MHz internal module clock Master mode 8 bits operation with LSB first depends on codec Leading clock edge set to low to high transition and shift data on leading edge depends on codec receive and transmit FIFOs disabled Baudrate set
61. the representation of a signal by a series of digital pulses firstly by sampling the signal quantizing it and then encoding it The PCM signal itself is a succession of discrete numerically encoded binary values derived from digitizing the analog signal Initially used for digitized speech the PCM later became the first step towards TDMA hierarchies The specification of PCM is detailed in the standard of ITU T G 711 AMPLITUDE ANALOGUE SIGNAL PULSE AMPLITUDE MODULATED SIGNAL Figure 1 Pulse amplitude modulation signal The amplitude modulated pulses are quantized by assigning integral values in a specific range to sample instances Each value is then coded into an 8 bit binary equivalent with the eighth bit representing sign The binary digits are then transformed into a digital signal using digital to digital encoding techniques Differential pulse code modulation delta modulation and adaptive delta modulation a more advanced version of delta modulation are the improved categories of pulse code modulation In audio applications the digital information is transferred usually as a PCM or IIS stream The IIS standard which is also a serial synchronous communication interface is used more in high end applications where high data rates and higher number of bits in quantization as compared to PCM are needed This standard interface is available on dedicated audio processing chips and addresses a specific market For voice
62. tion Note According to the test program loopback you can check than one frame later the output is the same as the input data shown here ra a o Mt ttttoo r 6 164 2 0027 Sngl Di_ STOP 1 Frm L I I 2Frm R_ I I I ajo out i Li 4 0 In t1 485 0ns t2 3 000ns At 488 0ns 1 At 2 049MHz Figure 36 Measured Signals Full Frame Application Note 53 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description On this picture you can see more than one frame you can see that they are coming every 8 kHz Note The noise on the Input signal comes because the line is high impedance therefore the logic analyzer is a bit lost 2 CK an wane anon Mt 744 DO 95 08 50 087 3ngl14D4 STOP 1 Frm Li 2 Frm Ri 3 D out i 4 0 In i 2 A u 3 ti 125 0us t2 0 000 s t 125 0us ir t 8 000kHz Figure 37 Measured Signals Multiple Frames As you can see the interface to the Audio PCM Codec is working quite fine without any CPU Load This is a real advantage Also this solution is quite flexible as you can connect a vvide variety of codecs mono stereo This solution can also be easily adapted to support higher precision codecs using 16 bits data for example You can also handle more than 1 stereo codec for example two stereo channels is not a problem there are a maximum of 8 SLSO pins 4 2 4 Register su
63. transmit output MAS TG FZ Figure 15 SSCO Pin Selection Tab Application Note 28 V 1 0 2005 01 AP32072 PCM Codec Connection to TC1130 technologies SVV Description In Slave Select Pins Tab Enable SLSO1 and SLSO2 you can also use other pins for chip select however those are easy as they are located on the same connector on the Triboard xi Jes 60 Module Clock Pin Selection Slave Select Pins Slave Select Control FIFO Baud Rate Interrupts Functia gt r Slave Select Output Pins 7 SLSO0 for SSCO Module PO 6 IM SLSO1 for SSCO Module P1 11 J SLSD3 for SSCO Module P2 12 J SLSD4 for SSCO Module P2 14 I SLSO5 for SSCO Module P3 7 I SLSO6 for SSCO Module P3 9 J SLSO7 for SSCO Module P3 11 r Slave Select Input Pins FP SLSIO for SSO Module P1 15 Figure 16 SSCO Slave Select Pins Tab Application Note 29 V 1 0 2005 01 Infineon A anra technologies PCM Codec Connection to TC1130 SW Description In Slave Select Tab Set SLSO1 and SLSO2 pins to be High active High Speed Synchronous Serial Interface SSCO zi cd M E mi E m al Figure 17 SSCO Slave Select Tab Application Note 30 V 1 0 2005 01 e Infineon ir technologies PCM Codec Connection to TC1130 SW Description In Baud Rate Tab Set the baudrate to 2 048 MBauds the reload value s
64. ule Kernel Multi CAN CAN_INT_O15 SSC1 Clock Generation Clock Control Fractional Divider Baud Rate Register Register Generator N SSC1_CLC E SSC1_FDR SSC1_BR SSC1 Module Kernel SSCClockGen Figure 2 2 SCC Clock Generation Chain When the fractional divider operates in a fractional divider mode it introduces a jitter in the output frequency The edges of the output signal of the fractional divider can jitter with maximum one period of the fractional dividers input frequency fsys On the average from the longer time period perspective the fractional divider always produces the required frequency but with a considerable period jitter When a jitter free operation is needed the simplest solution is not to use the fractional frequency divider in the Application Note 10 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 Introduction fractional divider mode On the ot her hand when the complete divisor is a relatively big number then the frequency jitter relative error is in a single digit percent range The operation of the SSC will not be affected by this jitter because it is a synchronous interface that drives out its own clock but if the sampling frequency of the codec depends on this SSC frequency then some additional noise will be introduced Application Note 11 V 1 0 2005 01 Infin n AP32072 Infineon PCM Codec Connection to TC1130 HW Descripti
65. upt Control 10 Interrupt is generated each time TCOUNT reaches IRDV WRPP 7 4 rw Wrap Pointer 0x0 Not Used INTP 11 8 irw Interrupt Pointer 0x0 Interrupts go to Interrupt Node O IRDV 15 12 rw Interrupt Raise Detect Value OxF Interrupt generated after 15 transfers 0 31 16 Reserved read as 0 should be written with 0 Application Note 76 V 1 0 2005 01 _ Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description DMA_SADR00 Value 2222722224 DMA Channel 00 Source Address Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SADR 1 1 rwh 1 1 1 1 1 Field Bits Typ Description SADR 31 0 rwh Source Start Address 0x Address set to Transmit_Slots address DMA DADROO Value FO10 01204 DMA Channel 00 Destination Address Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DADR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DADR rwh Application Note 77 V 1 0 2005 01 _ Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description Field Bits Typ Description DADR 31 0 rw Destination Start Address 0xF0100120 Address set to SSCO Transmit Buffer address DMA_ADRCROO Value 00000708 DMA Channel 00 Address Control Register Reset value 00
66. upt Pointer 0x0 Not used IRDV 15 12 rw Interrupt Raise Detect Value 0x0 Not used 0 31 16 r Reserved read as 0 should be written with O Application Note 80 V 1 0 2005 01 _ Infineon technologies AP32072 PCM Codec Connection to TC1130 DMA_SADRO1 DMA Channel 01 Source Address Register SW Description Value F010 0124 Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SADR 1 1 W 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SADR 1 1 TWR 1 1 1 L 1 Field Bits Typ Description SADR 31 0 rwh Source Start Address 0xF0100124 Address set to SSCO Receive Buffer address DMA DADRO1 IValue 27222 2222 DMA Channel 01 Destination Address Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DADR l l l l l i 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DADR l i l l l l l Application Note 81 V 1 0 2005 01 _ Infin n AP32072 Infineon PCM Codec Connection to TC1130 SW Description Field Bits Typ Description DADR 31 0 w Destination Start Address DMA ADRCRO1 Value 0000 7080 DMA Channel 01 Address Control Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SHCT z 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBL
67. w rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN AEN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Application Note 87 V 1 0 2005 01 _ Infineon technologies AP32072 PCM Codec Connection to TC1130 SW Description Field Bits Typ Description AENx rw Read Enable 0x01402000 Enable Read for EBU External Space EBU and SSCO address ranges Note For more details refer to Table 17 4 of the System User s Manual DMA_MEOARR Value OOFF FF00y DMA Move Engine 0 Access Range Register Reset value 0000 0000y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIZE3 SLICE3 SIZE2 SLICE2 l w l l FT 1 1 l FT 1 1 1 rw l 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE1 SLICE1 SIZEO SLICEO L TW ji 1 FT 1 1 L ET 1 1 L rw 1 1 Field Bits Typ Description SLICEO 4 0 rw Address Slice x x 0 1 2 3 SLICE1 12 8 0x00 Enable access to internal RAM SLICE2 20 16 Ox1F SLICE3 Ox1F 28 24 0x00 SIZEO 7 5 rw Address Size Slice x x 0 1 2 3 SIZE1 15 13 0x0 SIZE2 i 0x7 SIZE3 23 21 0x7 0x0 31 29 Note For more details please refer to chapter 17 3 1 2 of the System User s Manual Application Note 88
68. x00000000 0x00000000 SSCO uses MRSTA L MTSRA and SCLKA pins P1_ALTSEL 0xF0000D44 OxFFFFD700 0x00000000 Setup P1 13 and P1 11 0 as Outputs from SSCO module for SLSO2 and SLSO1 P1_ALTSEL 0xF0000D48 OxFFFFD700 0x00002800 4 P1_DIR 0xF0000D18 OxFFFFD700 0x00002800 P2_ALTSEL 0xF0000E44 OxFFFFFFE7 0x00000018 Setup P2 4 and P2 3 as 0 Outputs from SSCO module for SCLKO and MTSRO P2_ALTSEL 0xF0000E48 OxFFFFFFE7 0x00000000 1 P2_DIR OxFOOOOE18 OxFFFFFFE7 0x00000018 Application Note 55 V 1 0 2005 01 Infineon technologies AP32072 PCM Codec Connection to TC1130 SW Description Table 1 Register Overview Register Address Mask Value Comment DMA CLC 0xF0003C00 0x00000000 0x00000000 Enable DMA Module DMA_EER 0xF0003C20 OxFFFFFFFF 0x00000000 Nothing is changed here Depends on your application DMA_CHCR 0xF0003C84 0x00000000 0x00504020 Setup DMA Channel 00 00 for 32 bits 1 Move Triggered by SSCO 0 TIR DMA CHIC 0xF0003C88 0x00000000 0x0000F008 Setup to generate an ROO interrupt on Node 0 each time Channel 0 reaches TCOUNT 15 DMA SADR 0xF0003C90 0x00000000 0x Setup DMA Channel 00 00 Source Address to Transmit_Slots array DMA DADR 0xF0003C94 0x00000000 0xF0100120 Setup DMA Channel 00 00 Destination Address to SSCO Transmit Buffer Register DMA_ADRC 0xF0003C8C 0x00000000 0x00000708
69. xample is based on the following setup CON PH CON PO 1 SSC_APP Figure 2 1 SSC Operation Overview 2 3 The Clock Generation Audio application normally requires precise clock For example in order to work exactly with the frequency of 2 048MHZ it is needed that the PLL generates a frequency that is a whole number multiple of 2 048 MHz Going backwards the oscillator crystal should be chosen in such a way that when multiplied with the PLL factor the before mentioned requirement of creating the multiple of 2 048MHz is satisfied Application Note 9 V 1 0 2005 01 Infineon APARTA technologies PCM Codec Connection to TC1130 Introduction The SSC frequency generation chain starts with the system frequency fsys This frequency than goes through a fractional divider than through the baud rate generator divider The fractional divider can be used in normal mode that means divide through n mode and fractional mode or multiply with n 1024 mode where 0 lt n lt 1024 The output frequency of the fractional divider fsscx than goes through the baud rate generator that is a standard divide with n frequency divider fsys Baud ratessc 2 x BR BR_VALUE 1 x 1024 FDR STEP Baud rategsc 2 x BR BR_VALUE 1 x 1024 FDR STEP 0 1023 SSCO Clock Generation Clock Control Fractional Divider Baud Rate Register Register Generator il SSCO CLC PI SSCO FDR Sssco BR SSCO Mod

PCM Codec Connection to TC1130

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