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1. ide EM773 Bus Energy metering IC up to 32 kB flash and 8 kB SRAM Rev 2 3 January 2012 Product data sheet 1 General description The EM773 is an ARM Cortex M0 based low cost 32 bit energy metering IC designed for 8 16 bit smart metering applications The EM773 offers programmability and on chip metrology functionality combined with a low power simple instruction set and memory addressing with reduced code size compared to existing 8 16 bit architectures The EM773 operates at CPU frequencies of up to 48 MHz The peripheral complement of the EM773 includes up to 32 kB of flash memory up to 8 kB of data memory one Fast mode Plus C bus interface one RS 485 EIA 485 UART one SPI interface with SSP features three general purpose counter timers up to 25 general purpose I O pins and a metrology engine for energy measurement 2 Features and benefits E System ARM Cortex M0 processor running at frequencies of up to 48 MHz ARM Cortex M0 built in Nested Vectored Interrupt Controller NVIC Serial Wire Debug System tick timer E Memory 32 kB on chip flash programming memory 8kB SRAM In System Programming ISP and In Application Programming IAP via on chip bootloader software E Digital peripherals Up to 25 General Purpose I O GPIO pins with configurable pull up pull down resistors and a configurable open drain mode GPIO pins can be used as edge and lev
2. One capture channel per timer that can take a snapshot of the timer value when an input signal transitions A capture event may also generate an interrupt Four match registers per timer that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match 7 13 System tick timer The ARM Cortex M0 includes a system tick timer SYSTICK that is intended to generate a dedicated SYSTICK exception at a fixed time interval typically 10 ms 7 14 7 14 1 EM773 Windowed WatchDog Timer The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window Features Internally resets chip if not periodically reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Enabled by software but requires a hardware reset or a watchdog reset interrupt to be disabled Incorrect feed sequence causes reset or interrupt if enabled Flag to indicate watc
3. 002aag726 EM773 IRC CLOCK GENERATION TEST DEBUG POWER CONTROL CLKOUT INTERFACE SYSTEM FUNCTIONS ARM clocks and CORTEX MO controls ROM system bus 8 kB slave U slave U slave U HIGH SPEED a GPIO ports 3 AHB LITE BUS slave AHB TO APB BRIDGE a RXD _LOWGAIN RD UART K METROLOGY ENGINE _HIGHGAIN DTR CTS RTS VOLTAGE SCKO SSELO CT32B0_MAT 2 0 7 sro MISOO MOSIO 32 bit COUNTER TIMER 0 lt CT32B0_CAPO SCL 2C CT32B1_MAT 3 0 32 bit COUNTER TIMER 1 M PoBsus oO DA EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 4 of 51 NXP Semiconductors EM773 6 Pinning information Energy metering IC 6 1 Pinning 5 N Y EET lt ic Ss 2 z 9 S Db o oo T y aaa Se Pe P S O Q O eu qa a 2 vo x MSIE p E Cie 9 Q N 6 a FO _ a ml ea al aul a terminal 1 oo 222 eS index area CIGIGIGIGISIOIS PIO2_0 DTR 24 R PIO1_2 CT32B1_MAT1 RESET PIO0_0 3 R PIO1_1 CT32B1_MATO PIOO_1 CLKOUT CT32B0_MAT2 2 VOLTAGE XTALIN 1 _HIGHGAIN XTALOUT 0 _LOWGAIN Voo L6 9 SWCLK PIO0_10 SCKO CT16B0_MAT2 PIO1_8 48 PIOO_9 MOSI0 CT16B0_MAT1 PIO0_2 SSELO CT16B0_CAPO GZ PIO0_8 MISO0 CT16B0_MATO AA H d O t wD OJA IO A Ioi E 8 D Q 5 8 8 9 is 002aag727 s a S o ome gs2 aoa x n Fig 2 Pin configurat
4. 1 5Vpp Tj lt 125 C Tstg storage temperature non operating 41 65 150 C Tjmax maximum junction temperature 150 C Ptot pack total power dissipation per package based on package 1 5 Ww heat transfer not device power consumption Vesp electrostatic discharge voltage human body B 6500 6500 V model all pins 1 The following applies to the limiting values a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 2 Including voltage on outputs in 3 state mode 3 The peak current is limited to 25 times the corresponding maximum current 4 The maximum non operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime Please refer to the JEDEC spec J STD 033B 1 for further details 5 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 KQ series resistor EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 20 of 51 NXP Semicon
5. 1 8 V lt Vpp lt 2 5 V lon 12 mA 2 0 V lt Vpp lt 3 6 V loL 4 mA 1 8 V lt Voo lt 2 0 V lol 3 mA VoH Vpop 0 4 V 2 5 V lt Vpp lt 3 6 V 1 8 V lt Vpp lt 2 5 V 14 14 11 12 13 10 15 10 0 7Vpp 0 4 Vpop 0 4 Vpop 0 4 20 12 All information provided in this document is subject to legal disclaimers Typ 0 5 0 5 0 5 Max Unit mA mA mA mA 45 mA 50 mA 150 uA 85 uA 85 uA 0 uA 10 nA 10 nA 10 nA 5 0 V Vpp V V 0 3Vpp V V V V 0 4 V 0 4 V mA mA NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 22 of 51 NXP Semiconductors EM773 Energy metering IC Table 4 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit loL LOW level output VoL 0 4 V 4 mA current 2 0 V lt Vpop lt 3 6 V 1 8 V lt Vpp lt 2 0 V 3 mA loLs LOW level short circuit VoL Vpp Ha 50 mA output current log pull down current Vi 5V 10 50 150 uA lou pull up current V 0V 15 50 85 uA 2 0 V lt Vpp lt 3 6 V 1 8 V lt Vpp lt 2 0 V 10 50 85 uA Vpp lt Vi lt 5V 0 0 0 uA 1 C bus pins PIO0_4 and PIO0_5 Vin HIGH level input 0 7Vpp V voltage Vil LOW level input voltage 0 3Vpp V Vhys hysteresis voltage 0 05Vpp V loL LOW level output VoL 0 4 V I C bus pins 3 5
6. i 0 1 0 05 0 05 0 1 min 0 00 0 18 49 345 49 3 45 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included hvgfn33f_po Outline References European version JEDEC JEITA projection HOH MO 220 E46 11 10 17 Fig 26 Package outline HVQFN33 5x5 Issue date EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 44 of 51 NXP Semiconductors EM773 Energy metering IC HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals body 7 x 7 x 0 85 mm terminal 1 index area detail X terminal 1 index area Dimensions Unit A t b DM Dh EC Ep e amp e2 L y1 max 1 00 0 05 0 35 7 1 4 85 7 1 4 85 0 75 mm nom 0 85 0 02 0 28 0 2 7 0 4 70 7 0 4 70 0 65 4 55 4 55 0 60 0 1 0 05 0 08 0 1 min 0 80 0 00 0 23 6 9 4 55 6 9 4 55 0 45 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included hvgfn33_po Outline References European version JEDEC JEITA projection 09 03 4 7 E 09 03 23 Issue date Fig 27 Package outline HVQFN33 7x7 EM773 All information provided in th
7. logic state input 0l PIO1_11 27 no 1 O I PU PIO1_11 General purpose digital input output pin PIO2_0 0 Port 2 Port 2 is a 12 bit I O port with individual direction and function controls for each bit The operation of port 2 pins depends on the function selected through the IOCONFIG register block Pins PlO2_1 to PlIO2_11 are not available PIO2_0 DTR 113 no 1 O LPU PIO2_0 General purpose digital input output pin O DTR Data Terminal Ready output for UART PIO3_0 to PIO3 5 no O Port 3 Port 3 is a 12 bit I O port with individual direction and function controls for each bit The operation of port 3 pins depends on the function selected through the IOCONFIG register block Pins PIO3_0 PIO3_1 PIO3_3 and PIO3_6 to PIO3_11 are not available PIO3_2 28B no 1 O LPU PIO3_2 General purpose digital input output pin PIO3_4 13 3 no O0 I PU PIO3_4 General purpose digital input output pin PIO3_5 1413 no O I PU PIO3_5 General purpose digital input output pin Vpp 6 29 3 3 V supply voltage to the internal regulator the external rail and the metrology engine XTALIN 4l6l l Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 8 V XTALOUT 516 O 3 Output from the oscillator amplifier Vss 33 Thermal pad Connect to ground 1 2 3 4 5 6 EM773 Pin state at reset for default function Input O Output PU
8. 100 ns Fast mode Plus 50 gt ns 1 See the 1 C bus specification UM10204 for details 2 Parameters are valid over operating temperature range unless otherwise specified 3 tHD DAT is the data hold time that is measured from the falling edge of SCL applies to data in transmission and the acknowledge 4 A device must internally provide a hold time of at least 300 ns for the SDA signal with respect to the Vin min of the SCL signal to bridge the undefined region of the falling edge of SCL 5 EM773 Cy total capacitance of one bus line in pF All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 36 of 51 NXP Semiconductors EM773 6 7 8 9 10 Energy metering IC The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage tr is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified tr In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing The maximum typ pat Could be 3 45 us and 0 9 us for Standard mode and Fast mode but must be less than the maximum of tvp pat OF tvp ack by a tra
9. 16 5 APB interface 200 0000 716 6 AHBLI secere ccc crysis penne amini ied 7 16 7 External interrupt inputs 7 17 Emulation and debugging 8 Limiting values 0 00 e ewes 9 Static characteristics 05 9 1 BOD static characteristics 9 2 Power consumption 9 3 Peripheral power consumption 9 4 Electrical pin characteristics 10 Dynamic characteristics 10 1 Power up ramp conditions 10 2 Flash memory 0 0 e eee eee eee 10 3 External clock 00 0000000s 10 4 Internal oscillators 05 10 5 VO PINS i 22 eer De Nake earn e bee 10 6 Ket oli 2264 ee at ea oaks PE eee ah 10 7 SPI interface 2 00 eee eee 11 Application information 5 11 1 XTAL input ananunua aaaea 11 2 XTAL Printed Circuit Board PCB layout guidelines 00 202 eee eee 11 3 Standard I O pad configuration 11 4 Reset pad configuration 11 5 ElectroMagnetic Compatibility EMC 12 Package outline 0 cece eee eee 13 Soldering s seno 822ss02esew sere ndeerees 14 Abbreviations 000 c cece eee 15 Revision history 20 cee cence eens 16 Legal information 2000 ee eens 16 1 Data sheet status 0004 16 2 Definitions 0 0000005 16 3 Disclaimers
10. 20 2 n a s 3 O n no 2 a ao ta x ra 3 D solder land Remark solder resist J solder paste deposit Z N t ise O oi v nm Q Ss Stencil thickness 0 125 mm Dimensions in mm occupied area Fig 28 Reflow soldering of the HVQFN33 package NXP B V 2012 All rights reserved All information provided in this document is subject to legal disclaimers EM773 Rev 2 3 January 2012 46 of 51 Product data sheet NXP Semiconductors EM773 14 Abbreviations Energy metering IC EM773 Table 18 Abbreviations Acronym AHB APB BOD GPIO PLL RC SPI SSI SSP TEM UART Description Advanced High performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose Input Output Phase Locked Loop Resistor Capacitor Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transverse ElectroMagnetic Universal Asynchronous Receiver Transmitter All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 47 of 51 NXP Semiconductors EM773 15 Revision history Energy metering IC Table 19 Revision history Document ID EM773 v 2 Modifications EM773 v 1 Release date 20120103 20100901 Data sheet status Change notice Supersedes Product data sheet EM77
11. Deep power down mode by using the 12 MHz IRC oscillator as the clock source This allows chip operation to resume quickly If the system oscillator or the PLL is needed by the application software will need to enable these features and wait for them to stabilize before they are used as a clock source Power control The EM773 support a variety of power control features There are three special modes of processor power reduction Sleep mode Deep sleep mode and Deep power down mode The CPU clock rate may also be controlled as needed by changing clock sources reconfiguring PLL values and or altering the CPU clock divider value This allows a trade off of power versus processing speed based on application requirements In addition a register is provided for shutting down the clocks to individual on chip peripherals allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application Selected peripherals have their own clock divider which provides even better power control All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 16 of 51 NXP Semiconductors EM773 7 15 5 1 7 15 5 2 7 15 5 3 7 15 5 4 EM773 Energy metering IC Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls
12. EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 38 of 51 NXP Semiconductors EM773 EM773 Energy metering IC Tey clk a tok ToL SCK CPOL 0 SCK CPOL 1 lt _ _ _ _ _ MOSI DATA VALID tv Q MISO DATA VALID MOSI MISO DATA VALID DATA VALID DATA VALID Fig 21 SPI slave timing in SPI mode DATA VALID lt tha CPHA 1 CPHA 0 002aae830 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 39 of 51 NXP Semiconductors EM773 Energy metering IC 11 Application information 11 1 XTAL input EM773 The input voltage to the on chip oscillators is limited to 1 8 V If the oscillator is driven by a clock in slave mode it is recommended that the input be coupled through a capacitor with Ci 100 pF To limit the input voltage to the specified range choose an additional capacitor to ground Cy which attenuates the input voltage by a factor C C Cg In slave mode a minimum of 200 mV RMS is needed 5 100pF F Fig 22 Slave mode operation of the on chip oscillator 002aag730 In slave mode the input clock signal should be coupled by means of a capacitor
13. Energy metering IC order to keep the noise coupled in via the PCB as small as possible Also parasitics should stay as small as possible Values of Cy and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout Standard I O pad configuration Figure 24 shows the possible pin modes for standard I O pins with analog input function e Digital output driver e Digital input Pull up enabled disabled e Digital input Pull down enabled disabled e Digital input Repeater mode enabled disabled e Analog input pin configured as digital output driver pin configured as digital input pin configured as analog input A output enable output 48 repeater mode enable data input analog input pull up enable pull down enable VDD IE weak pull up Lro weak pull down select analog input i Fig 24 Standard I O pad configuration Ba 002aat304 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 42 of 51 NXP Semiconductors EM773 Energy metering IC 11 4 Reset pad configuration VDD VDD Rpu i ESD 20 ns RC igi reset Gt guitch FILTER lt i AN Vss 002aaf274 Fig 25 Reset pad configuration 11 5 ElectroMagnetic Compatibility E
14. connected to the NVIC but may have several interrupt flags Individual interrupt flags may also represent more than one interrupt source Any GPIO pin total of up to 25 pins regardless of the selected function can be programmed to generate an interrupt on a level or rising edge or falling edge or both IOCONFIG block The IOCONFIG block allows selected pins of the microcontroller to have more than one function Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt s being enabled Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined Fast general purpose parallel I O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers Pins may be dynamically configured as inputs or outputs Multiple outputs can be set or cleared in one write operation The EM773 uses accelerated GPIO functions e GPIO registers are a dedicated AHB peripheral so that the fastest possible I O timing can be achieved e Entire port value can be written in one instruction Additionally any GPIO pin total of up to 25 pins providing a digital function can be programmed to generate an interrupt on a level a rising or falling edge or both Features e Bit level port registers allow a
15. internal pull up enabled pins pulled up to full Vpp level IA inactive no pull up down enabled See Figure 25 for the reset pad configuration RESET functionality is not available in Deep power down mode Use the WAKEUP pin to reset the chip and wake up from Deep power down mode An external pull up resistor is required on this pin for the Deep power down mode Pin is 5 V tolerant 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 24 l2C bus pads compliant with the 1 C bus specification for 12C standard mode and 12C Fast mode Plus 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a analog input digital section of the pad is disabled and the pin is not 5 V tolerant see Figure 24 When the system oscillator is not used connect XTALIN and XTALOUT as follows XTALIN can be left floating or can be grounded grounding is preferred to reduce susceptibility to noise XTALOUT should be left floating All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 8 of 51 NXP Semiconductors EM773 Energy metering IC 7 Functional description EM773 7 1 7 2 7 3 7 4 ARM Cortex M0 processor The ARM Cortex M0 is a general purpos
16. is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 12 of 51 NXP Semiconductors EM773 7 10 1 7 11 7 11 1 7 12 7 12 1 EM773 Energy metering IC receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The 12C is a multi master bus and can be controlled by more than one bus master connected to it Features e The I C interface is a standard C bus compliant interface with open drain pins The l2C bus interface also supports Fast mode Plus with bit rates up to 1 Mbit s e Easy to configure as master slave or master slave e Programmable clocks allow versatile rate control e Bidirectional data transfer between masters and slaves e Multi master bus no central master e Arbitration between simultaneously transmitting masters without corruption of serial data on the bus e Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer e The l C bus can be used for test and diagnostic purposes e The I2C bus controller supports multiple address recognition and a bus monitor mode Metrology engine The EM773 contains a metrology engine designed to collect voltage and current inputs to calculate the active power reactive p
17. mA Conditions Vpp 3 3 V on pin PIOO_7 High drive output Typical HIGH level output voltage Voy versus HIGH level output current lop Fig 11 2aaf01 60 002aaf019 loL T 85 C mA 25 C 40 C 40 20 0 0 0 2 0 4 0 6 VoL V Conditions Vpp 3 3 V on pins PIOO_4 and PIOO_5 I2C bus pins high current sink Typical LOW level output current lo versus LOW level output voltage VoL All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 30 of 51 NXP Semiconductors EM773 EM773 Energy metering IC 15 002aae991 lot T 85 C mA 25 C 40 C 10 5 0 0 0 2 0 4 0 6 VoL V Conditions Vpp 3 3 V standard port pins and PIOO_7 Fig 12 Typical LOW level output current Io versus LOW level output voltage VoL 002aae992 3 6 24 loH mA Conditions Vpp 3 3 V standard port pins Fig 13 Typical HIGH level output voltage Voy versus HIGH level output source current loH All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 31 of 51 NXP Semiconductors EM773 Energy metering IC 002aae
18. of 100 pF Figure 22 with an amplitude between 200 mV RMS and 1000 mV RMS This corresponds to a square wave signal with a signal swing of between 280 mV and 1 4 V The XTALOUT pin in this configuration can be left unconnected External components and models used in oscillation mode are shown in Figure 23 and in Table 15 and Table 16 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cy and Cys need to be connected externally in case of fundamental mode oscillation the fundamental frequency is represented by L C and Rs Capacitance Cp in Figure 23 represents the parallel package capacitance and should not be larger than 7 pF Parameters Fogc CL Rs and Cp are supplied by the crystal manufacturer see Table 15 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 40 of 51 NXP Semiconductors EM773 EM773 Energy metering IC EM773 T XTALIN XTALOUT 4 Se GE Cp XTAL Rs CxX1 CX2 OO 002aag731 Fig 23 Oscillator modes and models oscillation mode of operation and external crystal model used for Cx1 Cx2 evaluation Table 15 Recommended values for Cx1 Cx2 in oscillation mode crystal and external components parameters low frequency mode Fundamental oscillation Crystal load Maximum
19. output pin CT32B1_MAT3 WAKEUP o CT32B1_MAT3 Match output 3 for 32 bit timer 1 WAKEUP Deep power down mode wake up pin with 20 ns glitch filter This pin must be pulled HIGH externally to enter Deep power down mode and pulled LOW to exit Deep power down mode A LOW going pulse as short as 50 ns wakes up the part PIO1_5 RTS 308 no 1 O LPU PIO1_5 General purpose digital input output pin CT32B0_CAPO O RTS Request To Send output for UART CT32B0_CAP0 Capture input 0 for 32 bit timer 0 PIO1_6 RXD 31B no 1 O LPU PIO1_6 General purpose digital input output pin CT32B0_MATO RXD Receiver input for UART O CT32B0_MATO Match output 0 for 32 bit timer 0 PIO1_7 TXD 32 3 no 1 0 LPU PIO1_7 General purpose digital input output pin CT32B0_MAT1 O TXD Transmitter output for UART O CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIO1_8 78 no 1 0 LPU PIO1_8 General purpose digital input output pin PIO1_9 1281 no 1 O LPU PIO1_9 General purpose digital input output pin LOWGAIN 20 no PU I_LOWGAIN Low gain current input for metrology EM773 All information provided in this document is subject to legal disclaimers engine NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 7 of 51 NXP Semiconductors EM773 Energy metering IC Table 2 EM773 pin description table continued Symbol Pin Start Type Reset Description
20. short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 16 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data shee
21. well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 17 Contact information Energy metering IC whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 16 4 Trademarks Notice All referenced brands product names service names and trademark
22. 000000 eee eeee 16 4 Trademarks 2000 2 eee eee 17 Contact information 0 2 00 18 Contents 625 sccieee disease ceeehe ees Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2012 For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 3 January 2012 Document identifier EM773 All rights reserved
23. 0x4004 8000 17 eee 0x4004 4000 16 SPIO 0x4004 0000 reserved 154 flash controller 0x4003 C000 0 5 GB ener 0x4003 8000 reserved Ox1FFF 4000 o 0x1 FFF 0000 E i reserved e 0x1000 2000 0x4001 C000 8 kB SRAM 32 bit counter timer 1 0x4001 8000 0x1000 0000 32 bit counter timer 0 0x4001 4000 reserved 0x4001 0000 reserved 16 bit counter timer 0 0x4000 C000 0x4000 8000 0x4000 4000 0x0000 8000 0x4000 0000 32 kB on chip flash 0x0000 00CO ive i t ti ees 0GB 0x0000 0000 002aag728 Fig 3 EM773 memory map 7 5 Nested Vectored Interrupt Controller NVIC The Nested Vectored Interrupt Controller NVIC is an integral part of the Cortex M0 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 7 5 1 Features e Controls system exceptions and peripheral interrupts e Inthe EM773 the NVIC supports 32 vectored interrupts including up to 13 inputs to the start logic from individual GPIO pins EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 10 of 51 NXP Semiconductors EM773 7 5 2 7 6 7 7 7 7 1 EM773 Energy metering IC e Four programmable interrupt priority levels with hardware priority level masking e Software interrupt generation Interrupt sources Each peripheral device has one interrupt line
24. 12 27 of 51 NXP Semiconductors EM773 EM773 Energy metering IC IDD HA 002aaf977 5 5 4 5 3 5 2 5 40 15 10 35 60 85 temperature C Conditions BOD disabled all oscillators and analog blocks disabled in the PDSLEEPCFG register PDSLEEPCFG 0x0000 18FF Fig 8 Deep sleep mode Typical supply current lpp versus temperature for different supply voltages Vpp 0 8 002aaf978 IDD uA 0 6 0 4 0 2 0 40 15 10 35 60 85 temperature C Fig 9 Deep power down mode Typical supply current lpp versus temperature for different supply voltages Vpp All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 28 of 51 NXP Semiconductors EM773 9 3 Peripheral power consumption Energy metering IC The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG for analog blocks registers All other blocks are disabled in both registers and no code is executed Measured on a typical sample at Tamp 25 C Unless noted otherwise the system oscillator and PLL are running in both measurements The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz Tab
25. 18FF 9 WAKEUP pin pulled HIGH externally 10 Low current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles 11 Including voltage on outputs in 3 state mode 12 Vpp supply voltage must be present 13 3 state outputs go into 3 state mode in Deep power down mode 14 Allowed as long as the current limit does not exceed the maximum current allowed by the device 15 To Vss EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 24 of 51 NXP Semiconductors EM773 EM773 9 1 BOD static characteristics Energy metering IC Table 5 BOD static characteristics Tamb 25 C Symbol Parameter Conditions Min Typ Max Unit Vin threshold voltage interrupt level 0 assertion 1 65 V de assertion 1 80 V interrupt level 1 assertion 2 22 V de assertion 2 35 V interrupt level 2 assertion 2 52 V de assertion 2 66 V interrupt level 3 assertion 2 80 V de assertion 2 90 V reset level 0 assertion 1 46 V de assertion 1 63 V reset level 1 assertion 2 06 V de assertion 2 15 V reset level 2 assertion 2 35 V de assertion 2 43 V reset level 3 assertion 2 63 V de assertion 2 71 V 1 Interrupt levels are selected by writing the level value to the BOD control register BODCTRL see EM773 user manual 9 2 Power consumption Power measuremen
26. 3 v 1 Updated Section 7 7 1 Features Updated Section 7 14 Windowed WatchDog Timer Updated Section 7 15 2 System PLL Added Section 7 15 5 1 Power profiles Updated Section 7 15 5 4 Deep power down mode Updated Section 7 16 2 Reset Updated Section 7 16 7 External interrupt inputs Updated Section 9 2 Power consumption Added Section 9 3 Peripheral power consumption Updated Section 10 Dynamic characteristics Added Section 11 5 ElectroMagnetic Compatibility EMC Table 2 EM773 pin description table Updated descriptions for WAKEUP and RESET Updated Table note 1 Table note 2 and Table note 5 Table 3 Limiting values Added non operating to T stg conditions Updated Table note 4 Table 4 Static characteristics Added updated power consumption information Updated l C bus Vhys typical to 0 05Vpp Updated Table note 6 and Table note 8 Added Table note 10 Product data sheet EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 48 of 51 NXP Semiconductors EM773 16 Legal information Energy metering IC 16 1 Data sheet status Document status I 2 Product status Definition Objective
27. 988 Vi V Conditions Vpp 3 3 V standard port pins Fig 14 Typical pull up current Ipu versus input voltage V 2 80 002aae989 lod T 85 C P 25 C HA 40 C 60 40 20 0 0 1 2 3 4 5 Vi V Conditions Vpp 3 3 V standard port pins Fig 15 Typical pull down current lpa versus input voltage V EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 32 of 51 NXP Semiconductors EM773 Energy metering IC 10 Dynamic characteristics 10 1 Power up ramp conditions Table 7 Power up characteristics Tamb 40 C to 85 C Symbol Parameter Conditions Min Typ Max Unit tr rise time att t4 0 lt Vi lt 400 mV O o 500 ms twait wait time 2 12 us Vi input voltage att t on pin Vpp 0 400 mV 1 See Figure 16 2 The wait time specifies the time the power supply must be at levels below 400 mV before ramping up yp VDD 400 mV e m twait 002aag001 Condition 0 lt V lt 400 mV at start of power up t t4 Fig 16 Power up ramp 10 2 Flash memory Table 8 Flash characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Nend
28. MC Radiated emission measurements according to the IEC61967 2 standard using the TEM cell method are shown in Table 17 Table 17 ElectroMagnetic Compatibility EMC TEM cell method Voo 3 3 V Tamp 25 CC Parameter Frequency band System clock Unit 12 MHz 24 MHz 48 MHz Input clock IRC 12 MHz maximum 150 kHz 30 MHz 7 5 7 dBuV peak level 30 MHz 150 MHz 2 1 10 dBuV 150 MHz 1 GHz 4 8 16 dBuV IEC level O N M Input clock crystal oscillator 12 MHz maximum 150 kHz 30 MHz 7 7 7 dBuV peak level 30 MHz 150 MHz 2 1 8 dBuV 150 MHz 1 GHz 4 7 14 dBuV IEC level O N M 1 IEC levels refer to Appendix D in the IEC61967 2 Specification EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 43 of 51 NXP Semiconductors EM773 Energy metering IC 12 Package outline HVQFN33 plastic thermal enhanced very thin quad flat package no leads 32 terminals body 5 x 5 x 0 85 mm terminal 1 index area detail X terminal 1 index area Dimensions mm are the original dimensions Unit A0 AY b c DI Dha EC Ep max 0 05 0 30 6 1 375 5 1 3 75 i mm nom 0 85 0 2
29. Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 49 of 51 NXP Semiconductors EM773 Export control This document as
30. SPIO PERIPHERAL SPIO CLOCK DIVIDER main clock UART PERIPHERAL CLOCK DIVIDER UART IRC oscillator WDT CLOCK MAINCLKSEL f DIVIDER WDT main clock select watchdog oscillator WDTUEN SYSTEM PLL WDT clock update enable IRC oscillator system oscillator CLKOUT PIN CLOCK CLKOUT pi pin e Castes watchdog oscillator DIVIDER CLKOUTUEN CLKOUT update enable 002aag729 EM773 clock generation block diagram 7 15 1 1 EM773 Internal RC oscillator The IRC may be used as the clock source for the WDT and or as the clock that drives the PLL and subsequently the CPU The nominal IRC frequency is 12 MHz The IRC is trimmed to 1 accuracy over the entire voltage and temperature range Upon power up or any chip reset the EM773 uses the IRC as the clock source Software may later switch to one of the other available clock sources All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 15 of 51 NXP Semiconductors EM773 7 15 1 2 7 15 1 3 7 15 2 7 15 3 7 15 4 7 15 5 EM773 Energy metering IC System oscillator The system oscillator can be used as the clock source for the CPU with or without using the PLL The system oscillator operates at frequencies of 1 MHz to 25 MHz This frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the system PLL Wa
31. Sleep Deep sleep and Deep power down modes Three reduced power modes Sleep Deep sleep and Deep power down Processor wake up from Deep sleep mode via a dedicated start logic using up to 13 of the functional pins Power On Reset POR Brownout detect with four separate thresholds for interrupt and forced reset m Unique device serial number for identification Single 3 3 V power supply 1 8 V to 3 6 V E Available as 33 pin HVQFN33 package 3 Applications E Smart Metering NXP B V 2012 All rights reserved 2 of 51 All information provided in this document is subject to legal disclaimers Rev 2 3 January 2012 EM773 Product data sheet NXP Semiconductors EM773 Energy metering IC 4 Ordering information Table 1 Ordering information Type number Package Name Description Version EM773FHN33 HVQFN33 HVQEFN plastic thermal enhanced very thin quad flat package no n a leads 33 terminals body 7 x 7 x 0 85 mm EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 3 of 51 NXP Semiconductors EM773 Energy metering IC 5 Block diagram SWD XTALIN XTALOUT RESET CT16B0_MAT 2 0 CT16B0_CAPO Fig 1 EM773 block diagram 16 bit COUNTER TIMER 0 gt o meore C escono NN WDT PMU
32. U PIOO_3 General purpose digital input output pin PIOO_4 SCL 10 4 yes O IA PIOO_4 General purpose digital input output pin open drain 1 O SCL l C bus open drain clock input output High current sink only if 2C Fast mode Plus is selected in the I O configuration register PIOO_5 SDA 114 yes V O IA PIO0_5 General purpose digital input output pin open drain 1 0 SDA l C bus open drain data input output High current sink only if 2C Fast mode Plus is selected in the I O configuration register PIOO_6 SCKO 15 3 yes O I PU PIO0_6 General purpose digital input output pin 1 O SCKO Serial clock for SPIO PIOO_7 CTS 168 yes 0 PU PIO0_7 General purpose digital input output pin high current output driver CTS Clear To Send input for UART PIO0_8 MISOO 178 yes 0 IPU PIO0_8 General purpose digital input output pin Geet MAT V0 MISOO Master In Slave Out for SPIO O CT16B0O_MATO Match output 0 for 16 bit timer 0 PIOO_9 MOSI0 1813 yes O I PU PIOO_9 General purpose digital input output pin CT16B0_MAT1 1 O MOSIO Master Out Slave In for SPIO O CT16B0_MAT1 Match output 1 for 16 bit timer 0 EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 6 of 51 NXP Semiconductors EM773 Energy metering IC Table 2 EM773 p
33. actory testing can be performed on the device CAUTION 7 16 5 7 16 6 7 16 7 7 17 EM773 In addition to the three CRP levels sampling of pin PIOO_1 for valid user code can be disabled For details see the EM773 user manual APB interface The APB peripherals are located on one APB bus AHBLite The AHBLite connects the CPU bus of the ARM Cortex M0 to the flash memory the main static RAM and the Boot ROM External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs In addition start logic inputs serve as external interrupts see Section 7 16 1 Emulation and debugging Debug functions are integrated into the ARM Cortex M0 Serial wire debug with four breakpoints and two watchpoints is supported All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 19 of 51 NXP Semiconductors EM773 Energy metering IC 8 Limiting values Table 3 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Vpop supply voltage core and external rail 1 8 3 6 V Vi input voltage 5 V tolerant I O 2 0 5 5 5 V pins only valid when the Vpp supply voltage is present Ipp supply current per supply pin B 100 mA Iss ground current per ground pin B 100 mA liatch I O latch up current 0 5Vpp lt Vi lt 100 mA
34. c must be configured in the system configuration block and in the NVIC before being used Reset Reset has four sources on the EM773 the RESET pin the Watchdog reset Power On Reset POR and the BrownOut Detection BOD circuit The RESET pin is a Schmitt trigger input pin Assertion of chip reset by any source once the operating voltage attains a usable level starts the IRC and initializes the flash controller A LOW going pulse as short as 50 ns resets the part When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values An external pull up resistor is required on the RESET pin if Deep power down mode is used Brownout detection The EM773 includes four levels for monitoring the voltage on the Vpp pin If this voltage falls below one of the four selected levels the BOD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt if not software can monitor the signal by reading a dedicated status register Four additional threshold levels can be selected to cause a forced reset of the chip Code security Code Read Protection CRP This feature of the EM773 allows user to enable different levels of security in the system so that a
35. ccess to the on chip flash and use of the Serial Wire Debugger SWD and In System Programming ISP can be restricted When needed CRP is invoked by programming a specific pattern into a dedicated flash location IAP commands are not affected by the CRP In addition ISP entry via the PIOO_1 pin can be disabled without enabling CRP For details see the EM773 user manual There are three levels of Code Read Protection 1 CRP1 disables access to the chip via the SWD and allows partial flash update excluding flash sector 0 using a limited set of the ISP commands This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 18 of 51 NXP Semiconductors EM773 Energy metering IC 2 CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands 3 Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP This mode effectively disables ISP override using PIOO_1 pin too It is up to the user s application to provide if needed flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via the UART If level three Code Read Protection CRP3 is selected no future f
36. crystal External load frequency Fosc capacitance C series resistance Rg capacitors Cy Cx2 1 MHz 5 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF lt 3009 39 pF 39 pF 30 pF lt 300 Q 57 pF 57 pF 5 MHz 10 MHz 10 pF lt 3009 18 pF 18 pF 20 pF lt 200 2 39 pF 39 pF 30 pF lt 1009 57 pF 57 pF 10 MHz 15 MHz 10 pF lt 1600 18 pF 18 pF 20 pF lt 600 39 pF 39 pF 15 MHz 20 MHz 10 pF lt 800 18 pF 18 pF Table 16 Recommended values for Cx1 Cx2 in oscillation mode crystal and external components parameters high frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rs capacitors Cy1 Cxo 15 MHz 20 MHz 10 pF lt 1800 18 pF 18 pF 20 pF lt 1002 39 pF 39 pF 20 MHz 25 MHz 10 pF lt 1600 18 pF 18 pF 20 pF lt 800 39 pF 39 pF XTAL Printed Circuit Board PCB layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors Cx Cx2 and Cx in case of third overtone crystal usage have a common ground plane The external components must also be connected to the ground plain Loops must be made as small as possible in All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 41 of 51 NXP Semiconductors EM773 11 3 EM773
37. de while 1 from flash all peripherals disabled in the SYSAHBCLKCTRL register SYSAHBCLKCTRL 0x1F all peripheral clocks disabled internal pull up resistors disabled BOD disabled low current mode 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled Fig 6 Active mode Typical supply current lpp versus temperature for different system clock frequencies All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 26 of 51 NXP Semiconductors EM773 Energy metering IC 6 002aaf982 IDD mA 48 MHz 2 4 36 MHz 2 24 MHz 2 2 12 MHz 0 40 15 10 35 60 85 temperature C Conditions Vpp 3 3 V sleep mode entered from flash all peripherals disabled in the SYSAHBCLKCTRL register SYSAHBCLKCTRL 0x1F all peripheral clocks disabled internal pull up resistors disabled BOD disabled low current mode 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled Fig 7 Sleep mode Typical supply current Ipp versus temperature for different system clock frequencies EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 20
38. ductors EM773 Energy metering IC 9 Static characteristics Table 4 Static characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vpp supply voltage core 1 8 3 3 3 6 V and external rail Power consumption in low current model Ipp supply current Active mode code while 1 executed from flash system clock 12 MHz ISIA 2 mA Vpp 3 3 V oL system clock 50 MHz AISI 7 mA Vbo 3 3 V Bra Sleep mode BBA 1 7 mA system clock 12 MHz Birs Vpp 3 3 V Deep sleep mode BIBIS 2 uA Vpp 3 3 V Deep power down mode l9 220 nA Vpp 3 3 V Standard port pins RESET lit LOW level input current V 0 V on chip pull up 0 5 10 nA resistor disabled la HIGH level input V Vpp on chip 0 5 10 nA current pull down resistor disabled loz OFF state output Vo 0 V Vo Vpp 0 5 10 nA current on chip pull up down resistors disabled VI input voltage pin configured to provide 102 9 5 0 V a digital function n3 Vo output voltage output active 0 Vpp V Vin HIGH level input 0 7Vpp V voltage ViL LOW level input voltage 0 3Vpp V Vhys hysteresis voltage 0 4 V VoH HIGH level output 2 0 V lt Vpp lt 3 6 V Vpop 0 4 V voltage lon 4 mA 1 8 V lt Vpp lt 2 0 V Vpop 0 4 V loH 3 MA VoL LOW level output 2 0 V lt Vpp lt 3 6 V 0 4 V voltage lol 4 mA 1 8 V lt Vpop lt 2 0 V 0 4 V lo
39. e 32 bit microprocessor which offers high performance and very low power consumption On chip flash program memory The EM773 contains 32 kB of on chip flash memory On chip SRAM The EM773 contains a total of 8 KB on chip static RAM memory Memory map The EM773 incorporates several distinct memory regions shown in the following figure Figure 3 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address remapping The AHB peripheral area is 2 megabyte in size and is divided to allow for up to 128 peripherals The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals Each peripheral of either type is allocated 16 kilobytes of space This allows simplifying the address decoding for each peripheral All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 9 of 51 NXP Semiconductors EM773 Energy metering IC EM773 AHB peripherals 0x5020 0000 4GB OxFFFF FFFF 16 127 reserved e reserved E 0x5004 0000 12 15 GPIO PIO3 0x5003 0000 pean Sl epee nna ere a eae 0x5002 0000 AHB peripherals 0x5000 0000 47 GPIOPIO1 0x5001 0000 0 3 GPIOPIOO 0x5000 0000 reserved APB peripherals 0x4008 0000 0x4008 0000 Qqocencaseseccceehe eee i 31 19 reserved x4000 0000 0x4004 C000 18 system control
40. el sensitive interrupt sources High current output driver 20 mA on one pin High current sink drivers 20 mA on two I2C bus pins in Fast mode Plus Three general purpose counter timers with a total of two capture inputs and 10 match outputs Programmable Windowed WatchDog Timer WWDT E Analog peripherals Metrology Engine for Smart Metering with two current inputs and a voltage input EM773 Energy metering IC NXP Semiconductors E Serial interfaces UART with fractional baud rate generation internal FIFO and RS 485 support One SPI controller with SSP features and with FIFO and multi protocol capabilities 2C bus interface supporting full 1 C bus specification and Fast mode Plus with a data rate of 1 Mbit s with multiple address recognition and monitor mode Clock generation 12 MHz internal RC oscillator trimmed to 1 accuracy that can optionally be used as a system clock Crystal oscillator with an operating range of 1 MHz to 25 MHz Programmable watchdog oscillator with a frequency range of 7 8 kHz to 1 8 MHz PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the system oscillator or the internal RC oscillator Clock output function with divider that can reflect the system oscillator clock IRC clock CPU clock and the Watchdog clock Power control Integrated PMU Power Management Unit to minimize power consumption during
41. eral purpose parallel O 11 Features 0 2000 eee eee 11 VART ssc2iccnetdewee bike Pee eee be a 12 F atures ccs be eee eee are Re eee ae 12 SPI serial I O controller 12 F atureS 2 2 22s 2i2ag2Gcou1 Fe Peco nee 12 l C bus serial I O controller 12 Features e ce Seca eae dn Saeed wn aed A 13 Metrology engine 13 Features 0 02 00 cece eee eee 13 General purpose external event counter timers 000000 ee eee 13 Features 00 000 eee 13 System tick timer 00055 14 Windowed WatchDog Timer 14 Features aieia ender dagen Shee adae awe 14 Clocking and power control 15 Crystal oscillators 5 15 Internal RC oscillator 15 System oscillator 00 55 16 Watchdog oscillator 16 System PLL 33 Aa Suis dak Ge date ated ed 16 Clock output 000 eee eee 16 Wake up process 20000005 16 Power control 2000 200 eee 16 Power profileS 0000 eee eae 17 Sleep mode 2 02 cece eee eee 17 Deep sleep mode 5 17 Deep power down mode 17 System control 2000000e 18 7 16 1 Start logic 0 0 2 ae E eee eee 7 16 2 PRES tes etre naak Bataan fence ig aei 7 16 3 Brownout detection 7 16 4 Code security Code Read Protection CRP 7
42. g negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof EM773 All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative pu
43. hdog reset Programmable 24 bit timer with internal prescaler Selectable time period from Tcy wDCLk x 256 x 4 to Tcy WDCLk x 224 x 4 in multiples of Tey WDCLK x 4 The Watchdog Clock WDCLK source can be selected from the IRC or the dedicated watchdog oscillator WDO This gives a wide range of potential timing choices of watchdog operation under different power conditions All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 14 of 51 EM773 Energy metering IC NXP Semiconductors 7 15 Clocking and power control 7 15 1 Crystal oscillators The EM773 includes three independent oscillators These are the system oscillator the Internal RC oscillator IRC and the Watchdog oscillator Each oscillator can be used for more than one purpose as required in a particular application Following reset the EM773 will operate from the Internal RC oscillator until switched by software This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency See Figure 4 for an overview of the EM773 clock generation IRC oscillator watchdog oscillator AHB clock 0 system SYSTEM CLOCK System clock IRC oscillator system oscillator Fig 4 AHB clocks 1 to 18 memories and peripherals SYSAHBCLKCTRL 1 18 AHB clock enable 4
44. in description table continued Symbol Pin Start Type Reset Description logic state input 0 SWCLK PIOO_10 SCKO 19 3 yes l I PU SWCLK Serial wire clock CT16B0_MAT2 O PIOO_10 General purpose digital input output pin 1 O SCKO Serial clock for SPIO O CT16B0_MAT2 Match output 2 for 16 bit timer 0 _HIGHGAIN 2115 no PU _HIGHGAIN High gain current input for metrology engine PIO1_1 to PIO1_9 O Port 1 Port 1 is a 12 bit I O port with individual PIO1_11 direction and function controls for each bit The operation of port 1 pins depends on the function selected through the IOCONFIG register block Pins PIO1_0 and PIO1_10 are not available VOLTAGE 22105 no I PU VOLTAGE Voltage input for the metrology engine R PIO1_1 235 no O LPU R Reserved Configure for an alternate function in CT32B1_MATO the IOCONFIG block 1 O PIO1_1 General purpose digital input output pin O CT32B1_MATO Match output 0 for 32 bit timer 1 R PIO1_2 2455 no PU R Reserved Configure for an alternate function in CT32B1_MAT1 the IOCONFIG block 1 O PIO1_2 General purpose digital input output pin O CT32B1_MAT1 Match output 1 for 32 bit timer 1 SWDIO PIO1_3 2515 no 1 O I PU SWDIO Serial wire debug input output C132B1_MAT2 1 0 PIO1_3 General purpose digital input output pin O CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIO1_4 26 no 0 LPU PIO1_4 General purpose digital input
45. ion HVQFN 33 package Transparent top view EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 5 of 51 NXP Semiconductors EM773 6 2 Pin description Energy metering IC Table 2 EM773 pin description table Symbol Pin Start Type Reset Description logic state input 0 PIO0_O to PIOO_10 1 0 Port 0 Port 0 is a 12 bit I O port with individual direction and function controls for each bit The operation of port 0 pins depends on the function selected through the IOCONFIG register block Pin PIOO_11 is not available RESET PIOO_0 212 yes l I PU RESET External reset input with 20 ns glitch filter A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 O PIOO_0 General purpose digital input output pin PIO0O_1 CLKOUT 313 yes 0 PU PIO0_1 General purpose digital input output pin A CT32B0_MAT2 LOW level on this pin during reset starts the ISP command handler O CLKOUT Clock out pin O CT32B0_MAT2 Match output 2 for 32 bit timer 0 PIOO_2 SSEL0 als yes 0 PU PIO0_2 General purpose digital input output pin CT16B0_CAP0 O SSELO Slave select for SPIO CT16BO_CAPO0O Capture input 0 for 16 bit timer 0 PIOO_3 93 yes O I P
46. is document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 45 of 51 EM773 Energy metering IC NXP Semiconductors 13 Soldering Footprint information for reflow soldering of HVQFN33 package 8 20 OA OID 0 30 CU 7 25 PA OA PID no 08 S 391 I Ga p BIN gt SO L ena A NO 964 I VOtWd Se 4 Ald gt wa Sto gt e OwDtot 5 10 OA 4 25 evia j W 0 65 e PAASIAAA a Z merererarerete U Re YJ Suse CN WL te SKS neces DNNN N RY QE S 1 00 SP gt SSSA lt __________p dS 02 2 4043S YS SS y NO 98 F SHA VO OLS 3015M0 VO 02 8 310 SPD E D z 3 2 85 gR g oOo zZ os o QO xe o 06 A So no oO g lt 4 5 ee a l N Es 1 a l te l fi igi j 2 Le tia iI 2 EOR 1 Q a S to D e S Oo Qo O Oo O EEL SON crc Q o Q 1 Ca a ai a ror Ss io p o YT g N IE 2 5 i NERS s OF I 2 9 D a aa 5 A side fully covered number of vias
47. ke up the chip from Deep sleep mode Unless the watchdog oscillator is selected to run in Deep sleep mode the clock source should be switched to IRC before entering Deep sleep mode because the IRC can be switched on and off glitch free Deep power down mode In Deep power down mode power is shut off to the entire chip with the exception of the WAKEUP pin The EM773 can wake up from Deep power down mode via the WAKEUP pin A LOW going pulse as short as 50 ns wakes up the part from Deep power down mode When entering Deep power down mode an external pull up resistor is required on the WAKEUP pin to hold it HIGH The RESET pin must also be held HIGH to prevent it from floating while in Deep power down mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 17 of 51 NXP Semiconductors EM773 7 16 7 16 1 7 16 2 7 16 3 7 16 4 EM773 Energy metering IC System control Start logic The start logic connects external pins to corresponding interrupts in the NVIC Each pin shown in Table 2 as input to the start logic has an individual interrupt in the NVIC interrupt vector table The start logic pins can serve as external interrupt pins when the chip is running In addition an input signal on the start logic pins can wake up the chip from Deep sleep mode when all clocks are shut down The start logi
48. le 6 Power consumption for individual analog and digital blocks Peripheral IRC Typical supply current in mA n a 12 MHz 48 MHz 0 27 System oscillator 0 22 Notes System oscillator running PLL off independent of main clock frequency IRC running PLL off independent of main clock at 12 MHz frequency Watchdog 0 004 System oscillator running PLL off independent oscillator at of main clock frequency 500 kHz 2 BOD 0 051 Independent of main clock frequency Main PLL 0 21 CLKOUT 0 12 0 47 Main clock divided by 4 in the CLKOUTDIV register CT16BO 0 02 0 06 CT16B1 0 02 0 06 CT32B0 0 02 0 07 CT32B1 0 02 0 06 GPIO 0 23 0 88 GPIO pins configured as outputs and set to LOW Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register IOCONFIG 0 03 0 10 12C 0 04 0 13 ROM 0 04 0 15 SPIO 0 12 0 45 UART 0 22 0 82 WDT 0 02 0 06 Main clock selected as clock source for the WDT EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 29 of 51 NXP Semiconductors EM773 EM773 Energy metering IC 9 4 Electrical pin characteristics Fig 10 Ve 36 002aae990 VoH T 85 C v 25 C 3 2 40 C 2 8 2 4 2 0 10 20 30 40 50 60 loH
49. mA current configured as standard mode pins 2 0 V lt Vpop lt 3 6V 1 8 V lt Vpp lt 2 0 V 3 loL LOW level output VoL 0 4 V I2C bus pins 20 mA current configured as Fast mode Plus pins 2 0 V lt Vpop lt 3 6 V 1 8 V lt Vpop lt 2 0 V 16 lu input leakage current Vj Vpp 15 2 4 uA Vi 5V 10 22 uA EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 23 of 51 NXP Semiconductors EM773 Energy metering IC Table 4 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Oscillator pins Vicxtal crystal input voltage 0 5 1 8 1 95 V Vo xtal crystal output voltage 0 5 1 8 1 95 y 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 Tamo 25 C 3 lbp measurements were performed with all pins configured as GPIO outputs driven LOW and pull up resistors disabled 4 IRC enabled system oscillator disabled system PLL disabled 5 BOD disabled 6 All peripherals disabled in the SYSAHBCLKCTRL register Peripheral clocks to UART and SPIO disabled in system configuration block 7 IRC disabled system oscillator enabled system PLL enabled 8 All oscillators and analog blocks turned off in the PDSLEEPCFG register PDSLEEPCFG 0x0000
50. nsition time see UM10204 This maximum must only be met if the device does not stretch the LOW period tLow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock tSu DAT is the data set up time that is measured with respect to the rising edge of SCL applies to data in transmission and the acknowledge A Fast mode 2C bus device can be used in a Standard mode 1 C bus system but the requirement tsu pat 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tr max tsu pat 1000 250 1250 ns according to the Standard mode C bus specification before the SCL line is released Also the acknowledge timing must meet this set up time SDA SCL tsu DAT 002aat425 Fig 19 I C bus pins clock timing 10 7 SPI interface Table 14 Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI masier in SPI mode Toy clk clock cycle time full duplex mode M 50 ns when only transmitting L 40 ns tps data set up time in SPI mode 2 15 ns 2 4 V lt Vpop lt 3 6 V 2 0 V lt Vpp lt 2 4V 8 20 ns 1 8 V lt Vpp lt 2 0V 2 24 ns tou data hold time in SPI mode 2 0 ns twa data output valid time in SPI mode Bo 10 ns tha data ou
51. ower apparent power and power factor of a load The purpose of the metrology engine is for non billing applications such as plug meters smart appliances industrial and consumer sub meters etc Features e 1 accurate for scalable input sources up to 230 V 50 Hz 16 A and 110 V 60 Hz 20 A while maintaining this accuracy with a factor of 1 to 400 down from this maximum current e Automatically calculates active power in W reactive power in VAr apparent power in VA power factor ratio Vrms and Irms without ARM CPU intervention e Standard API for initializing starting stopping and reading data from the metrology engine using the ARM Cortex MO General purpose external event counter timers The EM773 includes two 32 bit counter timers and one 16 bit counter timer The counter timer is designed to count cycles of the system derived clock It can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt Features e A 32 bit 16 bit timer counter with a programmable 32 bit 16 bit prescaler All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 13 of 51 NXP Semiconductors EM773 Energy metering IC Counter or timer operation
52. re at room temperature 25 C nominal supply voltages 2 The typical frequency spread over processing and temperature Tamb 40 C to 85 C is 40 3 See the EM773 user manual All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 35 of 51 NXP Semiconductors EM773 10 5 I O pins Energy metering IC Table 12 Dynamic characteristic I O pins Tamb 40 C to 85 C 3 0 V lt Vpp lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time pin 3 0 5 0 ns configured as output tr fall time pin 2 5 7 5 0 ns configured as output 1 Applies to standard port pins and RESET pin 10 6 C bus Table 13 Dynamic characteristic IC bus pinsi Tamb 40 C to 85 C Symbol Parameter Conditions Min Max Unit fscL SCL clock Standard mode 0 100 kHz frequency Fast mode 0 400 kHz Fast mode Plus 0 1 MHz ti fall time MISII of both SDA and 300 ns SCL signals Standard mode Fast mode 20 0 1 x Cp 300 ns Fast mode Plus 120 ns tLow LOW period of Standard mode 4 7 us the SCL clock Fast mode 1 3 us Fast mode Plus 0 5 us tHIGH HIGH period of Standard mode 4 0 us the SCL clock Fast mode 0 6 us Fast mode Plus 0 26 us HD DAT data hold time BIAI Standard mode 0 us Fast mode 0 z us Fast mode Plus 0 us tsu DAT data set up 91110 Standard mode 250 ns time Fast mode
53. reserved Product data sheet Rev 2 3 January 2012 34 of 51 NXP Semiconductors EM773 10 4 EM773 Energy metering IC Internal oscillators Table 10 Dynamic characteristic internal oscillators Tamb 40 C to 85 C 2 7 V lt Vpp lt 3 6 VII Symbol Parameter Conditions Min Typ Max Unit fosc RC internal RC oscillator frequency 11 88 12 12 12 MHz 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 12 15 002aat403 f MHz VDD 3 6V 3 3V 3 0 V 12 05 27V 2 4 V 2 0 V 11 95 11 85 40 15 10 35 60 85 temperature C Conditions Frequency values are typical values 12 MHz 1 accuracy is guaranteed for 2 7 V lt Vpp lt 3 6 V and Tamb 40 C to 85 C Variations between parts may cause the IRC to fall outside the 12 MHz 1 accuracy specification for voltages below 2 7 V Fig 18 Internal RC oscillator frequency versus temperature Table 11 Dynamic characteristics Watchdog oscillator Symbol Parameter Conditions Min Typ Max Unit fosc int internal oscillator DIVSEL 0x1F FREQSEL 0x1 S 7 8 5 kHz frequency in the WDTOSCCTRL register DIVSEL 0x00 FREQSEL 0xF S 1700 kHz in the WDTOSCCTRL register 1 Typical ratings are not guaranteed The values listed a
54. rposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum
55. s are the property of their respective owners 2C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 50 of 51 NXP Semiconductors EM773 18 Contents Energy metering IC 7 5 1 7 5 2 7 6 7 7 7 7 4 7 8 7 8 1 7 9 7 9 1 7 10 7 10 1 7 11 7 11 1 7 12 7 12 1 7 13 7 14 7 14 1 7 15 7 15 1 7 15 1 1 7 15 1 2 7 15 1 3 7 15 2 7 15 3 7 15 4 7 15 5 7 15 5 1 7 15 5 2 7 15 5 3 7 15 5 4 7 16 General description 000eeeee 1 Features and benefits 0000eeees 1 Applications 00 0 cece eee 2 Ordering information 0 00005 3 Block diagram 00 02e eee eens 4 Pinning information 0 000 eee 5 PINNING se twist ee old ae Ea dala AEDE 5 Pin description 0 22000 000e 6 Functional description 0 006 9 ARM Cortex M0 processor 9 On chip flash program memory 9 On chip SRAM 0 0c eee ee eee 9 Memory mMap 0020s 9 Nested Vectored Interrupt Controller NVIC 10 Features 2000 e eee eee 10 Interrupt SourceS 00 0055 11 IOCONFIG block 2000005 11 Fast gen
56. s of particular values e FIFO control mechanism that enables software flow control implementation e Support for RS 485 9 bit mode e Support for modem control SPI serial I O controller The SPI controller is capable of operation on a SSP 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer The SPI supports full duplex transfers with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carries meaningful data Features e Maximum SPI speed of 25 Mbit s master or 4 17 Mbit s slave in SSP mode e Compatible with Motorola SPI 4 wire Texas Instruments SSI and National Semiconductor Microwire buses e Synchronous serial communication e Master or slave operation e 8 frame FIFOs for both transmit and receive e 4 bit to 16 bit frame I2C bus serial I O controller The EM773 contains one l C bus controller The 2C bus is bidirectional for inter IC control using only two wires a Serial Clock Line SCL and a Serial DAta line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or All information provided in this document
57. single instruction to set or clear any number of bits in one write operation e Direction control of individual bits e All I O default to inputs with pull ups enabled after reset with the exception of the l2C bus pins PIOO_4 and PIOO_5 e Pull up pull down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin except for pins PIOO_4 and PIOO_5 All GPIO pins except PIOO_4 and PIOO_5 are pulled up to 3 3 V Vpp 3 3 V if their pull up resistor is enabled in the IOCONFIG block e Programmable open drain mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 11 of 51 NXP Semiconductors EM773 7 8 7 8 1 7 9 7 9 1 7 10 EM773 Energy metering IC UART The EM773 contains one UART Support for RS 485 9 bit mode allows both software address detection and automatic address detection using 9 bit mode The UART includes a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz Features e Maximum UART data bit rate of 3 125 MBit s e 16 Byte Receive and Transmit FIFOs e Register locations conform to 16C550 industry standard e Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B e Built in fractional baud rate generator covering wide range of baud rates without a need for external crystal
58. t 3 mA EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 21 of 51 NXP Semiconductors EM773 Table 4 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Energy metering IC Symbol loH loL lous lots Parameter HIGH level output current LOW level output current HIGH level short circuit output current LOW level short circuit output current pull down current pull up current High drive output pin PIOO_7 liL VoL loH EM773 LOW level input current HIGH level input current OFF state output current input voltage output voltage HIGH level input voltage LOW level input voltage hysteresis voltage HIGH level output voltage LOW level output voltage HIGH level output current Conditions Vou Vpp 0 4 V 2 0 V lt Vpp lt 3 6 V 1 8 V lt Vpp lt 2 0 V VoL 0 4 V 2 0 V lt Vpp lt 3 6 V 1 8 V lt Vpp lt 2 0 V Von 0V VoL Vpop Vi 5V Vi 0 V 2 0 V lt Vpp lt 3 6 V 1 8 V lt Vpop lt 2 0 V Vpop lt Vi lt 5 V V 0 V on chip pull up resistor disabled Vi Vpp on chip pull down resistor disabled Vo 0 V Vo Voo on chip pull up down resistors disabled pin configured to provide a digital function output active 2 5 V lt Vpop lt 3 6 V loH 20 mA
59. t which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 16 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort includin
60. tchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU the watchdog timer or the CLKOUT pin The watchdog oscillator nominal frequency is programmable between 7 8 kHz and 1 7 MHz The frequency spread over processing and temperature is 40 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 The CCO operates in the range of 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The PLL output frequency must be lower than 100 MHz The output divider may be set to divide by 2 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle The PLL is turned off and bypassed following a chip reset and may be enabled by software The program must configure and activate the PLL wait for the PLL to lock and then connect to the PLL as a clock source The PLL settling time is 100 us Clock output The EM773 features a clock output function that routes the IRC oscillator the system oscillator the watchdog oscillator or the main clock to an output pin Wake up process The EM773 begin operation at power up and when awakened from
61. to the power profile The power configuration routine configures the EM773 for one of the following power modes e Default mode corresponding to power configuration after reset e CPU performance mode corresponding to optimized processing capability e Efficiency mode corresponding to optimized balance of current consumption and CPU performance e Low current mode corresponding to lowest power consumption In addition the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock Sleep mode When Sleep mode is entered the clock to the core is stopped Resumption from the Sleep mode does not need any special sequence but re enabling the clock to the ARM core In Sleep mode execution of instructions is suspended until either a reset or interrupt occurs Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses Deep sleep mode In Deep sleep mode the chip is in Sleep mode and in addition all analog blocks are shut down As an exception the user has the option to keep the watchdog oscillator and the BOD circuit running for self timed wake up and BOD protection Deep sleep mode allows for additional power savings Up to 13 pins total serve as external wake up pins to the start logic to wa
62. tput hold time in SPI mode al o a ns EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 37 of 51 NXP Semiconductors EM773 Energy metering IC Table 14 Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI slave in SPI mode Tey PcLk PCLK cycle time 20 ns tps data set up time in SPI mode BIA 0 ns too data hold time in SPI mode BIA 3x Teypck 4 ns twa data output valid time in SPI mode BA 3 x Toy PcLk 11 ns tha data output hold time in SPI mode BA i 2 x Toy PCLk 5 ns 1 Tey SSPCLKDIV x 1 SCR x CPSDVSR fmain The clock cycle time derived from the SPI bit rate Tey cik is a function of the main clock frequency fmain the SPI peripheral clock divider SSPCLKDIV the SPI SCR parameter specified in the SSPOCRO register and the SPI CPSDVSR parameter specified in the SPI clock prescale register 2 Tamb 40 C to 85 C 3 Toy etk 12 x Tey PcLk 4 Tamb 25 C for normal voltage supply range Vpp 3 3 V SCK CPOL 0 SCK CPOL 1 tv Q j th Q tps tbH CPHA 1 MISO DATA VALID DATA VALID twa je th Q MOSI DATA VALID DATA VALID tos tbH CPHA 0 _ MISO DATA VALID DATA VALID 002aae829 Fig 20 SPI master timing in SPI mode
63. ts in Active Sleep and Deep sleep modes were performed under the following conditions see EM773 user manual e Configure all pins as GPIO with pull up resistor disabled in the IOCONFIG block e Configure GPIO pins as outputs using the GPIOnDIR registers e Write 0 to all GPIOnDATA registers to drive the outputs LOW All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 25 of 51 NXP Semiconductors EM773 EM773 Energy metering IC 002aaf980 48 MHz 2 36 MHz 2 24 MHz 2 12 MHz 1 8 2 4 3 0 3 6 Vpp V Conditions Tamb 25 C active mode entered executing code while 1 from flash all peripherals disabled in the SYSAHBCLKCTRL register SYSAHBCLKCTRL 0x1F all peripheral clocks disabled internal pull up resistors disabled BOD disabled low current mode 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled Fig 5 Active mode Typical supply current lpp versus supply voltage Vpp for different system clock frequencies 002aaf981 10 IDD mA 8 48 MHz 2 6 36 MHz 2 4 24 MHz 2 5 12 MHz 1 0 40 15 10 35 60 85 temperature C Conditions Vpp 3 3 V active mode entered executing co
64. u endurance O1 10000 100000 cycles tret retention time powered 10 years unpowered 20 gt years ter erase time sector or multiple 95 100 105 ms consecutive sectors torog programming 2 0 95 1 1 05 ms time 1 Number of program erase cycles 2 Programming times are given for writing 256 bytes from RAM to the flash Data must be written to the flash in blocks of 256 bytes EM773 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 3 January 2012 33 of 51 NXP Semiconductors EM773 Energy metering IC 10 3 External clock EM773 Table 9 Dynamic characteristic external clock Tamb 40 C to 85 C Vpp over specified ranges 1 Symbol Parameter Conditions Min Typ 2 Max Unit fosg oscillator frequency 1 25 MHz Tey cik clock cycle time 40 1000 ns tcHcx clock HIGH time Tey x 0 4 ns tcLcx clock LOW time Teya x 0 4 ns tcLcH clock rise time 5 ns tcHCL clock fall time 5 ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 002aaa907 Fig 17 External clock timing with an amplitude of at least Vi Rms 200 mV All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights

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