FMC176 User Manual - 4DSP LLC
Contents
1. rcm 14 5 2 SPIPrOogrammifigi 2 16 18 6 1 Temperature Rm 18 62 IUS a ea re e N eee ee usaq 18 SR MES 19 6 3 1 Convection cooling t o oS STA 19 63 2 GOnduectiori O0llfiQ uu ua o 19 f 5 19 5 19 9 Ordering information eee ete ee 20 20 Appendix A LPC HPC pin out1 u T T 21 Appendix B CPLD Register map U U u 24 UM022 www 4dsp com 3 UM022 FMC176 User Manual r1 10 1 Acronyms and related documents 1 1 Acronyms DDR DoubleDataRate QDR QuadrpleDatarate TTL Transistor Logic level XMC Table 1 Glossary 1 2 Related Documents e FPGA Mezzanine Card FMC standard ANSI VITA 57 1 2010 e Datasheet AD9250 Rev 0 Analog Devices e Datasheet AD9129 Rev C Analog Devices e Datasheet AD95172. 1 SSMC 2 Reserved Standard Feature 1 Mil I 46058c Conformal Coating No Conformal Coating 1 Add Conformal Coating 2 10 Warranty Basic Warranty 1 Year from Date of Shipment 90 Days from Date of Shipment included Extended Warranty 2 Years from Date of Shipment 1 Year from Date of Shipment optional UM022 www 4dsp com 20 UM022 FMC176 User Manual Appendix A LPC HPC pin out r1 3 e Note that FMC700 is required to use the FMC176 on KC705 AV57 1 HPC Pin FMC176 Signal AVS7 1 HPC Pin FMC176 Signal AVS7 1 HPC Pin FMC176 Signal CLKO_M2C_N H5 CLK_TO_FPGA_N HAOO_N_CC FS DAC1_DCO_N HBOO_N_CC K26 DAC1_P1_DPO5_N CLKO M2C P H4 CLK_TO_FPGA_P HAOO_P_CC F4 DAC1_DCO_P HB00_P_CC K25 DAC1_P1_DP05_P CLK1_M2C_N G3 EXT_TRIGGER_N N CC E3 DAC1_DCI_N HBO1_N J25 DAC1_P1_DP04_N CLK1_M2C_P G2 EXT_TRIGGER_P 6 E2 DAC1_DCI_P HBO1_P J24 DAC1_P1_DP04_P CLK2_BIDIR_N K5 N C HA02_N K8 DAC1_FRM_N HBO2_N F23 DAC1_P1_DP03_N CLK2_BIDIR_P K4 N C HA02_P K7 DAC1_FRM_P HB02_P F22 DAC1_P1_DP03_P CLK3_BIDIR_N 3 N C HAO3_N 17 DAC1_PO_DPOO_N HBO3_N E22 DAC1_P1_DP02_N 3 12 N C HAO3_P J6 1 PO DPOO P HB03 P E21 DAC1 P1 DPO2 P LAOO_N_CC G7 DACO_DCO_N HAO4_N F8 DAC1_P0_DP01_N HB04_N F26 DAC1_P1_DP01_N LAOO P CC G6 DACO DCO P 7 DAC1_PO_DP01_P
3. UM022 www 4dsp com 22 UM022 FMC176 User Manual r1 10 DACO_FRM_N DACO_PO_P lt 13 0 gt D A 0 Input LVDS Data bus 0 going to the 1st D A converter DACO PO N 13 0 DACO P1 19 05 D A 0 Input LVDS Data bus 1 going to the 1st D A converter DACO P1 N 13 0 DAC1 DCO P D A 1 Output LVDS Clock coming from the 2nd D A converter DAC1 DCO N 1 8V Sync output when enabled this output is DAC1 SYNC D A 1 Output CMOS DACCLK 8 Only available on r1 2 boards or later DAC1 DCI P D A 1 Input LVDS Clock going to the 2nd D A converter DAC1 DCI N DAC1 FRM P D A 1 Input LVDS Frame going to the 2nd D A converter DAC1 FRM N DAC1 PO 19 05 D A 1 Input LVDS Data bus 0 going to the 2nd D A converter DAC1 PO N 13 0 DAC1 P1 13 05 D A 1 Input LVDS Data bus 1 going to the 2nd D A converter DAC1 P1 N 13 0 GBTCLK_M2C_P lt 1 0 gt A D Output LVDS JESD204B reference clock Currently only GBTCLK M2C N 1 0 bit 0 is used SERDOUT_P lt 3 0 gt A D Output LVDS JESD204B links One lane per channel SERDOUT_N lt 3 0 gt SYNCIN_L A D Input LVDS JESD204B SYNC IN SYSREF A D Input LVDS JESD204B SYSREF CLK_TO_FPGA_P i i tHL o Output LVDS Clock coming from the clock tree Typically CLK TO FPGA N used for debug and monitoring purposes EXT_TRIGGER_P i Output LVDS
4. 4 10 Clock tree The FMC offers a clock architecture that combines flexibility and high performance Components have been chosen in order to minimize jitter and phase noise to reduce degradation of the data conversion performance The user may choose to use an external sampling clock or an internal sampling clock The clock tree has a PLL and clock distribution section The PLL ensures locking of the internal VCO clock to an external supplied reference An onboard reference is used if no external reference is present The onboard reference is a QuartzCom TX3 801 30 72MHz UM022 www 4dsp com 11 UM022 FMC176 User Manual Sr aio Loop Filter SWITCHOVER AND MONITOR Dco 1 mg E ours xo At gt O ouT4 To FMC PGE mesewos gt PSS D Q ours 7 9 To GBT owe Habivesewos PS curt n SERIAL CONTROL PORT oul AND S DIGITAL Logic Figure 6 Clock tree The AD9517 has four LVPECL outputs OUTO to OUTS which are used for clocking the ADC and DAC devices The other four clock outputs can be either programmed as LVDS or LVCMOS33 These outputs can enable a programmable delay OUT4 is connected to the FMC connector for test and monitoring purposes OUT5 connect to the gigabit transceiver reference clock on the FMC connector as a build option it can be connected to OUT7 OUT6 connects to the clock output on a MMCX connector 4 10 1 PLL design The PLL functionality of the AD95
5. of the external trigger EXT_TRIGGER_N gna SPI bus to CPLD on the FMC176 CMOS FMC_TO_CPLD 0 SPI Clock FMC_TO_CPLD lt 3 0 gt CONTROL Bidir VIO FMC TO CPLD 1 SPI Chip Select low active FMC TO CPLD 2 SPI Data In Out FMC TO CPLD 3 SPI Alert Interrupt CLK DIR is not connected CLK2 and CLK DIR CONTROL Output LVTTL are unused PG_C2M STATUS Input LVTTL Power good indicator from carrier to module PG_M2C STATUS Output LVTTL Power good indicator from module to carrier I2C_SCL 12C Input LVTTL I2C clock line 20 SDA 12C Bidir LVTTL I2C data line Table 8 FMC176 Signal Description UM022 www 4dsp com 23 UM022 FMC176 User Manual Sr aio Appendix B CPLD Register map Control register 0 0 for internal reference clock 1 for external reference clock disable internal reference 0 Release ADC reset 1 Assert ADC reset 0 Release DAC reset 1 Assert DAC reset 0 Release CLK reset AD9517 1 Assert CLK reset AD9517 0 Release CLK sync AD9517 1 Assert CLK sync AD9517 Reserved EEPROM write enable Recommended to write 0 Control register 1 0 for ADCO power enable 1 for ADCO power down Reserved for ADCO FDA status Reserved for ADCO FDB status 0 for ADC1 power enable 1 for ADC1 power down Reserved for ADC1 FDA status Reserved for ADC1 FDB status 0 for CLK po
6. 500 after the transformers by terminating to ground The R C R filter near the input of the A D converter can be used to improve performance when lower input bandwidth is required This filter is not assembled by default Figure 4 AC coupled input assembly UM022 www 4dsp com 9 UM022 FMC176 User Manual Sr anit The following filter is assembled C1 3 9pF C2 8 2pF R1 15R R2 0R R3 49R9 4 5 Analog output channels The DAC output circuit is constructed such that different build options can be made The default configuration will be a wideband balun ETC1 1 13 MACOM 4 5 to 3000MHz as shown in Figure 5 This configuration is the recommended output circuit for mixed mode operation of the DAC for details refer to the AD9129 datasheet Please contact 4DSP for custom configurations 4 5 1 Analog output phase While not intuitively obvious from the representative schematic below the analog output voltage tracks the data written to the DAC The analog output signal at its maximum when the DAC is set to full scale As shown in the schematic the analog output connector X8 is directly connected to the DACs IOUTN labeled DAC1 IN signal thru the balun T4 this results in the output voltage tracking the voltage on the IOUTN pin From the perspective of the output connector and IOUTN the analog output is formed by a voltage divider consisting of the high side pulled up to 1 8V by R89 and L13 and the low side pulled d
7. HBO4_P F25 DAC1_P1_DP01_P LAO1 CC D9 DACO_DCI_N HAOS_N E7 DAC1_PO_DP02_N HBOS_N E25 DAC1 P1 DPOO N LAO1 CC D8 DACO DCI P 5 P E6 DAC1_PO_DP02_P HBOS_P E24 DACI P1 DPOO P LAO2_N H8 DACO_FRM_N 6 K11 DAC1_PO_DP04_N HBO6_N_CC 29 DAC1_P1_DPO6_N LAO2 P H7 DACO FRM P HAO06 P K10 1 PO DPO4 P HB06 P CC 28 DAC1_P1_DP06_P LAO3_N G10 DACO_PO_DPOO_N 7 J10 DAC1_P0_DP03_N HB07_N J28 DAC1_P1_DP07_N LA03_P G9 DACO_PO_DPOO_P 7 19 DAC1_PO_DP03_P HBO7_P 127 DAC1_P1_DP07_P LAO4_N H11 DACO PO DPO1 N HAO8_N F11 DAC1_P0_DP05_N HB08_N F29 DAC1 P1 DPO9 N LAO4 P H10 DACO PO DPO1 P P F10 1 PO DPO5 P HBO8_P F28 DAC1_P1_DP09_P LAOS_N D12 DAC0_P0_DP02_N HA09_N E10 DAC1_PO_DPO6_N HB09 N E28 DAC1 P1 DPOS8 N LAOS P D11 DACO PO DPO2 P P E9 1 PO DPOG P HBO9_P E27 DAC P1 DPO8 P LAOG C11 DACO PO DPO3 N HA10 N K14 DAC1_PO_DPO9_N HB10_N K32 DAC1_P1_DP11_N LAO6_P C10 DACO PO DPO3 P HA10 P K13 1 PO DPO9 P HB10 P K31 DAC1_P1_DP11_P LAO7_N H14 DACO_PO_DP04_N HA11_N J13 DAC1_PO_DPO8_N HB11_N 131 DAC1_P1_DP10_N LAO7 P H13 DACO PO DPO4 P HA11 P J12 DAC1_PO_DPO8_P HB11_P J30 DAC1_P1_DP10_P LAO8_N G13 DACO_PO_DPOS_N HA12_N F14 DAC1_P0_DP07_N HB12_N F32 DAC1_P1_DP13_N LAO8_P 612 DACO PO DPOS P HA12 P F13 1 PO DPO7 P HB12 P F31 DAC1_P1_DP13_P LAOS_N D15 DAC0_P0_DP06_N HA13_N E13 DAC1_P0_DP10_N HB13_N E31 DAC1_P1_DP12_N LA09_P D14 DAC0_P0_DP06_P HA13_P E12 DAC1_P0_DP10_P HB13_P E30 DAC1_P1_DP12_P LA10 N C15 D
8. allowed range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 6 3 2 Conduction cooling In demanding environments the ambient temperature inside a chassis could be close to the operating temperature defined in this document It is very likely that in these conditions the junction temperature of power consuming devices will exceed the operating conditions recommended by the devices manufacturers mostly 85 C While a low profile heat sink coupled with sufficient air flow might be sufficient to maintain the temperature within operating boundaries some active cooling would yield better results and would certainly help with resuming operations much faster if the devices are disabled because of a temperature over range 7 Safety This module presents no hazard to the user 8 EMC This module is designed to operate within an enclosed host system built to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system UM022 www 4dsp com 19 UM022 FMC176 User Manual Sr a4 9 Ordering information Part Number FMC176 2 1 1 1 Card Type Temperature Range Industrial 40 C to 85 C 1 Commercial 0 C to 70 C 2 Connector Type MMCX Standard feature
9. 17 operates from an internal sampling clock to enable flexibility in frequency selection while maintaining high performance The default loop filter is designed for a phase detector frequency of 7 68MHz fret 4 loop bandwidth of 10 KHz phase margin of 45 deg and a charge pump of 4 8mA Lower phase detector frequencies might be required to achieve the required output clock frequency phase detector frequency equals the VCO tuning step size Whether the loop filter design still works for other configurations should be investigated case by case UM022 www 4dsp com 12 UM022 FMC176 User Manual DES r1 10 AD9517 1 FMC176 2300MHz 2650MHz 2457 60MHz 245 76MHz 2457 60MHz Table 3 FMC default clock configurations Note Higher DAC clock frequencies fs up to 5700MHz can be achieved using external clock CLK CLK Bypass AD9517 X REFIN 4 330pF Ri R2 1 00k 2 00k 4 70nF 9 C2 220nF NA Figure 7 Loop filter design 4 11 Power supply C3 T 150pF Power is supplied to the FMC card through the FMC connector The pin current rating is 2 7A but the overall maximum is limited according to Table 4 Voltage Pins Max Amps Max Watt 3 3V 4 3A 10 W 12V 2 1A 12 W VADJ 4 4A 10 W VIO B VADJ 2 1 15 A 2 3 W Table
10. 3 Write instruction to AD9129 registers A4 A0 N_CS sok T YUU UU U UU UU UU UU UU SDIO P7 P6 I P5 P4 I P3 P2 Po Rav N1 NO as as a2 t ao o7 pe os D4 bs ps pt bo gt 8 bit pre selection 8 bit instruction 8 bit register data Figure 14 Read instruction to AD9219 registers A4 A0 N_CS suk SDIO P7 Pe ps pa pa Pe P1 Po jawi wi wo Aeon aro as v e as s A2 oo D7 Ds Ds pa ps vs p bo 8 bit pre selection 16 bit instruction 8 bit register data Figure 15 Write instruction to AD9517 AD9250 registers A12 A0 UM022 www 4dsp com 17 UM022 FMC176 User Manual Sr aio N_CS sak TY YU UU UU UU UU UU UU UU UU UU i P I SDIO ne ps Pa Ps p2 P1 Po RA w wo as x os as s A2 oo D7 De 05 pa 0 ve pi o gt 8 bit pre selection 16 bit instruction 8 bit register data Figure 16 Read instruction to AD9517 AD9250 registers A12 A0 6 Environment 6 1 Temperature Operating temperature e 40 C to 85 C Industrial Storage temperature e 40 C to 120 C 6 2 Monitoring The FMC has an AD7291 device for monitoring several power supply voltages on the board as well as temperature The device can be program
11. 3V LVTTL into 50Ohm would result in 14dBm a 1A Schottky diode in the clock input circuit protects the clock input from overvoltage when driving the input with a LVTTL signal AD9517 device does support up to 2850MHz with a clock input level of OdB and higher UM022 www 4dsp com 8 UM022 FMC176 User Manual Sr anit External reference clock input Serial numbers FMC176 0000 to FMC176 0104 Input Level LVTTL 3 6 gt Vin gt 2 0V 0 3 lt Vi lt 0 8V Input impedance 50Q DC coupled Input range OMHz to 250MHz Serial numbers FMC176 0105 and above LVTTL 3 6 gt Vin gt 2 0V 0 3 lt Vi lt 0 8V Input is DC coupled and self biased to 1 5V refer to section 4 8 Input range OMHz to 250MHz Input Level External clock output 800mVp p into 50Q typical Output Level LVCMOS output available as build option contact 4DSP External Trigger input LVTLL LVCMOS33 Logic 0 gt max 0 8V Logic 1 gt min 2 0V Frequency range Up to 300 MHz Internal sampling clock Format LVPECL Format ADC up to 250MHz Software selectable Frequency Range DAC up to 5300MHz Software selectable contact 4DSP for frequencies higher frequencies up to 5700MHz Table 2 FMC daughter card main characteristics 4 4 Analog input channels The analog input signals are connected to the FMC via MMCX connectors on the front panel The input is AC coupled using wideband RF transformers TC4 1W The input impedance is matched to
12. 4 FMC standard power specification The power provided by the carrier card can be very noisy Special care is taken with the power supply generation on the FMC card to minimize the effect of power supply noise on clock generation and data conversion Clean 1 8V is derived from 3 3V with linear regulators Clean 3 3V is derived from 12V in two steps for maximum efficiency The first step uses a high efficient switched regulator to generate a 3 8V power rail From this power rail each analog supply is derived with separate low dropout low noise and linear regulators The regulators have sufficient copper area to dissipate the heat in combination with proper airflow see section 6 3 Cooling UM022 www 4dsp com 244 UM022 FMC176 User Manual Sr aio ADP2301 22mA 12V 45mw ITI 120mA 1 5V Eff 85 Max 200mA ADP 151 eo ecd AD9129 263mW soma 45va 8 Uum dich ADP1753 __g60mA 1 8V1 Consumption 990mW 8 8W Max 800mA ADP151 E Hi AD9129 263mW i 80mAQ 15Va SOTW 1954mA VADJ ADP1753 520mA 1 8V 260mA 1 8Va 1954mA 3 3V 780mw me AD9250 lax 800mA 850mW aye poral i 212mA 1 8Vd 260mA 9 1 8Va AD9250 ADP1753 850mW e3emw 424mA 1 8V 212mA 1 8V
13. ACO PO DPO9 N HA14 N J16 1 PO DP11 N HB14 N K35 LA10 P 614 DACO PO DPO9 P P J15 DAC1_PO_DP11_P HB14_P K34 LA11_N H17 DACO PO DPO8 N HA15 N F17 DAC1_PO_DP12_N HB15_N J34 LA11_P H16 DACO_PO_DPO8_P HA15 P F16 1 PO DP12 P HB15 P J33 LA12_N G16 DACO PO DPO7 N HA16 N E16 DAC1_PO_DP13_N HB16_N F35 LA12 P G15 DACO PO DPO7 P HA16 P E15 1 PO DP13 P HB16 P F34 LA13 N D18 DACO PO DP10 N 17 N CC K17 DACI1 SYNC HB17 N CC K38 LA13 P D17 DACO PO DP10 P HA17 P CC K16 DACO SYNC HB17 P CC K37 LA14 N C19 DACO PO DP13 N HA18 N 119 HB18_N 137 LA14 P C18 DACO PO DP13 P HA18 P J18 HB18 P J36 LA15 N H20 DACO PO DP12 N HA19 N F20 HB19 N E34 LA15 P H19 DACO PO DP12 P HA19 P F19 HB19 P E33 LA16 N G19 DACO PO DP11 N HA20_N E19 HB20_N F38 LA16 P G18 DACO PO DP11 P HA20 P E18 HB20 P F37 LA17 N CC D21 DACO P1 DPOO0 N HA21 N 20 HB21_N E37 LA17 P CC D20 DACO P1 DPOO P HA21 P K19 HB21 P E36 UM022 FMC176 User Manual Sr aio LA18 N CC C23 DACO Pi DPO1 N HA22 N 122 LA18 P CC C22 DACO P1 DPO1 P HA22 P J21 LA19 N H23 DACO P1 DPO3 N HA23 N K23 GBTCLKO M2C P D4 GBTCLKO M2C P LA19 P H22 DACO P1 DPO3 P HA23 P K22 GBTCLKO_M2C_N D5 GBTCLKO_M2C_N 20 G22 DACO_P1_DP02_N GBTCLK1_M2C_P B2O GBTCLK1_M2C_P LA20_P G21 DACO_P1_DP02_P GBTCLK1_M2C_N B21 GBTCLK1_M2C_N LA21 N H26 DACO P1 DPOS N M2
14. C N C7 SERDOUTA N LA21 P H25 DACO P1 DPO5 P DPO M2C P C6 SERDOUTA P LA22 N 625 DACO Pi DPO4 N DP1 M2C N A3 SERDOUTB N LA22 P G24 DACO P1 DPO4 P DP1 M2C P A2 SERDOUTB P LA23 N D24 DACO P1 DPOG N DP2 M2C N A7 SERDOUTC N LA23 P D23 DACO P1 DPO6 P DP2 M2C P A6 SERDOUTC P LA24 N H29 DACO P1 DP10 N DP3 M2C N Ali SERDOUTD N LA24 P H28 DACO P1 DP10 P DP3 M2C P A10 SERDOUTD P LA25 N G28 DACO Pi 09 N LA25 P G27 DACO P1 DPOS P LA26 N D27 DACO Pi DPO7 N LA26 P D26 DACO P1 DPO7 P LA27 N C27 DACO Pi DPO8 N LA27 P C26 DACO P1 DPO8 P LA28 N H32 DACO P1 DP12 N LA28 P H31 DACO P1 DP12 P LA29 N G31 DACO Pi DP1i N LA29 P G30 DACO Pi DP11 P 30 N H35 DACO P1 DP13 N LA30 P H34 DACO P1 DP13 P LA31 N G34 FMC TO CPLD 1 LA31 P 533 FMC TO CPLD 0 DIR B1 LA32 N H38 FMC TO CPLD 3 PG C2M D1 PG C2M LA32 P H37 FMC TO CPLD 2 PG M2C F1 PG_M2C LA33_N 637 SYNCIN_L I2C_SCL C30 12C_SCL LA33_P G36 SYSREF I2C SDA C31 12 SDA Table 7 FMC176 Pinout x DAC0_DCO_P D A 0 Output LVDS Clock coming from the 1st D A converter DAC0_DCO_N 1 8V Sync output when enabled this output is DACO_SYNC D A 0 Output CMOS DACCLK 8 Only available on r1 2 boards or later DACO_DCI_P D A 0 Input LVDS Clock going to the 1st D A converter DACO_DCI_N DACO_FRM_P D A 0 Input LVDS Frame going to the 1st D A converter
15. Cl Reference Input RI Clock Output CO 66000000008 Figure 2 Front panel layout 4 2 Electrical specifications The main ADC sample data is transferred using JESD204B coded differential pairs connected to the GBT pins on the FMC connector There is one lane available per ADC channel UM022 www 4dsp com 6 UM022 FMC176 User Manual Sr anit The DAC devices use DDR LVDS signals mapped to the regular FMC pins Each channel has two 14 bit wide DDR LVDS busses Control signals operate in LVCMOS mode A VADJ range of 1 2V to 3 3V is supported The voltage on VIO B pins will follow the voltage on VADJ The CLKx pins are required to be LVDS by the FMC standard CLK2 and CLK3 are not used for best compatibility with Xilinx development platforms CLKO is connected to a spare clock output of the clock tree CLK1 is connected to the external trigger 4 2 1 EEPROM The FMC card carries a small serial EEPROM M24C02 which is accessible from the carrier card through the I C bus The EEPROM is powered by 3P3VAUX The standby current is only 0 01 when SCL and SDA are kept at 3P3VAUX level These signals may also be left floating since pull up resistors are present on the FMC By default the EEPROM is write protected 4 2 1 FMC Connector FMC Top Connector The top connector is the main connector to the FMC carrier board The pin out is defined in the appendix The connector is a HPC connector FMC Bottom Connector The h
16. Rev A Analog Devices e Datasheet AD7291 Rev B Analog Devices e FMC700 User Manual 4DSP UM022 www 4dsp com 4 UM022 FMC176 User Manual Sr anit 2 General description The FMC176 is a four channel ADC and two channel DAC FMC daughter card It provides four 14 bit up to 250MSPS ADC channels and two 14 bit up to 5 7GSPS DAC channels which can be clocked by an internal clock source optionally locked to an external reference or an externally supplied sample clock There is one trigger input for customized sampling control The FMC daughter card is mechanically and electrically compliant to FMC standard ANSI VITA 57 1 The FMC has a high pin count connector front panel I O and can be used in a conduction cooled environment The design is based on Analog Devices AD9250 dual channel 14 bit 250MSPS ADC with JESD204B coded serial digital outputs and Analog Devices AD9129 single channel 14 bit 5 7GSPS DAC with DDR LVDS inputs The analog signal inputs outputs are AC coupled connecting to MMCX coax connectors on the front panel The FMC allows flexible control of sampling frequency analog input gain and over range detection through serial communication busses The card is also equipped with power supply and temperature monitoring and offers several power down modes to switch off unused functions or protect the card from overheating Ref Clock Sample Clock K Clock Tree Status amp Control Clock Output K Trigger e
17. UM022 FMC176 User Manual Sr anit FMC176 User Manual 4DSP USA Email support 4dsp com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP LLC 4DSP LLC 2015 UM022 FMC176 User Manual wp C Revision History 2012 12 17 2013 02 05 2013 03 22 2013 08 15 2014 04 11 2014 05 30 2014 07 03 2014 10 02 2015 03 05 2015 06 22 2015 09 28 UM022 Corrected pin assignments in Appendix A Updated analog input output range in Table 2 and added a FMC700 requirement information for KC705 Updated analog output bandwidth in Table 2 Updated the pinout table and added a signal description in Appendix A Revised some descriptions and fixed typos Corrected analog output power range in Table 2 Added DACx_SYNC signals in Appendix A Updated external reference input characteristics Clarified external clock frequency range Updated analog output and external sample clock input characteristics Updated Figure 5 Wideband balun output option to 1 10 match board schematic added section 4 5 1 5 2 www 4dsp com r1 10 UM022 FMC176 User Manual r1 10 Table of Contents 1 Acronyms and related documents J U 4 DEM CO0 T uuu ooo term 4 1 2 Related Documents toca cascade Gum bera RU HE Edd qud 4 2 General descr
18. When internal clock is enabled and there is no need for an external reference it is highly recommended to leave the clock input unconnected to prevent interference with the internal clock 4 8 External reference input There is one MMCX reference input on the front panel that can serve as reference clock input Refer also to section 4 10 for more information about the clock tree Note When internal clock is enabled and there is no need for an external reference it is highly recommended to terminate the reference input with 50O to ground to prevent interference with the internal clock The external reference input connects to the single ended high impedance REF2 input of the AD9517 clock generator The input is DC coupled to support reference frequencies below 20MHz The AD9517 has got an internal self bias voltage of 1 5V The single ended input characteristics of the clock generator specify lt 0 8V and Vin gt 2 0V If the external reference source is DC coupled make sure that the lt 0 8V and Vin gt 2 0V levels are met If the external reference source is AC coupled the clock generator uses its self bias to pull its reference input to the offset level of 1 5V The required AC voltage swing ranges from 1 4Vpk pk to 2 2Vpk pk 4 9 External clock output There is one MMCX clock input on the front panel that can serve as sampling reference clock output Refer also to section 4 10 for more information about the clock tree
19. d Max 800mA ADP151 TCXO Ssma OS TX3 801 ADP2301 169 mA 12V 406mw 480mA 3 6V ADP1753 455ma 3sy D9517 135mW 1 5W Eff 85 Max 800mA Figure 8 Power supply tree Power plane Typical Maximum VADJ 0 2A lvio B 3P3V 2 0A 2 1 12 0 0 2A 0 3A 3P3VAUX Operating 0 1 mA 3mA 3P3VAUX Standby 0 01 HA 1 uA Table 5 Typical Maximum current drawn from FMC carrier card 5 Controlling the FMC176 5 1 Architecture The data interface of one DAC channel occupies 31 differential pairs on the FMC connector Since one DAC channel is available on the LPC connections there are only six signals left on the LPC connections to control the board The FMC will therefore be controlled from a single SPI interface connecting to an onboard CPLD Xilinx Coolrunner Il XC2C64A QFG Four connections are available between the FMC connector and the CPLD The CPLD is factory programmed and acts as a SPI distribution device and level translator The two remaining signals on the FMC connector will be used for controlling the JESD204B devices SYNCIN_L and SYSREF will be translated to LVDS and fanned out on the FMC UM022 www 4dsp com 14 UM022 FMC176 User Manual Sr anit 3 3V VADJ FMC Connector ADG3304 FMC TO CPLD 3 0 Signals to AD9517 Signals to AD9250 AD9129 ADCO SYNCIN L NB6N11S SYNCIN_L ADC1_SYNCIN_L ADCO SYSREF NB6N11S SYSCLK ADC1_SYSREF Figure 9 FMC c
20. eeds to be preceded with a preselection byte The preselection byte is used by the CPLD to forward the SPI command to the right destination The preselection bytes are defined as follows CPLD 0x00 AD9250 1 0x80 AD9250 2 0x81 AD9129 1 0x82 AD9129 2 0x83 AD9517 0x84 The CLPD has three internal registers which are described in the Appendix The registers of the other devices are transparently mapped UM022 www 4dsp com 16 UM022 FMC176 User Manual Sr aio YT N_CS sik T YUU UU U UU UU UU UU UU LL SDIO P7 P6 P5 P4 P3 P2 I P1 P0 in A6 A5 A4 A3 A2 ao 07 be os 04 os os o1 D0 gt 8 bit pre selection 8 bit instruction 8 bit register data Figure 11 Write instruction to CPLD registers A1 A0 N_CS sik T YUU UU UU UU UU UU UU UU UU UU SDIO P7 P6 P5 P4 I P3 P2 P1 Po RAN A6 A5 A4 A3 A2 Ao 07 06 ps s es et o gt 8 bit pre selection 8 bit instruction 8 bit register data Figure 12 Read instruction to CPLD registers A1 A0 N CS sik T YUU UU UU UU UU UU UU UU Li SDIO P7 P6 I P5 I P4 I P3 I P2 e Po rit N1 i No A4 A3 A2 A1 AO D7 D6 D5 D4 D3 D3 D1 DO 8 bit pre selection 8 bit instruction 8 bit register data Figure 1
21. gt ADC A Data JESD204B Status amp Control p ADC B 9 ADC C Data JES D204B Status amp Control ADC D DDR LVDS DAC A Status amp Control p DDR LVDS DAC B Status amp Control Figure 1 FMC176 block diagram UM022 www 4dsp com 5 UM022 FMC176 User Manual Sr anit 3 Installation 3 1 Requirements and handling instructions e Prevent electrostatic discharges by observing ESD precautions when handling the card e Do not flex the card e The FMC daughter card must be installed on a carrier card compliant to the FMC standard e The FMC carrier card must support the high pin count connector 400 pins to support all channels A low pin count connector is supported but may result in limited features e The FMC carrier card may support a VADJ VIO_B voltage of 1 2V to 3 3V e The FMC700 is required in order to use the FMC176 on KC705 4 Design 4 1 Phycisal specifications 4 1 1 Board Dimensions The FMC card complies with the FMC standard known as ANSI VITA 57 1 The card is a single width conduction cooled mezzanine module with region 1 and front panel I O There may be a mechanical conflict with the front rib on a carrier card The stacking height is 10mm and the PCB thickness is 1 6mm 4 1 2 Front panel There are 10 MMCX connectors available from the front panel From top to bottom Analog inputs D A3 C A2 B A1 and A AO Analog outputs B D1 and A DO Trigger in TR Clock Input
22. igh pin count connector enables FMC card stacking The following connections are available between the top and bottom FMC connector e Unused gigabit data signals DP 4 9 M2C_P N DP 0 9 C2M P N e All gigabit reference clocks GBTCLK 0 1 M2C P N e RESO e 3P3VAUX 3 93 12POV VADJ e JTAG see section 4 2 1 The bottom connector is not mounted by default 4 2 1 JTAG In a stacked environment the TDI pin will be decoupled from the TDO pin by the PRST_M2C_L signal coming from the bottom connector TRST TCK TMS TDI and TDO are directly connected between top to bottom connector UM022 www 4dsp com 7 UM022 FMC176 User Manual Sr aio Bottom connector to stacked FMC TRST TCK TMS TDI TDO PRSNT_M2C_L CPLD Z Y TRST TCK TMS TDI TDO PRSNT_M2C_L Top connector to FMC carrier Figure 3 JTAG Connection 4 33 Main characteristics impedance Analogue input bandwidth 700MHz Analog outputs voltage range 1 12 Vpp 5 dBm Outputimpedance impedance 500 500 optimized output impedance for mixed mode operation output impedance 500 optimized output impedance for mixed mode operation mixed mode operation Analog output bandwidth 1 4GHz please refer to AD9129 datasheet for details External sampling clock input 10dBm lt Clock In Level lt 10dBm OdBm typical LVTTL level supported Input Level 1 8
23. iption J J 5 3 installati n u cess u tie sche ca 6 3 1 Requirements and handling instructions r 6 er eae 6 4 1 Phycisal SER 6 4 1 1 Board 6 4 1 2 6 4 2 Electrical specifications 5 42 0 9 20 6 421 EEPROMu u u 7 4 2 1 FMC erue ERU T ore eee eer eee 7 42A 7 AS Main NUR 8 4 4 Analog input channels a 9 4 5 Analog output channels eene 10 4 5 1 Analog output phase 10 46 External trigger input ms 10 47 External clock n 11 48 External reference input 11 49 External COCK u 11 4 10 dius d mre 11 410 1 PEL MSGI mrt 12 4 11 Power SUPPLY 13 5 Controlling the FMC176 uu an u u 14
24. med and read out through the I C bus Continuously operating the bus might interfere with the conversion process and result in signal distortion It is recommended to program the minimum and maximum limits in the monitoring devices and only read from the devices when the interrupt line is asserted It is recommended that the carrier card and or host software uses the power down features if the temperature is too high Parameter Device 1 Formula address 010 1111 GA 00 address 010 1100 GAz01 address 010 0011 GA 10 address 010 0000 GA 11 On chip temperature External VINO 1 8Va DAC VINO 1 External VIN1 1 8Vd DAC VINI 1 External VIN2 1 8Va ADC VIN 1 External VIN3 1 8Vd ADC VIN3 1 External VINA 3V3 CLK VINA 2 External VIN5 3V3 TCXO VIN5 2 External VIN6 VADJ VIN6 2 External VIN7 1V5 3 3 2 VIN7 Table 6 Temperature and voltage parameters UM022 www 4dsp com 18 UM022 FMC176 User Manual Sr anit 6 3 Cooling Two different types of cooling will be available for the FMC 6 3 1 Convection cooling The air flow provided by the fans of the chassis the FMC is enclosed in will dissipate the heat generated by the onboard components A minimum airflow of 300 LFM is recommended For standalone operations such as on a Xilinx development kit it is highly recommended to blow air across the FMC and ensure that the temperature of the devices is within the
25. ontrol interface The FMC is controlled from the carrier hardware through a single SPI communication bus The SPI communication bus is connected to a CPLD which has the following tasks e Distribute SPI access from the carrier hardware along the local devices 2x AD9250 A D converters 2x AD9129 D A converters 1x AD9517 Clock Tree e Enable disable internal reference based on a SPI command from the carrier hardware REF_EN e Generate SPI reset for AD9517 CLK N RESET both AD9129 DAC_RST and both AD9250 ADC_N_RST e Collect local status signals and store them in a register which can be accessed from the carrier hardware e Drive a LED according to the level of the status signals UM022 www 4dsp com 15 UM022 FMC176 User Manual Sr aio Local Side CPLD FMC Side ADCO N CS N CS DACO N CS N CS CLK N CS FMC_TO_CPLD 0 SCLK SCLK FMC_TO_CPLD01 SDIO q gt Shift register REF_EN YY ADC_N_RST Ctrl DAC_RST CLK_N_RESET ADC0_PD ADC1_PD REFMON gt LD STATUS p gt AND gt Rv ALERT gt LED Figure 10 CPLD architecture Notes e SDO on the AD9517 AD9250 and AD9129 devices is not connected SDIO is used bidirectional 3 wire SPI 5 2 SPI Programming The SPI programmable devices on the FMC can be accessed as described in their datasheet but each SPI communication cycle n
26. own to 1 5V by the DACs programmable current source When 0x0000 is written to the DAC IOUTN will be sourcing its maximum current thru the pullups resulting in a negative output voltage When the full scale value is written to the DAC the current thru IOUTN and the pullups will be at its minimum resulting in the maximum positive voltage on the output The complementary output signal IOUTP performs in a similar manner except that it is 180 degrees out of phase with the value written to the DAC The IOUTP and IOUTN signals are combined by the transformer action of the balun T4 L12 0402 E e RB PIVBA_DAC 49R9 m2 pn m T t Rag DNP i 7It8 15t ana 49R9 pur S X87 t 888 DACLIN ir iem O nF T4 ETCI 1 13 i L13 0482 Figure 5 Wideband balun output option 4 6 External trigger input An external trigger is available on the front panel MMCX connector The trigger signal connects to a buffer NB6N11S before being sent to the carrier card The buffer translates the UM022 www 4dsp com 10 UM022 FMC176 User Manual Sr aio external LVTTL signal to LVDS and connects to the FMC connector The trigger input is terminated to ground with 4 7kQ 4 7 External clock input There is one MMCX clock input on the front panel that can serve as sampling clock input Refer also to section 4 10 for more information about the clock tree Note
27. wer enable AD9517 1 for CLK power down AD9517 0 for MONITORING power enable AD7291 rst_l 1 for MONITORING power down AD7291 rst Status register REFMON AD9517 LD AD9517 STATUS AD9517 ALERT AD7291 IRQ DAC CPLD revision current b 001 Table 9 CPLD Register Map UM022 www 4dsp com 24
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