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VPC3+C User Manual

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1. Address Intel Mot Bit No Significance Write Access 00H 01H Int Req Reg 7 0 01H 00H Int Req_Reg 15 8 02H 03H Int Ack Reg 7 0 Interrupt Controller Register 03H 02H Int Ack Reg 15 8 04 05H Int Mask Reg 7 0 05H 04H Int Mask Reg 15 8 06H 07H 7 0 Setting parameters for individual bits 07H 06H 15 8 08H Mode Reg1 S 7 0 09H Mode Reg1 R 7 0 Square root value for OAH WD_BAUD_CONTROL_Val 7 0 baud rate monitoring OBH minTspa Val 7 0 minTspn time OCH Mode Reg2 7 0 Mode Register 2 Sync PW Reg 7 0 Sync Pulse Width Register Control Command value for Control Command Reg 0 comparison with SYNCH telegram Group Select value for comparison OFH Group_Select_Reg 7 0 with SYNCH telegram 10H Reserved 11H 12H Mode Reg3 7 0 Mode Register 3 13H 14H Reserved 15H Figure 4 3 Assignment of the Internal Parameter Latches for WRITE Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 4 3 Organizational Parameters RAM Memory Organization 4 The user stores the organizational parameters in the RAM under the specified addresses These parameters can be written and read Address Intel Mot Name Bit No Significance 16H R TS Adr Setup Station
2. Parameter Symbol Limits Unit DC supply voltage Vpp 0 3 to 6 0 V Input voltage Vi 0 3 to 40 3 V Output voltage Vo 0 3 to 0 3 V DC output current lo See Figure 10 4 mA Storage temperature Tstore 40 to 125 C Figure 10 1 Absolute Maximum Ratings 10 2 Recommended Operating Conditions Parameter Symbol MIN MAX Unit DC supply voltage Vpp 3 00 5 50 V Static supply current lop 100 uA Circuit ground Vss 0 0 V Input voltage Vi 0 Vpp V Input voltage HIGH level Vin 0 7 Vpp Vpp V Input voltage LOW level Vit 0 0 3 Vpp V Output voltage Vo 0 Voo V Ambient temperature TA 40 85 D Static loo current is exclusively of input output drive requirements and is measured with the clock stopped and all inputs tied to Vpp or Vss Figure 10 2 Recommended Operating Conditions 10 3 General DC Characteristics Parameter Symbol MIN TYP MAX Unit Input LOW current lit 1 1 Input HIGH current lia 1 1 Tri state leakage current loz 10 10 Current consumption 3 3V lA 36 mA Current consumption 5V la 72 mA Input capacitance Cin pF Output capacitance Cour pF Bi directional buffer capacitance Ca 5 pF Thermal Resistance 52 6 K W Figure 10 3 General DC Characteristics VPC3 C User Manual Revision 3 02 87 Copyright profichip GmbH 2014 10 Operational Specifications 10 4 Ratings for the Output Drivers S
3. 53 7 1 Set Ext Prm SAP 53 SAP 2 53 7 2 PROFIBUS sente 54 7 2 1 Acyclic Communication Relationships 54 7 2 2 Diagnosis Model 57 73 PROFIBUS DP V2 58 7 3 1 DXB Data eXchange Broadcast 58 7 3 2 0 1 MOOG un 64 7 3 3 CS Clock Synchronization 68 8 Hardware Interface 75 8 1 Universal Processor Bus Interface 75 I 75 8 1 2 Bus Interface DID sacco heureuse 75 8 1 3 Application Examples Principles 79 8 1 4 Application with 80C32 2K Byte RAM Mode 81 8 1 5 Application with 80C32 4K Byte RAM Mode 82 8 1 6 Application with 80C165 83 8 2 Dual Port RAM Controller 83 RAT eee 84 84 ASIG Thann 84 9 PROFIBUS Interface ns 85 9 1 Pin Assignment 85 9 2 Example for the RS485 Interface 86 10 Operational Specifications 87 10 1 Absolute Maximum Ratings 87 10 2 Recommended Operating Conditions
4. Address 7 6 5 4 3 2 1 0 Designation 0 0 0 0 0 0 0 1 Reset Value OCH Mode Reg 2 TD o 7 0 9 c 8 gt i o 5 5 5 gt l zi l 16 6mx m o E x gt d i 20 a zoo VPC3 C User Manual Revision 3 02 23 Copyright profichip GmbH 2014 5 ASIC Interface Mode Register 2 Address bit 7 4KB Mode size of internal RAM w 0 0 2K Byte RAM default 1 4K Byte RAM bit 6 No Check Prm Reserved disables checking of the reserved bits in w 0 DPV1 Status 2 3 of Set Prm telegram 0 reserved bits of a Set Prm telegram are checked default 1 reserved bits of a Set Prm telegram are not checked bit 5 SYNC Pol polarity of SYNC pulse for Isochron Mode only w 0 0 negative polarity of SYNC pulse default 1 positive polarity of SYNC pulse bit 4 SYNC Ena enables generation of SYNC pulse for Isochron Mode only w 0 0 SYNC pulse generation is disabled default 1 SYNC pulse generation is enabled bit 3 DX Int Port Port mode for DX Out interrupt ignored if _ set w 0 0 DX Out interrupt is not assigned to port DATAEXCH default 1 DX Out Interrupt synchronized to SYNCH telegram is assigned to port DATAEXCH bit 2 DX Int Mode Mode of DX out interrupt w 0 0 DX Out interrupt is only generated if Len_Dout_Buf is unequal 0 default 1 DX_Out interrupt
5. 19 5 1 1 Mode Register 0 NP 19 5 1 2 Mode Register 1 ecc 21 5 1 3 Mode Register 2 23 5 1 4 Mode Register 3 25 6 26 5 3 Interrupt Controller m 28 5 3 1 Interrupt Request 29 5 3 2 Interrupt Acknowledge Mask Register 32 5 4 Watchdog TII uoces rene 32 5 4 1 Automatic Baud Rate Identification 33 5 4 2 Baud Rate Monitoring 33 5 4 3 Response Time Monitoring 33 6 PROFIBUS DP Interface 35 6 1 DP Buffer Structure xin nti 35 6 2 Description of the DP 38 6 2 1 Set Slave Add SAP 55 38 p 22 Set Pm SAP 61 uu u uu u uuu DUI S ES D UE 39 p 2 9 Chk Cfg SAP has mme Gao psu xd incu pta E 43 6 24 Slave Diag SAP 60 ciiin tenentes 44 6 2 5 Write Read Data Data Exchange Default SAP 46 6 2 6 Global Control SAP 58 50 6 2 7 RD Input SAP 51 6 2 8 RD Output SAP 57 51 6 2 9 Get Cfg SAP 59 52 VPC3 C User Manual Revision 3 02 3 Copyright profichip GmbH 2014 Table of Contents 7 PROFIBUS DP Extensions
6. Figure 7 7 Overview DXB The VPC3 C can handle a maximum of 29 links simultaneously Publisher A Publisher is activated with Publisher Enable 1 in DPV1 Status 1 The time minT spa must be set to Tipi 37 tit 2 Tour All Data Exchange telegrams containing the function code 7 Send and Request Data Multicast are responded with destination address 127 If Publisher mode is not enabled these requests are ignored Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 Subscriber A Subscriber requires information about the links to its Publishers These settings are contained in a DXB Linktable or DXB Subscribertable and transferred via the Structured Prm Data in a Set Prm or Set Ext Prm telegram Each Structured Prm Data is treated like the User Prm Data and therefore evaluated by the user From the received data the user must generate DXB Link Buf and DXB Status Buf entries The watchdog must be enabled to make use of the monitoring mechanism The user must check this Bit Position 2 5 Byte Designation 7 6 5 4 3 2 1 0 0 Structured_Length 1 0 0 0 0 0 0 1 1 Structure_Type 2 0 0 0 0 0 0 0 0 Slot Number 3 0 0 0 0 0 0 0 0 Reserved 4 0 0 0 0 0 0 0 1 Version 5 Publisher Addr 6 Publisher Length 7 Sample Offset 8 Sample Length 9 further link entries 120 Figure 7 8 Format of the Structured_Prm_Data
7. Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Interface 6 During start up the VPC3 C does not go to DATA EXCH before all parameter telegrams configuration telegrams have been acknowledged If Diag Freeze Mode 1 there is no buffer change prior to sending The user can read the status of the state machine cell with the following codings for the four states Nil Dout Buf Ptri Dout Buf Ptr2 and Dout Buf Ptr3 The pointer for the current data is in the N state Bit Position Address Designation 7 6 5 4 3 2 1 0 08H F U N D Din Buffer SM Din Buffer SM Address 08H bit 7 6 F Assignment of the F Buffer 00 Nil 01 Din Buf Ptr1 10 Din Buf Ptr2 11 Din Buf bit 5 4 U Assignment of the U Buffer 00 Nil 01 Din Buf Ptr1 10 Din Buf Ptr2 11 Din Buf bit 3 2 N Assignment of the N Buffer 00 Nil 01 Din Buf Ptr1 10 Din Buf Ptr2 11 Din Buf bit 1 0 D Assignment of the D Buffer 00 Nil 01 Din Buf Ptr1 10 Din Buf Ptr2 11 Din Buf Figure 6 14 Din Buffer Management VPC3 C User Manual Revision 3 02 49 Copyright O profichip GmbH 2014 6 PROFIBUS DP Interface Bit Position Address Designation 7 6 5 4 3 2 1 0 09H 0 0 0 0 0 0 U U New_Din_Buf_ 0 1 Din_Buf_Ptr1 1 0 Din_Buf_Ptr2 1 1
8. bit 7 Reserved rw 0 bit 6 Reserved rw 0 bit 5 Res User WD Resetting the User WD Timer rw 0 1 VPC3 C sets the User WD Timer to the parameterized value User WD Value After this action VPC3 C sets Res User WD to O bit 4 En Change Cfg Buffer Enabling buffer exchange Config Buffer for rw 0 Read Config Buffer 0 With User Cfg Data Okay the Config Buffer may not be exchanged for the Read Config Buffer 1 With User Cfg Data Okay Cmd the Config Buffer must be exchanged for the Read Config Buffer bit 3 User LEAVE MASTER Request to the DP SM to go to WAIT PRM rw 0 1 The user causes the DP SM to go to WAIT PRM After this action VPC3 sets User LEAVE MASTER to 0 again bit 2 Go Offline Going into the Offline state rw 0 1 After the current request ends VPC3 C goes to the Offline state and sets Go Offline to 0 again bit 1 EOI End of Interrupt rw 0 1 VPC3 C disables the interrupt output and sets EOI to 0 again bit 0 Start VPC3 Exiting the Offline state rw 0 1 VPC34C exits offline and goes to Passive Idle In addition the Idle Timer and Watchdog Timer are started and Go Offline 0 is set Figure 5 3 Coding of Mode Register 1 22 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 ASIC Interface 5 5 1 3 Mode Register 2 Setting parameters for Mode Register 2 may take place in the Offline State only like Mode Register 0 Bit Position
9. 3 0 0 0 0 0 0 0 Status Specifier 4 Publisher Addr Link Link_ Data_ Status Error D Exist 6 further link entries 61 Link Status bit 7 Link Status 1 active valid data receipt during last monitoring period 0 not active no valid data receipt during last monitoring period DEFAULT bit 6 Link Error 0 no faulty Broadcast data receipt DEFAULT 1 wrong length error occurred by reception bit O Data Exist 0 no correct Broadcast data receipt during current monitoring period DEFAULT 1 error free reception of Broadcast data during current monitoring period Figure 7 10 DXB Link Status Buf specific link is grey scaled Processing Sequence VPC3 C processes DXBout Buffers like the Dout Buffers The only difference is that the DXBout Buffers are not cleared by the VPC3 C The VPC3 C writes the received and filtered broadcast data in the D buffer The buffer contains also the Publisher Address and the Sample Length After error free receipt the VPC3 C shifts the newly filled buffer from D to N In addition the DXBout interrupt is generated The user now fetches the current output data from N The buffer changes from N to U with the Next DXBout Buffer Cmd VPC3 C User Manual Revision 3 02 61 Copyright O profichip GmbH 2014 7 PROFIBUS DP Extensions Bit Position Byte Designation 7 6 5 4 3 0 0 Publisher Addr 1 Sample
10. C RAM 2K 4K Byte Segment 0 Segment 1 Segment 2 8 16 bit segment addresses pointer to the buffers Segment 254 Segment 255 Building of the physical buffer address 2K Byte Mode 7 0 Segment base address 8 bit 0 0 0 0 0 Offset 3 bit 10 0 Physical address 11 bit 4K Byte Mode 7 0 Segment base address 8 bit 01010 0 Offset 4 bit T 11 0 Physical address 12 bit 14 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Memory Organization 4 4 2 Control Parameters Latches Registers These cells can be either read only or write only In the Motorola Mode the VPC3 C carries out address swapping for an access to the address locations OOH 07H word registers That is the VPC3 C internally generates an even address from an odd address and vice versa Address Intel Mot Name Bit No Significance Read Access 00H 01H Int Req Reg 7 0 01H 00H Int Req Reg 15 8 Interrupt Controller Register 02H 03H Int Reg 7 0 03H 02H _ Int Reg 15 8 04H 05H Status Reg 7 0 Status Register 05H 04H Status Reg 15 8 06H 07H Mode Reg 0 7 0 Mode Register 0 07H 06H Mode Reg 0 15 8 Buffer assignment of
11. User Prm Data first with byte 10 VPC3 C User Manual Revision 3 02 39 Copyright O profichip GmbH 2014 6 PROFIBUS DP Interface Bit Position 1 Byte Designation 7 6 5 4 3 2 1 0 TD TD TD 15818 0 9 ol 9 o 5 Station Status GS a o 7 0 gt 2 tr c cc cc 1 WD Fact 1 2 WD Fact 2 3 minTspr 4 Ident_Number_High 5 Ident_Number_Low 6 Group Ident lo D D a c 7 55 0 5 8 0 0 a 5 8 5 Spec User Prm Byte c 5 Ez 1 DPV1 Status 1 aw zu QO 2o6 26 L ja ao 8 DPV1 Status 2 9 DPV1 Status 3 10 User Prm Data 243 Figure 6 5 Format of the Set Prm Telegram 40 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Interface 6 Spec User Prm Byte DPV1 Status 1 bit 7 DPV1 Enable 0 DP V1 extensions disabled default 1 DP V1 extensions enabled bit 6 Fail Safe 0 Fail Safe mode disabled default 1 Fail Safe mode enabled bit 5 Publisher Enable 0 Publisher function disabled default 1 Publisher function enabled bit 4 3 Reserved To be parameterized with 0 bit 2 WD Base Watchdog Time Base 0 Watchdog time base is 10 ms default 1 Watchdog time base is 1 ms bit 1 Dis Stop Control Disable Stop bit Control 0 Stop bit monitoring in the receiver is enabled
12. VPC3 C offers two Diagnosis Buffers The user enters the updated diagnosis data into these buffers One Diagnosis Buffer is always assigned to the VPC3 C The Bus Interface Unit is a parameterizable synchronous asynchronous 8 bit interface for various Intel and Motorola microcontrollers processors The user can directly access the internal 2K 4K Byte RAM or the parameter latches and control registers via the 11 12 bit address bus Procedure specific parameters Station Address control bits etc must be transferred to the Parameter Registers and to the Mode Registers after power on The MAC status can be observed at any time in the Status Register Various events e g various indications error events etc are entered in the Interrupt Controller These events can be individually enabled via a mask register Acknowledgement takes place by means of the acknowl edge register The VPC3 C has a common interrupt output VPC3 C User Manual Revision 3 02 7 Copyright O profichip GmbH 2014 2 Functional Description The integrated Watchdog Timer is operated in three different states BAUD SEARCH BAUD CONTROL and DP CONTROL The Micro Sequencer MS controls the entire process It contains the DP Slave state machine DP SM The integrated 4K Byte RAM that operates as a Dual Port RAM contains procedure specific parameters buffer pointer buffer lengths Station_Address etc and the data buffers In the UART the parallel data f
13. address locations The Organizational Parameters are located in RAM beginning with address 16H The entire buffer structure for the DP SAPs is based on these pa rameters n addition general parameter data Station Address Ident Number etc and status information Global Control command etc are also stored in these cells Corresponding to the parameter setting of the Organizational Parameters the user generated buffers are located beginning with address 40H All buffers or lists must begin at segment addresses 8 bytes segmentation for 2K Byte mode 16 bytes segmentation for 4K Byte mode Address Function 000H Control Parameters latches registers 21 bytes LIESS UD RU CRUS 015H 016H Organizational Parameters 42 bytes O3FH DP buffers Data in 3 Data out 3 Diagnosis data 2 Parameter data 1 Configuration data 2 Auxiliary buffers 2 SSA buffer 1 DP V1 buffer SAP List 1 Indication Response buffers DP V2 buffer DXB out 3 DXB buffers 2 CS buffers 1 040H LIII Figure 4 1 Memory Table Data in means input data from DP Slave to DP Master Data out means output data from DP Master to DP Slave number of buffers depends on the entries in the SAP List DXB out means input data from another DP Slave slave to slave communication VPC3 C User Manual Revision 3 02 13 Copyright O profichip GmbH 2014 4 Memory Organization Internal VPC3
14. 0 The interrupt inactive time is at least 1 us long 1 The interrupt inactive time is at least 1 ms long bit 8 DP Mode DP Mode enable rw 0 0 DP_Mode is disabled 1 DP Mode is enabled VPC3 C sets up all DP SAPs default configuration Figure 5 2 Coding of Mode Register 0 High Byte 5 1 2 Mode Register 1 Some control bits must be changed during operation These control bits are combined in Mode Register 1 and can be set independently of each other Mode Reg 1 S or can be reset independently of each other Mode Reg 1 Separate addresses are used for setting and resetting A logical 1 must be written to the bit position to be set or reset For example to set START VPC3 write a 1 to address 08H in order to reset this bit write a 1 to address 09H VPC3 C User Manual Revision 3 02 21 Copyright O profichip GmbH 2014 5 ASIC Interface Bit Position Address Designation 7 6 5 4 3 2 1 0 08H Mode Reg 1 S gt d aoa 70 z SS u if OM IE N o o 24 lt O o oo cgo O rau ra c gt 09H w Mode Reg_1_R 5 lt 7 0 Cir cee g g B 3 E ps 9 5199 sa _ 8 See below 8 89 lt di or r2 uo 2z o Ep gt orcoqing Mode Register 1 Set Address 08H
15. 0 Seconds 2 0 since 1 1 1900 0 00 00 0 or since 7 2 2036 6 28 16 if value Ox9dff4400 Clock Value 7 Fraction Part of Seconds 2 0 Time Event Base is 1 232 Seconds Seconds 2 0 since 1 1 1900 0 00 00 8 or since 7 2 2036 6 28 16 if value Ox9dff4400 Clock Value 15 Fraction Part of Seconds 2 0 previous TE Base is 1 2 Seconds t D 16 C CV Clock Value Status1 5 5 17 SWT SYF Clock Value Status2 O O Figure 7 22 Format of Clock Value Processing Sequence The Clock Sync Interval is a time for monitoring and has to be written into the Clock Sync Buffer by the user The Time Receiver state machine in the VPC3 C is started after this write access The value for Clock Sync Interval is locked until the next LEAVE MASTER or a new parameterization occurs In addition it can be unlocked if the user set the Stop Clock Sync in Command byte VPC3 C User Manual Revision 3 02 69 Copyright O profichip GmbH 2014 7 PROFIBUS DP Extensions Following to a clock synchronization sequence the Clock Sync interrupt will be asserted Further information is contained in the Status byte If an overflow of the Receive Delay Timer occurs the Status byte will be cleared The VPC3 C cannot write new data to the Clock Sync Buffer until the user has acknowledged the Clock Sync interrupt Hence to ensure no new data overwrites the buffer the user sho
16. 10 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Pin Description 3 3 2 Pinout VPC3 C has a 44 pin PQFP housing with the following pinout m lt 0 E o OQ o 0 0 o ui O m m x m E x m 3 x lt lt r lt gt r lt lt gt 33 23 34 22 XTESTO DB7 XTEST1 DB6 RESET DB5 AB4 DB4 VSS VDD VDD VSS AB3 DB3 AB2 DB2 AB5 XREADY XDTACK AB1 XDATAEXCH SYNC ABO e DB1 44 SL 12 1 11 rzxosctrcoo T lt I M TEPFEPEPEEPEE gt n OE amp x 2 O cc x lt Figure 3 3 VPC3 C Pinout For details about package outline and dimensions see section 10 8 VPC3 C User Manual Revision 3 02 11 Copyright profichip GmbH 2014 3 Pin Description Notes 12 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 4 1 Memory Organization 4 Overview The internal Control Parameters are located in the first 21 addresses The latches registers either come from the internal controller or influence the controller Certain cells are read or write only The internal working cells which are not accessible by the user are located in RAM at the same
17. Clock Value which contains the actual time when the Time Event was sent plus the send delay time tsp By receiption of the second message the Clock Sync interrupt will be generated To achieve the most accuracy the receive delay timer is running until the user reads the Clock Sync Buffer The VPC3 C only synchronizes the received telegrams the system time management is done by the user The user has also to account for the time after the receive delay timer has been read till the update of the system time tpp process delay time The time for transmission delay CS Delay Time and the Clock Sync Interval are communicated to the VPC3 C by a Structured Prm Data block The CS Delay Time is used by the user to calculate the system time ts Clock Value Time Event tpt tap tpp Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 Bit Position 1 Byte Designation 7 6 5 4 3 2 1 0 0 Structured Length 1 0 0 0 0 1 0 0 0 Structure Type 0 0 0 0 0 0 0 0 Slot Number Reserved O N o o o o Clock Sync Interval 5 Time Base 10 ms Seconds 2 0 F CS Delay Time Fraction Part of Seconds 2 0 13 xb can be omitted Base is 1 2 Seconds Figure 7 21 Format of Structured Prm Data with Time AR Bit Position A Byte Designation 7 6 5 4 3 2 1
18. Copyright profichip GmbH 2014 7 1 PROFIBUS DP Extensions Set Ext Prm SAP 53 SAP 61 The PROFIBUS DP extensions require three bytes to implement the new parameterization function The bits of the Spec User Prm Byte are included Bit Position Byte Designation 7 6 5 4 3 2 1 0 0 p DPV1 Status 1 DPV1 Enable Fail Safe Publisher Enable Reserved Reserved WD Base Dis Sto Control Dis Start Control Specific Alarm Enable g Alarm g Mode DPV1 Status 2 Enable Update Alarm Manufacturer Status Alarm Enable Chk Cf Enable _ Diagnostic Alarm Process Alarm Enable Pull Plu Enable q 0 Alarm Mode DPV1 Status 3 IsoM Re Prm_ Structure 10 User Prm Data 243 Figure 7 1 Set Prm with DPV1 Status bytes If the extensions are used the bit Spec Clear Mode in Mode Register 0 serves as Fail Safe required Therefore it is used for a comparison with the bit Fail Safe in parameter telegram Whether the DP Master supports the Fail Safe mode or not is indicated by the telegram bit If the DP Slave requires Fail Safe but the DP Master doesn t the Prm Fault bit is set If the VPC3 C should be used for DXB IsoM or redundancy mode the parameterization data must be packed in a Structured Prm Data block to distinguish between the User Prm Data The bit Prm Structure indicates this If redundancy sh
19. Data Not Okay acknow ledgements are read accesses to defined registers with the relevant signals e User Prm Finished No additional parameter telegram is present e Prm Conflict An additional parameter telegram is present processing again e Not Allowed Access not permitted in the current bus state Bit Position J Address Designation 7 6 5 4 3 2 1 0 User Prm OEH 0 0 0 0 0 0 U y Data Okay 0 0 User Prm Finished 0 1 Prm Conflict 1 1 Not Allowed Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Interface 6 Bit Position Address Designation 7 6 5 4 3 2 1 0 User Prm OFH 0 0 0 0 0 0 U y EE Data Not Okay 0 0 User Prm Finished 0 1 Prm Conflict 1 1 Not Allowed Figure 6 7 Coding of User Prm Not Okay Cmd If another Set Prm telegram is supposed to be received in the meantime the signal Prm Conflict is returned for the positive or negative acknowledgement of the first Set Prm telegram Then the user must repeat the validation because the VPC3 C has made a new Parameter Buffer available 6 2 3 Chk_Cfg SAP 62 The user checks the correctness of the configuration data After receiving an error free Cfg telegram the VPC3 C exchanges the Aux Buffer 1 2 all data bytes are entered here for the Config Buffer stores the input data length in R Len Cfg Data and generates
20. Din_Buf_Ptr3 Figure 6 15 Coding of New_Din_Buf_Cmd User_Watchdog_ Timer After start up DATA EXCH state it is possible that the VPC3 C continually answers Data_Exchange telegrams without the user fetching the received Dout Buffers or making new Din Buffers available If the user processor hangs up the DP Master would not receive this information Therefore a User_Watchdog_Timer is implemented in the VPC3 C This User_WD_Timer is an internal 16 bit RAM cell that is started from a user parameterized value R User WD Value and is decremented by the VPC3 C with each received Data Exchange telegram If the timer reaches the value 0000H the VPC3 C goes to the WAIT PRM state and the DP SM carries out a LEAVE MASTER The user must cyclically set this timer to its start value Therefore Res User WD 1 must be set in Mode Register 1 Upon receipt of the next Data Exchange telegram the VPC3 C again loads the User WD Timer to the parameterized value R User WD Value and sets Res User WD 0 Mode Register 1 During power up the user must also set Res User WD 1 so that the User WD Timer is set to its parameterized value 6 2 6 Global Control SAP 58 The VPC3 C processes the Global Control telegrams like already described The first byte of a valid Global Control is stored in the R GC Command RAM cel The second telegram byte Group Select is processed internally The interrupt behavior regarding to the r
21. Figure 7 6 FDL Interface of VPC3 C e g same Buffer for Indication and Response 7 2 2 Diagnosis Model The format of the device related diagnosis data depends on the GSD keyword DPV1 Slave in the GSD If DPV1 Slave 1 alarm and status messages are used in diagnosis telegrams Status messages are required by the Data eXchange Broadcast service for example Alarm Ack is used as the other acyclic services VPC3 C User Manual Revision 3 02 57 Copyright O profichip GmbH 2014 7 PROFIBUS DP Extensions 7 3 7 3 1 58 PROFIBUS DP V2 DXB Data eXchange Broadcast The DXB mechanism enables a fast slave to slave communication A DP Slave that holds input data significant for other DP Slaves works as a Publisher The Publisher can handle a special kind of Data Exchange request from the DP Master and sends its answer as a broadcast telegram Other DP Slaves that are parameterized as Subscribers can monitor this telegram A link is opened to the Publisher if the address of the Publisher is registered in the linktable of the Subscriber If the link have been established correctly the Subscriber can fetch the input data from the Publisher DP Master Classi Request 7 Response DA 127 Data Exchange with Data Exchange with DR LI Data DP Master Class 1 DP Master Class 1 from Publisher Dout Din Dout Din DXBout DP Slave Publisher DP Slave Subscriber k a
22. New Diag Cmd to make the request to exchange the Diagnosis Buffers The user receives confirmation of the buffer exchange with the Diag Buffer Changed interrupt When the buffers are exchanged the internal Diag Flag is also set For an activated Diag Flag the VPC3 C responds during the next Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Interface 6 Data Exchange with high priority response data That signals the DP Master that new diagnosis data are present at the DP Slave The DP Master then fetches the new diagnosis data with a Slave Diag telegram Then the Diag Flag is cleared again However if the user signals Diag Stat Diag 1 that is static diagnosis see the structure of the Diagnosis Buffer the Diag Flag still remains activated after the relevant DP Master has fetched the diagnosis The user can poll the Diag Flag in the Status Register to find out whether the DP Master has already fetched the diagnosis data before the old data is exchanged for the new data According to IEC 61158 Static Diagnosis should only be used during start up Status coding for the diagnosis buffers is stored in the Diag Buffer SM control parameter The user can read this cell with the possible codings for both buffers User VPC3 or VPC3 Send Mode Bit Position Address Designation 7 6 5 4 3 2 1 0 OCH 0 0 0 0 Diag Buf2 Diag_Buf1 Diag Buffer SM Diag Buffer S
23. With this command the output data is deleted D and is changed to N bit 0 Reserved Figure 6 16 Format of the Global Control Telegram 6 2 7 RD Input SAP 56 The VPC3 C fetches the input data like it does for the Data Exchange telegram available Prior to sending N is shifted to D if new input data are in N For Diag Freeze Mode 1 there is no buffer change 6 2 8 RD Output SAP 57 The VPC3 C fetches the output data from the Dout Buffer in U The user must preset the output data with 0 during start up so that no invalid data can be sent here If there is a buffer change from N to U through the VPC3 C User Manual Revision 3 02 51 Copyright O profichip GmbH 2014 6 PROFIBUS DP Interface Next Dout Buffer Cmd between the first call up and the repetition the new output data is sent during the repetition 6 2 9 Get Cfg SAP 59 52 The user makes the configuration data available in the Read Config Buffer For a change in the configuration after the Chk Cfg telegram the user writes the changed data in the Config Buffer sets En Change Cf g buffer 1 see Mode Register 1 and the VPC3 C then exchanges the Config Buffer for the Read Config Buffer If there is a change in the configuration data during operation for example for a modular DP systems the user must return with Go Offline command see Mode Register 1 to WAIT PRM Revision 3 02 VPC3 C User Manual
24. XRD and from the rising edge of the write signal XWR ALE AB10 0 DB7 0 address XRD ALE AB10 0 DB7 0 XWR Figure 10 10 Synchronous Intel Mode WRITE XRD 1 VPC3 C User Manual Revision 3 02 91 Copyright O profichip GmbH 2014 10 Operational Specifications Voo 3 3 V Vppz5V No Parameter MIN MAX MIN MAX Unit 1 ALE pulsewidth 10 10 ns 2 ALE J to XRD 20 20 ns 3 Address to ALE 4 setuptime 10 10 ns 4 Address holdtime after ALE 4 10 10 ns 5 XRD 1 to data valid 103 97 ns 6 XRD pulsewidth 115 115 ns 7 XRD to ALE T 10 10 ns 8 address AB7 0 holdtime after XRD XWR f 5 5 ns 9 data holdtime after XRD T 4 16 4 13 ns 10 XRD XWR cycletime 155 155 ns 11 ALE J to XWR 20 20 ns 12 XWR pulsewidth 83 83 ns 13 data setuptime to XWR f 10 10 ns 14 XWR f to ALE f 10 10 ns 15 data holdtime after XWR T 10 10 ns Figure 10 11 Timing Synchronous Intel Mode 92 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Operational Specifications 10 10 7 3 Timing in the Asynchronous Intel Mode In the asynchronous Intel mode the VPC3 C acts like a memory with ready logic The access time depends on the type of access The request for an access to the VPC3 C is generated from the falling edge of the read signal XRD or the rising edge of the
25. be used in this mode When using HC11 types with a multiplexed bus the address signals AB7 0 must be generated from the DB7 0 signals externally Asynchronous bus timing with evaluation of the XREADY signal 8 bit non multiplexed bus DB7 0 AB11 0 in 4K Byte mode The internal VPC3 C address decoder is disabled the XCS input is used instead Chip select logic is available and programmable in all microcontrollers mentioned above AB11 must be connected to XWR E CLOCK pin 2 in 4K Byte mode as this is the additional address bus signal in this mode In 2K Byte mode this pin is not used and should be pulled to GND VPC3 C User Manual Revision 3 02 77 Copyright profichip GmbH 2014 8 Hardware Interface 78 Synchronous Motorola Mode Motorola microcontrollers like the HC11 types K N M F1 or the HC16 and HC916 types with programmable E Clock timing can be used in this mode When using HC11 types with a multiplexed bus the address signals AB7 0 must be generated from the DB7 0 signals externally Synchronous bus timing without evaluation of the XREADY signal 8 bit non multiplexed bus DB7 0 AB10 0 AB11 0 in 4K Byte mode The internal VPC3 C address decoder is disabled the XCS input is used instead For microcontrollers with chip select logic K F1 HC16 and HC916 the chip select signals are programmable regarding address range pri ority polarity and window width in the write cycle or read cycle For microcontr
26. default 1 Stop bit monitoring in the receiver is disabled bit 0 Dis Start Control Disable Start bit Control 0 Start bit monitoring in the receiver is enabled default 1 Start bit monitoring in the receiver is disabled Figure 6 6 Spec User Prm Byte DPV1 Status 1 It is recommended not to use the DPV1 Status bytes bytes 7 9 for user parameter data VPC3 C User Manual Revision 3 02 41 Copyright O profichip GmbH 2014 6 PROFIBUS DP Interface 42 Parameter Data Processing Sequence In the case of a positive validation of more than seven data bytes the VPC3 C carries out the following reaction The exchanges Aux Buffer 1 2 all data bytes are entered here for the Parameter Buffer stores the input data length in R Len Prm Data and triggers the New Prm Data interrupt The user must then check the User Prm Data and either reply with User Prm Data Okay or with User Prm Data Not Okay Cmd The entire telegram is entered in this buffer The user parameter data are stored beginning with data byte 8 or with byte 10 if DPV1 Status bytes used The user response User Prm Data Okay Cmd or User Prm Data Not Okay clears the New Prm Data interrupt The user cannot acknowledge the New Prm Data interrupt in the IAR register With the User Prm Data Not Okay Cmd message relevant diagnosis bits are set and the SM branches to WAIT PRM The User Prm Data Okay and User Prm
27. entry is 7FH Byte 3 Service Supported Indicates the permitted FDL service 00 all FDL services allowed Byte 4 Ind Buf Ptr 0 pointer to Indication Buffer 0 Byte 5 Ind Buf Ptr 1 pointer to Indication Buffer 1 Byte 6 Resp Buf Ptr pointer to Response Buffer Figure 7 3 SAP List entry In addition an Indication and Response Buffer are needed Each buffer consists of a 4 byte header for the buffer management and a data block of configurable length VPC3 C User Manual Revision 3 02 55 Copyright O profichip GmbH 2014 7 PROFIBUS DP Extensions Bit Position Byte Designation 7 6 5 4 3 2 1 0 0 m D Control 5 2 oc z 1 Max Length 2 Length 3 Function Code SAP List entry Byte 0 Control bits for buffer management USER buffer assigned to user IND indication data included in buffer RESP response data included in buffer INUSE buffer assigned to VPC3 C Byte 1 Max Length length of buffer Byte 2 Length length of data included in buffer Byte 3 Function Code function code of the telegram Figure 7 4 Buffer Header Processing Sequence A received telegram is compared with the values in the SAP List If this check is positive the telegram is stored in an Indication Buffer with the INUSE bit set In case of any deviations the VPC3 C responses with no service activated RS or if no free buffer is available with
28. like 80C51 52 32 and compatible processor series from several manufacturers can be used Synchronous bus timing without evaluation of the XREADY signal 8 bit multiplexed bus ADB7 0 The lower address bits AB7 0 are stored with the ALE signal in an in ternal address latch The internal CS decoder is activated VPC3 C generates its own CS signal from the address lines AB10 3 The VPC3 C selects the relevant address window from the AB2 0 signals A11 from the microcontroller must be connected to XCS pin 1 in 4K Byte mode as this is the additional address bus signal in this mode In 2K Byte mode this pin is not used and should be pulled to VDD Asynchronous Intel Mode In this mode various 16 8 bit microcontroller series like Intel s x86 Siemens 80C16x or compatible series from other manufacturers can be used Asynchronous bus timing with evaluation of the XREADY signal 8 bit non multiplexed bus DB7 0 AB10 0 AB11 0 in 4K Byte mode The internal VPC3 C address decoder is disabled the XCS input is used instead External address decoding is always necessary External chip select logic is necessary if not present in the microcon troller A11 from the microcontroller must be connected to ALE AS pin 24 in 4K Byte mode as this is the additional address bus signal in this mode In 2K Byte mode this pin is not used and should be pulled to GND Asynchronous Motorola Mode Motorola microcontrollers like the HC16 and HC916 can
29. the New Cfg Data interrupt Then the user has to check the User Config Data and either respond with User Cfg Data Okay Cmd or with User Cfg Data Not Okay The pure data is entered in the buffer in the format of the standard The user response User Cfg Data Okay Cmd or the User Cfg Data Not Okay response clears the New Cfg Data interrupt The user cannot acknowledge the New Cfg Data in the IAR register If an incorrect configuration is reported several diagnosis bits are changed and the VPC3 C branches to state WAIT PRM For a correct configuration the transition to DATA EXCH takes place immediately if trigger counters for the parameter telegrams and configuration telegrams are at 0 When entering into DATA EXCH the VPC3 C also generates the Go Leave DATA EXCH Interrupt If the received configuration data from the Config Buffer is supposed to result in a change to the Read Config Buffer contains the data for the Get telegram the user have to make the new Read Config data available in the Read Config Buffer before the User Cfg Data Okay Cmd acknowledgement that is the user has to copy the new configuration data into the Read Config Buffer During acknowledgement the user receives information about whether there is a conflict or not If another Chk Cfg telegram was supposed to be VPC3 C User Manual Revision 3 02 43 Copyright O profichip GmbH 2014 6 PROFIBUS DP Interface received in the meantime t
30. 14 Operational Specifications 10 VDD 3 3 V VDD 5 V No Parameter MIN MAX MIN MAX Unit 43 address setuptime to AS 4 0 0 ns 44 AS J to data valid 103 97 ns 45 AS pulsewidth read access 115 115 ns 46 R W setuptime to AS Y 10 10 ns 47 XCS setuptime to AS 4 5 5 ns 48 to XDTACK J Normal Ready 132 126 ns 49 AS to XDTACK Early Ready 111 105 ns 50 last AS J to XCS 1 93 93 ns 51 AS cycletime 125 125 ns 52 address holdtime after AS T 10 10 ns 53 Data holdtime after AS T 4 16 4 13 ns 54 ASinactive time 10 10 ns 55 W holdtime after AS T 10 10 ns 56 XCS holdtime after AS 0 0 ns 57 XDTACK holdtime after AS T 6 21 5 16 ns 58 Data setuptime to AS f 10 10 ns 59 AS pulsewidth write access 83 83 ns 60 Data holdtime after AS T 10 10 ns Figure 10 20 Timing Asynchronous Motorola Mode VPC3 C User Manual Revision 3 02 99 Copyright profichip GmbH 2014 10 Operational Specifications 10 8 Package The 44 pin PQFP package of the VPC3 C is compliant to the Reduction of Hazardous Substances RoHS Directive of the European Parliament Please see the following figures for outlines and dimensions at a E1 E F 1 A4 7 C SEATING PLANE 0 1 ofc U eC H Figure 10 21 Package Drawing 100 Revision 3 02 VPC3 C User Manual Copyright O profich
31. 2014 ASIC Interface 5 5 1 Mode Registers In the VPC3 C parameter bits that access the controller directly or which the controller directly sets are combined in three Mode Registers 0 1 2 and 3 5 1 1 Mode Register 0 Setting parameters for Mode Register 0 may take place in the Offline state only for example after power on The VPC3 C may not exit the Offline state until Mode Register 0 all Control and Organizational Parameters are loaded START VPC3 1 in Mode Register 1 Bit Position Address 7 6 5 4 3 2 1 0 Designation 06H Mode Reg 0 Intel gt 3 o E 7 0 E e lt ss yelda gt amp amp OE See below for o5 55 2110381 Q 26 coding Co d o ao ao Bit Position I 1 Address 15 14 13 12 11 10 9 8 Designation 07H il E Mode Reg 0 g gle 15 Intel 9 Blo e 2 5 8 gt E 5 O AS 5 158 Z E lo gt See below for o amp oS9 o l 5 loo co 5 5 coding gt 2 um a If Spec Clear Mode 1 Fail Safe Mode the VPC3 C will accept Data Exchange telegrams without any output data data unit length 0 in the state DATA EXCH The reaction to the outputs can be parameterized in the parameterization telegram When a large number of parame
32. 3 Copyright O profichip GmbH 2014 7 PROFIBUS DP Extensions Notes 74 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 8 1 8 1 1 Hardware Interface 8 Universal Processor Bus Interface Overview The VPC3 C has a parallel 8 bit interface with an 11 bit address bus The VPC3 C supports all 8 bit processors and microcontrollers based on the 80C51 52 80C32 from Intel the Motorola HC11 family as well as 8 16 bit processors or microcontrollers from the Siemens 80C166 family X86 from Intel and the HC16 and HC916 family from Motorola Because the data formats from Intel and Motorola are not compatible VPC3 C automatically carries out byte swapping for accesses to the following 16 bit registers Interrupt Register Status Register and Mode Register 0 and the 16 bit RAM cell R User WD Value This makes it possible for a Motorola processor to read the 16 bit value correctly Reading or writing takes place as usual through two accesses 8 bit data bus The Bus Interface Unit BIU and the Dual Port RAM Controller DPC that controls accesses to the internal RAM belong to the processor interface of the VPC3 C The VPC3 C is supplied with a clock pulse rate of 48MHz In addition a clock divider is integrated The clock pulse is divided by 2 Pin DIVIDER 1 or 4 Pin DIVIDER 0 and applied to the pin CLKOUT 2 4 This allows the connection of a slower controller without additional expenditures in a lo
33. 4 VDD 3K3 28 MODE gt 94 ALE XANT uc gt 2R 2 wn XRD 4 4 XRD VDD 34 4 XrESTO xcrs _33 1K GND VDD 3 35 XTEST connect to VDD or GND 3 DIVIDER RxD 30 lt 5485 ABS 441 ABO RTS 27 RS485 43 ABI TxD RS485 AB10 41 apo ABI fey ti ADBO AB12 40 aps pat 32 ADB1 ABIS i 37 pas di ADB2 AB14 4 Des 18 ADB3 AB15 8d n DB4 9 ADB4 x SEN Des 2 ADB5 AB 15 8 m 29 BE ADB6 He gt 36 ABS HET ADB7 GND 4K 10 AB10 gt DB 7 0 Figure 8 8 80C32 Application in 4K Byte mode The internal chipselect is activated when the address inputs AB 10 3 of the VPC3 C are set to 0 In the example above the start address of the VPC3 C is set to 2000H Processor AD 7 0 AB 10 8 AB 11 AB 15 12 VPC3 B 8 Z all bits zero gt CS 2 gt internal address 1 decoder internal chip select Figure 8 9 Internal Chipselect Generation in Synchronous Intel Mode 4K Byte RAM 82 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Hardware Interface 8 8 1 6 Application with 80C165 VPC3 48 MHz 5 GND 1K 8 XINTIMOT cu 7 gt gt 36
34. 5 Interface To minimize the capacity of the bus lines the user should avoid additional capacities The typical capacity of a bus station should be 15 25 pF SHIELD a 9 8 219 9 9 9 EA TT be o o a a 3 8 9 gt 5 2 EE k 2 TT S e 2 gt o o 218 2 x 8 2 ot 9 2 gt afolha Q mo 9 gt Bu PE m i 8 6 88 o 28 2 1a 2 8 FE a z 5 o By 2 9 2 zr 0 g 2 gu Pet gt gt 8 28 o o 1 3 a 9 39 lo 28 2 2 T 1 88 2 7 88 2 9 5 128 2 la o o 8 z 9 g gt m pu om 8 8 gt gt a a 8 5 99 S 9 2 8 2 Be le M NOE M 3 a a lS 5 8 oo 258 8 258 5 81 gt gt 823 8 gt 568 e o Jj A 2a e f S lt z gt x 2 o TA ONE Si a z m Q n ka a 8 m lt x a amp gt Figure 9 2 Example for the RS485 Interface 86 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Operational Specifications 10 10 1 Absolute Maximum Ratings
35. 87 10 3 General DC Characteristics 87 10 4 Ratings for the Output Drivers 88 10 5 DC Electrical Characteristics Specification for 5V Operation 88 10 6 DC Electrical Characteristics Specification for 3 3V Operation 89 10 7 Timing Characteristics 90 10 7 1 System Bus Interface 90 10 7 2 Timing in the Synchronous Intel Mode 91 10 7 3 Timing in the Asynchronous Intel Mode 93 10 7 4 Timing in the Synchronous Motorola Mode 95 10 7 5 Timing in the Asynchronous Motorola Mode 97 10 8 oco co c T HE 100 10 9 Processing Instructions ena Seitan neret ies 102 10 100rdering Information r 102 4 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Introduction 1 Profichips VPC3 C is a communication chip with processor interface for intelligent PROFIBUS DP Slave applications It s an enhancement of the VPC3 B in terms of protocol functions and power consumption The VPC3 C handles the message and address identification the data security sequences and the protocol processing for PROFIBUS DP In addition the acyclic communication and alarm messages described in DP V1 extension are supported Furthermore the slave to slave communication Data eXchange Broadcast DXB and the Isochro
36. 94 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Operational Specifications 10 10 7 4 Timing in the Synchronous Motorola Mode If the CPU is clocked by the VPC3 C the output clock pulse CLKOUT 2 4 must be 4 times larger than the E Clock That is a clock pulse signal must be present at the CLK input that is at least 10 times larger than the desired system clock pulse E Clock The Divider Pin must be connected to 0 divider 4 This results in an E Clock of 3 MHz The request for a read access to the VPC3 C is derived from the rising edge of the E Clock in addition XCS 0 W 1 The request for write access is derived from the falling edge of the E Clock in addition XCS 0 0 lt a E CLOCK AB10 0 DB7 0 data valid RW lt 9 xcs ado Figure 10 15 Synchronous Motorola Mode READ AS 1 VPC3 C User Manual Revision 3 02 95 Copyright O profichip GmbH 2014 10 Operational Specifications lt gt E CLOCK 33 lt ARI 41 4 42 DB7 0 data valid RW 25 4 39 35 XCS 36 gt lt 40 Figure 10 16 Synchronous Motorola Mode WRITE AS 1 VDD 3 3 V VDD 5V No Parameter MIN MAX MIN MAX Unit 31 E Clock pulse width 136 7 136 7 ns 33 Address setuptime A10 0 to E Clock T 10 10 ns 37 Address holdtime after E Cloc
37. Address of the VPC3 C 174 SAP tis Pr 18H 19H R User WD Value 7 0 In DP Mode an internal 16 bit watchdog 19H 18H User WD Value 15 8 timer monitors the user 1AH R Len Dout Buf Length of the 3 Dout Buf 1BH Dout Ptr1 Segment base address of Dout_Buf 1 1CH R Dout Buf Ptr2 Segment base address of Dout 2 1DH R Dout Buf Ptr3 Segment base address Dout Buf 1EH R Len Din Buf Length of the Din 1FH R Din Buf Ptr1 Segment base address of Din Buf 1 20H R Din Buf Ptr2 Segment base address of Din Buf 2 21H R Din Buf Ptr3 Segment base address of Din 22H R Len DXBout Buf Length of the 3 DXBout Buf 23H DXBout Buf Ptr1 Segment base address of DXBout 1 24H Len Diag Buf1 Length of Diag Buf 1 25H R Len Diag Buf2 Length of Diag_Buf 2 26H R Diag Buf Ptr1 Segment base address of Diag Buf 1 27H R Diag Buf Ptr2 Segment base address of Diag Buf 2 Length of Aux 1 and the 28H Len Se ee example Read_Cfg_Buf Length of Aux_Buf 2 and the 29H Len Buf2 en PCIE example Read Cfg Bit array defines the assignment of the 2AH R Aux Buf Sel Aux Buf 1 and 2 to the control buffers SSA Buf Prm Buf Cfg Buf 2BH Aux Buf Ptr1 Segment base address of Aux Buf 1 2CH R Aux Buf Ptr2 Segment base address of Aux Buf 2 f Len SSA Dat i SSA But Pr 2FH R Len Prm Data Length of the input data in the Prm Buf VPC3 C User Manual Revisio
38. C3 C for sending The other Diagnosis Buffer U belongs to the user for preprocessing new diagnosis data VPC3 C User Manual Revision 3 02 35 Copyright O profichip GmbH 2014 6 PROFIBUS DP Interface 36 N U Dout Buffer k D N changed N U changed by VPC3 by User N U Din Buffer lt gt Diagnosis U Buffer Read_Config Buffer A changed by User Config Buffer Set Slave Address Buffer Parameter Buffer Figure 6 1 DP SAP Buffer Structure The VPC3 C first stores the parameter telegrams Set Slave Add and Set Ext Prm and the configuration telegram Chk Cfg in Aux Buffer 1 or Aux Buffer 2 If the telegrams are error free data is exchanged with the corresponding target buffer Set Slave Add Buffer Parameter Buffer and Config Buffer Each of the buffers to be exchanged must have the same length In the R Aux Buf Sel parameter cell see Figure 6 2 the user defines which Aux buffers are to be used for the telegrams mentioned Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Interface 6 above The Aux Buffer 1 must always be available Aux Buffer 2 is optional If the data profiles of these DP telegrams are very different for example the length of the Set Prm telegram is significantly larger than the length of the other telegrams it is suggested to make an 2 available R Aux Sel Set Prm 1 for this telegram The ot
39. H o Indicates DATA EXCH state for PROFIBUS DP LED SYNC Synchronization Signal for Isochron Mode see section 8 3 2 CPU 14 XREADY XDTACK O Ready for external CPU System CPU 15 DB2 C32 mode Data Address Bus multiplexed 16 DB3 I C O Data Bus C165 mode Data Address Bus separate CPU Memory 17 VSS 18 VDD 19 DB4 CO 20 DBS C32 mode Data Address Bus multiplexed 21 DB6 I C O ata Bus C165 mode Data Address Bus separate CPU Memory 22 DB7 I C O 0 80C166 Data Address Bus separated Ready Signal 23 MODE 117 80032 Data Address Bus multiplexed fixed Timing Configuration Pin ALE AS Address Latch C32 mode ALE Enable C165 mode 0 2K Byte RAM 24 CPU AB11 Address Bus 11 Asynchronous Intel and Synchronous Motorola Mode 4K Byte RAM C32 Mode lt log gt 0 25 AB9 Address Bus C165 Mode Address Bus CPU Memory 26 TXD Serial Transmit Port external pull up resistor required PROFIBUS Interface 27 RTS Request to Send PROFIBUS Interface 28 VSS C32 mode 0 29 AB8 KC Address Bus C165 mods Address Bus CPU Memory VPC3 C User Manual Copyright O profichip GmbH 2014 Revision 3 02 3 Pin Description Pin Signal Name In Out Description Source Destination 30 Serial Receive Port PROFIBUS Interface 31 AB7 Address Bus CPU Mem
40. Int Mode 0 w 0 0 GC Interrupt is only generated if changed GC telegram is received 1 GC Interrupt is only generated if GC telegram with changed Control Command is received Figure 5 5 Coding of Mode Register 3 VPC3 C User Manual Revision 3 02 25 Copyright O profichip GmbH 2014 5 ASIC Interface 5 2 Status Register The Status Register shows the current VPC3 C status and can be read only Bit Position Address Designation 7 6 5 4 3 2 0 04H E Status Reg Intel WD State DP State S v 7 0 e i e o2 9 S 9 See below 1 0 1 0 oc a n for coding Bit Position Address Designation 15 14 13 12 11 10 9 8 05H Status Reg Intel VPC3 Release Baud Rate 15 8 See below 3 2 1 0 3 2 1 0 for coding 26 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 ASIC Interface 5 Status Register Low Byte Address 04H Intel bit 7 6 WD State 1 0 State of the Watchdog State Machine r 00 00 BAUD_SEARCH state 01 BAUD CONTROL state 10 DP CONTROL state 11 Not possible bit 5 4 DP State 1 0 State of the DP State Machine r 00 00 WAIT PRM state 01 WAIT CFG state 10 DATA EXCH state 11 Not possible bit 3 Reserved r 0 bit 2 Diag_Flag Status of the Diagnosis Buffer ro 0 The Diagnosis Buffer had been fetched by the DP Master 1 Th
41. Length 2 Sample_Data 246 Figure 7 11 DXBout Buffer When reading the Next_DXBout_buffer_Cmd the user gets the information which buffer U buffer is assigned to the user after the change or whether a change has taken place at all Bit Position Address 7 6 5 4 3 Designation 12H F U D DXBout_Buffer_SM DXBout Buffer SM Address OAH bit 7 6 F Assignment of the F Buffer 00 Nil 01 DXBout Buf Ptr1 10 DXBout Ptr2 11 DXBout Buf Ptr3 bit 5 4 U Assignment of the U Buffer 00 Nil 01 DXBout Buf Ptr1 10 DXBout Ptr2 11 DXBout Buf Ptr3 bit 3 2 N Assignment of the N Buffer 00 Nil 01 DXBout Buf Ptr1 10 DXBout Buf Ptr2 11 DXBout Buf Ptr3 bit 1 0 D Assignment of the D Buffer 00 Nil 01 DXBout Buf Ptr1 10 DXBout Buf Ptr2 11 DXBout Buf Ptr3 Figure 7 12 DXBout Buffer Management 62 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 Bit Position R A Address Designation 7 6 5 4 3 2 1 0 13H 0 0 0 0 0 Next DXBout _ _ gt ob See coding 35 v5 below om m Next DXBout Buf Address 0BH bit 7 3 Don t care Read as 0 bit 2 State_U_Buffer State of the User Buffer 0 no new U buffer 1 new U buffer bit 1 0 Ind U Buffer Indicate
42. M Address bit 7 4 Don t care Read as 0 bit 3 2 Diag_Buf2 Assignment of Diagnosis Buffer 2 00 Nil 01 User 10 VPC3 11 VPC3_Send_Mode bit 1 0 Diag_Buf1 Assignment of Diagnosis Buffer 1 00 Nil 01 User 10 VPC3 11 VPC3_Send_Mode Figure 6 9 Diagnosis Buffer Assignment The New Diag Cmd is also a read access to a defined control parameter indicating which Diagnosis Buffer belongs to the user after the exchange or whether both buffers are currently assigned to the VPC3 C No_Buffer Diag_Buf1 Diag_Buf2 VPC3 C User Manual Revision 3 02 45 Copyright profichip GmbH 2014 6 PROFIBUS DP Interface Bit Position Address Designation 7 6 5 4 3 2 1 0 New Dia 0 0 0 0 0 0 U U i om Buffer Cmd 0 0 No Buffer 0 1 Diag 1 0 Diag Buf2 Figure 6 10 Coding of New Diag Cmd Bit Position i i Byte Designation 7 e g D D gt G a i Oo 0 A a s al l 1 2 3 4 5 Ext Diag Data user input n max 243 Figure 6 11 Format of the Diagnosis Buffer The Ext Diag Data must be entered into the buffers after the VPC3 C internal diagnosis data Three different formats are possible here device related ID related and port related If PROFIBUS DP extensions shall be used the device related diagnosi
43. RESET XDATAEX c 13 LED for Data Exchange ac gt xcs XREADY 5 1 4 a6 gt GND 1K 23 MODE GND 1K 24 ALE XANT 9 ac gt XWRL a yc gt D 4_ XRD VDD lt 34 XTESTO 5 39 1 GND 3K3 35 XrESTI connect to 3 DIVIDER 90 85485 VDD or GND ars 27 H ABO 26 185485 1 Ps 41 AB2 DBO 11 DBO AB3 40 AB3 DB1 12 DB1 ABA 37 apa pee DB2 5 42 AB5 DB3 16 DB3 k ilius ER AB7 DB5 AB8 29 ABS DB6 21 DB6 AB9 25 AB9 DB7 22 DB7 Aere 10 ean uc Dae gt AB 10 0 80 0 Figure 8 10 80C165 Application 8 2 Dual Port RAM Controller The internal 4K Byte RAM of the VPC3 C is a single port RAM An integrated Dual Port RAM controller however permits an almost simultaneous access of both ports bus interface and microsequencer interface When there is a simultaneous access of both ports the bus interface has priority This guarantees the shortest possible access time If the VPC3 C is connected to a microcontroller with an asynchronous interface the controller can evaluate the Ready signal VPC3 C User Manual Revision 3 02 83 Copyright O profichip GmbH 2014 8 Hardware Interface 8 3 8 4 84 UART The transmitter converts the parallel data structure into a serial data flow Signal Request to Send RTS is generated before the first character The XCTS input is available for connecting a modem After RTS active the transmitte
44. VPC3 C User Manual Revision 3 02 profichip automation in silicon Liability Exclusion We have tested the contents of this document regarding agreement with the hardware and software described Nevertheless there may be deviations and we do not guarantee complete agreement The data in the document is tested periodically however Required corrections are included in subsequent versions We gratefully accept suggestions for improvements Copyright Copyright O profichip GmbH 2004 2014 Rights Reserved Unless permission has been expressly granted passing on this document or copying it or using and sharing its content are not allowed Offenders will be held liable All rights reserved in the event a patent is granted or a utility model or design is registered This document is subject to technical changes Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Table of Contents col un tu dan imite 5 2 Functional Description 7 ANE U m 7 S Ld jupe 9 3 1 Pin Assignment riti net ensure 9 32 11 4 Memory Organization 13 locom itu Et uidi dr t E e EEE Ma esu oit RE 13 4 2 Control Parameters Latches Registers 15 4 3 Organizational Parameters 17 5 ASIC MONACO 19 bo Mode
45. XTESTO VDD Normal VPC3 function VSS GND Various test modes 35 XTEST1 VDD Normal VPC3 function Figure 8 11 Test Ports Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 9 1 PROFIBUS Interface 9 Pin Assignment The data transmission is performed in RS485 operating mode i e physical RS485 The VPC3 C is connected via the following signals to the galvanically isolated interface drivers Signal Name Input Output Function RTS Output Request to send TXD Output Sending data RXD Input Receiving data Figure 9 1 PROFIBUS Signals The PROFIBUS interface is a 9 way sub D plug connector with the following pin assignment Pin 1 Free Pin 2 Free Pin 3 B line Pin 4 Request to send RTS Pin 5 Ground 5V M 5 Pin 6 Potential 5V floating P5 Pin 7 Free Pin 8 A line Pin 9 Free The cable shield must be connected to the plug connector housing The free pins are described as optional in IEC 61158 2 CAUTION The pin names A and B on the plug connector refer to the signal names in the RS485 standard and not the pin names of driver ICs Keep the wires from driver to connector as short as possible Note TXD is tristate output and requires external pull up resistor for correct operation with common line drivers VPC3 C User Manual Revision 3 02 85 Copyright O profichip GmbH 2014 9 PROFIBUS Interface 9 2 Example for the RS48
46. art number added to ordering information V3 02 26 05 2014 9 85 88 Notes regarding external pull up on TXD added 89 input voltage specification for 3 3V operation changed VPC3 C User Manual Copyright O profichip GmbH 2014 Revision 3 02 103 profichip GimbH Einsteinstrasse 6 91074 Herzogenaurach HM profichip Phone 49 9132 744 200 7 Fax 49 9132 744 2164 automation in silicon www profichip com
47. atus Set Time bit 0 The VPC3 D has received a valid Clock Value telegram and made the 0 data available in the Clock Sync Buffer Command Reserved bit 7 3 r 00000 Command Clock Value Check Ena bit x 0 don t evaluate Clock Value previous TE Dis 1 check Clock Value previous TE with local variable Time Last Rcvd Command Ignore Cyclic State Machine bit 0 Clock Synchronization stops after the receiption of a new Set Prm or E a LEAVE MASTER 1 Clock Synchronization continues until the user set Stop Clock Sync Command Stop Clock Sync bit 0 Stop the Clock Synchronization in order to write a new Tcsi without 0 previous Set Prm LEAVE MASTER The Bit is cleared by the Time Receiver State Machine Clock Value Sign of CV 0 add correction value to Time 1 substract correction value to Time Clock Value CV Correction Value Sel 0 2 0 min r 00000 1 31 30 930 min Clock Value Reserved Status1 bit 1 0 r 00 VPC3 C User Manual Revision 3 02 71 7 PROFIBUS DP Extensions Clock Sync Buffer Clock Value Announcment Hour 0 no change planned within the next hour E 1 a change of SWT will occur within the next hour Clock Value SWT Summertime Status 0 Winter Time bit 6 1 Summer Time r 0 Clock Value Reserved Status2 bit 5 r 0 Clock Value CR Accuracy Status2 0 21ms bit 4 3 1 10 ms r 00 2 100 ms 321s Clock Value Reserved Status2 bi
48. breaks down bit 4 User Timer Clock rw 0 The time base for the User Timer Clocks is run out 1 10ms bit 3 WD DP CONTROL Timeout rw 0 The watchdog timer expired in the DP CONTROL state bit 2 Baud Rate Detect rw 0 The VPC3 C has left the BAUD SEARCH state and found a baud rate bit 1 Go Leave DATA EXCH rw 0 The DP_SM has entered or exited the DATA EXCH state bit O MAC Reset used if CS_Supported 0 rw 0 After processing the current request the VPC3 D has entered the Offline state by setting the Go Offline bit Clock Sync used if CS Supported 1 The VPC3 D has received a Clock Value telegram or an error occurs Further differentiation is made in the Clock Sync Buffer Figure 5 9 Interrupt Request Register Low Byte 30 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 ASIC Interface 5 Interrupt Request Register 0 High Byte Address 01H Intel bit 15 FDL Ind rw 0 The VPC3 C has received an acyclic service request and made the data available in an Indication Buffer biti4 Poll End Ind rw 0 The VPC3 C have send the response to an acyclic service bit 13 DX_Out rw 0 The VPC3 C have received a Data Exchange telegram and made the new output data available in the N buffer bit 12 Diag Buffer Changed rw 0 Due to the request made by New Diag Cmd the VPC3 C exchanged the Diagnosis Buffers and made the old buffer available to
49. d Rate Monitoring The detected baud rate is permanently monitored in BAUD CONTROL The Watchdog is triggered by each error free telegram to its own Station Address The monitoring time results from multiplying twice WD BAUD CONTROL Val user sets this parameter by the time base 10 ms If the timer expires WD SM again goes to BAUD SEARCH If the user uses the DP protocol DP Mode 1 see Mode Register 0 the watchdog is used for the DP CONTROL state after a Set Prm telegram was received with an enabled response time monitoring WD On 1 The watchdog timer remains in the baud rate monitoring state when the master monitoring is disabled WD On 0 The DP SM is not reset when the timer expires in the state BAUD CONTROL That is the DP Slave remains in the DATA EXCH state for example 5 4 3 Response Time Monitoring The DP CONTROL state serves as the response time monitoring of the DP Master Diag Master Add The used monitoring time results from multiplying both watchdog factors and then multiplying this result with the time base 1 ms or 10 ms Two WD Base WD Fact 1 WD Fact 2 See byte 7 of the Set Prm telegram The user can load the two watchdog factors WD Fact 1 and WD Fact 2 and the time base that represents a measurement for the monitoring time via the Set Prm telegram with any value between 1 and 255 EXCEPTION The WD Fact 1 WD Fact 2 1 setting is not allowed The circuit does not check this setting A
50. d User Buffer 01 DXBout Buf Ptr1 10 DXBout Buf Ptr2 11 DXBout Buf Ptr3 Figure 7 13 Coding of Next DXBout Buf Cmd Monitoring After receiving the DXB data the Link Status in DXB Status Buf of the concerning Publisher is updated In case of an error the bit Link Error is set If the processing is finished without errors the bit Data Exist is set In state DATA EXCH the links are monitored in intervals defined by the parameterized watchdog time After the monitoring time runs out the VPC3 C evaluates the Link Status of each Publisher and updates the bit Link Status The timer restarts again automatically Link _ Link _ Data __ Event Status Error Exist valid DXB data receipt 0 1 faulty DXB data receipt 0 1 0 WD Time elapsed AND Data Exist 1 1 0 0 WD Time elapsed AND Link Error 1 0 0 0 Figure 7 14 Link Status handling To enable the monitoring of Publisher Subscriber links the watchdog timer must be enabled in the Set Prm telegram The user must check this VPC3 C User Manual Revision 3 02 63 Copyright O profichip GmbH 2014 7 PROFIBUS DP Extensions 7 3 2 64 IsoM Isochron Mode IsoM synchronizes DP Master DP Slave and DP Cycle The isochron cycle time starts with the transmission of the SYNCH telegram by the IsoM master If the VPC3 C supports the IsoM a synchronization signal at Pin 13 XDATAEXCH SYNC is generated by each reception of SYNCH te
51. dy again to receive another Set Slave Add telegram for example from a different DP Master The VPC3 C reacts automatically to errors Bit Position Address Designation 7 6 5 4 3 2 1 0 SSA_Buf_ 14H 0 0 0 0 0 0 0 0 SSA Buf Free Address 14H bit 7 0 Don t care Read as 0 Figure 6 3 Coding of SSA Buffer Free Command Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Interface 6 Structure of the Set Slave Add Telegram The net data are stored as follows in the SSA buffer Bit Position p Byte Designation 7 6 5 4 3 2 1 0 0 New Slave Address 1 Ident Number High 2 Ident Number Low 3 No Add Chg 4 Rem Slave Data additional application 243 specific data Figure 6 4 Structure of the Set Slave Add Telegram 6 2 2 Set Prm SAP 61 Parameter Data Structure The VPC3 C evaluates the first seven data bytes without User Prm Data or the first eight data bytes with User Prm Data The first seven bytes are specified according to the standard The eighth byte is used for VPC3 C specific characteristics The additional bytes are available to the application If a PROFIBUS DP extension shall be used the bytes 7 9 are called DPV1 Status and must be coded as described in section 7 PROFIBUS DP Extensions Generally it is recommended to start the
52. e Diagnosis Buffer had not been fetched by the DP Master yet bit 1 Reserved r 0 bit 0 Offline Passive Idle Offline Passive ldle state r 0 0 is in Offline 1 VPC3 C is in Passive_ldle Figure 5 6 Status Register Low Byte Status Register High Byte Address 05H Intel bit 15 12 VPC3 Release 3 0 Release number for VPC3 1100 5000 Step A 1011 Step B 1100 Step C 1101 Step D Rest Not possible bit 11 8 Baud Rate 3 0 The baud rate found by VPC3 C T1111 0000 12 00 Mbit s 0001 6 00 Mbit s 0010 3 00 Mbit s 0011 1 50 Mbit s 0100 500 00 Kbit s 0101 187 50 Kbit s 0110 93 75 Kbit s 0111 45 45 Kbit s 1000 19 20 Kbit s 1001 9 60 Kbit s 1111 after reset and during baud rate search Rest not possible Figure 5 7 Status Register High Byte VPC3 C User Manual Revision 3 02 27 Copyright O profichip GmbH 2014 5 ASIC Interface 5 3 28 Interrupt Controller The processor is informed about indication messages and various error events via the interrupt controller Up to a total of 16 events are stored in the interrupt controller The events are summed up to a common interrupt output The controller does not have a prioritization level and does not provide an interrupt vector not 8259A compatible The controller consists of an Interrupt Request Register IRR an Interrupt Mask Register IMR an Interrupt Register IR and an Interrupt Ackno
53. e at all Bit Position Address Designation 7 6 5 4 3 2 1 0 OBH 0 0 0 0 Next Dout _ TD 2 S gt See coding 19 85 D 5 below D20 0m m Next Dout Buf Cmd Address OBH bit 7 4 Don t care Read as 0 bit 3 U_Buffer_Cleared User Buffer Cleared Flag 0 U buffer contains data 1 U buffer is cleared bit 2 State_U_Buffer State of the User Buffer 0 no new U buffer 1 new U buffer bit 1 0 Ind U Buffer Indicated User Buffer 01 Dout Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 Figure 6 13 Coding of Next Dout Buf Cmd The user must clear the U buffer during initialization so that defined cleared data can be sent for a RD Output telegram before the first data cycle Reading Inputs The VPC3 C sends the input data from the D buffer Prior to sending the VPC3 C fetches the Din Buffer from N to D If no new buffer is present in N there is no change The user makes the new data available in U With the New Din Buffer Cmd the buffer changes from U to N If the user s preparation cycle time is shorter than the bus cycle time not all new input data are sent but just the most current At a 12 Mbit s baud rate it is more likely however that the user s preparation cycle time is larger than the bus cycle time Then the VPC3 C sends the same data several times in succession
54. eception of a Global Control telegram can be configured via bit 8 of Mode Register 2 The VPC3 C either generates the New GC Control interrupt after each receipt of a Global Control telegram default or just in case if the Global Control differs from the previous one GC Command RAM cell is not initialized by the VPC3 C Therefore the cell has to be preset with 00H during power up The user can read and evaluate this cell 50 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Interface 6 In order to use Sync and Freeze these functions must be enabled in the Mode Register 0 Bit Position Address Designation 7 6 5 4 3 2 1 0 3CH R GC a 5 5 z Command o N a o Z 2 o gt by 5 o See below D 8 t for coding a 2 LL 2 R GC Command Address bit 7 6 Reserved bit 5 Sync The output data transferred with a Data Exchange telegram is changed from D to N The following transferred output data is kept in D until the next Sync command is given bit 4 Unsync The Unsync command cancels the Sync command bit 3 Freeze The input data is fetched from to D and frozen New input data is not fetched again until the DP Master sends the next Freeze command bit 2 Unfreeze The Unfreeze command cancels the Freeze command bit 1 Clear Data
55. esults either in a 16 byte or in an 8 byte granularity VPC3 C User Manual Revision 3 02 37 Copyright O profichip GmbH 2014 6 PROFIBUS DP Interface 6 2 6 2 1 38 Description of the DP Services Set Slave Add SAP 55 Sequence for the Set Slave Add service The user can disable this service by setting R SSA Puf Ptr 00H The Station Address must then be determined for example by reading a DIP switch or an EEPROM and writing the address in the RAM cell R TS Adr There must be a non volatile memory available for example an external EEPROM to support this service It must be possible to store the Station Address and the Real No Add Change True parameter in this EEPROM After each restart caused by a power failure the user must read these values from the EEPROM again and write them to the R TS Adrund R Real No Add Change RAM registers If SAP55 is enabled and the Set Slave Add telegram is received correctly the VPC3 C enters the pure data in the Aux Buffer 1 2 exchanges the Aux Buffer 1 2 for the Set Slave Add Buffer stores the entered data length in R Len SSA Data generates the New SSA Data interrupt and internally stores the New Slave Add as Station Address and the No Add Chg as Real No Add Chg The user does not need to transfer this changed parameter to the VPC3 C again After reading the buffer the user generates the SSA Buffer Free Cmd read operation on address 14H This makes the VPC3 C rea
56. g the WAIT PRM state If the user fetches this buffer he receives U Buffer Cleared during the Next Dout Buffer Cmd If the user is supposed to enlarge the output data buffer after the Chk Cfg telegram the user must delete this deviation in the N buffer himself possible only during the start up phase in the WAIT CFG state If Diag Sync Mode 1 the D buffer is filled but not exchanged with the Data Exchange telegram It is exchanged at the next Sync or Unsync command sent by Global Control telegram Bit Position Address Designation 7 6 5 4 3 2 1 0 OAH F U N D Dout Buffer SM Buffer SM Address OAH bit 7 6 F Assignment of the F Buffer 00 Nil 01 Buf Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 bit 5 4 U Assignment of the U Buffer 00 Nil 01 Dout Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 bit 3 2 N Assignment of the N Buffer 00 Nil 01 Dout Buf Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 bit 1 0 D Assignment of the D Buffer 00 Nil 01 Buf Ptr1 10 Dout Buf Ptr2 11 Dout Buf Ptr3 Figure 6 12 Dout Buffer Management VPC3 C User Manual Revision 3 02 47 Copyright O profichip GmbH 2014 6 PROFIBUS DP Interface 48 When reading the Next Dout Buffer Cmd the user gets the information which buffer U buffer belongs to the user after the change or whether a change has taken plac
57. gister The New Ext Prm Data New Data interrupts cannot be acknowledged via the Interrupt Acknowledge Register The relevant state machines clear these interrupts through the user acknowledgements for example User Prm Data Okay etc 5 4 Watchdog Timer The VPC3 C is able to identify the baud rate automatically The state ma chine is in the BAUD SEARCH state after each RESET and also after the Watchdog WD Timer has expired in the BAUD CONTROL state BAUD SEARCH ES N WD Timeout baudrate detected A x WD On 0 or WD_On 1 WD_DP_CONTROL_Timeout DP CONTROL Figure 5 12 Watchdog State Machine WD SM 32 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 ASIC Interface 5 5 4 1 Automatic Baud Rate Identification The VPC3 C starts searching for the transmission rate using the highest baud rate If no SD1 telegram 02 telegram 03 telegram was received completely and without errors during the monitoring time the search continues using the next lower baud rate After identifying the correct baud rate the VPC3 C switches to the BAUD CONTROL state and observes the baud rate The monitoring time can be parameterized WD BAUD CONTROL Val The watchdog uses a clock of 100 Hz 10 ms Each telegram to its own Station Address received with no errors resets the Watchdog If the timer expires the VPC3 C switches to the BAUD SEARCH state again 5 4 2 Bau
58. he user receives the Cfg Conflict signal during the positive or negative acknowledgement of the first Chk Cfg telegram Then the user must repeat the validation because the VPC3 C have made a new Config Buffer available The User Cfg Data Okay and User Cfg Data Not Okay acknowledgements are read accesses to defined memory cells with the relevant Not Allowed User Cfg Finished or Cfg Conflict signals If the New Prm Data and New Cfg Data are supposed to be present simultaneously during start up the user must maintain the Set Prm and then the Chk_Cfg acknowledgement sequence Bit Position Address Designation 7 6 5 4 3 2 1 0 User Cf 10H 0 0 0 0 0 0 y U Data Okay 0 0 User Cfg Finished 0 1 Conflict 1 1 Not Allowed Bit Position Address Designation 7 6 5 4 3 2 1 0 User Cf of of of l Data Not Okay 0 0 User Cfg Finished 0 Cfg Conflict 1 1 Not Allowed Figure 6 8 Coding of User Cfg Not Okay Cmd 6 2 4 Slave Diag SAP 60 44 Diagnosis Processing Sequence Two buffers are available for diagnosis These two buffers can have different lengths One Diagnosis Buffer which is sent on a diagnosis request is always assigned to the VPC3 C The user can pre process new diagnosis data in the other buffer parallel If the new diagnosis data are to be sent the user issues the
59. her telegrams are then read via Aux Buffer 1 R Aux Buf Sel Set Slave Adr 0 Chk Cfg 0 If the buffers are too small the VPC3 C responds with no resources RR Bit Position Address Designation 7 6 5 4 3 2 1 0 2AH R Aux Buf Sel 8 lt B E 9 9 Wc Im amp See below 98 for coding Nn O a R Aux Buf Sel Address 2AH bit 7 3 Don t Care Read as 0 bit 2 Set Slave Adr Set Slave Address 0 Aux Buffer 1 1 Aux Buffer 2 bit 1 Chk Cfg Check Configuration 0 Aux Buffer 1 1 Aux Buffer 2 bit O Set Prm Set Extended Parameter 0 Aux Buffer 1 1 Aux Buffer 2 Figure 6 2 Aux Buffer Management The user makes the configuration data Get Cfg available in the Read Config Buffer for reading The Read Config Buffer must have the same length as the Config Buffer The RD Input telegram is serviced from the Din buffer in the D state and the RD Output telegram is serviced from the Dout Buffer in the U state All buffer pointers are 8 bit segment addresses because the VPC3 C have only 8 bit address registers internally For a RAM access VPC3 C adds 8 bit offset address to the segment address shifted by 4 bits result 12 bit physical address in case of 4K Byte RAM or shifted by 3 bits result 11 bit physical address in case of 2K Byte RAM With regard to the buffer start addresses this specification r
60. ich contains all SAPs needed for the communication The user must do the initialization of this area SAP List in Offline state Each entry in the SAP List consists of 7 bytes The pointer at address 17H contains the segment base address of the first element of the SAP List The last element in the list is always indicated with FFH If the SAP List shall not be used the first entry must be FFH so the pointer at address 17H must point to a segment base address location that contains FFH The new communication features are enabled with DPV1 Enable in the Set Prm telegram Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 Bit Position Byte Designation 7 6 5 4 3 2 1 0 e 0 e SAP_Number SAP_Number o ee 1 Request_SA 2 Request_SSAP 3 Service_Supported 4 Ind_Buf_Ptr 0 5 Ind_Buf_Ptr 1 6 Resp_Buf_Ptr SAP List entry Byte 0 Response_Sent Response Buffer sent 0 no Response sent 1 Response sent SAP Number 0 51 Byte 1 Request SA The source address of a request is compared with this value At differences the VPC3 C response with no service activated RS The default value for this entry is 7FH Byte 2 Request SSAP The source SAP of a request is compared with this value At differences the VPC3 C response with no service activated RS The default value for this
61. ignal Direction dm Driver Strength er feud DB 0 7 Tristate 8mA 100pF RTS Push Pull 8mA 50pF TXD Tristate 8mA 50pF X INT O Push Pull 4mA 50pF XREADY XDTACK Push Pull 4mA 50pF XDATAEXCH Push Pull 8mA 50pF CLKOUT2 4 Push Pull 8mA 100pF Figure 10 4 Ratings for the Output Drivers Note TXD is tristate output and requires external pull up resistor for correct operation with common line drivers 10 5 DC Electrical Characteristics Specification for 5V Operation Parameter Symbol MIN TYP MAX Unit DC supply voltage Voc 4 50 5 00 5 50 V CMOS input voltage LOW level 0 0 3 Vcc V CMOS input voltage HIGH level Vinc 0 7 Vcc Vcc V Output voltage LOW level VoL 0 4 V Output voltage HIGH level Von 3 5 V CMOS Schmitt Trigger negative going threshold voltage i 1g CMOS Schmitt Trigger positive going threshold voltage Vr 3 2 29 d TTL Schmitt Trigger negative going threshold voltage is te TTL Schmitt Trigger positive going threshold voltage Vis 1 9 2 d Input LOW current li 1 1 Input HIGH current lia 1 1 Tri state leakage current loz 10 1 10 Output current LOW level 4 cell lo 4 0 mA Output current HIGH level 4mA cell 4 0 Output current LOW level 8mA cell lo 8 0 mA Output current HIGH level 8mA cell 8 0 Figure 10 5 DC Specification of I O Drivers for 5V Operation 88 Revi
62. into consideration that the processor carries out word accesses That is either a swapper is necessary that switches the characters out of the VPC3 C at the correct byte position of the 16 bit data bus during reading or the least significant address bit is not connected and the 80286 must read word accesses and evaluate only the lower byte Name Comments DB 7 0 Tristate High resistance during RESET AB 10 0 10 has a pull down resistor MODE Configuration syn async interface XWR E CLOCK Intel Write Sync Motorola E CIk AB11 AB11 Asynchronous Motorola Mode XRD R W Intel Read Motorola Read Write XCS Chip Select AB11 AB11 Synchronous Intel Mode ALE AS Intel Motorola Address Latch Enable AB11 AB11 Async Intel Sync Motorola Mode DIVIDER Scaling factor 2 4 for CLKOUT 2 4 X INT O Push Pull Polarity programmable XRDY XDTACK O Push Pull Intel Motorola Ready Signal CLK 48 MHz XINT MOT Setting Intel Motorola CLKOUT2 4 Push Pull 24 12 MHz RESET Schmitt Trigger Minimum of 4 clock cycles Figure 8 2 Microprocessor Bus Signals Due to compatibility reasons to existing competitive chips the XRDY XDTACK output of the VPC3 C has push pull characteristic no tristate 76 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Hardware Interface 8 Synchronous Intel Mode In this mode Intel CPUs
63. ip GmbH 2014 Functional Description 2 2 1 Overview The makes a cost optimized design of intelligent PROFIBUS DP Slave applications possible The processor interface supports the following processor series Intel 80C31 80X86 Siemens 80C166 165 167 Motorola HC11 HC16 and HC916 types The handles the physical layer 1 and the data link layer 2 of the ISO OSI reference model excluding the analog RS485 drivers The integrated 4K Byte Dual Port RAM serves as an interface between the VPC3 C and the software application In case of using 2K Byte the entire memory is divided into 256 segments with 8 bytes each Otherwise in the 4K Byte mode the segment base addresses starts at multiple of 16 Addressing by the user is done directly however the internal Micro Sequencer MS addresses the RAM by means of the so called base pointer The base pointer can be positioned at the beginning of a segment in the memory Therefore all buffers must be located at the beginning of a segment If the VPC3 C carries out a DP communication it automatically sets up all DP SAPs The various telegram information are made available to the user in separate data buffers for example parameter and configuration data Three buffers are provided for data communication three for output data and three for input data As one buffer is always available for communica tion no resource problems can occur For optimal diagnosis support the
64. ip GmbH 2014 Operational Specifications 10 SYMBOL MILLIMETER MIN NOM MAX A 2 70 A1 0 25 0 35 A2 1 80 2 00 2 20 b 0 22 0 30 0 38 0 10 0 15 0 20 0 80 BSC 13 70 18 90 14 10 D1 9 90 10 00 10 10 E 13 70 18 90 14 10 E1 9 90 10 00 10 10 L 0 73 0 88 0 93 L1 1 95 REF 0 7 Figure 10 22 Package Dimensions and Tolerances Notes 1 JEDEC outline n a 2 Datum plane H is located at the bottom of the mold parting line coincident with where the lead exits the body 3 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0 25 mm per side Dimensions D1 and E1 do not in clude mold mismatch and are determined at datum plane H 4 Dimension b does not include dambar protrusion VPC3 C User Manual Revision 3 02 101 Copyright O profichip GmbH 2014 10 Operational Specifications 10 9 Processing Instructions Internal circuitry protects the inputs against damage caused by high static voltages or electric fields however normal precautions are necessary to avoid application of any voltage higher than maximum rated voltages to this circuit The VPC3 C is cracking endangered component that must be handled properly Profichip products are tested and classified for moisture sensitivity according to the procedures outlined by JEDEC The VPC3 C is classified as m
65. is generated after every Data_Exchange telegram bit 1 No_Check_GC_Reserved Disables checking of the reserved bits in w 0 Global_Control telegram 0 reserved bits of a Global_Control telegram are checked default 1 reserved bits of a Global Control telegram are not checked bit O GC Int Mode Controls generation of GC Command interrupt w 1 0 New GC Command interrupt is only generated if a changed Global Control telegram is received 1 New GC Command interrupt is generated after every Global Control telegram default Figure 5 4 Coding of Mode Register 2 24 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 ASIC Interface 5 5 1 4 Mode Register 3 Setting parameters for Mode Register 3 may take place in the Offline State only like Mode Register 0 Bit Position Address 7 6 5 4 3 2 1 0 Designation m 2 2 Mode Reg 3 12H Reserved 7 0 x o a 9 Mode Register 3 Address 12H bit 7 Reserved w 0 bit 6 w 0 Reserved bit 5 Reserved w 0 bit 4 Reserved w 0 bit 3 w 0 Reserved bit 2 Reserved w 0 bit 1 DX_Int_Mode_2 Mode of DX_out interrupt w 0 0 DX Out interrupt is generated after each Data Exch telegram 1 DX Out interrupt is only generated if received data is not equal to current data in DX Out buffer of user bit O GC Int Mode Ext extend GC Int Mode works only if GC
66. k 5 5 ns 32 E Clock f to Data valid 103 97 ns 38 Data holdtime after E Clock 4 4 16 4 12 ns 35 R W setuptime to E Clock T 10 10 ns 39 R W holdtime after E Clock 5 5 ns 36 XCS setuptime to E Clock T 0 0 ns 40 XCS holdtime after E Clock 0 0 ns 41 Data setuptime to E Clock 10 10 ns 42 Data holdtime after E Clock 4 10 10 ns Figure 10 17 Timing Synchronous Motorola Mode 96 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Operational Specifications 10 10 7 5 Timing in the Asynchronous Motorola Mode In the asynchronous Motorola mode the VPC3 C acts like a memory with Ready logic whereby the access times depend on the type of access The request for an access of the VPC3 C is generated from the falling edge of the AS signal in addition XCS 0 W 1 The request for a write access is generated from the rising edge of the AS signal in addition XCS 0 R_W 0 AB10 0 DB7 0 AS RW XCS XDTACK normal XDTACK early lt 60 gt lt 6 gt Figure 10 18 Asynchronous Motorola Mode READ E CLOCK 0 VPC3 C User Manual Revision 3 02 97 Copyright O profichip GmbH 2014 10 Operational Specifications AB10 0 DB7 0 AS XCS XDTACK normal XDTACK early lt 60 Figure 10 19 Asynchronous Motorola Mode WRITE 98 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 20
67. legram The SYNCH telegram is a special coded Global Control request SYNCH Cyclic Cyclic Acyclic Acyclic Spare SYNCH Service Service Service Service Token Time mesage Cyclic gt lt Acyclic Part Part Cycle Time T Figure 7 15 Telegram sequences in IsoM with one DP Master Class 1 Two operation modes for cyclic synchronization are available in the VPC3 C 1 Isochron Mode Each SYNCH telegram causes an impulse on the SYNC output and a New GC Command interrupt 2 Simple Sync Mode A Data Exchange telegram no longer causes a DX Out interrupt immediately rather the event is stored in a flag By a following SYNCH message reception the DX Out interrupt and a synchronization signal are generated at the same time Additionally a New GC Command interrupt is produced as the SYNCH telegram behaves like a regular Global Control telegram to the DP state machine no Data Exchange telegram precedes the SYNCH telegram only the New GC Command interrupt is generated Bit Position Byte Designation 7 6 5 4 3 2 1 0 0 0 0 0 Control Command Group 8 1 Group Select Figure 7 16 IsoM SYNCH telegram Each Global Control is compared with the values that can be adjusted in Control Command Reg 0Eh and Group Select Reg If the values are equal a SYNCH telegram
68. loads specified in the table above 10 7 1 System Bus Interface Clock Clock frequency is 48 MHz Distortion of the clock signal is permissible up to a ratio of 30 70 at the threshold levels 0 9 V and 2 1 V Parameter Symbol MIN MAX Unit Clock period T 20 83 20 83 Clock high time Tcu 6 25 14 6 ns Clock low time Tc 6 25 14 6 ns Clock rise time Tor 4 ns Clock fall time Tcr 4 ns Figure 10 7 Clock Timing Interrupt After acknowledging an interrupt with EOI the interrupt output of the VPC3 C is deactivated for at least 1 us or 1 ms depending on the bit EOI Time Base in Mode Register O Parameter MIN MAX Unit Interrupt inactive time EOL Timebase 0 1 1 Hs Interrupt inactive time _ 1 1 1 ms Figure 10 8 End of Interrupt Timing Reset VPC3 C requires a minimum reset phase of 100 ns at power on 90 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Operational Specifications 10 10 7 2 Timing in the Synchronous Intel Mode In the synchronous Intel mode the VPC3 C latches the least significant addresses with the falling edge of ALE At the same time the VPC3 C expects the most significant address bits on the address bus An internal chipselect signal is generated from the most significant address bits The request for an access to the VPC3 C is generated from the falling edge of the read signal
69. low is converted into the serial data flow and vice versa The VPC3 C is capable of automatically identifying the baud rates 9 6 Kbit s 12 Mbit s The Idle Timer directly controls the bus times on the serial bus line 8 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Pin Description 3 3 1 Pin Assignment Pin Signal Name In Out Description Source Destination C32 Mode 2K Byte RAM connect to VDD XCS Chip Select 1 C165 Mode CS Signal CPU 80C165 AB11 Address Bus 11 C32 Mode 4K Byte RAM XWR E CLOCK Write Signal E Clock for Motorola 2 AB11 Address Bus 11 Asynchronous Motorola Mode 4K Byte RAM Setting the scaling 0 CLK divided by 4 IDIVIDER KC factor for CLKOUT2 4 CLK divided by 2 Configuration Pin 4 XRD RW KC Read Signal Read _ Write for Motorola CPU 5 CLK ITS System Clock Input 48 MHz System 6 VSS 7 CLKOUT2 4 O Clock Output System Clock divided by 2 or 4 System CPU 0 Intel Interface 8 XINT MOT 4 Motorola Interface Configuration Pin CPU Interrupt 9 X INT Interrupt Controller C32 0 10 AB10 Address Bus C165 Mode Address Bus System CPU 11 DBO I C O C32 Mode Data Address Bus multiplexed 12 DB1 I C O Data Pus C165 Mode Data Address Bus separated CPU Memory i3 XDATAEXC
70. m overwrites this memory cell in the DP Mode Refer to the user specific data bit 0 Dis Start Control Disable Startbit Control rw 0 0 Monitoring the following start bit is enabled 1 Monitoring the following start bit is switched off Set Prm telegram overwrites this memory cell in the DP Mode Refer to the user specific data Figure 5 1 Coding of Mode Register 0 Low Byte 20 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 ASIC Interface 5 Mode Register 0 High Byte Address 07H Intel bit 15 Reserved rw 0 bit 14 PrmCmd_Supported PrmCmd support for redundancy rw 0 0 PrmCmd is not supported 1 PrmCmd is supported bit 13 Spec Clear Mode Special Clear Mode Fail Safe Mode rw 0 0 No special clear mode 1 Special clear mode VPC3 C will accept data telegrams with data unit 0 bit 12 Spec Prm Buf Mode Special Parameter Buffer Mode rw 0 0 No Special Parameter Buffer 1 Special Parameter Buffer mode Parameterization data will be stored directly in the Special Parameter Buffer bit 11 Set Ext Prm Supported Set Ext Prm telegram support rw 0 0 SAP 53 is deactivated 1 SAP 53 is activated bit 10 User Time Base Timebase of the cyclical User Time Clock Interrupt rw 0 0 The User Time Clock Interrupt occurs every 1 ms 1 The User Time Clock Interrupt occurs every 10 ms bit 9 EOI Time Base End of Interrupt Timebase rw 0
71. monitoring time between 2 ms and 650 s independent of the baud rate can be implemented with the allowed watchdog factors VPC3 C User Manual Revision 3 02 33 Copyright O profichip GmbH 2014 5 ASIC Interface If the monitoring time expires the VPC3 C goes to BAUD CONTROL state again and generates the WD DP CONTROL Timeout interrupt In addition the DP State Machine is reset that is it generates the reset states of the buffer management This operation mode is recommended for the most applications If another DP Master takes over the VPC3 C the Watchdog State Machine either branches to BAUD CONTROL WD On 0 or to DP CONTROL WD_On 1 34 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Interface 6 6 1 DP Buffer Structure The DP Mode is enabled in the VPC3 C with DP Mode 1 see Mode Register 0 In this mode the following SAPs are permanently reserved Default SAP Write and Read data Data Exchange SAP 53 Sending extended parameter setting data Set Ext Prm SAP 55 Changing the Station Address Set Slave Add SAP 56 Reading the inputs RD Input SAP 57 Reading the outputs RD Output SAP 58 Control commands to the DP Slave Global Control SAP 59 Reading configuration data Get SAP 60 Reading diagnosis information Slave Diag SAP 61 Sending parameter setting data Set Prm SAP 62 Checking configuration data Chk Cfg The DP Slave protocol is completely integra
72. n 3 02 17 Copyright O profichip GmbH 2014 4 Memory Organization 18 Address Intel Mot Name Bit No Significance 30H R Prm Buf Ptr Segment base address of the Prm Buf 31H R Len Cfg Data Length of the input data in the Cfg_Buf 32H R Cfg Buf Ptr Segment base address of the Cfg Buf 33H R Len Read Cfg Data Length of the input data in the Read Cfg Segment base address of the 34H R Read Cfg Buf Ptr Read Cfg Buf 35H R Len DXB Link Buf Length of the DXB Linktable Segment base address of the 36H R DXB Link Buf Ptr DXB Link Buf 37H R Len DXB Status Buf Length of the DXB Status Segment base address of the 38H R DXB Status Buf Ptr DXB Status Buf This parameter specifies whether the 39H R Real No Add Change Station Address may be changed again later The user sets the parameters for the R_Ident_Low Ident Number_Low value The user sets the parameters for the 3BH R_Ident High Ident Number High value The Control Command of Global Control 3CH R GC Command last received If parameters are set for the Spec Prm Buffer Mode see Mode FEES nec Dum Bn Register 0 this cell defines the length of the Prm Buf 3EH R DXBout Buf Ptr2 Segment base address of DXBout_Buf 2 3FH R DXBout Buf Ptr3 Segment base address of DXBout_Buf 3 Figure 4 4 Assignment of the Organizational Parameters Revision 3 02 VPC3 C User Manual Copyright profichip GmbH
73. nous Bus Mode IsoM described in DP V2 extension are also provided Automatic recognition and support of data transmissions rates up to 12 Mbit s the integration of the complete PROFIBUS DP protocol 4K Byte communication RAM and the configurable processor interface are features to create high performance PROFIBUS DP Slave applications The device can be operated with either 3 3V or 5V single supply voltage Profichips VPC3 is the predecessor of VPC3 C and VPC3 B VPC3 and VPC3 C are pin compatible Therefore VPC3 can be replaced by VPC3 C in existing applications without any restrictions SW modifications However downgrading from VPC3 C to VPC3 is only possible if the additional features of VPC3 C 4K Byte RAM DP V1 or DP V2 functionality 3 3V supply are not used As there are also simple devices in the automation engineering area such as switches or thermoelements that do not require a microcontroller for data preprocessing profichip offers a DP Slave ASIC with 32 direct input output bits The VPCLS2 handles the entire data traffic independently No additional microprocessor or firmware is necessary The VPCLS2 is compatible to existing chips Further information about our products or current and future projects is available on our web page http www profichip com VPC3 C User Manual Revision 3 02 5 Copyright O profichip GmbH 2014 1 Introduction Notes 6 Revision 3 02 VPC3 C User Manual Copyright profich
74. ock Generator 48 MHz DIVIDER i d n Dar RD i iat RTS INTO X INT TxD DB 7 0 80C 32 Data RxD N DB 7 0 20 16 MHz ALE ji lAddress Latch XCTS LM Address VPC3 B Port o AD 7 0 Latch Port2 15 8 0000 0XXX GND AB 15 0 AB9 Reset AB10 VPC3 Mode Reset Address EPROM RAM Decoder E 64kB 32kB f 1 1K AK RD W R GND VDD Figure 8 4 80C32 System with External Memory VPC3 C User Manual Revision 3 02 79 Copyright O profichip GmbH 2014 8 Hardware Interface 12 24 MHz Clockgenerator 48 MHz XWR XRD X INT XREADY 80286 Buscontr DB 15 0 DB7 0 82288 82244 AB 23 0 AES GND RD WR driver control logic DEEE EM J address cs EPROM RAM decoder 64kB 32kB Figure 8 5 80286 System X86 Mode 80 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Hardware Interface 8 8 1 4 Application with 80C32 2K Byte RAM Mode VPC3 48 MHz 5 1 8 lt XINT IMOT cLk2 7 36 RESET XDATAEX 5112 LED for Data Exchange VDD 1 3K3 1 4 xcs XREADY 14 VDD 3K3 23 MODE aC gt 24 ALE XANT 16 g
75. oisture sensitivity level MSL 3 Note In order to minimize any potential risk caused by moisture trapped inside non hermetic packages it is a general recommendation to perform a drying process 125 C for 24 hours before soldering 10 10 Ordering Information Version Order Code Package Temperature Range Notes Part Number Industrial Clock Synchronization VPC3 CLF3 PALF2080 PQFP44 40 C to 85 C RoHS compliant 102 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Revision History Version Date Page Remarks V1 00 10 05 2004 First release V1 01 18 07 2004 Re formatting and correction of typing errors V1 02 22 09 2004 Some minor corrections V1 03 12 01 2006 Consecutive paging 54 Additional figures for FDL Interface 80 Figure 9 2 updated 85 Figure 10 10 revised V1 04 19 03 2007 62 Figure 7 12 revised 63 Figure 7 13 revised 96 Ordering Information added 81 Thermal Resistance added V2 00 30 04 2008 25 add Mode Register 3 68 73 add Clock Synchronization V2 01 02 06 2008 25 correct description of DX Int Mode 2 in Mode Register 3 V2 02 05 12 2008 87 Absolute Maximum Rating of Vi changed to 6 0 V V2 03 07 05 2009 25 correct description of GC Int Mode Ext in Mode Register V3 00 10 01 2013 100 101 package data updated 101 processing instructions revised 101 ordering information updated V3 01 18 02 2014 102 P
76. ollers without chip select logic N and M and others an external chip select logic is required This means additional hardware and a fixed assignment If the CPU is clocked by the VPC3 C the output clock pulse CLKOUT 2 4 must be 4 times larger than the E Clock That is a clock pulse sig nal must be present at the CLK input that is at least 10 times larger than the desired system clock pulse E Clock The Divider Pin must be connected to 0 divider 4 This results in an E Clock of 3 MHz AB11 must be connected to ALE AS pin 24 in 4K Byte mode as this is the additional address bus signal in this mode In 2K Byte mode this pin is not used and should be pulled to GND Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Hardware Interface 8 8 1 3 Application Examples Principles Clock Generator 48MHz DIVIDER Y CLK wa eem Clockdivider BD PI XRD RTS INTO lt X INT DB 7 0 TxD Port 0 A D 7 0 k 4 80C 32 B DB 7 0 RxD Address Latch C501 ALE ress Latc AB 7 0 VPC3 1K Port 2 AB 1 5 8 0000 0XXX Decoder T GND ABB AB9 AB10 VPC3 Mode Reset Reset 1 HK 3K 3 GND VDD Figure 8 3 Low Cost System with 80C32 Cl
77. ory 32 AB6 33 XCTS Clear to Send 0 send enable FSK Modem 34 XTESTO Pin must be connected to VDD 35 XTEST1 Pin must be connected to VDD 36 RESET I CS Connect Reset Input with CPU s port pin 37 4 Address Bus CPU Memory 38 VSS 39 VDD 40 AB3 41 AB2 42 5 Address Bus CPU Memory 43 AB1 44 ABO Figure 3 1 Pin Assignment Notes All signals that begin with X are LOW active C32 Mode means Synchronous Intel Mode and C165 Mode means Asynchronous Intel Mode VDD 45V VSS OV Input Levels CMOS I CS CMOS Schmitt Trigger I CPD CMOS pulldown I TS TTL Schmitt Trigger 4K Byte RAM extension Beginning with Step B of the VPC3 the communication RAM has been extended to 4K Byte whereas Step A only has 2K Byte To access the entire 4K Byte RAM in VPC3 C an additional address signal AB11 is required Which pin is assigned to A11 depends on the Processor Interface Mode used see Figure 3 2 Due to compatibility reasons the pin which is now assigned to A11 was unused in Step A for the certain Interface Mode Processor Interface Mode Pin Signal Name Synchronous Intel Mode 1 XCS Asynchronous Intel Mode 24 ALE AS Asynchronous Motorola Mode 2 XWR E_CLOCK Synchronous Motorola Mode 24 ALE AS Figure 3 2 Pin assignment for AB11 The 4K Byte RAM extension must be enabled in Mode Register 2 see section 5 1 3 By default the 4K Byte mode is disabled
78. ould be supported the PrmCmd Supported bit in Mode Register 0 must be set VPC3 C User Manual Revision 3 02 53 Copyright O profichip GmbH 2014 7 PROFIBUS DP Extensions 7 2 7 2 1 54 Bit Position Byte Designation y 7 6 5 4 3 2 1 0 0 Structured_Length 1 Structure Typ 2 Slot Number 3 Reserved 4 User Prm Data 243 Figure 7 2 Format of the Structured Prm Data block Additional to the Set Prm telegram SAP 61 a Set Ext Prm SAP 53 telegram can be used for parameterization This service is only available in state WAIT CFG after the reception of a Set Prm telegram and before the reception of a Chk Cfg telegram The new Set Ext Prm telegram simply consists of Structured Prm Data blocks The new service uses the same buffer handling as described by Set Prm By means of the New Ext Prm Data interrupt the user can recognize which kind of telegram is entered in the Parameter Buffer Additional the SAP 53 must be activated by Set Ext Prm Supported bit in Mode Register 0 The Aux Buffer for the Set Ext Prm is the same as the one for Set Prm and has to be different from the Chk Cfg Aux Buffer Furthermore the Spec Prm Buf Mode in Mode Register 0 must not be used together with SAP 53 PROFIBUS DP V1 Acyclic Communication Relationships VPC3 C supports acyclic communication as described in the DP V1 specification Therefore a memory area is required wh
79. r must hold back the first telegram character until the modem acti vates XCTS XCTS is checked again after each character The receiver converts the serial data flow into the parallel data structure and scans the serial data flow with the four fold transmission speed Stop bit testing can be switched off for test purposes Dis Stop Control 1 in Mode Register 0 or Set Prm telegram for DP One requirement of the PROFIBUS protocol is that no rest states are permitted between the telegram characters The VPC3 C transmitter ensures that this specification is maintained The synchronization of the receiver starts with the falling edge of the start bit The start bit is checked again in the middle of the bit time for low level The data bits the parity and the stop bit are also scanned in the middle of the bit time To compensate for the synchronization error a repeater gen erates a 25 distortion of the stop bit at a four fold scan rate In this case the should be parameterized with Dis Start Control 1 in Mode Register 0 or Set Prm telegram for DP in order to increase the permissible distortion of the stop bit ASIC Test All output pins and I O pins can be switched to the high resistance state via the XTESTO test pin An additional XTEST1 input is provided to test the chip on automatic test devices not in the target hardware environment Pin Name Value Function VSS GND All outputs high resistance 34
80. resource RR After finishing the processing of the incoming telegram the INUSE bit is reset and the bits USER and IND are set by VPC3 C Now the FDL Ind interrupt is generated Polling telegrams do not produce interrupts The RESP bit indicates response data provided by the user in the Response Buffer The Poll End Ind interrupt is set after the Response Buffer is sent Also bits RESP and USER are cleared 56 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 DP Master PROFIBUS DP Slave Request to acyclic SAP gt fill Indication Buffer short acknowledgement SC Polling telegram to acyclic SAP gt process data short acknowledgement SC update Response Buffer Polling telegram to acyclic SAP gt Response from acyclic Figure 7 5 acyclic communication sequence VPC3 C Firmware set Request_SA Request_SSA set INUSE in Control of Ind_Buf write data in Ind Buf clear INUSE and set USER and IND in Control of Ind Buf set FDL Ind interrupt clear FDL Ind interrupt search for Ind Buf with IND 1 read clear IND in Control of Ind Buf write Response in Resp Buf set RESP in Control of Resp Buf check on RESP 1 read Resp Buf clear RESP and USER in Control of Resp Buf set Response Sent set Poll End Ind interrupt clear Poll End Ind interrupt search for SAP with Response Sent 1 clear Response Sent
81. s is substituted by alarm and status messages In addition to the Ext Diag Data the buffer length also includes the VPC3 C diagnosis bytes Len Diag 1 R Len Diag Buf 2 6 2 5 Write Read Data Data Exchange Default SAP 46 Writing Outputs The VPC3 C writes the received output data in the D buffer After an error free receipt the VPC3 C shifts the newly filled buffer from D to N In addition the DX Out interrupt is generated The user now fetches the current output data from N The buffer changes from N to U with the Next Dout Buffer Cmd so that the current data can be transmitted to the application by a RD Output request from a DP Master Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Interface 6 If the user s evaluation cycle time is shorter than the bus cycle time the user does not find any new buffers with the next Next Dout Buffer Cmd in N Therefore the buffer exchange is omitted At a 12 Mbit s baud rate it is more likely however that the user s evaluation cycle time is larger than the bus cycle time This makes new output data available in N several times before the user fetches the next buffer It is guaranteed however that the user receives the data last received For power on LEAVE MASTER and the Global Control telegram with Clear Data 1 the VPC3 C deletes the D buffer and then shifts it to N This also takes place during power up enterin
82. s used Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 ASIC Interface 5 The polarity of the interrupt output is parameterized via the Int Pol bit in Mode Register 0 After hardware reset the output is low active 5 3 4 Interrupt Request Register Bit Position Address 7 6 5 4 3 2 1 0 Designation 00H Int Req Reg Intel 7 0 Intel E _ Ll F ES _ TN 5 e io Be See below 5 Se le E O G lt gt for coding gt 5 18 s mU 17 x E SS as lt zceau2olso imao lo a zo Bit Position h Address 15 14 13 12 11 10 9 8 Designation 01H g LI Int Req Reg Intel D c lt lt 15 8 o 3O S A OS 5 d m le d 5 al E See below a x Sc amp amp BG forcoding 2 zaj zaj zo VPC3 C User Manual Revision 3 02 29 Copyright O profichip GmbH 2014 5 ASIC Interface Interrupt Request Register Low Byte Address 00 Intel bit 7 DXB Out rw 0 VPC3 C has received a DXB telegram and made the new output data available in the N buffer bit 6 New Ext Prm Data rw 0 The VPC3 C has received a Set Ext Prm telegram and made the data available in the Parameter Buffer bit 5 DXB Link Error rw 0 The Watchdog cycle is elapsed and at least one Publisher Subscriber connection
83. sion 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 Operational Specifications 10 10 6 DC Electrical Characteristics Specification for 3 3V Operation Parameter Symbol MIN TYP MAX Unit DC supply voltage Voc 3 00 3 30 3 60 V CMOS input voltage LOW level 0 0 3 Vcc V CMOS input voltage HIGH level Vinc 0 7 Vcc Vec V Output voltage LOW level VoL 0 4 V Output voltage HIGH level 2 4 V CMOS Schmitt Trigger negative going threshold voltage 0 8 CMOS Schmitt Trigger positive going threshold voltage Vr S V TTL Schmitt Trigger negative going threshold voltage Vr ho id TTL Schmitt Trigger positive going threshold voltage Vr Vet X Input LOW current li 1 1 Input HIGH current lia 1 1 uA Tri state leakage current loz 10 1 10 Output current LOW level 4mA cell lo 2 8 mA Output current HIGH level 4mA cell 2 8 Output current LOW level 8mA cell lo 5 6 mA Output current HIGH level 8mA cell 5 6 Figure 10 6 DC Specification of I O Drivers for 3 3V Operation Note For 3 3V operation the guaranteed minimum output current is 7096 of that for 5V operation mode VPC3 C User Manual Revision 3 02 89 Copyright O profichip GmbH 2014 10 Operational Specifications 10 7 Timing Characteristics All signals beginning with X are low active All timing values are based the capacitive
84. t XWR 2 XWR gc XD 4 lt XRD VDD 34 XTESTO xcrs 33 1K GND VDD 3K3 35 XTESTI 3 E aiu DIVIDER RXD lt RTS RS485 d 7 ABO 26 RSA ABI AB10 41 apo a Abt 40 aps E ABI2 37 apy ABIS a2 e 14 2 M 15 si ass Das AB 15 8 K 29 ABg s gt 1K 25 AB9 DB7 10 Figure 8 6 80C32 Application in 2K Byte mode lt pC gt DB 7 0 The internal chipselect is activated when the address inputs AB 10 3 of the VPC3 C are set to 0 In the example above the start address of the VPC3 C is set to 1000H Processor AD 7 0 AB 10 8 AB 15 11 VPC3 B 8 gt address latch 11 8 gt all bits zero gt CS gt gt internal address 1 decoder internal chip select Figure 8 7 Internal Chipselect Generation in Synchronous Intel Mode 2K Byte RAM VPC3 C User Manual Copyright O profichip GmbH 2014 Revision 3 02 81 8 Hardware Interface 8 1 5 Application with 80C32 4K Byte RAM Mode VPC3 48 MHz CLK GND 4K 8 XINTIMOT cuk2 Z pe gt gt 36 RESET XDATAEX 5 13 LED for Data Exchange XREADY 1
85. t 2 1 r 00 Clock Value SYF Synchronisation Active Status 0 Clock Value Time Event is synchronized x 1 Clock Value Time Event is not synchronized r 0 Clock Value Time Event Same format as defined in IEC 61158 6 is used Value is stored with the most significant byte at the lowest address No address swapping is done for Intel format r 0 Receive Delay Time Value is stored with the most significant byte in address 12 No address swapping is done for Intel format r 0 Clock Value previous TE Same format as defined in IEC 61158 6 is used Value is stored with the most significant byte at the lowest address No address swapping is done for Intel format rw 0 Clock Sync Interval Value is stored with the most significant byte in address 24 No address swapping is done for Intel format Figure 7 23 Format of the Clock Sync Buffer 72 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 VPC3 C Firmware set CS_Supported reception of Set Ext Prm set New Ext Prm Data interrupt acknowledge interrupt write Clock Sync Interval to CS Buffer reception of Time Event start Receive Delay Timer reception of Clock Value set Clock Sync interrupt read CS Status IF Set Time 1 THEN stop Receive Delay Timer read CS Buffer update system time END IF acknowledge interrupt Figure 7 24 communication scheme VPC3 C User Manual Revision 3 02 7
86. ted in the VPC3 C and is handled independently The user must correspondingly parameterize the ASIC and process and acknowledge received messages All SAPs are always enabled except the Default SAP SAP 56 SAP 57 and SAP 58 The remaining SAPs are not enabled until the DP SM goes into the DATA EXCH state The user can disable SAP 55 to not permit changing the Station Address The corresponding buffer pointer R SSA Buf Ptr must be set to OOH for this purpose The DP SAP Buffer Structure is shown in Figure 6 1 The user configures all buffers length and buffer start in the Offline state During operation the buffer configuration must not be changed except for the length of the Dout Din Buffers The user may still adapt these buffers in the WAIT CFG state after the con figuration telegram Chk Cfg Only the same configuration may be accepted in the DATA EXCH state The buffer structure is divided into the data buffers Diagnosis Buffers and the control buffers Both the output data and the input data have three buffers available with the same length These buffers are working as changing buffers One buffer is assigned to the data transfer D and one buffer is assigned to the user U The third buffer is either in a next state N or a free state F One of the two states is always unoccupied For diagnosis two Diagnosis Buffers that can have different lengths are available One Diagnosis Buffer D is always assigned to the VP
87. ters have to be transmitted from the DP Master to the DP Slave the Aux Buffer 1 2 must have the same length as the Parameter Buffer Sometimes this could reach the limit of the available memory in the VPC3 C When Spec Prm Buf Mode 1 the parameterization data are processed directly in this special buffer and the Aux Buffers can be held compact VPC3 C User Manual Revision 3 02 19 Copyright O profichip GmbH 2014 5 ASIC Interface Mode Register 0 Low Byte Address 06H Intel bit 7 Freeze Supported Freeze Mode support rw 0 0 Freeze Mode is not supported 1 Freeze Mode is supported bit 6 Sync Supported Sync Mode support rw 0 0 Sync Mode is not supported 1 Sync_ Mode is supported bit 5 Early Rdy Early Ready rw 0 0 Normal Ready Ready is generated when data is valid write or when data has been accepted read 1 Ready is generated one clock pulse earlier bit 4 INT Pol Interrupt Polarity rw 0 0 The interrupt output is low active 1 The interrupt output is high active bit 3 CS Supported Enable Clock Synchronization rw 0 0 Clock Synchronization is disabled default 1 Clock Synchronization is enabled bit 2 WD Base Watchdog Time Base rw 0 0 Watchdog time base is 10 ms default state 1 Watchdog time base is 1 ms bit 1 Dis Stop Control Disable Stopbit Control rw 0 0 Stop bit monitoring is enabled 1 Stop bit monitoring is switched off Set Prm telegra
88. the oer Dicere 7 0 DP Din Buffer State Machine The user makes a new DP Din Buf 09H New Din Buffer Cmd 1 0 available in he N state Buffer assignment of the CAM Dout_Buffer_SM 70 DP Dout Buffer State Machine The user fetches the last DP OBH Next Dout Buffer Cmd 3 0 Dout Buf from the N state Buffer assignment for the ven Diag Buffer SM 3 0 DP Diag Buffer State Machine New Diag Buffer 1 0 The user makes a new DP Diag Buf available to the VPC3 C The user positively acknowledges User Prm Data Okay 1 0 the user parameter setting data of a Set Ext Prm telegram The user negatively acknowledges OFH User_Prm_Data_Not_Okay 1 0 the user parameter setting data of a Set_ Ext_ Prm telegram The user positively acknowledges 10H User_Cfg_Data_Okay 1 0 the configuration data of a Chk_Cfg telegram The user negatively acknowledges 11H User_Cfg_Data_Not_Okay 1 0 the configuration data of a Chk_Cfg telegram Buffer assignment of the ten DXBout Buter SM 79 DXBout Buffer State Machine The user fetches the last 13H Next DXBout Buffer Cmd 2 0 DXBout Buf from the N state The user has fetched the data from 14H SSA Buffer Free Cmd the SSA Buf and enables the buffer again 15H Mode Reg 1 7 0 Figure 4 2 Assignment of the Internal Parameter Latches for READ VPC3 C User Manual Revision 3 02 15 Copyright O profichip GmbH 2014 4 Memory Organization
89. the user again bit 11 New Prm Data rw 0 The VPC3 C have received a Set Prm telegram and made the data available in the Parameter Buffer bit 10 New Cfg Data rw 0 The VPC3 C have received a Chk Cfg telegram and made the data available in the Config Buffer bit 9 New SSA Data rw 0 The VPC3 C have received a Set Slave Add telegram and made the data available in the Set Slave Add Buffer bit 8 New GC Command rw 0 The VPC3 C have received a Global_Control telegram and stored the Control Command in the R GC Command RAM cell Figure 5 10 Interrupt Request Register High Byte VPC3 C User Manual Revision 3 02 31 Copyright O profichip GmbH 2014 5 ASIC Interface 5 3 2 Interrupt Acknowledge Mask Register The other interrupt controller registers are assigned in the bit positions like the Interrupt Request Register Address Register Reset state Assignment 02H 03H Interrupt Readable only All bits Register IR cleared 04H 05H Interrupt Writeable can All bits set 1 Mask is set and the Mask be changed interrupt is disabled Register during operation 0 Mask is cleared and the IMR interrupt is enabled 02H Interrupt Writeable can All bits 1 Interrupt is Acknowledge be changed cleared acknowledged and the IRR Register during operation bit is cleared IAR 0 IRR bit remains unchanged Figure 5 11 Interrupt Acknowledge Mask Re
90. uld read out the buffer before acknowledging the interrupt The base address of the Clock Sync Buffer depends on the memory mode 2K Byte mode 4 Bit Position A 5 Byte Designation 7 6 5 4 3 2 1 0 o 5 5 E 0 reserved S Status e gt o O e su SS se gt oO 1 reserved k i Command S ic 2 9 o 55 2 C CV reserved Clock Value Status1 TD 3 ANH SWT CR reserved SYF Clock Value Status2 Seconds 222 1 0 since 1 1 1900 0 00 00 4 or since 7 2 2036 6 28 16 if value lt 9DFF4400H Clock Value 11 Fraction Part of Seconds 222 1 0 Time_Event Base is 1 2 Seconds 12 274 0 Receive Delay Time 15 Time Base 1 us Seconds 222 1 0 since 1 1 1900 0 00 00 16 or since 7 2 2036 6 28 16 if value lt 9DFF4400H Clock Value 23 Fraction Part of Seconds 222 1 0 previous TE Base is 1 232 Seconds 24 29 1 0 Clock Sync Interval 25 Time Base 10 ms SUPE 70 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 Clock Sync Buffer Copyright O profichip GmbH 2014 Status Reserved bit 7 2 r 000000 Status Clock Sync Violation bit 1 Wrong telegram or Time period of 2 Tcsi expired after reception of ro Time Event St
91. umber_Low e Il 6 Group Ident 5 n 7 DPV1 Status 1 zl T LL 8 DPV1 Status 2 o 9 T DPV1 Status 3 gt o 2 10 User_Prm_Data 246 Figure 7 18 Format of Set Prm telegram for IsoM 66 Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 DP Slave in a IsoM network To enable cyclic synchronization the Simple Sync Mode the bit DX Int Port in Mode Register 2 have to be set Bit SYNC must not be set The settings of the pulse polarity are adjusted like described in the IsoM For the parameterization telegram the DP format is used Though the DPV1 Status bytes 1 3 could be used as User Prm Data it is generally recommended starting the User Prm Data at byte 10 Bit Position Byte Designation 7 6 5 4 3 2 1 0 WI E Uu E S of 0 Station Status O 5 N 20 58219 oz gt Qu wn 1 WD Fact 1 2 WD Fact 2 3 minTspr 4 Ident_Number_High 5 Ident_Number_Low n 6 Group Ident 5 7 DPV1 Status 1 8 DPV1 Status 2 9 DPV1 Status 3 10 User Prm Data 246 Figure 7 19 Format of Set Prm for DP Slave using isochrones cycles In opposite to IsoM the DX Out interrupt is generated first after the receipt of a SYNCH telegram If no Data Exchange telegram had been received before a SYNCH occ
92. urred no synchronization signal is generated For this mechanism the interrupt controller ist used Hence no signal will be generated if the mask for DX Out in the IMR is set Since the synchronization signal is now the DX Out interrupt it remains until the interrupt acknowledge VPC3 C User Manual Revision 3 02 67 Copyright O profichip GmbH 2014 7 PROFIBUS DP Extensions 7 3 3 CS Clock Synchronization 68 The Clock Synchronization mechanism synchronizes the time between devices on a PROFIBUS segment A time master is a DP Master The scheme used is a backwards time based correction The knowledge of when a special timer event message was broadcasted is subsequently used to calculate appropriate clock adjustments The synchronized time can be used for time stamp mechanism Time Master Output Time Event Clock Value gt l Time Receiver Input Time Event Clock Value gt Time Receiver Application gt le P lt P lt tsp tor lap Tz i 1 2 3 4 1 Time Event 2 Clock Sync Interrupt 3 read access Receive Delay Time 4 update system timer Figure 7 20 clock synchronization mechanism The clock synchronization sequence consists of two messages broadcasted by the time master When the first message called Time Event is received the VPC3 C starts the receive delay timer tgp The time master then sends a second message called
93. w cost application 8 1 2 Bus Interface Unit The Bus Interface Unit is the interface to the connected processor microcontroller This is a synchronous or asynchronous 8 bit interface with an 11 bit 12 bit in 4K Byte mode address bus The interface is configurable via 2 pins XINT MOT MODE The connected processor family bus control signals such as XWR XRD and the data format is specified with the XINT MOT pin Synchronous or asynchronous bus timing is specified with the MODE pin XINT MOT MODE Processor Interface Mode 0 1 Synchronous Intel mode 0 0 Asynchronous Intel mode 1 0 Asynchronous Motorola mode 1 1 Synchronous Motorola mode Figure 8 1 Configuration of the Processor Interface Examples of various Intel system configurations are given in subsequent sections The internal address latch and the integrated decoder must be VPC3 C User Manual Revision 3 02 75 Copyright O profichip GmbH 2014 8 Hardware Interface used in the synchronous Intel mode One figure shows the minimum con figuration of a system with the where the chip is connected to an EPROM version of the controller Only a clock generator is necessary as an additional device in this configuration If a controller is to be used without an integrated program memory the addresses must be latched for the external memory Notes If the VPC3 C is connected to an 80286 or similar processor it must be taken
94. will be detected Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 Data Ex SYNCH SYNCH Data Ex GC SYNCH telegrams IsoM SYNC DX Out New GC Command Simple Sync Mode SYNC DX Out New GC Command Figure 7 17 SYNC signal and interrupts for synchronization modes picture only shows the effects by reception of telegrams time between telegrams is not equal Isochron Mode To enable the Isochron Mode in the VPC3 C bit SYNC in Mode Register 2 must be set Additionally the Spec Clear Mode in Mode Register 0 must be set The polarity of the SYNC signal can be adjusted with the SYNC Pol bit The register Sync PW contains a multiplicator with the base of 1 12 us to adjust the SYNC pulse width Settings in the Set Prm telegram are shown below The Structured Prm Data block IsoM Structure Type 4 is also required for the application If it is sent by Set Prm telegram the bit Prm Structure must be set VPC3 C User Manual Revision 3 02 65 Copyright O profichip GmbH 2014 7 PROFIBUS DP Extensions Bit Position 5 5 Byte Designation 7 6 5 4 3 2 1 0 e 7 g g 0 E Station Status N c o gt 1 WD Fact 1 2 WD Fact 2 3 minTspr 4 Ident_Number_High 5 Ident_N
95. with DXB Linktable specific link is grey scaled VPC3 C User Manual Revision 3 02 59 Copyright profichip GmbH 2014 7 PROFIBUS DP Extensions 60 Bit Position 7 Byte Designation 7 6 5 4 3 2 1 0 0 Structured Length 1 1 1 Structure Type Slot Number Reserved e m 1 Version Publisher Addr Publisher Length Sample Offset Dest Slot Number N Offset Data Area Sample Length further link entries 120 Figure 7 9 Format of the Structured Prm Data with DXB Subscribertable specific link is grey scaled The user must copy the link entries of DXB Linktable or DXB Subscribertable without Dest Slot Number and Offset Data Area in the DXB Link Buf and set R Len DXB Link Buf Also the user must enter the default status message in DXB Status Buf with the received links and write the appropriate values to R Len DXB Status Buf After that the parameterization interrupt can be acknowledged Revision 3 02 VPC3 C User Manual Copyright profichip GmbH 2014 PROFIBUS DP Extensions 7 Bit Position Designation 7 6 5 4 3 2 1 0 0 0 0 Block Length Header Byte 1 1 0 0 0 0 0 1 1 Status Type 2 0 0 0 0 0 0 0 Slot Number
96. wl edge Register IAR uP INT_POL Figure 5 8 Block Diagram of Interrupt Controller Each event is stored in the IRR Individual events can be suppressed via the IMR The input in the IRR is independent of the interrupt masks Events that are not masked in the IMR set the corresponding IR bit and generate the X INT interrupt via a sum network The user can set each event in the IRR for debugging Each interrupt event that was processed by the microcontroller must be deleted via the IAR except for New_ Ext_ Prm_Data and New_Cfg_ Data A logical 1 must be written on the specific bit position If a new event and an acknowledge from the previous event are present at the IRR at the same time the event remains stored If the microcontroller enables a mask subsequently it must be ensured that no prior IRR input is present To be on the safe side the position in the IRR must be deleted prior to the enabling of the mask Before leaving the interrupt routine the microprocessor must set the end of interrupt bit EOI 1 in Mode Register 1 The interrupt output is switched to inactive with this edge change If another event occurs the interrupt output is not activated again until the interrupt inactive time of at least 1 us or 1 ms expires This interrupt inactive time can be set via EOI Time Base in Mode Register 0 This makes it possible to enter the interrupt routine again when an edge triggered interrupt input i
97. write signal XWR The VPC3 C generates the Ready signal synchronously to the system clock The Ready signal gets inactive when the read or the write signal is deactivated The data bus is switched to Tristate with XRD 1 DB7 0 lt 24 XRD XCS XREADY normal XREADY early lt OJ gt Figure 10 12 Asynchronous Intel Mode READ XWR 1 VPC3 C User Manual Revision 3 02 93 Copyright O profichip GmbH 2014 10 Operational Specifications AB10 0 valid DB7 0 XWR XCS XREADY normal XREADY early rl OJ Figure 10 13 Asynchronous Intel Mode WRITE XRD 1 VDD 3 3 V VDD 5V No Parameter MIN MAX MIN MAX Unit 16 address setuptime to XRD XWR 0 0 ns 17 XRD 4 to data valid 103 97 ns 18 XRD pulsewidth 115 115 ns 19 XCS J setuptime to XRD XWR 4 0 0 ns 20 XRD to XREADY 1 Normal Ready 132 126 ns 21 XRD J to XREADY Early Ready 111 105 ns 22 XRD XWR cycletime 125 125 ns 23 address holdtime after XRD XWR T 0 0 ns 24 data holdtime after XRD T 4 16 4 13 ns 25 read write inactive time 10 10 ns 26 XCS holdtime after XRD XWR T 0 0 ns 27 XREADY holdtime after XRD XWR 6 21 5 16 ns 28 data setuptime to XWR T 10 10 ns 29 XWR pulsewidth 83 83 ns 30 data holdtime after XWR T 10 10 ns Figure 10 14 Timing Asynchronous Intel Mode

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