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THE BUTTER PROJECT, A TEST CASE.

1. Figure 7 An example of the filling facility 11 2 4 A formal description of the blitter For further design we need a more precise description of the blitter To get a formal description of the circuit we wrote a C program with same functionality as the blitter I this way we got an exact description of what the blitter should do We will discuss only the major procedures of the program The complete source text can be found in Appendix 2 4 1 The main loop After a reset the blitter waits until it is addressed to load one of its registers This is the case if the pin ce chip select becomes high The addressed register is loaded with the data on the databus and the blitter starts scanning ce again This cycle is repeated until the blitter register BLTSIZE is loaded This register contains the size of the window the blit has to be performed upon If this register has been loaded the procedure blit is started to perform the blitter operation main while TRUE address get reg addr port if get chip select wait until ce high data get data bus write register reg address data if reg address BLTSIZE blit start processing put interrupt 1 Figure 8 The main loop After the blit has finished the blitter will start loading its registers again Most of the registers will still contain their old value It is possible and allowed to use them again wi
2. 0 for y 0 SCR y printf 0 69 Eskiss input for the main controller this state machine controls the the blitting process Wim Philipsen July 19 1988 11 takes care of loading the x and y counters and of the first word timer The counter is supposed to take care of the last word timer To this controller belongs a logic circuit with 2 downcounters one for x and one for y And a register containing the size 4 value The x counter has an output line that is high if the contence of the register is one This line is used as last word timer inputs zero x x zero flag one y y one flag ce chip enable size size addressed by the decoder 1 if yes usea useb outputs load y re ioad y counter 4 load x re load x counter fwt first word timer tr_x trigger x counter tr trigger y counter tr 014 load aold register L tr bold load bold register zero a b 0 do not use a and b addr en r read from address port addr tr trigger address bus latches cee data data tr dec en tr sta read start tr bdat tr cdat tr 70 read from data port trigger data bus latches enable address decoder for register load address generator can calculate the next adderss start the read cycle store a data store b data store c data xycsabcpr 10 0 ge
3. 1 4 int10 7 110 sub9 sub9 SUb10 sub10 Figure 38 Example of the output of log mapper The register generator Log mapper can add master slave registers for a two phase non overlapping clock for you This is only possible if you use aoi gates To use the build in register generator include the following line in the inputfile register inputvar outputvar Log mapper now automatically includes a register in the outputfile The clock signals will have the names PHIL 2 An example of register declaration register SN4 054 The corresponding output lines for one of the registers 46 register 054 7 621 PHli G22 G21 054 1 G23 G22 23 PHI2 SN4 G23 022 PHI2 SN4 An other facility is a comparison and a tautology test of two sets of boolean functions The inverter optimalization is sensitive to long carry paths For example my function logop which has a very long carry path took over half an hour But the shifter with even more transistors takes only five minutes Log mapper was written in Lisp There were some problems because the lisp system needs a lot of memory If there are cyclic definitions in the input you will get a lisp stack overflow The machine then enters the lisp debugger You can the debugger with the command quit If the delay times estimated by log mapper
4. see schema fig 6 15 page 196 61 WORD bltAold bltBold bltCold source data registers see Appendix C page C 2 PORT reg addr port R W R register address W RAM address ram_addr_port W port rest RAM address data bus port data reading and writing data_bus_req W port request for data bus dma_req acknowledge from DMA controller ram write W pon selects read write from to RAM chip_select register read enable interrupt W port interrupt when blit completed PORT unsigned int get loadmem fM MAIN ROUTINE main UBYTE reg address WORD data these should be declarations actually reg addr port port 8 reg addr ram addr port 10 ram data bus port 16 data bus data bus req port 1 data bus req req 1 req ram write port 1 ram write chip select port 1 chip select interrupt 1 interrupt initialisation of the screen memory 0 while TRUE reg address get reg addr port if chip select data get data bus write register reg address data if address BLTSIZE put interrupt 1 62 write register add
5. fe sk ep dla 09 23 Blitter Features 3 3 2 3 1 Datacopying 6 2 3 2 Pointers and modulos 6 2 3 3 Ascending and descending addressing 7 2 3 4 Shif ng 7 2 3 5 Logic operations 8 2 3 6 Masking 9 2 3 7 Areafilling 9 24 formal description of the blitter 2 4 1 The mainloop 11 24 2 The blitting part 12 24 3 Logic operations 14 2 4 4 The Communication 14 2 5 Escher simulation 2 5 1 Escher scheme y 2 5 2 The control unit 18 2 5 3 Registers 18 2 5 4 The behaviour of mask 19 2 5 5 Logop 19 2 5 6 Shift 19 2 5 7 Display 20 2 6 Final design PES 2 6 1 The main controller 22 2 6 2 Address generator 25 2 6 3 Logic unit 34 2 6 4 The size controller 35 2 6 5 register address decoder 36 The ES design system 5 os ae UR 3 2 EUCLID 32 1 LOG SIM The logic simpli 3 2 2 LOG DECOM 41 3 2 3 LOG MAPPER 44 3 2 4 Cell generation 46 3 3 Placementand routing 3 3 1 MACPLACE Pluri cell Placer 47 3 3 2 The floor planner 49 3 3 3 ROCOCO The Router 49 34 ESCHER Schematic Editor and Behaviour Evaluator 3 4 1 Introduction to escher 52 3 42 escher simulator 52 3 5 EULER The Layout Editor ee we we we 3 6 SLS Switched Level Simulator ew ew 3 7 DALI Delft
6. abcef acgf f schedtime 10 delay 5 11110 b schedtime 6 delay 4 gatecount 6 torcount 76 Figure 37 Output of log_decom for the little example Cyclic expressions can cause a crash You ll probably get this error message unable to unwind stack because of invalid stack frame process manager process fault manager Runtimes are small Up to a few minutes for very large examples 3 2 3 LOG MAPPER Log mapper maps input file which must be in logic syntax format onto a set of standard cells The standard cell to chose from are aoi and or invert gates nor nand or ao and or gates The user can also specify the size of the gates The default values are right for the standard NMOS process There are a number of different functions the user can chose from Some of these functions can lead to very long runtimes The functions are described in the manual page mapper has to be called with log mapper lt input file gt options The output are files lt filename gt db and lt filename gt gf The file filename db contains a readable description of what log mapper has done and some debugging information The file filename gf contains a description of the circuit in logic syntax and can be used as input for log celgen With the options the users can chose between the different optimizations the kind of cells to be used and the siz
7. display printf This is in memory 0 for y 0 lt SCR y printf 0 for x 0 x SCR x for i 15 1 gt 0 prinif 9614 SCR x prinif 9614 y 10 0 loadmem FILE fopmQ int ij if fp fopen screen r 0 printf can t open file 5 exit 1 else for i 0 i lt MEM SIZE i fscanf fp 9od 1 menmf i j include lt stdio h gt include blitter h BLITTER REGISTERS see page 2 4 WORD 0 control register 0 WORD bltcon 0 control register 1 WORD bitsize 0 size of window if written starts blit ADDRESS 0 high low source C pointer ADDRESS bltBpt 0 high low source B pointer ADDRESS bltApt 0 high low source A pointer ADDRESS 0 high low destination D pointer WORD bltAfwm 65535 bltAlwm 65535 lt 1 1 word masks for WORD bltCmod 0 bltBmod 0 bltAmod 0 modulo s for C B and A respectively WORD bltDmod 0 modulo for destination D WORD bltAdat 0 bltBdat 0 bltCdat 0 source data registers WORD bitDdat 0 destination data register SCREEN MEMORY
8. ADDR addr hr addr RAM ADDR addr put data bus addr data pat data if BIT USED 0 putword bltDpt bltDdat if BIT DESC 1 bltDpt else include lt stdio h gt define TRUE 1 define FALSE 0 define PORT unsigned int just to fool the compiler typedef unsigned shon WORD typedef unsigned char UBYTE typedef unsigned long ADDRESS define MIN a b a lt b a b define gt define BIT i a a gt gt i amp 1 define SHIFT a b n d WORD d lt lt 16 lt lt gt gt 16 amp OxFFFF 8 b lt lt 16 gt gt amp OxFFFF define MASK i 1 lt lt i Reading shift values from the control registers rest is extracted using BIT define SH a gt gt 12 amp Oxf define USEA 1 define USEB 10 define USEC define USED 8 define EFE 4 define IFE 3 define define DESC 1 define LINE 0 Reading sizes from size register define WIDTH a amp Ox3f define HEIGHT a a gt gt 6 amp Ox3ff On input addresses written in two parts bits 1 15 LOW 16 18 HIGH PUTLOW a d amp Ox7fff d gt gt 1 amp Ox7fff define PUTHIGH a d amp Ox7fff 4 amp 0 7 lt
9. BIT DESC bltCold fco put data if WIDTH bltsize gt 1 get data bltAdat bltAdat amp bltAlwm bliDdat logop SHIFT bltAold bltAdat 5 BIT DESC bltconl SHIFT bltBold bltBdat SH BIT DESC bltCold put data else bltAdat bltAdat amp bltAlwm bltDdat logop SHIFT bitAdat 0 SH BIT DESC SHIFT bltBdat 0 SH bitcon1 BIT DESC bltcon bitCdat fco put data if BIT DESC bltconl bltApt bltAmod bltBpt bltBmod bltCpt bltCmod bltDmod else bltApt bltBpt bltBmod bitCpt bitCmod bltDpt bltDmod LOGIC OPERATION WORD logop Adata fco WORD Adata Bdata Cdata WORD ddat int j ddat BIT 7 bltcon0 Adata amp Bdata amp BIT 6 bltcon0 Adata amp Bdata amp BIT 5 bltcon0 Adata amp Bdata amp Cdata 4 bltcon0 Adata amp Bdata amp BIT 3 Adata amp Bdata amp Cdata BIT 2 bltconO Adata amp Bdata amp BIT 1 bltconO Adata amp amp 0 Adata amp amp Cdata if BIT IFE bltc
10. Bdata amp Cdata 4 bltcon0 Adata 4 Bdata amp Cdata 3 bltconO Adata amp Bdata amp Cdata 2 bltcon0 Adata amp Bdata amp Cdata BIT 1 bltconO Adata amp Bdata amp Cdata 0 bltconO Adata amp Bdata amp if BIT IFE bltcont BIT EFE bltcont for 0 lt 16 j fco fco BIT ddat if BIT EFE bltcont 1 if fco 1 ddat ddat MASK else ddat ddat amp MASK j if BIT IFE bltcont if fco BIT ddat ddat ddat MASK else ddat ddat 4 return ddat Figure 10 logic operations 2 4 4 The Communication protocol There are three types of communication First in the set up phase the blitter reads the contents of the register bus and the databus to get the register address and the value to be stored in the register During the 15 blit the blitter can read data from memory or write data to memory Because there was no clear description of the protocols used by the Amiga blitter we made some for our selves We used for the program a protocol that was easy to implement in C It is always possible to alter afterwards the protocol because it is not a real part of the blitter Any other protocol can be implemented without dramatic changes of the blitter 2 4 4 1 Loading the registers The code for the
11. Our 19 bit address bus enables our blitter to address the lower 512 word 1024 kbyte of memory twice as much as the amount of the Amiga blitter Because each channel has its own pointer and modulo registers each channel can address a bitplane with different sizes and at different locations When the blitter has to perform an operation on a part of an image the blitter uses the modulo registers The modulo is the difference of the width of the larger image and the smaller window that the blitter should operate upon The modulo is added to address at the end of each line Because each channel has its own modulo register each channel may address a window within a larger bit plane with different sizes Figure 3 A window within a larger image Figure 3 shows an example of an image larger as the window used To operate upon the smaller window only the address sequence must be as follows 19 20 21 26 27 28 33 34 35 This requires a normal increment of two each time and at the end of each window line the additional jump value the modulo to bring the pointer to the start of the next window line The module is 8 in this case so the original width of the image was 7 words 2 3 3 Ascending and descending addressing It is important to be able to control the direction of addressing when source and destination areas overlap When you want to move the data to a lower address in memory you use ascending and and when you wan
12. 0 rd c 1 rd put wt pt wt pt en d wr d wr d 0 tr x wt c pt rd c rd c calc put wt pt d wt pt d en d wr d wr d tr_x other 000000000000000000 000000000000001000 000000000000000000 000000000000000010 000000000000000010 000000000000000000 000000000000001000 000000000000000000 000000000000000001 000000000000000000 000000000000000000 000000000000000000 000000000000000110 000000000000000111 000000000000000110 001100000000000000 000000000000000000 wait until read save c dat and goto new wrd load x goto getdata first go get B go get C do nothing wait until pt 1 start read cycle wait until save adat and go get B save adat and go get C save adat and goto calc wait until pt 1 start read cycle wait unti read save bdat and goto calc save bdat and go get C wait until pt 1 start read cycle wait until data read save dat and goto calc data loaded wait or calculations wait logop finished wait until pt enable ddat and d address start write cycle wait until ready d saved 9X get next data save last data word of put wt pt wt pt en d d wr d tr y tr y this try put line wt pt d pt d en d wr d wr d y Id x 0 000010000000000000 000000000
13. b b cb aie d e The output data sim The file listing for a different input with some error messages 1 2d ecb 714 15 REMARK 713 Error Summary Number of errors this compilation 3 13 expected inserted 14 77 expected inserted 15 identifier expected Number of lines processed 2 If there is already a file listing then this file will not be removed This can be confusing when log sim reports an error but you can t find it in the listing Remove the file listing and run log sim again If you have big input files with many different variables pay attention If the number variables in the input exceeds a certain number something between 30 and 40 log sim will generate bad but syntactic good output A solution for this program is to split the input file into pieces and run log sim on each piece separately Since log sim can only find simplifications within a line the results will be the same Log sim doesn t accept the comment in the form of a line starting with an Runtimes for log sim are small Up to a few minutes for very large examples 3 2 2 LOG DECOM Decomposition and minimization of boolean expressions log decom decomposes a set of boolean 42 expressions boolean expression is a redundant set of cubes cube is a product term To obtain nonredundant set of cubes log sim can be used log decom tries to fi
14. lt netname gt and lt pinname gt equal to the name of the pin in the interface file Supply pins are treated differently way by the router It requires two pins for each supply net thus we also need two nets in the netlist for each supply net Macplace is called with 48 macplace options lt netlist file interface file gt Different aspect ratios will lead to different areas The differences can be very large Table shows the results for a rather small example This causes the strange effects for 1x3 and 3x1 The layout for 2x1 was much higher than necessary width height 487512 390642 596484 1631016 599550 TABLE 2 The areas of pluri cell layout for a small multiplexer for different aspect ratios For a larger circuit the results are stated in table 3 ____ __ mma width height area width height 4 1 11016 1865 20544840 10124 2011 8840 2041 18042440 8520 1969 6178 2587 15982486 6310 2561 3752 4132 15503264 1 3 2189 10184 22292776 2579 11006 28384474 1 4 2195 12317 27035815 2243 12643 28358249 area 20359364 16775880 16159910 TABLE 3 The areas of pluri cell layout for the shifter for different aspect ratios The placement generated by macplace often show a hill in the center The columns in the center are much higher as those at the left and right sides The o
15. 32 0 0 0 DO 000000001 1 0 0 C1 100000010 0 C1 C2 000100010 00 C2 C2 000100010 10 C2 DO 000000001 the same cycle for D channel 0 0 DO start 000001000 1 0 DO D1 100000001 0 02 000010001 00 02 02 000010001 10 02 start 000001000 Figure 27 ESKISS description the address generator controller Pluri cell layout has been generated for this module using the register generator of log mapper Both the gate file and the extracted layout have been simulated with SLS den w MLO MO ML cen E ar ee EE was cup E trptb PA sta juo eU suele eee eS I I useb usea ka o Imo vdd VSS 0 200 6 400 6 600 6 800 6 1000 6 Figure 28 51 5 simulation output for the controller 24 In this simulation the lines USEA and USED were high These addresses are calculated with enabling the the register AEN or DEN high and then storing the next address TRPTA or TRPTB high There are still many spikes on the output lines They are generate when after a change of the inputs the system
16. Advanced Layout Interface Ihe C sOUFCe wA XI Eskiss input forthe main controller 6 6 2 6 ew ew te REFERENCES 17 21 38 41 47 52 54 57 58 67 70 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 LIST OF FIGURES The Direct Memory Access system The addresses of an image in memory A window within a larger image example of shifting The minterms selected by LF control An example of masking An example of the filling facility The main loop The blitting part logic operations Reading from memory Reading with validation Writing to memory Escher simulation scheme The blitter circuit Behaviour to ESKISS translation example State machine for the main controller Get data state machine put data state machine address generator boolean description of a full adder Boolean description for the adder Gate description for one d flip flop Boolean description for a 2 channel 4 bit multiplexer Layout for a small multiplexer State machine
17. are compared with those calculated with extraction and simulation Log mapper seems to be rather optimistic 3 2 4 Cell generation 3 2 4 1 Log euler Log euler is the next step towards a pluri cell layout The pluri cells consist of a column of transistors for one cell or a linear transistor array Log euler finds a transistor ordering for this linear transistor array The input for the program is a file with gate description in the gate syntax format Log euler also determines the width of each driver transistor The result is such that for each input pattern for the cell the resulting low output voltage will be smaller then 0 5 Volt Log celgen has to be called with 104 euler lt inputfile gt The transistor ordering is written to standard output and can be redirected or piped into log celgen Log celgen generates from this output the layouts of the cells This output contains some control characters which complicates reading In general this isn t a problem because the user can t do anything with the intermediate results between log euler and 10 celgen Log euler writes to stder the name of the input file the error messages and whether the inputfile contained errors Or not The version installed now is from April 1988 When it was installed it still contained a nasty bug The output generated was syntactic all right but not correct 3 2 4 2 log celgen Log celgen reads the transistor ordering made by log euler and genera
18. current escher it is not possible to give a net a specific name This will be possible in the new versions of escher The placer consists of several programs to be executed through a make file They are not easy to use Many programs operate upon absolute file names and error handling is not poor programs were encoded in Pascal Net and modules are generally stored in arrays When placing large circuits it is possible that the arrays are not big enough and thus they have to be recompiled with larger constants In one case the nets were stored in a set Because in the Apollo Pascal the number of elements in a set is limited to 256 in other dialects it might even be less This puts an absolute limit to the number of nets of 256 With Pastoc PAScal TO C compiler a C version was made that allows far more 3 3 3 ROCOCO The Router After all modules have been placed they have to be connected Rococo Routing with Contour Compaction takes care of To do this it needs four files technology file lt ldm file lt netlist gt interface file gt In the technology file there has to be a description of the used technology The technology file in fusr local lib for the process is nearly all right Only the at the tag NAMES the name of the floorplan has to be added at the end of the line Default this is root for the placements made by macplace and floor for those by the floorplanner Thus
19. default it is not possible to use always the same technology file In the Cakefile used by us the name root is alway replaced by floor to be able to use always the same technology file The ldm file has to contain layout descriptions of all the used models and a description of the floorplan The floorplan has to be the last module in the ldm file For placements made by macplace the same netlist can be used as for macplace For a placement made with the floorplanner the nets for the terminals have to be added to the file terminal This has to be done after the the floorplan has been made because the floorplanner can t cope with these nets The interface file is similar to the one used by macplace When you use the floorplanner it has to be made manually else the file made for macplace can be used here also In our cake system this file will be generated form the escher interface file Rococo has to be called with 50 rococo t tech file lt ldm file lt netlist gt interface file There is not yet a manual page Run times are small For my largest examples it took up to 10 minutes The supply nets are routed in a special way They are the only nets which will be implemented completely in metal other nets will routed using both metal and poly To route the supply nets the router starts searching from the left bottom point for one supply net and at right top point for the other From those points it starts to g
20. first kind is included in the main loop see section 2 4 1 The blitter keeps reading the reg address port until it is chip select is high At that moment it reads the word from the data bus and transfers that word into the addressed register It repeats this cycle until the register BLTSIZE is loaded with a value When the processor has written a value to the BLTSIZE register the blitter starts the blit defined by the contents of it is registers There is no acknowledgement from the blitter to the processor but because the blitter is at that moment only reading it will not be difficult to define a certain data valid period If this solution is impossible it is always possible to use the request lines for validation 2 4 4 Reading from memory This is the piece of code in the program that takes care of reading one word from the address stored in addr in memory reading from memory WORD getword addr ADDRESS addr put data bus req 1 request for cycle while get dma req 0 cycle available put ram write O select read put reg addr port REG ADDR addr write address put ram addr port RAM addr return get data bus read data 4 Figure 11 Reading from memory When the blitter wants to read from memory it puts the data bus request line high After the dma req line is pulled down it puts the ram write to O and loads the address into reg addr port and r
21. for the address generator controller ESKISS description for the address generator controller SLS simulation output for the controller The logic unit One bit mask One cell for logop The size controller The connection between the tools iii 9 0 3 QN w 11 13 14 15 16 16 17 21 22 24 24 25 26 27 28 29 29 29 30 32 33 34 34 35 36 39 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Inputfile for ESKISS An example of the file decom config Input example for log decom Output of log decom for the little example Example of the output of log mapper Lay out for a cell generated by log celgen Places of the intervals in the interface file Routing example for a supply net 40 42 42 43 45 47 47 50 1 Introduction Vast developments in the Integrated Circuit technology increased the need for Computer Aided Design tools In the Design Automation Group of the department of Electrical Engineering of Eindhoven University of Technology several tools have been developed The goal of this project was to test these tools by designing a chip with them The chip to be designed was a blitter a graphics processor The specifications of an existing blitter have been used to design our own chip This report consists of two parts In the first there is a description of the blitter and its design In the second part We all
22. fsm convert log sim log decom editor log mapper log euler log celgen macplace floor planner escher makevin Figure 33 The connection between the tools Figure 33 shows the connections between the tools Only the tools that have been used in this project are shown The arrows represent a data streams An arrow from the text editor indicates that the intermediate files have to be edited 40 3 1 5 55 This is set of tools that generate a boolean description for state machine description of the state machine has to be prepared with espresso before eskiss can process The syntax for the input file can be found in the the manual for espresso The order of the lines is important The lines with the keywords inputvars outputvars mv type and kiss have to be in the same order as in figure 34 inputvars usea useb usec used reset trstate Outputvars enadder trpta trptb trpte trptd mv 9 6 12 12 5 type fr kiss 1 start 00000 00 start start 00000 01 start 0 00000 0 0 0 BO 00000 1 0 A0 A1 10000 0 A1 BO 11000 0 0 BO co 00000 1 0 BO 1 00000 00 1 1 00000 01 1 B2 10000 0 B2 co 10100 0 0 DO 00000 1 0 C1 00000 00C1 C1 00000 01 C1 C2 10000 0 C2 10010 00 start 00000 10 00 01 00000 00D1 D1 00000 01D1 D2 10000 0 D2 start 10001 end Figure 34 Inpu
23. is not yet settled They can be removed by latching the outputs 34 2 6 3 Logic unit The logic unit contains everything concerned with processing of the data When comparing the Escher scheme with this on we see one major difference Because layout for the shifters became very large we decided to use one shifter to shift both the A and B channel This cost some additional multiplexers and registers but saves one large shifter The registers and multiplexers used are in principle the same as those from the address generator fun 16 usea FEENITES cdattr bdattr s EE boldtr Figure 29 The logic unit 2 6 3 1 mask For the mask the boolean description is obvious Figure 30 gives the boolean description for one bit The complete mask consists of 16 such bits kO fwmO fwt nO wmO Iwt outO nO ind Figure 30 One bit mask This boolean description will give a masking unit described in section 2 3 6 and 2 5 4 A pluri cell layout has been generated After an extraction we simulated the mask with 51 5 to verify the layout 35 2 6 3 2 shifter Shifting is done in stages First we do 8 bit shift or not depending on the most significant bit of the shift value With this new bit vector we do 4 bit shift followed by a 2 and a 1 bit shift The generated layout for the shifter has been simulated with SLS the line desc has a very large fanout The value of desc
24. lt 7 Addresses are written to two address ports reg 1 8 and ram 9 17 REG ADDR a amp Oxff RAM ADDR a gt gt 8 amp define 0 define 1 define C 2 define D 3 define BLTCONO 0x40 define BLTCON1 0x42 define BLTAFWM 0x44 BLTALWM 0x46 define BLTAPTH 0x50 define BLTAPTL 0x52 BLTBPTH 0 4 define BLTBPTL 0 4 define BLTCPTH 0x48 define BLTCPTL 4 BLTDPTH 0x54 define BLTDPTL 0x56 define BLTAMOD 0x64 BLTBMOD 0x62 define BLTCMOD 0x60 define BLTDMOD 0x66 define BLTADAT 0x74 define BLTBDAT 0x72 define BLTCDAT 0x70 define BLTDDAT 0x0 define BLTSIZE 0x58 67 defining the width and the hight of the screen sidefine SCR 4 byte count I define SCR 20 define MEM SIZE SCR W SCR Winclude lt stdio h gt define SCR 20 SCR W 4 define MEM SIZE SCR W SCR BIT i a gt gt G amp 1 int i MEM SIZE loadmemQ for i 0 i lt MEM SIZE i printf 964 i displayQ loadmemO FILE fopmQ im ij if fp fopen screen r 0 printf can t open file screen O exit 1 else for i 0 i lt MEM SIZE i fscanf fp Fod amp j j display printf This is in
25. placed in a floorplan with the floorplanner and routed with rococo 3 3 4 MACPLACE The Pluri cell Placer Macplace computes a placement for the cells generated by log celgen The input for macplace is the netlist in general the netlist generated by log celgen and an interface file The interface file has to have the following format module module name shape width height pin name interval pin end After the keyword module the user has to give the name of the module With shape the user can control the aspect ratio The width and height should be given in layout units If the given area is to small macplace will give a warning and generate a module with the desired aspect ratio With the pin definitions the interval in which the pin has to be placed can be defined The interval is two floats in the range from 0 to 4 that describe the preferred placement of the terminal e g upper side 2 3 leftup 33 5 north 3 2 west east 4 south 1 Figure 40 Places of the intervals in the interface file The interfacefile ends with the keyword end The netlist generated by log_celgen is not complete Nets for the connection of the terminals have to be added An item in the netlist has this format lt netname gt lt modulename gt lt pinname gt Typically you have for each pin entry in the interface file one extra line in the netlist With the lt modulename gt the same as in the interface file and
26. simulated with SLS 2 3 The Blitter Features 2 3 1 Data copying The most important function of a blitter is copying large blocks of image data from one location in memory to an other Bitplane images are usually stored in a linear way in memory Each word is stored at the address of it is left neighbour plus one And the first word of a line is stored at the address of the last word of the previous line plus one Figure 2 shows an example of a representation of a bit plane Each address accesses one 16 bit word The blitter needs only to know the starting point the width and the height in the example 10 7 and 5 After the processor has loaded the registers of the blitter the blitter performs the transfer independently of the processor To get access to the memory it claims DMA cycles from the DMA manager When it has finished the blit operation the blitter signals this to the processor by setting an interrupt flag Figure 2 The addresses of an image in memory 2 3 2 Pointers and modulos In a pointer register the blitter stores the address of the next data word to fetch from memory The 19 bit addresses are divided in two parts The upper 3 bits are stored in the PTH register and the lower 16 in the PTL register In most systems the memory will be divided in bytes although the processor uses word one word is two bytes addressing For this reason the least significant bit will always be zero and is in general not implemented
27. 000000000 000000000000000000 000000000000000000 000000000000000110 000000000000000111 000000000000000110 000010000000000000 010000000000000000 000000000000000000 s trigger y count put data wait logop finished wait until pt enable ddat and d address start write cycle wait until ready trigger y count put last word ready 70 REFERENCES 1 Commodore Business Machines Inc Amiga Hardware Reference Manual Addison Wesley 1986 2 William Cramer Gerry Kane 68000 Microprocessor Handbook Osborne McGraw Hill 1986 3 M E Sloan Computer Hardware and Organization Science Research Associates Inc 1983 4 J T H Verhoeven A Software Inter 5 unix reference manual 6 M R C M Berkelaar Technology Mapping from Boolean expressions to Standard Cells EUT Research Report 1987 7 L P P P van Ginneken Gridless Routing for Generalized Cell Assemblies EUT Research Report 8 Lodder van Stiphout J TJ van Eijndhoven Eindhoven 5 EditoR Reference Manual EUT Research Report 9 van der Steen Interactive Event driven Simulation Master thesis TUE 10 P Dewilde The Integrated Circuit Design Book Delft University Press 1986
28. 5524 EINDHOVEN UNIVERSITY TECHNOLOGY DEPARTMENT OF ELECTRICAL ENGINEERING DESIGN AUTOMATION GROUP THE BLITTER PROJECT A TEST CASE WJ M Philipsen Master thesis reporting on graduation work performed from 01 12 87 to 24 08 88 by order of prof dr ing J A G Jess and supervised by G L J M Janssen The Eindhoven University of Technology is not responsible for the contents of training and thesis reports This report present test case for the design tools present at the Design Automation Group We designed blitter graphic processor with these tools and evaluated the use and the results obtained with them Blitter stands for Bit BLock Image TransfERrer It can move large blocks of bitplane image data from one location in memory to an other We give a description of the blitter and a description of the design process The blitter is not yet finished but most parts are ready In the second part there is a description of each tool and a report of the problems we encountered designing the blitter It appeared that parts of the blitter were hard examples We discovered some bugs in the tools But most of the problems have been solved l Htrod clion 4 4 4 o 4 09 0 26 A 9 9 2 The Blitter CREER ou UR S Yen a A 2 1 A short description of the bit blitter UEM eh der log 24 The design palin ex
29. C bit is high it has to subtract Thus the adder can be in 4 different states Table 1 gives the function for each state Because overflows of the adder can only occur in the case of errors we can can neglect their effects Then subtracting is the same as adding the 2 complement The 2 complement of a value is equal to the inverted value plus one This gives to the 2 complement functions for the adder where mod is the bitwise inverted of mod 27 The third function reduces to pt mod We can now implement the adder using full adders The carry in bit for the first adder can be used to add one One input channel for the adder is always the pointer We get the input for the other and the state of the carry in bit of table 1 memorei memtei Prior EM pt mod 41 1 mod TABLE 1 Adder states and functions In we found this circuit for a full adder rewritten the logic syntax l 5 a b ab count bci ci b Figure 21 boolean description of a full adder Using this description we get the boolean specification for our adder by making a chain of full adders and adding the special features we wanted In the first line the carry in for the first full adder is defined The intermediate represents the function stated if table 1 For the upper 3 bits the b value is always zero becaus
30. H DESC bltcon SHIFT bltBold bltBdat SH bltcont BIT DESC bltCold fco put data 12 if WIDTH bltsize gt 1 get bltAdat bitAdat 8 bltAlwm bltDdat logop SHIFT bltAold bitAdat SH bltconO BIT DESC bltconi SHIFT bitBold bitBdat SH bltcon BIT DESC bltCoid fco put data alse bltAdat bltAdat amp bltAlwm bitDdat logop SHIFT bltAdat 0 SH bltconO BIT DESC SHIFT bltBdat 0 SH BIT DESC bltcon bltCdat fco put data if BIT DESC bltcon bltApt bltAmod bltBpt bliBmod bltCpt bltCmod bitDpt 61 else bltApt bltAmod bItBpt blitBmod bltCpt bitCmod bltDpt bitDmod Figure 9 The blitting part 14 2 4 3 Logic operations This procedure calculates all minterms and uses them if the corresponding bit in the CONI register is one After that one of the two filling modes is applied if necessary Note that the words are scanned from right to left thus filling only makes sense if using descending addressing WORD logop Adata Bdata Cdata fco WORD Adata Cdata WORD ddat int ddat BIT 7 Adata amp Bdata amp BIT 6 bltcon 0 Adata 4 Bdata amp 5 bltcon0 Adata amp
31. RD typedef unsigned char UBYTE typedef unsigned long ADDRESS defining the width and the hight of the screen define SCR 4 count define SCR 20 define MEM SIZE 5 W SCR typedef struct PORT Short fildes short size byte count char name PORT INITIALISING PORT PORT size name short size char name char calloc PORT newport if newport PORT calloc 1 sizeof PORT 59 newport size size 7 8 newport fildes 0 newport name name return newport printf Cannot allocate port size 9040 size exit 1 GET 1 unsigned int get PORT unsigned int data printf gt 15s port gt name amp data input is supposed to hexadecimal printf 9000 data read port gt fildes char amp data4 1 port gt size port size return data port data PORT int data printf lt 155 9000 gt data write port fildes char amp data 1 port gt size port gt size DISPLAY WORD mem SIZE
32. a lot of errors and warnings When working on the Apollo you even don t have enough time read them If a lay file is loaded the first time with euler it often crashes It will quit with the message segmentation violation or just hang up Kill it and start again For very large layout both from and euler will become very slowly For the floorplan of the logic unit from took 4 days and euler 30 minutes only for starting up 55 3 6 SLS Switched Level Simulator SLS simulate the logical behaviour and the timing of digital MOS circuits A user manual is enclosed in the ICD 9 SLS needs two files a description of the network and file with the simulation commands The network description can be extracted from a layout See the manual for the syntax of the circuit description and the command file The simulator uses the Delft database Here is step by step how to build one Do it manually the first time to know each program and write a shell script to do it for you the second time Because of all those sub directories it will be impossible to comprehend the intermediate results anyway mkpr lt project name gt It is not allowed to have a file or directory lt project name gt in the current directory Now you an amount of empty directories and sub directories You can chose any project name it isn t used elsewhere cd lt project name gt cldm lt ldm file gt makeboxl lt module name gt makevln lt
33. am addr port Then it reads the data bus Put and get do nothing but reading the value of the port addressed So there is no check if the data available at the data bus is good or not nor is there a signal to the processor to validate the address This means that there has to be an exact timing schedule for reading and writing Information concerning the speed of the memory has To be available when designing the timing for the blitter It is possible to use the dma request line and data bus request line for the validation In this case the only time that the data is valid at the data bus should be defined Then getword would become 16 reading from memory with validation of the data WORD getword addr ADDRESS addr put data bus req 1 request for cycle while get dma 0 cycle available put ram write 0 select read put reg addr port REG ADDR addr write address put ram addr port RAM ADDR addr put data bus req 0 addr valid while get req 1 data valid return get data bus read data Figure 12 Reading with validation 2 4 4 3 Writing to memory M There is only small difference in the signals ram write becomes 1 and the data is put on the data bus instead of read from it Timing is the same with the same remarks Also for writing it is possible to use the existing request lines for validation writing
34. an error It is very dangerous to copy or rename modules with UNIX commands Escher has the tendency to crash sometimes for unknown reasons especially on the HP system Due to many checks if the circuit is still legal escher will become very slow for large circuits It is not yet possible to give a net a user specified name For example in combination with the router the supply nets have to have very specific names 3 4 2 The escher simulator After escher was finished the behaviour evaluator has been added It is also menu driven and all menus are clear Under Escher the user has the possibility to add a behaviour description to each template The circuit can now be simulated These behaviour descriptions have a lisp like syntax In v d Steen P there is a syntax description The command list is not complete any more Several commands have been changed of added since then The syntax of the behaviour description are not checked thorough So if there are syntax errors in your descriptions escher crashes If Escher does complain about an error it does not say where it is Because of this bad error handling it is difficult to get acquainted with the syntax User interrupt handling has been improved recently Formerly it was impossible the interrupt the simulator when there was a infinite loop in one of the behaviour descriptions This will not cause no problems any more The simulation can be interrupted by pushing any key It is
35. communication with the outside has been described poor in the behaviour description That is why this part a completely different form the Escher behaviours For the communication in the set up phase loading the blitter registers we now use the protocol described in the C document in section 2 4 4 Figure 17 18 and 19 show the state machine resulting from this approach The parts to get and put data have been put in separate figures because the total figure would have become to big Figure 18 Get data state machine 25 Figure 19 put data state machine The way the blitter reads and writes to memory during the blit is the same as the 68000 processor This will make it easier to find a suitable DMA manager for the system If a particular DMA manager is to be used the blitter can always be changed The communication protocols are completely enclosed in the main controller and can be changed by changing its ESKISS description To simplify adjusting the controller not everything has been squeezed out of the controller It will possible to make the controller more compact but this will be bad for the readability of the description The controller has not been tested yet due to time limitations Testing may show the need for wait states If modules connected to the controller have very long delay times it may be necessary to stop the controller for some clock cycles to allow the module to finish its operations For exam
36. e last word timer lwt is false the registers are transferred to the out lines when not the the last word mask lwm is put on it first 2 5 5 Logop In lines 28 through 62 the value of each bit is computed from the three sources and the logfun input lines The results are stored in reg The values stored in reg are transferred direct or after further processing depending on if one of the fill enable lines is high For efe the carry computed by taking the exclusive or of the bit and the old carry taken as output For inclusive fill the result of an or operation on the carry and bit When filling the last carry is transferred to fco It s the users responsibility that only one fill enable is high 2 5 6 Shift The shift template gets two words as input old and new and the shift value sh These two words are put into a bit vector that is twice as long as a word with the old word left E g for a 4 bit word 10 lt the words 10 lt the bit vector When the addressing is ascending thus desc 0 the output has to be bit 7 sh through 4 sh This is done by setting offset to 4 sh en the using bits offset through offset 3 But when addressing is descending the words should be put the other way around E g new 0 the words 0 the bit vector the other way around We now have to take bits 3 sh through sh This means bits sh through 0 from new and through sh from old That are bits sh through 0 and 7 throug
37. e of those cells Default type is the aoi cell with a size of 3 3 Log mapper also computes the inputs and outputs of the circuit If no inputvars or outputvars are specified they will be listed after the entries inputvars and outputvars If they are already specified log mapper will give a warning if there are differences between the calculated lists and the specified lists The list specified by the user will be put in the outputfile These entrys are not standard logic syntax If the user specifies for one input both the not inverted and the inverted signal then those signals will be used and there will not be made an inverter for that signal Also for the outputs if the user specifies also the inverse of a variable then log mapper will also generate this inverse Figure 38 is the output for the example of log decom 45 gate type AOI inputvarsbceg outputvars Fi F2 functions subi0 sub9 sub8 d 5007 sub b g subi0 a ge 5006 d c 5065 10 5464 5168 b 4 6 int10 sub3 7 d 11110 g f 5062 d int10 subt 9 f int10 b b F2 sub7 f sub4 g sub5 sube f F1 6 3 g 6061 sub2 f ec e4 5 4 bee bc 9 09 c b b
38. e the modulos are only 16 bit Thus we can suffice with a simplified version of a full adder 28 ci desc sub sub desc one 0 0 a0 xO xO x0 ci x0 ci ci ad 0 X1 sub one 61 sub one desc 51 al cO al x1 cO al x1 cO al cO al cO cO 1 al X15 615 sub b15 sub one one desc 15 15 x15 c14 15 x15 c14 a15 x15 c14 a15 x15 c14 615 15 c14 x15 c14 15 14 15 x15 x16 one desc 16 816 x16 15 16 x16 15 a16 x16 c15 a16 x16 15 616 16 c15 4 x16 15 a16 15 a16 x16 x17 one desc 17 817 x17 c16 a17 x17 c16 17 x17 c16 a17 x17 c16 617 817 c16 x17 17 a17 x17 x18 one desc 18 a18 x18 c17 a18 x18 c17 a18 x18 c17 a18 x18 c17 Figure 22 Boolean description for the adder 2 6 2 2 Registers The pointers are 19 bit wide The least significant 16 bit are stored in a 16 bit register and the others in a 3 bit register Their input is connected to the internal register bus In the set up phase the low and the high part can be controlled separately The data bus will be connected to the register bus and the controller can load the registers with the value During the blit the address g
39. enerator controller can load the pointer with a newly calculated address We used 2 phase non overlapping clock flip flops for the registers The registers were made by writing a gate description There is a separate tool that generates a layout description for registers But these static registers are easier in the simulations For the dynamic registers a certain clock speed is needed and they don t work without their gate capacities So SLS simulations without taking the delays in account would be much more difficult These registers don t provided a scan path like those generated by the register generator do This scan path should be implemented in a real design 29 q0 7 40 0 90 7 40 0 940 cl 0 d0 cl 90 90 Figure 23 Gate description for one d flip flop 2 6 2 3 The multiplexers The boolean description for the multiplexers has been made and layout was generated for them In figure 24 there is a listing of the boolean description of the smal multiplexer 2 multiplexer 4 bit wide version 1 010 aen 50 aen outi al aen 51 aen out2 aen 52 out3 a3 aen Figure 24 Boolean description for 2 channel 4 bit multiplexer Figure 25 shows the pluri cell layout for this multiplexer EK Figure 25 Layout for a small multiplexer 2 6 2 4 The controller The contr
40. h 4 sh from the old bit vector That is the same as 8 sh mod 8 through 4458 mod 8 In the behaviour description this means setting the offset to 4 sh and using bit it offset mod 8 The modulo 8 has no influence when addressing the other way When using an other word length as 4 modulo 2 width should be used instead of the modulo 8 20 2 5 7 Display 2 5 7 1 The behaviour of mem big The memory is divided in 8 rows of 4 words that are 4 bits wide R w is the read write control line It should be 0 for reading and 1 for writing This line is also used to trigger this block The control unit first set the right values for address and data when writing on the input lines and then writes on the w line Row0 through row7 are the rows Each row is a four words bus When reading the wanted value is put on the data line When writing the value of the data line is stored in the right word The right word is selected by a block of if else statements The behaviour of first and other pix In other pix 0 through in 2 are put to the output 3 is divided by 2 and put to the output after color is set to first bit of in 3 In first pix the pixel at the right edge of a word in 0 is passed to 1 and so on to have the right word in 3 in the next word It would be much nicer to be able to use a part of the pixels of the screen directly but it is possible to work with this solution 21 2 6 Final design For f
41. ing and ascending addressing 2 3 5 Logic operations Three sources are available to the blitter logic unit These sources are usually one bit plane from each of three separate graphics images While each of these sources is a rectangular region composed of many points the same logic function is performed to each point throughout the rectangular region The logic function performed on each point is chosen by the LF control byte in the BLTCONO register For each bit all possible minterms 8 are constructed Each bit in the LF control byte enables one minterm Table 1 shows them This gives 256 logic functions enable bits 7 6 5 4 3 2 1 0 minterms Figure 5 The minterms selected LF control As an example I will derive the value for LF for the cookie cut operator The formula for the function is D AB AC This is equal to D ABC ABC ABC ABC Thus bits 7 6 3 and 2 should be high in LF to select the cookie cut In an other method can be found to calculate the value for the logic function a more confusing method 2 3 6 Masking blitter operations are done upon words To do operations on windows with boundarys within a word the masking facility is available Two masks can be defined One the FWM First Word Mask will be laid on the first word of each line If a mask is laid on a word all bits of the word whose corresponding bit in the data word is zero
42. module name gt extract L lt module name gt Use the L option to get a SLS network description The lt module name gt has to be the same as you used with macplace Afterwards the file lt module name gt sls will contain the description If you want to change the description do it in this file sls mkdb module name gt sls Sls exp module name When sls exp responds circuit test mc item NNN integer expected you probably have a transistor with width or length 10 as NNN th item For some curious reason this is not allowed change it into 9 or 11 and try it again After writing the command file you are ready to start the simulation with Sls module name command file Sls produces two files The file module name gt out with the results in a readable format and module name res which contains the result in a format suitable for further processing with for example slsmenu or Ipsig For examples I have done up till now with a few hundred transistors the runtime 56 for the creation of the database is about 20 minutes and for the simulation itself about 20 seconds For each program there is a manual page In the output of the extractor the vss and vdd were interchanged depletion transistors were connected to vss Check this in the file module name sls I also tried the postprocessing tools and slsmenu Slsmenu is easy to use and all menus are clear Figure 28 is an exam
43. modules controllers and others For the controller we made state machine descriptions using the behaviour descriptions from ESCHER simulation With ESKISS the controllers have been converted into modules of the second kind ESKISS computes a state encoding for the state machine The output is a boolean specification of the controller For the other modules we manually made boolean descriptions These logic specifications were optimized with EUCLID The optimized logic specifications were prepared with the technology mapper for the pluri cell generator The output of the technology mapper is a gate file The cell generator generates layout for these cells and a netlist with the connections between the cells From the gatefile SLS description can be made with the tool log 515 SLS is an abbreviation of Switched Level Simulator a logic simulator These simulations proved to be useful design errors could be found in a very early stage The cells obtained with the cell generator were placed and routed with MACPLACE and ROCOCO The result is a pluri cell layout The cells are placed in columns and between the columns there are the routing channels MACPLACE computes a placement for the cells and the connections were made by ROCOCO With the floorplanner we made a floorplan for these modules using the network we made with ESCHER The floorplan also was routed with ROCOCO From this final layout the circuit could be extracted again and
44. mprehend the discussion about the blitter it is necessary to know the design system in general A thorough description of each too can be found in part two of this report This chip has been designed for the nmos process available at EFFIC Eindhoven Fabrication Facility for Integrated Circuits using the design rules We started with a thorough description of the functionality of the blitter in plain English with the description of the blitter in the Commodore Amiga personal computer as an example This description in words was refined by writing a computer program with the same functionality as the blitter but that writes it output to a terminal The program was written in C We tried to make the C description as close as possible to the functionality of the blitter Non blitter functions as writing to the screen were placed in separate functions Using this formal description of the blitter it was divided into several high level blocks For drawing the pictures we used ESCHER Eindhoven SCHematic EntRy With the ESCHER simulator an extension of ESCHER it is possible to add to each module a description of its behaviour and to simulate the resulting design With these high level simulations one already encounters specific hardware problems as for example the communication between the different parts Stepwise refinement of the schematic with ESCHER dividing large modules into smaller ones finally leads to two basic kind of
45. nd all the common subexpressions in the given boolean expressions For each common subexpression a new intermediate variable intxxx is created It has to be called with log decom lt inputfile gt lt outputfile gt lt configurationfile gt When no output file is specified the output is written to the file decom out The default configuration file is decom config If this file isn t present it uses a default set of parameters In general these values are good The default values are listed int the manual page The expressions must be given as a sum of products The expressions must be represented by a minimum prime irredundant cover This can be achieved by the program log sim min kernel size 2 amount 2 min cube size 2 min cube amount 2 max kemel subst 5 max kernels 100 maxdelaytime 100 Figure 35 An example of the file decom config Finally a small example Fi ac g ef a b eg a d eg be fgsae fgscde fg F2 ac bdfg ab d fg a c b e f a b d ef acbef acfg abfg efg Figure 36 Input example for log decom And the results 43 a b schedtime 0 delay 6 d bce schedtime 0 delay 4 x69 schedtime 6 delay 4 Fi int10 f g inti0 g ef ea d cdf ge schedtime 10 delay 5 F2 f 4 1 110 f 1 110 f 10 abd g 4
46. nished f wt b pt 000000000000000000 wait until pt 1 f rd b 000000000000001000 start read cycle f rd b 000000000000000000 wait unti read f wt c pt 000000000000000010 save bdat and go get C new wrd 000000000000000010 4 save bdat and goto new wrd nal that nished wt c pt 000000000000000000 wait until pt 1 f rd c 000000000000001000 start read cycle wait until data available 0 f rd c e 1 f rd c get dala 1 01 new wrd 001 new wrd 000 new wrd f rd c new wrd wt a pt wt b pt wt c pt calc pt pta ptb ptc ptd signal that the last calculation is finished wt a pt wt a pt wait until data available wt pt rd a And if available ioad a data 5 0 rd a MM 1 1 rd a M 01 1 rd a 00 1 rd a for the B channel rd a b pt wt c pt calc 71 000000000000000000 000000000000000001 000000000000000000 000000000000000000 000000000000000000 000000000000000000 000000000000000000 000000000000001000 000000000000000000 000000000000000100 000000000000000100 000000000000000100 pt pta ptb ptc ptd signal that the last calc is finished wt b pt wt b pt wait until data available 0 rd b M 0 1 rd b 1 1 rd b wt b rd b rd b calc wt c pt pt pta ptbeptceptd signal that the last calculation is finished wt c pt wt c pt wait until data available
47. oller has to wait until it gets a signal from the main controller that the next address has to be calculated and the one now present in the selected pointer has to be put on the address bus If the 30 calculations are finished it signals this to the main processor by putting a line high The input for ESKISS is to be found in fig 26 trstate 0 irstate 1 E E E Figure 26 State machine for the address generator controller 31 State table for the address generation controller INPUTS usea useb usec used trsta OUTPUTS enadr trpta irptb trptc trptd aen ben cen den HN HON ABCDtr eABCDabcd stay in start until triggered data ready 1 start 000001000 00 start start 000001000 10 start AO 000001000 calculate addr only if needed enable b channel registers is necessary 0 0 0 0 000000100 1 0 0 1 100001000 delay to allow adder to finish calc not yet implemented update pointer register and signal main controller that address is valid M 0 A1 010001000 wait for next trigger signal from main controller 00 2 2 010001000 the pt signal stays high 10 BO 000000100 the same cycle for B channel 0 0 BO 000000010 1 0 BO B1 100000100 M 0 B2 001000100 00 B B2 001000100 10 B2 000000010 the same cycle for C channel
48. omment in the behaviour description The difference between byte and byte desc is the last also use descending addressing When using this possibility the shift desc and load desc should be used 2 52 2 The behaviour of load big This template just loads the control unit with new blitter operations and starts it with setting the ready line to 0 The blitter should not be started at simtime is because of the initialization in the control unit at that time The user should use this block to edit the blitter operations 2 5 3 Registers 2 5 3 1 The behaviour of delay The delay templates are used to offer the shift templates both the old and the new data word of the A or B source The contents of reg new is transferred to old and new is loaded within Then the reg old is transferred to the output 2 5 3 2 The behaviour of dhold This is a special register that transfers the output of the logic unit to the data bus It converts the 4 bit input bus into an output integer 19 2 5 3 3 The behaviour of big hold The input value is stored in reg Then the right bit is delayed to the corresponding output line and reg is shifted one bit right by dividing it by 2 This is done for every output line 2 5 4 The behaviour of mask If the first word timer fwt is false the registers are loaded with the input values Otherwise the first word mask is put on the input lines first If th
49. on1 BIT EFE bltcon1 for 150 j 16 j fco fco BIT j ddat if BIT EFE bltconl if fco 1 ddat ddat MASK j else ddat ddat amp MASK j if BIT IFE bltconl if fco BTT ddat ddat ddat MASK j else ddat ddat amp MASK j return ddat READING MEMORY WORD getword addr ADDRESS reading from memory is done in the array mem put data bus req 1 while get req 0 write 0 reg addr port ADDR addr Pr ram addr port ADDR addr return get data bus retum addr 1 data bitAold bltBold bltBdat bltCold bltCdat if BIT USEA bltconO bltAdat getword bltApt if BIT USEB bitBdat getword bltBpt if BIT USEC bltCdat getword bltCpt if BIT DESC bltconl bltApt bltBpt bltCpt else bltApt bltBpt bltCpt WRITING MEMORY putword addr data ADDRESS addr WORD data writing inmemory is done in the array mem data bus req 1 while req 0 rh put ram write 1 addr
50. only possible to do simulations on one level for all modules in one scheme there has to be a description This is awkward because in most cases the user will want to have the possibility to define the behaviour of a module on a lower level also Using Escher we came to the following list of things that could be improved Simulations can only be done on one level There should be a syntax check of the behaviour files e It should be possible to define functions 53 Global variables and constants should be added e The error messages you get now do not say in which template the error is At the time of writing two new versions of Escher were nearly ready Most of the problems are likely to have been solved in the new ones 54 3 5 EULER The Layout Editor Euler accepts only lt filename gt lay files The conversion of Idm file can be done with from 1dm from ldm filename without extension For the nmos process respond to both questions 1 It will create lt filename gt lay file that can be viewed at and changed with euler It be converted back to an ldm file with to 1dm to ldm filename without extension Euler has problems with the names for modules generated automatically Names with control characters or longer than 6 characters aren t allowed by euler Euler allows no underscores or names that start with capital letter It will try to find other legal names While doing this it sends
51. oted each tool a section 2 Blitter In this chapter we discuss the blitter After a short description of a blitter and a bird s eye view of the tools used for the design there is a description of the design process of the blitter 2 1 A short description of the bit blitter Blitter is an abbreviation for block image transferrer It is a graphics processor whose main application is movement of large blocks of bitplane data It can perform such operations after a set up of its registers considerably faster than an ordinary processor It includes features to facilitate copying and processing of rectangular regions of memory Typically these regions are areas within graphics images The process of performing a blitter operation is also called a blit The blitter uses up to four DMA Direct Memory Access channels Of the four DMA channels three are dedicated to retrieving data from memory to the blitter These are known as source source B and source C The one destination DMA channel is designated source D It is not always necessary to use all the channels Each channel may independently be enabled All three sources are fetched from memory in a pipelined fashion and held in registers for logic combination before being send to destination Figure 1 shows the DMA system The DMA controller distributes the memory cycles between the blitter and the processor If the blitter uses the memory while the processor works up it is last instr
52. output file There have been many problems with this rococo The version installed is still an old Pascal implementation of the program A C version of the program is ready but not yet installed When using this new implementation we encountered many bugs But is seems that most of them have been found and removed 52 3 4 ESCHER Schematic Editor and Behaviour Evaluator 3 4 1 Introduction to escher Escher is a schematic entry program The network drawn will be saved in the standard database format and can be used by other programs It is completely menu driven and all menus are obvious and explained in 81 For each module there is a directory the escher library Two environment variables control the name and location of the escher library There are several versions of escher The main difference between them is the way they store their graphics data The version used for the blitter design saves its graphics in a binary file called escher data When the circuit was correct at the time of saving it also saved the network data files The network will be stored in three files The file connection contains the nets in the file interface there is a list of the terminals of the module And the file call has a list of the instances of modules in this module If the file escher data becomes corrupt it occurred a few times with our design the circuit is lost Saving modules with an other name can cause such
53. ox This has been fixed by putting the terminal at the bounding box and adding a piece of metal from the old position to the new position Also an other another way to determine to which side terminal belongs has been added to handle 5611 the problems that occur if terminal lies exactly in the corner There are still troubles with the supply pin placement Some times the terminal will not be situated at the box side and the router will add a description for a piece of metal with a negative size The main problem is the piece of metal because this not according to the Idm syntax and it causes other programs trouble Also the the layout generated by rococo is much to high At the top of a module there is a large gap filled only with lines to the terminals connected to the upper side the possibility that this will happen is very small but if it does the only cure is to change the aspect ratio in the interface file In the ldm syntax nested modules are not allowed modules names are known globally This can cause problems if pluri cell modules are enclosed in floorplan If a name for a module occurs more then once this will be fatal for the router These names can be changed and rococo started again but there is an other solution There is a tool that can make a module flat It deletes all hierarchy It is called flat and has to be called with usr local bin flat usr local lib nmos tech lt lt input file gt gt lt
54. ple logop with a fill operation is in use will take a lot of time The complete ESKISS input file is to be found in appendix B 2 6 2 Address generator Each channel has its own pointer and modulo During the blit we always have to add 1 in the ascending mode and subtract 1 in descending mode At the end of a line we have an additional increase or decrease of the modulo We wanted to use only one ALU to calculate the addresses We also wanted the addresses to 26 calculated while the rest of the blitter was reading the data from memory or processing it Therefore this module has it own controller It enabled the right registers for calculations and stores the new calculated values ptaltr ptahtr ptbltr ptbhtr ptcltr ptchtr ptdltr ptdhtr H 1 i pus d tbus baodtr caodtr daodtr Figure 20 address generator The modulos can be stored in a 16 bit register The data input is connected to the data bus The trigger is available for the main controller With this line it can load the modulo registers in the set up phase 2 6 2 1 The Adder The adder takes care of the calculation of the address pointers It has to add one to the address to get the next address within a line or the contents of the modulo register at the and of a line We will use the last word timer line to indicate the end of a line Depending on the ascending or descending mode it has to subtract or add If the DES
55. ple of the output of Ipsig 57 3 7 Delft Advanced Layout Interface Before DALI can be used to view or edit an ldm file the layout has to be converted to a Delft Database This involves the steps executing the programs mkpr cldm makeboxl and makevin In the section about SLS there is a description of these steps So if you want to look at a piece of layout for which a SLS simulation has to be made anyway this doesn t involve extra work when not this means a lot of extra work For small layouts EULER is almost always faster and easier For large pluri cell modules it depends if the module is flat or not If it is flat it doesn t make much difference If not the performance is poor compared to EULER due to the enormous amount of directories in the database For big floorplans many large modules DALI beats EULER In this case both take their time to show the layout on the lowest level but you can t see anything in it anyway DALI has in contrary to EULER the possibility to show also a limited number of modules on a lower level With DALI you can also zoom in on a small part of the floorplan very quickly EULER not In general the menu s are clear but it is strange the the item to leave the editor is not located at the top level It is located in a sub menu called dm menu 58 A The C source include lt stdio h gt define gt gt 1 amp 1 typedef unsigned shon WO
56. ption helps See the results of table 3 Sometimes the layout with this option will become smaller Because it adds extra width it can also give a larger layout If there is no place for a pin in the specified interval the router will respond with something like too much south terminals If Macplace responds with the error message interface pin not found in the netlist it is also possible that the module name in the interface file is not the same as the module name used in the netlist for the interface pins The placer takes quite a lot of time To place an example with about 100 transistors it took about half an hour 49 3 3 2 The floor planner The floorplanner computes a plan for the floor It chooses a shape for the modules to be placed in the floorplan and a placement of the modules Then the modules with the wanted shape have to be generated and the floorplan can be routed with rococo Due to time limitations the floorplanner has not been tested thorough in this project We didn t use the possibility to let the floorplanner choose from different shapes for the modules This resulted in a non optimal layout Using all possibilities of the floorplanner will probably give a better layout The netlist has been generated from the escher connection file of the corresponding scheme For this conversion a emacs lisp function has been written This also changes the names of the supply nets into their proper names In the
57. r data UBYTE addr WORD data Switch addr case BLTCONO bltconO data break case BLTCONI data break case BLTSIZE bltsize data break case BLTAFWM bltAfwm data break case BLTALWM bltAlwm data break case BLTAPTL PUTLOW bltApt data break case BLTAPTH PUTHIGH bltApt data break case BLTBPTL PUTLOW bitBpt data break case BLTBPTH PUTHIGH bliBpt data break case BLTCPTL PUTLOW bltCpt data break case BLTCPTH PUTHIGH bltCpt data break case BLTDPTL PUTLOW bltDpt data break case BLTDPTH PUTHIGH bliDpt data break case BLTAMOD bltAmod data gt gt 1 break case BLTBMOD bltBmod data gt gt 1 break case BLTCMOD bltCmod data gt gt 1 break case BLTDMOD bltDmod data gt gt 1 break case BLTADAT bltAdat data break case BLTBDAT bltBdat data break case BLTCDAT bltCdat data break case BLTDDAT bltDdat data break WORD logop int i j fco for i HEIGHT bltsize 1 gt 0 1 bltAdat 0 reset registers at the 0 new line bliCdat 0 fco BIT FCI 1 reset the fill carry bit get data bltAdat bltAdat amp bltAfwm for WIDTH bltsize 2 j gt 0 j get data bltDdat logop SHIFT bltAold bltAdat 63 SH BIT DESC bltcon SHIFT bltBold bltBdat SH bltcon1
58. rasp around the modules see figure 40 To be able to guarantee successful routing of the for general floorplans this means that every module has to have two terminals at opposite sides for each supply net as in the figure For placements made with macplace this is not necessary The modules generated by log celgen have only single supply pins but the placement by macplace guarantees reachability When routing a floorplan with modules made with macplace and rococo rococo can provide this special supply pin placement when making the modules To do this there have to be two pins in the interface file for each supply net The names of these pins may only differ in the last character and that character has to be a letter e g vssA and vssB These pins have to be connected to the suply nets in entering for each an entry in the netlist Rococo should now provided a proper placement of the pins Figure 41 Routing example for a supply net It took a lot of time to get this working properly The main problem was that formerly the supply pins were not always placed on the side of a box by the router because this was not always necessary and it saves area But the router itself has to determine to witch side the terminal belongs to be able to determine if it is possible to reach the terminal or not In the old version the terminal belonged to the side closest to a terminal side This could be wrong if the supply terminal was not at the bounding b
59. ribed in section 2 6 2 2 136 datin 161 10 vss lvdd 6 vss vdd ycnt 0 xcnt 0 Figure 32 The size controller The counters have not yet been implemented The counter will be triggered by the main controller during the blit and have to signal to the main controller whether the end of a line is reached or not This leads to the following features load facility one comparison or zero comparison or reset facility comparison 2 6 5 The register address decoder The purpose of the address decoder is simple It selects the right register during the set up phase The bit needed from the address bus and the selected register will enabled The minterms of the combinations of the input bits have been used directly as a boolean description and a pluri cell layout has been generated for it 37 We have thought about giving the register other addresses It might be example useful two specific bit are always the code for the A B C or D channel This appeared not to be necessary and we chose the keep the addresses compatible with the Amiga blitter 38 3 he ES design system In this chapter we will give a short description of each tool used to design the blitter In section 2 2 we already explained each tool briefly Now we will discuss for each tool in detail input output and the problems we encountered during the blitter design 39 espresso eskiss
60. rom the main controller ESKISS description save last data wo put wt p wt p en d wr d wr d tr y tr y other tr y put rd of this line wt pt 4 t wt pt d t en d wr d wr d tr y Id x 10 000000000000000000 000010000000000000 000000000000000000 000000000000000000 000000000000000000 000000000000000110 000000000000000111 000000000000000110 000010000000000000 010000000000000000 000000000000000000 get next data trigger y count put data wait logop finished wait until pt enable ddat and d address start write cycle wait until ready trigger y count put last word ready Figure 16 Behaviour to ESKISS translation example The controller has been implemented using ESKISS First an ESKISS description of the controller has been made ESKISS generated automatically a boolean description for the controller 23 size not loaded Figure 17 State machine for the main controller Because I had already introduced states in ESCHER behaviour of my controller it was easy to translate this behaviour into an ESKISS description Here are some lines of the behaviour description and their corresponding lines in the ESKISS description For example the command setq x 1 x will be implemented by setting the output pin tr x high and low again And the following if statement by jumping to 2 different states depending on the in the value on the input line zero x The
61. t to move the data to a higher address you use descending addressing Otherwise it is possible that the blitter writes to an address that is not yet read With the fill operation only descending addressing is available Also with shifting the direction of addressing is important because a certain direction of addressing implies a certain direction for shifting The addressing direction is controlled by the bit desc in the CONI register 2 3 4 Shifting In order to be able to shift an image any number of bits and not just multiples of 16 there is a separate shift facility to shift words across word boundaries The shifter has the two last read words for one channel as input These two words are put in one 32 bit wide bit vector For ascending addressing the oldest word is put at the most significant places The output will be bits 16 sh through 31 sh Sh is the number of bit to be shifted ASCENDING ADDRESSING old new 1511403121110 9 8 7 6 5 4 3 2 1 0 output DESCENDING ADDRESSING old new js 1514 131211110 9 8 7 6 5 4 3 2 110 output Figure 4 example of shifting When descending addressing is used the words are placed the other way around in the vector In this way we will always have the word with the lowest address at the most significant place In this case the output is bits sh through 15 sh Figure 4 shows 4 bit shifting operation for both descend
62. tdat load reg load reg get the first data words first first first first Se m 01 001 000 pt ptatptb ptc ptd sig the last calculation is fi f wt pt f wt a pt get data first wait until data available And if available load a d Te 0 f rd a 1 1 f rd 01 1 f rd a 00 1 f rd a for the B channel pt ptasptbeptceptd sig f 0 f wt b pt Me 1 f wt b pt wait until data available T 0 f rd b 1 1 f rd b 0 1 f rd b pt pta ptb ptc ptd sig the last calculation is fi 0 f wt c pt f wt c pt yx xyabzaadddtrabc 10 000000001010000000 wait until chip addressed getdat 000000001111000000 go get data from the bus load reg 000000001010100000 load the registers 10 000000001010000000 wait for next data first 100000000000000000 start the blitter because sizereg has been loaded load y and load x f wt a pt 010000000000000000 go get f wt b pt 010000000000000000 go get B f wt c pt 010000000000000000 go get C new wrd 010000000000000000 do nothing nal that nished f wt a pt 000000000000000000 wait until pt 1 f rd a 000000000000001000 start read cycle ata f rd a 000000000000000000 wait until pt 1 f wt b pt 000000000000000100 4 save and go get B f wt c pt 000000000000000100 save adat and go get C new wrd 000000000000000100 4 save and goto end nal that the last calc is fi
63. tes layout descriptions in Idm for the cell and a netlist The format of the netlist is a simplified version of the standard network format for example used by Escher In the netlist written by log celgen a connection has the following format 47 net name instance name pin name It has to be called with log celgen filename The input is read from standard input The layout will be in the file filename ldm and the netlist in filename nlt The output of log euler will usually be piped into log celgen there are no other programs that can deal with output of log euler and the user can t use it because of the control characters Figure 39 shows the lay out of a cell generated by celgen Figure 39 Lay out for a cell generated by log celgen The layout description generated by log celgen contains errors In some of the box declarations the coordinates are swapped the first is larger then the second figure This is not allowed in the Idm syntax Such an error has already been deleted once These errors were re introduced when a new version of the program was installed end of April Already in March I discovered the same kind of error in the old version of log celgen 47 3 3 Placement and routing After log celgen we have layout for the modules But these module are not yet placed and routed This can be done with macplace and rococo When the layout for a module is ready if can be
64. tfile for ESKISS The numbers after the mv key have the following meaning The number of input variables plus 3 The number of input variables The number of different states in the second collumn a don t care is not counted as a state The number of different states in the third collumn e number of output variables The 3th and 4th entry are preceded with a minus First the input has to be prepared with espresso using the kiss entry Then the program ESKISS can compute a state encoding for state machine The output of espresso and ESKISS put together and changed a These changes done with awk The resulting boolean description in espresso format has to be simplified again with espresso before it can be converted to the logic syntax with fsm conv All these programs are called by a script state enc that should do the whole procedure But this script doesn t work properly Instead of the awk it uses a program with a bug 41 3 2 EUCLID 3 2 1 LOG SIM The logic simplifier Log sim does a simplification and minimization of the input It handles an expression given as a sum of minterms The used syntax is the logic syntax The input is read from standard input The output are two files listing contains a listing of the input and error messages if there are any data sim contains the simplified output As an example of the results and the used syntax The input file
65. thout reloading them 12 2 4 2 The blitting part There are two loops The first is done for each line and the second for each word within a line At the start of each line the data registers and the fill carry bit are reset The first data words are read and masking is applied upon the A source The shifter has to read two words read from each channel before the first output word can be calculated The second for loop is limited to have always two words in the pipeline After the last word has been read there is one word left in the pipeline It is shifted with the other word put to zero The if statement is necessary to be able to handle windows that have a width of only one word Finally the pointers are adjusted to point to the next addresses If the bit DESC in the register CONI is high the modulos are added else they are subtracted The procedures get data and put data take care of the additional decrease or increase after each word blit WORD logop int i fco for i HEIGHT bltsize i 0 i the start of a new line reset registers bltAdat 0 bltBdat 0 bitCdat 0 reset the fill carry in bit fco BIT bitconi get the first data word of this line get data apply the mask on the and B channel bltAdat bltAdat 8 bltAfwm for j WIDTH bltsize 2 j 0 j get data bltDdat logop SHIFT bltAold bitAdat S
66. to memory putword addr data ADDRESS addr WORD data data bus req 1 request for cycle while get dma req 0 cycle available put ram write 1 select write put reg addr port REG ADDR addr write address put ram addr port RAM ADDR addr put data bus data write data Figure 13 Writing to memory d Wr 17 2 5 Escher simulation 2 5 1 The Escher scheme For a part of the C description an Escher simulation was made At the time the simulations were done it was not yet possible the use multiple levels Each instance in the current template had to have its own behaviour description Simulating the complete blitter would have led to very complicated behaviour descriptions Therefore we simulated only part of the blitter Loading of the registers was left out in this simulation The display replaces the memory All blitter operations are done upon a memory with start address 00 and that contains 32 words It represents a 8 lines high image with 4 4 bit words in a line The blitter consists of two shifters the masking hardware logop the logic operations block some registers and a control unit The next sections will give an explanation of the behaviour of the different blocks CONTROL UNIT Figure 14 Escher simulation scheme 18 2 5 2 The control unit 2 5 2 1 The behaviour of cntr Most of the registers have been incl
67. uction it doesn t hold up the processor The 68000 processor has been the example when processor dependent features had to be defined DMA controller Figure 1 The Direct Memory Access system summary of the blitter features and operations Data copying blitter can copy bit plane image data from one location to an other Multiple pointers and modulos Each channel has it is own pointer and modulo registers This allows the blitter to operate upon identical windows within larger images with different sizes e Ascending and descending addressing The blitter can address in two directions it can either start at the bottom or at the top of the window Logic Operations blitter can perform a logic operation upon the data of the three sources before transferring the result to the target Before a blit is started the blitter is set up to perform one of the logic operations on the three data sources when preparing the output Shifting The blitter can shift one or two of its data sources up to 15 bits before applying the logic operation This is necessary when you want to move images across word boundaries Masking The blitter can mask the leftmost and the rightmost data word from each horizontal line of a window rea filling The blitter can perform hardware assisted area fill between predrawn lines 2 2 The design path In this section we will give an overview of the design system To co
68. uded in the control unit and not been implemented as real registers to simplify the design During the first simulation at simtime is 0 the initializations in lines 53 through 63 are evaluated These are resets of control lines the state register is set to zero and the interrupt line ready is set to one The ready line has two functions First it is connected to the interrupt block it signals when the blitter operation is finished Second it is used to start the blitter again By putting a one on this line during the initialization the blitter is prevented from starting a random blitter operation When all control inputs have their values the blitter can be started by setting the ready line to 0 Then the block of line 63 is evaluated The control inputs are passed to their corresponding output lines That are ife efe logfun sha shb lwm and fwm This block will be evaluated each new blitter operation At the end of the block the local wait is set to zero and trigger is triggered The local wait insures that only one block is evaluated each time the control unit is evaluated With the delay of the trigger we can evaluate the unit immediately or at a time in future again when it is ready for the next All statements are almost a one to one projection of the C document in the Lisp like code with a state added when a delay was necessary and at destinations of jump statements Whenever possible we put the corresponding C statements as c
69. urther design we will not use the same scheme as we used for the Escher simulations In this case the blitter has been split up in 9 blocks The address generator calculates at witch address the next data word is located for each channel The logic unit takes care of preparing the data It includes the masking hardware shifting and the logic operations Size control keeps track of the number of lines and words and signal at the end of a line and at the end of the window In the set up phase the decoder choses the destination for the data And finally four of the blitter registers and the main controller for all other jobs em i Figure 15 The blitter circuit 2 6 1 The main controller 22 The main controller has been constructed using the behaviour description of the controller from the Escher simulation This behaviour description proved to be very useful for constructing the controller From the behaviour of byte cntr setq wait 1 if and state 4 progn setq x x 1 i delay 0 trigger state 2 f x size 1 setq state 2 setq state 5 setq wait 1 if and state 5 wait 0 delay 0 data 0 1 wait 0 for sfor x lt SIZE delay 1 en ahold 1 2 delay 1 en bhold 1 2 setq return 6 setq state putdata delay 2 trigger state 2 setq wait 1 next eval this cycle next eval after 2 cycles The lines f
70. will only change in the set up phase so this won t cause many problems 2 6 3 3 logop The logop consist as the masking unit of 16 equal cells Figure 31 shows one such cell is the result of the boolean function chosen with 50 57 With this value the filling is performed if necessary The output variable fcO has to be connected to the fci of the next cell x0 57 a0 cO 56 a0 0 55 ad cO 54 cO 53 a0 cO 52 0 cO 51 cO 50 fcO x0 fci dO efe fcO ife 0 ife fcO ife Figure 31 One cell for logop We made one file with the boolean description of the complete logop and generated layout for it The simulations showed what we already expected that the settle times for fill and no fill differ very much 2 6 4 The size controller The size controller takes care that the blitter stays in its window During the set up phase the register SIZE is loaded The upper 10 bits contain the number of lines and the others the number of words in one line The main controller can load the counters with its value When the controller now triggers the counter it will decrease the value in the counter The output lines Y ONE and ONE will become high if the value in the corresponding counter becomes one This line will also be used as last word timer The registers used here are the same as the registers desc
71. will be treated as is they were zero s during further processing The other mask LWM the Last Word Mask will be apllied on the last word Figure 6 gives an example input word 1110011110000111 mask 0000000111111111 result 00000001 10000111 Figure 6 An example of masking 2 3 7 Area filling The blitter can perform a hardware assisted area fill between predrawn lines It scans each word from right to left for bit that are one If it finds a one it inverts its fill state The output bit is always the fill state There are two filling modes Inclusive fill Exclusive fill If the input bit is one and the fill state changes from zero to one the output bit will be zero in the exclusive fill mode and in the inclusive fill mode In other cases the output will always be equal to the filling state The filling modes are enabled respectively with the bits IFE and EFE in the register CONI The user has to take care that only one of the modes is enabled The initial fil state at the beginning of each line is equal to the bit in CONI Within a line the fill state is passed as a kind of carry bit from one word to an other The filling is done after the logic operation has been applied upon the data Because words are scanned from right to left filling can only be used in the descending addressing mode input 1 ojo ojo ojojo o 1 ojo o o exclusive fill inclusive fill 1

THE BUTTER PROJECT, A TEST CASE.

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