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ERTEC 200 Enhanced Real-Time Ethernet Controller with 32

1. 252 ARM9 Control Register ARM9 CTRL 1 2 253 ARM9 Control Write Enable Register ARM9 254 ERTEC 200 TAG Identification Register ERTEC200 TAG 255 PHY1 2 Configuration Register PHY CONFIG 1 4 256 PHY1 2 Configuration Register PHY CONFIG 2 4 257 PHY1 2 Configuration Register PHY CONFIG 3 4 258 PHY1 2 Configuration Register PHY CONFIG 4 4 259 PHY1 2 Status Register PHY STATUS sss 260 UART Clock Section Register UART_CLK sees 261 Detailed Representation of Clock Unit 22 0400 0 264 Clock Supply of Ethernet 265 PEE Power up Phase ie dere ee aede ee Au ue did ae PA dE dede 267 JTAG Connector Pin 276 Preliminary User s Manual A17988EE1V1UMO0 13 14 Preliminary User s Manual 17988 1 10 00 Table 1 1 Table 1 2 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table 2 10 Table 2 11 Table 2 12 Table 2 13 Table 2 14 Table 2 15 Tab
2. 109 93 Page Size Settings cool cr RR Sosa nea dg 111 92 Page Offset Setting 112 9 3 Local Bus Unit Address Mapping 113 94 Page Control Setting o cirerer ente e 115 9 5 Host Accesses to ERTEC 200 116 9 6 Host Interrupt 0 119 9 7 Address Assignment of LBU 119 9 8 Detailed LBU Register 120 Chapter 10 ROM gt RE 123 10 1 Booting from External 124 10 2 22222 Sear eh ie a Pe eee eee 124 10 3 Booting via UART 2 22 eet eee een eee ke 444 Foran 0 124 10 4 Booting Via ene teehee edie ss 124 10 5 Memory 124 Chapter 11 General Purpose I O GPIO 125 11 1 Address Assignment of GPIO 127 11 2 Detailed GPIO Register 128 Chapter 12 Asynchronous Serial Interface UART
3. 22 Preliminary User s Manual 17988 1 10 00 Chapter 1 Introduction Table 1 1 Pin Configuration of ERTEC 200 2 5 ae Pin Name ee Pin Name GPIO3 P2 SPEED 100LED N P2 SPEED 10LED VDD Core GPIO1 P2 DUPLEX LED N GPIO15 WD WDOUTO N GND IO GPIO14 DBGACK VDD IO GPIO11 UART DSR N A6 GND Core A5 VDD Core P1TDxP GNDNete P1TDxN P1RDxN A8 P1RDxP 12 4 A11 CS PERO N A20 CONFIG3 VDD Core GND Core RDY_PER_N VDD Core OE_DRIVER_N GND Core VDD Core GND IO GP1023 SPI1_SCLKIN 28 GP1020 SPI1_SCLKOUT GPIO22 SPI1 SFRMIN DBGACK VDD Core PLL AGND GPIO19 SPI1_SSPTXD GPIO17 SPI1_SSPOE CLKP_B GND IO GPIOT P2 RX LED N P2 TX LED N P2 ACTIVE LED GND Core GPIO5 P2 LINK LED VDD Core GPIO2 P1 SPEED 100LED N P1 SPEED 10LED GND PECL VDD Core P1SDxN GPIOO P1 DUPLEX LED GNDNete VDDQ PECL VDD33ESD VDDQ PECL 14 10 13 9 A21 CONFIG4 A19 CONFIG2 GND IO VDD Core GND Core GND Core DGND2 DTR_N BOOTO DVDD1 GPIO31 DBGREQ P1SDxP GPIO29 GND IO GND Core PLL AVDD A15 BOOT1 Note Connect to GND to improve heat dissipation pins may as well be left open Preliminary User s Manual A17988EE1V1UM00 23 Number A23 CONFIG6 Table 1 1 Pin Name Chapter 1 Introduction Pin Configuration of ERTEC 200 3 5 Pin Number WE SDRAM N Pin Name
4. 163 Address Assignment of Timer 2 Registers 8 171 Fehmer Pin Funcions ni ces rte eet co ee o ee 174 Preliminary User s Manual A17988EE1V1UMO0 15 Table 14 4 Table 15 1 Table 16 1 Table 16 2 Table 16 3 Table 16 4 Table 16 5 Table 16 6 Table 16 7 Table 16 8 Table 16 9 Table 16 10 Table 16 11 Table 16 12 Table 16 13 Table 16 14 Table 17 1 Table 18 1 Table 19 1 Table 19 2 Table 21 1 Table 21 2 Table 21 3 16 Address Assignment of F Timer 175 Address Assignment of Watchdog Registers 2 179 PHY Interface Pin Functions 186 AB 5B GCode Table cent eh fce Ee E e E dU Hd ge 190 Assignment of LED Signals to 195 PHY Interrupt Events einrichten ee qe d decer iden 199 Diagnosis Interface 203 SMI Diagnosis Interface 4 22240 0 204 MDI Interface Sigrnals teet nares dag deg e une iae 204 Other PHY Related Signals esee enne nnne nennen enne 205 PHY internal Registers 22224 1 206 Initial Parameter Settings for 5 207 4 e cett cerdo sedet cv eher et
5. Receive clock port 1 LBU_BEO_N TX_CLK_P1 Transmit clock port 1 LBU_WR_N Note MII SMI diagnosis interface pins are alternatively used as local bus interface or trace pins in this table the I O type is listed for the MII SMI diagnosis function 36 Preliminary User s Manual 17988 1 10 00 2 Pin Functions Table 2 4 PHY Interface Pin Functions Pin Name Function Alternate Function Differential transmit data output Differential FX transmit data output Differential FX transmit data output Differential receive data input Differential receive data input Differential FX receive data input Differential FX receive data input Differential FX signal detect input Differential FX signal detect input External reference resistor 12 4 Note DVDD 4 1 Digital power supply 1 5 V DGND 4 1 Digital GND P 2 1 VSSATX 2 1 Analog port GND P 2 1 VDDARXTX Analog port RX TX power supply 1 5 V P 2 1 VSSARX Analog port GND VDDAPLL Analog central power supply 1 5 V VDDACB Analog central power supply 3 3 V VSSAPLLCB Analog central GND VDD33ESD Analog test power supply 3 3 V VSS33ESD Analog test GND Note The external resistor must have a maximum tolerance of 1 Preliminary User s Manual A17988EE1V1UMO00 37 GPIO 44 43 VoNote 2 Pin Functions Table 2 5 General Purpose I O Pin Functions
6. 169 Current Timer Value Register for Timer 0 170 Current Timer Value Register for Timer 1 170 Control Register for Timer 2 2 17 2 172 Current Timer Value Register for Timer 2 173 F Timer Block Diagram ee drei dace va doen 174 F Timer Value Register F COUNTER VAL 175 F Timer Reset Register F COUNTER RES 175 Watchdog Timer Block 177 Watchdog Timer Output Timing sss enne nennen 178 Watchdog Control Status Register CTRL STATUS 1 2 180 Reload Register Low for Watchdog 0 RELDO LOW 181 Reload Register High for Watchdog 0 RELDO _ 182 Reload Register Low for Watchdog 1 RELD1 LOW 182 Reload Register High for Watchdog 1 RELD1 HIGH 183 Counter Register for Watchdog 0 WDOGO 183 Counter Register for Watchdog 1 WDOG1 183 PHY Block Diagram e sedi ue dea 187 MLT 3 Encoding Example essen eee 191 Internal and Remote Loopback
7. 172 14 3 F Timer ee ge soda Ua UC oan E Ete Cn 174 14 3 1 Functional description of the 174 14 3 2 Address assignment of F Timer 175 14 3 3 Detailed F Timer register 175 Chapter 15 Watchdog 177 15 1 Watchdog Timer 177 15 2 Address Assignment of Watchdog 179 15 3 Detailed Watchdog Register 180 Chapter 16 Multiport Ethernet 185 16 1 Functional Description 187 16 1 1 10BASE T Operation 187 16 1 2 100BASE TX 189 16 1 3 100BASE FX 192 16 1 4 Gee ad Gent E Epp 193 8 Preliminary User s Manual 17988 1 10 00 16 1 5 Miscellaneous Function 195 16 2 PHY Related Interfaces 202 16 3 PHY R
8. 80 Preliminary User s Manual 17988 1 10 00 Chapter 7 DMA Coniroller 7 2 Detailed DMA Controller Register Description Figure 7 1 DMACO SRC ADDR REG DMA Source Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value START ADDRESS 8000 0000H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 START ADDRESS START START ADDRESS 31 0 31 0 ADDRESS R W Specifies the address of the first data to be transferred from the source Only addresses with 4 Byte alignment are permitted bits 1 0 are ignored Figure 7 2 DMACO DEST ADDR REG DMA Destination Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value DESTINATION ADDRESS 8000 0004H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DESTINATION ADDRESS DESTINATION ADDRESSY 31 0 DESTINATION ADDRESS R W Specifies the address to which the first data is to be transferred Only addresses with 4 Byte alignment are permitted bits 1 0 are ignored Preliminary User s Manual A17988EE1V1UMO0 81 Chapter 7 DMA Controller Figure 7 3 DMACO CONTR REG DMA Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value D DELAY EX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE COUNT Bit position Bit name Function Reserved D DELAY EXTENSION 2 0 D DELAY Extends the D DELAY delay between two write accesses to the DMA desti EXT
9. 137 12 1 Address Assignment of UART Registers 140 12 2 Detailed UART Register Description 141 12 3 GPIO Register Initialization for UART Usage 150 Chapter 13 Synchronous Serial Interface 151 13 1 Address Assignment of SPH 153 13 2 Detailed SPI1 Register Description 154 13 3 GPIO Register Initialization for 160 Chapter 14 ERTEC 200 161 141 Timer 0 and Timer 1 161 14 1 1 Operation mode of Timer 0 and Timer 1 162 1412 Timmerinterrupts i ss pea pea eka xu ERE S ERR RR geld 162 144 39 Timerprescalerz uice ER Riz Ge bc die bd SEE ERE MERE RH 162 141 44 Cascading of timers 162 14 1 5 Address assignment of Timer 0 1 registers 163 14 1 6 Detailed description of Timer 0 1 163 14 2 Timer 2 oru neveu eve eheu Mex e A 171 14 2 1 Address assignment of Timer 2 171 14 2 2 Detailed description of Timer 2 registers
10. 196 Phase Offset Indicator 4400 100 201 PHY Related 8 202 Basic Control Register 1 2 eene 208 Basic Control Register 2 2 209 Basic Status Register 1 3 042 1 0000 210 Basic Status Register 2 3 404 24 10 10 1100000 a nnn 211 Basic Status Register 3 3 200400000 212 PHY Identifier Register REG2OUIIN sess 214 PHY Identifier Register REGSOUIIN sse 214 Auto Negotiation Advertisement Register 1 3 215 Preliminary User s Manual 17988 1 10 00 Figure 16 10 Figure 16 10 Figure 16 11 Figure 16 11 Figure 16 12 Figure 16 12 Figure 16 13 Figure 16 14 Figure 16 15 Figure 16 16 Figure 16 16 Figure 16 16 Figure 16 17 Figure 16 17 Figure 16 18 Figure 16 19 Figure 16 19 Figure 16 20 Figure 16 21 Figure 16 21 Figure 16 22 Figure 16 23 Figure 16 24 Figure 16 25 Figure 16 26 Figure 17 1 Figure 17 2 Figure 17 3 Figure 17 4 Figure 17 5 Figure 17 6 Figure 17 7 Figure 17 8 Figure 17 9 Figure 17 10 Figure 17 11 Figure 17 12 Figure 17 13 Figure 17 14 Figure 17 15 F
11. 269 Chapter 20 Address Space and Timeout 0 271 20 1 AHB Bus Monitoring 271 20 2 Bus Monitoring 271 20 3 External Memory Interface Monitoring 272 Chapter 21 Test and 273 211 ETM9 Embedded Trace 273 212 ETMS Registers 1 i RR IS 274 21 3 Tracelnter ace looge IRIS 274 21 4 JTAG Interface ex eee ele 275 21 5 Debugging via 276 Preliminary User s Manual A17988EE1V1UMO0 9 10 Preliminary User s Manual 17988 1 10 00 Figure 1 1 Figure 1 2 Figure 3 1 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 Figure 8 10 Figure 8 11 Figure 8 12 Figure 8 13 Figure 8 14 Figure 8 15 Figure 8 16 Figure 8 17 Figure 8 18 Figure 8 19 Figure 8 20 Figure 8 21 Figure 8 22 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Fi
12. 65 Detailed EMIF Register 65 Asynchronous Access Timing 74 External Memory Connection 76 Hints for Setting the EMIF Registers 77 DMA Conlroller os assis ted ot REN E E ACE x e a 79 Address Assignment of DMA Controller Registers 80 Detailed DMA Controller Register 81 Interrupt Controller 9e er vede ERIS ERIS DE ie IIS 87 Prioritization 88 Trigger Modes i clo REI 89 Masking the Interrupt 89 Software Interrupts 89 Nested Interrupt Structure 89 EOI 90 IRQ Interrupts as FIQ Interrupt Sources 90 Interrupt Control Register 91 Detailed ICU Register 93 Preliminary User s Manual A17988EE1V1UMO0 7 Chapter 9 Local Bus Unit
13. 8 mee ERTEC 200 gt ARRO h control GPIO logic Status LEDs lt 9 registers gt E MII gt g 9 E 0 gt PHY1 e gt gt gt lt gt SMI 1 d gt ra gt 4 gt MAC2 PHY2 4 gt MDI2 MII lt gt IRT switch 21 control and communication paths into and out of the PHYs can be categorized four respectively five groups 1 Interface The media independent interface is the data communication interface between and PHY each PHY respectively each MAC has its own MIl interface The two MIl interfaces on ERTEC 200 are on chip interfaces however they can be externally monitored if ERTEC 200 is configured to MII diagno sis mode LBU interface pins are used for this purpose Table 16 5 lists the signals that belong to the MII diagnosis interface and the normal usage of the same pins for LBU signals 202 Preliminary User s Manual 17988 1 10 00 Pin NameNote Chapter 16 Multiport Ethernet PHY Table 16 5 Diagnosis Interface Signals Function Alternate FunctionNete TXD P2 3 0 Transmit data port 2 bits LBU D 9 6 RXD P23 Receive data port 2 bit 3 LBU A11 PIPESTA2 RXD P22 Receive data port 2 bit 2 LBU A10 TRACESYNC RXD 21 RXD P20 Receive data port
14. Preliminary User s Manual ERTEC 200 Enhanced Real Time Ethernet Controller 32 Bit RISC CPU Core Hardware py PD800261F1 523 HN2 Document No A17988EE1V 1UMOO Date Published August 2007 NEC Electronics Corporation 2007 Printed in Germany NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vi MAX and MIN due to noise etc the device malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vit MAX Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected Voo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when expos
15. 200 Timers 14 11 1 Operation mode of Timer 0 and Timer 1 Both timers are deactivated after a reset The timers are enabled by setting the Run xStop bit in the status control register of the respective timer The timer then counts downwards from its loaded 32 bit starting value When the timer value reaches 0 a timer interrupt is generated The interrupt can then be evaluated by the IRQ interrupt controller The interrupt generated by Timer 0 is connected to the IRQO input of the IRQ interrupt controller the interrupt from Timer 1 is connected to IRQ1 If the Reload Mode bit is set to Op the timer stops when 0 is reached if the Reload Mode bit is 1 the timer is reloaded with the 32 bit reload value and automatically restarted The timer can also be reloaded with the reload value during normal timer function count value 0 This happens by setting the LOAD bit in the status control register of the timer Normally the timer clock operates at 50 MHz which is generated by the internal PLL Each timer can also be operated with an 8 bit prescaler that can be used to increase the timer period accordingly 14 1 2 Timer interrupts The timer interrupt is active High starting from the point at which the timer value is counted down to 0 The timer interrupt is deactivated Low when the reload value is automatically reloaded or the LOAD bit is set by the user The interrupt is not reset if the loaded reload value is 0 If the timer
16. 130 Preliminary User s Manual A17988EE1V1UMO0 11 Figure 11 6 Figure 11 7 Figure 11 8 Figure 11 9 Figure 11 10 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 12 5 Figure 12 6 Figure 12 7 Figure 12 8 Figure 12 9 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 13 5 Figure 13 6 Figure 13 7 Figure 13 8 Figure 14 1 Figure 14 2 Figure 14 3 Figure 14 4 Figure 14 5 Figure 14 6 Figure 14 7 Figure 14 8 Figure 14 9 Figure 14 10 Figure 14 11 Figure 14 12 Figure 14 13 Figure 14 14 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 15 5 Figure 15 6 Figure 15 7 Figure 15 8 Figure 15 9 Figure 16 1 Figure 16 2 Figure 16 3 Figure 16 4 Figure 16 5 Figure 16 6 Figure 16 6 Figure 16 7 Figure 16 7 Figure 16 7 Figure 16 8 Figure 16 9 Figure 16 10 12 GPIO PORT MODE H Register 131 GPIO POESEL Registet a p eet dere tie 132 GPIO2 IOCTRL Register 40224224 0 nennen entente enn sin aiian 133 GPIO2 OUT Register menisini aa Lee aes oder dee To e e dde 133 GPIO2 IN Register eie tete page sed 134 UART Macro Block Diagram ssssseesseeeeneneneenen nne nennen nnne 138 UARTDR Data Register 0224 nennen nennen 141 UARTRSR UARTECR Registers sse nennen 142 UARTLCR H Register
17. 5000 0074H 5000 0078 PRIOREG1 PRIOREG2 0000 000FH 0000 000FH 5000 007 PRIOREG3 0000 000FH 5000 0080 PRIOREG4 0000 000FH 5000 0084 PRIOREG5 0000 000FH 5000 0088H PRIOREG6 0000 000FH 5000 008 5000 0090 PRIOREG7 PRIOREG8 0000 000FH 0000 000FH 5000 0094 PRIOREG9 0000 000FH 5000 0098H PRIOREG10 0000 000FH 5000 009 PRIOREG 1 1 0000 000FH 5000 00A0H PRIOREG12 0000 000FH 5000 00A4H 5000 00A8H PRIOREG13 PRIOREG14 0000 000FH 0000 000FH 5000 00ACH Note Reserved bits in all registers undefined when read always write the initial reset values to PRIOREG15 these bits 92 0000000FH Description IRQ priority registers for inputs IRQO to IRQ15 of the IRQ interrupt controller Preliminary User s Manual 17988 1 10 00 Chapter8 Interrupt Controller 8 9 Detailed ICU Register Description Figure 8 1 IRVEC IRQ Interrupt Vector Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Vector ID 5000 0000 FFFF FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Vector ID IRVEC Bit position Bit name Function Vector ID 27 0 Differentiates valid IRQ interrupt vectors from the default IRQ vector Vector ID Vector ID 27 0 IRQ interrupt vector identification 0000H Valid IRQ interrupt vector pending FFFFH Default
18. Preliminary User s Manual A17988EE1V1UMO0 113 9 Local Bus Unit LBU Figure 9 1 Example for LBU Address Line Connection 21 20 0 LBU_A 20 0 Host 21 LBU SEGO 200 A22 LBU_SEG1 In order to program an address mapping according to Table 9 4 the LBU registers must be set as shown in Table 9 5 these values are the initial values of the LBU registers after ERTEC 200 has been reset Table 9 5 LBU Register Initialization Example Register LBU_Pn_RG_L LBU_Pn_RG_H LBU_Pn_OF_L LBU_Pn_OF_H 114 Preliminary User s Manual 17988 1 10 00 Chapter 9 Local Bus Unit LBU 9 4 Page Control Setting The user can program the page control register to set the type of access to the relevant page Certain areas of ERTEC 200 must be accessed 32 bit wide in order to ensure data consistency For other areas an 8 bit or 16 bit data access is permitted or even required Table 9 6 lists the areas where 32 bit accesses are allowed respectively obligatory Table 9 6 32 bit Accesses in Various Address Ranges other access than 32 bit allowed ERTEC 200 address range 32 bit access required System control registers Timer 0 1 2 F counter Watchdog IRT register SDRAM Communication SRAM as User RAM Communication SRAM as Switch RAM Remaining APB I O UART SPI1 GPIOs A setting is made in the page control registers to indicate whe
19. ignore on read access Enable 4B5B Allows to bypass the 4B 5B encoder decoder 6 Enable R W Enable 4B 5B 4B 5B encoder decoder bypass selection 4B5B O 4B 5B encoder decoder is bypassed 01 48B encoder decoder is enabled initial value Reserved g PUAN Write 000 ignore on read access Speed Indication Indicates Speed and HD FD mode of the currently established link Speed Indication Current link speed indication 000 No link initial value 001 10BASE T half duplex 010 100BASE TX half duplex 101 10BASE T full duplex 110 100BASE TX full duplex Speed Indication others Reserved 234 Preliminary User s Manual 17988 1 10 00 Bit position Chapter 16 Multiport Ethernet PHY Figure 16 21 PHY Special Control Status Register 2 2 Bit name Function 1 Scramble Disable Reserved Write 0p ignore on read access Scramble Disable Allows to bypass the data scrambler descrambler blocks R W Scramble disable Data scrambler descrambler bypass selection EDEN Data scrambler descrambler enabled initial value Data scrambler descrambler disabled Preliminary User s Manual A17988EE1V1UMO0 235 Chapter 16 Multiport Ethernet PHY 16 4 Board Design Recommendations In this chapter some board design recommendations will be given with respect to supply voltage circuitry line interfaces for 10BASE T 100BASE TX and 100BA
20. 222 cn e x ER eme 33 Pin Characteristics 43 Pin Status and Drive Characteristics 45 CPU FUuDctlOn ve teens POLL Tetiers kr 2E 49 Structure of The ARM946E S Processor 49 Cache Structure of ARM946E S 50 Tightly Coupled Memories 50 Memory Protection Unit 51 Bus Interface of 946 6 51 ARM946E S Embedded Trace Macrocell ETM9 52 946 5 53 ERTEG 200 Bus 55 Multilayer AHB 55 APBUY O BUS 2 ore Reese usu 56 200 Memory 57 Memory Partitioning of ERTEC 200 57 Detailed Memory 58 Memory 60 External Memory Interface 63 Address Assignment of EMIF Registers
21. 140 O P 2 1 RDxN ERTEC 200 P 2 1 RDxP 82 79 1130 Optical transceiver 82 OF 130 P 2 1 SDxN 820 9 130 P 2 1 SDxP VRef 0 z o 5 Q L Note The circuitry in the transmit path deviates slightly from the examples that are typically given in optical transceiver data sheets However it is required to implement the circuit above in order to provide pECL compliant output levels In applications that do not use 10BASE T respectively 100BASE TX modes but only the 100BASE FX mode the analog I Os P 2 1 TxN P 2 1 TxP P 2 1 RxN and P 2 1 RxP should be left open Only EXTRES must still be connected with the 12 4 resistor to analog GND Preliminary User s Manual A17988EE1V1UMO0 239 Chapter 16 Multiport Ethernet PHY MEMO 240 Preliminary User s Manual 17988 1 10 00 Chapter 17 System Control Registers The system control registers are no peripheral in the original sense but rather an ERTEC 200 specific register set that can be read and written to from the various AHB masters via the AHB to APB bridge The system control registers provide a certain level of self diagnosis and configuration capabilities A listing of all system control registers and their address assignments as well as a detailed description are included in the following sections 17 1 Address Assignment of System Control Registers
22. 16 1 1 10BASE T Operation A 10BASE T transceiver is implemented for a 10 Mbps CSMA CD LAN over two pairs of twisted pair wires according to the specifications given in clause 14 of the IEEE 802 3 standard During transmis sion 4 bit nibble data comes from the MII interface at a rate of 2 5 MHz and is converted into a 10 Mbps serial data stream The data stream is then Manchester encoded and sent to the analog transmitter which drives a signal to the twisted pair cable via external magnetics In order to comply with legacy 10BASE T MAC Controllers the transmitted data is looped back to the receive path if the PHY is configured to work in half duplex mode On the receiver side the receive clock is recovered from the incoming signal The received Manches ter encoded analog signal from the cable is recovered to the NRZI data stream using the clock Then the 10 Mbps serial data stream is again converted to 4 bit data that are passed to the MAC across the MII interface at a rate of 2 5 MHz Preliminary User s Manual A17988EE1V1UMO0 187 Chapter 16 Multiport Ethernet PHY The PHY realizes a complete 10BASE T transceiver function It includes the receiver transmitter and the following functions lt 1 gt Filter and squelch lt 2 gt Jabber detection lt 3 gt Signal quality error SQE message test function lt 4 gt Timing recovery from received data lt 5 gt Manchester encoding decoding 6 Full duplex or half duplex mode In
23. Note In Table 12 4 and 12 5 x stands for don t care 150 Preliminary User s Manual 17988 1 10 00 Chapter 13 Synchronous Serial Interface SPI1 A synchronous serial interface is implemented in ERTEC 200 it is referred to as SPI1 The inputs and outputs of the SPI1 interface are available as an alternative function at GPIO 23 16 To use SPI1 it is required to set input output direction accordingly for the affected pins using the GPIO_IOCTRL register to configure alternative function 1 for the affected pins using the GPIO PORT MODE register Note that after reset all GPIO pins are configured as GPIO inputs an eventually configured SPI1 is lost If the is used the affected pins are no longer available as standard I O The base frequency for the internal bit rate generation is the 50 MHz APB clock The data bit width for read write accesses to the SPI1 registers is 16 bits The following signal pins are available for the SPI1 interface on the ERTEC 200 Table 13 1 5 Pin Functions Pin Name Function Number of pins SPI1 SSPTXD SPI transmit data output SPI1 SSPRXD SPI receive data input SPI1 SCLKIN SPI clock input SPI1 SCLKOUT SPI clock output SPI1 SSPCTLOE SPI clock and serial frame output enable SPI1 SSPOE SPI output enable SPI1 SFRMIN SPI serial frame input signal SPI1 SFRMOUT SPI serial frame output signal total The SPI1 interface is implemented as A
24. Silicon revision register Mode control status register Special modes Reserved Control status indication register Reserved Interrupt source register Interrupt mask register PHY special control status register Vendor specific During a hardware reset or when the PHYs are driven out of the power down state by setting the P1 2 PHY ENB bits in the PHY CONFIG register to 1 a pre defined configuration is set in the regis ters This configuration is partly hardwired and affects the initial settings of PHY internal registers Table 16 10 shows these settings the initial configuration can be altered later by writing to the PHY internal registers 206 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Table 16 10 Initial Parameter Settings for PHYs Description P1 2 PHYADDRESS 4 0 PHY address P1 2 PHYMODE 2 0 PHY mode depends on PHY CONFIG register setting 1 2 MIIMODE 1 0 Interface mode of PHY permanently set to MII mode P1 2 SMIISOURCESYNC SMII source mode permanently set to normal mode P1 2 FXMODE 100BASE FX mode depends on PHY CONFIG register setting P1 2 AUTOMDIXEN Enable AutoMDIX state machine depends on PHY CONFIG register setting 1 2 NPMSGCODE 2 0 Test of next page function permanently set to 000 P1 2 PHYENABLE Enables the PHYs depends on PHY register setting REG2OUIIN 15 0 Default value for SMII register
25. GPIO2 GPIO2 IOCTRLn GPIO pin direction control IOCTRL is used as output is used as input initial value Figure 11 9 GPIO2 OUT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit name Function 31 13 Reserved GPIO2 OUT 12 0 Data written into this register is output at the GPIO pins on a bit by bit basis under the assumption that the pin is actually configured as output GPIO2 OUTn GPIO output data 0 Output low level at pin initial value 1p Output high level at Preliminary User s Manual A17988EE1V1UM00 133 Chapter 11 General Purpose I O GPIO Figure 11 10 GPIO2 IN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2528H 0000 xxxxH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIO2_IN Bit position Bit name Function 31 13 Reserved GPIO2 IN 12 0 This register reflects the logical level at the GPIO pins on a bit by bit basis under the assumption that the pin is actually configured as input GPIO2 IN GPIO2 INn GPIO input data 0 Low level is applied to GPIOn pin 1p High level is applied to GPlOn pin 134 Preliminary User s Manual 17988 1 10 00 Chapter 11 General Purpose I O GPIO The following Table 11 3 describes the GPIO 31 0 pins and their alter
26. Chapter 16 Multiport Ethernet PHY Figure 16 18 Special Control Status Indication Registerr 15 14 13 12 11 10 9 8 No Initial value SWRST_ 7 6 5 4 3 2 1 0 Bit position Bit name Function Reserved Write 000 ignore on read access SWRST_FAST Accelerates software reset extension from 256us to 10 5 for production test SWRST_FAST Software reset extension acceleration Software reset is extended 256us initial value Software reset is extended to 10us initial value SQEOFF Disables the SQE heartbeat test SQEOFF SQE test disable SQEOFF SQE test is enabled initial value after hardware reset SQE test is disabled Note The value is unchanged after a software reset of the PHYs Reserved Write 00H ignore on read access FEFIEN Enables far end fault indication FEFIEN Far end fault indication is disabled initial value when FX_MODE bit is 1 during reset Far end fault indication is enabled initial value when FX_MODE bit is 0 during reset XPOL Indicates polarity state of a 10BASE T link Normal polarity initial value Reversed polarity Reserved Ignore on read access 230 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Figure 16 19 Interrupt Source Flag Register 1 2 15 14 13 12 11 10 9 8 No Initial value Reserved 29 OH 7 6 5 4 3 2 1 0 Bit position Bit name Function Reserved Ignore on read a
27. Function General purpose I O signal Alternate FunctionN te LBU IRQ 1 0 N GPIO42 General purpose signal LBU RDY N GPIO41 General purpose signal LBU D15 GPIO40 General purpose signal LBU CS MN 9 General purpose signal LBU_CS_R_N GPIO 38 37 General purpose signal LBU SEG 1 0 GPIO 36 32 General purpose signal LBU A 20 16 GPIO31 GPIO 30 26 General purpose signal General purpose signal DBGREQ GPIO25 General purpose signal TGEN OUT1 N GPIO24 GPIO23 General purpose signal General purpose signal PLL EXT IN N SPI1 SCLKIN GPIO22 General purpose signal SPI1_SFRMIN DBGACK 21 GPIO20 General purpose signal General purpose signal SFRMOUT SPI1 CLKOUT GPIO19 General purpose signal SPI1 SSPTXD GPIO18 GPIO17 General purpose signal General purpose signal SPI1 SSPRXD SPI1 SSPOE GPIO16 General purpose signal SPI1 SSPCTLOE GPIO15 GPIO14 General purpose signal General purpose signal WD WDOUTO N DBGACK GPIO13 General purpose signal GPIO12 GPIO11 General purpose I O signal General purpose I O signal UART CTS_N UART DSR_N GPIO10 GPIO9 GPIO8 General purpose signal General purpose sig
28. PLL is locked initial value Note These interrupts are connected via wired OR and then routed to the FIQ3 input of the FIQ interrupt controller Preliminary User s Manual A17988EE1V1UMO00 247 Chapter 17 System Control Registers Figure 17 7 AHB Timeout Address Register QVZ_AHB_ADR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value QVZ_AHB_ADR 4000 2628H 0000 0000H 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 QVZ_AHB_ADR QVZ AHB ADR 31 0 31 0 AHB ADR Holds the address case of an incorrect multilayer access Figure 17 8 AHB Timeout Control Signal Register QVZ_AHB_CTRL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 262CH 0000 0000H 15 14 13 12 1 1109 8 7 6 5 4 2 1 0 HW reserved HBURST HSIZE RIT E Bit position Bit name Function Reserved HBURST 2 0 HBURST Holds the logical level of the HBURST 2 0 signals in case of an incorrect multilayer AHB access HSIZE 2 0 Holds the logical level of the HSIZE 2 0 signals in case of an incorrect multilayer AHB access HWRITE Holds the logical level of the HWRITE signal in case of an incorrect multilayer AHB access HWRITE HWRITE status of incorrect access HWRITE Incorrect access was a read access initial value Incorrect access was a write access 248 Preliminary User s Manual 17988 1 10 00 Chapter 17 System Control Registers Fi
29. Quartz connection Quartz connection Reference clock output Clock for F counter Power On reset Watchdog output Power supply for core 15V GND for core Power supply for IO 3 3 V GND for IO Analog power supply for PLL 1 5 V Analog GND for PLL Power supply for PECL buffers 3 3 V GND for PECL buffers Digital power supply for PHYs 1 5 V Digital GND for PHYs Analog port power supply 1 5 V Analog port GND Analog port GND Analog central power sup ply 1 5 V Analog central power sup ply 3 3 V Analog central GND Analog test power supply 3 3 V Analog test GND Chapter 1 Introduction 1 6 Configuration of Functional Blocks 1 6 1 Block Diagram of ERTEC 200 Figure 1 2 Internal Block Diagram Trace 25 MHz External Memory Interface JTAG Debug Port ri Fa Clock 4 Reset ARM946E S Unit 5 External with Ny 2 DMA ARM 8 kBytes 2 i B Memory L
30. the integrated PHYs need a reset pulse duration of more than 100us PULSE DUR must be set to values greater than 625 EN WD SOFT RES IRTE Selects if watchdog and soft resets include resetting the IRT switch EN WD SOFT RES IRTE Software reset EN WD SOFT RES IRTE Do not reset IRT switch with watchdog and soft D resets Reset IRT switch with watchdog and soft resets initial value XRES SOFT Allows to trigger a reset under software control This bit is not stored as the reset that is initiated by writing 1 to this bit automatically resets the bit again XRES_SOFT Do not trigger software reset initial value Trigger software reset WD RES FREI Enables disables a reset triggered by watchdog timer 1 Disable watchdog reset initial value Enable watchdog reset 244 Preliminary User s Manual 17988 1 10 00 Chapter 17 System Control Registers Figure 17 5 Reset Status Register RES_STAT_REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HW SW WD reserved RES RES RES ET ET ET Bit position Bit name Function Reserved HW RESET Indicates if the last reset event was a hardware reset or PowerOn reset Note HW RESET Hardware reset status 0 Last reset event was hardware reset 1 Last reset event was a hardware reset or PowerOn reset initial value SW_RESET Indicates if
31. 0000 000000 00 1xxx XXXXp 0000 0000 512 kBytes LBU A 0000 0000 00 01 XXXX XXXXp 0000 0000 1 MByte LBU_A 0000 0000 00 1X XXXXp XXXX XXXXp 0000 0000 2 MBytes LBU_A Note Bit numbers in the table refer to the complete 32 bit address that is formed by concatenating LBU Pn and LBU Pn L registers X Remark stands for don t care The largest of all configured pages determines the number of address lines that have to be connected to the LBU In Table 9 2 above the largest page is 2 Mbyte and the most significant bit that is set to 1p is Bit 21 In this case the number of required address lines is calculated from Amax 21 1 20 Therefore address lines LBU_A 20 0 are required This addressing mechanism results in a mirroring of the specified page size in the total segment Preliminary Users Manual A17988EE1V1UMO00 111 Chapter 9 Local Bus Unit LBU 9 2 Page Offset Setting The page offset of each page is set in the LBU Pn OF H and LBU Pn OF L registers n 0 to 3 Bit 7 0 of LBU Pn OF L are hardwired to Op Together the two page offset registers yield a 32 bit address register The register is evaluated in such a way that the offset is evaluated only down to the most significant bit of the associated page range register that is set to 15 These bits are then put on the AHB bus as the upper part of the address This mechanism guarantees that the
32. 10 0 LBU on LBU WR N used as write control signal LBU RD N used as read control signal LBU_RDY_N is active high 01 0 LBU on LBU WR N used as read write control signal LBU RDY Nis active low 00 Op LBU on LBU WR N used as write control signal LBU RD N used as read control signal LBU_RDY_N is active low 10 1 LBU off GPIO 44 32 active embedded trace on MII interface for diagnosis off 01 1 LBU GPIO 44 32 active embedded trace off MII interface for diagnosis on others Reserved CONFIG 4 3 00 50 MHz CPU core clock frequency 01 100 MHz CPU core clock frequency 150 MHz CPU core clock frequency Reserved CONFIG1 Clock output via REF_CLK pin 25 MHz REF_CLK pin in tri state Preliminary User s Manual 17988 1 10 00 Chapter 20 Address Space and Timeout Monitoring Several monitoring mechanisms are incorporated in ERTEC 200 for detection of incorrect addressing illegal accesses and timeout The following blocks are monitored AHB bus APB bus EMIF The monitoring mechanisms for these blocks will be described in detail in the subsequent chapters 20 1 AHB Bus Monitoring Separate address space monitoring is implemented for each of the four AHB masters If an AHB master addresses an unused address space the access is acknowledged with an error response and an FIQ interrupt is triggered at input FIQ2 of the ARM946E S
33. Able to perform auto negotiation initial value Link Status Indicates if a valid link has been established Link Status Link status indication Link Status fm Link status is down initial value Note This bit is cleared when it has been read Preliminary Users Manual A17988EE1V1UMO00 211 Bit position 212 Bit name Extended Capability Chapter 16 Multiport Ethernet PHY Figure 16 7 Basic Status Register 3 3 Function Jabber Detect Indicates if a jabber condition has been detected Jabber Detect Jabber condition detection indication No jabber condition has been detected initial value Jabber condition has been detected Note This bit is cleared when it has been read Extended Capability Indicates if the PHY supports extended register capabilities Extended Capability Extended register capabilities indication o Only basic register capabilities supported 1 Extended register capabilities supported initial value Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY The PHYs on ERTEC 200 have two registers for storage of a PHY identifier pattern a part of this pat tern forms the upper 24 bits of the MAC address and a part of these 24 bits is given by the so called organizationally unique identifier OUI The information in the REG2 3OUIIN registers is composed respectively interpreted as follows NEC s OUI number is 003013H This hexadec
34. Adjustable 8 16 32 bit data bus width 4 chip selects with individual timing control Default setting for boot operation timing is slow Maximum of 16 Mbytes can be addressed for each chip select Chip select 5 PERO can be used for boot memory Data bus width of boot ROM at C8 PERO Ni is selectable via BOOT 3 0 pins Adjustable timeout monitoring DTR N direction and OE DRIVER N enable control signals for direct control of an external driver for chip select signals C8 PER 3 0 e IRT Switch Two Fast Ethernet ports with integrated PHYs 10BASE T and 100BASE TX FX support Full duplex half duplex mode support Supports RT and IRT data traffic Autonegotiation Broadcast filter IEEE 1588 time stamping 64 kBytes of Communication SRAM Local Bus Unit LBU 16 bit data bus width 21 bit address bus width Host access to LBU paging registers via chip select signal LBU_CS_R_N Host access to any address area of ERTEC 200 via chip select signal LBU CS M N Maximum of 4 pages can be addressed Adjustable page range and page offset for each page reconfigurable at any time Preliminary User s Manual A17988EE1V1UMO0 19 1 Introduction DMA Controller One channel DMA controller Supports data transfers between internal and external memories Supports data transfers between peripherals and internal memory Selectable transfer width 8 16 32 bits and block size 4 request inputs for synchronization with periphera
35. FIQ interrupts No 4 and 5 are the interrupts of embedded ICE RT communication The UART can also be used as a debugger instead of the ICE An effective real time debugging is possible if the IRQ interrupt sources of the UART are mapped to the FIQs with numbers 6 or 7 This enables debugging of interrupt routines 90 Preliminary User s Manual 17988 1 10 00 8 8 Interrupt Control Register Summary Interrupt Controller The interrupt control registers are used to specify all aspects of control prioritization and masking of the IRQ FIQ interrupt controllers they are located at address 5000 0000 and beyond in the 32 bit AHB address space Interrupt control registers can only be accessed by the ARM946E S CPU table 8 3 summarizes these registers Address 5000 0000H Table 8 3 Register Name IRVEC Initial value FFFF FFFFH Interrupt Control Registers 1 2 Description Interrupt vector register 5000 0004H FIVEC FFFF FFFFH Fast interrupt vector register 5000 0008H LOCKREG 0000 0000H Priority lock register 5000 000CH FIQ1SREG 0000 0000H Fast int request 1 select register FIQ6 on FIQ interrupt controller 5000 0010H FIQ2SREG 0000 0000H Fast int request 2 select register FIQ7 on FIQ interrupt controller 5000 0014H IRQACK FFFF FFFFH Interrupt vector register with IRQ acknowledge 5000 0018H FIQACK FFFF FFFFH Fast interrupt vector register
36. Figure 15 4 Reload Register Low for Watchdog 0 RELDO LOW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ReloadO Bit position Bit name Function Key bits 15 0 Key bits Must be written with 9876H in order to make a write access effective read 0000H Reload0 15 0 Holds the reload value for bits 15 0 of watchdog timer 0 counter ReloadO Preliminary User s Manual A17988EE1V1UMO00 181 Chapter 15 Watchdog Timers Figure 15 5 Reload Register High for Watchdog 0 RELDO HIGH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Key bits 4000 2108H 0000 FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ReloadO Bit position Bit name Function Key bits 15 0 Key bits Must be written with 9876H in order to make a write access effective read 0000H Reload0 15 0 Reload0 Holds the reload value for bits 31 16 of watchdog timer 0 counter Figure 15 6 Reload Register Low for Watchdog 1 RELD1_LOW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Key bits 4000 210CH 0000 FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reload1 Bit position Bit name R W Function Key bits 15 0 Key bits Must be written with 9876H in order to make a write access effective read 0000H Reload1 15 0 Reload1 Holds the reload value for bits 19 4 of watchdog timer 1 counter bits 3 0 are always reloa
37. IRQO interrupt request can be re routed to FIQ6 initial value IRQ15 interrupt request can be re routed to FIQ6 Preliminary User s Manual 17988 1 10 00 Chapter8 Interrupt Controller Figure 8 5 FIQ2SREG Interrupt Select Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 0010H 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIQ2S reserved ENA reserved FIQ2SREG BLE Bit position Bit name Function Reserved FIQ2SENABLE Enables or disables the re routing of an IRQ interrupt to FIQ7 routi hani FIQ2SENABLE FIQ2SENABLE Interrupt re routing mechanism enable 0 Interrupt re routing to FIQ7 disabled initial value 1p Interrupt re routing to FIQ7 enabled Reserved FIQ2SREG 3 0 Declaration of an IRQ interrupt as FIQ input FIQ7 on FIQ interrupt controller FIQ2SREG 3 0 Interrupt number selection FIQ2SREG IRQO interrupt request can be re routed to FIQ7 0000 initial value 1111 IRQ15 interrupt request be re routed to FIQ7 Preliminary User s Manual A17988EE1V1UMO00 97 Chapter 8 Interrupt Controller Figure 8 6 IRQACK IRQ Interrupt Acknowledge Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Vector ID 5000 0014 FFFF FFFFH 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 Vector ID IRVEC Bit position Bit name Function Vector ID 27 0 Differentiates valid IRQ inter
38. M_LOCK_CTRL 2 0 Enables AHB master bus locking for each AHB master Bit Setting AHB master bus locking selection AHB master bus locking disabled for IRT initial value AHB master bus locking enabled for IRT M_LOCK_CTRL AHB master bus locking disabled for LBU initial value AHB master bus locking enabled for LBU AHB master bus locking disabled for ARM946E S initial value AHB master bus locking enabled for ARM946E S 252 Preliminary User s Manual 17988 1 10 00 Chapter 17 System Control Registers Figure 17 14 ARM9 Control Register ARM9_CTRL 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2650H 0000 1939H SYSOPT Bit position Bit name Function 31 14 Reserved BIGENDIAN Indicates whether the processor is running in big endian mode BIGENDIAN Big Endian mode BIGENDIAN Processor is running in little Endian mode initial value Processor is running in big Endian mode DISABLE_GATE_THE_CLK Determines if ARM9 CPU clock runs freely or not DISABLE_GATE_THE_CLK CPU clock run mode DISABLE_GATE_ THE CLK ARM9 processor clock is paused by a Wait for Interrupt 1 9 processor clock runs freely initial b value DBGEN Enables embedded ARM9 debugger DBGEN Embedded debugger enable Embedded debugger disabled Embedded debugger enabled initial value MICEBYPASS Allows to bypass synchronisation
39. Reload 15 0 Reload This register holds the 16 bit reload value for Timer 2 172 Preliminary User s Manual 17988 1 10 00 Chapter 14 ERTEC 200 Timers Figure 14 11 Current Timer Value Register for Timer 2 TIM2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 16 Reserved 15 0 Timer 15 0 i This register holds the current counter value for Timer 2 Preliminary User s Manual 17988 1 10 00 173 Chapter 14 ERTEC 200 Timers 14 3 F Timer An F timer is integrated in ERTEC 200 in addition to the system timers This timer works independently of the system clock and can be used for fail safe applications for example The F timer is operated with an external clock that is supplied via the F_CLK input pin The following signal pins are available for the F timer on ERTEC 200 Table 14 3 F Timer Pin Functions F_CLK F_CLK for F timer total 14 3 1 Functional description of the F Timer The asynchronous input signal of the external independent time base is applied at a synchronization stage via the F_CLK input pin To prevent occurrences of metastable states at the counter input the synchronization stage is implemented with three flip flop stages The count pulses are generated in a series connected edge detection All flip flops run at the APB clock of 50 MHz The F COUNTER VAL register is reset using an asynchronous block r
40. The system control registers are 32 bits wide they are summarized in Table 17 1 below Address 4000 2600H Table 17 1 Address Assignment of System Control Registers Register Name ID REG Initial value 4027 0100H Description Device identification register ERTEC 200 4000 2604H BOOT REG Boot mode pin register 4000 2608H CONFIG REG Config pin register 4000 260CH RES CTRL REG 0000 0004H Control register for ERTEC 200 reset 4000 2610H RES STAT REG 0000 0004H Status register for ERTEC 200 reset 4000 2614H 4000 2628H 4000 262CH PLL STAT REG QVZ AHB ADR QVZ AHB CTRL 0007 0005H 0000 0000H 0000 0000H Status register for PLL FIQ3 Address of incorrect addressing on multilayer AHB Control signals of incorrect addressing on multilayer AHB 4000 2630H QVZ AHB M 0000 0000H Master detection of incorrect addressing on multilayer AHB 4000 2634H QVZ APB ADR 0000 0000H Address of incorrect addressing on APB 4000 2638H QVZ EMIF ADR 0000 0000H Address that leads to timeout on EMIF 4000 2644H 4000 264CH 4000 2650H MEM SWAP M LOCK CTRL ARM9_CTRL 0000 0000H 0000 0000H 0000 1939H Memory swapping in Segment 0 between ROM and RAM AHB master lock enable Master selec tive enable of AHB lock functionality Control of ARM9 and ETM inputs 4000 2654H ARM9 WE 0000 0000H Write protection register for AR
41. Wait polarity Wait if RDY_PER_N is low Wait if RDY_PER_N is high initial value Reserved MAX EXT WAIT 7 0 Determines the number of AHB cycles before termination of an asynchronous memory or peripheral access with an IRQ MAX EXT WAIT 7 0 Wait cycle setting MAX EXT This value multiplied by 16 is equivalent to the WAIT number of AHB clock cycles that the asynchro n 0H FFH nous controller waits for RDY PER N before access is terminated with timeout IRQ The initial setting is 80H corresponding to 2048 AHB cycles or 40 96 us in case of 50 MHz AHB clock 66 Preliminary User s Manual 17988 1 10 00 Chapter6 External Memory Interface EMIF Figure 6 3 SDRAM Bank Config Register 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit name R W Function 31 14 Reserved CL CAS latency CAS latency Op CAS latency 2 1p CAS latency 3 initial value Reserved ROWS 2 0 row address select Configures the number of used row address lines ROWS 2 0 Number of used row address lines 000 8 row address lines initial value 9 row address lines 10 9 Mete 10 row address lines 11 row address lines 12 row address lines 13 row address lines Reserved Reserved Note Writing to the SDRAM Bank Config register executes the Mode Register Set command on th
42. gt Link status is down 2 Setting the Auto Negotiation Restart bit in the Basic Control register to high 3 Priority Resolution If two Ethernet communication partners negotiate their capabilities there are four possible matches of the technology abilities In the order of priority these are 100M full Duplex highest priority 100M Half Duplex 10M full Duplex 10M Half Duplex lowest priority Since two devices local device and remote device may have multiple abilities in common a prioritiza tion scheme exists to ensure that the highest common denominator ability is chosen Full duplex solu tions are always higher in priority than their half duplex counterparts 10BASE T is the lowest common denominator and therefore has the lowest priority Preliminary User s Manual A17988EE1V1UMO0 193 Chapter 16 Multiport Ethernet PHY If a link is formed via parallel detection then the Link Partner Auto negotiation Able bit in the Auto Negotiation Expansion register is cleared to indicate that the link partner is not capable of auto negotia tion The controller has access to this information via the management interface If a fault occurs during parallel detection the Parallel Detection Fault bit in the same register is set The Auto Negotiation Link Partner Ability register 5 is used to store the link partner s ability information which was decoded from the received FLPs If the link partner is not auto negotiation capable th
43. 50 kQ pull up Tp Note 6 TMsNote 6 50 kQ pull up 50 kQ pull up Preliminary User s Manual A17988EE1V1UM00 45 TDONoete 6 Table 2 15 Pin Status During Reset and Recommended Connections 2 2 Internal pull during Level External pull up down reset during reset up down required SRST N 50 kO pull up TAP SEL Notes 1 Oo m mc 50 kO pull up These pins are used as inputs only during the active reset phase The levels during reset shown in Table 2 15 refer to the default configuration without external pull up down resistors connected to BOOT 3 0 CONFIG 6 1 These pins have alternative functions to which the characteristics apply as well Note that the I O type given in Table 2 14 applies to the pin I O types that apply to one of the shared functions of a specific pin are found in Tables 2 1 to 2 12 The reset behaviour of this pin is determined by the CONFIG1 signal RESET N must be externally driven low in order to reset the device High level is generated from external pull up resistor and not by internal device circuitry The reset signal that affects these signals is TRST All trace interface pins are configured as inputs in the default configuration that is determined by the internal pull up down resistors at the CONFIG 6 5 and pins Remarks 1 Shared pins are not listed with all possible pin names Ple
44. A22 CONFIG5 RAS SDRAM N GND IO P2VSSATX1 GNpNote GNpNote GND33ESD DVDD2 P2TxN DGND1 VDDACB GND IO BEO DQMO N 16 2 D20 BE2 DQM2_N D21 leave open P2VSSARX D18 P2VDDARXTX P1VSSARX GNpDNote GNpNote GNpNote P1VDDARXTX GNpNote 1 P1TxP D2 D3 A18 CONFIG1 D25 17 D16 DQMS3 D22 D17 GNpNote D19 GNpNote P1VSSATX1 GNDNote P1VSSATX2 P2RxP VDDAPLL GNpNote P2RxN D4 GNpNote VDD Core CS_SDRAM_N CAS_SDRAM_N D26 D23 VDD Core D24 GND Core DGND3 VSSAPLLCB GNpNote P2VSSATX2 VDDQ PECL EXTRES DVDD4 leave open DVDD3 CLK_SDRAM GND IO Note 24 DO Preliminary User s Manual 17988 1 10 00 D5 Connect to GND to improve heat dissipation pins may as well be left open Chapter 1 Introduction Table 1 1 Pin Configuration of ERTEC 200 4 5 Pin Number Pin Name D27 Pin Number Pin Name LBU D13 SMI MDIO leave open LBU D14 RES PHY N GND Core GND IO DGND4 VDD Core GND PECL P2SDxP GND PECL VDDQ PECL VDD Core GNpNote GNDNote D9 D6 D7 D29 D28 D30 GND IO D31 VDD Core TCK GND IO TAP_SEL VDD Core LBU A16 GPIO32 TDI
45. AutoMDIX en Enables the state machine for automatic detection of MDI MDIX mode AutoMDIX en Automatic MDI MDIX detection enable State machine for automatic MDI MDIX detection AutoMDIX_ disabled initial value after device reset en State machine for automatic MDI MDIX detection enabled Note The initial value after only the PHY has been reset is selected by the contents of the AUTOMDIXEN bit in the PHY CONFIG register MDI mode Selects MDI or MDIX mode manually MDI mode Manual MDI MDIX setting MDI mode o Set MDI mode initial value Note This bit is only relevant if the AutoMDIX en bit is set to Op Reserved Write 0p ignore on read access PHYADBP Causes the PHY to ignore PHY address during SMI write access this bit can be used for simultaneous write access to several PHYS PHYADBP PHYADBP PHY address bypass enable Do not ignore PHY address during SMI write access initial value Ignore PHY address during SMI write access Force Good Link Status Forces an active 100BASE X link irrespective of what is happening on the line Force Good Link Status Normal operation initial value Force an active 100BASE X link Note This bit should only be used during laboratory testing 226 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Figure 16 16 Mode Control Status Register 3 3 Bit position Bit name Function ENERGYO
46. Chapter 16 Multiport Ethernet PHY Figure 16 16 Mode Control Status Register 1 3 13 12 11 10 9 8 Initial value Reserved Reserved 17 XyzH AutoMDIX en Bit position Bit name Force Reserved Good Link Reserved Status Function Reserved Write 0p ignore on read access EDPWRDOWN Enables the energy detect power down function EDPWRDOWN Energy detect power down enable o Energy detect power down disabled initial value Energy detect power down enabled Reserved Write 0p ignore on read access LOWSQEN Sets a lower threshold for the sqelch function LOWSQEN Energy detect power down enable Higher threshold for squelch function set less sensitive initial value Lower threshold for squelch function enabled more sensitive MDPREBP Management data preamble bypass 10 MDPREBP R W Ignore SMI packets without preamble initial value Detect SMI packets without preamble FARLOOPBACK Enables the remote loopback mode in which all received packets are immedi ately re transmitted if the PHY is set to 100 or 100BASE FX mode FAR LOOP 9 BACK R W Remote loopback mode disabled initial value Remote loopback mode enabled Preliminary User s Manual A17988EE1V1UM00 225 Chapter 16 Multiport Ethernet PHY Figure 16 16 Mode Control Status Register 2 3 Bit position Bit name Function Reserved Write 0p ignore on read access
47. For read write access of the timer registers to be meaningful a 32 bit access is required However an 8 bit or 16 bit access is not intercepted by the hardware Table 14 1 Address Assignment of Timer 0 and Timer 1 Registers Address Register Name Initial value Description 4000 2000H CTRL_STATO 0000 0000H Control status register timer 0 4000 2004H STAT1 0000 0000H Control status register timer 1 4000 2008H RELDO 0000 0000H Reload register timer 0 4000 200CH RELD1 0000 0000H Reload register timer 1 4000 2010H CTRL_PREDIV 0000 0000H Control register for both prescalers 4000 2014H RELD PREDIV 0000 0000H Reload register for both prescalers 4000 2018H TIMO 0000 0000H Timer 0 value register 4000 201CH TIM1 0000 0000H Timer 1 value register Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits 14 1 6 Detailed description of Timer 0 1 registers Figure 14 2 Control Status Register 0 CTRL STATO 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2000H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 Relo reserved Sta res ad Load un tus xStop Mode Bit position Bit name Function Reserved Status Timer 0 status indication Timer 0 status indication Status Timer 0 has not expired initial value Timer 0 has expired Note Note This b
48. Interrupt Mask Register 0 0000400 nennen ennemis 233 PHY Special Control Status Register 1 2 234 PHY Special Control Status Register 2 2 235 Decoupling Capacitor Usage ssssssssssssseeseeeeee eene 237 10BASE T and 100BASE TX Interface Circuit Example 1 237 10BASE T and 100BASE TX Interface Circuit Example 2 238 Circuit for Unused 100BASE FX 238 100BASE FX Interface 220 400400 00 239 Device Identification Register ID 242 Boot Mode Pin Register BOOT_REG 242 Config Pin Register CONFIG 243 Reset Control Register RES_CTRL_REG 1 2 244 Reset Status Register RES STAT 245 PLL Status Register PLL_STAT_REG 1 2 246 AHB Timeout Address Register QVZ 248 AHB Timeout Control Signal Register QVZ 248 AHB Timeout Master Register QVZ 249 APB Timeout Address Register QVZ ADR 250 EMIF Timeout Address Register QVZ EMIF ADR 250 Memory Swap Register MEM 5 nennen nns 251 AHB Master Lock Control Register M
49. LBU 17 TRST LBU A15 COL P2 SEG 1 GPIO38 LBU A19 GPIO35 LBU CS N GPIO40 VDD Core GND IO LBU D12 SMI MDC GND Core LBU D1 TXD P11 VDD Core LBU D15 GPIO41 P2SDxN VDD Core leave open IRQ1 N GPIO44 P2RDxN LBU RDY N GPIO42 P2RDxP P2TDxN BE1 DOM1 VDD IO D8 VDD IO VDD Core D11 VDD Core P2TDxP GND Core VDD IO TMS D12 SRST N D13 TDO D15 LBU A18 GPIO34 GND Core LBU A1 RXD P11 ETMEXTIN1 LBU A2 RXD P12 TRACEPKT7 LBU A20 GPIO36 LBU_A4 CRS_P1 TRACEPKT5 LBU_SEG_0 GPIO37 GND Core LBU_A6 RX_DV_P1 TRACEPKT3 LBU_A8 RXD_P20 TRACEPKT1 Note Connect to GND to improve heat dissipation pins may as well be left open Preliminary User s Manual A17988EE1V1UM00 25 1 Introduction Table 1 1 Pin Configuration of ERTEC 200 5 5 EL Pin Name R Pin Name AA9 LBU_A10 RXD_P22 TRACESYNC AB5 LBU_A3 RXD_P13 TRACEPKT6 AA10 LBU A11 RXD P23 PIPESTA2 AB6 LBU_A5 RX_ER_P1 TRACEPKT4 AA11 LBU A13 RX ER P2 PIPESTAO LBU_A7 COL_P1 TRACEPKT2 AA12 LBU WR N TX CLK P1 AB8 A9 RXD P21 TRACEPKTO AA13 LBU BE1 N RX CLK P2 9 VDD IO AA14 LBU DO TXD P10 AB10 LBU_A12 CRS_P2 PIPESTA1 AA15 VDD Core 11 A14 RX DV P2 16 LBU DS3 TXD P13 AB12 LBU CS N GPIOS39 17 LBU D5 TX ERR P1 AB13 LBU RD N TX CLK P2 AA18 LBU D7 TXD
50. LBU D1 _ 11 LBU_DO _ 10 z Preliminary User s Manual A17988EE1V1UM00 47 O O O 2 Pin Functions Table 2 16 Alternative Functions of LBU Interface Pins 2 2 LBU active MII diagnosis mode Trace interface active CONFIG 6 5 xx CONFIG 6 5 01 CONFIG 6 5 10 CONFIG2 0p CONFIG2 1 CONFIG2 1 Function 1 LBU_WR_N during reset Function 2 during reset Function 3 during reset TX_CLK_P1 LBU_RD_N LBU_BE1_N 2 2 LBU_BEO_N RX CLK P1 LBU SEG 1 LBU SEG 0 GPIO38 GPIO38 7 7 LBU_IRQ_1_N 44 GPIO44 LBU IRQ 0 N GPIO43 GPIO43 LBU RDY N GPIO42 GPIO42 LBU CS M N GPIO40 GPIO40 LBU CS R N 48 9 9 Preliminary User s Manual 17988 1 10 00 Chapter 3 CPU Function 3 1 Structure of ARM946E S Processor System An ARM946E S processor system is used in ERTEC 200 Figure 3 1 shows the structure of the proces sor In addition to the ARM9E S processor core the system contains a data cache an instruction cache a memory protection unit MPU a system control coprocessor and a tightly coupled data mem ory The processor system has an interface to the integrated AHB bus Figure 3 1 ARM 946E S Processor Sys
51. SMI Serial Management interface Control Auto negotiation a Internal loopback This loopback mode is defined in the 802 3 specification it is enabled by setting the Loop back bit in the Basic Control register 101 In this mode the scrambled transmit data is looped into the receive logic The COL_P 2 1 signal will be inactive in this mode unless the Collision Test bit in the Basic control register is active When the internal loopback mode is active the receive circuitry should be isolated from the net work medium In this mode the assertion of TX_EN_P 2 1 at the MII interface does not result in the transmission of data on the network medium and transmitters are powered down b Remote loopback This mode is enabled by setting the FARLOOP BACK bit in the Mode Control Status register to 1p This mode can be used only when the PHYs are in 100BASE TX or 100BASE FX mode In this mode packets that arrive at the receiver are looped back out to the transmitter In 100BASE TX mode the data path includes the ADC DSP PCS circuits in 100BASE FX mode the data path includes the PECL logic clock recovery and PCS logic As long as no data is received IDLE sym bols are transmitted In this mode the complete preamble SFD and EFD are re generated by the PHY so that always complete packets are transmitted even if received packets lack part of the preamble The Isolate bit in the Basic Control register needs to be cleared to
52. 2 VDDESD VDDAPLL VDDACB and P 2 1 VDDARXTX they should be placed as close as possible to the chip Additonally pairs of 0 1 and 22uF capacitors should be applied to DVDD4 DVDD1 VDD3ESD and P 2 1 VDDARXTX Figure 16 22 shows the proposed circuit 236 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Figure 16 22 Decoupling Capacitor Usage GND VDD Core 1 5 V VDD IO 3 3 V e e a a 8 a a VDD33ESD GND33ESD P1VDDARXTX P1VSSARX P1VSSATX1 P1VSSATX2 VSSAPLLCB P2VSSATX2 P2VSSATX1 P2VSSARX P2VDDARXTX ERTEC 200 16 4 2 10BASE T and 100BASE TX Mode Circuitry The analog input and output signals are very noise sensitive and PCB layout of these signals should be done very carefully 2 1 P 2 1 TxP P 2 1 RxN and P 2 1 RxP must be routed with differential 100 O impedance and the trace length must be kept as short as possible The EXTRES input must be connected to analog GND with 12 4 resistor 1 tolerance Figures and show typical circuit examples for 10BASE T and or 100BASE TX operation modes Figure 16 23 10BASE T and 100BASE TX Interface Circuit Example 1 Unmarked resistors 1 16 W and 1 tolerance Resistors marked with 1 8 W and 1
53. 2 MBytes Therefore Bits 7 0 and 31 22 of the PAGEn RANGE register remain unchanged at a value of 0 even if a value of 1 is written If no bit at all is set in one of the page size registers the size of this page is set to 256 Bytes by default If several bits are set to 1 in one of the page range registers the size is always calculated based on the most significant bit that is set to 15 Table 9 2 summarizes the possible settings Table 9 2 Page Size Settings LBU Pn RG H Pn L Page size Required Bit 31 22 Note Bit 21 16 Note Bit 15 8 Bit 7 0 of page n address lines 0000 0000 00 00 0000 0000 0001 0000 0000 256 Bytes LBU_A 7 0 0000 0000 00 00 0000 0000 001 0000 0000 512 Bytes LBU_A 8 0 0000 0000 00 00 0000 0000 01 0000 0000 1 kByte LBU_A 9 0 0000 0000 00 00 0000 0000 1 0000 0000 2kBytes LBU_A 0000 0000 00 00 0000 0001 0000 0000 4kBytes LBU_A 10 0 11 0 0000 0000 00 00 0000 001x xxxxp 0000 0000 8 kBytes LBU_A 12 0 0000 0000 00 00 0000 01 XXXXp 0000 0000 16 kBytes LBU_A 13 0 0000 0000 00 00 0000 1XXX XXXXp 0000 0000 32 kBytes LBU_A 14 0 0000 0000 00 00 0001 XXXX XXXXp 0000 0000 64 kBytes LBU_A 15 0 0000 0000 00 00 001 XXXX XXXXp 0000 0000 128 kBytes LBU A 16 0 17 0 18 0 19 0 20 0 0000 0000 00 00 01 XXXX XXXXp 0000 0000 256 kBytes LBU_A
54. 21 AB14 BEO CLK P1 AA19 LBU DS9 TXD P23 AB15 VDD IO AA20 LBU D10 TX EN P2 16 LBU_D2 TXD_P12 AA21 LBU IRQO N GPIO43 AB17 LBU D4 TX EN P1 AA22 GND Core AB18 LBU_D6 TXD_P20 D14 LBU D8 TXD P22 LBU AO RXD P10 ETMEXTOUT VDD IO TRACECLK LBU D11 TX ERR P2 26 Preliminary User s Manual 17988 1 10 00 1 1 5 Pin Identification A 23 0 D 31 0 WR_N RD_N CLK_SDRAM BE 3 0 _DQM 3 0 _N CS_SDRAM_N RAS SDRAM N CAS SDRAM N WE SDRAM N CS PER 3 0 N RDY PER N DTR OE DRIVER N BOOT 3 0 CONFIG 6 1 GPIO 44 0 UART TXD UART RXD UART DCD N UART DSR N UART CTS N LBU A 20 0 LBU D 15 0 LBU WR N LBU RD N LBU BE 1 0 N LBU SEG 1 0 LBU IRQ 1 0 N LBU RDY N LBU CS MN LBU CS R N Introduction Table 1 2 Pin Identification 1 2 Address bus Data bus Write strobe Read strobe Clock to SDRAM Byte enable Chip select to SDRAM Row address strobe to SDRAM Column address strobe to SDRAM RD WR SDRAM Chip select Ready signal Direction signal for external driver or scan clock Enable signal for external driver or scan clock Boot mode System configuration GPIO pins UART transmit data output UART receive data input UART carrier detection signal UART data set ready signal UART transmit enable signal LBU address
55. 5 Controller Interrupt D Cache 4 kBytes lt 0 9 Interface Controller D TCM 4 kBytes EMIF 50 100 150MHz e Boot 8 ROM Slave Master Slave Slave Master APB 8 kBytes 1 x 1 32 bit 50 MHz IX Arb Input ecode pout o le MUX Arb st ge Decode Decodi stag blg GPIO t 2 o o 52 2 2 Bridge Multilayer m 32 bit 50 MH ES 2 n 4 le SPI ia UART gt 6 Timer jo a Watchdog S MC PLL o 5 o SPH B Master Slave E 4 gt o A jm ko Interface ao Wrapper Wrapper Slave Master 3 M ster MC Bus 32 bit 50 MHz SC Bus 32 bit 50 MHz Timer 85 Watchdog 4 gt F Timer Local Communi Switch Control p cation Bus Unit SRAM o System LBU 64 kBytes Control 16 bit 1 4 Registers Ethernet Ethernet Channel Channel Switch liis 9 EN 1 l y y v PHY PHY MUX Port 0 Port 1 Local Bus MDI Port 0 MDI Port 1 GPIO ETM MII Preliminary User s Manual A17988EE1V1UM00 29 Chapter 1 Introduction 1 6 2 On chip Units 1 2 3 4 5 6 7 8 30 CPU ARM946E S ERTEC 200 uses an ARM946E S 32 bit RISC processor core running at a maximum speed of 150 MHz This core processes 32 bit instructions according to the ARM5v5TE instruction set architecture as well as 16 bit wide THUMB instructions Instruction throughput is increased using a five stage
56. 9 8 7 6 5 4 3 2 1 0 Address Initial value 00 0014H 0000H 00 0024H 0000H 00 0034H 2000H LBU Pn OF L R W Bit 15 8 of the LBU page n offset setting Always 0p writing has no effect Figure 9 9 LBU Page Offset Register High LBU Pn OF H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value LBU Pn OF H 00 0006H 1010H 00 0016H 1000H 00 0026H 3000H 00 0036H 4000H LBU Pn OF H Bit 31 16 of the LBU page n offset setting Preliminary Users Manual A17988EE1V1UMO00 121 Chapter 9 Local Bus Unit LBU Figure 9 10 LBU Page Configuration Register LBU Pn CFG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value reserved 00 0008H 0000H 00 0018H 0001H 00 0028H 0000H 00 0038H 0001H Bit position Bit name Function Reserved Page n 32 Configures 32 bit or 16 bit pages Page n 32 Page n 32 Page width configuration 16 bit page width 32 bit page width 122 Preliminary User s Manual 17988 1 10 00 Chapter 10 Boot ROM 200 is equipped with a pre programmed boot ROM that allows software to be downloaded from an external storage medium The boot ROM has a size of 2k x 32 bits 8 kBytes and may only be read with 32 bit accesses Various routines are available for the different boot and download modes In order to select the boot source and mode four BOOT 3 0 inputs are available on ERTEC 200 During the active reset phase the boot pins are read in and stored i
57. Address Initial value reserved 4000 2004H 0000 0000H 15 14 13 12 1 1 10 9 8 7 6 5 4 3 1 0 Cas Relo reserved cad Sta res ad Load tus xStop ing Mode Bit position Bit name Function Reserved Cascading Selects if Timers 0 and 1 are cascaded Cascading Cascading of Timers 0 and 1 Timers 0 and 1 are not cascaded initial value Timers 0 and 1 are cascaded Status Timer 1 status indication Status Timer 1 has not expired initial value Timer 1 has expired Note Note This bit can only be read as 1 when the Run xStop bit is set to 1 Reserved Reload Mode Timer 1 Reload mode selection Note Timer 1 stops at value 0000 0000h initial value Timer 1 is loaded with the reload register value when the timer value is 0000 0000h and the timer continues to run Note If Timers 0 and 1 are cascaded this setting applies to both timers Preliminary User s Manual 17988 1 10 00 165 Chapter 14 ERTEC 200 Timers Figure 14 3 Control Status Register 1 CTRL_STAT1 2 2 Bit position Bit name Function Load Load trigger for Timer 1 No effect initial value Timer 1 is loaded with the reload register value Note Reload is executed irrespective of the Run xStop bit Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 1p to this bit is sufficient to trigger the timer 0 1 edge is n
58. CMOS 3 3 V CMOS 50 KQ pull up 50 KQ pull up CLKP_A CLKP_B Osc in Osc out TRACECLK 3 3 V CMOS Preliminary User s Manual A17988EE1V1UM00 43 2 Pin Functions Input type 3 3 V CMOS Output type Table 2 14 Pin Characteristics 2 2 Internal pull up down Drive capability REF_CLK 3 3 V CMOS RESET_N Schmitt 50 kQ pull up P 2 1 TXN Analog Analog Analog Analog 3 3 V CMOS 3 3 V CMOS Analog Analog P 2 1 SDxP EXTRES TRST_N Schmitt TCK TDI Schmitt Schmitt 50 kQ pull up 50 kQ pull up TMS TDO Schmitt 3 3 V CMOS 50 kQ pull up SRST_N TAP_SEL Schmitt Schmitt 3 3 V CMOS 50 kQ pull up 50 kQ pull up Notes 1 The address pins A 23 15 and the DTR_N pin are used as inputs only during the active reset phase 2 These pins have alternative functions to which the pin characteristics apply as well Note that the I O type given in Table 2 14 applies to the pin I O types that apply to one of the shared functions of a specific pin are found in Tables 2 1 to 2 12 3 These pins require external circuitry in order to provide PECL compliant output levels Remark Shared pins are not listed with all possible pin names Please check Tables 2 1 to 2 11 for possible pin names first before looking up pin characteristics in Table
59. Detailed LBU Register Description This chapter gives a detailed description of the LBU register bit functions As there is an identical set of five LBU registers for each configurable page only one set will be described as representative The initial values of the LBU registers result in a frequently usable view into the ERTEC 200 internal resources Page 0 64 kBytes view into Communication SRAM from 1010 0000 onwards 16 bit page Page 1 1 MByte view into the IRT switch internal registers from 1000 0000H onwards 32 bit page Page2 2 MBytes view into external memory connected to C8 PERO from 3000 0000H onwards 16 bit page 2 kBytes view into APB peripherals from 4000 2000 onwards above internal boot ROM 32 bit page Figure 9 6 LBU Page Range Register Low LBU_Pn_RG_L 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 00 0010H 0000H 00 0020H 0000H 00 0030H 0800H LBU Pn RG L R W Bit 15 8 of the LBU page n size setting Always 0p writing has no effect Figure 9 7 LBU Page Range Register High LBU Pn RG H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 00 0012H 0010H 00 0022H 0020H 00 0032H 0000H Always Op writing has no effect LBU Pn RG H R W Bit 21 16 of the LBU page n size setting 120 Preliminary User s Manual 17988 1 10 00 Chapter 9 Local Bus Unit LBU Figure 9 8 LBU Page Offset Register Low LBU Pn OF L 15 14 13 12 11 10
60. EMIF serial Flash or EEPROM via SPI LBU with an external host and UART Selection of boot sources is done via the BOOT 3 0 configuration pins GPIO Block ERTEC 200 has a total of 45 GPIO pins that are individually programmable as input or output Four of these GPIOs be used as interrupts 38 of these GPIOs are shared with other inter faces like UART SPI and LBU UART The integrated UART can be used for asynchronous serial communication It is based on the ARM PrimeCell 1 010 and is widely 16550 compatible 2 data lines and 3 handshake lines are used The internal 50 MHz clock is used for the UART operation and with a baud rate generator standard baud rates up to 115 kbps can be selected SPI The SPI is used for synchronous serial communication according to Motorola and National quasi standards Frame size protocol and speed are software programmable The maximum transmission speed is 25 MHz in master mode and 4 16 MHz in slave mode The SPI is based on the ARM PLo21 Timers Watchdog ERTEC 200 has four timers and two watchdogs Three of the timers are driven with the internal 50 MHz clock and based on 32 bit respectively 36 bit down counters that are cascadable and that can be configured with an additional 8 bit prescaler and an additional 16 bit up counter The fourth timer the F timer runs under the control of an external clock The watchdog timers are also based on 32 bit and 36 bit dow
61. Enables the interrupt after DMA transfer completionNete 2 INTR ENABLE DMA interrupt disabled initial value DMA interrupt enabled SYNCHRONIZATION 1 0 Determines which synchronization scheme is used for DMA source and des tination SYNCHRO NIZA DMA synchronization scheme SYNCHRONI TION 1 0 ZATION No synchronization initial value Synchronization to destination Synchronization to source Synchronization to source and destination Notes 1 The DMA is started with START ABORT 1 and stopped during operation with START ABORT Op The remaining bits are locked while the DMA is in operation If the DMA has been stopped it requires at least 2 clocks 50 MHz before it can be restarted 2 When synchronization is used the interrupt takes place only after the target request has been acti vated again When D Delay is used the interrupt takes place only after the delay of the last write access Preliminary User s Manual A17988EE1V1UMO0 83 Chapter 7 DMA Controller Figure 7 4 DMACO CONF REG DMA Configuration Register 2 4 Bit position Bit name Function 26 24 Reserved S ADDR MODE 1 0 Configures how the data source address is modified during the DMA transfer 5 ADDR MODE 1 0 DMA source address modification Increment source address initial value Decrement source address Hold source address Reserved S DMA REQ 2 0 Selects the in
62. Function Reserved CPSDVSR 7 0 Sets the divisor for the SPI1 clock prescaler CPSDVSR is always an even CPSDVSR number even when this field is written with an odd number bit O returns a O The resulting SPI1 clock frequency can be calculated with the formula Figure 13 2 Figure 13 7 SSPIIR SSPICR 5 Interrupt Identification and Clear Register 14 11 1 Address Initial value Bit position Bit name Function Reserved RORIS SPI1 receive FIFO overrun interrupt status SSP ROR INTR status indication SSP INTR not active initial value SSP ROR INTR active TIS SPI1 transmit FIFO service request interrupt status SSP TX INTR status indication 0 SSP_TX_INTR not active initial value SSP_TX_INTR active RIS SPI1 receive FIFO service request interrupt status SSP_RX_INTR status indication SSP_RX_INTR not active initial value SSP_RX_INTR active With any write access to this register the SPI1 receive FIFO overrun interrupt SSP_ROR_INTR is deleted without checking whether data are currently being written Preliminary User s Manual A17988EE1V1UM00 159 13 3 GPIO Register Initialization for SPI1 Usage Due to the fact that all SPI1 pins are shared with GPIO pins ERTEC 200 the GPIO registers need to be initialized properly before the SPI1 on ERTEC 200 can be used Below an example is given for a simple three wire SPI connection to an external serial Flash
63. ID Number Model Number 3 2001H 7 6 5 4 3 2 1 0 Bit position Bit name Function REG3OUIIN 15 0 REG3OUIIN Reflects bits 24 19 of the organizationally unique identifier OUI for the ERTEC 200 see Table 16 12 for exact bit assignment Model Model Number 5 0 Number Reflects a manufacturer depending revision number initial value is OOH Revision Revision number 3 0 number Reflects a manufacturer depending revision number initial value is 1H 214 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Figure 16 10 Auto Negotiation Advertisement Register 1 3 15 14 13 12 11 10 9 8 No Initial value 100BASE Note 14 4 xxxxH Reserved Reserved Pause Operation 10BASE T Full TOBASE Selector Field Duplex Note The initial value depends on the setting of the P 2 1 PHY MODE 2 0 bits the 1 2 Con figuration Register in the System Control Register block Bit position Bit name Function Next Page Selects if next page capablility is indicated to the link partner Next Page Next page capability indication No next page capability is indicated initial value Next Page Next page capability is indicated Reserved is 2 R write Op ignore on read access Remote Fault Indicates if a remote fault has been detected Remote Fault Remote fault detection indication Remote 13 Fault R W No remote fault condition has been detected
64. MBytes Not used Parallel Flash 3000 0000H FFFFH 256 MBytes 3000 0000H 303F FFFF 4 MBytes Not used Internal boot 4000 0000H 4000 0000H ROM 4000 1FFFH 8 kBytes 4000 1FFFH 8 kBytes 4000 2000H 32 Bytes i 4000 201 4000 20FFH 556 Bylue Not used 4000 2100H 28 Bytes 4000 211 57 4000 21FFH Not used 4000 2200H 4000 2200H x 4000 22FFH 226 Byles 4000 22 256 Bytes 4000 2300H 4000 2300H S a 4000 23FFH 256 Byles 4000 23FFH 256 Bytes 4000 2400H 4000 2400H Reserved 4000 24FFH 256 Bytes 4000 24FFH 256 Bytes 4000 2500H y AS 32 Bytes 4000 251FH Re 4000 25FFH Not used 60 Preliminary User s Manual 17988 1 10 00 Chapter 5 ERTEC 200 Memory Table 5 3 Memory and Used Address Range Example 2 2 Available Used Segment Contents Address range Size Address range Size 4000 2600H System Control 4000 2600H 4000 26A3H 164 Bytes Registers 4000 26FFH 256 Bytes Not used 4000 2700H 7 4000 2700 4000 2707 F Counter 4000 27FFH 256 Bytes 8 Bytes Not used 4000 2800H almost Not used 4FFF FFFFH 256 MBytes Not used 5000 0000H Interrupt 5000 0000H 5000 007F 128 Bytes controller 5FFF FFFFH 256 MBytes Not used 6000 0000H EM 6000 0000H 6000 1FFFH y 6FFF FFFFH 296 MByigs Internal SRAM Not used 7
65. Memory Map Decode Regions ETM9 ERTEC 200 Segment Memory 0 4 kBytes Instruction and data access to complete Instruction and data access to BOOT ROM SDRAM CS PERO 0 1MBytes Data access to IRT register 1 2MBytes Instruction and data access to IRT internal communication SRAM 0 256 MBytes Instruction and data access to external SDRAM 0 16kBytes Instruction and data access to external C8 PERO typically Flash 16 32 kBytes Instruction and data access to external C8 PER1 typically SRAM complete Data access to internal registers APB ICU EMIF DMA For more information on the ETM refer to the additional documents listed on page 6 Preliminary User s Manual A17988EE1V1UM00 273 Chapter 21 Test and Debugging 21 2 ETM9 Registers The ETM registers are not described in this document because they are handled differently according to the ETM version being used For a detailed description the reader is referred to the documents listed on page 6 21 3 Trace Interface In order to read out the trace information collected by the 9 a trace port is provided ERTEC 200 for tracing internal processor states The trace port is controlled enabled and disabled using a suitable hardware debugger that is connected to the JTAG interface This trace port uses the following signals Table 21 2 Trace Port Pin Functions Pin Name Function Number of pins PIP
66. Related Signals Pin NameNete Function Alternate FunctionNete RES PHY N Reset signal to PHYs LBU D14 EXTRES External reference resistor 12 4 Nete DVDD 4 1 Digital power supply 1 5 V DGND 4 1 Digital GND P 2 1 VSSATX 2 1 Analog port GND P 2 1 VDDARXTX Analog port RX TX power supply 1 5 V P 2 1 VSSARX Analog port GND VDDAPLL Analog central power supply 1 5 V VDDACB Analog central power supply 3 3 V VSSAPLLCB Analog central GND VDD33ESD Analog test power supply 3 3 V VSS33ESD Analog test GND Note The external resistor must have a maximum tolerance of 1 Preliminary User s Manual A17988EE1V1UMO00 205 Chapter 16 Multiport Ethernet PHY 16 3 PHY Register Description Via the SMI interface access is given to the internal registers listed in Table 16 9 Note that these regis ters are implemented for each PHY During write or read accesses the registers are selected using their register number as an address The PHY internal registers are not memory mapped Register number Table 16 9 PHY internal Registers Description Basic control register Basic status register PHY identifier 1 PHY identifier 2 Auto negotiation advertisement register Auto negotiation link partner ability register base page Auto negotiation link partner ability register next page Auto negotiation expansion register Next page transmit register Reserved Extended
67. S processor clock 100 MHz CONFIG 4 3 10 ARM946E S processor clock 150 MHz CONFIG 4 3 11 reserved Figure 18 1 shows the structure of the clock unit with the individual input and output clocks Figure 18 1 Detailed Representation of Clock Unit CONFIG4 HCLKEN HCLKEN gt Generator gt CONFIG3 to ARM946E S CLK ARM 9 50 100 150 MHz CLKP A PLL IN PLL OUT 25 MHz Divider 12 5 MHz 300 MHz CLK IN OSC 15 CLK_50 CLKP_B Clock gt 50 MHz Generation REF CLK p CLK 100 25 MHz 100 MHz CONFIG1 p gt LOCK STATE Lock Timer Power up 650 us Lock Monitor gt PHY 264 Preliminary User s Manual 17988 1 10 00 18 200 18 2 Specific Clock Supplies The clock supply for the JTAG interface is implemented using the JTAG_CLK pin The frequency range is between 0 and 10 MHz The boundary scan and the ICE macro cell of the ARM946E S are enabled via the JTAG interface The connection between the integrated Ethernet MACs and the integrated PHYs is realized with on chip MII interfaces The integrated PHYs are operated with the 25 MHz clock that is supplied via the CLKP A and CLKP B pins respectively via the CLKP pin only This clock is then used by the PHYs to generate the normally internal RX CLK and TX CLK clocks that are part of the MII interface to the MACs see Figure 18 2 Figur
68. SDRAM a data bus width of 16 or 32 bits can be configured the addressing capabilities allow connection of up to 128 MBytes of SDRAM SDRAM is accessed with the clock speed of the multilayer AHB bus therefore the maximum SDRAM speed is 50 MHz with a CAS latency of 2 For static devices 4 chip selects with an address range of 16 MBytes each are prepared They are independently configurable to 8 16 or 32 bit bus width and to individual access timings Slow peripherals are supported with a ready signal input and a timeout function Static chip select 0 can be used for an external boot device typically a flash memory as an alternative to using the boot loader in the on chip ROM IRT Switch The IRT switch block provides two Ethernet channels for 10 or 100 Mbps respectively half or full duplex operation The IRT switch is coupled to the multilayer AHB bus as a master and a slave and to the external world via two integrated PHYs allowing direct connection to magnetics or optical transceivers For the use of external PHYs the IRT switch can be re configured to 2 channel MII operation A large internal Communication SRAM with 64 kBytes in size helps to support RT and IRT data communication over Ethernet Local Bus Unit The Local Bus unit LBU allows to run ERTEC 200 as a peripheral to an external host controller The LBU is a master to the multilayer AHB bus and has separate address 21 bit and data 16 bit buses to the external world Seen with
69. SEL tylnternal RES signal from IRT switch resets the PHYs If the PowerOn reset is used the PHYs are active after reset if RES PHY N is used the PHYs remain in power down mode after reset and must subsequently be activated with the PowerDown bit in the Basic Control register The HW reset must be present for at least 100 us These reset sig nals are internally extended by 5 2ms to ensure that the PHY is properly reset All analog circuits and all digital logic including management registers are initialized After initialization the respec tive PWRUPRST signal in the PHY STATUS register is set Notes 1 During the hardware reset and its extension the clock signal for the PHYs must be supplied 2 Ahardware reset is commonly issued to both PHYs b Software reset Resetting the PHYs core can also be accomplished by setting the Reset bit in the respective Basic Control register to 15 This signal is self clearing After the register has been written the internal software reset is extended by 256us for PLL stabilization before the logic is released from reset A software reset affects the PHY registers and resets them to their initial values except where noted Note A software reset can be issued separately for each PHY c Reset by software and energy detect power down When the PHYs come out of software and energy detect power down they are automatically acti vated After exiting the power down mode the PHY internal powe
70. The PHYs on ERTEC 200 support a signal quality error SQE test function This function controls if data transmission is successful successful transmission is indicated by activating the COL P 2 1 sig nal for 1 us 2 us after TX EN P 2 1 has been deasserted This signal is also referred to as heart beat signal If desired the SQE test function can be disabled by setting the SQEOFF bit in control status register 27 to 1p The setting of the SQEOFF bit is irrelevant when the PHY is working in 100BASE TX or FX modes 4 Manchester encoding decoding When encoding the 4 bit nibble data that is coming from the MII interface is converted to a 10 Mbps serial NRZI data stream The 10M PLL locks onto the external clock and produces a 20 MHz clock sig nal which is used to Manchester encode the NRZ data stream When no data is being transmitted normal link pulses NLPs are output to maintain communications with the remote link partner When decoding the 10M PLL is locked onto the received Manchester signal and from this the internal 20 MHz receive clock is generated Using this clock the Manchester encoded data is extracted and converted to a 10 MHz NRZI data stream This stream is then converted from serial to 4 bit nibble data 188 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY 16 1 2 100BASE TX Operation 100BASE TX specifies operation over two copper media two pairs of shielded twisted pair ca
71. access is not intercepted by the hardware Table 14 2 Address Assignment of Timer 2 Registers 4000 2020H 2 CTRL 32 bit R W 0000 0000H Control register timer 2 4000 2024H TIM2 32 bit R 0000 0000H Timer 2 value register Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary User s Manual A17988EE1V1UMO00 171 Chapter 14 ERTEC 200 Timers 14 2 2 Detailed description of Timer 2 registers Figure 14 10 Control Register for Timer 2 TIM2_CTRL 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Address Initial value One Run reserved 1 Shot xStop 4000 2020H 0000 0000H Mode T2 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Bit position Bit name Function Reserved Timer Mode Selects trigger mode for Timer 2 Timer Mode Timer 2 trigger mode selection Timer 2 is free running initial value Timer 2 is re triggered if UART RXD pin goes to 0 OneShot Mode Selects between one shot mode and reload mode for Timer 2 OneShot Timer 2 is automatically set to OH when the reload Mode value is reached and continues counting reload mode initial value Timer 2 stops when the timer value equals the reload value one shot mode Run xStop T2 Starts and stops Timer 2 Run Run xStop_T2 Timer 2 start stop xStop_T2 Stops Timer 2 resets timer value register and de activates Timer 2 interrupt request initial value
72. and CONFIG2 are set to 111 reserved configuration this bit cannot be writ ten to it is then fixed to the default value Op 256 Preliminary User s Manual 17988 1 10 00 Chapter 17 System Control Registers Figure 17 17 PHY1 2 Configuration Register PHY CONFIG 2 4 Bit position Bit name R W Function P2_PHY_MODE 2 0 Select operation mode for PHY2 P2_PHY_MODE PHY2 operation mode Select 10BASE T HD Auto negotiate disa bled initial value Select 10BASE T FD Auto negotiate disa bled Select 100BASE TX FX HD Auto negotiate disabled Select 100BASE TX FX FD Auto negotiate disabled Select 100BASE TX HD advertised Auto negotiate enabled Select 100BASE TX HD advertised Auto negotiate enabled repeater mode 000 P2 PHY MODE Reserved Auto negotiate enabled AutoMDIX enabled P2 FX MODE Enables 100BASE FX interface P2 FX MODE PHY FX mode enable P2 FX MODE 100BASE FX interface disabled initial value 100BASE FX interface enabledNote 2 P2 PHY ENB Enables PHY2 P2_PHY_ENB PHY enable P2 PHY ENB 2 is disabled and in power down mode initial value Note 3 PHY2 is enabledNotes 1 3 4 Notes 1 If CONFIG 6 5 and CONFIG2 set to 111 reserved configuration this bit cannot be written to it is then fixed to the default value 2 This setting is only meaningful for PHY MODE set to 010 or 011p 3 If the PHY is disa
73. bit corresponds to bit 7 of the Extended Config register in the Note INT_QVZ_ EAE INT_QVZ_EMIF_STATE interrupt status TATE Interrupt request is not active initial value Interrupt request is active Note These interrupts are connected via wired OR and then routed to the FIQ3 input of the FIQ interrupt controller 246 Preliminary User s Manual 17988 1 10 00 Bit position Chapter 17 System Control Registers Figure 17 6 PLL Status Register PLL_STAT_REG 2 2 Bit name Function 4 Reserved INT_LOSS _ STATE INT_LOSS_STATE Indicates if the PLL input clock has once been lost This bit is not reset when the PLL input clock returns Once set it can only be reset by overriding itNote INT_LOSS_STATE INT_LOSS_STATE interrupt status Interrupt request is not active initial value Interrupt request is active INT_LOCK _STATE PLL_ INPUT_ CLK_LOSS INT_LOCK_STATE Indicates if the PLL has once been unlocked This bit is not reset when the PLL locks again Once set it can only be reset by overriding itNote Interrupt request is not active Interrupt request is active initial value PLL_INPUT_CLK_LOSS Represents the current monitoring status of the PLL input clock PLL input clock present initial value No PLL input clock present PLL_LOCK PLL_LOCK Indicates if the PLL is currently locked PLL is not locked
74. bus LBU data bus LBU write control LBU read control LBU byte enable LBU page selection LBU interrupt request LBU ready signal LBU chip select to ERTEC 200 internal resources LBU chip select to page configuration registers Preliminary User s Manual A17988EE1V1UMO0 SSPRXD SSPTXD SPI1 SCLKOUT SFRMOUT SPI1_SFRMIN SPI1_SCLKIN SPI1 SSPCTLOE SPI1 SSPOE TXD P 2 1 0 RXD P 2 1 2 RXD P 2 1 3 TX EN P 2 1 TX ERR P 2 1 RX ER P 2 1 CRS P 2 1 RX DV P 2 1 COL P 2 1 RX CLK P 2 1 TX CLK P 2 1 SMI MDC MDIO RES PHY N P 2 1 TxP 2 1 Tx 2 1 Rx 2 1 Rx 2 70 7 79 2 P 2 1 TDxP SPI receive data SPI transmit data SPI clock out SPI serial frame output SPI serial frame input SPI clock in SPI clock and serial frame output enable SPI output enable MII transmit data bit 0 MII transmit data bit 1 MII transmit data bit 2 MII transmit data bit 3 MII receive data bit 0 MIl receive data bit 1 receive data bit 2 receive data bit 3 MII transmit enable MII transmit error MII receive error MII carrier sense MII receive data valid MII collision MII receive clock MII transmit clock MII SMI clock MII input output Reset to PHY Differential transmit output Differential transmit output Differential receive input Differential receive i
75. bytes 2 Hold Address Mode In this mode the target or source addressed is fixed The DMA transfer can be initiated by soft ware via the DMACO_CONF_REG register or by a hardware signal a Software control The transfer can be started or stopped by writing to the Start Abort DMA configuration register bit b Hardware control The data transfer is controlled by activating the synchronisation signal see Table 7 2 As soon as the sync signal is deactivated the DMA controller stops the transfer With the next activation of the sync signal the data transfer is resumed by the DMA controller When the DMA transfer is complete a DMA INT interrupt takes place that is routed to the IRQ15 input of the IRQ interrupt controller In the case of a transfer to the UART or SPI the interrupt takes place after the last byte is transferred 7 1 Address Assignment of DMA Controller Registers The DMA registers are 32 bits in width The registers can be written to with 32 bit accesses only Only the ARM946E S processor can access the registers Table 7 3 DMA Controller Registers Address Register Name Size Initial value Description 8000 0000H DMACO SRC ADDR REG 32 bit 0000 0000H DMA source address register 8000 0004H DMACO DEST ADDR REG 32 bit 0000 0000H DMA destination address register 8000 0008H DMACO CONTR REG 32 bit 0000 0000H DMA control register 8000 000CH DMACO CONF REG 32 bit 0000 0000H DMA configuration register
76. enabledNote Note This setting is only meaningful for PHY MODE set to 010 or 0115 258 Preliminary User s Manual 17988 1 10 00 Bit position Notes 1 Chapter 17 System Control Registers Figure 17 17 PHY1 2 Configuration Register PHY CONFIG 4 4 Bit name Function P1 PHY ENB Enables PHY1 P1 PHY ENB PHY enable P1 PHY ENB PHY1 is disabled and in power down mode initial value Note 1 PHY1 is enablegNetes 1 2 If the PHY is disabled and subsequently re enabled a disable time of mode than 100 us must be maintained by the software If the PHY is enabled a reset is extended internally in the PHY by 5 3 ms During this time the PHY internal PLL and all analog and digital components of the PHY are started up The completion of this start up phase is signaled in the PHY_STATUS register with P1_PWRUPRST 1 Preliminary User s Manual A17988EE1V1UMO00 259 Chapter 17 System Control Registers Figure 17 18 PHY1 2 Status Register PHY STATUS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 Address Initial value 4000 2660H 0000 0000H reserved Bit position Bit name reserved Function Reserved P2_PWRUPRST Indicates whether PHY2 is ready to operate P2_PWRUPRST PHY operation status PHY2 is not ready to operate i e in power down mode or in start up phase initial value P2_PWRUPRST PHY2
77. gener ated INT1 Indicated if an auto negotiation page has been received Auto negotiation page receive interrupt No auto negotiation page receive interrupt has been generated initial value Auto negotiation page receive interrupt has been generated Reserved Ignore on read access 232 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Figure 16 20 Interrupt Mask Register 15 14 13 12 11 10 9 8 No Initial value 7 6 5 4 3 2 1 0 Mask bits Bit position Bit name Function Reserved Write Ob ignore on read access Mask bits Mask each interrupt from interrupt flag register separately Mask bit n n Interrupt n masking 1 7 Mask bits m source n from interrupt flag register is masked initial value Interrupt source n from interrupt flag register is enabled Reserved Write Ob ignore on read access Preliminary User s Manual A17988EE1V1UMO0 233 Chapter 16 Multiport Ethernet PHY Figure 16 21 PHY Special Control Status Register 1 2 15 14 13 12 11 10 9 8 No Initial value 7 6 5 4 3 2 1 0 Enable Scramble Bit position Bit name Function Reserved 15 12 R W write 000 ignore on read access Autodone Indicates if auto negotiation is done Auto negotiation done indication H pulogone n Auto negotiation is not done or disabled initial value Auto negotiation is done Reserved uc g TAN Write
78. initial value Insert two stop bits Preliminary User s Manual A17988EE1V1UMO00 143 Chapter 12 Asynchronous Serial Interface UART Figure 12 4 UARTLCR_H Register 2 2 Bit position Bit name Function EPS Selects even or odd parity for check and generation The setting of this bit is irrelevant when parity is disabled with the PEN bit Parity type selection Odd parity selected initial value Even parity selected PEN Enables or disables parity checking and generation Parity checking generation enable bit Parity checking generation disabled initial value Parity checking generation enabled BRK Selects if a low level is sent continuously at the transmit output MERE j Do not send break initial value Send break continuous low level Figure 12 5 UARTLCR M Register 7 6 5 4 3 2 1 0 Address Initial value BAUD DIVMS 4000 230CH 00H 7 0 BAUD B W BAUD DIVMS 7 0 DIVMS Higher byte of 16 bit wide baud rate divisor 144 Preliminary User s Manual 17988 1 10 00 Chapter 12 Asynchronous Serial Interface UART Figure 12 6 UARTLCR_L Register 7 6 5 4 3 2 1 0 Address BAUD DIVLS 4000 2310H Initial value 00H 7 0 BAUD BAUD DIVLS 7 0 DIVLS Lower byte of 16 bit wide baud rate divisor Note The baud rate divisor is calculated according to the following formula BAUDDIVLS 10481 01 _ 16 Zero is not a valid divisor this cas
79. is 50 or 100 MHz otherwise half rate mode must be selected Bus System ERTEC 2005 internal bus structure is made up of a multilayer AHB bus and an bus Both run at a maximum speed of 50 MHz The multilayer AHB bus offers multimaster capability and up to four simultaneous bus communica tion processes between masters and slaves Thus a very high availability of the AHB bus is achieved Potential bus masters are the ARM core the LBU interface the DMA controller and the IRT switch slaves are the external memory interface the DMA controller the IRT switch the inter rupt controller and the AHB to APB bridge The APB bus connects to the less demanding peripherals like UARTs SPI GPIOs etc On chip Memories ERTEC 200 has two categories of on chip memories the caches and the data TCM that are regarded as belonging to the core and a ROM area that is on chip but off core The on chip ROM has a size of 8 kBytes and is implemented as an APB peripheral The boot ROM content is pre defined and cannot be altered by the user It contains a boot loader program with the ability to choose among various other boot sources if desired Preliminary User s Manual A17988EE1V1UMO0 17 4 5 6 7 8 9 18 Chapter 1 Introduction External Memory Interface The memory controller on ERTEC 200 supports synchronous DRAM as well as static memories like SRAM or Flash Additionally static peripherals can be connected For
80. is deactivated Run XStop bit set to 0p the interrupt is also deactivated If the timer operates in reload mode without a prescaler the interrupt is present for only one 50 MHz cycle This must be taken into account when assigning the relevant interrupt input level edge evaluation 14 1 3 Timer prescaler An 8 bit prescaler is available for each timer Both prescalers are inactive after reset and are started setting the Run xStop V bit to 15 Settings can be made independently for each prescaler Each pres caler has its own 8 bit reload register If the reload value or starting value of the prescaler is 0 prescal ing does not occur The current prescaler value cannot be read out In addition there are no status bits for the prescalers The prescalers always operate in reload mode 14 1 4 Cascading of timers If the cascading bit is set both 32 bit timers can be cascaded to a 64 bit timer This cascaded timer is enabled via the status control register of Timer 1 The interrupt of Timer 1 is active The interrupt of Timer 0 must be disabled when the timers are cascaded When prescalers are specified additionally only the prescaler of Timer 1 is used The user must ensure data consistency in the user software when initialising or reading out the 64 bit timer 162 Preliminary User s Manual 17988 1 10 00 Chapter 14 200 Timers 14 1 5 Address assignment of Timer 0 1 registers The timer registers are 32 bits in width
81. levels are required for operation of ERTEC 200 The internal logic is running at 1 5 V the and parts of the integrated PHYs are operating at 3 3 V Preliminary User s Manual 17988 1 10 00 Chapter 1 Introduction 1 2 Device Features ARM946E S Processor Adjustable operating frequency 50 100 150 MHz System control coprocessor CP15 4 kBytes of Data TCM Interface with Write buffer on 32 bit multilayer AHB bus 8 kBytes and 4 kBytes D cache with lock functionality Memory Protection Unit Cacheability attribute setting for regions Read write access rights for certain modes only 2 interrupt controllers with 16 inputs for IRQ and 8 inputs for FIQ Debug trace functionality by ETM9 module via JTAG interface Trace in full rate mode at operating frequencies of 50 and 100 MHz Trace in half rate mode at an operating frequency of 150 MHz 4 8 bit trace data width selectable Trace can be restricted to selected address ranges and memory regions External Memory Interface SDRAM memory controller Adjustable 16 32 bit data bus width PC100 SDRAM compatible 50 MHz clock frequency Maximum of 128 MBytes 32 bit or 64 Mbytes 16 bit SDRAM Adjustable RAS CAS latency 2 3 for Write 1 2 for Read 2 bit bank address 1 2 4 banks via address bits A 1 0 8 9 10 11 bit column address A13 11 2 Maximum 13 bit row address A 14 2 Asynchronous memory controller for SRAM Flash
82. logic level represents a code bit 1 and the logic output remaining at the same level represents a code bit 0 In the receive direction the MLT 3 code is converted to an NRZI data stream The NRZI to MLT 3 con version is illustrated in Figure 16 2 Figure 16 2 MLT 3 Encoding Example Data 14114 01110110 MLT 3 encoded data 0 Preliminary User s Manual A17988EE1V1UMO00 191 Chapter 16 Multiport Ethernet PHY 7 Receive Data Valid Receive Error The receive data valid signal RX_DV_P 2 1 indicates that recovered and decoded nibbles are being presented on the RXD P1 3 0 respectively RXD_P2 3 0 outputs synchronous to RX CLK P 2 1 RX DV P 2 1 becomes active after the J K delimiter has been recognized and RXD P 2 1 is aligned to nibble boundaries It remains active until either the T R delimiter is recognized or link test indicates failure or CRS P 2 1 becomes false RXDV is asserted when the first nibble of translated J K is ready for transfer over the Media Independ ent Interface MII During a frame unexpected code groups are considered as receive errors Expected code groups are the data set OH through FH and the T R ESD symbol pair When a receive error occurs the RX ERR P 2 1 signal is asserted and arbitrary data is driven onto the RXD lines Should an error be detected during the time that the J K delimiter is being decoded bad SSD error RX ERR 2 1 is asserted true and the value 1110 is driv
83. memory as it is typically used for boot pur poses Note that in the specific case of a serial Flash for boot purposes two extra GPIOs are used in order to identify the type of external memory and to control the chip select signal of the serial Flash These two GPIOs are not directly involved in the SPI communication Table 13 3 GPIO Register Initialization Example for External Serial Flash Memory SPI pin func Realized with tion SPI1 SSPRXD GPIO18 function 1 SPI1 SSPTXD GPIO19 function 1 SPI1 SCLKOUT GPIO20 function 1 GPIO PORT MODE HNete XXXX XXXX XXXX XXXX 01 0101 GPIO_PORT_ MODE LNete XXXX XXXX XXXX XXXX XXXX XXXX XXXXp GPIO IOCTRLNete XXXX XXXX XXx0 01xx XXXX XXXX XXXX XXXXp Chip select GPIO22 function 0 control Memory f GPIO23 function 0 detection Note XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0000 XXXX XXXXp XXXX XXXX XXXX XXXXp In Table 13 3 x stands for don t care XXXX 01 XXXX XXXX XXXXp Figure 13 8 shows a simple circuit diagram for the connection of a serial Flash memory to ERTEC 200 based on above initialization Figure 13 8 to3 3V 4 7k 4 7k ERTEC 200 GPIO23 iud GPIO22 HPD80261 s ssprxp SPI1 SSPRXD SPIt_SCLKOUT 160 RESET_N WP_N Serial Flash s 450 011 so S
84. of GPIO 31 0 42 Pin Characteristics iren cede cep der ite ie ee edes 43 Pin Status During Reset and Recommended 5 45 Alternative Functions of LBU Interface 47 CP15 Coprocessor Registers enne 53 Possible AHB Master Slave Combinations sess 56 Memory Area 57 Detailed Description of Memory Segment sse 58 Memory and Used Address Range Example 60 External Memory Interface Pin 63 External Memory Interface Control 65 DMA Transfer Modes cried ede tne iia itil an 79 DMA Synchronization Signals 79 DMA Controller 80 FIQ Intem pt iSOUrees roe cde i A eed doe 87 IRQ Interrupt Sources ai rie een ee 88 Interrupt Control Registers eene nnne 91 Local Bus Interface Pin 109 Page SIZE Settings acs ia dd eder ctr e Rose idea P 111 Page Offset Setting Examples essessssssssssssseseeeene nente nennen nenne 112 L
85. of UART Registers Address Register Name Initial value Description 4000 2300H UARTDR Read write data from interface Receive status register when 4000 2304H UARTRSR UARTECR read error clear register when written 4000 2308H UARTLCR_H Line control register high byte 4000 230CH UARTLCR_M Line control register middle byte 4000 2310H UARTLCR_L Line control register low byte 4000 2314H UARTCR Control register 4000 2318H UARTFR Flag register Interrupt identification register 4000 231CH UARTIIR UARTICR read Interrupt clear register write 4000 2320H Reserved 4000 23FFH Remarks 1 During reset pins GPIO 31 0 are configured as input port pins Thus I O direction and alternative pin function usage have to be configured first before using the UART 2 Reserved bits in all registers are undefined when read always write the initial reset values to these bits 140 Preliminary User s Manual 17988 1 10 00 Chapter 12 Asynchronous Serial Interface UART 12 2 Detailed UART Register Description Figure 12 2 UARTDR Data Register 7 6 5 4 3 2 1 0 Address UARTDR 4000 2300H Bit position Bit name Function UARTDR 7 0 Write access If FIFO is enabled the written data are entered in the FIFO If FIFO is disabled the written data are entered in the transmit holding register the first word of the transmit FIFO UARTDR Read access If FIFO is enabled the receiv
86. offset is always an integer multiple of the selected page size The following Table 9 3 shows some examples for offset calculations for various page sizes Table 9 3 Page Offset Setting Examples Page size LBU Pn OF H LBU Pn OF L ofpagen Bit 31 24 Note Bit 23 16 Note Bit 15 8 Bit 7 0 256 Bytes 0000 0000 0000 0000 0000 0001 0000 0000 256 Bytes 256 Bytes 0000 0000 0000 0000 0001 0000 0000 0000 4kBytes Resulting offset 2 MBytes 0100 0000 00000000 0000 0000 0000 0000 1 GByte 512 kBytes 0001 0000 00000000 0000 0000 0000 0000 256 MBytes 8 kBytes 0000 0000 0000 0001 0000 0000 0000 0000 64 kBytes 8 kBytes 0000 0000 0000 0001 0100 0000 0000 0000 80 kBytes Note Bit numbers in the table refer to the complete 32 bit address that is formed by concatenating LBU Pn and Pn L registers Because the host computer can always access the page registers the pages can be reassigned at any time This is useful for example if a page is to be used to initialize the I O If access to this address area is no longer required after the initialization the page can then be reassigned in order to access other address areas of ERTEC 200 112 Preliminary User s Manual 17988 1 10 00 Chapter 9 Local Bus Unit LBU 9 3 Local Bus Unit Address Mapping Example The following Table 9 4 illustrates how an external host processor looks into the ERTEC 200 memo
87. pinning and hardware circuitry for JTAG signals at the Trace interface please refer to the documents listed on page 6 21 5 Debugging via UART If the UART is not used for user specific tasks it can also be used as a debugging interface In this case itis recommended to map the UART interrupt source to FIQ6 or FIQ7 in order to allow the debugging of interrupt routines 276 Preliminary User s Manual 17988 1 10 00 Although NEC has taken all possible steps essage to ensure thatthe documentation supplied to our customers is complete bug free From and up to date we readily accept that errors may occur Despite all the care and precautions we ve taken you may Name encounter problems in the documentation Please complete this form whenever Company you d like to report errors or suggest improvements to us Tel FAX Address Thank you for your kind support North America Hong Kong Philippines Oceania Asian Nations except Philippines NEC Electronics America Inc NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 65 6250 3583 Fax 1 800 729 9288 1 408 588 6130 Europe korea Japan NEC Electronics Europe GmbH NEC Electronics Hong Kong Ltd NEC Semiconductor Technical Hotline Marketing Services amp Publishing Seoul Branch Fax 81 44 435 9608 Fax 49 0 211 6503 1344 Fax 02 528 4411 Taiwan NEC Elec
88. separate LBU_RD_N and LBU_WR_N lines CONFIGS 1 LBU_WR_N serves as common RD WR line Preliminary User s Manual A17988EE1V1UM00 109 Chapter 9 Local Bus Unit LBU The polarity of the ready signal is selected via the CONFIG6 input level during the active reset phase CONFIG6 0 LBU_RDY_N active low CONFIG6 15 LBU RDY N active high LBU RDY N is a tri state output and must be pulled to its normally ready level by an external pull down or pull up resistor During an access from an external host via the LBU interface to ERTEC 200 the RDY output is first driven to its inactive level first When ERTEC 200 is ready to take or to provide data LBU RDY N will be active for approximately 20 ns 50 MHz internal clock period After that LBU RDY N is switched back to tri state and the external pull down or pull up generates the ready state again The four pages that were defined using the page registers are addressed via the SEG 1 0 inputs LBU SEG 1 0 00 LBU PAGEO addressed LBU SEG 1 0 01 PAGE 1 addressed LBU SEG 1 0 10 LBU 2 addressed LBU SEG 1 0 11 LBU addressed 110 Preliminary User s Manual A17988EE1V1UMO00 Chapter 9 Local Bus Unit LBU 9 1 Page Size Setting The page size of each page is set in the LBU Pn RG H and LBU Pn RG L range registers n 0 to 3 Together the two page range registers yield a 32 bit address register The size of the page varies between 256 Bytes and
89. supported by the link partner Selector Selector Field Field Indicates basic capabilities of the link partner according to the IEEE802 3 specification Preliminary User s Manual A17988EE1V1UMO0 219 Chapter 16 Multiport Ethernet PHY Figure 16 12 Auto Negotiation Link Partner Ability Register Next Page 1 2 15 14 13 12 11 10 9 8 No Initial value Next Page Acknowledge 2 Acknowledge 2 Toggle Message Unformatted Code field 5 0000H 7 6 5 4 3 2 1 0 Message Unformatted Code field Bit position Bit name Function Next Page Indicates if additional next page with link information will follow Next Page Next page indication Next Page No additional next page will follow initial value Additional next page will follow Acknowledge Indicates if the link partner s link code word has been successfully received Acknowl Not successfully received the link partner s link edge code word initial value Successfully received the link partner s link code word Message Page Page type indication Message Message Page Page type indication Page fm Next page is an unformatted page initial value Next page is a message page Acknowledge 2 Indicates if device complies to message Acknowl Acknowledge 2 Message compliance indication 2 Device does not comply to message initial value Device complies to message 220 Preliminary User s Manual 17988 1 10 00 Chapter
90. the code is copied from the boot Flash memory to SDRAM during the system startup phase and subse quently executed from SDRAM for optimized system performance Figure 6 11 External Memory Connection Example 2 e 5 8 3 8 2 uv a ERN 225 Quz gea 85 588 a 22 4 8 x 2227 SEEMS 2 9 92 2 22222 5 lt lt ZEEE 586868 JJJJJJJJJJJJJJ oON NOO amp 2 gt Dv 8 ZU 88h RESS8ARRERREELEES gs Zo x ae z z z z s dde 299 88 2 Bese 48 5 lt ANNO 6 gt 5 HE x 8SE
91. the UART Figure 12 1 UART Macro Block Diagram read data 10 0 rxd 10 0 TxFIFO RxFIFO 16 x 8 bit 16 x 8 bit Internal Reset Control amp status m UART TXD Baud rate divisor B Transmitter Receiver Baud16 AMBA APB APB bus lt interface and register block Baud rate Generator UART RXD Receive FIFO status Transmit FIFO status UART_CLK Operation clock 50 MHz or 6 MHz FIFO status UART INTR lt and interrupt UART DSR N FIFO Flags UART CTS_N generation UART DCD_N The UART has a single interrupt source that is wired to the IRQ interrupt controller see Table 8 2 UART_INTR UART group interrupt wired to IRQ8 Data transfer to and from the UART can either be controlled by the ARM946E S core or alternatively by the DMA controller In DMA mode the FIFO must be switched off because it does not indicate the watermark level As the DMA controller supports only one channel it can control either send or receive direction control of the other direction must then be implemented in software The baud rate and the divisor are calculated according to the following formulas BR SUART_CLK BAUDDIV SuaRT_CLK BAUDDIV 1 x 16 BR x 16 This yields the following error tolerance calculation dts BR BRI BRI x 100 with BRI being the ideal bit rate 138 Preliminary User s Manual 1
92. the last reset event was a software reset Note SW_RESET Software reset status SW_RESET Last reset event was no software reset initial value HW_RESET Last reset event was a software reset WD_RESET Indicates if the last reset event was a watchdog reset triggered by watchdog timer 1 Note WD_RESET atchdog reset status Last reset event was no watchdog reset initial value Last reset event was a watchdog reset Note Only the bit of the most recent reset event is set the other two bits are reset Preliminary User s Manual A17988EE1V1UMO00 245 Chapter 17 System Control Registers Figure 17 6 PLL Status Register PLL_STAT_REG 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address value MAS MAS reserved K LOK LO 4000 2614H 0007 0005H SS CK 4 3 2 0 INT INT AU PLL_ reserved res LOSSI LOG U_CLI LOC _STA K_ST K Lol TE ATE Bit position Bit name Function 31 18 Reserved INT MASK LOSS Interrupt masking for INT LOSS STATE interrupt INT MASK INT MASK LOSS INT LOSS STATE interrupt masking du Interrupt is enabled 15 14 13 12 11 10 9 8 7 6 Interrupt is masked initial value INT MASK LOCK Interrupt masking for INT LOCK STATE interrupt INT MASK LOCK Interrupt is enabled Interrupt is masked initial value Reserved INT_QVZ_EMIF_STATE External memory interface timeout interrupt status This
93. this table the I O types are listed for the UART function Pin Name SPI1_SSPRXD VoNote Table 2 7 SPI1 Pin Functions Function SPI1 receive data input Alternate FunctionNete GPIO18 SPI1 SSPTXD SPI transmit data output GPIO19 SPI1 SCLKOUT SPI1 clock output GPIO20 SPI1_SFRMOUT SPI1 serial frame input signal GPIO21 SFRMIN SPI1 serial frame output signal GPIO22 DBGACK SPI1_SCLKIN SPI1 clock input GPIO23 SPI1 SSPCTLOE SPI1 clock and serial frame output enable GPIO16 SPI1 SSPOE Note Function and alternative SPI output enable functions are selected with GPIO17 the GPIO PORT MODE GPIO PORT MODE L registers In this table the I O types are listed for the SPI1 function PLL EXT IN N Table 2 8 MC PLL Pin Functions MC PLL input signal GPIO24 TGEN OUT1 N PLL output signalNote 2 GPIO25 Notes 1 the I O types are listed for the MC PLL function 2 For a PROFINET IRT application GPIO25 must be configured as TGEN 1 output pin syn chronous clock signal is then output at this pin during certification of a PROFINET IO device with IRT support this signal must be accessible from the outside Preliminary User s Manual A17988EE1V1UMO0 Function and alternative functions are selected with the GPIO PORT MODE register In this table 39 2 Pin Functions Table 2 9 Clock an
94. to ARM9 clock MICEBYPASS TCK synchronization mode is synchronized to ARMO clock initial value ty is not synchronized to ARM9 clock MICEBYPASS Preliminary User s Manual A17988EE1V1UMO00 253 Chapter 17 System Control Registers Figure 17 14 ARM Control Register ARM9_CTRL 2 2 Bit position Bit name Function INITRAM Indicates whether the TCMs are enabled to useNote INITRAM TCM enable INITRAM 0 TCMs disabled initial value 1p TCMs enabled Note This bit is not affected by soft or watchdog reset it is only affected by a hardware reset via RESET SYSOPT 8 0 SYSOPT Displays the implemented ETM options the default value of this field is 139H Details can be found in the documents listed on page 6 Remark This register may only be changed for debug purposes Writing to this register must be enabled in the ARM9 WE register prior to accessing this register Figure 17 15 ARM Control Write Enable Register ARM9 WE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Bit position Bit name Function 31 1 Reserved WE 9 CTRL Enables to write to and change the ARM9 CTRL register WE ARM9 ARM9 WE CTRL ARMS CTRL register write enable TRL C ARM9_CTRL register write disabled initial value ARM9_CTRL register write enabled 254 Preliminary User s Manual 1798
95. to enable instructions and data to be traced The ARM946E S supplies the ETM module with the signals needed to carry out the trace functions The ETM9 module is operated by means of the trace interface or JTAG interface The trace information is stored in an internal FIFO and forwarded to the debugger via the interface The trace interface is shared with the LBU interface selection is made with the CONFIG 6 5 and CONFIG2 pins The following trace modes are supported Normal mode with 4 or 8 data bit width Transmission mode Full rate mode at 50 or 100 MHz CPU core clock frequency Half rate mode at 150 MHz CPU core clock frequency The ETM9 embedded trace macrocell is available in different complexity levels ERTEC 200 has the medium complexity version of the ETM9 implemented Thus the ETMO provides the following features 4 address comparator pairs 2data comparators with filter function 4 direct trigger inputs one of which can be connected via GPIO16 if the alternative function ETMEXTIN1 has been selected 1 trigger output that is also available at GPIO12 for external purposes if the alternative function ETMEXOUT has been selected 8 memory map decoders for decoding the physical address area of ERTEC 200 1 e 2 counters Supplemental to the ETM specification 8 memory map decode regions been decoded out via hardware these regions are summarized in Table 21 1 Table 21 1
96. tolerance 8 88 P 2 1 TxP rn 1 E i Em P 2 1 TxN e NN 2 mum ioc l 500 4 m 750 500 AGND 500 5 e e ERTEC 200 c o l See Table 16 141 RJ45 g g s P 2 1 RxN 4 ues 3 Em 2 1 e E t 6 EXTRES 500 7 x 75 0 500 d AGND 50 Q a 10 2 M salis Case GND Preliminary User s Manual A17988EE1V1UM00 237 Chapter 16 Multiport Ethernet PHY Figure 16 24 10BASE T and 100BASE TX Interface Circuit Example 2 Unmarked resistors 1 16 W and 1 tolerance Resistors marked with 1 8 W and 1 tolerance 2 1 2 1 ET i I 50 e AGND 1 1 1 1 lo fo 1 16 141 200 s P 2 1 RxN 4 i 1 2 1 e t t EXTRES 750 9 AGND e 10 2 MI gt Case GND AGND Table 16 14 shows some alternatives for the magnetics used in the previous circuits Table 16 14 Examples for Magnetics Selection Manufacturer Remarks Pulse Engineering single channel 0 70 C operating temperature Pulse Engineering HX1188 single channel 40 85 C operating temperature Pulse Engineering H1270 du
97. work in remote loopback mode Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY 5 Power Down Modes a Hardware power down This state is entered after a hardware reset of ERTEC 200 The PHYs are switched off and their power consumption is almost 0 W This state is left by setting the 1 2 ENB bits in the PHY_CONFIG register All analog and digital blocks in the PHYs are initialized and the pre defined configuration the PHY CONFIG register is copied to the PHYs Then the PHY internal registers can be configured as well Setting the 1 2 bits extends the internal reset signal in the PHYs to 5 2 ms in order to stabilize the PLL and all analog and digital blocks When the PHYs are ready to operate this is automatically indicated in the PHY_STATUS registers with the P1 2_PWRUPRST bits set to 1 b Software power down This state is entered by writing a 15 into the PowerDown bit of the Basic Control register of the PHYs The affected PHY will then go into a low power state where the MDIO interface is still active but where no activity is possible on the MII interface The power consumption of the PHYs in low power state is around 15 mW per PHY The low power mode is left by writing a 0 into the PowerDown bit The digital parts of the circuitry are re initialised however the start up configuration that is stored in the PHY CONFIG register is not copied again into the PHYs and
98. 0 Individual masking of fast interrupt inputs Bit 0 corresponds to FIQO etc MASK FIQ MASKREGn n O 7 Masking of fast interrupt inputs REG Fast interrupt request FIQn enabled Fast interrupt request FIQn masked initial value Preliminary User s Manual A17988EE1V1UMO0 103 Chapter 8 Interrupt Controller Figure 8 16 IRREG IRQ Interrupt Request Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 0058H 0000 01xxH 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 IRREG Bit position Bit name Function 31 16 Reserved IRREG 15 0 Individual indication of IRQ interrupt requests that have been recognized by the ICU Bit 0 corresponds to IRQO etc IRREGn n 0 15 Recognition of IRQ interrupt request Interrupt request IRQn not recognized by ICU Interrupt request IRQn has been recognized by ICU The initial value of 0000 01xxH for this register is caused by GPIO 31 30 and GPIO 1 0 that are by default configured as interrupt inputs with internal pull up resistors and that can though be pulled down externally Thus IRQ requests that are masked due to the default setting of the MASKALL register may automati cally be generated during reset Figure 8 17 MASKREG IRQ Interrupt Mask Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MASKREG Bit position Bit name Funct
99. 0 00 Chapter 12 Asynchronous Serial Interface UART Figure 12 9 UARTIIR UARTICR Register 7 6 5 4 Address Initial value 3 2 1 0 Bit position Bit name Function Reserved undefined when read RTIS Receive timeout interrupt status bit indicates if a receive timeout interrupt was generated within the UART and if the internal UARTRTINTRN signal is active RTIS Receive timeout interrupt status bit Receive timeout interrupt did not occur initial value Receive timeout interrupt occurred TIS Transmit interrupt status bit indicates if a transmit interrupt was generated within the UART and if the internal UARTTXINTRNote signal is active Transmit interrupt status bit Transmit interrupt did not occur initial value Transmit interrupt occurred RIS Receive interrupt status bit indicates if a receive interrupt was generated within the UART and if the internal UARTRXINTRNete signal is active Receive interrupt status bit Receive interrupt did not occur initial value Receive interrupt occurred MIS Modem interrupt status bit indicates if a modem interrupt was generated within the UART and if the internal UARTMSINTRNete signal is active Modem interrupt status bit Modem interrupt did not occur initial value Modem interrupt occurred MIS bit is cleared when a write access with any value is performed to this register Note These are internal interrupt signa
100. 0 N X X LBU_RDY_N I X i LBU_D 15 0 Preliminary Users Manual A17988EE1V1UMO00 117 Chapter 9 Local Bus Unit LBU Figure 9 5 LBU Write to ERTEC 400 with Common Read Write Control Line LBU CS R N LBU CS M N LBU WR N LBU A 20 0y LBU SEG 1 0 Valid address LBU BE 1 0 N TI 1 f n LBU_D 15 0 Valid data Preliminary User s Manual 17988 1 10 00 Chapter 9 Local Bus Unit LBU 9 6 Host Interrupt Handling ERTEC 200 is a pure slave with respect to the LBU interface In order to be able to issue requests to an external host ERTEC 200 can generate the two interrupt signals LBU_IRQ 1 0 _N Both interrupts are generated in the IRT switch and by default configured as active low However this configuration can be changed in the IRT switch A mailbox communication going via the IRT switch is possible between the ARM946E S core and the external host processor An interrupt request from the ARM946E S processor to the external host is triggered by writing to the Activate_HP_Interrupt register An interrupt request from the external host to the ARM946E S processor is triggered by writing to the Activate_SP_Interrupt register Both registers are only writeable the written value does not matter 9 7 Address Assignment of LBU Registers The LBU registers are 16 bit wide the registers can be written to with 16 bit accesses only The LBU page configuration registers are addressed via the
101. 000 0000H Externalmemory 7000 OOOOH 7000 003FH 64 Bytes interface register 7FFF FFFFH peony es Not used 8000 0000H EUM 8000 0000H 8000 000 y 8FFF FFFFH AMENE Not used 9000 0000H Not used FFFF FFFFH 1 75 GBytes Not used Preliminary User s Manual A17988EE1V1UM00 61 Chapter 5 ERTEC 200 Memory MEMO 62 Preliminary User s Manual 17988 1 10 00 Chapter6 External Memory Interface EMIF In order to access external memory areas an External Memory Interface EMIF is incorporated in ERTEC 200 The interface contains an SDRAM memory controller for standard SDRAM and an SRAM memory controller for asynchronous memories and peripherals Both interfaces can be configured separately as active interfaces That is the data bus is driven actively to high level at the end of each access The internal pull up resistors keep the data bus actively at high level external pull up resistors are not required When writing this occurs after the end of the strobe phase When reading this occurs after a specified time has elapsed after the end of the strobe phase to avoid driving against the externally read block For the SDRAM controller this time is equivalent to one AHB bus cycle For the asynchronous controller the time is equivalent to the time required for the hold phase to elapse which corresponds to the time from the rising edge of to the rising edge of the chip select sign
102. 1 2 enne enne nre ens 143 UARTEGR M Register Qe di De eroe 144 UARTEGR E Register 1 aire ber Pere Pee ba ebd e 145 UARTCR Register 1 2 irisi inen 145 UARTER Register 1 2 ott atin ican iet iier ete tetti iride 147 UARTIIR UARTICR Register 149 Block Diagram of SPI1 Interface sse 152 SSPCRO SPI1 Control Register 0 1 2 154 SSPCR1 SPI1 Control Register 1 1 2 156 SSPDR Rx Tx FIFO Data Register sse 157 SSPSR SPI11 Status Register sse eene nnne 158 SSPCPSR SPI1 Clock Prescale Register 159 SSPIIR SSPICR SPI1 Interrupt Identification and Clear Register 159 Connection of Serial Flash Memory to ERTEC 200 SPI Interface 160 Simplified Block Diagram of Timers 0 and 1 sse 161 Control Status Register 0 STATO 1 7 163 Control Status Register 1 CTRL_STAT1 1 7 165 Reload Register for Timer 0 RELDO 167 Reload Register for Timer 1 RELD1 167 Control Register for Prescaler 0 and 1 CTRL_PREDIV 1 2 168 Reload Register for Prescaler 0 and 1 RELD PREDIV
103. 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 00xxH 0000 000FH 15 14 13 12 11 10 9 8 4 3 2 1 0 Bit position Bit name Function Reserved PRIOREGO i15 PRIOREGO 15 3 0 Specifies priority for individual IRQ interrupt requests PRIOREGO corresponds to IRQO etc It is not allowed to assign equal priorities to more than one IRQ interrupt request PRIOREGn 3 0 IRQn interrupt request priority Assigns priority 0 highest to IRQ interrupt Assigns priority 15 lowest to IRQ interrupt IRQn initial value Preliminary User s Manual A17988EE1V1UMO0 107 MEMO 108 Preliminary User s Manual 17988 1 10 00 Chapter 9 Local Bus Unit LBU ERTEC 200 can be operated from an external host processor via a local bus interface The local bus interface is selected using the CONFIG2 input pin CONFIG2 0 LBU bus system is active CONFIG2 1 LBU bus system is inactive alternative functions like MII diagnosis ETM trace and GPIOs be used instead The LBU interface uses a 16 bit data bus and a 21 bit address bus The externally connected uC is always the master with respect to this interface All registers of the LBU are 16 bits wide write accesses to these registers must be 16 bit wide Table 9 1 Local Bus Interface Pin Functions Pin Name Function Number of pins LBU_A 20 0 LBU address bits LBU_D 15 0 LBU data bits LBU_WR_N LBU wr
104. 16 Multiport Ethernet PHY Figure 16 12 Auto Negotiation Link Partner Ability Register Next Page 2 2 Bit position 10 1 Bit name Message Unformatted Code field Function Toggle Indicates if the toggle bit of the previous page equalled 0 or 1 this function is used by the next page arbitration protocol Toggle Toggle bit indication Toggle bit in the previously transmitted link code word has been 1p initial value Toggle bit in the previously transmitted link code word has been Op Message Unformatted Code field R a message or unformatted 11 bit code word from the link partner depending on the setting of the Message Page bit Preliminary Users Manual A17988EE1V1UMO00 221 Chapter 16 Multiport Ethernet PHY Figure 16 13 Auto Negotiation Expansion Register 15 14 13 12 11 10 9 8 No Initial value Reserved 6 0000H Parallel Link Partner Link Partner Reserved Detection Next Page NextPage Page Auto Negotia Fault Able Able tiny Able Bit position Bit name Function Reserved Reserved Ignore on read access Parallel Detection Fault Indicates if a fault occured during parallel detection Parallel Parallel Detection Fault Parallel detection fault indication E No fault has occured during parallel detection ini tial value A fault has occured during parallel detection Link Partner Next Page Able Indicates if the link pa
105. 17988EE1V1UMO0 99 Chapter 8 Interrupt Controller Figure 8 8 IRCLVEC IRQ Interrupt Request Clear Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 001CH undefined 15 14 13 12 11 10 9 8 3 0 Bit position Bit name Function Reserved IRCLVEC 3 0 Writing an IRQ interrupt vector number to these bits clears the respective request the interrupt request register IRREG IRCLVEC IRCLVEC 3 0 IRQ Interrupt vector number to be cleared clears IRQO in interrupt request register IRREG clears IRQ15 in interrupt request register IRREG Figure 8 9 MASKALL Mask All IRQ Interrupt Request Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 reserved MAS KALL Bit position Bit name Function Reserved MASKALL Masks all pending IRQ interrupt requests independent of their individual mask bit setting in MASKREG register MASKALL IRQ interrupt request masking MASKALL Enable all IRQ interrupt requests that are not individually masked in MASKREG Mask all IRQ interrupt requests independent of their individual mask bit setting in MASKREG register ini tial value 100 Preliminary User s Manual 17988 1 10 00 Chapter8 Interrupt Controller Figure 8 10 IRQEND End of IRQ Interrupt Signaling Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value do
106. 2 0033H REGSOUIIN 15 0 Default value for SMII register 3 2001H Preliminary User s Manual A17988EE1V1UMO0 207 Chapter 16 Multiport Ethernet PHY Figure 16 6 Basic Control Register 1 2 15 14 13 12 11 10 9 8 Initial value Restart Isolate Auto 0 xxxxHNote Negotiation Speed Power selection Down 7 6 5 4 3 2 1 0 Collision Test Reserved Note The initial value depends on the setting of the P 2 1 PHY MODE 2 0 bits in the PHY1 2 Con figuration Register in the System Control Register block Bit position Bit name Function Reset Resets the complete PHY o Normal operation initial value Execute a software reset for the affected PHY Note This bit is self clearing it is automatically set to 0 by the reset pro cess Loopback Controls internal loopback mode Loopback Internal loopback mode L k m oopbac eu x Disable internal loopback mode initial value Enable internal loopback mode Speed selection Selects either 10 or 100Mbps transmission speed the setting of this bit is irrelevant if auto negotiation is enabled Speed selection Speed selection function Speed Select 10Mbps mode initial value after device selection reset Select 100Mbps mode Note The initial value after only the PHY has been reset is selected by the contents of the PHY MODE field in the PHY CONFIG register Auto Negotiation Enable Controls the auto negotiation pr
107. 2 14 44 Preliminary User s Manual 17988 1 10 00 2 Pin Functions 2 3 Pin Status and Drive Characteristics Table 2 15 Pin Status During Reset and Recommended Connections 1 2 Pin Name oote 1 Internal pull up down 50 kQ pull up during reset Note 1 Level during reset External pull up down required oNote 1 50 kQ pull down Note 1 pNote 1 pNote 1 50 kQ pull up 50 kO pull down Note 1 Note 1 pNote 1 50 kQ pull up Note 1 oNote 1 50 KQ pull down Note 1 50 kQ pull up CLK_SDRAM CS_SDRAM_N RAS_SDRAM_N CAS_SDRAM_N WE_SDRAM_N CS_PER 3 0 _N BE 3 0 _DQM 3 0 _N Oi O O O 0l OC ojojo RDY_PER_N 50 kQ pull up H DTR_N yONete1 50 kQpull up Note 1 Note 1 OE_DRIVER_N ETMEXTOUTNete 2 50 kQ pull up Note 7 ETMEXTIN1Note 2 50 kQ pull up TRACEPKT 7 0 Note 2 50 kQ pull up Note 7 PIPESTA 2 0 Note 2 GPIO 44 32 Note 2 50 kQ pull up 50 kQ pull up Note 7 GPIO 31 30 Nete 2 50 kQ pull up GPIO 28 8 Nete 2 50 KQ pull up 50 KQ pull up GPIO 29 27 Note 2 GPIO 7 0 Note 2 50 kQ pull up ae 20 a ae a es CLKP_A CLKP_B TRACECLK F_CLK REF_CLK tri stateNote 3 RESET_N 50 kQ pull up TRST_N TCKNote 6
108. 2 bit 1 Receive data port 2 bit 0 LBU_A9 TRACEPKTO LBU_A8 TRACEPKT1 2 Transmit enable port 2 LBU_D10 CRS_P2 Carrier sense port 2 LBU_A12 RX_ER_P2 Receive error port 2 PIPESTAO TX_ERR P2 Transmit error port 2 LBU D11 RX DV P2 COL P2 Receive data valid port 2 Collision port 2 LBU A14 LBU A15 RX CLK P2 Receive clock port 2 LBU BE1 N TX CLK P2 TXD P1 3 0 Transmit clock port 2 Transmit data port 1 bits LBU RD N LBU D 3 0 RXD P13 Receive data port 1 bit 3 AS TRACEPKT6 RXD P12 RXD P11 Receive data port 1 bit 2 Receive data port 1 bit 1 LBU_A2 TRACEPKT7 LBU A1 ETMEXTIN1 RXD P10 Receive data port 1 bit 0 AO ETMEXTOUT TX EN P1 CRS P1 Transmit enable port 1 Carrier sense port 1 LBU D4 LBU A4 TRACEPKT5 ER P1 Receive error port 1 LBU_A5 TRACEPKT4 TX ERR P1 RX DV P1 CO O Transmit error port 1 Receive data valid port 1 LBU D5 LBU_A6 TRACEPKT3 COL P1 RX CLK P1 TX CLK P1 Collision port 1 Receive clock port 1 Transmit clock port 1 LBU_A7 TRACEPKT2 LBU_BEO_N LBU_WR_N Note MII diagnosis interface pins are alternatively used as local bus interface or trace pins in this table the I O type is listed for the MII diagnosis function 2 SMI Interface The serial management int
109. 4000 2200H 0000H Bit position Bit name Function SCR 7 0 Selects serial transmission speed for master mode The value that has been programmed in this field determines transmission speed via the following formula 2 S0MH 0 SCLKOUT CPSDVSR x 14 SCR SPH Selects phase of transmitted bits This bit is only applicable to Motorola SPI frame format Serial transmission phase Received MSB is expected immediately after frame signal goes low initial value Received MSB is expected half a clock period after frame signal goes low SPO Selects serial clock output polarity This bit is only applicable to Motorola SPI frame format Serial clock output polarity Received bits are latched on the rising edge of SCLKIN OUT outgoing bits are switched on the falling edge of SCLKIN OUT initial value Received bits are latched on the falling edge of SCLKIN OUT outgoing bits are switched on the rising edge of SCLKIN OUT FRF 1 0 Selects one of the possible operation modes Frame format Motorola SPI frame format initial value TI synchronous serial frame format National Microwire frame format Reserved 154 Preliminary User s Manual 17988 1 10 00 Bit position Bit name Chapter 13 Synchronous Serial Interface SPI1 Figure 13 2 SSPCRO 5 Control Register 0 2 2 DSS 3 0 DSS 3 0 Function Selects data word size for serial transmission reception Da
110. 7988 1 10 00 Chapter 12 Asynchronous Serial Interface UART The following Table 12 2 shows the baud rate values to be set and the deviations from the standard baud rates The associated error percentages are within the baud rate tolerance range Table 12 2 Baud Rates and Tolerances for 50 MHz UART Operation Clock BAUDDIV 115200 115740 0 47 76800 76219 0 76 57600 57870 0 47 38400 38580 0 47 19200 19171 0 15 14400 14400 9 0 006 9600 9585 9 0 15 2400 2400 15 0 006 1200 1200 077 0 006 110 110 0004 0 0003 The UART can also be used as a BOOT medium if for example functions from an external PC are to be loaded to ERTEC 200 and executed The BOOT medium is selected by the BOOT 3 0 inputs during the active reset phase see section 10 3 The BOOT loader then takes over setting of the UART signal pins and loading of the program code The Boot strap loader functionality is also used If the UART is not utilized as boot source or for normal communication it can also be used as a debugging interface Preliminary User s Manual A17988EE1V1UMO00 139 Chapter 12 Asynchronous Serial Interface UART 12 1 Address Assignment of UART Registers The UART registers are 8 bits in width When they are accessed with 16 or 32 bit read operations the upper bits are undefined The following Table 12 3 gives an overview of the address assignment for the UART registers Table 12 3 Address Assignment
111. 7988EE1V1UM00 125 Chapter 11 General Purpose I O GPIO The following Figure 11 1 shows the structure of a GPIO pin as a standard I O function or as an alternative function Figure 11 1 GPIO Cells of ERTEC 200 for GPIO 31 0 8 amp j Alternate input function 1 2 if available GPIO_INn GPIO_OUTn Alternate output function 1 2 3 if available GPIOn GPIO PORT MODE L H 2n 1 2n GPIO IOCTRLn GPIO 44 32 are shared with the LBU interface and are only available if the LBU interface is not used This is configured using the CONFIG2 pin that is tested during the active reset phase CONFIG2 0 Use LBU interface CONFIG2 1 Use GPIO 45 32 If CONFIG2 was 1 during the active reset phase GPIO 44 32 can be used as normal inputs or out puts I O direction can be programmed bit wise using the GPIO IOCTRL2 register 126 Preliminary User s Manual A17988EE1V1UMO00 Chapter 11 General Purpose I O GPIO 11 1 Address Assignment of GPIO Registers The GPIO registers are 32 bits wide However the registers can be read or written to with 8 bit 16 bit or 32 bit accesses In case of accesses with less than 32 bits note that the ERTEC 200 memory organization is Little Endian Table 11 2 Address Assignment of GPIO Registers Address Register Name Initial value Description Configuration register for GPIO 31 0 4000 2504H GPIO OUT 0000 0000H Data output register for GP
112. 8 1 10 00 Chapter 17 System Control Registers Figure 17 16 ERTEC 200 TAG Identification Register ERTEC200_TAG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value REVISION ID 4000 2659H 0001 0118H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VERSION ID DEBUG ID Bit position Bit name Function Reserved REVISION ID REVISION ID 7 0 Reflects the revision ID of the current ERTEC switching state 01H VERSION ID VERSION 7 0 Reflects the version ID of the current ERTEC switching state 01H DEBUG 1 DEBUG 7 0 Reflects the debug ID of the current ERTEC switching state 18H Preliminary User s Manual A17988EE1V1UMO0 255 Chapter 17 System Control Registers Figure 17 17 PHY1 2 Configuration Register PHY_CONFIG 1 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 265CH 0000 0000H 4 3 2 1 0 1_ _ E m MODE ope lens XEN Bit position Bit name Function 31 17 Reserved PHY RES SEL Selects reset source for PHY1 and PHY2 like the IRT switch initial value DENN PHYs are reset with the internal IRT output reset phy n Nete Reserved P2 AUTOMDIXEN Enables AutoMDIX state machine for PHY2 P2 AUTOMDIXEN AutoMDIX enable Disable AutoMDIX state machine for PHY2 initial value Enable AutoMDIX state machine for PHY2 P2 AUTOMDIXEN Note If CONFIG 6 5
113. ARMGQE S Rev 1 Technical Reference Manual DDIO0165BNote ARM AMBA Specification Rev 2 0 IH10011 ANote ARM PrimeCell UART 1 010 Technical Reference Manual DDIO139BNote ARM PrimeCell Synchronous Serial Port PLO21 Technical Refer DDIO171BNete ence Manual ARM Embedded Trace Macrocell Architecture Specification 0014 0 ARM Multi ICE System Design Considerations Application Note 72 DAIO072ANete Note These documents are available from ARM Limited www arm com 6 Preliminary User s Manual 17988 1 10 00 Chapter 1 2 1 2 2 2 3 Chapter 3 Chapter 4 4 1 4 2 Chapter 5 5 1 5 2 5 3 Chapter 6 Chapter 7 7 1 7 2 Chapter 8 ak Table of Contents Introduction 2 22 ke I RR RR EE REFS 17 General 22 7 1 BE cu 17 Device Features 21 19 Ordering Information 21 Pin Configuration sses dna be eee hee rr rur ER ee 22 Pin Identification 1 2 clle R xe RR 27 Configuration of Functional 29 6 1 Block Diagram of ERTEC 200 29 6 2 On chip Units iae tenes a ANA e RUE LR ERUIT ene 30 Pin Functions 2 a Ee He eet gn RR xr RR 33 List of PinF nctiohns
114. ASE TX transmitter The PLL generates multiple phases of the 125 MHz clock A multiplexer controlled by the timing unit of the DSP block selects the optimum phase for sampling the data This is used as the recovered receive clock which is then used to extract the serial data from the received signal 2 Adaptive equalizer The adaptive equalizer compensates phase and amplitude distortion caused by the physical transmis sion channel consisting of magnetics connectors and CAT 5 cable Thus the supported cable length is increased 3 Baseline wander correction If the DC content of the signal is such that the low frequency components fall below the low frequency pole of the isolation transformer then the droop characteristics of the transformer will become signifi cant and baseline wander BLW on the received signal will result To prevent corruption of the received data the PHY corrects the baseline wander effects using DSP algorithms 4 4B 5B encoding decoding In 100BASE TX mode 4B 5B coding is used The 4B 5B encoder converts 4 bit nibbles coming from the interface to 5 bit symbols that are referred to as code groups The relation between original and encoded data is shown in Table 16 2 For testing purposes the encoder and decoder can be bypassed with the Enable 4B5B bit in the PHY special control status register In this case the 5th bit of the output pattern reflects the current level of the TX ERR P 2 1 signal of the M
115. BBBSB8EBSEPEZSEZ ys Zo T x ae z z 22 se Sus RS 2423 88 9 992995 82z2kz Bese 88 amp lt ENS pm ppm pm po po p d p pem SIS S RIS TESTES SISISIR ES BEBRBzS ELBSOoLOPIOSLPORLHEEZERERSE zzz 88883838588382538583855852888888888888 222 g 8 aus ae oS 98 eo zzz zo rM ie ART I z5asd3 5155 2 228 5 25 22 zoas 5585 42590 8695828 CN dg sg gnis 2 252 2 82 2 22 22 2 25 22 2 2 oSeSsS ce pop poo ee p pm p o 8 76 Preliminary User s Manual 17988 1 10 00 Chapter6 External Memory Interface EMIF 6 5 Hints for Setting the EMIF Registers For proper operation of an SDRAM in conjunction with ERTEC 200 the bits BURST LENGTH 1 0 and SDSIZE must be set carefully The bits must be set before the Mode Register Set command is issued to the SDRAM otherwise the new settings are not transferred The Mode Register Set command is triggered by writing to the SDRAM_Bank_Config register while the INIT DONE bit bit 29 in the SDRAM Refresh Control register is 1p Possible settings f
116. CK Preliminary User s Manual 17988 1 10 00 Connection of Serial Flash Memory to ERTEC 200 SPI Interface Chapter 14 200 Timers ERTEC 200 has two types of timers integrated Timer 0 and Timer 1 are two almost identical but cascadable timers that work with an internal clock Timer 2 is a self contained block but also working from an internal clock Timer F however works from an external clock source All timers can interrupt the processor 14 1 Timer 0 and Timer 1 Timer 0 and Timer 1 are two independent timers integrated in ERTEC 200 They can be used for inter nal monitoring of diverse software routines Each timer has an interrupt output that is connected to the IRQ interrupt controller of the ARM946E S CPU Access to the timer registers is always 32 bits in width Both timers have the following functionality 32 bit count register Input clock can be switched to 50 MHz clock default setting 8 bit prescaler per timer can be assigned separately Down counting Load reload function Start stop and continue functions Interrupt when counter state 0 is reached Count register can be read write accessed Figure 14 1 shows a simplified block diagram of Timers 0 and 1 Figure 14 1 Simplified Block Diagram of Timers 0 and 1 LK 50 Prescaler 0 D Timer 0 IRQO Timer 1 IRQ1 Control Status Preliminary User s Manual A17988EE1V1UMO00 161 Chapter 14
117. E S Processor ERTEC 200 uses an ARM946E S processor with configurable clock frequencies of 50 100 or 150 MHz This processor however is based on the ARM9E S core that supports the ARM5vTE instruction set architecture with 32 bit wide normal instructions and the 16 bit wide THUMB instruction set It includes support for separate instruction and data caches as well as tightly coupled memory In case of ERTEC 200 8 kBytes of instruction cache I cache and 4 kBytes of data cache D cache are available The tightly coupled memory TCM has a size of 4 kBytes and can be accessed with full CPU speed An integrated memory protection unit MPU allows to restrict access permission to eight program mable portions of the ERTEC 200 address space The processor core is extended with two on chip interrupt controllers one of which is connected to the core s FIQ input while the other one is connected to the IRQ input The IRQ interrupt controller handles up to 16 interrupt sources that can be prioritized the FIQ interrupt controller can handle up to 8 sources Most interrupt sources are assigned to internal peripheral units however GPIO pins can be used as interrupt sources as well For easy debugging ERTEC 200 is equipped with an ETM9 debug and trace module In addition to the on chip debug capabilities of the ARM946E S core the ETM9 module allows instruction and data trace The ETM cell can be operated in full rate mode as long as the CPU core frequency
118. E TX Half Duplex 100BASE TX half duplex ability indication fm 100BASE TX half duplex ability 100BASE TX half duplex supported initial value 10Mb s Full Duplex 10Mb s Full Duplex Indicates ability to support 10Mb s full duplex mode 10Mb s Full Duplex 10Mb s full duplex ability indication 10Mb s full duplex ability 10Mb s full duplex supported initial value 210 10Mb s Half Duplex 10Mb s Half Duplex Indicates ability to support 10Mb s half duplex mode 10Mb s half duplex ability 10Mb s half duplex supported initial value Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Figure 16 7 Basic Status Register 2 3 Bit position Bit name R W Function Reserved Auto Negotiation Complete Indicates if auto negotiation process has been completed Auto Auto Negotiation Complete Negotiation Auto negotiation completion indication Complete Auto negotiation has not been completed initial value Auto negotiation has been completed Remote Fault Indicates if a remote fault has been detected Remote Fault Remote fault detection indication No remote fault condition has been detected initial value Remote fault condition has been detected Note This bit is cleared when it has been read Auto Negotiation Ability Indicates ability to perform auto negotiation Auto Negotiation Ability Unable to perform auto negotiation
119. EN nation that can be specified in the DMACO CONF REG register in number SION of 50 MHz clocks The resulting delay is given by addition of the parameters D DELAY and D DELAY EXTENSION S DELAY EXTENSION 4 0 S DELAY Extends the 5 DELAY delay between two read accesses from the DMA EXTEN source that can be specified in the DMACO CONF REGi register in number SION of 50 MHz clocks The resulting delay is given by addition of the parameters S DELAY and S DELAY EXTENSION BYTE COUNT 15 0 BYTE_ Number of bytes to be transferred via DMA The byte count must be aligned COUNT with the configured bus width that is if a 32 bit transfer width is set for the tar get or source only one 4 byte aligned byte count can be used 82 Preliminary User s Manual 17988 1 10 00 Chapter 7 DMA Coniroller Figure 7 4 DMACO CONF REG DMA Configuration Register 1 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Address Initial value INTR res Ena SYCHRONI 9 DMA S WIDTH 8000000CH 00000000H MODE 14 D ADDR MODE D DMA REQ D WIDTH D DELAY S DELAY Bit position Bit name Function START ABORT Starts or stops the DMA transfer START ABORT START EE ABORT Write stops the DMA transfer Read DMA transfer completed or stopped initial value Write starts the DMA transfer Read DMA transfer ongoing Note 1 DMA transfer start stop Reserved INTR ENABLE
120. ESTA 2 0 CPU pipeline status TRACESYNC Trace sync signal TRACECLK ETM trace or scan clock TRACEPKT 7 0 Trace packet bits total All these signals except TRACECLK are alternative signal pins at the LBU interface The trace interface can be configured to a data width of 4 bits or 8 bits in the debugger If a data width of 4 bits is selected the TRACEPKT 3 0 signals are automatically switched to the trace function If a data width of 8 bits is assigned the TRACEPKT 7 4 signals are also switched to the trace function For connectors pinning and hardware circuitry for the trace interface please consult the additional documents listed on page 6 274 Preliminary User s Manual 17988 1 10 00 Chapter 21 Test and Debugging 21 4 JTAG Interface ERTEC 200 has a serial debug interface that conforms to the JTAG standard If this interface is made accessible in a system it can be used for the connection of hardware debuggers from different manu facturers Table 21 3 summarizes the debug interface pins Table 21 3 JTAG and Debug Interface Pin Functions Pin Name VoNote Function Number of pins TRST_N JTAG reset signal JTAG clock signal JTAG data input signal JTAG test mode select signal TDO JTAG data output signal DBGREQ Debug request signal DBGACK Debug acknowledge signal TAP_SEL TAP controller select signal Besides the debug function the JTAG interface is also used for the bounda
121. FF FFFFH 5000 0000H 5FFF FFFFH 8 Bytes physicalNote 1 ARM interrupt controller 128 Bytes physicalNote 1 Reserved 58 256 MBytes 6000 0000H 6FFF FFFFH Preliminary User s Manual 17988 1 10 00 Segment Chapter 5 ERTEC 200 Memory Table 5 2 Detailed Description of Memory Segments 2 2 Contents Address range Comment External memory Control registers for external memory interface register 256 MBytes 7000 0000H 7FFF FFFFH interface 64 Bytes physicalNete 1 Notes 1 2 Control registers for DMA 16 Bytes DMA controll 256 MByt 8000 0000H 8FFF FFFFH controler ytes ohysicalNote j Not used 1 75 GBytes 9000 0000H FFFF FFFFH Memories respectively register sets are mirrored over the complete partial segment size the address distance of the mirrored blocks corresponds to an integer power of two that is greater or equal to the physically implemented size For example for the watchdog timers 28 Bytes are physically implemented The next higher power of two is 32 Bytes and thus the watchdog registers are mirrored every 32 Bytes over a 256 Byte range Accesses to the gaps in this address area do not activate the bus monitoring circuitry that is described in section 20 1 read and write accesses to these addresses result in undefined data IRT registers and Communication SRAM may only be accessed at the first 2 MBytes of memory segment 1 Access
122. FFFH 3000 0000H 30FF FFFFH Comment After reset Boot ROM 8 kBytes physical Note 1 After memory swap using MEM SWAP register Internal SRAM 8 kBytes physical Nete 1 1000 0000H 100F FFFFH for registersNete 2 Bank 1 16 MBytes 3100 0000H 31FF FFFFH Bank 2 Bank Not used 16 MBytes 16 MBytes 192 MBytes 3200 0000H 32FF FFFFH 3300 0000H 33FF FFFFH 3400 0000H 3FFF FFFFH 1010 0000H 1010 FFFFH for Communication SRAM 64 kBytes physical Note 2 Maximum 128 MBytes Smaller external memories are mir rored over the entire range Smaller external memory ranges are mirrored over the entire 16 MByte range Internal boot ROM 8 kBytes 4000 0000H 4000 1FFFH 8 kBytes physical Timers 256 Bytes 4000 2000H 4000 20FFH 32 Bytes physicalNote 1 Watchdog 256 Bytes 4000 2100H 4000 21FFH 28 Bytes physicalNote 1 SPI 256 Bytes 4000 2200H 4000 22FFH 256 Bytes physical UART 256 Bytes 4000 2300H 4000 23FFH 256 Bytes physical Reserved 256 Bytes 4000 2400H 4000 24FFH 256 Bytes physical GPIO System Control Registers 256 Bytes 256 Bytes 4000 2500H 4000 25FFH 4000 2600H 4000 26FFH 32 Bytes physicalNote 1 164 Bytes physical General register blockNete 1 F Counter Not used Interrupt controller 256 Bytes 256 MBytes 4000 2700H 4000 27FFH 4000 2800H 4F
123. ICE logic this allows single step debugging from the reset address onwards As with the RESET input a 5 ns anti spike filter is implemented at the SRST_N input After a hardware reset with SRST 200 will boot in the same mode that was stored during the last PowerOn reset PowerOn as well as hardware reset set the HW RESET bit in the RES STAT REG register This register can be evaluated after restart of the processor 19 3 Watchdog Reset The watchdog reset involves software monitoring with hardware support The monitoring process is based on a time set in the watchdog timer reload registers The time starts with activation of the watch dog timer Re triggering and thus reloading the timer with a specified reload value prevents the watch dog reset from being triggered If the timer is not re triggered the watchdog reset is activated after the timer expires if the watchdog function is enabled with the WD RES FREI bit in the reset control regis ter RES CTRL REG As the reset pulse that is generated by the watchdog is too short the watchdog reset is extended in ERTEC 200 by means of a programmable pulse stretching PV The maximum duration that can be programmed in the RES CTRL REG register is approximately 2 05 ms in case of a 50 MHz clock The watchdog reset resets the same circuitry as the hardware reset if the EN WD SOFT RES bit is set in the RES CTRL REG Otherwise the IRT switch is not affected by the
124. II interface Preliminary User s Manual A17988EE1V1UMO0 189 Code group Table 16 2 4B 5B Code Table Transmitter Receiver from MAC via MII Interpretation Interpretation to MAC via MII olol gt olon oj 1111 Data F Sent after T and R end of stream until TX_EN_P 2 1 is asserted again Idle Sent when TX_EN_P 2 1 is asserted 13 nibble of start of stream data SSD translates to 0101 if received after idle otherwise RX ERR P 2 1 is asserted Sent after J 274 nibble of SSD translates to 0101 if received after J otherwise RX ERR P 2 1 is asserted Sent when TX EN P 2 1 is deas serted Sent after T 18 nibble of end of stream data ESD translates to 1010 and causes deassertion of CRS 2 1 when fol lowed by R otherwise RX ERR P 2 1 is asserted 23 nibble of ESD translates to 1010 and causes deassertion of CRS 2 1 when preceded by T otherwise RX ERR P 2 1 is asserted 00100 Sent when TX ERR P 2 1 is asserted Transmit error Undefined all others Invalid code Invalid code RX ERR P 2 1 is asserted if received while RX DV P 2 1 is active Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY 5 Scrambling Descrambling Scrambling the data before transmission helps to eliminate large narrow band signal power peaks for repeat
125. IO 31 0 4000 2508H GPIO IN xxxx xxxxHNote Data input register for GPIO 31 0 4000 250CH GPIO PORT MODE L 0000 0000H Function selection for GPIO 15 0 4000 2510H GPIO PORT MODE H 0000 0000H Function selection for GPIO 31 16 4000 2514H GPIO POLSEL 0000 0000H Polarity of GPIO interrupts Configuration register for GPIO 44 32 Data output register for GPIO 44 32 4000 2500H GPIO IOCTRL FFFF FFFFH 4000 2520H GPIO2 IOCTRL 0000 1FFFH 4000 2524H GPIO2 OUT 0000 0000H 4000 2528H GPIO2 IN 0000 xxxxHNote Data input register for GPIO 44 32 Note During reset all GPIO pins are configured as input port pins Thus the content of the GPIO IN register reflects the logical level of the GPIO 31 0 pins during reset Additionally the content of the GPIO2 IN register reflects the logical level of the GPIO 44 32 pins during reset if the LBU pins are configured as GPIOs with the CONFIG2 signal Remark Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary User s Manual A17988EE1V1UMO00 127 Chapter 11 General Purpose I O GPIO 11 2 Detailed GPIO Register Description Figure 11 2 GPIO IOCTRL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value GPIO IOCTRL 4000 2500H FFFF FFFFH 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 GPIO_IOCTRL Bit position Bit name Function GPIO_IOCTRL 31 0 Control
126. LBU CS R N signal Table 9 8 summarizes the implemented registers Table 9 8 Address Assignment of LBU Registers Address Register Name Initial value Description 00 0000H RG L LBU page 0 range register low 00 0002H PO LBU page 0 range register high 00 0004H PO OF L LBU page 0 offset register low 00 0006H LBU PO OF H LBU page 0 offset register high 00 0008H LBU PO CFG LBU page 0 configuration register 00 0010H LBU P1 LBU page 1 range register low 00 0012H LBU P1 RG H LBU page 1 range register high 00 0014H LBU P1 OF L LBU page 1 offset register low 00 0016H LBU P1 OF H LBU page 1 offset register high 00 0018H LBU P1 CFG LBU page 1 configuration register 00 0020H LBU P2 LBU page 2 range register low 00 0022H LBU P2 RG H LBU page 2 range register high 00 0024H LBU P2 OF L LBU page 2 offset register low 00 0026H LBU P2 OF H LBU page 2 offset register high 00 0028H LBU P2 CFG LBU page 2 configuration register 00 0030H LBU page range register low 00 0032H LBU_P3_RG_H LBU page 3 range register high 00 0034H LBU_P3_OF_L LBU page 3 offset register low 00 0036H LBU_P3_OF_H LBU page 3 offset register high 00 0038H LBU_P3_CFG LBU page 3 configuration register Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary User s Manual A17988EE1V1UMO00 119 9 8
127. LBU data bit 8 LBU data bit 7 LBU data bit 6 TXD P22 TXD P21 TXD P20 LBU D4 LBU data bit 5 LBU data bit 4 TX ERR P1 TX EN P1 LBU LBU data bit 3 TXD P13 LBU D2 LBU data bit 2 TXD P12 LBU D1 LBU data bit 1 TXD P11 LBU DO LBU data bit 0 TXD P10 LBU WR LBU RD N LBU BE 1 0 N LBU write control signal LBU read control signal LBU byte enable TX CLK P1 TX CLK P2 RX CLK P 2 1 LBU SEG 1 LBU SEG 0 LBU page selection signal LBU page selection signal GPIO38 7 LBU_IRQ_1_N LBU interrupt request signal GPIO44 LBU IRQ N 34 LBU interrupt request signal GPIO43 Preliminary User s Manual 17988 1 10 00 2 Pin Functions Table 2 2 Local Bus Interface Pin Functions 2 2 Pin Name Function Alternate FunctionNote LBU RDY N LBU ready signal GPIO42 LBU CS M N LBU chip select for ERTEC 200 internal resources GPIO40 LBU CS R N LBU chip select for page configuration registers GPIO39 Note Local bus interface pins are alternatively used as MII diagnosis trace or GPIO pins in this table the I O type is listed for the local bus function Preliminary User s Manual A17988EE1V1UMO0 35 Pin NameNote SMI MDC 2 Pin Functions Table 2 3 MII SMI Diagnosis Interface Pin Functions Function Serial management interface clock Alternate FunctionNote LBU D12 SMI MDIO Serial man
128. M9 4000 2658H 200 TAG 0001 0118 Tag number of current switching status 4000 265CH PHY_CONFIG 0000 0000H PHY1 2 configuration register 4000 2660H PHY_STATUS 0000 0000H PHY1 2 status register 4000 2670H UART_CLK 0000 0000H UART Clock selection Remark Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary User s Manual A17988EE1V1UM00 241 Chapter 17 System Control Registers 17 2 Detailed System Control Register Description Figure 17 1 Device Identification Register ID REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value ERTEC200 ID 4000 2600H 4027 0100H 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 HW RELEASE METAL FIX Bit position Bit name Function ERTEC200 ERTEC200 ID 15 0 ID Holds an ERTEC 200 identification pattern 4027H HW HW RELEASE 7 0 RELEASE Holds a number representing the HW release step currently 01H METAL FIX 7 0 Holds a number representing the metal fix step currently OOH Figure 17 2 Boot Mode Pin Register BOOT_REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 40002604H H 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 reserved BOOT Bit position Bit name Function Reserved BOOT 3 0 Reflect the logical level of the BOOT 3 0 pins during the active reset phase
129. MHz quartz to the A and B pins connect 25 MHz oscillator to the CLKP pin In order to reduce power consumption the PHYs can be driven to a power down mode either manually or automatically if there is no activity on the Ethernet line Preliminary User s Manual A17988EE1V1UM00 185 Chapter 16 Multiport Ethernet PHY The on chip PHYs of ERTEC 200 use the following pins Table 16 1 PHY Interface Pin Functions Pin Name 1 0 Function Number of pins Differential transmit data output Differential FX transmit data output Differential FX transmit data output Differential receive data input Differential receive data input Differential FX receive data input Differential FX receive data input Differential FX signal detect input m m MY MP NI N PM NIN Differential FX signal detect input External reference resistor 12 4 Note DVDD 4 1 Digital power supply 1 5 V DGND 4 1 Digital GND P 2 1 VSSATX 2 1 Analog port GND P 2 1 VDDARXTX Analog port RX TX power supply 1 5 V P 2 1 VSSARX Analog port GND VDDAPLL Analog central power supply 1 5 V P P A HR AP VDDACB Analog central power supply 3 3 V VSSAPLLCB Analog central GND VDD33ESD Analog test power supply 3 3 V VSS33ESD Analog test GND total Note that Table 16 1 includes the specific power supply pins that are needed for operation of the PHYs however it does n
130. N Indicates wheter energy is detected on the line If no respetively too little energy is detected for 256ms this bit automatically goes to Op ENERGYON Energy detected indication 0 No sufficient energy level detected initial value 1p Sufficient energy level detected Reserved Write O ignore on read access Preliminary Users Manual A17988EE1V1UMO00 227 Chapter 16 Multiport Ethernet PHY Figure 16 17 Special Mode Register 1 2 15 14 13 12 11 10 9 8 No Initial value 7 6 5 4 3 2 1 0 PHY MODE PHY_ADD Bit position Bit name Function MIIMODE Selects different interface types between PHY and MAC MIIMODE MIIMODE selecti MIIMODE ODE selection 00 interface initial value others Reserved Reserved Ignore on read access Reserved Write 0p ignore on read access FX MODE Enables the 100BASE FX mode FX MODE 100BASE TX mode enable FX MODE disabled initial value after hardware reset FX MODE FX MODE enabled Notes 1 The initial value after a software reset of the PHYs is selected by the contents of the FX MODE field in the PHY CONFIG reg ister When FX MODE is set to 15 the PHY MODE field must be set to either 011 or 010 A consistent setting of both fields is required otherwise proper operation of the PHYs cannot be guaranteed Reserved Write 0p ignore on read access 228 Preliminary User s Manual A17988EE1V1UMO00 Chapter 16 M
131. O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device All other product brand or trade names used in this publication are the trademarks or registered trademarks of their respective trademark owners Product specifications are subject to change without notice To ensure that you have the latest product data please contact your local NEC Electronics sales office 2 Preliminary User s Manual 17988 1 10 00 The information in this document is current as of August 2007 information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual prope
132. PIO25 GPIO24 PORT MODE PORT MODE PORT MODE PORT MODE PORT PORT MODE PORT MODE PORT MODE 14 11 10 15 18 12 9 8 lt 7 26 15 Bee 20 M 0 GPIO23 GPIO22_ GPIO21 GPIO20 GPIO19 GPIOI8 GPIO17_ GPIO16_ PORT MODE PORT MODE PORT MODE PORT MODE PORT PORT MODE PORT MODE PORT MODE 4000 2510H 0000 0000H Bit position Bit name Function GPIO31 PORT MODE 1 0 Selects one of max four different functions for GPIO31 GPIO31 PORT MODE GPIO31 function selection GPIO31 PORT 00 Select function 0 for GPIO31 initial value MODE 01 Select function 1 for pin GPIO31 if available 10 Select function 2 for GPIO31 if available 11 Select function for pin GPIO31 if available GPIO16 PORT MODE 1 0 Selects one of max four different functions for pin GPIO16 GPIO16 PORT MODE GPIO16 function selection GPIO16 PORT 00 Select function 0 for GPIO16 initial value MODE 01 Select function 1 for GPIO16 if available 10 Select function 2 for pin GPIO16 if available 11 Select function 3 for pin GPIO16 if available Preliminary User s Manual A17988EE1V1UMO00 131 Chapter 11 General Purpose I O GPIO Figure 11 7 GPIO POLSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2514H 0000 0000H 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 Bit position Bit name Function Rese
133. PKTO PIPESTA2 Trace packet bit 0 CPU pipeline status bit 2 LBU A9 RXD_P21 LBU A11 RXD_ P23 PIPESTA1 CPU pipeline status bit 1 LBU A12 CRS P2 PIPESTAO TRACESYNC CPU pipeline status bit 0 A13 ER P2 A10 RXD_P22 ETMEXTIN1 External input to the ETM LBU A1 RXD P11 ETMEXTOUT Output signal from the ETM LBU 0 RXD P10 Note Trace port pins are alternatively used as local bus or MII diagnosis pins the function is selected with the GPIO PORT MODE H and GPIO PORT MODE L registers In this table the types are listed for the trace port pin functions Pin Name VDD Core Table 2 12 Power Supply Pin Functions Function Power supply for core 1 5 V GND Core VDD IO GND IO GND CORE Power supply for IO 3 3 V GND for IO PLL AVDD PLL AGND Analog power supply for PLL 1 5 V Analog GND for PLL VDDQ PECL Power supply for PECL buffers 3 3 V GND PECL GND for PECL buffers Preliminary User s Manual A17988EE1V1UMO00 41 GPIO 2 Pin Functions Table 2 13 Alternative Functions of GPIO 31 0 Pins FunctionNete P1 DUPLEX LED N after Reset GPIOO P2 DUPLEX LED N GPIO1 P1 SPEED 100LED N TX FX P1 SPEED 10LED N GPIO2 P2 SPEED 100LED N TX FX P2 SPEED 10LED N GPIO3 P1 LINK LED_N 4 P2 LINK LED
134. RM PLO21 macro For a detailed description please refer to the list of documents on page 6 Figure 13 1 shows the structure of the SPI1 macro In order to support a wide range of connectable devices the SPI1 interface provides several operation modes Motorola SPl compatible mode Texas Instruments synchronous serial interface compatible mode National Semiconductor microwire interface compatible mode The operation mode is software configurable in the SSPCRO register Furthermore the SPI1 interface has the following features Separate send and receive FIFOs for 8 entries with 16 bit data width Data frame sizes of 4 to 16 bits can be selected in steps of 1 bit e Master and slave mode operation Bitrate from 769 Hz to 25 MHz in master mode Maximum bit rate of 4 16 MHz in slave mode Preliminary User s Manual A17988EE1V1UMO00 151 Chapter 13 Synchronous Serial Interface SPI1 Figure 13 1 Block Diagram of SPI1 Interface SPI1 SSPOE M oh SPI1 SSPTXD x SSP_TX_INTR SPI1 SFRMOUT AMBA peng SPI1 SCLKOUT bus Data receive 5 1 55 interface 145 0 logic SPI1 SCLKIN RxFIFO SPI1 SFRMIN 16 x 8 bit SPI1 SSPRXD APB Clock CLK 50 di Tx Rx SSP_TX_INTR Interrupt parameters SSP_RX_INTR Logic REIREI oe SSP ROR INTR oc prescaler Divided Clock Internal Reset
135. ROBE 5 0 00 0011 W_HOLD 2 0 010 Figure 6 8 Read from External Device Active Data Bus am ANNA AA 23 0 valid address valid data i i D 31 0 i timing determined by i i external device i i CS PER 3 0 N R_SU 3 0 0010 R_STROBE 5 0 00 0001 R_HOLD 2 0 011 Bee ea gt RD_N lt 74 Preliminary User s Manual 17988 1 10 00 Chapter6 External Memory Interface Figure 6 9 Write to External Device Using RDY_PER_N Active Data Bus 23 0 f valid address 7 1 D 31 0 valid data CS_PER 3 0 _N d i IL 01 STROBE 5 0 00 001 3 D 2 0 001 2 gt _ lt WRN T f f f f RDY_PER_N Figure 6 10 32 bit Write to External 8 bit Device Active Data Bus cx E SU 0 W_STROBE 5 0 W_HOLD 2 0 0 Mania eae ui 23 0 0 7 0 Preliminary User s Manual 17988 1 10 00 75 Chapter6 External Memory Interface EMIF 6 4 External Memory Connection Example Figure 6 11 shows an example for a memory system consisting of two external SDRAMs with 16M x 16 bit organization and an additional parallel boot Flash memory of 2M x 16 bit In a typical application
136. SE FX unused line interfaces 16 4 4 Supply Voltage Circuitry ERTEC 200 works with two operating voltages VDD Core 1 5 V and VDD IO 3 3 V Additionally the on chip PLL for the device clock generation requires a supply voltage called PLL AVDD of 1 5 V that is typically a filtered version of VDD Core The on chip PHYs of ERTEC 200 require additional filtered operating voltages as shown in Table 2 4 The subsequent Table 16 13 illustrates how these supply voltage are related to the normal VDD Core and VDD IO Table 16 13 Generation of PHY specific Supply Voltages Pin Name Function Supply Voltage Generation P 2 1 VDDARXTX Analog port RX TX power supply 1 5 Must be generated from VDD VDDAPLL Analog central power supply 1 5 V Core 1 5 V via a filter VDD33ESD Analog test power supply 3 3 V IO 3 3 V via a filter No filter required just capacitive decoupling from VDD Core DVDD 4 1 Digital power supply 1 5 V P 2 1 VSSARX Analog port GND Must be generated from GND P 2 1 VSSATX 2 1 Analog port GND Core via a filter or connected VSSAPLLCB Analog central GND to GND at the far end from ERTEC 200 VSS33ESD Analog test GND No filter required just capacitive DOND 4 1 Digital GND decoupling from GND Core Beside filtering the PHY specific supply voltages should be equipped with pairs of decoupling capaci tors 10nF and 22 nF capacitors should be used for DVDD 3
137. SSP_INTR SSP_ROR_INTR The SPI1 interface talks to the rest of ERTEC 200 via the APB bus and via two interrupt lines that are connected to the IRQ interrupt controller of the ARM946E S CPU these are SSP_INTR SPI1 group interrupt wired to IRQ10 SSP ROR INTR receive overrun error interrupt wired to IRQ11 Data transfers from and to the SPI1 interface can be operated under control of the ARM946E S core or the DMA controller For the synchronous clock output of the SPI1 interface the SPI1 has an internal clock divider Clock division is performed in two steps and must be programmed in two registers The prescaler is configured in the SSPCPSR register and the serial clock rate parameter SCR is configured in the SSPCRO register The resulting frequency is calculated according to the assigned SPI registers Based on the settings made in the respective fields of these registers the output clock frequency is calculated as follows r 2222 50MH SCLKOUT CPSDYVSR x 1 SCR SPI1 parameters be set to the following values CPSDVSR from 2 to 254 SCR from 0 to 255 This results in an overall frequency range of 769 Hz for CPSDVSR 254 SCR 255 25 MHz for CPSDVSR 2 SCR 0 SPI1 interface can also be used as a BOOT medium if for example functions from a serial EEPROM are to be loaded to ERTEC 200 and executed The boot medium is selected by the BOOT 3 0 inputs during the active reset phase see sec
138. Select full duplex mode Note The initial value after only the PHY has been reset is selected by the contents of the PHY MODE field in the PHY CONFIG register Collision Test Activates collision signal test on internal MII interface Collision Disable collision signal test initial value Enable collision signal test Reserved Write 0p ignore on read access Preliminary User s Manual A17988EE1V1UMO00 209 15 Reserved Bit position 14 100BASE TX Full Duplex Bit name 100BASE T4 100BASE TX Full Duplex Duplex Negotiation Complete Chapter 16 Multiport Ethernet PHY Figure 16 7 Basic Status Register 1 3 13 12 11 10 9 8 NO Initial value 100 5 10Mb s 10Mb s TX Half Full Half Reserved 1 7809H Duplex Duplex Auto Negotiation Ability Auto Extended Capability Link Sta tus Jabber Detect Function 100BASE T4 Indicates ability to support 100 5 4 mode 100BASE T4 100BASE TA ability indication fm No 100BASE T4 ability initial value 100BASE T4 ability supported 100BASE TX Full Duplex Indicates ability to support 100BASE TX full duplex mode 100BASE TX Full Duplex 100BASE TX full duplex ability indication 100BASE TX full duplex ability 100BASE TX full duplex supported initial value 100BASE TX Half Duplex 100BASE TX Half Duplex Indicates ability to support 100BASE TX half duplex mode 100BAS
139. Service Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit Function Reserved FIQISR 7 0 Individual indication of fast interrupt requests that have been confirmed by the CPU Bit 0 corresponds to FIQO etc FIQISR FIQISRn n 0 7 Confirmation of FIQ interrupt request Fast interrupt request FIQn not confirmed initial value Fast interrupt request FIQn has been confirmed 102 Preliminary User s Manual 17988 1 10 00 Chapter8 Interrupt Controller Figure 8 14 FIQIRR FIQ Interrupt Request Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FARR Bit position Bit name R W Function Reserved FIQIRR 7 0 Individual indication of fast interrupt requests that have been recognized by the ICU Bit 0 corresponds to FIQO etc FIQIRRn n O 7 Recognition of FIQ interrupt request FIQIRR Fast interrupt request not recognized by ICU initial value for bits FIQIRR 7 6 and FIQIRR 4 0 Fast interrupt request FIQn has been recognized by ICU initial value for bit FIQIRR5 Figure 8 15 FIQ MASKREG FIQ Interrupt Mask Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit name Function Reserved FIQ MASKREG 7
140. _N GPIO5 P1 RX LED N P2 RX LED N P1 TX LED N P2 TX LED N P1 ACTIVE LED N P2 ACTIVE LED N GPIO6 GPIO7 UART TXD GPIO8 GPIO10 UART RXD UART DCD N GPIO9 GPIO10 GPIO11 UART DSR_N GPIO11 GPIO12 GPIO13 UART CTS N Reserved GPIO12 GPIO13 GPIO14 DBGACK GPIO14 GPIO15 GPIO16 WD WDOUT N SPI1 SSPCTLOE GPIO15 GPIO16 GPIO17 SPI1 SSPOE GPIO17 GPIO18 GPIO19 SSPRXD SPI1 SSPTXD GPIO18 GPIO19 GPIO20 SPI1_SCLKOUT GPIO20 GPIO22 21 GPIO22 SFRMOUT SPI1 SFRMIN DBGACK 21 GPIO22 GPIO23 GPIO24 GPIO24 TGEN OUT1 N GPIO25 GPIO23 GPIO25 SPI1_SCLKIN PLL_EXT_IN_N Reserved GPIO23 GPIO25 GPIO 30 26 GPIO 30 26 GPIO31 DBGREQ Reserved GPIO 30 26 Note Alternative functions are software configurable using the GPIO PORT MODE L H registers 42 Preliminary User s Manual 17988 1 10 00 2 2 Pin Characteristics Pin Name 2 Pin Functions Table 2 14 Pin Characteristics 1 2 pNote 1 Input type SchmittNote 1 Output type 3 3 V CMOS Internal pull up down 50 kQ pull up Drive capability ONote 1 SchmittNote 1 3 3 V CMOS 50 kQ pull down 1 ONote 1 SchmittNete 1 3 3 V CMOS 50 kQ pull up pNote 1 SchmittNete 1 3 8 V CMOS 50 kQ pull down 19 17 pNote 1 Sc
141. agement interface data input output LBU D13 RES PHY N Reset signal to PHYs LBU_D14 TXD P2 3 0 Transmit data port 2 bits LBU D 9 6 RXD P23 Receive data port 2 bit 3 LBU A11 PIPESTA2 RXD P22 Receive data port 2 bit 2 LBU A10 TRACESYNC RXD 21 Receive data port 2 bit 1 LBU_A9 TRACEPKTO RXD_P20 2 Receive data port 2 bit 0 Transmit enable port 2 LBU_A8 TRACEPKT1 LBU_D10 CRS_P2 Carrier sense port 2 LBU A12 RX ER P2 TX ERR P2 Receive error port 2 Transmit error port 2 PIPESTAO LBU D11 RX DV P2 Receive data valid port 2 LBU A14 COL P2 RX CLK P2 Collision port 2 Receive clock port 2 LBU A15 LBU BE1 N TX CLK P2 Transmit clock port 2 LBU RD N TXD P1 3 0 RXD P13 Transmit data port 1 bits Receive data port 1 bit 3 LBU D 3 0 LBU_A3 TRACEPKT6 RXD P12 Receive data port 1 bit 2 LBU_A2 TRACEPKT7 RXD P11 RXD P10 Receive data port 1 bit 1 Receive data port 1 bit 0 LBU_A1 ETMEXTIN1 LBU_A0 ETMEXTOUT TX EN Transmit enable port 1 LBU D4 CRS P1 Oj O O O O CO OC CO CO Carrier sense port 1 LBU_A4 TRACEPKT5 RX ER P1 Receive error port 1 LBU_A5 TRACEPKT4 TX ERR P1 Transmit error port 1 LBU D5 RX DV P1 Receive data valid port 1 LBU A6 TRACEPKT3 COL P1 Collision port 1 LBU_A7 TRACEPKT2
142. al By default the active interface is switched on The following signal pins are available for the EMIF on ERTEC 200 Table 6 1 External Memory Interface Pin Functions Pin Name Function Number of pins A 23 15 External memory address bus 23 15 External memory address bus 14 0 External memory data bus 31 0 Write strobe signal Read strobe signal CLK SDRAM Clock to SDRAM CS SDRAM N Chip select to SDRAM RAS SDRAM N Row address strobe SDRAM CAS SDRAM N Column address strobe to SDRAM WE SDRAM N RD WR signal to SDRAM CS PER 3 0 N Chip select BE 3 0 DQM 3 0 Byte enable Ready signal Direction signal for external driver or scan clock Enable signal for external driver or scan clock Note The pins A 23 15 and DTR N are used as inputs BOOT 3 0 and CONFIG 6 1 and read into the REG respectively CONFIG REG system configuration registers during the active RESET phase After a reset these pins are available as normal function pins and used as out puts The external memory interface supports all transfer types transfer sizes and burst operations as described in the ARM AMBA specification see page 6 except for the Split and Retry functions All AHB burst accesses to asynchronous blocks are divided into individual accesses on the external bus AHB burst accesses with a non specified length to the SDRAM controller are divided into 8 beat burst access
143. al channel 0 70 C operating temperature Pulse Engineering HX1294 dual channel 40 85 C operating temperature In applications that do not use the 100BASE FX mode the related inputs P 2 1 RDxN P 2 1 RDxP P 2 1 SDxN and P 2 1 SDxP should be connected to analog GND while the related outputs P 2 1 TDxN and P 2 1 TDxP should be left open Figure 16 25 shows the circuit for this case Figure 16 25 Circuit for Unused 100BASE FX Mode P 2 1 TDxP open P 2 1 TDxN open P 2 1 RDxN ERTEC 200 P 2 1 RDxP P 2 1 SDxN P 2 1 SDxP GND PECL 238 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY 16 4 3 100BASE FX Circuitry In case of 100BASE FX operation a standard optical transceiver module like Agilent HFBR 5803 is connected to the P 2 1 RDxN P 2 1 RDxP P 2 1 SDxN P 2 1 SDxP P 2 1 TDxN and P 2 1 TDxP pins The connection is straight forward and consists mainly of pull up and pull down resistors The sig nals between the PHYs and the transceiver module s are 100 Q differential respectively 50 Q single ended signals This must be taken into account during PCB design The external resistors should be placed as close to the ERTEC 200 pins as possible Figure 16 26 shows the details of the circuit Figure 16 26 100BASE FX Interface Example VDD PECL 820 9 P 2 1 TDxP 1500 820 40 P 2 1 TDxN 1500
144. as inputs and read into the BOOT_REG respectively CONFIG_REG system configuration registers during the active Power On reset phase After a reset these pins are available as normal function pins and used as outputs Preliminary User s Manual A17988EE1V1UMO00 33 LBU_A 20 16 pNote 2 Pin Functions Table 2 2 Local Bus Interface Pin Functions 1 2 Function LBU address bits Alternate FunctionMote GPIO 36 32 LBU A15 LBU address bit 15 COL P2 LBU A14 LBU address bit 14 RX DV P2 LBU A13 LBU address bits 13 RX ER P2 PIPESTAO LBU A12 LBU address bit 12 CRS P2 PIPESTA1 LBU A11 LBU address bit 11 RXD P23 PIPESTA2 LBU A10 LBU address bit 10 RXD P22 TRACESYNC LBU A9 LBU address bit 9 LBU address bit 8 RXD P21 TRACEPKTO RXD_P20 TRACEPKT1 LBU address bit 7 COL_P1 TRACEPKT2 LBU address bit 6 LBU address bit 5 RX_DV_P1 TRACEPKT3 RX_ER_P1 TRACEPKT4 LBU address bit 4 CRS_P1 TRACEPKT5 LBU address bit 3 LBU address bit 2 RXD_P13 TRACEPKT6 RXD_P12 TRACEPKT7 LBU address bit 1 RXD_P11 ETMEXTIN1 LBU_D15 LBU address bit 0 LBU data bit 15 RXD_P10 ETMEXTOUT GPIO41 LBU D14 LBU data bit 14 RES PHY N LBU D13 LBU D12 LBU data bit 13 LBU data bit 12 SMI MDIO SMI MDC LBU D11 LBU data bit 11 TX ERR P2 LBU D10 LBU data bit 10 LBU data bit 9 TX EN P2 TXD P23
145. ase check Tables 2 1 to 2 11 for possible pin names first before looking up reset characteristics and recommended connections in Table 2 15 Remarks 2 and level during reset are given for the default configuration that is determined by the internal 46 pull up down resistors at the CONFIG 6 5 and pins Preliminary User s Manual 17988 1 10 00 2 Pin Functions Table 2 16 Alternative Functions of LBU Interface Pins 1 2 LBU active MII diagnosis mode Trace interface active CONFIG 6 5 Xx CONFIG2 0 CONFIG 6 5 014 CONFIG2 1p CONFIG 6 5 10 CONFIG2 1p Function 1 during reset Function 2 during reset Function 3 during reset GPIO36 GPIO35 4 LBU_A20 LBU_A19 LBU_A18 LBU_A17 LBU_A16 LBU_A15 LBU_A14 LBU_A13 LBU_A12 LBU_A11 LBU_A10 LBU A9 LBU 8 GPIO36 GPIO35 GPIO34 GPIO33 GPIO33 GPIO32 GPIO32 COL P2 5 DV P2 ER P2 PIPESTAO CRS P2 PIPESTA1 RXD P23 PIPESTA2 RXD P22 TRACESYNC RXD P21 TRACEPKTO RXD P20 TRACEPKT1 COL P1 TRACEPKT2 RX DV P1 ER P1 TRACEPKT4 CRS P1 5 RXD_P13 6 RXD_P12 TRACEPKT7 LBU A1 RXD P11 ETMEXTIN1 LBU AO RXD P10 ETMEXTOUT LBU D15 GPIO41 GPIO41 LBU D14 RES PHY LBU D13 SMI_MDIO LBU_D12 SMI MDC LBU D11 TX ERR P2 LBU D10 TX EN P2 LBU D9 TXD_ P23 LBU D8 TXD P22 LBU D7 TXD P 1 LBU D6 TXD P20 LBU D5 TX ERR P1 TX EN P1 TXD P13 TXD P12
146. ation mode is supported 100BASE No 100BASE TX operation support initial value TX after device reset 100BASE TX operation support Note Theinitial value after only the PHY has been reset is selected by the contents of the PHY MODE field in the PHY CONFIG register 10BASE T Full Duplex Indicates if 10BASE T full duplex operation mode is supported 10BASE T No 10BASE T full duplex operation support Full Duplex initial value after device reset 10BASE T full duplex operation support Note Theinitial value after only the PHY has been reset is selected by the contents of the Pn PHY MODE field in the PHY CONFIG register 216 Preliminary User s Manual A17988EE1V1UMO00 Chapter 16 Multiport Ethernet PHY Figure 16 10 Auto Negotiation Advertisement Register 3 3 Bit position Bit name Function 10BASE T Indicates if 1OBASE T operation mode is supported 10BASE T 10BASE T operation support No 10BASE T operation support initial value after 10BASE T device reset 10BASE T operation support Note The initial value after only the PHY has been reset is selected by the contents of the PHY MODE field in the PHY CONFIG register Selector Selector Field Field Indicates basic capabilities according to the IEEE802 3 specification Preliminary Users Manual A17988EE1V1UMO00 217 Chapter 16 Multiport Ethernet PHY Figure 16 11 Auto Negotiation Link Partner Ability Regis
147. avoid inconsistencies Table 14 4 Address Assignment of F Timer Registers 4000 2700H F COUNTER VAL 32 bit R 0000 0000H F timer value 4000 2704H F COUNTER RES 32 bit W 0000 0000H F timer reset register 14 3 3 Detailed F Timer register description Figure 14 13 F Timer Value Register F COUNTER VAL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value F CNT VAL 4000 2700H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F CNT VAL Bit position Bitname RW Function F CNT VAL 31 0 ONAL This register contains the current value of the F timer s counter register Figure 14 14 F Timer Reset Register F COUNTER RES 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F CNT RES Bit position Bit name Function Reserved Write arbitrary data F CNT RES 15 0 Reset value for F timer a reset of the F timer is only performed if the pattern 55AAH is written to the lower 16 bits of the F timer reset register Conse quently an F timer reset could as well be performed with a 16 bit write access Preliminary User s Manual A17988EE1V1UM00 175 MEMO 176 Preliminary User s Manual 17988 1 10 00 Chapter 15 Watchdog Timers Two watchdog timers are integrated in ERTEC 200 The watchdog timers are intended for stand alone monitoring of processes Like the processor clock their working clock of 50 MHz is deriv
148. ble STP and two pairs of unshielded twisted pair cable Category 5 UTP 100BASE TX function includes the physical coding sub layer PCS the physical medium attachment PMA and physical medium depend ent sub layer PMD When transmitting 4 bit data nibbles come from the MII interface at a rate of 25 MHz and are converted to 5 bit encoded data The data is then serialized and scrambled subsequently converted to a NRZI data stream and MLT 3 encoded In the receive path the ADC samples the incoming MLT 3 signal at a sapling frequency of 125 MHz resulting MLT 3 signal is reconverted to the NRZI data stream and then the descrambler performs the inverse function of the scrambler in the transmit path and parallelizes the data The 4B 5B decoder completes the processing and supplies the data ready for transmission over the MII interface This section describes the main functions of the 100BASE TX portion of the PHYs 1 Full duplex or Half duplex mode 2 Oollision detect indication 9 Carrier Sense detection 4 MLT 3 to from NRZ Decoding Encoding b 4B 5B Encoding Decoding 6 Scrambler Descrambler 7 Adaptive Equalization DSP 8 Baseline Wander Correction 9 Timing recovery from received data 10 Support RMII and Symbol interface 1 Timing recovery The 125M PLL locks onto the 25 MHz reference clock and generates an internal 125 MHz clock used to drive the 125 MHz logic and the 100B
149. bled and subsequently re enabled a disable time of mode than 100 us must be maintained by the software 4 If the PHY is enabled a reset is extended internally in the PHY by 5 3 ms During this time the PHY internal PLL and all analog and digital components of the PHY are started up The completion of this start up phase is signaled in the PHY STATUS register with P2_PWRUPRST 1p Preliminary User s Manual A17988EE1V1UM00 257 Chapter 17 System Control Registers Figure 17 17 PHY1 2 Configuration Register PHY CONFIG 3 4 Bit position Bit name Function Reserved P1 AUTOMDIXEN Enables AutoMDIX state machine for PHY1 P1 AUTOMDIXEN AutoMDIX enable P1 AUTOMDIXEN Disable AutoMDIX state machine for PHY1 initial value Enable AutoMDIX state machine for PHY 1 P1 PHY MODE 2 0 Select operation mode for PHY2 P1 PHY MODE PHY1 operation mode Select 10BASE T HD Auto negotiate disa bled initial value Select 10BASE T FD Auto negotiate disa bled Select 100BASE TX FX HD Auto negotiate disabled Select 100BASE TX FX FD Auto negotiate disabled Select 100BASE TX HD advertised Auto negotiate enabled Select 100BASE TX HD advertised Auto negotiate enabled repeater mode P1 PHY MODE Reserved 111 Auto negotiate enabled AutoMDIX enabled P1 FX MODE Enables 100BASE FX interface P1 FX MODE PHY FX mode enable P1 FX MODE 100BASE FX interface disabled initial value 100BASE FX interface
150. cation Message Page Page type indication a Next page is an unformatted page Next page is a message page initial value Acknowl edge 2 Acknowledge 2 Indicates if device complies to message Acknowledge 2 Message compliance indication o Device does not comply to message initial value Device complies to message 10 1 Message Unformatted Code field R W Toggle Indicates if the toggle bit of the previous page equalled 0 or 1 this function is used by the next page arbitration protocol Toggle bit indication Toggle bit in the previously transmitted link code word has been 1p initial value Toggle bit in the previously transmitted link code word has been Op Message Unformatted Code field Contains a message or unformatted 11 bit code word to be transmitted to the link partner The default message that is stored in this field after reset is the Null message 001H Preliminary User s Manual A17988EE1V1UMO0 223 Chapter 16 Multiport Ethernet PHY Figure 16 15 Silicon Revision Register 15 14 13 12 11 10 9 8 i 7 6 5 4 3 2 1 0 Silicon Revision Reserved Bit position Bit name Function Reserved Ignore on read access Initial value 0040H Silicon Silicon Revision Revision A 4 bit silicon revision identifier that is hardwired to 1H Reserved Ignore on read access 224 Preliminary User s Manual 17988 1 10 00 15 Reserved 14
151. ccess INT7 Indicates if the ENERGYON bit has been set Energy detection interrupt o No sufficient energy level detected initial value Sufficient energy level detected INT6 Indicates if auto negotiation process has been completed INT6 Auto negotiation completion interrupt Auto negotiation has not been completed initial value Auto negotiation has been completed INT5 Indicates if a remote fault condition has been detected INT5 Remore fault detection interrupt No remote fault condition has been detected initial value Remote fault condition has been detected INT4 Indicates if the ENERGYON bit has been set INT4 Link down interrupt R No link down interrupt has been generated initial value Link down interrupt has been generated Preliminary User s Manual A17988EE1V1UM00 231 Chapter 16 Multiport Ethernet PHY Figure 16 19 Interrupt Source Flag Register 2 2 Bit position Bit name Function INT3 Indicates if a link partner acknowledge has been received during the auto negotiation process INT3 Link partner acknowledge interrupt No link partner acknowledge interrupt has been generated initial value Link partner acknowledge interrupt has been generated INT2 Indicates if a parallel detection fault has occurred No parallel detection fault interrupt has been gen erated initial value Parallel detection fault interrupt has been
152. cessed Note Note If data with less than 16 bits width is used the user must write the data to the Transmit FIFO the proper format When data are read they are read out correctly from the Receive FIFO Preliminary User s Manual A17988EE1V1UM00 157 Chapter 13 Synchronous Serial Interface SPI1 Figure 13 5 55 5 5 Status Register 15 14 13 12 11 10 9 8 7 6 5 Address Initial value 4 3 2 1 0 Bit position Bit name Function Reserved BSY SPI1 busy status indication Busy status indication SPI is not busy initial value SPI1 is sending and or receiving a frame or the transmit FIFO is not empty RFF Receive FIFO full indication Receive FIFO full indication Receive FIFO is not full initial value Receive FIFO is full RNE Receive FIFO not empty indication Receive FIFO not empty indication Receive FIFO is empty initial value Receive FIFO is not empty TNE Transmit FIFO not full indication Transmit FIFO not full indication 0 Transmit FIFO is full initial value Transmit FIFO is not full TFE Transmit FIFO empty indication Transmit FIFO empty indication zai Transmit FIFO is not empty initial value Transmit FIFO is empty 158 Preliminary User s Manual 17988 1 10 00 Chapter 13 Synchronous Serial Interface SPI Figure 13 6 SSPCPSR 5 Clock Prescale Register 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 Address Initial value Bit position Bit name
153. complete Interrupt Event Remote fault detected Link down Auto negotiation LP acknowledge Parallel detection fault INT1 Auto negotiation page received Each of the interrupt events above is described in the protocol of the Interrupt Source Flag register in the PHYs it can as well be masked or unmasked individually in the Interrupt Mask register in the PHYs see Table 16 9 Preliminary User s Manual A17988EE1V1UMO00 199 Chapter 16 Multiport Ethernet PHY 9 Isolate Mode The PHY data path may be electrically isolated from the MII by setting the Isolate bit in the Basic Con trol register to 1 In isolate mode in internal MII interface of the respective PHY is made inactive How ever the PHYs still respond to management transactions Isolation provides a means for multiple PHYs to be connected to the same MII without contention occurring and it is not really required to use onERTEC 200 The PHYs are not in isolate mode on power up 10 Link integrity Test The PHYs perform a link integrity test as outlined in the IEEE 802 3 Link Monitor state diagram The link status is multiplexed with the 10Mbps link status to form the reportable Link Status bit in the Basic Con trol register 1 and is driven to the P 2 1 LINK LED output The DSP block indicates a valid MLT 3 waveform present on the P 2 1 RxP and P 2 1 RxN inputs as defined by the ANSI X3 263 TP PMD standard to the link monitor state machine using a
154. d Reset Pin Functions Pin Name Function Alternate Function TRACECLK ETM trace or scan clock CLKP_A Quartz connection CLKP_B Quartz connection F_CLK F_CLK for F counter REF_CLK Reference clock RESET_N Power On reset Table 2 10 JTAG and Debug Interface Pin Functions Pin Name 1 oNote Function Alternate FunctionN te JTAG reset signal JTAG clock signal JTAG data input signal JTAG test mode select signal JTAG data output signal Hardware reset for debug usage DBGREQ Debug request signal GPIO31 DBGACK Debug acknowledge signal GP1014 GPIO22 SPI1_SFRMIN TAP_SEL TAP controller select signal Note The DBGREQ DBGACK pin is alternatively used as GPIO GPIO or SPI1 pin the function is selected with the GPIO_PORT_MODE_H and GPIO PORT MODE L registers In this table the I O type is listed for the DBGREQ DBGACK function 40 Preliminary User s Manual 17988 1 10 00 TRACEPKT7 2 Pin Functions Table 2 11 Trace Port Pin Functions Function Trace packet bit 7 Alternate FunctionNote LBU A2 RXD P12 TRACEPKT6 Trace packet bit 6 LBU RXD P13 TRACEPKT5 Trace packet bit 5 LBU A4 CRS P1 TRACEPKT4 Trace packet bit 4 LBU A5 RX ER P1 TRACEPKT3 Trace packet bit 3 LBU A6 RX DV P1 TRACEPKT2 Trace packet bit 2 LBU AT COL P1 TRACEPKT1 Trace packet bit 1 LBU_A8 RXD_P20 TRACE
155. ded to 0000p 182 Preliminary User s Manual 17988 1 10 00 Chapter 15 Watchdog Timers Figure 15 7 Reload Register High for Watchdog 1 RELD1_HIGH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Key bits 4000 2110H 0000 FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reload1 Bit position Bit name Function Key bits 15 0 Key bits Must be written with 9876H in order to make a write access effective read 0000H Reload1 15 0 Holds the reload value for bits 35 20 of watchdog timer 1 counter Reload1 Figure 15 8 Counter Register for Watchdog 0 WDOGO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value e WDOGO O 40002114 FFFFFFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Function WDOG0 31 0 31 0 weed Holds the current counter value for watchdog timer 0 Figure 15 9 Counter Register for Watchdog 1 WDOG1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value WDOG1 40002118H FFFF FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDOG1 WDOG 1 31 0 31 0 WDOG1 Holds bit 35 4 of the current counter value for watchdog timer 1 bits 3 0 of the current counter value cannot be read Preliminary User s Manual A17988EE1V1UM00 183 MEMO 184 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY ERTEC 200 has a multiport Ethernet PHY Physical Layer Tra
156. diaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1 Preliminary User s Manual A17988EE1V1UMO00 For further information please contact NEC Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki Kanagawa 211 8668 Japan Tel 044 435 5111 http www necel com America NEC Electronics America Inc 2880 Scott Blvd Santa Clara CA 95050 2554 U S A Tel 408 588 6000 800 366 9782 http www am necel com Europe NEC Electronics Europe GmbH Arcadiastrasse 10 40472 Dusseldorf Germany Tel 0211 65030 http www eu necel com Hanover Office Podbielskistrasse 166 B 30177 Hannover Tel 0 511 33 40 2 0 Munich Office Werner Eckert Strasse 9 81829 Munchen Tel 0 89 92 10 03 0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel 0 711 99 01 0 0 United Kingdom Branch Cygnus House Sunrise Parkway Linford Wood Milton Keynes MK14 6NP U K Tel 01908 691 133 Succursale Frangaise 9 rue Paul Dautier B P 52 78142 Velizy Villacoublay C dex France Tel 01 3067 5800 Sucursal en Espa a Juan Esplandiu 15 28007 Madrid Spain Tel 091 504 2787 Tyskland Filial Centrum Entrance S 7th floor 18322 Taby Sweden Tel 08 638 72 00 Filiale Italiana Via Fabio Filzi 25 A 20124 Milano Italy Tel 02 667541 Branch The Netherlands Steijgerweg 6 5616 HS Eindhoven The N
157. e During this period no communication is possible with a debugger using the JTAG interface Figure 19 1 shows the power up phase of the PLL after a reset Figure 19 1 PLL Power up Phase f PLL oyr MHz t Lock 645 us Power up of PLL 35 Uus The lock status of the PLL is monitored Loss of the input clock and the PLL unlock state are signalled with the fast interrupt The state of the PLL can also be read out from the PLL STAT REG status register A filter is integrated at the RESET input which suppresses spikes up to 5 ns In case of a PowerOn reset bit 2 is set in the reset status register RES STAT REG This bit remains unaffected by the triggering reset function and can be evaluated after a restart An external debug tool is informed of a PowerOn reset with the SRST signal SRST_N is activated while RESET is active and while the internal RESET extension is working This allows the exter nal debugger to recognize the PowerOn reset phase Preliminary User s Manual A17988EE1V1UM00 267 19 Reset Logic of 200 19 2 Hardware Reset A hardware reset is activated using the bi directional SRST_N pin open drain SRST_N is only used by the debugger While SRST_N is active the complete internal logic is reset except the clock system and the BOOT and CONFIG pins not read While SRST N is active the debugger can communicate via the JTAG interface with the embedded
158. e SDRAM if Bit 29 INIT DONE is set in the SDRAM Refresh Control register i e the SDRAM power up sequence has been executed Preliminary User s Manual 17988 1 10 00 67 Chapter6 External Memory Interface EMIF Figure 6 3 SDRAM Bank Config Register 2 2 Bit position Bit name Function IBANK 2 0 internal SDRAM bank setup IBANK 2 0 Number of internal SDRAM banks 1 bank 2 banks 4 banks initial value Reserved Reserved PAGESIZE 2 0 page size Configures the SDRAM page size by selection of the number of column address lines PAGESIZE 2 0 Number of column address lines 8 column address lines initial value PAGESIZE 9 column address lines 10 column address lines 11 column address lines others Reserved 68 Preliminary User s Manual 17988 1 10 00 Chapter6 External Memory Interface EMIF Figure 6 4 SDRAM_Refresh_Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 reserved REFRESH_RATE Bit position INIT_ AT DON 12 11 10 9 Bit name reserved 7000 000CH 0000 0190H 8 7 6 5 4 3 2 1 0 Function Reserved AT asynchronous timeout Indicates whether the interval that is specified with the Async Wait Cycle Control register has elapsed ON o Asynchronous timeout Interval that is specified with the Async Wait Cycle Control register has not yet elapsed initial val
159. e 18 2 Clock Supply of Ethernet Interface Ethernet Ethernet Port 0 Port 1 ERTEC 200 TX CLK P1 RX CLK P2 TX CLK P2 n E O from 25 2 MII interface is also presented at the LBU interface pins for Ethernet interface debugging In this case the LBU interface is not usable The configuration is selected with the configuration pins CONFIG 6 5 and CONFIG2 CONFIG 6 5 015 CONFIG2 15 MII interface in diagnosis mode Preliminary User s Manual A17988EE1V1UMO0 265 MEMO 266 Preliminary User s Manual 17988 1 10 00 Chapter 19 Reset Logic of ERTEC 200 The reset logic resets the entire circuit of ERTEC 200 A reset of ERTEC 200 is activated by the follow ing events PowerOn reset via external RESET_N pin Software reset via XRES SOFT bit in the reset control register Watchdog reset via watchdog timer overflow The triggering reset event can be read out in the reset status register RES STAT REG 19 1 PowerOn Reset The PowerOn reset circuitry is connected to the RESET pin of ERTEC 200 If the PowerOn reset is activated the entire ERTEC 200 circuit is reset internally The PowerOn reset must be present steadily for at least 35 us see Figure 19 1 Afterwards the PLL powers up within a lock time of tLock 645 us In ERTEC 200 the PowerOn reset phase is extended for this period and the rest of the clock system is activated at the end of the PLL start up phas
160. e remote fault number code 1 Parallel detection The parallel detection function allows detection of Link Partners that support 100BASE TX and or 10BASE T but do not support Auto Negotiation The PHY is able to determine the speed of the link based on either 100M MLT 3 symbols or 10M Normal Link Pulses If the PHY detects either mode it automatically reverts to the corresponding operating mode In this case the link is presumed to be half duplex If a link is established via parallel detection then Bit O of the Auto Negotiation Expansion register is cleared to indicate that the link partner is not capable of auto negotiation The controller has access to this information via the management interface If a fault occurs during parallel detection bit 4 of the Auto Negotiation Expansion register is set The Auto Negotiation Link Partner Ability register is used to store the link partner ability information which is coded in the received FLPs If the link partner is not auto negotiation capable then the Auto Negotiation Link Partner Ability register is updated after completion of parallel detection to reflect the speed capabilities of the link partner 2 Re negotiation Auto negotiation is started by one of the following events 1 H W reset 2 S W reset 9 setting the Auto Negotiation Enable bit in the Basic Control register from low to high When auto negotiation is enabled it is re started by one of the following events lt
161. e sending or receiving is not possible Figure 12 7 UARTCR Register 1 2 5 4 3 2 1 0 Address 7 6 Bit position Bit name Function LBE Activates loop back mode for testing purposes Initial value 00H Loop back mode enable bit 0 Loop back mode disabled initial value Loop back mode enabled RTIE Enables receive timeout interrupt enable RTIE Receive timeout interrupt enable bit Receive timeout interrupt disabled initial value Receive timeout interrupt enabled Preliminary User s Manual A17988EE1V1UMO00 145 Chapter 12 Asynchronous Serial Interface UART Figure 12 7 UARTCR Register 2 2 Bit position Bit name Function TIE Transmit interrupt enable bit Transmit interrupt enable bit Transmit interrupt disabled initial value Transmit interrupt enabled RIE Receive interrupt enable bit Receive interrupt enable bit Receive interrupt disabled initial value Receive interrupt enabled MSIE Modem status interrupt enable bit MSIE Modem status interrupt enable bit Modem status interrupt disabled initial value Modem status interrupt enabled Reserved UARTEN UART enable bit UARTEN UART enable bit RATEN 7 UART disabled initial value 1 UART enabled reception and transmission of data is possible 146 Preliminary User s Manual 17988 1 10 00 Chapter 12 Asynchronous Serial Interface UART Figure 12 8 UARTFR Reg
162. ect Register 04 4 105 EDGEREG IRQ Trigger Edge Select Register 106 SWIRREG Software IRQ Interrupt Register sse 106 PRIOREGO 15 IRQ Interrupt Priority Register ssseeeee 107 Example for LBU Address Line 114 LBU Read from ERTEC 400 with Separate Read Control Line 116 LBU Write to ERTEC 400 with Separate Write Control Line 117 LBU Read from ERTEC 400 with Common Read Write Control Line 117 LBU Write to ERTEC 400 with Common Read Write Control 118 LBU Page Range Register Low LBU Pn 2 024 211 120 LBU Page Range Register High LBU Pn RQG 120 LBU Page Offset Register Low LBU Pn OF L 121 LBU Page Offset Register High LBU Pn OF H senes 121 LBU Page Configuration Register LBU Pn CFQG sene 122 GPIO Cells of ERTEC 200 for 3 0 126 GPIO IOCTRL Register 2002 0 0 128 GPIO OUT Register iarasi aai de ditat ea 128 GPIO IN Register 129 GPIO PORT MODE L Register
163. ectronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsi
164. ed ARM documents see page 6 52 Preliminary User s Manual 17988 1 10 00 Chapter 3 CPU Function 3 7 946 5 Registers Beside the working registers that are part of the ARM9E S core architecture the ARM946E S proces sor system includes a CP15 coprocessor with a register set for system control These registers are used for functions like e Cache type and cache memory area configuration Tightly coupled memory area configuration Memory protection unit setting for various regions and memory types Assignment of system option parameters Configuration of Little Endian or Big Endian operation Table 3 1 summarizes the function of the CP15 coprocessor registers and their access options Table 3 1 15 Coprocessor Registers Register Access type Comment ID code register Cache type register Tightly coupled memory size register Control register Cache configuration register Write buffer control register Reserved Access permission register Protection region base size register Cache operation register Reserved Cache lock down register Tightly coupled memory region Reserved Reserved Reserved Trace process ID register Reserved RAM TAG BIST test register Test state register Cache debug index register Trace control register Notes 1 These register locations provide access to several registers that are selected with the opcode 2
165. ed data are entered in the FIFO register the first word of the receive FIFO Preliminary User s Manual A17988EE1V1UMO00 Initial value xxH If FIFO is disabled the received data are entered in the receive holding Note When data are received the UARTDR data register must be read out first and then the UARTRSR UARTECR error register 141 Chapter 12 Asynchronous Serial Interface UART Figure 12 3 UARTRSR UARTECR Registers 7 6 5 4 3 2 1 Address Initial value 0 Bit position Bit name Function Reserved undefined when read OE Overrun error is detected when the FIFO is full and a new character is received Co oo No overrun error detected initial value Overrun error detected BE A break error is detected when the received data are at low for longer than a standard character with all control bits lasts fm No break error detected initial value Break error detected PE A parity error is detected when the parity of received character does not match the parity that is configured in the EPS bit No parity error detected initial value Parity error detected FE A framing error is detected when the received character does not have a valid stop bit No framing error detected initial value Framing error detected UARTECR 7 0 All error flags are cleared when a write access is performed to this register Note When new data are displayed the UARTDR data register mu
166. ed data patterns and spreads the signal power more uniformly over the entire channel band width The scrambler encodes a plaintext NRZ bit stream by addition modulo 2 of 2047 bits generated by the recursive linear function X n X n 11 X n 9 modulo 2 The scrambler generates the specified non zero key stream whenever the active output interface is required to transmit a scrambled data stream The seed for the scrambler is generated from the PHY address ensuring that in multiple PHY applica tions each PHY will have its individual scrambler sequence The descrambler descrambles the NRZ ciphertext bit stream coming from the MLT 3 decoder by addi tion modulo 2 of a key stream to re produce a plaintext bit stream During the reception of IDLE sym bols the descrambler synchronizes its descrambler key to the incoming stream Once synchronization is achieved the descrambler locks on this key and is able to descramble incoming data Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE symbols within a window of 4000 bytes 40us This window ensures that a maximum packet size of 1514 bytes allowed by the IEEE 802 3 standard can be received with no interference This core has a scrambler and descrambler bypass mode for testing purposes 6 MLT3 Encoding Decoding In the transmit direction the serial 125 MHz NRZI data stream is encoded to MLT 3 MLT 3 is a trilevel code where a change in the
167. ed from the PLL Figure 15 1 shows a simplified block diagram of the watchdog timers Figure 15 1 Watchdog Timer Block Diagram 50 D Watchdog Timer 0 Watchdog Timer 1 WDOUT1_N to reset controller WDOG 0 WDOG1 WDOUTO_N to FIQO input of ICU and GPIO15 Control Status 15 1 Watchdog Timer Function Watchdog timer 0 is a 32 bit down counter to which the WD WDOUTO N output is assigned This out put can be used as an alternative function 2 of the GPIO15 pin see section 11 2 The timer is locked after a reset It is started by setting the Run xStop 70 bit in the CTRL STATUS watchdog register A maximum monitoring time of 85 89 s with a resolution of 20 ns can be programmed Watchdog timer 1 is a 36 bit down counter in which only the upper 32 bits can be programmed The WDOUT 1 output signal is assigned to watchdog timer 1 This output signal is not routed to the outside it triggers a hardware reset internally The timer is locked after a reset It is started by setting the Run xStop Z1 bit in the CTRL STATUS watchdog register A maximum monitoring time of 1374 3 s with a resolution of 320 ns can be programmed When the Load bit is set in the CTRL STATUS watchdog register both watchdog timers are simultaneously reloaded with the applicable reload values of their reload registers In the case of watchdog timer 1 bits 35 4 are loaded with the reload value bits 3 0 are set to 0 The coun
168. ed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an pull up power supply while the device is not powered The current injection that results from input of such a signal or I
169. egister 206 16 4 Board Design Recommendations 236 16 4 1 Supply Voltage 1 236 16 4 10BASE T and 100BASE TX Mode 237 16 4 8 100BASE FX Circuitry 239 Chapter 17 System Control 241 17 1 Address Assignment of System Control Registers 241 17 2 Detailed System Control Register 242 Chapter 18 ERTEC 200 Clock 263 18 1 Clock Supply in ERTEC 200 263 18 2 Specific Clock Supplies 265 Chapter 19 Reset Logic of ERTEC 200 267 19 1 ea ee Ae eee 267 19 2 Hardware 1 268 19 3 Watchdog 268 19 4 55522 eodd eel 268 19 5 IRT Switch 268 19 6 Actions when HW Reset is Active
170. eload Register for Prescaler 0 and 1 RELD PREDIV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2014H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Prediv V1 Prediv VO Bit position Bit name R W Function 31 16 Reserved Prediv V1 7 0 This register holds the 8 bit reload value for Prescaler 1 Prediv V1 Prediv VO 7 0 This register holds the 8 bit reload value for Prescaler 0 Preliminary User s Manual A17988EE1V1UMO00 169 Chapter 14 ERTEC 200 Timers Figure 14 8 Current Timer Value Register for Timer 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 31 0 Timer 10 This register holds the current counter value for Timer 0 Figure 14 9 Current Timer Value Register for Timer 1 TIM1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 0 Timer mineral This register holds the current counter value for Timer 1 170 Preliminary User s Manual 17988 1 10 00 Chapter 14 200 Timers 14 2 Timer 2 Timer 2 is a simple 16 bit up counter that can be used for all kinds of supervision functions Timer 2 has an interrupt output that is connected to the IRQ6 input of the interrupt controller of the ARM946E S CPU Access to the timer registers is always 32 bits in width Timer 2 has the following func
171. en onto the RXD 2 1 lines Note that the valid vata signal is not yet asserted when the bad SSD error occurs 16 1 3 100BASE FX Operation This section describes main functions within the PHY in 100BASE FX operation 1 NRZI to from NRZ converter 2 Far End Fault Indication 3 Timing recovery from received data 4 Support MII RMII and Symbol interface The 100BASE FX shares logic with 100BASE TX the differences between 100BASE FX mode and 100BASE TX mode are following 1i Transmit output receive input is not scrambled or MLT3 encoded 2 All analog circuits except for the PLL are powered down 3 Auto Negotiation is disabled 4 The transmit data is output to a FX transmitter b The receive data is input to the FX ECL level detector instead of the equalizer 6 The FX interface has a signal detect input 1 Signal Detect The signal detect signals P 2 1 SDxP N are input signals to the PHY from the PMD FX transceiver Assertion of P 2 1 SDxP N indicates a valid FX signal on the fiber When SD is deactivated the LINK goes down and no data is sent to the controller 2 Far End Fault indication Far End fault indication FEFI is a mechanism used to communicate physical status across a fiber link Each PHY monitors the status of its receive link using the Signal Detect input If the PHY detects a problem with its receive link it communicates that to its link partner using the FEFI mecha
172. en register is updated after completion of parallel detection to reflect the speed capability of the link partner 4 Next Page function Additional information exceeding that required by base page exchange is also sent via Next Pages this PHY supports the optional Next page function Next page exchange occurs after the base page has been exchanged Next page exchange consists of using the normal Auto Negotiation arbitration process to send next page messages Two kinds of message encodings are defined Message Pages which contain predefined 11 bit codes and unformatted pages Next page transmission ends when both ends of a link segment set their Next Page bits to logic zero indicating that neither has anything additional to transmit It is possible for one device to have more pages to transmit than the other device Once a device has completed transmission of its next page information it shall transmit message pages with Null message codes and the NP bit set to logic zero while its link partner continues to transmit valid next pages Devices that are able of auto negotiation shall recognize reception of message pages with Null mes sage codes as the end of its link partner s next page information The default value of the next page support is disable Next Page bit in Auto Negotiation Advertisement register To enable next page sup port the Next Page bit should be set to 15 Auto Negotiation should be restarted and the message code t
173. ent phase variations of 125Mbps received packets against the 25Mbps data on the interface only in 100BASE TX FX mode It cor responds to the system latency between MII TX EN P 2 1 and MII RX DV P 2 1 and itis measured based on the first packet after link up This value is then stored in the PHASE OFFSET field of the Spe cial Controls Status Indications register Figure 16 4 illustrates this function 200 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Figure 16 4 Phase Offset Indicator Function MII PHY on Ethernet line PHY on MII transmit side receive side Resulting phase offset e Latency gt i TX_EN_P 2 1 RX_DV_P 2 1 Preliminary User s Manual A17988EE1V1UM00 201 Chapter 16 Multiport Ethernet PHY 16 2 PHY Related Interfaces Like any other peripheral on the ERTEC 200 the PHYs have internal registers that allow control over their behaviour and that reflect their operation status however in contrast to the other peripherals the PHY control registrs are not memory mapped and not directly accessible for the ARM CPU core or any other AHB master within ERTEC 200 This is due to the standardized MII SMI interface between the PHYs and the MACs that are integrated in the IRT switch Figure 16 5 shows the different paths into the PHYs Figure 16 5 PHY Related Interfaces
174. er terminated The interrupt controller is operated at a clock frequency of 50 MHz Interrupt request signals that are generated at a higher clock frequency must be extended accordingly for error free detection 8 1 Prioritization of Interrupts It is possible to set priorities for the IRQ and FIQ interrupts Priorities 0 to 15 can be assigned to IRQ interrupts while priorities O to 7 can be assigned to FIQ interrupts The highest priority is O for both interrupt levels After a reset all IRQ interrupt inputs are set to priority 15 and all FIQ interrupt inputs are set to priority 7 A priority register is associated with each interrupt input PRIOREGO to PRIOREG15 are for the IRQ interrupts and FIQPRO to FIQPR7 are for the FIQ interrupts A priority must not be assigned more than once The interrupt control logic does not check for assignment of identical priorities All interrupt requests with a lower or equal priority can be blocked at any time in the IRQ priority resolver by assigning a priority in the LOCKREG register If an interrupt that is to be blocked is requested at the same time as the write access to the LOCKREG register an IRQ signal is output However the signal is revoked after two clock cycles If an acknowledgement is to be generated nonetheless the transferred interrupt vector is the default vector 88 Preliminary User s Manual 17988 1 10 00 Chapter8 Interrupt Controller 8 2 Trigger Modes Edge trigger or level trigger m
175. erface SMI between MAC and PHY gives access to the PHY s internal con trol registers There is a common SMI interface for both PHYs the two PHYs have hardwired addresses that are part of the protocol over the SMI interface The SMI signals can as well be moni tored together with the MII signals in MII diagnosis mode Table 16 6 lists the signals that belong to the SMI diagnosis interface and the normal usage of the same pins for LBU signals Preliminary User s Manual A17988EE1V1UMO00 203 Chapter 16 Multiport Ethernet PHY Table 16 6 SMI Diagnosis Interface Signals SMI MDC Serial management interface clock LBU_D12 SMI MDIO Serial management interface data input output LBU_D13 Note SMI diagnosis interface pins are alternatively used as local bus interface or trace pins in this table the I O type is listed for the SMI diagnosis function 3 MDI Interface The media dependent interface MDI is the PHY s data communication interface to the Ethenet net work in 10BASE T 100BASE TX or 100BAE FX mode It is partly analog and partly digital the circuitry that is connected to the MDI interfaces must be carefully selected Proposals can be found in Chapter 16 4 Table 16 7 shows the MDI interface signals arranged for the various supported operation modes Table 16 7 MDI Interface Signals Pin Name Function Operation mode Differential transmit data output Differential transmit data output 10BASE TX D
176. erface The GPIO22 control line is then used as the chip select for the serial boot ROM The storage medium Flash or EEPROM is selected by means of the GPIO23 control line Booting from an external host processor system via the LBU interface Booting from UART with the bootstrap method a routine for operation of the serial interface is executed first This routine then controls the actual program download Note A more detailed description of the boot modes and the operation of the related program parts is given in the documentation that is listed on page 6 Preliminary User s Manual A17988EE1V1UMO0 123 Chapter 10 Boot ROM 10 1 Booting from External ROM This boot mode is provided for applications for which the majority of the user firmware runs on the ARM946E S The boot process is completely determined be the external image and it can be started with a minimum initialisation 10 2 Booting via SPI SPI compatible EEPROMs as well as SPl compatible Data Flash memories can be used as an SPI source GPIO23 is used to select the type GPIO23 0 SPl compatible Data Flash e g AT45DB011B 23 1 SPI compatible EEPROM e g AT25HP256 GPIO22 is used as chip select output for the boot device The serial protocols by Motorola Texas Instruments and NSC are in principle supported 10 3 Booting via UART When booting via the UART a bootstrap methodology is used that first downloads a routine for opera tion of the serial int
177. erface to ERTEC 200 This routine then takes care of the actual download of the pro gram to be executed After the boot process is finished the UART can be used for other purposes 10 4 Booting via LBU Booting of user software via LBU must be actively performed by an external host processor The LBU host can then transfer the user code into the ERTEC 200 memories The boot software for boot via LBU does not read any device identification information from the ERTEC 200 system If required such device ID must be stored in a storage medium for example EEPROM connected to SPI1 that the host processor reads via the LBU interface The host processor can then decide based on the device ID which user code is to be downloaded to the LBU 10 5 Memory Swapping The reset vector of the ARM946E S core points to the address 0000 0000H and consequently to the boot ROM Additionally the boot ROM can be accessedi in its mirror area see Table 5 1 After comple tion of the boot process SRAM or SDRAM can be swapped to address 0000 0000H in order to imple ment the exception vector table for the ARM946E S from this address onwards The original memory positions of boot ROM SRAM or SDRAM are not affected by memory swapping Memory swapping is controlled by the register MEM SWAP in the system control register area 124 Preliminary User s Manual 17988 1 10 00 Chapter 11 General Purpose I O GPIO A maximum of 45 general purpose inputs outputs i
178. es on the external bus Preliminary User s Manual A17988EE1V1UMO0 63 Chapter6 External Memory Interface EMIF The SDRAM controller has the following features e 16 bit or 32 bit data bus width selectable PC100 SDRAM compatible at 50 MHz SDRAM clock frequency Up to 128 MBytes of SDRAM for 32 bit data bus width configured as 1 bank of 128 MBytes 2 banks of 64 MBytes 4 banks of 32 MBytes e Supports various SDRAMs with the following properties CAS latency 2 or 3 clock cycles 1 2 4 internal banks can be addressed via A 1 0 8 9 10 1 1 bit column address A13 11 2 Maximum of 13 bit row address A 14 2 SDRAMs with a maximum of 4 banks are supported The SDRAM controller can keep all 4 banks open simultaneously In terms of addresses these four banks correspond to one quarter of the SDRAM address area on the AHB bus As long as the alternating accesses are in the respective page no page miss can occur The asynchronous memory controller has the following features 8 bit 16 bit or 32 bit data bus width can be selected 4chip select signals Maximum of 16 MBytes per chip select can be addressed Different access timing can be configured for each chip select Ready signal can be configured differently for each chip select Chip select CS PERO N can be used for boot operations from external memory Data bus width of the external boot memory selected via the BOOT 3 0 input pins Default reg
179. es to the gaps in this address area do not activate the bus monitoring circuitry that is described in section 20 1 read and write accesses to these addresses result in undefined data These 2 MBytes are mirrored every 8 MByte over the complete 256 MByte range of segment 1 Preliminary User s Manual A17988EE1V1UM00 59 5 3 In this chapter a memory map example for a stripped down memory system consisting of 64 MBytes of external SDRAM and 4 MBytes of external parallel Flash memory connected to chip select CS PERO is shown The representation in Table 5 3 is somewhat different than in the previous tables as the last two columns illustrate the actually used address ranges to which programmers should limit their addressing operations Users are discouraged from using mirrors of the addressing ranges shown in Table 5 3 in order to avoid the risk of future software compatibiliy problems Segment Table 5 3 Memory and Used Address Range Example 1 2 Contents Boot ROM Available Address range 0000 0000H OFFF FFFFH Size 256 MBytes Address range 0000 0000H 0000 1FFFH Size 8 kBytes Not used IRT switch 1000 0000H 100F FFFFH 1 MBytes Not disclosed Not disclosed Not used 1010 0000H 1FFF FFFFH 255 MBytes 1010 0000H 1010 FFFFH 64 kBytes Not used 2000 0000H 2FFF FFFFH 256 MBytes 2000 0000H 23FF FFFFH 64
180. ese pins cannot be re configured dynamically The primary function of these pins is dedicated to the LBU interface in this context the GPIO function must be regarded as an alternative function Table 11 4 summarizes all possible functions for GPIO 44 32 Table 11 4 Alternative Functions of GPIO 44 32 pins Function 0 1 2 CONFIG 6 5 xxy CONFIG 6 5 01 CONFIG 6 5 10 CONFIG2 0 CONFIG2 1 CONFIG2 1 GPIO32 LBU_A16 GPIO32 GPIO32 GPIO33 LBU_A17 GPIO33 GPIO33 GPIO34 LBU A18 GPIO34 GPIO34 GPIO35 LBU_A19 GPIO35 GPIO35 GPIO36 LBU_A20 GPIO36 GPIO36 GPIO37 LBU SEG 0 GPIO37 GPIO37 GPIO38 LBU_SEG_1 GPIO38 GPIO38 GPIO39 LBU_CS_R_N GPIO39 GPIO39 GPIO40 LBU CS M N GPIO40 GPIO40 GPIO41 LBU D15 GPIO41 GPIO41 GPIO42 LBU RDY GPIO42 GPIO42 GPIO43 LBU IRQO N 43 GPIO43 44 LBU IRQ1 N GPIO44 GPIO44 GPIO pin 136 Preliminary User s Manual 17988 1 10 00 Chapter 12 Asynchronous Serial Interface UART A UART is implemented in ERTEC 200 The inputs and outputs of the UART are available as an alter native function at GPIO 12 8 To use the UART it is required to set input output direction accordingly for the affected pins using the GPIO IOCTRL register to configure alternative function 1 for the affected pins using the GPIO PORT MODE L H registers Note that after reset GPIO 31 0 pins are configured as GPIO inputs an eventually configured UART is
181. eset or by writing the value 55AAH x means don t care to the F counter register F COUNTER RES The next count pulse sets the counter to FFFF FFFFH and the counter is decremented at each additional count pulse The F COUNTER_RES register is cleared again at the next clock cycle The current count value can be read out by a 32 bit read access While an 8 bit or 16 bit read access is possible it is not useful because it can result in an inconsistency in the read count values Note The maximum input frequency for the F_CLK pin is one quarter of the APB clock In the event of a quartz failure on ERTEC 200 a minimum output frequency between 40 and 90 Miz is set at the PLL This results in a minimum APB clock frequency of 40 MHz 6 6 6666 MHz To prevent a malfunction in the edge evaluation the F_CLK frequency must not exceed a quarter of the minimum APB clock frequency thus 6 66 MHz 4 1 6666 MHz The figure below shows the function blocks of the F timer Figure 14 12 F Timer Block Diagram CONFIG 4 3 32 bit Down Counter F COUNTER EN ey F COUNTER VAL Read F COUNTER VAL F_CLK XXXX55AAH F COUNTER RES to APB Bus 174 Preliminary User s Manual 17988 1 10 00 Chapter 14 200 Timers 14 3 2 Address assignment of F Timer registers The F timer registers are 32 bits wide The registers should be read or written to with 32 bit accesses only in order to
182. etherlands Tel 040 265 40 10 Asia amp Oceania NEC Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 Tel 010 8235 1155 http www cn necel com Shanghai Branch Room 2509 2510 Bank of China Tower 200 Yincheng Road Central Pudong New Area Shanghai P C 200120 Tel 021 5888 5400 http Awww cn necel com Shenzhen Branch Unit 01 39 F Excellence Times Square Building No 4068 Yi Tian Road Futian District Shenzhen P R China P C 518048 Tel 0755 8282 9800 http Avww cn necel com NEC Electronics Hong Kong Ltd Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 2886 9318 http www hk necel com NEC Electronics Taiwan Ltd 7F No 363 Fu Shing North Road Taipei Taiwan 02 8175 9600 http www tw necel com NEC Electronics Singapore Pte Ltd 238A Thomson Road 3112 08 Novena Square Singapore 307684 Tel 6253 8311 http www sg necel com NEC Electronics Korea Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 02 558 3737 http www kr necel com 60705 Preliminary User s Manual 17988 1 10 00 Readers Purpose Organization Legend Preface This manual is intended for users who want to understand the functions of the ERTEC 200 This manual presents
183. etween two write accesses to the DMA destination initial value Insert n delay clocks in between two write accesses to the DMA destination Nete 5 DELAY 3 0 Sets the read inactive delay counter The DMA controller puts the specified number of clocks 50 MHz in between two read accesses to the DMA source S DELAY S DELAY 3 0 Read inactive delay counter Do not insert delay clocks in between two read accesses to the DMA source initial value Insert n delay clocks in between two read accesses to the DMA sourceNete Note With the delay counter there is a wait time until the next request if the target UART SPI1 is too slow With the following settings the specified delay values for UART and SPI1 are obligatory otherwise the DMA will incorrectly process the relevant request signal and will access the cor responding I O module too soon Synchronization Destination D DMA Requ SPI1 SPI TXDMA gt D DELAY 4 Synchronization Destination D DMA Requ UART_UARTTXINTR gt D_DELAY gt 5 Synchronization Source S Requ SPI1_SPI1RXDMA gt S_DELAY gt 0 Synchronization Source S DMA Requ UART_UARTRXINTR gt 5 DELAY gt 0 86 Preliminary User s Manual 17988 1 10 00 Chapter 8 Interrupt Controller The interrupt controller ICU on ERTEC 200 supports the FIQ and IRQ interrupt levels of the ARM946E S processor An interrupt controller with 8 interrupt inputs is implemented f
184. gister 0 low 4000 2108H RELDO_HIGH 0000 FFFFH Reload register 0 high 4000 210CH RELD1_LOW 0000 FFFFH Reload register 1 low 4000 2110H RELD1_HIGH 0000 FFFFH Reload register 1 high 4000 2114H WDOGO FFFF FFFFH Watchdog timer 0 counter register 4000 2118H WDOG1 FFFF FFFFH Watchdog timer 1 counter register Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary User s Manual A17988EE1V1UMO0 179 Chapter 15 Watchdog Timers 15 3 Detailed Watchdog Register Description Figure 15 3 Watchdog Control Status Register CTRL STATUS 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved 1 0 Bit position Bit name Function Key bits Key bits Must be written with 9876H in order to make a write access effective read 0000H Reserved Status Counter 1 Represents the current status of watchdog timer 1 counter Status Counter 1 Watchdog timer 1 counter status Status_ Watchdog 1 has not expired initial value Counter 1 Watchdog 1 has expiredNote Note This bit can only be read as 1 when the Run xStop Z1 bit is set Status Counter 0 Represents the current status of watchdog timer 0 counter Status Counter 0 Watchdog timer 0 counter status Status_ Watchdog 0 has not expired initial value Counte
185. gister 1 2 2 Bit position Bit name Function RORIE Receive FIFO overrun interrupt enable RORIE Receive FIFO overrun interrupt enable FIFO overrun display interrupt 55 ROR INTRNete 1 js disabled when this bit is deleted the SSP INTR interrupt is also deleted if this interrupt was currently being enabled initial value FIFO overrun display interrupt SSP ROR INTR is enabled TIE Transmit FIFO interrupt enable Transmit FIFO interrupt enable Transmit FIFO half full or less interrupt SSP TX INTRNete 2 is disabled initial value Transmit FIFO half full or less interrupt SSP TX INTR is enabled RIE Receive FIFO interrupt enable Receive FIFO interrupt enable Receive FIFO half full or less interrupt SSP INTRNete is disabled initial value Receive FIFO half full or less interrupt SSP RX INTR is enabled Notes 1 The SSP INTR interrupt is mapped to the IRQ11 input of the IRQ interrupt controller 2 The interrupts 55 TX INTR and SSP RX INTR are combined wired OR to the SSP INTR interrupt that is wired to the IRQ10 input of the IRQ interrupt controller Figure 13 4 SSPDR SPI1 FIFO Data Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value Data 4000 2208H xxxxH Data 15 0 Data R W Accesses the first position of the transmit receive FIFOs when read the receive FIFO is accessed when written the transmit FIFO is ac
186. gure 17 9 AHB Timeout Master Register QVZ_AHB_M 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 14 QVZ QVZ QVZ pu reserved AHB AHB AHB DMA IRT LBU 946 Bit position Bit name Function Reserved QVZ_AHB_DMA Indicates whether the DMA controller was master during the incorrect multilayer AHB access QVZ_AHB_DMA QVZ_AHB_DMA DMA bus mastership DMA controller was not bus master initial value DMA controller switch was bus master QVZ AHB IRT Indicates whether the IRT switch was master during the incorrect multilayer AHB access QVZ AHB IRT IRT switch was not bus master initial value IRT switch was bus master QVZ AHB LBU Indicates whether the LBU block was master during the incorrect mul tilayer AHB access QVZ AHB LBU LBU block was not bus master initial value LBU block was bus master QVZ AHB ARM946 Indicates whether the ARM946E S CPU core was master during the incorrect multilayer AHB access ARM946 2 5 was not bus master initial ARM946E S was bus master Preliminary User s Manual A17988EE1V1UM00 249 Chapter 17 System Control Registers Figure 17 10 APB Timeout Address Register QVZ_APB_ADR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value QVZ_APB_ADR 4000 2634H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QVZ_APB_ADR 1 QVZ_APB_ADR 31 0 31 0 QVZ re Ar Holds the address i
187. gure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 List of Figures Pin Configuration of ERTEC 200 304 Pin Plastic FBGA 19 mm x 19 mm 22 Internal Block Diagrar onerare eee iei o de eim eve 29 ARM 946E S Processor System in ERTEC 200 49 Revision Code and Status Register 0 65 Async Wait Cycle Config Register 66 SDRAM Bank Config Register 1 2 sse 67 SDRAM Refresh Control Register 69 Async Bank 3 0 Config Registers 1 2 sse 70 Extended Config Register 1 2 sse nennen 72 Write to External Device Active Data 74 Read from External Device Active Data 74 Write to External Device Using RDY PER Active Data 75 32 bit Write to External 8 bit Device Active Data 75 External Memory Connection Example enne 76 DMACO SRC ADDR REG DMA Source Address Register 81 DMACO DEST ADDR REG DMA Destination Address Register 81 DMACO CONTR REG DMA Con
188. half duplex mode the PHY transmits and simultaneously receives in order to provide loopback of the transmitted signal Refer to section 14 2 1 3 of IEEE802 3 7 Oollision presence function half duplex mode only 8 Carrier sense detection CRS is asserted only to receive activity for Full Duplex mode CRS is asserted during either packet transmission or reception for half duplex mode 1 Filter and Squelch The Manchester encoded signal from the cable is fed into the transceiver s receive path via 1 1 ratio magnetics see Chapter for details of the circuit It is first filtered to reduce any out of band noise It then passes through a squelch circuit a set of amplitude and timing comparators that normally reject differential voltage levels below 300 mV and detect and recognize differential voltages above 585 mV 2 Jabber detection Jabber is a condition in which a station transmits for a period of time longer than the maximum permis sible packet length usually due to a fault condition that results in holding the TX EN P 2 1 signal active for a long period Special logic is used to detect the jabber state and to abort the transmission to the line within 45 ms The maximum time of of unjab is 350 ms Once TX EN P 2 1 is deasserted the logic resets the jabber condition Basic status register 1 indicates that a jabber condition was detected details about the register functions are given in Chapter 16 3 3 SQE test function
189. hen all of the set ISR bits have been reset by the appropriate number of EOI commands Afterwards low priority interrupts that occurred in the meantime and were entered in the IRREG register can be processed in the priority logic During one or more accepted interrupts the priority distribution of the IRQ FIQ interrupt inputs must not be changed because the ICU can otherwise no longer correctly assign the EOI commands An IRQ FIQ request is accepted by the CPU by reading the IRVEC FIVEQ register This register contains the binary coded vector number of the highest priority interrupt request at the moment Each of the two interrupt vector registers can be referenced using two different addresses The interrupt controller interprets the reading of the vector register with the first address as an interrupt acknowledge This causes the sequences for this interrupt to be implemented in the ICU logic Reading of the vector register with the second address is not linked to the acknowledge function This is primarily useful for the debugging functions in order to read out the content of the interrupt vector register without starting the acknowledge function of the interrupt controller 8 7 IRQ Interrupts as FIQ Interrupt Sources The interrupts of the FIQ interrupt controller are used for debugging monitoring of address space accesses and for the watchdog Additionally two arbitrary IRQ interrupts can be re routed to the FIQ inputs FIQ6 and FIQ7
190. hmittNete 1 3 3 V CMOS 50 kQ pull up A 16 15 pNote 1 SchmittNote 1 3 3 V CMOS 50 kQ pull down 3 3 V CMOS A 14 0 D 31 0 Schmitt 3 3 V CMOS 50 kQ pull up WR N 3 3 V CMOS RD_N 3 3 V CMOS CLK_SDRAM 3 3 V CMOS CS SDRAM N 3 3 V CMOS RAS SDRAM N 3 3 V CMOS CAS SDRAM N 3 3 V CMOS WE SDRAM N 3 3 V CMOS CS_PER 3 0 _N 3 3 V CMOS 3 0 3 0 3 3 CMOS RDY_PER_N Schmitt 50 kQ pull up DTR_N OE_DRIVER_N pNote 1 SchmittNete 1 3 8 V CMOS 3 3 V CMOS 50 kQ pull up LBU_A 20 0 Note 2 LBU_D 15 0 Note 2 Schmitt Schmitt 3 3 V CMOS 3 3 V CMOS 50 KQ pull up 50 KQ pull up LBU WR N Nete2 Schmitt 3 8 V CMOS 50 kQ pull up LBU RD N Nete2 Schmitt 3 3 V CMOS 50 kQ pull up LBU_BE 1 0 _NNote 2 LBU SEG 1 0 Note 2 Schmitt Schmitt 3 8 V CMOS 3 3 V CMOS 50 kQ pull up 50 kQ pull up LBU IRQ 1 0 Note 2 LBU RDY N Nete2 Schmitt Schmitt 3 8 V CMOS 3 8 V CMOS 50 kQ pull up 50 kQ pull up LBU CS M N Note2 LBU CS R N Nete2 Schmitt Schmitt 3 3 V CMOS 3 3 V CMOS 50 kQ pull up 50 kQ pull up GPIO 31 30 Note 2 Schmitt 3 3 V CMOS 50 kQ pull up GPIO 29 27 Note 2 Schmitt 3 3 V CMOS 50 kQ pull up GPIO 26 8 Note 2 GPIO 7 0 Note 2 Schmitt Schmitt 3 3 V
191. ifferential receive data input 100BASE TX Differential receive data input Differential FX transmit data output Differential FX transmit data output Differential FX receive data input 100BASE FX Differential FX receive data input Differential FX signal detect input Differential FX signal detect input 4 System conirol register interface A few general controls for the PHYs can be directly set via a subset of the system control registers that are described in Chapter 17 2 select the reset source for the PHYs enable auto MDIX mode select the initial start up mode of the PHY after they have been reset enable 100BASE FX mode enable PHYs and release them from power down mode check operation status of PHYs 204 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY 5 Status LED Outputs Each PHY provides six status LED outputs four of these can be made simultaneously available on GPIO 7 0 The following status can be visualized in parallel P1 2 DUPLEX N Half duplex full duplex P1 2 SPEED N 10BASE T 100BASE TX 100BASE FX P1 2 LINK STATUS N Link up link down P1 2 ACTIVITY N Receive activity transmit activity no activity Table 11 3 shows the assignment of GPIO pins to these status informations 6 Other Signals There are a few other signals mainly supply voltages related to the PHYs summarized in Table 16 8 Table 16 8 Other PHY
192. igger mode for IRQn Preliminary User s Manual A17988EE1V1UMO00 105 Chapter 8 Interrupt Controller Figure 8 20 EDGEREG IRQ Trigger Edge Select Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 EDGEREG Bit position Bit name R W Function 31 16 Reserved EDGEREG 15 0 Individual selection of positive or negative trigger edge for each IRQ interrupt input The setting of this bit is only relevant if edge trigger mode has been set for the respective IRQ input using the TRIGREG register Bit 0 corresponds to IRQO etc EDGEREG EDGEREGn n 0 15 Selection of IRQ trigger edge w Positive edge trigger for IRQn initial value Negative edge trigger for IRQn Figure 8 21 SWIRREG Software IRQ Interrupt Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWIRREG Bit position Bit name R W Function 31 16 s Reserved SWIRREG 15 0 Generation of individual IRQ interrupts by software This register is primarily used for debugging purposes SWIRREG SWIRREGn n 0 15 Generation of IRQ interrupts Do not generate interrupt request for IRQn initial value Generate interrupt request for IRQn 106 Preliminary User s Manual 17988 1 10 00 Chapter8 Interrupt Controller Figure 8 22 PRIOREGO 15 IRQ Interrupt Priority Register 3
193. igure 17 16 Figure 17 17 Figure 17 17 Figure 17 17 Figure 17 17 Figure 17 18 Figure 17 19 Figure 18 1 Figure 18 2 Figure 19 1 Figure 21 1 Auto Negotiation Advertisement Register 2 3 216 Auto Negotiation Advertisement Register 3 3 217 Auto Negotiation Link Partner Ability Register Base Page 1 2 218 Auto Negotiation Link Partner Ability Register Base Page 2 2 219 Auto Negotiation Link Partner Ability Register Next Page 1 2 220 Auto Negotiation Link Partner Ability Register Next Page 2 2 221 Auto Negotiation Expansion Register 2 222 Auto Negotiation Next Page Transmit Register 223 Silicon Revision Register sssssssssesesesssssseeeeeenneee enne nnne 224 Mode Control Status Register 1 3 sse 225 Mode Control Status Register 2 3 sees 226 Mode Control Status Register 3 3 227 Special Mode Register 1 2 nennen nnne 228 Special Mode Register 2 2 0 444 4 1 0 0 enne tenente 229 Special Control Status Indication Registerr 2 230 Interrupt Source Flag Register 1 0 2 004000 00 000 231 Interrupt Source Flag Register 2 232
194. imal number is mapped into OUI format according to Table 16 11 Table 16 11 NEC OUI Composition 9 Hex format SERIE Os Oa Os O Oo O O O O O e aO O o o o O O 0 format THe PHY ID number however is composed of the OUI bits 24 3 a 6 bit wide manufacturer model number and a 4 bit revision number Table 16 12 shows the details Table 16 12 PHY ID Number Composition 0a 02 08 0b 09 0b Oo On On to te On 0b ta 108 b to 0b ObO Vales Manufacturer model number 5 0 0 Op Op Ob Op Ob Revision number 3 0 0 ESESET 1 0 3 0 0 REG2OUIIN REGS3OUIIN ERE ER DRE The setting shown Table 16 12 is the initial value after the PHYs have been reset As both registers as writable the PHY ID number can be changed arbitrarily Preliminary User s Manual A17988EE1V1UMO00 213 Chapter 16 Multiport Ethernet PHY Figure 16 8 PHY Identifier Register REG2OUIIN 15 14 13 12 11 10 9 8 No Initial value PHY ID Number 2 0033H 7 6 5 4 3 2 1 0 PHY IOD Number PHY ID PHY ID Number 15 0 15 0 Number R W Reflects bits 18 3 of the organizationally unique identifier OUI for the ERTEC 200 see Table 16 12 for exact bit assignment Figure 16 9 PHY Identifier Register REG3OUIIN 15 14 13 12 11 10 9 8 NO Initial value PHY
195. initial value Remote fault condition has been detected 42 R Reserved Write 0p ignore on read access Pause Operation Indicates the supported pause operation functions to the link partner No pause operation supported initial value 11 10 Tui R W Asymmetric pause operation towards link partner supported Symmetric pause operation supported Symmetric pause operation and asymmetric pause operation towards local device supported Preliminary User s Manual A17988EE1V1UMO00 215 Chapter 16 Multiport Ethernet PHY Figure 16 10 Auto Negotiation Advertisement Register 2 3 Bit position Bit name Function 100BASE T4 Indicates if 100BASE T4 operation is supported 100BASE T4 100BASE T4 operation support indication 100BASE No 100BASE T4 operation support initial value T4 after device reset 100BASE T4 operation support Note The initial value after only the PHY has been reset is selected by the contents of the PHY MODE field in the PHY CONFIG register 100BASE TX Full Duplex Indicates if 100BASE TX full duplex operation is supported 100BASE TX Full No 100BASE TX full duplex operation support Duplex initial value after device reset 100BASE TX full duplex operation support Note Theinitial value after only the PHY has been reset is selected by the contents of the Pn PHY MODE field in the PHY CONFIG register 100BASE TX Indicates if 100BASE TX oper
196. interrupt controller The incorrect access address is stored in the QVZ AHB ADR system control register and the associated access type HBURST HSIZE HWRITE is stored in the QVZ AHB CTRL system control register The master that caused the access error is stored in the QVZ AHB M register In case of an access violation by the LBU as an AHB master an interrupt request is also enabled and stored in the IRT macro Additionally an LBU_IRQO interrupt is issued to the external host If more than one AHB master causes an access violation simultaneously within a single AHB clock cycle only the violation of the highest priority AHB master is protocoled in the registers see Table 4 1 Diagnostic registers QVZ ADR QVZ AHB CTRL and QVZ AHB M remain locked for subsequent access violations until the QVZ AHB CTRL register has been read 20 2 APB Bus Monitoring The APB address space is monitored on the APB bus If incorrect addressing is detected in the APB address space access to the APB side and AHB side is terminated with an OKAY response because the APB bus does not recognize response type signalling An FIQ interrupt is triggered at input FIQ1 of the ARM946E S interrupt controller The incorrect access address is placed in the QVZ ADR system control register The QVZ APB ADR system control register is locked for subsequent address violations until it has been read Preliminary User s Manual A17988EE1V1UMO00 271 Chapter 20 Address S
197. interrupt vector initial value IRVEC 3 0 Number of the currently pending valid IRQ interrupt vector with the highest priority IRVEC 3 0 Interrupt vector number Valid IRQO with highest priority pending Valid IRQ15 with highest priority pending or default vector initial value Preliminary User s Manual A17988EE1V1UMO0 93 Chapter 8 Interrupt Controller Figure 8 2 Interrupt Vector Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Vector ID 5000 0004 FFFF FFFFH 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 Vector ID FIVEC Bit position Bit name Function Vector ID 28 0 Differentiates valid FIQ interrupt vectors from the default FIQ vector Vector ID Vector ID 28 0 FIQ interrupt vector identification 0000 0000H Valid FIQ interrupt vector pending 1FFF FFFFH Default interrupt vector initial value FIVEC 2 0 Number of the currently pending valid FIQ interrupt vector with the highest priority FIVEC 2 0 Interrupt vector number 000 Valid FIQO with highest priority pending Valid FIQ7 with highest priority pending or default vector initial value 94 Preliminary User s Manual 17988 1 10 00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 Bit position Chapter 8 Interrupt Controller Figure 8 3 LOCKREG IRQ Interrupt Priority Lock Register 12 11 10 reserved B
198. ion 31 16 Reserved MASKREG 15 0 Individual masking of IRQ interrupt inputs Bit 0 corresponds to IRQO etc MASKREGn n 0 15 Masking of IRQ interrupt inputs Interrupt request IRQn enabled MASKREG Interrupt request IRQn masked initial value 104 Preliminary User s Manual 17988 1 10 00 Chapter8 Interrupt Controller Figure 8 18 ISREG IRQ Interrupt In Service Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 0060H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISREG Bit position Bit name Function 31 16 Reserved ISREG 15 0 Individual indication of IRQ interrupt requests that have been confirmed by the CPU Bit 0 corresponds to IRQO etc ISREGn n 0 15 Confirmation of IRQ interrupt request Interrupt request IRQn not confirmed initial value Interrupt request IRQn has been confirmed Figure 8 19 TRIGREG IRQ Trigger Mode Select Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 0064H 0000 0000H 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 7 TRIGREG Bit position Bit name R W Function 31 16 Reserved TRIGREG 15 0 Individual selection of edge or level trigger mode for each IRQ interrupt input Bit 0 corresponds to IRQO etc TRIGREG TRIGREGn 0 15 Selection of IRQ trigger mode Ob Edge trigger mode for IRQn initial value Level tr
199. ion Write protection for watchdog Watchdog interrupt on the FIQ interrupt controller Preliminary User s Manual 17988 1 10 00 Chapter 1 Introduction 1 3 Ordering Information Device Part Number Package 800261 1 523 2 200 P FBGA304 19 19 mm 800261 1 523 2 Remark Products with A at the end of the part number lead free products Preliminary User s Manual A17988EE1V1UMO00 21 Chapter 1 Introduction 1 4 Pin Configuration Figure 1 1 Pin Configuration of ERTEC 200 304 Pin Plastic FBGA 19 mm x 19 mm o0000090000000000000 7 AWURNLJIGECA INDEX MARK VT P MK HFODB Table 1 1 Pin Configuration of ERTEC 200 1 5 vun Pin Name MM Pin Name A21 GND Core B1 GND IO B2 A6 CS PER2 N B4 0 26 5 RD_N GND IO B6 5 VDD IO RESET_N VDD IO GPIO30 GPIO21 SPH SFRMOUT GPIO25 TGEN OUT1 N GND IO GPIO27 GPIO16 SPI1_SSPCTLOE GPIO24 PLL EXT IN N VDD IO GPIO18 SPI1 SSPRXD REF CLK F CLK GPIO12 UART CTS N CLKP A GPIOS UART RXD GPIO13 VDD IO GPIO10 UART DCD N GPIO4 P1 LINK LED GPIO8 UART TXD GND IO GPI06 P1 RX LED_N P1 TX LED_N P1 ACTIVE LED_N
200. is ignored or not EWS_XAS Extended wait mode 2 ignore RDY_PER_N signal initial value 1 Check timeout condition based Async_Wait_Cycle b _Config register setting and generate IRQ if required W_SU 3 0 write strobe setup cycles Determines the number of AHB clock cycles between valid address data and chip select and falling edge of the write signal WR_N W_SU 3 0 Write strobe setup cycles n 0H EH n 1 AHB cycles 16 AHB cycles initial value W_STROBE 5 0 write strobe duration cycles Determines the number of AHB clock cycles between falling and rising edges of the write signal WR_N W_STROBE W_STROBE 5 0 Write strobe duration cycles n 0H 3EH 1 AHB cycles 3FH 64 AHB cycles initial value 70 Preliminary User s Manual 17988 1 10 00 Chapter6 External Memory Interface EMIF Figure 6 5 Async Bank 3 0 Config Registers 2 2 Bit position Bit name Function W HOLD 2 0 write strobe hold cycles Determines the number of AHB clock cycles between rising edge of the write signal WR and change of address data and chip select W HOLD 2 0 Write strobe hold cycles n 0H 6H n 1 AHB cycles 8 AHB cycles initial value SU 3 0 read strobe setup cycles Determines the number of AHB clock cycles between valid address and chip select and falling edge of the read signal RD R SU 3 0 Read strobe setup cycles n 0H EH n 1 AHB cycles FH 16 AHB cycles initia
201. is ready to operate Reserved P1_PWRUPRST Indicates whether PHY1 is ready to operate P1 PWRUPRST PHY1 is not ready to operate i e in power down mode or in start up phase initial value PHY1 is ready to operate 260 Preliminary User s Manual 17988 1 10 00 Chapter 17 System Control Registers Figure 17 19 UART Clock Section Register UART CLK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Bit position Bit name Function Reserved UART Selects operation clock for UART UART PHY operation status 50 MHz APB clock is used as UART opera UART tion clock initial value 6 MHz clock is used as UART operation clock allows setting of a baudrate of 187 5 kbps Preliminary User s Manual A17988EE1V1UMO0 261 MEMO 262 Preliminary User s Manual 17988 1 10 00 Chapter 18 ERTEC 200 Clock Supply The clock system of ERTEC 200 basically consists of four clock domains that are decoupled through asynchronous transfers these are ARM946E S together with AHB bus APB bus and IRT JTAG interface LBU interface PHYs and Ethernet MACs 18 1 Clock Supply in ERTEC 200 The required clocks are generated in the ERTEC 200 by means of an internal PLL and or through direct clock supply The following Table 18 1 provides a detailed list of the clocks Table 18 1 Ove
202. ister 1 2 Address Initial value 7 6 5 4 3 2 1 0 Bit position Bit name Function TXFE Indicates whether the transmit FIFO is empty TXFE Transmit FIFO empty flag Else Transmit FIFOs are enabled and empty or FIFOs are disabled and transmit holding registers are empty initial value RXFF Indicates whether receive FIFO is full Else initial value Receive FIFOs are enabled and full or FIFOs are disabled and receive holding registers are full TXFF Indicates whether transmit FIFO is full Else initial value Transmit FIFOs are enabled and full or FIFOs are disabled and transmit holding registers are full RXFE Indicates whether receive FIFO is empty Else Receive FIFOs are enabled and empty or FIFOs are disabled and receive holding registers are empty initial value BUSY Indicates that the UART is busy Else Sending data is in progress or transmit FIFO is not empty or both Preliminary User s Manual A17988EE1V1UMO00 147 Bit position Chapter 12 Asynchronous Serial Interface UART Figure 12 8 UARTFR Register 2 2 Bit name Function DCD DCD This flag reflects the inverse logical level of the UART DCD_N input pin DSR DSR This flag reflects the inverse logical level of the UART DSR_N input pin 148 CTS eS This flag reflects the inverse logical level of the UART CTS N input pin Preliminary User s Manual 17988 1 1
203. ister setting Slow timing for boot operation Timeout monitoring can be selected Supports the following asynchronous devices SRAM Flash memory ROM External I O devices Care must be taken when configuring the asynchronous access timing The maximum asynchronous access duration must not exceed the time between two refresh cycles because otherwise an SDRAM refresh may get lost It must also be taken into account that a 32 bit access to an 8 bit external device requires four sequential accesses that are not interruptible for an SDRAM refresh 64 Preliminary User s Manual 17988 1 10 00 6 1 Address Assignment of Registers Chapter6 External Memory Interface EMIF The EMIF registers are 32 bits wide The registers can be written to with 32 bit accesses only Table 6 2 gives an overview of all external memory interface control registers Address 7000 0000H Table 6 2 Register Name Revision Code and Status 32 bit Initial value 0000 0100H External Memory Interface Control Registers Description Contains revision code and status register information 7000 0004H Async Wait Cycle Config 32 bit 4000 0080H Configures number of wait cycles for asynchronous accesses 7000 0008H SDRAM Bank Config 32 bit 0000 20A0H Sets SDRAM bank configuration number of row and column addresses and latency 7000 000CH SDRAM Refresh Control 32 bit 0000 0190H Sets
204. it can only be read as 1 when the Run xStop bit is set to 1p Reserved Preliminary User s Manual A17988EE1V1UMO00 163 Chapter 14 ERTEC 200 Timers Figure 14 2 Control Status Register 0 CTRL_STATO 2 2 Bit position Bit name Function Reload Mode Timer 0 reload mode selectionN te Reload Mode Timer 0 reload mode selection Reload Timer 0 stops at value 0000 0000h initial value Mode Timer 0 is loaded with the reload register value when the timer value is 0000 0000h and the timer continues to run Note If Timers 0 and 1 are cascaded the reload mode setting of Timer 0 is irrelevant Load Load trigger for Timer 0 No effect initial value Timer is loaded with the reload register value Note Reload is executed irrespective of the Run xStop bit Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 15 to this bit is sufficient to trigger the timer 0 1 edge is not needed Run xStop Starts and stops the counter in Timer oNete Run xStop Timer 0 start stop Timer 0 is stopped initial value Run xStop Timer 0 is running Nete Note If Timers 0 and 1 are cascaded the Run xStop bit setting of Timer 0 is irrelevant 164 Preliminary User s Manual 17988 1 10 00 Chapter 14 ERTEC 200 Timers Figure 14 3 Control Status Register 1 CTRL_STAT1 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
205. it name Address Initial value 5000 0008H 0000 0000H 7 6 5 4 3 2 1 0 LOCK ENA reserved LOCKPRIO BLE Function Reserved LOCKENABLE LOCKENABLE Enables or disables lock mechanism LOCKENABLE Interrupt locking mechanism enable Interrupt locking disabled initial value Interrupt locking enabled Reserved LOCKPRIO LOCKPRIO 3 0 Specification of a priority for blocking interrupt requests of lower and equal priority LOCKPRIO 3 0 Blocked interrupt priority Interrupts with priority 0 or lower can be blocked initial value Interrupts with priority 15 or lower can be blocked Preliminary User s Manual A17988EE1V1UM00 95 31 30 29 28 27 26 25 24 23 22 21 00 19 18 17 16 reserved 15 14 13 Bit position Chapter 8 Interrupt Controller Figure 8 4 FIQ1SREG Interrupt Select Register 12 11 10 reserved Bit name Address Initial value 5000 000CH 0000 0000H 7 6 5 4 3 2 1 0 015 ENA reserved FIQ1SREG BLE Function Reserved FIQ1SENABLE FIQ1SENABLE Enables or disables the re routing of an IRQ interrupt to FIQ6 FIQ1SENABLE Interrupt re routing mechanism enable 0 Interrupt re routing to FIQ6 disabled initial value Interrupt re routing to FIQ6 enabled Reserved 96 FIQ1SREG FIQ1SREG 3 0 Declaration of an IRQ interrupt as FIQ input FIQ6 on FIQ interrupt controller FIQ1SREG 3 0 Interrupt number selection
206. itch which enables the slave momentarily via an IDLE state after 8 consecutive data transfers burst or single access In this phase another AHB mas ter can access this slave In case of simultaneous accesses of two AHB masters to the same address the characteristics of the higher priority masters access are stored in several system control registers see section 20 1 for details 4 2 APBI O Bus All less demanding peripherals are connected to the ARM946E S processor system via the multilayer AHB bus an AHB to APB bridge and an APB bus The APB bus itself has a width of 32 bits and operates at a frequency of 50 MHz All registers in the peripheral I O blocks are memory mapped into the address space of the ARM946E S processor system Remark detailed specification of the internal bus systems of ERTEC 200 be found in the related ARM documents see page 6 56 Preliminary User s Manual 17988 1 10 00 Chapter 5 200 Memory This section presents detailed description of the memory areas of all integrated function blocks memory map depends partly on the device configuration selected during reset and partly on the block that actually accesses the memory 5 1 Memory Partitioning of ERTEC 200 The memory partitioning is explained from the position of the multilayer AHB bus Basically the AHB bus has an 32 bit address range that corresponds to 4 GBytes of memory Every potential master on the multila
207. ite control signal LBU_RD_N LBU read control signal LBU BE 1 0 N LBU byte enable LBU SEG 1 0 LBU page selection signals LBU IRQ 1 0 N LBU interrupt request signals LBU RDY N LBU ready signal LBU CS M N LBU chip select for ERTEC 200 internal resources LBU CS R N LBU chip select for page configuration registers total Four different pages within ERTEC 200 can be accessed via the LBU Each page can be set individu ally The settings for the four pages are made via the LBU page registers Five registers are available per page These registers are used for the size offset and access width settings of the page The LBU CS R Nchip select signal can be used to access the page registers The following settings are possible for each page Access size of a page between 256 Bytes and 2 MBytes with two page range registers LBU Pn RG Hand LBU Pn L with n 0 1 2 3 Offset segment of page in 4 GBytes address area with two page offset registers LBU Pn OF H and LBU Pn OF L with n 0 1 2 3 Access type data bit width with a page control register LBU Pn with n 0 1 2 3 The ERTEC 200 internal address area is accessed via the LBU CS M N chip select signal The LBU supports accesses to the address area with two separate read and write lines or with a common read write line The access type is selected via the CONFIGS input level during the active reset phase CONFIGS 0
208. l value STROBE 5 0 read strobe duration cycles Determines the number of AHB clock cycles between falling and rising edges of the read signal RD R STROBE R STROBE 5 0 Read strobe duration cycles 1 AHB cycles 64 AHB cycles initial value HOLD 2 0 read strobe hold cycles Determines the number of AHB clock cycles between rising edge of the read signal RD N and change of address and chip select HOLD 2 0 Read strobe hold cycles n 0H 6H 1 AHB cycles 8 AHB cycles initial value Reserved ASIZE 1 0 data bus width Defines the assumed width of the data bus for each chip select individually ASIZE 1 0 Data bus width 8 bit data bus 16 bit data bus 32 bit data bus initial value 32 bit data bus Remark AHB clock cycle normally has a length of 20 ns Preliminary User s Manual A17988EE1V1UMO0 71 Chapter6 External Memory Interface EMIF Figure 6 6 Extended_Config Register 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Address Initial value 14 Aly reserved SDS ATI reserved len IZE RQ Bit position Bit name Function Reserved Test mode 1 TEST_1 Test mode 1 200 us delay after system reset SDRAM power up initial value Delay after system reset is immediately terminated Normal function initial value All SDRAM accesses are misses Reserved ADS active data bus for SDRAM accesse
209. le 2 16 Table 3 1 Table 4 1 Table 5 1 Table 5 2 Table 5 3 Table 6 1 Table 6 2 Table 7 1 Table 7 2 Table 7 3 Table 8 1 Table 8 2 Table 8 3 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 9 5 Table 9 6 Table 9 7 Table 9 8 Table 10 1 Table 11 1 Table 11 2 Table 11 3 Table 11 4 Table 12 1 Table 12 2 Table 12 3 Table 12 4 Table 12 5 Table 13 1 Table 13 2 Table 13 3 Table 14 1 Table 14 2 Table 14 3 List of Tables Pin Configuration of ERTEC 200 22 Pin ddentifiGation citri i pear dete eas 27 External Memory Interface Pin enne 33 Local Bus Interface Pin eee 34 MII SMI Diagnosis Interface Pin 36 PHY Interface Pin 0 37 General Purpose I O Pin 38 UART Pin Functions 2 estne tree deze TE ete POSER e ERE 39 SPA PiN FUNG ONS araea x 39 MC PLL Pin FUNCIONS oerte u a ee dee Due 39 Clock and Reset Pin Functions 40 JTAG and Debug Interface Pin 40 Trace Port Pin Functioris 5 ied ea e dei editus 41 Power Supply Pin 41 Alternative Functions
210. lost If the UART is used the affected pins are no longer available as standard I O The baud rate gen eration is derived from the internal 50 MHz APB clock or a dedicated 6 MHz clock The data bit width for read write accesses to UART registers on the APB bus is 8 bits The following signal pins are available for the UART on ERTEC 200 Table 12 1 UART Pin Functions Pin Name Function Number of pins UART TXD UART transmit data output 1 UART RXD UART receive data input UART DCD N UART carrier detection signal UART DSR N UART data set ready signal UART CTS N UART transmit enable signal total The UART is implemented as an ARM PrimeCell M 1 010 macro This is similar to the standard UART 16C550 the functional differences between the PLO10 macro and a 16 550 as follows Receive FIFO trigger level is set permanently to 8 bytes Receive errors are stored in the FIFO Receive errors do not generate an interrupt The internal register address mapping and the register bit functions are different 1 5 Stop bits are not supported Forcing stick parity function is not supported An independent receive clock is not possible Modem signals DTR RTS and RI are not supported For a detailed description of the PLO10 macro please refer to the list of documents on page 6 Preliminary User s Manual A17988EE1V1UM00 137 Chapter 12 Asynchronous Serial Interface UART Figure 12 1 below shows the structure of
211. ls Change hold address modes selectable DMA control via hard or software End of transfer can be signalled with an interrupt Other I O Interfaces 45 bit General Purpose I O GPIO Input outputs GPIO 31 0 can be assigned on a bit by bit basis Input outputs GPIO 44 32 can be used alternatively to LBU interface All GPIOs equipped with internal pull up resistor 4 GPIO inputs are interruptible active Low level is not a supported interrupt level GPIO 31 0 can be assigned up to 4 different functions see Table 11 3 8 16 32 bit access to registers is possible UART Based ARM UART PL010 and widely 16550 compatible e SPI Supports Motorola SPI SSI and National Instruments microwire modes Programmable data frame size and bit rate Master and slave mode capability Send and Receive FIFOs with 8 16 bit entries Group and overrun error interrupts Timers Two 32 bit down counters with load reload capability 0 1 Start stop continue functions and interrupts Cascadable to a 64 bit timer and additional 8 bit prescaler selectable Timers run on 50 MHz internal clock Single 16 bit up counter with load reload capability T2 Start stop functions and interrupts Timer runs on 50 MHz internal clock Additional 32 bit fail safe F Timer Runs from external clock F_CLK Watchdog 20 32 bit count down watchdog 0 with output pin WD WDOUTO N 36 bit count down watchdog 1 Load reload funct
212. ls that are generated within the UART block and that are not routed to the ICU For details on these signals please refer to the list of documents on page 6 Preliminary User s Manual A17988EE1V1UMO00 149 12 3 GPIO Register Initialization for UART Usage Due to the fact that all UART pins are shared with GPIO pins on ERTEC 200 the GPIO registers need to be initialized properly before any of the UARTs on ERTEC 200 can be used Below two examples are given for a two wire UART and a five wire UART Table 12 4 GPIO Register Initialization Example for Two wire UART UART pin y GPIO_PORT_ GPIO_PORT_ Realized with MODE HNote MODE Note IOCTRLNete UARTTXD GPIO8 function 1 xxxx XXXX 0101 XXXX XXX XXXX 90009010 000000000 UART RXD GPIOS function 1 Table 12 5 GPIO Register Initialization Example for Five wire UART UART pin GPIO PORT GPIO PORT Realized with MODE Note MODE Note GPIO IOCTRL Nete UART TXD GPIO8 function 1 UART RXD GPIOS function 1 XXXX 01 0101 0101 XXXX VARTDED N XXXX XXXX XXXXp Xxx1 1110 XXXXp UART DSR N GPIO11 function 1 UART CTS_N GPIO12 function 1
213. n addition the address position of the D TCM must be set in the Tightly Coupled Memory Region register 50 Preliminary User s Manual 17988 1 10 00 Chapter 3 CPU Function 3 4 Memory Protection Unit MPU The memory protection unit enables the user to partition the address space of the ARM946E S proces sor into several regions and to assign various attributes to these regions A maximum of 8 regions of variable size can be set If regions overlap the attributes of the higher region number apply The possible settings for each region are as follows Base address of region Size of region Cache and write buffer configuration Read write access enable for privileged users users They have to be made in the following registers of the ARM946E S e Register 2 Cache configuration register Register 3 Write buffer control register Register 5 Access permission register Register 6 Protection region base size register The base address defines the start address of the region It must always be a multiple of the size of the region Example The region size is 4 kBytes The starting address is then always a multiple of 4 kBytes Before the MPU is enabled at least one region must have been specified Otherwise the ARM946E S can enter a state that can only be cancelled by a reset The MPU can be enabled by setting Bit 0 of the CP15 control register If the MPU is locked neither the nor the D cache ca
214. n be accessed even if they are enabled 3 5 Bus Interface of ARM946E S The ARM946E S uses an AHB bus master interface to the multilayer AHB bus for opcode fetches and data transfers The interface operates at a fixed frequency of 50 MHz independently of the CPU frequency The two uni directional data buses and the address bus each have a width of 32 bits The AHB bus supports burst transfers that are typically used during cache operations To improve system performance the AHB bus master interface contains a write buffer that reduces CPU stall times during data cache misses The write buffer operation is normally transparent however there is indirect control over the write buffer using the MPU If a memory region is specified as non cacheable and non bufferable in the MPU the write buffer is effectively bypassed Preliminary User s Manual A17988EE1V1UMO0 51 Chapter 3 CPU Function 3 6 ARM946E S Embedded Trace Macrocell ETM9 An ETM9 module is connected at the ARM946E S This module permits debugging support for data and instruction traces in the ERTEC 200 The module contains all signals required by the processor for the data and instruction traces The ETM9 module is operated by means of the JTAG interface The trace information is provided outwards to the trace port via a FIFO memory A more detailed description is provided in section 21 1 Remark Details about the ARM946E S processor system and its components can be found in the relat
215. n case of an incorrect APB access Figure 17 11 Timeout Address Register QVZ_EMIF_ADR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value QVZ_EMIF_ADR 4000 2638H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QVZ_EMIF_ADR QVZ_EMIF_ADR 31 0 31 0 QVZ_EMIF_ADR Holds the address in case of an external memory access that caused a timeout 250 Preliminary User s Manual 17988 1 10 00 Chapter 17 System Control Registers Figure 17 12 Memory Swap Register MEM_SWAP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i reserve SWAP Bit position Bit name Function Reserved MEM SWAPY 1 0 Re maps alternative memories to the original internal ROM address loca tion MEM SWAP Memory mapping 00 Internal boot ROM at address 0000 OOOOH initial MEM_SWAP vee 01 External SDRAM at address 0000 0000H 10 External static memory connected to CS_PERO_N at address 0000 0000H b 11 No memory at address 0000 0000H locked cache can be mapped to 0000 0000 Preliminary User s Manual A17988EE1V1UMO00 251 Chapter 17 System Control Registers Figure 17 13 AHB Master Lock Control Register M_LOCK_CTRL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d M_LOCK_ reserve CTRL Bit position Bit name Function Reserved
216. n counters Watchdog 0 32 bit is generating an output signal on the WD WDOUTO N pin watchdog 1 36 bit generates a reset System Control Registers A bundle of specific system control registers help to configure the processor and to analyse internal problems like access right and or address range violations or timeouts Preliminary User s Manual A17988EE1V1UMO00 31 MEMO 32 Preliminary User s Manual 17988 1 10 00 2 Pin Functions 2 1 List of Pin Functions Table 2 1 External Memory Interface Pin Functions Pin Name Function Alternate Function A 23 18 External memory address bus 23 18 CONFIG 6 1 Note A 17 15 External memory address bus 17 15 BOOT 3 1 Note 14 0 External memory address bus 14 0 D 31 0 WR_N RD_N CLK_SDRAM CS SDRAM N RAS SDRAM N CAS SDRAM N WE SDRAM N CS PER 3 0 N BE 3 0 DQM 3 0 RDY PER N External memory data bus 31 0 Write strobe signal Read strobe signal Clock to SDRAM Chip select to SDRAM Row address strobe SDRAM Column address strobe to SDRAM RD WR signal to SDRAM Chip select to static memories and peripherals Byte enable signal Ready signal DTR_N ONote Direction signal for external driver or scan clock BOOTONote OE_DRIVER_N Enable signal for external driver or scan clock Note The BOOT 3 0 and CONFIG 6 1 pins are used
217. n internal sig nal called DATA VALID When it is asserted the control logic moves into a link ready state and waits for an enable from the auto negotiation block When received the link up state is entered and the transmit and receive logic blocks become active Should auto negotiation be disabled the link integrity logic moves immediately to the link up state when the DATA VALID signal is asserted Note that to allow the link to stabilize the link integrity logic will wait a minimum of 330 usec from the time DATA VALID is asserted until the link ready state is entered Should the DATA VALID input be negated at any time this logic will immediately negate the link signal and enter the link down state When the 10 100 digital block is in 10BASE T mode the link status generated from the 10Base T receiver logic 11 Link Lockup Protection During the reception of 10BASE T data the link partner may switch to 100BASE TX without starting auto negotiation In this case the PHY must recognize this de assert the link status and switch to 100BASE TX mode To achieve this a counter is activated at the beginning of every 10BASE T packet When the counter reaches the count of 157 msec and no end of packet was recognized then the link will be de asserted and the PHY will restart either auto negotiation if enabled or try to achieve a 10 BASE T link again 12 Phase Offset Indicator The latency between transmitter and receiver can lead to 5 differ
218. n t care 5000 0024H undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 don t care Don t care 81 0 W A write to this register indicates the completion of the interrupt service routine associated with the current IRQ request to the IRQ interrupt controller the value that is written to this register does not matter Figure 8 11 FIQEND End of FIQ Interrupt Signaling Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value don t care 5000 0028H undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 don t care Don t care 81 0 W A write to this register indicates the completion of the interrupt service routine associated with the current FIQ request to the FIQ interrupt controller the value that is written to this register does not matter Preliminary User s Manual A17988EE1V1UMO00 101 Chapter 8 Interrupt Controller Figure 8 12 FIQPRO 7 FIQ Interrupt Priority Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 8 7 6 5 4 3 2 1 Bit position Bit name R W Function Reserved FIQPRO 7 2 0 Sets priority of the fast interrupt request at inputs FIQO to FIQ7 of the FIQ interrupt controller FIQPRn 2 0 FIQ Interrupt request priority FIQPRO 7 000 Assigns priority 0 highest to FIQ interrupt FlQn 111 Assigns priority 7 lowest FIQ interrupt FlQn d initial value Figure 8 13 FIQISR FIQ Interrupt In
219. n the BOOT_REG register in the system control register area After start up of the processor the system branches to the appropriate boot routine based on the previ ously read boot mode selection and the download is performed After the download is complete the newly loaded functions are executed When reset has become inactive the pins BOOT 3 0 can be used as normal external memory interface pins The following actions lead to a boot operation HW reset Watchdog reset Software reset caused by setting the XRES_SOFT bit in the reset control register SCR area Table 10 1 summarizes the supported download modes the shaded area shows the default boot mode that is used when only the internal pull up down resistors at the BOOT 3 0 pins are effective Table 10 1 Supported Download Modes Selected download mode Via external ROM NOR flash with 8 bit width Via external ROM NOR flash with 16 bit width Via external ROM NOR flash with 32 bit width Fast boot via external ROM NOR flash with 8 bit width Fast boot via external ROM NOR flash with 16 bit width Fast boot via external ROM NOR flash with 32 bit width SPI e g for use with EEPROMs with serial interface UART bootstrap method LBU from external host All others Reserved Booting from NOR Flash or EEPROM with 8 16 32 bit data width via Bank 0 CS PERO Booting from serial EEPROMsS Flashes via the int
220. nal General purpose signal UART DCD N UART RXD UART TXD GPIO7 General purpose signal General purpose signal P2 RX LED N P2 TX LED N P2 ACTIVE LED P1 RX LED N P1 TX LED N P1 ACTIVE LED General purpose signal P2 LINK LED N General purpose signal P1 LINK LED N General purpose signal P2 SPEED 100LED N TX FX P2 SPEED 10LED N General purpose signal P1 SPEED 100LED N TX FX P1 SPEED 10LED N Note General purpose signal General purpose signal P2 DUPLEX LED N P1 DUPLEX LED N Primary and alternative functions for GPIO 31 0 are selected with the GPIO PORT MODE and GPIO PORT MODE L registers primary and alternative functions for GPIO 44 32 are selected with the configuration pins In this table the types are listed for the GPIO function 38 Preliminary User s Manual 17988 1 10 00 UART TXD 2 Pin Functions Table 2 6 UART Pin Functions Function UART transmit data output Alternate FunctionNote GPIO8 UART RXD UART receive data input 9 UART DCD_N UART carrier detection signal GPIO10 UART DSR_N UART data set ready signal GPIO11 UART CTS_N Note Primary and alternative UART transmit enable signal functions selected with GPIO12 the GPIO PORT MODE H GPIO PORT MODE L registers In
221. native functions that are config urable with the GPIO PORT MODE L H registers Table 11 3 Alternative Functions of GPIO 31 0 pins Function GPIO pin GPIOO GPIOO P1 DUPLEX LED N GPIO1 GPIO1 P2 DUPLEX LED N P1 SPEED 100LED P2 SPEED 100LED N GPIO4 GPIO4 P1 LINK LED_N GPIO5 GPIO5 P2 LINK LED_N GPIO6 GPIO6 P1 RX LED_N P1 TX LED_N P1 ACTIVE LED_N GPIO7 GPIO7 P2 RX LED_N P2 TX LED_N P2 ACTIVE LED_N GPIO8 GPIO8 UART TXD GPIO9 9 UART RXD GPIO10 GPIO10 UART DCD N GPIO 1 1 GPIO11 UART DSR_N GPIO12 GPIO12 UART CTS N GPIO13 GPIO13 Reserved GPIO14 GPIO14 DBGACK GPIO15 GPIO15 WD WDOUT N GPIO16 GPIO16 SPI1 SSPCTLOE GPIO17 GPIO17 SPI1 SSPOE GPIO18 GPIO18 SPI1 SSPRXD GPIO19 GPIO19 SPI1 SSPTXD GPIO20 GPIO20 SPI1 SCLKOUT 21 GPIO21 SPI1 SFRMOUT GPIO22 GPIO22 SPI1 SFRMIN DBGACK GPIO23 GPIO23 SPI1 SCLKIN Reserved GPIO24 GPIO24 PLL EXT IN N GPIO25 TGEN OUT1 N GPIO 30 26 GPIO 30 26 Reserved GPIOS31 GPIO31 DBGREQ GPIO2 GPIO2 P1 SPEED 10LED N GPIO3 GPIO3 P2 SPEED 10LED_N Remark There is no protection against the selection of non existing alternative GPIO functions implemented in this case the behaviour of ERTEC 200 is unpredictable Preliminary User s Manual A17988EE1V1UMO00 135 The function of the GPIO 44 32 pins is selected using the configuration pins 6 5 and CONFIG2 the function of th
222. nism FEFI consists of a modification to the IDLE code patterns In this mode every 16 IDLE code groups are followed by a data 0 code group If the PHY detects a FEFI pattern in its receive stream it de asserts its link status and transmits only IDLE patterns not FEFI on its transmit stream A full description of the Far End Fault Function is given in Section 24 3 2 1 in the 802 3 standard The objective of the Auto Negotiation function is to provide the means to exchange information between two devices that share a link segment and to automatically configure both devices to take maximum advantage of their abilities 192 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY 16 1 4 Auto Negotiation The auto negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller The auto negotiation function sends fast link pulse FLP bursts for exchanging information with its link partner A FLP burst consists of 33 pulse positions The 17 odd numbered pulse positions shall contain a link pulse and represent clock information The 16 even numbered pulse positions repre sent data information The data transmitted by an FLP burst is known as a Link Code Word These are fully defined in clause 28 of the IEEE 802 3 specification This core supports auto negotiation and implements the Base page defined by IEEE 802 3 It also supports the optional Next page function to get th
223. nput FX differential transmit out put 27 P 2 1 TDxN P 2 1 SDxN EXTRES P 2 1 DUPLEX LED_N P 2 1 LINK LED_N P 2 1 SPEED 100LED_N TX FX P 2 1 SPEED 10LED_N P 2 1 RX LED_N P 2 1 TX LED_N P 2 1 ACTIVE LED_N PLL EXT IN TGEN OUT1 TRACEPKT 7 0 ETMEXTOUT ETMEXTIN1 PIPESTA 2 0 TRACESYNC TRACECLK TCK TDI TMS TDO SRST N 28 Chapter 1 Introduction Table 1 2 Pin Identification 2 2 FX differential transmit out put FX differential receive input FX differential receive input FX differential SD input FX differential SD input Reference resistor 12 4 PHY LED PHY LED PHY LED PHY LED PHY LED PHY LED PHY LED MC PLL input signal MC PLL output signal Trace pins of ETM ETM output signal ETM input signal Trace pipeline status Trace sync signal ETM trace or scan clock JTAG reset JTAG clock JTAG data in JTAG test mode select JTAG data out Hardware reset for debug usage Preliminary User s Manual 17988 1 10 00 DBGREQ DBGACK TAP_SEL CLKP_A CLKP_B REF_CLK F_CLK RESET_N WD_WDOUTO_N VDD Core GND Core VDD IO GND IO PLL_AVDD PLL_AGND VDDQ PECL GND PECL DVDD 4 1 DGND 4 1 P 2 1 VDDARXTX P 2 1 VSSARX P 2 1 VSSATX 2 1 VDDAPLL VDDACB VSSAPLLCB VDD33ESD GND33ESD Debug request to ARM9 Debug acknowledge Select TAP controller
224. nsceiver for 2 channels integrated that supports the following transmission modes 10BASE T 100BASE TX 100BASE FX It can be connected to unshielded twisted pair UTP cable via external magnetics or to optical fiber via fiber PMD modules Internally on the ERTEC 200 it interfaces to the MAC layer through the IEEE 802 3 Standard Media Independent Interface MII The core has a DSP based architecture for signal equalization and baseline wander correction This helps to achieve high noise immunity and to extend UTP cable lengths The transmission modes can be configured for each port individually Beside these basic modes the following configurable features are supported as well Auto negotiation Auto MDI MDIX detection Auto polarity The PHYs comply to the following standards EEE802 3 EEE802 3u ANSI X3 263 1995 ISO IEC9314 Communication between the integrated PHYs and the integrated Ethernet MACs is realized with on chip MII interfaces Internal registers of the PHYs can be accessed via the common on chip serial management interface SMI Furthermore certain set ups for the PHYs can be programmed using the system control registers that are described in Chapter 17 A couple of output signals per channel is available to reflect the connection status via LEDs these signals are shared with GPIO pins The PHYs need a 25 MHz clock that can be provided on two alternative ways connect a 25
225. o be transmitted to the remote link partner should be written to bit 10 0 of the Auto Negotiation Next Page Transmit register 5 Disabling Auto Negotiation Auto negotiation can be disabled by setting the Auto Negotiation Enable bit in the Basic Control regis ter When Auto negotiation is disabled the speed and duplex mode settings are configured via the serial management interface 194 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY 16 1 5 Miscellaneous Function This chapter summarizes some additional functions of the PHYs 1 LED indicators Six LED signals are provided per PHY These provide a convenient means to determine the operation mode of the PHYs All LED signals are active low The LED signals are made available through the GPIO pins of the ERTEC 200 The functions of the LED signals are as follows 100BASE TX FX status This signal shows that operation speed is 100Mbps or during Auto Negotiation this signal will go inactive when the operating speed is 10Mbps or during line isolation 10BASE T status This signal shows that operation speed is 10Mbps this signal will go inactive when the operating speed is 100Mbps or during line isolation e Link status This signal shows that the PHY detects a valid link The use of the 10Mbps or 100Mbps link test status is determined by the condition of the internally determined speed selection e Full Half Duplex This signal shows whethe
226. ocal Bus Unit Address Mapping Example ee 113 LBU Register Initialization 114 32 bit Accesses in Various Address Ranges sse 115 Possible Host Accesses to ERTEC 200 sese 116 Address Assignment of LBU Registers 119 Supported Download Modes cecccceeeececeeeeeeeeceeeeeeeeecaeeeeeeeeeseaeeeseaaeeseeeeeeeeeseeeeneas 123 GPIO Pin and Related Drive 2 2 04 00 4 0 0 125 Address Assignment of GPIO Registers 2 127 Alternative Functions of GPIO 31 0 135 Alternative Functions of GPIO 44 32 136 UART Pin EUnctlonss o poire reae e bete PECORE hts 137 Baud Rates and Tolerances for 50 MHz UART Operation Clock 139 Address Assignment of UART 140 GPIO Register Initialization Example for Two wire 150 GPIO Register Initialization Example for Five wire 150 SPI Pin nctiongs coe reiten rei EIE bre Prem E aaa true are eeu due sa 151 Address Assignment of SPI1 153 GPIO Register Initialization Example for External Serial Flash Memory 160 Address Assignment of Timer 0 and Timer 1
227. ocess Auto Negotiation Enable Auto negotiation enable selection AUD Disable auto negotiation initial value after device Negotiation reset Enable Enable auto negotiation The initial value after only the PHY has been reset is selected by the con tents of the PHY MODE field in the PHY CONFIG register 208 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Figure 16 6 Basic Control Register 2 2 Bit position Bit name Function PowerDown Puts the PHYs into power down mode PowerDown Power down mode control PowerDown Normal operation initial value Enter general power down mode Isolate Isolates the PHY electrically from MII interface Isolate mode control Isolate Normal operation initial value after device reset Puts PHY into isolate mode Note The initial value after only the PHY has been reset is selected by the contents of the PHY MODE field in the PHY CONFIG register Restart Auto Negotiation Restarts the auto negotiation process Restart Restart Auto i iation Auto negotiation restart control Normal operation initial value Negotiation Restarts the auto negotiation process Note This bit is self clearing Duplex Mode Configures the PHY to half or full duplex mode the setting of this bit is irrele vant if auto negotiation is enabled Select half duplex mode inital value after device reset
228. odes are available for each interrupt input The trigger type is defined by means of the assigned bit in the TRIGREG register For the edge trigger mode setting differentiation can be made between a positive and negative edge evaluation This is set in the EDGEREG register Edge trigger with positive edge is the default trigger mode assignment for all interrupts The active level in level trigger mode is always high The interrupt input signal must be present for at least one clock cycle in edge trigger mode The input signal must be present until confirmation by the ARM946E S CPU in level trigger mode Shorter signals result in loss of the event 8 3 Masking the Interrupt Inputs Each IRQ interrupt can be enabled or disabled individually The MASKREG register is available for this purpose The interrupt mask acts only after the IRREG interrupt request register That is an interrupt is entered in the IRREG register in spite of the block in the MASKREG register After a reset all mask bits are set and thus all interrupts are disabled At a higher level all IRQ interrupts can be disabled globally via a command When IRQ interrupts are enabled globally via a command only those IRQ interrupts that are enabled by the corresponding mask bit in the MASKREG register are enabled For the FIQ interrupts only selective masking by the mask bits in the FIQ MASKREG register is possible After a reset all FIQ interrupts are disabled A detected FIQ interr
229. on 100BASE T4 Indicates if 100 4 operation is supported by the link partner 100BASE T4 100BASE T4 operation support indication 100BASE T4 100BASE T4 operation not supported by the link partner initial value 100BASE T4 operation supported by the link partner 100BASE TX Full Duplex Indicates if 100BASE TX full duplex operation is supported by the link partner 100BASE 100BASE TX Full Duplex 100BASE TX full duplex operation support ur x 100BASE TX full duplex operation not supported by the link partner initial value 100BASE TX full duplex operation supported by the link partner 100BASE TX Indicates if 100BASE TX operation is supported by the link partner 100BASE TX 100BASE TX operation support indication 100BASE TX No 100BASE TX operation not supported by the link partner initial value 100BASE TX operation supported by the link partner 10BASE T Full Duplex Indicates if 1OBASE T full duplex operation is supported by the link partner 10BASE T Full Duplex 10BASE T full duplex operation support 10BASE T 7 10BASE T full duplex operation not supported by Full Duplex E the link partner initial value 1 10BASE T full duplex operation supported by the 3 link partner 10BASE T Indicates if 1OBASE T operation mode is supported 10BASE T 10BASE T operation support 10BASE T 10BASE T operation not supported by the link partner initial value 10BASE T operation
230. or CRm field of the ARM register access instructions Separate registers implemented for instruction and data Undefined when read do not write Preliminary User s Manual A17988EE1V1UMO00 53 MEMO 54 Preliminary User s Manual 17988 1 10 00 Chapter 4 200 Bus System ERTEC 200 has two internal buses respectively bus systems High performance communication bus multilayer AHB bus O bus APB bus The following functional blocks are directly connected to the multilayer AHB bus e ARM946E S processor system Master interface IRT switch Master Slave interface Local bus unit Master interface Interrupt controller Slave interface DMA controller Master Slave interface External memory interface Slave interface AHB to APB bridge Slave interface The current AHB master can access the remaining I O devices that are connected to the APB bus via the AHB to APB bridge 4 1 Multilayer AHB Bus The multilayer AHB bus in ERTEC 200 is characterized by high bus availability and data throughput The multilayer AHB bus is a 32 bit wide bus with multiple master capability It runs at a frequency of 50 MHz and has the functionality of the ARM AHB bus see documents listed on page 6 By combina tion of multiple AHB segments to the multilayer AHB bus four AHB masters can access various AHB slaves simultaneously 1 AHB Arbiters Arbiters control the access when multiple AHB maste
231. or BURST LENGTH 1 0 and SDSIZE are shown below f SDSIZE 0 32 bit data bus BURST LENGTH 11 Full Page Read INCR S burst length 8 BURST LENGTH 10 Full Page Read INCR 5 burst length 4 BURST LENGTH 00 Burst length 1 e If SDSIZE 1 16 bit data bus BURST LENGTH 11 Full Page Read INCR S burst length 8 BURST LENGTH 10 Full Page Read INCR 5 burst length 4 BURST LENGTH 01 Burst length 2 Other settings than the ones shown above lead to malfunction of the memory controller Preliminary User s Manual 17988 1 10 00 77 Chapter6 External Memory Interface EMIF MEMO 78 Preliminary User s Manual 17988 1 10 00 Chapter 7 DMA Controller ERTEC 200 has a one channel DMA controller integrated This enables data to be transferred without placing an additional load on the ARM946E S core The supported transfer modes are summarized in Table 7 1 Table 7 1 DMA Transfer Modes Synchronisation PeripheralNote Memory Source Memory PeripheralNote Target PeripheralNote PeripheralNote Source and target Memory Memory None Note Due to the single channel structure the DMA controller can handle only one direction transmit or receive of a peripheral For full duplex operation the other direction must be serviced by soft ware The characteristics of the DMA controller are listed below AHB master interface for data transfers AHB slave interface for acce
232. or FIQ Six FIQ interrupt inputs are assigned to internal peripherals respectively function blocks of the ERTEC 200 and two interrupt inputs are available for external events Table 8 1 summarizes the possible FIQ interrupt Sources Table 8 1 FIQ Interrupt Sources Function Block Signal name Default setting Comment Watchdog Rising edge Access to a non existing address APB Rising ed bus Bng at the APB bus Note 1 Access to a non existing address at the AHB bus Note 1 Multilayer AHB Brie Rising edge Group interrupt of several blocksNote 2 PLL Status Register Rising edge EMIF QVZ PLL Loss state PLL Lock state ARM CPU Rising edge Debug receive communications channel interrupt Debug transmit communications ARM CPU Tx Rising edge channel interrupt Selectable Configurable from IRQ Rising edge User selectable from IRQ Selectable Configurable from IRQ Rising edge User selectable from IRQs Notes 1 Access to a non existing address is detected by the individual function blocks of ERTEC 200 and triggers an interrupt pulse with duration Tp 2 50 MHz For evaluation of this interrupt the connected FIQ input must be specified as an edge triggered input 2 See PLL_Stat_Reg register description in section 17 2 Preliminary User s Manual A17988EE1V1UMO00 87 Chapter 8 Interrupt Controller An interrupt controller for 16 interrupt inputs is implemented fo
233. ory interface registers DMA Not used Not used External memory interface registers Not used Not used Not used 9000 0000H FFFF FFFFH Not used Not used Not used Preliminary User s Manual A17988EE1V1UMO0 Not used 57 Chapter 5 ERTEC 200 Memory 5 2 Detailed Memory Map Description Table 5 2 below presents a more detailed description of the memory segments Memories in address ranges that are handled by external chip select signals are mirrored over the complete address range of the respective chip select However mirrored segments should not be used for addressing to ensure compatibility in case of future memory expansions When a locked or D cache and D TCM are used they can only be addressed by the ARM946E S and not by the IRT When the is used it cross fades the first 4 kBytes addresses 0000 0000H to 0000 OFFFH of the memory area The D TCM memory can be positioned flexibly in the address space of the ARM946E S with the Tightly Coupled Memory Region register of the CP15 sys tem control coprocessor Table 5 2 Detailed Description of Memory Segments 1 2 Segment Contents Boot ROM SDRAM Static memory D TCM Locked IRT switch External memory interface SDRAM Bank 0 256 MBytes 256 MBytes 256 MBytes 16 MBytes Address range 0000 0000H OFFF FFFFH 1000 0000H 1FFF FFFFH 2000 0000H 2FFF F
234. ot include the status indication signals that are shared with GPIO pins 186 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY 16 1 Functional Description This chapter gives a functional description of the integrated PHYs on ERTEC 200 based on the block diagram shown in Figure 16 1 Figure 16 1 shows a single channel both channels have identical struc ture The subsequent chapters will frequently refer to signals that are present on the MII interface between on chip PHY and on chip MAC In these cases the signal names that have been introduced in Table 2 3 will be used Note that these signals can be externally monitored when ERTEC 200 has been configured to diagnosis mode with the CONFIG 6 1 pins Figure 16 1 PHY Block Diagram gt 100BASE FX 4B 5B NRZ to NRZI MLT 3 D A TOOBASE TX encoding Scrambler converter encoding gt converter line driver Transmit Manchester 10 5 10BASE T encoding filter line driver 10BASE T wu ME 100BASE TX Manchester 10BASE T decoding receiver filter Receive 5B 4B NRZI to NRZ MLT 3 DSP GE 100BASE decoding convertor decoding lt correction 4 a adapt Equ 100BASE FX 4 M SMI Serial Management interface Control Auto negotiation
235. ot needed Run xStop Starts and stops the counter in Timer 1Note Run xStop Timer 1 start stop Run xStop Timer 1 is stopped initial value 1p Timer 1 is running Note lf Timers 0 and 1 are cascaded this setting applies to both timers 166 Preliminary User s Manual 17988 1 10 00 Chapter 14 200 Timers Figure 14 4 Reload Register for Timer 0 RELDO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 0 Reload pelea This register holds the 32 bit reload value for Timer 0 Figure 14 5 Reload Register for Timer 1 RELD1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 0 Reload Bene 10 This register holds the 32 bit reload value for Timer 1 Preliminary User s Manual A17988EE1V1UMO00 167 Chapter 14 ERTEC 200 Timers Figure 14 6 Control Register for Prescaler 0 and 1 CTRL PREDIV 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Reserved 4000 2010H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Run Run reserved E Stop i xStop V0 Bit position Bit name Function Reserved Load V1 Load trigger for Prescaler 1 Load V1 Reload for Prescaler 1 No effect initial value Prescaler 1 is loaded with the prescaler reload Load V1 register value Note Reload is executed irrespecti
236. pace and Timeout Monitoring 20 3 External Memory Interface Monitoring In case of the EMIF the external RDY_PER_N ready signal can be monitored In order to enable monitoring the Extended Wait Mode bit must be switched on in the Async BANK 0 Config to Async BANK 3 Config configuration registers If one of the four memory areas that are selected via the 5 PER 3 0 chip select outputs is addressed the memory controller of the ERTEC 200 waits for the RDY PER N input signal The monitoring duration is set in the Async Wait Cycle Config register and it is active if timeout monitoring Bit 7 is set in the Extended Config register The specified value maximum of 255 multiplied by 16 yields the monitoring time given in AHB clock cycles i e the time that the memory controller waits for the Ready signal After this time elapses an internal ready signal is generated for the memory controller and an FIQ interrupt is generated at input FIQ3 of the ARM946E S interrupt controller In addition the address of the incorrect access is stored in the QVZ EMIF ADR system control register The QVZ EMIF ADR system control register is locked for subsequent address violations until it has been read The previously set FIQ3 interrupt is then removed if timeout monitoring is reset 272 Preliminary User s Manual 17988 1 10 00 Chapter 21 Test and Debugging 21 1 ETM9 Embedded Trace Macrocell An ETM9 module is integrated in the ARM946E S of ERTEC 200
237. pipeline 8 kBytes of I cache 4 of D cache and 4 kBytes of D TCM Multilayer AHB Bus The Multilayer AHB bus is the data highway within ERTEC 200 It connects all major functional blocks with a 32 bit 50 MHz segmented bus structure that is able to run four bus transfers in par allel without blocking External Memory Interface Access to external memories is provided with a double memory controller that supports 128 MBytes of standard SDRAM with an access speed of 50 MHz and a total of 64 MBytes of static memory with one dynamic and four static chip select signals The static chip select signals can be used for SRAM Flash and peripheral devices External bus width is configurable to 16 32 bit for SDRAM and 8 16 32 bit for the static portion of the interface Access timings are individually selectable for each chip select Interrupt Controller The ARM processor core on ERTEC 200 has a normal interrupt input IRQ and a fast interrupt input FIQ With the on chip interrupt controller the interrupt processing capabilities are extended to 16 IRQs and 8 FIQs with prioritization and vectorization These interrupts are partly assigned to internal resources and partly accessible to the external world via GPIO pins IRT Switch The IRT switch block on ERTEC 200 provides two 10 100 Mbps Ethernet channels due to special control features and the large Communication SRAM of 64 kBytes all channels support real time and isochrono
238. r 0 Watchdog 0 has expiredNote Note This bit can only be read as 1 when the 5 Z0 bit is set Load Common load trigger for both watchdog timer counters Reload for watchdog timer counters No effect initial value Watchdog counters 0 and 1 are loaded with their respective reload register values Note Note Reload is executed irrespective of the Run xStop Z1 0 bits Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 1 to this bit is sufficient to trigger the timer a 0 1 edge is not needed 180 Preliminary User s Manual 17988 1 10 00 Chapter 15 Watchdog Timers Figure 15 3 Watchdog Control Status Register CTRL STATUS 2 2 Bit position Bit name Function Run xStop Z1 Starts stops watchdog timer 1 counter Run xStop Z1 Watchdog 1 start stop Watchdog 1 is stopped initial value Run xStop Z1 Watchdog 1 is running Remark f this bit is 0 the watchdog output to the reset controller inactive high and the status bit of the watchdog counter 1 is Op Run xStop 70 Starts stops watchdog timer 0 counter Run xStop ZO Watchdog 0 start stop Watchdog 0 is stopped initial value Run xStop 70 Watchdog 0 is running Remark f this bit is Op the WD WDOUTO output of the ERTEC 200 is active low the interrupt request of the watchdog is 0 and the status bit of the watchdog counter 1 is Op
239. r 19 Reset Logic of ERTEC 200 19 6 Actions when HW Reset is Active During the active HW reset phase the states of the 4 boot pins BOOT 3 0 are latched into the BOOT_REG register and the states of the 6 config pins CONFIG 6 1 are latched into the CONFIG_REG register After the hardware reset phase these pins are available as normal EMIF func tion pins Tables 19 1 and 19 2 summarize the function of the BOOT and CONFIG pins Note that BOOT and CONFIG pins are only latched in case of a PowerOn reset a hardware watchdog or soft ware reset do not have this effect Table 19 1 BOOT3 BOOT2 BOOT1 BOOTO BOOT 3 0 Pin Functions Selected download mode Via external ROM NOR flash with 8 bit width Via external ROM NOR flash with 16 bit width Via external ROM NOR flash with 32 bit width Fast boot via external ROM NOR flash with 8 bit width Fast boot via external ROM NOR flash with 16 bit width Fast boot via external ROM NOR flash with 32 bit width SPI e g for use with EEPROMs with serial interface 0 1p 1p 0 UART bootstrap method 0 1p Tp LBU from external host All others Reserved Preliminary User s Manual A17988EE1V1UM00 269 270 CONFIG 6 5 CONFIG2 Chapter 19 Reset Logic of ERTEC 200 Table 19 2 CONFIG 6 1 Pin Functions Setting 11 Op Function LBU on LBU WR N used as read write control signal LBU RDY Nis active high
240. r IRQ Of the 16 IRQ inputs 2 IRQ sources can be selected for processing as fast interrupt requests The assignment is made by specifying the IRQ number of the relevant interrupt input in the FIQ1REG FIQ2REG register The interrupt inputs selected as FIQ must be disabled for the IRQ logic All other interrupt inputs can continue to be processed as IRQs Twelve IRQ interrupt inputs are assigned to internal peripherals of the ERTEC 200 and four IRQ interrupt inputs are available for external events as they are routed to GPIO pins Table 8 2 summarizes the possible IRQ interrupt sources Function Block Timer Table 8 2 Signal name TIM_INTO TIM_INT1 IRQ Interrupt Sources Default setting Rising edge Rising edge Comment Timer 0 interrupt Timer 1 interrupt GPIO 1 0 Configurable External input ERTEC 200 GPIO 1 0 31 30 Configurable External input ERTEC 200 31 30 2 Rising edge Timer 2 interrupt UART UART_INTR High level Reserved Group interrupt UART PHYO A 1 INTERP High level Interrupt from PHYO 1 SPI1 SPI1 SSP INTR SSP ROR INTR Rising edge Rising edge Group interrupt SPI1 Receive overrun interrupt SPI1 IRT Switch IRQO SP Rising edge High priority IRT interrupt IRT Switch 1 SP Rising edge Low priority IRT interrupt Reserved DMA INT Rising edge DMA transf
241. r down reset is extended by 256us for PLL stabilization before logic is released from reset Note This PHY internal power down reset does not affect the PHY management registers Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY 7 Half Full Duplex In half duplex mode stations contend for the use of the physical medium using the CSMA CD algo rithms specified Half duplex mode is required on those media that are not capable of supporting simul taneous transmission and reception without interference like 10BASE 2 and 100BASE TA The full duplex operation mode can be used when all of the following conditions are fulfilled 1 The physical medium is capable of supporting simultaneous transmission and recep tion without interference 2 There are exactly two stations on the LAN This allows the physical medium to be treated as a full duplex point to point link between the stations 3 Both stations on the LAN are capable of and have been configured to use full duplex operation 8 Interrupt handling Each PHY can generate a collective interrupt that can be triggered by several PHY internal events these two interrupts are routed with a wired OR to the common 9 input of the ERTEC 200 interrupt controller Table 16 4 shows the events that can generate an interrupt from the PHYs Table 16 4 PHY Interrupt Events Interrupt number INT8 not used ENERGYON generated Auto negotiation
242. r the established link is operating in full or half duplex mode it is active in full duplex mode Transmit Activity This signal shows that CRS P 2 1 is active high at transmit When CRS becomes inactive the transmit activity LED output is extended by 128ms in order to improve visibility Receive Activity This signal shows that CRS P 2 1 is active high at receive When CRS becomes inactive the receive activity LED output is extended by 128ms in order to improve visibility In loopback mode this LED is not active Table 16 3 illustrates how the LED signals are made available at the GPIO pins Table 16 3 Assignment of LED Signals to GPIO Pins Function GPIO pin 1 2 3 GPIOO P1 DUPLEX LED N P1 DUPLEX LED N P2 DUPLEX LED N P1 SPEED 100LED N TX FX P1 SPEED 10LED N P2 SPEED 100LED N TX FX P2 SPEED 10LED N P1 LINK LED N P2 LINK LED N P1 RX LED N P1 TX LED N P1 ACTIVE LED N P2 RX LED N P2 TX LED N P2 ACTIVE LED N Preliminary User s Manual A17988EE1V1UMO0 195 2 Chapter 16 Multiport Ethernet PHY MDI MDI X crossover detection The PHYs automatically detect and correct MDI MDI X crossover This function can be disabled by set ting the AutoMDIX en bit in the Mode Control Status register to Oy When it is disabled crossover is corrected manually by setting the MDI mode bit in the same register accordingly 3 Polarity This core automatically detects and corrects polari
243. refresh rate indication for timeout 7000 0010H Async BANKO Config 32 bit FFF2H 7000 0014H Async BANK1 Config 32 bit FFF2H 7000 0018H 7000 001CH Async BANK2 Config Async BANKS Config 32 bit FFF2H FFF2H Configures access timing and data bus width for asynchronous chip selects C8 PER 3 0 individually 7000 0020H Extended Config 0303 0000H Sets miscellaneous other functionalities Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits 6 2 Detailed EMIF Register Description 31 30 29 28 27 26 25 24 23 22 21 Figure 6 1 19 18 17 Revision Code and Status Register 16 Address Initial value 15 14 13 12 11 10 9 8 7 MAJOR REVISION 7 0 Bit position 31 16 Bit name Reserved MAJOR REVISION 6 3 2 1 MINOR REVISION 7 0 Function Major revision code initial value 01H MINOR REVISION Preliminary User s Manual A17988EE1V1UMO0 Minor revision code initial value OOH 65 Chapter6 External Memory Interface Figure 6 2 Async_Wait_Cycle_Config Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 Bit position Bit name Function Reserved WP wait polarity Selects if RDY_PER_N signal is interpreted as active high or active low
244. rnal SPI1_SPI1RXDMA signal used for DMA transfer synchronization on the destination side initial value Internal SPI1_SPI1TXDMA signal used for DMA transfer synchronization on the destination side Internal UART_UARTRXINTR signal used for DMA transfer synchronization on the destination side Internal UART_UARTTXINTR signal used for DMA transfer synchronization on the destination side 000 001 010 011 others Reserved D WIDTH 2 0 Determines the width of the data elements to be transferred to the DMA des tinationNote D WIDT H 2 0 000 8 bit transfers to DMA destination initial value use 16 bit transfers to DMA destination DMA data element width use 32 bit transfers to DMA destination others Reserved Note Byte count and destination width D WIDTH must match up If Half word is selected in D WIDTH then bit 0 is ignored by byte count considered to be 0 If Word is selected in D WIDTH then bits 1 0 are ignored by byte count considered to be 00 Preliminary User s Manual A17988EE1V1UMO0 85 Chapter 7 DMA Controller Figure 7 4 DMACO CONF REG DMA Configuration Register 4 4 Bit position Bit name Function D DELAY 3 0 Sets the write inactive delay counter The DMA controller puts the specified number of clocks 50 MHz in between two write accesses to the DMA desti nation D DELAY D DELAY 3 0 Write inactive delay counter Do not insert delay clocks in b
245. rs try to access a slave simultaneously Each of the AHB arbiters uses the same round robin arbitration scheme The round robin arbitration scheme prevents mutual blocking of the AHB masters over a long period on the multilayer AHB bus A fixed priority scheme as shown in Table 4 1 can be configured but it is not recommended to do so because the AHB bus can potentially be blocked by a high priority master Preliminary User s Manual A17988EE1V1UMO0 55 Chapter 4 ERTEC 200 Bus System 2 AHB Master Slave Coupling As can be seen in the block diagram in Figure 1 2 not every AHB master is connected to an arbi trary AHB slave Table 4 1 shows the possible AHB masters slave communication combinations Table 4 1 Possible AHB Master Slave Combinations AHB slaves AHB External master memory DMA priority interface Interrupt controller high x AHB masters low Remark x stands for possible stands for impossible For closed loop control applications attention must be paid that AHB masters do not block each other over a long period This would be possible if for example a IRT master and ARM master want to access the same EMIF slave with a time lag In this case the ARM master would have to pause in a Wait until the IRT master enables the slave again To prevent this situation monitoring is inte grated into the AHB master interface of the IRT sw
246. rtner is next page able or not Link Part ner Next Page Able Link partner is not next page able initial value Link partner is next page able Next Page Able Indicates if the local device is next page able or not Next Page Able Local device is not next page able Local device is next page able initial value Page Received Indicates if a new page has been received 1 Page R Received No new page has been received initial value A new page has been received Link Partner Auto Negotiation Able Indicates if the link partner is auto negotiation able or not Link Part Hng Farner Auto Link partner auto negotiation ability indication 0 ner Auto R Negotiation Able M Link partner is not auto negotiation able initial value Link partner is auto negotiation able 222 Preliminary User s Manual 17988 1 10 00 Chapter 16 Multiport Ethernet PHY Figure 16 14 Auto Negotiation Next Page Transmit Register No Initial value 15 14 13 12 11 10 9 8 Next Page Reserved eod Acknowledge 2 Toggle Message Unformatted Code field 7 2001H 7 6 5 4 3 2 1 0 Message Unformatted Code field Bit position Bit name Next Page Function Next Page Indicates if next page with link information exists Next Page Next page indication No next page exists initial value Next page exists Message Page Reserved Write 0p ignore on read access Message Page Page type indi
247. rty rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC El
248. rupt vectors from the default IRQ vector Vector ID Vector ID 27 0 IRQ interrupt vector identification 000 0000H Valid IRQ interrupt vector pending FFFFH Default interrupt vector initial value IRVEC 3 0 Acknowledge of highest priority pending interrupt request by reading the associated IRQ interrupt vector number IRVEC 3 0 IRQ Interrupt vector number 0000 Valid IRQO with highest priority pending 1111 Valid IRQ15 with highest priority pending or 9 default vector initial value 98 Preliminary User s Manual 17988 1 10 00 Chapter8 Interrupt Controller Figure 8 7 FIQ Interrupt Acknowledge Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Vector ID 5000 0018H FFFF FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Vector ID FIVEC Bit position Bit name Function Vector ID 28 0 Differentiates valid FIQ interrupt vectors from the default FIQ vector Vector ID Vector ID 28 0 FIQ interrupt vector identification 0000 0000H Valid FIQ interrupt vector pending 1FFF FFFFH Default interrupt vector initial value FIVEC 2 0 Acknowledge of highest priority fast interrupt request by reading the associated FIQ interrupt vector number FIVEC 2 0 FIQ Interrupt vector number Valid FIQO with highest priority pending Valid FIQ7 with highest priority pending or default vector initial value Preliminary User s Manual A
249. rved POLSEL_GPIO31 Controls if GPIO31 input signal is inverted before interrupt controller input POLSEL_GPIO31 GPIO input inversion POLSEL GPIO31 1 is not inverted before IRQS input to ICU initial value GPIO31 is inverted before IRQ5 input to ICU POLSEL GPIO30 Controls if GPIO30 input signal is inverted before interrupt controller input POLSEL GPIO30 0 is not inverted before IRQ4 input to ICU initial value is inverted before IRQ4 input to ICU POLSEL_GPIO1 Controls if GPIO1 input signal is inverted before interrupt controller input POLSEL_GPIO1 GPIO input inversion POLSEL_ GPIO1 GPIO1 is not inverted before IRQ3 input to ICU initial value c is inverted before IRQ3 input to ICU POLSEL_GPIOO Controls if GPIOO input signal is inverted before interrupt controller input POLSEL POLSEL GPIOO GPIO input inversion GPIOO GPIOO is not inverted before IRQ2 input to ICU initial value GPIOO is inverted before IRQ2 input to ICU 132 Preliminary User s Manual 17988 1 10 00 Chapter 11 General Purpose I O GPIO Figure 11 8 GPIO2 IOCTRL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2520H 0000 1FFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIO2 IOCTRL Bit position Bit name Function 81 13 Reserved GPIO2 IOCTRL 12 0 Controls if GPIO pin is used as input or output pin
250. rview of ERTEC 200 Clocks Clock generation Module Frequency Clock source Name ARM946E S CLK_ARM int 50 100 150 MHz selectable AHB EMIF ICU Band 50 int 50 2 except MIl subsequent PLL CLK_50 CLK_100 50 and 100 MHz APB 50 50 2 and PHYs CLKP_A CLKP_B PHY CLK int 25 MHz F Timer F CLK F Clock 0 1 6666 MHz JTAG JTAG clock 0 10 2 The synchronous clocks 50 and 100 used primarily ERTEC 200 These clocks generated with an internal PLL that is in turn supplied by a 25 MHz quartz or oscillator There are two possibilities for feeding the clock Input clock is fed with a 25 MHz quartz via the CLKP_A CLKP_B pins Input clock is fed with an 25 MHz oscillator directly to the CLKP_A pin The 25 MHz input clock is internally divided by 2 and then supplied to the internal PLL The PLL however generates an internal clock of 300 MHz that is supplied to the internal clock generator This generator provides all required internal system clocks Preliminary User s Manual A17988EE1V1UM00 263 Chapter 18 200 Clock Supply The PLL generates the CLK_50 50 MHz and CLK_100 100 MHz system clocks as well as the clock for the ARM946E S This clock can be selected the CONFIG 4 3 configuration pins CONFIG 4 3 00 ARM946E S processor clock 50 MHz CONFIG 4 3 01 ARM946E
251. ry space for a specific page range and offset register setting The example is based on the initial register values after reset and the full 2 MByte segment size which can be achieved by connecting all LBU address lines of the external host processor to ERTEC 200 as shown in Figure 9 1 Selection of the segment is done by connecting the host address lines A 22 21 to the segment select inputs LBU SEG 1 0 of ERTEC 200 Table 9 4 Local Bus Unit Address Mapping Example Host address ERTEC 200 Memory area seen LBU_SEG 1 0 LBU A 20 0 internal address by externalhost 00 0000H 1010 0000H Setting 64 kBytes of Communication SRAM Range 0001 0000H 00 FFFFH 1010 FFFFH Offset 1010 0000H 01 0000 UNOR Mirrors of 64 kBytes of Com munication SRAM 1F FFFFH 1010 FFFFH 00 0000H 1000 0000H Lower 1 MByte of IRT Switch internal registers Range 0010 0000H OF FFFFH 100F FFFFH Offset 1000 0000H 10 0000H MODO Goon Mirror of lower 1 MByte of IRT Switch internal registers 1F FFFFH 100F FFFFH 00 0000H 3000 0000H Lower 2 MBytes of external memory connected to CS PERO N Range 0020 0000H Offset 3000 0000H 1F FFFFH 301F FFFFH 00 0000H 4000 2000H 2 kBytes of APB peripherals above internal boot ROM Range 0000 0800H t 0007FFH 400027FFH Offset 4000 2000H 00 0800H 4000 2000H Mirrors of 2 kBytes of APB peripherals above internal boot ROM 1F FFFFH 4000 27FFH
252. ry scan function selection between these two functions is made with the TAP_SEL input pin TAP_SEL 0 Boundary scan function selected TAP_SEL 1p Debug function selected The TAP_SEL input is equipped with an internal pull up resistor and must be at high level for normal operation of the ERTEC 200 In addition to the JTAG interface the DBGREQ and DBGACK signals are available as alternative func tion pins Due to the different debuggers an internal pull up resistor at the TRST_N JTAG pin is not included The user has to ensure the proper circuitry for the utilized debugger Preliminary User s Manual A17988EE1V1UMO00 275 The standard connector for JTAG interfaces is a low cost 20 connector with a pin spacing of 0 1 inch All JTAG pins and the two additional DBGREQ and DBGACK pins are connected here The connector pins are assigned as follows Figure 21 1 JTAG Connector Pin Assignment TDI TMS TCK RTCKNote TDO SRST_N DBGREQ DBGACK GND GND GND GND GND GND GND GND GND Note This optional pin is not supported on ERTEC 200 For connectors pinning signal description and hardware circuitry for a standard JTAG interface for the ARM Multi ICE debugger for example refer to the documents listed on page 6 In addition to the standard JTAG connector the pins can also be connected with the trace signals at a single connector For connectors
253. s With an active data bus the data bus is driven actively to high level after each access to the SDRAM in order to support the integrated pull up resistors Active data bus for SDRAM No active data bus after SDRAM accesses Active data bus after SDRAM accesses initial value ASDB active data bus for asynchronous accesses With an active data bus the data bus is driven actively to high level after each access to an asynchronous device in order to support the integrated pull up resistors Active data bus for asynchronous accesses No active data bus after asynchronous accesses Active data bus after asynchronous accesses initial value 72 Preliminary User s Manual 17988 1 10 00 Chapter6 External Memory Interface EMIF Figure 6 6 Extended_Config Register 2 2 Bit position Bit name Function Reserved Test mode 3 TEST 3 Test mode 3 Normal function initial value DTR_N is test output Reserved BURST LENGTH 1 0 SDRAM burst length BURST_LENGTH 1 0 SDRAM burst length 00 BURST_ LENGTH 01 Full Page Read INCR_S burst length 4 Full Page Read INCR_S burst length 8 initial value Reserved TRCD TCD time between the SDRAM commands Activate and read write pre charge and activate TRCD TCD Time between two SDRAM commands EE 2 AHB clocks between SDRAM commands initial value 1 AHB clock between SDRAM commands Reser
254. s available in ERTEC 200 these can be divided into two groups GPIO 31 0 32 pins shared with other peripherals that are connected to the internal ABP bus GPIO 44 32 13 pins as alternative function of the LBU interface GPIO 31 0 can be used as follows as inputs as outputs as one of maximum alternative functions watchdog F counter UART SPI1 or the ETM Depending on the internal circuitry the GPlOs may have different current drive capabilities ERTEC 200 users drives with 6 9 or 24 mA capability the relation between GPIO pin number and drive capability is summarized in Table 11 1 Table 11 1 GPIO Pin and Related Drive Capabiliy GPIO pin number Drive capability GPIO 44 42 GPIO 40 32 GPIO 31 30 GPIO 26 8 GPIO41 GPIO 7 0 GPIO 29 27 Input values are stored in the GPIO IN register output values must be written to the GPIO OUT register The direction of the I O can be programmed bit by bit in the GPIO IOCTRL register The special I O function selection can be programmed in the GPIO PORT MODE L and GPIO PORT MODE H registers and the direction input or output in the GPIO IOCTRL register GPIO 1 0 and GPIO 31 30 can also be used as external interrupt inputs They are connected to the IRQ interrupt controller of the ARM946E S An interrupt can be generated only with an active High input level rising edge or falling edge for configuration refer to Chapter 8 9 Preliminary User s Manual A1
255. s controller of the host processor In this case the address area access must be assigned as Little Endian access If an external host accesses 200 ERTEC 200 behaves like 16 bit little endian device with 8 bit and 16 bit access possibilities Table 9 7 lists all allowed access types Table 9 7 Possible Host Accesses to ERTEC 200 LBU BE1 N LBU BEO N Internal AHB access 8 bit low byte 8 bit high byte 16 bit Others Not allowed Accesses from the external host are typically asynchronous to the ERTEC 200 internal AHB clock therefore they are synchronized to the internal AHB clock Figures 9 2 and 9 3 show typical read and write sequences Figure 9 2 LBU Read from ERTEC 400 with Separate Read Control Line LBU CS R N CS M N LBU RD N N LBU 20 0 LBU SEG 1 0 Valid address LBU BE 1 0 N JJ __ LBU_RDY_N J LBU_D 15 0 r Valid data 116 Preliminary User s Manual A17988EE1V1UM00 Chapter 9 Local Bus Unit LBU Figure 9 3 LBU Write to ERTEC 400 with Separate Write Control Line LBU CS R N LBU CD M N LBU_WR_N LBU_A 20 0 LBU_SEG 1 0 K Valid address x LBU_BE 1 0 _N 2 LBU_RDY_N 2 eee 4 y Figure 9 4 LBU Read from ERTEC 400 with Common Read Write Control Line LBU_CS_R_N LBU_CS_M_N LBU_WR_N I LBU_A 20 0 LBU SEG 1 0 Valid address LBU BE 1
256. s if GPIO pin is used as input or output pin GPIO_IOCTRLn GPIO pin direction control GPIO_IOCTRL 0 is used as output Tp GPIOn is used as input initial value Figure 11 3 GPIO_OUT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value GPIO_OUT 4000 2504H 0000 0000H 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 GPIO_OUT Bit position Bit name R W Function GPIO_OUT 31 0 Data written into this register is output at the GPIO pins on a bit by bit basis under the assumption that the pin is actually configured as output GPIO OUT GPIO OUTn GPIO output data Output low level at GPlOn pin initial value Output high level at GPlIOn pin 128 Preliminary User s Manual A17988EE1V1UMO00 Chapter 11 General Purpose I O GPIO Figure 11 4 GPIO_IN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value GPIO_IN 4000 2508H xxxxH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit name GPIO IN Function GPIO IN 31 0 This register reflects the logical level at the GPIO pins on a bit by bit basis under the assumption that the pin is actually configured as input GPIO INn GPIO input data 0 Low level is applied to GPlOn High level is applied to pin Preliminary User s Manual A17988EE1V1UMO00 129 Chapter 11 General Purpose I O GPIO Figure 11 5 GPIO_PORT_MODE_L Regi
257. see Table 19 1 for possible settings Note that the boot mode cannot be changed using this register as it is a read only register 242 Preliminary User s Manual 17988 1 10 00 Chapter 17 System Control Registers Figure 17 3 Config Pin Register CONFIG_REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 40002608H 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 Bit position Bit name Function Reserved CONFIG 6 1 CONFIG Reflect the logical level of the CONFIG 6 1 pins during the active reset phase see Table 19 2 for possible settings Note that the configuration cannot be changed using this register as it is a read only register Reserved Preliminary User s Manual A17988EE1V1UMO0 243 Chapter 17 System Control Registers Figure 17 4 Reset Control Register RES_CTRL_REG 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 260CH 0000 0004H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN_W D SO XRES WD_ reserved PULSE DUR FT RE SIRT FREI Bit position Bit name Function 31 13 Reserved PULSE_DUR 9 0 Extends the duration of a software or a watchdog reset generated by watchdog timer 1 in multiples of the AHB clock period With being the AHB clock period typically 20 ns the resulting pulse duration is given by PULSE_DUR TRES PULSE 8x PULSE 1 x Remark
258. ss of the ARM946E S CPU to the DMA control registers 4 request inputs for synchronisation of the DMA controller with peripherals like UART or SPI Source and destination address must be 4 Byte aligned address bits 1 0 are ignored Transfer width can be specified independently for source and target transfer width may be smaller than the width of source or target DMA block size is specified in Bytes and must be aligned to the transfer width if a DMA transfer is configured to 32 bit transfer width the block size must be 4 Byte aligned Change address and hold address modes must be specified separately for source and target UART and SPI provide synchronisation signals to the DMA controller that can be selected in the DMACO_CONF_REG register these signals are listed in Table 7 2 Table 7 2 DMA Synchronization Signals Peripheral Source Description SPI1_SSPRXDMA RX FIFO not empty SPI1_SSPTXDMA TX FIFO empty UART_UARTRXINTR_ UART receive interrupt UART_UARTTXINTR UART transmit interrupt Preliminary User s Manual A17988EE1V1UMO00 79 Chapter 7 DMA Controller In order to be able to deal with memories as well as with FIFOs the DMA controller supports different addressing modes that are described below 1 Change Address Mode Increments or decrements the target and or source address after each transfer 8 16 32 bit The byte counter is incremented or decremented in accordance with the number of transferred
259. st be read out first and then the UARTRSR UARTECR error register The error register is not updated until the data register is read 142 Preliminary User s Manual 17988 1 10 00 Chapter 12 Asynchronous Serial Interface UART The UART line control register UARTLCR consists of 3 Bytes that are distributed over the registers UARTLCR_H UARTLCR_M and UARTLCR_L Writing the UARTLCR register is complete when UARTLCR_H has been written If one of the first two bytes is to be changed UARTLCR_H must be writ ten at the end following the change Example Write UARTLCR_L and or UARTLCR_M then write UARTLCR_H to accept the changes Write UARTLCR_H only means write and accept UARTLCR_H bits Figure 12 4 UARTLCR_H Register 1 2 7 6 5 3 1 0 Address Initial value 4 2 Bit position Bit name R W Function 7 Reserved WLEN 1 0 The word length indicates the number of data bits within a frame WLEN Word length 00 5 bit data initial value 01 6 bit data 7 bit data 8 bit data FEN FIFO modes for sending and receiving data are enabled or disabled If the FIFOs are disabled sending receiving is performed via 1 Byte holding registers actually the first elements of the FIFOs FIFO enable FIFO disable initial value STP2 Two stop bits are appended at the end of the frame when sending The receive logic does not check the received character for two stop bits STP2 Two stop bit select Ob Insert one stop bit
260. ster 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 Address Initial value 6 GPIO15 GPIO14 GPIOI3 GPIO12 GPIO11_ GPIO10_ GPIO9_ GPIO8_ PORT PORT MODE PORT MODE PORT MODE PORT MODE PORT MODE PORT MODE PORT MODE 14 13 G 15 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7 PIO6 GPIO5_ GPIO4_ GPIO3_ GPIO2_ GPIO1 GPIOQ PORT PORT MODE PORT MODE PORT MODE PORT MODE PORT PORT MODE 4000 250CH 0000 0000H Bit position Bit name Function GPIO15 PORT MODE 1 0 Selects one of max four different functions for pin GPIO15 GPIO15 PORT MODE GPIO15 function selection GPIO15 PORT 00 Select function 0 for pin GPIO15 initial value MODE 01 Select function 1 for GPIO15 10 Select function 2 for pin GPIO15 if available if available 11 Select function 3 for pin GPIO15 if available GPIOO PORT 1 0 Selects one of max four different functions for pin GPIOO GPIO0 PORT MODE GPIOO function selection GPIOO PORT _ 00 Select function 0 for GPIOO initial value 10 Select function 2 for GPIOO if available 11 Select function 3 for GPIOO if available 130 Preliminary User s Manual 17988 1 10 00 Chapter 11 General Purpose I O GPIO Figure 11 6 GPIO_PORT_MODE_H Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value G x PIO31_ GPIO30 GPIO28 GPIO28 GPIO27 GPIO26_ G
261. t remains set until the CPU returns an End of interrupt command to the interrupt controller As long as the ISR bit is set interrupts with lower priority in the priority logic of the interrupt controller are disabled Interrupts with a higher priority are allowed by the priority logic to pass and generate an IRQ FIQ signal to the CPU As soon as the CPU accepts this interrupt the corresponding ISR bit in the ISREG or FIQISR register is also set The CPU then interrupts the lower priority interrupt routine and executes the higher interrupt routine first Lower priority interrupts are not lost They are entered in the IRREG register and are processed at a later time when all higher priority interrupt routines have been executed Preliminary User s Manual A17988EE1V1UM00 89 Chapter 8 Interrupt Controller 8 6 EOI End Of Interrupt A set ISR bit is deleted by the End of Interrupt command The CPU must use the EOI command to communicate this to the interrupt controller after the corresponding interrupt service routine is processed To communicate the EOI command to the interrupt controller the CPU writes any value to the IRQEND FIQEND register The interrupt controller autonomously decides which ISR bit is reset with the EOI command If several ISR bits are set the interrupt controller deletes the ISR bit of the interrupt request with the highest priority at the time of the EOI command The interrupt controller regards the interrupt cycle as ended w
262. t values of the watchdog timers can also be read When watchdog timer 1 is read bits 35 4 are read out The status of the two watchdog timers can be checked by reading the CTRL STATUS register The output of watchdog timer 0 is routed to the input FIQO of the FIQ interrupt controller The interrupt is only active High if watchdog timer 0 is in RUN mode and if watchdog timer 0 has reached zero exception to this is a load operation with reload value 0 Preliminary User s Manual A17988EE1V1UMO00 177 Chapter 15 Watchdog Timers WD WDOUTO N output is at Low after a reset If watchdog timer 0 is set in RUN mode and the timer value does not equal zero the output changes to High The output changes to Low again when the count has reached zero The output can also be reset by stopping and then restarting watchdog timer 0 The signal can be used as an external output signal at the GPIO15 port if the alternative func tion 2 is configured for this pin The output can thus inform an external host about an imminent watch dog event The internal WDOUT1 signal is at high inactive level after a reset when watchdog timer 1 goes to Stop If watchdog timer 1 is started WDOUT1 changes to Low when the timer reaches zero It remains Low until watchdog timer 1 is loaded with the reset value again by setting the LOAD bit The exception is when reload value 0 is loaded A hardware reset is triggered internally with WDOUT1 Fig
263. ta size select Reserved initial value Reserved Reserved 4 bit data words 5 bit data words 16 bit data words Preliminary User s Manual 17988 1 10 00 155 Chapter 13 Synchronous Serial Interface SPI1 Figure 13 3 SSPCR1 SPI1 Control Register 1 1 2 15 14 13 12 11 10 9 8 7 Address Initial value 6 5 4 3 2 1 0 Bit position Bit name Function Reserved SOD The slave mode output enable bit This bit is only relevant in slave mode In Multiple slave systems the master can send a broadcast message to all slaves in the system in order to ensure that only one slave drives data at its transmit output Slave mode output enable bit SPI operates the SSPTXD output in slave mode initial value SPI1 does not have to operate the SSPTXD output in slave mode MS Master slave mode selection Device is master initial value Device is slave SSE Synchronous serial port enable bit Synchronous serial port enable IERI SPI is disabled initial value SPI1 is enabled LBM Activates the loop back mode Loop back mode activation 0 Loop back mode is disabled initial value Loop back mode is enabled the output of the transmit shift register is internally connected to the input of the receive shift register 156 Preliminary User s Manual 17988 1 10 00 Chapter 13 Synchronous Serial Interface SPI Figure 13 3 SSPCR1 5 Control Re
264. te d IRE Rachida 213 PHY ID Number 213 Generation of PHY specific Supply 236 Examples for Magnetics Selection sess 238 Address Assignment of System Control 241 Overview of ERTEC 200 2242224 0 1 0 263 3 0 Pin Functions 269 CONFIG 6 1 Pin nennen nennen nennen nnns 270 Memory Map Decode Regions in ETM9 on ERTEC 200 273 Trace Port Pin Functions rne tee eet tene oe rne d nee e 274 JTAG and Debug Interface Pin Functions 275 Preliminary User s Manual 17988 1 10 00 Chapter 1 Introduction 1 1 General ERTEC 200 is a powerful communication block for development of industrial Ethernet devices with hard real time capabilities ERTEC 200 contains a 32 bit RISC processor an external memory interface with SDRAM and SRAM controller a local bus interface a 2 channel real time Ethernet interface with inte grated PHYs synchronous and asynchronous serial ports and general purpose l Os Its robust con struction specific automation functions and openness to the IT world are distinguishing features The ERTEC 200 is housed in a 304 pin plastic FBGA package 19 mm x 19 mm 1 2 3 ARM946
265. tem in ERTEC 200 To from AHB bus D TCM System AHB I F l l Cache D Cache control control TCM control Dout Addr Din a VF System control coprocessor CP15 System control To from external coprocessors The ARM946E S processor system is a member of the ARM9 Thumb family It has a processor core with Harvard architecture Compared to the standard ARM9 family the ARM946E S has an enhanced 5vTE architecture permitting faster switching between ARM and Thumb code segments and an enhanced multiplier structure In addition the processor has an integrated JTAG interface The processor can be operated at 50 MHz 100 MHz or 150 MHz The operating frequency is set during the reset phase via the CONFIG3 and CONFIG4 configuration pins Communication with the compo nents of the ERTEC 200 takes place via the AHB bus at a frequency of 50 MHz Preliminary User s Manual A17988EE1V1UMO00 49 Chapter 3 CPU Function 3 2 Cache Structure of ARM946E S The following caches are integrated in the ARM946E S processor system 8 kBytes of instruction cache with lock function 4 kBytes of data cache D cache with lock function Both caches are 4 way set associa
266. ter Base Page 1 2 15 14 13 12 11 10 9 8 No Initial value Acknowl 100BASE 100BASE Reserved TX Full 5 0001H edge T4 duplex 10BASE T Full PRSE Selector Field T Duplex Bit position Bit name Function Next Page Indicates if additional next page with link information will follow Next Page Next Page Next page indication a See No additional next page will follow initial value Additional next page will follow Acknowledge Indicates if the link partner s link code word has been successfully received Acknowledge Next page indication Acknowl edge Not successfully received the link partner s link code word initial value Successfully received the link partner s link code word Remote Fault Indicates if a remote fault has been detected Remote Fault No remote fault condition has been detected initial value Remote fault condition has been detected Reserved Ignore on read access Pause Operation Indicates if pause operation functions is supported by the remore link partner Pause Operation Pause operation support indication Pause Operation No pause operation supported by remote link part ner initial value LU GR uj Pause operation supported by remote link partner 218 Preliminary User s Manual A17988EE1V1UMO00 Chapter 16 Multiport Ethernet PHY Figure 16 11 Auto Negotiation Link Partner Ability Register Base Page 2 2 Bit position Bit name Functi
267. ternal hardware handshake signal for DMA transfer synchroni zation on the source side S DMA ET REQ 2 0 DMA synchronization scheme Internal SPl1 SPHRXDMA signal used for DMA transfer synchronization initial value 5 DMA REQ Internal SPI1_SPI1TXDMA signal used for DMA transfer synchronization Internal UARTRXINTR signal used for DMA transfer synchronization Internal UART UARTTXINTR signal used for DMA transfer synchronization 000 Reserved S_WIDTH 2 0 Determines the width of the data elements to be transferred from the DMA source DMA data element width S_WIDTH use 8 bit transfers from DMA source initial value use 16 bit transfers from DMA source 010 use 32 bit transfers from DMA source others Reserved 84 Preliminary User s Manual 17988 1 10 00 Bit position Figure 7 4 Bit name Chapter 7 DMA Coniroller DMACO CONF REG DMA Configuration Register 3 4 Function D ADDR MODEY 1 0 Configures how the data destination address is modified during the DMA transfer D ADDR Increment destination address initial value Decrement destination address DMA destination address modification Hold destination address Reserved D DMA REQ D WIDTH D DMA REQ 2 0 Selects the internal hardware handshake signal for DMA transfer synchroni zation on the destination side D DMA REQ 2 0 DMA synchronization scheme Inte
268. the PHY registers are not set to their initial values Leaving the low power state generates an internal reset for the PHYs with a duration of 256 us for PLL stabili zation c Automatic power down The PHYs support an automatic power down mode that is entered if there is no activity on the Ethernet line To enable this mode a 1 must be written into the EDPWRDOWN bit of the Mode Control Status register of the PHYs No activity on the line will then automatically drive the PHY into the low power mode with approximately 15 mW power consumption per PHY If link pulses or data packets are detected the low power mode is automatically left with an internal reset of 256 15 and re initialization of the circuitry The first and possibly the second packet may be lost during the energy detection process No configuration data is copied from the PHY CONFIG register to the PHY at this point Automatic power down cannot be used as long as Auto negotiation is enabled therefore the Auto Negotiation Enable bit in the Basic Control register must be set to 0 for automatic power down Preliminary User s Manual A17988EE1V1UMO0 197 6 198 Chapter 16 Multiport Ethernet PHY Resetting the 5 a Hardware reset There are two methods to issue a hardware reset to the ERTEC 200 on chip PHYs the reset source can be selected using the PHY RES SEL bit in the PHY CONFIG register PHY RES SEL 0 PowerOn reset via RESET N input resets the PHYs PHY RES
269. the eyes of the external host the LBU opens a total of four configurable windows into the ERTEC 200 that allow to configure ERTEC 200 and to access all internal resources DMA Controller ERTEC 200 has a one channel DMA controller for data transfers between peripherals between memories and between peripheral and memory The DMA controller supports programmable transfer sizes and auto increment and address hold functions for data source and target A set of control registers can be accessed from the ARM946E S core to set up transfers as required The completion of a DMA transfer is signalled with an interrupt or with a status bit Other Peripherals The ERTEC 200 has several additional communication interfaces that can be accessed over the AHB to APB bridge and the subsequent APB bus These are a widely 16550 compatible UART an SPI channel three timers a watchdog an additional fail safe timer F timer and a GPIO block with up to 45 individually configurable I Os The interfaces share their pins with the GPIOs so that depending on the selected configuration a reduced number of GPIOs is available 4 GPIOs can be used as interrupt sources Clock and Power Supply The ERTEC 200 can be operated with a single external 25 MHz crystal An internal oscillator and PLL generate all required clocks for the ARM946E S the IRT block the internal buses and other peripherals Alternatively an external clock of 25 MHz can be supplied Two supply voltage
270. the hardware manual of ERTEC 200 This user s manual describes the following sections e Pin function CPU function Internal peripheral function Test function Symbols and notation are used as follows Weight in data notation Left is high order column right is low order column Active low notation Memory map address Note Caution Remark Numeric notation N capital letter before or after signal name High order at high stage and low order at low stage Explanation of Note in the text Item deserving extra attention Supplementary explanation to the text Binary Decimal XXXx Hexadecimal or Ox Prefixes representing powers of 2 address space memory capacity Data Type k kilo 210 1024 M mega 220 10242 1 048 576 G giga 230 1024 1 073 741 824 Word 32 bits Halfword 16 bits Byte 8 bits Preliminary User s Manual A17988EE1V1UMO0 5 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Document Name Document No ERTEC 200 Preliminary Data Sheet A17989EE1V1DS00 ERTEC 200 Preliminary User s Manual Boot Mode Description TPS HE A 1066 CB 12 Family L M Type Block Library 1535 4 0 00 CB 12 Family L M Type Product Data A14937EJ3VODMOO ARM946E S Technical Reference Manual DDI0201CNete
271. ther the relevant page area is addressed according to a 16 bit or 32 bit organization In case of a page with 16 bit organization each 8 bit or 16 bit access is forwarded to the AHB bus In case of a page with 32 bit organization a 32 bit read access is implemented on the AHB bus when the LOW word is read In addition the LOW word is for warded and the HIGH word is stored temporarily in the LBU A subsequent read access to the HIGH word address outputs the temporarily stored value This ensures consistent reading of 32 bit data ona 16 bit bus In the case of a 32 bit write access the LOW word is first stored temporarily in the LBU area When the HIGH word is write accessed a 32 bit access to the AHB bus is implemented Eight bit accesses are forwarded directly to the AHB bus and are therefore not useful for a 32 bit page Preliminary User s Manual A17988EE1V1UMO00 115 Chapter 9 Local Bus Unit LBU 9 5 Host Accesses to ERTEC 200 When the host uC accesses address areas of the ERTEC 200 a distinction must be made between 16 bit and 32 bit host processors The data width of the variables is defined for a 16 bit host processor The various compilers implement the accesses in any order In case of a 32 bit access by the user Software it must be ensured that the lower 16 bit half word access to the 32 bit address area precedes the upper 16 bit half word access In case of a 32 bit host processor the access order is defined by setting the external bu
272. tion 10 2 The boot loader then takes care of setting the SPI1 signal pins and loading the program code In the boot mode via the SPI1 interface the pin GPIO22 is used as a chip select signal 152 Preliminary User s Manual 17988 1 10 00 13 1 Address Assignment of SPI1 Registers Chapter 13 Synchronous Serial Interface SPI The SPI1 registers are 16 bits in width For meaningful read write accesses to the SPI1 registers 16 bit accesses are required However a byte by byte write operation is not intercepted by the hardware Address 4000 2200H Table 13 2 Address Assignment of SPI1 Registers Register Name SSPCRO Initial value Description SPI1 control register 0 4000 2204H SSPCR1 SPI1 control register 1 4000 2208H SSPDR FIFO data register 4000 220CH SSPSR SPI1 status register 4000 2210H SSPCPSR SPI1 clock prescale register 4000 2214H SSPIIR SSPICR Interrupt identification register read Interrupt clear register write 4000 2218H 4000 22FFH Reserved Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary User s Manual 17988 1 10 00 153 Chapter 13 Synchronous Serial Interface SPI1 13 2 Detailed Register Description Figure 13 2 SSPCRO SPI1 Control Register 0 1 2 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 Address Initial value SCR DSS
273. tionality 16 bit count register e Input clock hardwired to 50 MHz clock Up counting Load reload function Start stop functions Interrupt when counter state 0 is reached IRQ6 Support of different counter modes One shot mode Timer 2 is started by setting Run xStop T2 to 15 Timer 2 counts up from OH until the reload value is reached Timer 2 then stops at the reload value and an interrupt is generated at IRQ6 Setting Run xStop 2 to 0 will reset the count register TIM2 and reset the interrupt request Circular mode Timer 2 is started by setting Run xStop T2 to 1 Timer 2 counts up from until the reload value is reached Then an interrupt is generated at IRQ6 the timer is automatically reset and re starts counting from OH Setting Run xStop T2 to 0 will stop the counter reset the count register TIM2 and reset the interrupt request if active Retrigger mode Timer 2 is started by setting Run xStop T2 to 15 Timer 2 counts up from OH if the UART RXD pin is at high level If UART RXD goes to low level the timer register 2 is reset to zero and re starts counting when UARD RXD goes back to high level If Timer 2 reaches the reload value before UART RXD goes to low level an interrupt is generated at IRQ6 14 2 1 Address assignment of Timer 2 registers The timer registers are 32 bits in width For read write access of the timer registers to be meaningful a 32 bit access is required However an 8 bit or 16 bit
274. tive and have 1 kByte segments Each segment consists of 32 lines with 32 Bytes 8 x 4 Bytes The D cache has a write buffer with write back function The lock function enables the user to freeze the contents of the cache segments This function allows the code for fast routines to be kept permanently in the This mechanism can only be imple mented on a segment specific basis in the ARM946E S Both caches are locked after a reset The caches can be enabled only if the memory protection unit is enabled at the same time The can be enabled by setting Bit 12 of the CP15 control register the D cache can be enabled by setting Bit 2 of the CP15 control register Access to this area is blocked if the cache is not enabled When enabled the caches can be accessed with the full CPU speed i e with a maximum of 150 MHz 3 3 Tightly Coupled Memories A 4 kBytes data TCM D TCM is implemented in the ARM946E S processor of ERTEC 200 A TCM is a mostly small portion of memory that is close to the core that can be accessed with full CPU speed but that is not subjected to automatic control mechanisms like a cache It is typically used to keep the data for time critical routines The D TCM is locked after a reset it can be mapped to various positions in the address space of the ARM946E S and must be used together with a region of the memory protection unit The D TCM can be enabled by setting Bit 16 of the CP15 control register I
275. trol Register 82 DMACO CONF REG DMA Configuration Register 1 4 83 IRVEC IRQ Interrupt Vector Register 4 4 000 93 FIVEC FIQ Interrupt Vector Register sssssssssseeeneeenneen nennen 94 LOCKREG IRQ Interrupt Priority Lock Register ssseeeee 95 FIQISREG Interrupt Select Register 96 FIQ2SREG Interrupt Select Register 02 00 000 97 IRQACK IRQ Interrupt Acknowledge Register 0040 98 FIQACK FIQ Interrupt Acknowledge Register 2 99 IRCLVEC IRQ Interrupt Request Clear Register 100 MASKALL Mask All IRQ Interrupt Request Register 100 IRQEND End of IRQ Interrupt Signaling Register 101 FIQEND End of FIQ Interrupt Signaling Register 101 FIQPRO 7 FIQ Interrupt Priority Register 102 FIQISR FIQ Interrupt In Service Register 102 FIQIRR FIQ Interrupt Request Register 103 FIQ MASKREG FIQ Interrupt Mask Register seen 103 IRREG IRQ Interrupt Request Register sse 104 MASKREG IRQ Interrupt Mask Register 104 ISREG IRQ Interrupt In Service Register 2 105 TRIGREG IRQ Trigger Mode Sel
276. tronics Taiwan Ltd Fax 02 2719 5951 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Clarity o Technical Accuracy Organization m
277. ty reversal in wiring in 1OBASE T mode The result of polarity detection is indicated by the XPOL bit in the Special Control Status Indications register Polarity is checked at end of packets in 10BASE T When a packet is corrupted by noise the PHY may mis interprete information inside the packet as end of packet In this case the PHY may invert the polarity and a maximum of three packets is be needed to detect the valid polarity again 4 Loopback mode This ERTEC 200 PHYs support two loopback modes internal loopback and remote loopback Figure 16 3 illustrates the differences between these two modes Figure 16 3 Internal and Remote Loopback Modes gt 100BASE FX Ee 4B 5B Scrambler 77 JNRZ to gt MLT 3 soar D A 008ASE TXE een encoding __ ES converter encoding converter line driver Remote loopback i Transmit Manchester 10BASE T 10BASE T encoding t gt filter line driver iat 10 5 100 Manchester E 10BASE T r decoding im receiver filter 6 Local loopback j lt miim 5B4AB NRZI to NRZ MLT 3 DECRE 100BASE decoding re Descrambler converter 2 decoding correction lt a CREER A E adapt Equ ha 100BASE FX 196 lt
278. ue Interval that is specified with the Async Wait Cycle Control register has elapsed INIT DONE INIT DONE SDRAM initialization done Indicates if the SDRAM initialization sequence is completed INIT DONE SDRAM initialization done SDRAM initialization sequence is not completed initial value SDRAM initialization sequence is completed Reserved REFRESH RATE REFRESH RATE refresh rate Specifies the number of AHB clock cycles between 2 SDRAM refresh cycles the initial setting of 190H corresponds to a refresh cycle of 8us with 50 MHz SDRAM clock Note The refresh counter is always active even if no SDRAM is used at all In this case REFRESH RATE should be set to its maximum value in order to keep the additional bus load as low as possible Preliminary User s Manual 17988 1 10 00 69 Chapter6 External Memory Interface EMIF Figure 6 5 Bank 3 0 Config Registers 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value W_STROBE W_HOLD 7000 001xH 3FFF FFF2H 15 14 13 12 11 10 9 8 7 6 3 2 1 0 5 4 R STROBE R HOLD ASIZE gt lt Bit position Bit name Function EWS_XAS extended wait timing mode Selects if RDY_PER_N signal is treated synchronously or not EWS_XAS Extended wait timing mode 00 queat RDY_PER_N asynchronously initial value te RDY_PER_N synchronously EW extended wait mode Decides if the RDY_PER_N signal
279. ultiport Ethernet PHY Figure 16 17 Special Mode Register 2 2 Bit position Bit name Function PHY_MODE Selects between different operation modes of the PHYs PHY_MODE PHY operation mode Select 10BASE T HD Auto negotiate disabled initial value after hardware reset Select 10BASE T FD Auto negotiate disabled Select 100BASE TX FX HD Auto negotiate disa bled Select 100BASE TX FX FD Auto negotiate disa bled PHY MODE Select 100BASE TX HD advertised Auto negoti ate enabled Select 100BASE TX HD advertised Auto negoti ate enabled repeater mode PHY starts in power down mode Auto negotiate enabled AutoMDIX enabled The initial value after a software reset of the PHYs is selected by the contents of the PHY MODE field in the PHY CONFIG register Aconsistent setting of both FX MODE and PHY MODE fields is required otherwise proper operation of the PHYs cannot be guar anteed PHY_ADD Selects the internal PHY address for accesses via the management interface PHY ADD PHY address setting Address for PHY 1 is OOH address for PHY2 is 01H initial value after hardware reset Address for PHY 1 is 02H address for PHY2 is PHY_ADD m 03H Address for PHY 1 is 1EH address for PHY2 is 1FH The lowest bit of the PHY ADD fiels is ignored it is internally hard wired to Ob for PHY1 and to 1b for PHY2 Preliminary User s Manual A17988EE1V1UMO0 229
280. upt request is entered in the FIQ interrupt request register If the interrupt is enabled in the mask register processing takes place in the priority logic If the interrupt request is accepted by the ARM946E S CPU and an entry is made in the in service request register ISR the corresponding bit is reset in the IRREG register Each bit that is set in the IRREG register can be deleted via software For this purpose the number of the bit to be reset in the IRCLVEC register is transferred to the interrupt controller 8 4 Software Interrupts for IRQ Each IRQ interrupt request can be triggered by setting the bit corresponding to the input channel in the SWIRREG software interrupt register Multiple requests can also be entered in the 16 bit SWIRREG register The software interrupt requests are received directly in the IRREG register and thus treated like a hardware IRQ Software interrupts can only be triggered by the ARM946E S processor because only this processor has access rights to the interrupt controller 8 5 Nested Interrupt Structure When enabled by the interrupt priority logic an IRQ interrupt request causes an IRQ signal to be output Similarly an FIQ interrupt request causes the FIQ signal to be output to the CPU If the request is accepted by the CPU in the IRQACK or FIQACK register the bit corresponding to the physical input is set in the ISREG or FIQISR register The IRQ FIQ signal is revoked The ISR bit of the accepted interrup
281. ure 15 2 below shows the time sequence of the watchdog interrupt and the two watchdog signals Figure 15 2 Watchdog Timer Output Timing xRESET N ade MEE EE Run xStop Z1 internal Run xStop 70 t WDOUTO N WDINT internal WDOUT1 N internal generates i l reset Counter 0 0 Trigger Counters start Counter 1 0 WDOUTO N deleted by Run xStop Z0 Stop gt Start 178 Preliminary User s Manual A17988EE1V1UMO00 Chapter 15 Watchdog Timers 15 2 Address Assignment of Watchdog Registers The watchdog registers are 32 bits in width For meaningful read write accesses to the watchdog registers 32 bit accesses are required However a byte by byte write operation is not intercepted by the hardware To prevent the watchdog registers from being written to inadvertently e g in the event of an undefined computer crash the writable watchdog registers are provided with a write protection mechanism The upper 16 bits of the registers are so called key bits In order to write a valid value in the lower 16 bits the key bits must be set to 9876 yyyyH where yyyyH is the 16 bit value to be written Address 4000 2100H Table 15 1 Register Name CTRL STATUS Initial value 0000 0000H Address Assignment of Watchdog Registers Description Control status register watchdog 4000 2104H RELDO_LOW 0000 FFFFH Reload re
282. us real time communication Connection to an Ethernet network is realized with integrated PHYs that support 1OBASE T and 100BASE TX FX modes The internal MII interface between MACs and PHYs can be made available for diagnosis purposes Local Bus Interface ERTEC 200 has a local bus interface LBU to an external host controller it offers 21 address bits and 16 data bits ERTEC 200 is a slave with respect to this interface The external host can look through four configurable in size and position windows into ERTEC 200 s address space Read write control is either done with separate read and write lines or with a common read write line DMA Controller The integrated DMA controller reduces CPU load for data transfers between memory and memory respectively between memory and peripheral Address increment hold modes as well as soft or hardware handshake between the DMA transfer and the CPU are supported AHB to APB Bridge The slower peripherals of ERTEC 200 are connected to an internal 32 bit 50 MHz APB bus that can be accessed via an AHB to APB bridge from the AHB side From the programmers point of view these peripherals are memory mapped like any other Preliminary User s Manual 17988 1 10 00 9 10 11 12 13 14 Chapter 1 Introduction Boot ROM ERTEC 200 has 8 kBytes of 32 bit wide boot ROM it is pre defined with a boot loader program that supports various external boot sources external Flash via
283. ve of the Run xStop V1 bit Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 1p to this bit is sufficient to trigger the timer a 0 1 edge is not needed Run xStop V1 Starts and stops Prescaler 1 for Timer 1 Run xStop V1 Prescaler 1 start stop Prescaler 1 is stopped initial value Prescaler 1 is running Load VO Load trigger for Prescaler 0 Load VO Reload for Prescaler 0 BEEN No effect initial value Prescaler 0 is loaded with the prescaler reload register value Reload is executed irrespective of the Run xStop VO bit Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 1p to this bit is sufficient to trigger the timer 0 1 edge is not needed 168 Preliminary User s Manual 17988 1 10 00 Chapter 14 200 Timers Figure 14 6 Control Register for Prescaler 0 and 1 CTRL PREDIV 2 2 Bit position Bit name Function Run xStop VO Starts and stops Prescaler 0 for Timer 0 Run Run xStop VO Prescaler 0 start stop xStop VO 0 Prescaler 0 is stopped initial value 1p Prescaler 0 is running Remark The current counter value of the prescalers cannot be read In addition there are no status bits for the prescalers indicating when the counter state is 0 The prescalers always run continuously in Reload mode after they have been started Figure 14 7 R
284. ved SDSIZE SDRAM bank size SDSIZE SDRAMbaksze bank size SDSIZE Sa 32 bit data bus initial value EE 16 bit data bus ATIRQ asynchronous access timeout enable After the watchdog expires 256 AHB clock cycles an interrupt is triggered Setting Bit 7 to 0 deletes the interrupt request Asynchronous access timeout enable Timeout watchdog for asynchronous accesses disabled initial value Timeout watchdog for asynchronous accesses enabled Reserved Preliminary User s Manual 17988 1 10 00 73 Chapter6 External Memory Interface EMIF 6 3 Asynchronous Access Timing Examples The following Figures 6 7 to 6 10 illustrate the access timing for asynchronous devices like SRAM that are connected to the ERTEC 200 external memory interface The accesses that are asynchronous from the external viewpoint are internally synchronized to the 50 MHz clock signal CLK_50 that is shown in the subsequent timing diagrams for reference Below timings are based on a specific setting of the Async_Bank 3 0 Config registers and vary of course on the individual setting of these registers Figure 6 7 Write to External Device Active Data Bus 22225 m VEMM _ Maus sara mE CLK 50 int 23 0 D 31 0 valid address valid data CS_PER 3 0 _N W_SU 3 0 0001 W_ST
285. watchdog reset The watchdog event can be signalled to the host system via the GPIO15 pin if this pin was configured to be the WD WDOUTO N pin As in the case of a hardware reset a bit is set in the reset status register RES STAT REG This bit remains unaffected by the triggering reset function This register can be evaluated after a restart 19 4 Software Reset A software reset be triggered in ERTEC 200 by setting the XRES_SOFT bit in the reset control register RES CTRL REG this bit is not stored The subsequent reset will be extended in the same way than the watchdog reset The software reset resets the same circuitry as the hardware reset if the EN WD SOFT RES bit is set in the RES REG Again a bit is set in the reset status reg ister RES STAT REG when the reset is triggered BOOT and CONFIG pins are not re read after a software reset 19 5 IRT Switch Reset The IRT switch can be reset via a bit in an internal register The reset will be active until the bit is reset again The internal PHYs can either be reset using RESET N or using the internal PHY RES signal via the switch controller Selection between the two reset sources is done in the PHY CONFIG register with the PHY RES SEL bit As long as the SMI interface in the IRT switch in not active PHY RES N is active and keeps the PHYs in power down mode in order to reduce power consumption 268 Preliminary User s Manual 17988 1 10 00 Chapte
286. with FIQ acknowledge 5000 001CH 5000 0020H IRCLVEC MASKALL undefined 0000 0001H Interrupt request clear vector Mask for all interrupts 5000 0024 IRQEND Ox End of IRQ interrupt 5000 0028H 5000 002CH FIQEND FIQPRO Ox 0000 0007H 5000 0030H FIQPR1 0000 0007H 5000 0034H 5000 0038H FIQPR2 FIQPR3 0000 0007H 0000 0007H 5000 003CH FIQPR4 0000 0007H 5000 0040H 5000 0044H FIQPR5 FIQPR6 0000 0007H 0000 0007H 5000 0048H FIQPR7 0000 0007H End of FIQ interrupt FIQ priority registers for inputs FIQO to FIQ7 of the FIQ interrupt controller 5000 004CH 5000 0050H FIQISR FIQIRR 0000 0000H 0000 0020H FIQ in service register FIQ request register 5000 0054H FIQ MASKREG 0000 00FFH FIQ interrupt mask register 5000 0058H IRREG 0000 01xxH Interrupt request register 5000 005CH MASKREG 0000 FFFFH Interrupt mask register 5000 0060H ISREG 0000 0000H In service register 5000 0064H TRIGREG 0000 0000H Trigger select register 5000 0068H EDGEREG 0000 0000H Edge select register 5000 006CH SWIRREG 0000 0000H Software interrupt register Preliminary User s Manual A17988EE1V1UMO0 91 Chapter 8 Interrupt Controller Table 8 3 Interrupt Control Registers 2 2 Address 5000 0070H Register Name PRIOREGO Initial value 0000 000
287. yer AHB bus has its own perception of the memory range These different perceptions are summarized in Table 5 1 Start address End address 0000 0000H OFFF FFFFH 1000 0000H FFF FFFFH 2000 0000H 2FFF FFFFH Segment Table 5 1 ARM946E S Internal boot ROM 0 8 kBytes SDRAM 0 128 MBytes Static memory 0 64 MBytes D TCM 4 kBytes Locked l cache 2 4 6 kBytes IRT Switch External memory interface CS SDRAM N IRT Switch Internal boot ROM 0 8 kBytes SDRAM 0 128 MBytes Static memory 0 64 MBytes IRT Switch External memory interface CS SDRAM N Memory Area Partitioning Internal boot ROM 0 8 kBytes SDRAM 0 128 MBytes Static memory 0 64 MBytes IRT Switch External memory interface CS SDRAM N Internal boot ROM 0 8 kBytes SDRAM 0 128 MBytes Static memory 0 64 MBytes Not used External memory interface CS SDRAM N 3000 0000H 3FFF FFFFH 4000 0000H 4FFF FFFFH External memory interface CS PER 3 0 N AHB to APB bridge External memory interface CS PER 3 0 N Not used External memory interface CS PER 3 0 N AHB to APB bridge External memory interface CS PER 3 0 N AHB to APB bridge 5000 0000H 5FFF FFFFH Interrupt controller Not used Not used Not used 6000 0000H 6FFF FFFFH Not used Not used Not used Not used 7000 0000H 7FFF FFFFH 8000 0000H 8FFF FFFFH External mem

ERTEC 200 Enhanced Real-Time Ethernet Controller with 32

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