AFE5804EVM user Manual
Contents
1. EVALUATION BOARDIKIT IMPORTANT NOTICE Texas Instruments TI provides the enclosed product s under the following conditions This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use Persons handling the product s must have electronics training and observe good engineering practice standards As such the goods being provided are not intended to be complete in terms of required design marketing and or manufacturing related protective considerations including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards This evaluation board kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility restricted substances RoHS recycling WEEE FCC CE or UL and therefore may not meet the technical requirements of these directives or other related directives Should this evaluation board kit not meet the specifications indicated in the User s Guide the board kit may be returned within 30 days from th2. T RAE Paten bi b z k EI atx PURE GREEN xx 0500 00 x osa E e m TEST Ee H veco 4 Di m mr 0 TXE 1 QUEE vee ou RESET 2 E REY 1 L pwren mz USBDM we usBop TEST vee 025 305 vss RST NMI P20 ACLK A0 P24 INCLK AL 2 p22 TAO AZ P30 STEO AS Z P337SIM00 P32 S0M10 P33 UCLKO PLI TA2 TOO TOI PL6 TAL TOI TCLK gt PLS TAO TMS PLA SMCLKZTCK 2 PLZ TAL PL1 TA0 P267TA2 A6 VREF VEREF 7 PLO TACLK ADCIOCLK P23 TA1 A3 VREF VEREF P33 AT P36 6 P3S URXDO P34 UTXDO Ua B5 d E 7 VIT id 2 gt rem v e i omar e nH PURE GREEN
3. Characterizes the AFE5804 e Supports CW functionalities test e Provides 8 channel low voltage differential signal LVDS outputs from the ADC Compatible with the standard TI LVDS deserializer ADSDeSer 50EVM Communicates with a personal computer PC through a USB interface e RS 232 interface also can be configured in case users wish to control the AFE5804 with a microcontroller MSP430 programming is required e Includes multiple power management solutions for the AFE5804 and other devices e Onboard generator 0 V 1 2 V Power Supplies The AFE5804EVM requires only 5 V power supplies for operation Indicators The AFE5804EVM has four LEDs onboard as shown in Figure 1 The states of these LEDs demonstrate the normal operation of the AFE5804EVM e LED1 LED2 3 3 VA and 3 3 VD power supply indicators They show the normal operation of 3 3 V power regulators e LED 3 MCU operation indicator Flashing state can indicate the normal operation of the MSP430 when the MSP430 is appropriately programmed e LED 4 1 8 V power indicators AFE5804EVM SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Introduction Figure 1 AFE5804EVM LED Locations SLOU241 September 2008 AFE5804EVM 3 Submit Documentation Feedback 5 INSTRUMENTS Board Configuration www ti com 2 Board Configuration This section describes in detail the locations and f
4. 3044 3196 3237 3162 2978 2702 2358 5 Then select TSW1000 the chip shown Figure 1 ADC Characteristics TIChp Tswio00 Number of Bts 12 2 Complement e Frequency 1 99829102M Hz Noise Integration Start Freq 0 0 0 0 0 D 1 1 T 0 0 1 T T 1 q 6H 7M 8M 9H 10M 11H 12H 13H 14M 15H 16M 47H 18M 19M 20H Stop Freq 1 0 Inband Power 0 dem Vetage Ranges 0 Power spectrum win Qoo Qe Setup Save File About Status Message Plot Y A Remote control of Calculate and use A TSW1100 not detected Les Smee 1f using Capture Card please of Harmonics in SNR 2 y Calculate and use 5 exit and ensure it s powered and X Axis Mapping Prime Bins Only Advanced Timing recognized in the Hardware Device Mode Manager before restarting application 3 125 Notch Spurs J Reference Value to Texas Instruments TSW1100 High Speed ADC Capture System 45 TEXAS INSTRUMENTS Waveform Fin Clock Fs Sampling 40 Rate Fs Capture Capture Statistics Data 0 ReadfromFle INT 3241 Captive Re rom 9 Min Samples in File 65536 dbFS 4 67 Computations ZndHarmonic 66 87 dBFS SFDR 53 99 dBc 3rd Harmonic 58 67 dBFS THO 57 98 dBFS 4th Harmonic 87 93 dBFS SNR 62 91 dBFS Sth Harmonic 75 65 dBFS SNRD 56 77 dBFS Highest Spur 58 67
5. 5100241 September 2008 AFE5804EVM 11 Submit Documentation Feedback 5 INSTRUMENTS Schematics and Layout www ti com Figure 11 Inner Layer 1 Ground 12 AFE5804EVM SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Schematics and Layout Figure 12 Inner Layer 2 Signal 5100241 September 2008 AFE5804EVM 13 Submit Documentation Feedback 5 INSTRUMENTS Schematics and Layout www ti com Figure 13 Inner Layer 3 Power 14 AFE5804EVM SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Schematics and Layout Figure 14 Inner Layer 4 Ground 5100241 September 2008 AFE5804EVM 15 Submit Documentation Feedback 5 INSTRUMENTS Schematics and Layout www ti com P T 5 T g Figure 15 Bottom Layer Signal 16 AFE5804EVM SLOU241 September 2008 Submit Documentation Feedback 13 5 INSTRUMENTS www ti com Schematics and Layout cwour AFE5804EVM RevB 1106 2008 BO o2 L3 sie Co 12 TP4 25V G TP5 TP3 VCM 3 3VA G 6 0 C19 C20 C21 CW9 Lee 75 ADS RET ADS SDATA E ADS SCLK E R33 ADS CSZ R29 GND R30 CSZ 1 R32 VCA SDATA T DOUT R46 VCA_SCLK or R45
6. ENOB 9 138 bis Going into file read only mode Figure A 1 TSW1100 Interface INSTRUMENTS www ti com Finally click the Acquire Data button select the text file with header information and see the analysis results TSW1100 also supports analysis of noncoherent sampled data However some artifacts may be noticed during analysis The appropriate FFT window must be applied to the data Users must first follow the preceding steps to get the nonwindowed analysis results shown in Figure A 2 a Then after the appropriate FFT window is applied the correct analysis results are obtained as shown in Figure A 2 b Note that some DC artifacts can be seen in Figure A 1 b TSW 1100 for Evaluating AFE5804 5 SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Appendix A i Texas Instruments TSW1100 High Speed ADC Capture System TEXAS INSTRUMENTS ADC Characteristics TiChp Tsw1000 Number of Bits 12 2 s Complement Waveform Fin Clock Fs te Capture Capture Statistics ReadiromFie INT 3241 Capture Trigge Min 849 Samples in Fle Ns 65529 dbFS 4 67 ndHarmonic 68 94 dBF5S SFOR 5 384 3rd Harmonic 58 56 dBF5 THD 58 12 dBFS 4thHarmonic 8907 dBFS 9 327 BFS Sth Harmonic 77 41 dBFS SNRD 9 327 dBFS Highest Spur 11 89 dBc 1 257 bits Noise Integration
7. v LED4 amp FB6 R41 C36 C44 TO 19 P20 m 2 o 1 8VG Llc 22 EXT INT 23 d 5804 CH4 CH3 CH2 CH1 CH5 CH6 CH7 CH8 59 ADSDESER CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 C48 Figure 16 Top Silk Screen Layer SLOU241 September 2008 AFE5804EVM 17 Submit Documentation Feedback 5 INSTRUMENTS Schematics and Layout www ti com Spopp 8 8 E no 0 Figure 17 Bottom Silk Screen Layer 18 AFE5804EVM SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com 4 3 Bill of Materials Table 3 Bill of Materials Schematics and Layout Item MFG MFG Part Number RefDes Value or Function 1 MSP430F12321PW U3 MIXED SIGNAL MICROCONTROLLER 2 KEMET C0402C103K3RAC C9 CAPACITOR SMT 0402 CER 0 01pF 25V 10 X7R 3 KEMET C0402C104K8PAC C1 C2 C4 C5 C7 C8 CAPACITOR SMT 0402 CER 0 1uF 10V 10 X5R C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C32 C33 C34 C35 C40 C41 C42 C45 C46 C47 C51 C52 C53 C55 C56 C58 C60 C63 C64 C67 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C93 C94 C96 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C
8. 3rd Harmonic Amplitude dBF5 51 42 80 0 4th Harmonic Amplitude dBFS 96 95 _ Sth Harmonic Amplitude dBFS 71 19 6th Harmonic Amplitude 485 9th Harmonic Amplitude dBF5 91 94 Miscellaneous Test Info 795 9 A Eg 3 6 18 11 12 13 14 15 16 17 18 19 20 PGA 30 dB Vcntl 1 V Vin 11 mVpp Performance Data Output FFT 2 5 Firig 00 1 9 8 sede 18 8 cw Reference 0 00 20 0 Highest Spur 9847 95 0105 30 0 Highest SNR Spur 444580 40 0 Highest SNR Spur 10 00 D 8 i Highest spur 5 1 50 04 10 04 Fri 30 2008 Fundamental Amplitude 6 5 20 93 ine 2nd Harmonic Amplitude dBF5 48 33 3rd Harmonic Amplitude dBFS 47 95 Ath Harmonic Angltude es 780 0 Sth Harmonic Amplitude dBF5 64 57 6th Harmonic Amplitude dBF5 90 53 7th Harmonic Amplitude dBF5 76 95 8th Harmonic Amplitude dBF5 92 90 Sth Harmonic Amplitude dBF5 82 67 Miscellaneous Test Info 1 COND VE DR ERU RR RE pear 8 9 18 11 12 13 15 15 16 17 18 19 20 b PGA 30 dB Vcntl 0 34 V Vin 290 mVpp Figure 18 Typical Performances of AFE5804 As Figure 18 shows the SNR degrades as the gain increases the HD degrades as the input signal increases 22 AFE
9. 2 25 500 22 STEWARD HIO805R800R 00 FB6 FB7 FB9 FB10 FB13 FERRITE SMT 0805 80 Q at 100MHz FB14 FB15 FB16 FB17 FB18 FB19 FB20 FB21 23 STEWARD LI1206H151R 00 FB5 FERRITE SMT 1206 150 Q at 100MHz 0 8A 24 MOLEX 39357 0003 P2 HEADER THRU POWER 3P 3 5MM EUROSTYLE 25 QTH 040 01 L D DP A P26 HEADER SMT 80P 0 5mm FEM DIFF PAIR RECEPTACLE 168H 26 SAMTEC SSQ 104 02 F D P9 HEADER THU 8P 2x4 100LS FEM VERT 194TL 27 TSW 103 08 G D P6 P10 HEADER THU 6P 2x3 MALE DUAL ROW 100LS 200TL 28 SAMTEC TSW 107 07 G D P7 HEADER THU 14P 2x7 MALE DUAL ROW 100LS 100TL 29 SAMTEC TSW 108 07 G D P16 HEADER THU 16P 2x8 MALE DUAL ROW 100LS 100TL UNINSTALLED 30 TYCO 103321 2 P3 P8 P12 P21 P23 HEADER W SHUNT 2P 100LS ELECTRONICS SLOU241 September 2008 Submit Documentation Feedback AFE5804EVM 19 Schematics and Layout TEXAS INSTRUMENTS www ti com Table 3 Bill of Materials continued Item MFG MFG Part Number RefDes Value or Function 31 MOLEX 22 23 2021 P P4 P24 MALE 2PIN 100CC W FRICTION LOCK 32 MILL MAX 350 10 103 00 006 P13 P18 P22 HEADER THU MAL 0 1LS 3P 1x3 284H 110TL 33 MOLEX 22 23 2041 P1 4P VERT FRICTION LOCK 34 TYCO 4 103239 0x3 P5 P11 P14 P15 P19 P20 HEADER THU MAL 0 1LS 3P 1x3 ELECTRONICS 35 Tl AFE5804 DUT1 AFE5804 8 CH ULTRASOUND
10. state machine is enabled The AFE5804 is operated using only one SPI port ADS SPI port e P15 RST pin connects to H4 in the default mode through 0 resistors e P16 Debug port for monitoring and ADS SPI signals e P19 Tl internal use Connects to 3 3 VD e P20 INT EXT reference mode selection 3 3 VD for the internal reference mode default GND for the external reference mode P22 Uses onboard 40 MHz clock or external clock through J13 The default mode uses the onboard clock P23 Power on onboard 40 MHz clock generator Default is on e P18 Because U4 is uninstalled this jumper must be set as Figure 4 shows e 51 MSP430 reset button SW1 SW2 CW outputs summation switch Individual CW output current can be summed through the IV translator U1 when its corresponding switch is set to ON Test Points Multiple test points are provided on the EVM Detail descriptions follow Under normal operation mode it is unnecessary to measure voltages at most of these test points e TP1 GND 2 GND e e TP4 Vontl test point TP5 GND 6 GND TP7 Test point TI internal only e TP8 5 V 9 e TP10 GND e TP11 5 V AFE5804EVM SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Board Operation 3 Board Operation This section describes how to operate the AFE5804EVM for evaluation purposes Both software and hardware
11. 1 TEXAS User s Guide INSTRUMENTS SLOU241 September 2008 AFE5804EVM AFE5804EVM is an evaluation tool designed for the ultrasound analog front end AFE device AFE5804 In order to deserialize the outputs of the AFE5804 use of the ADSDeSer 50EVM during evaluation is also recommended Contents 1 INTODUCHOMN DANN ou puan MT x 2 1 1 2 1 2 lise Ie 2 1 3 e mm 2 2 Board eM 4 2 1 V O and Power a a E 4 2 2 NIU Te Tes mesi DD M 5 2 3 Eee EE 6 3 2 an a Taka a khus 7 3 1 Software Installation and 0 7 3 2 9 3 3 GIG Ss eme 10 3 4 Data Anal SIS I C 10 4 Sehematics DD 11 4 1 SCSI CS 2 E 11 4 2 POB Layout 14 4 3 Bill of Materials aaa saa aaa kaqa aaa aa sas 19 5 su wats 2
12. 112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 4 PANASONIC ECJ 0EC1H100D C66 C95 C97 CAPACITOR SMT 0402 CER 10pF 50V 0 5pF NPO 5 MURATE GRM155R60J225ME15D C37 C92 CAPACITOR SMT 0402 CERAMIC 2 2uF 6 3V 20 X5R 6 PANASONIC ECJ 1VB0J475K C36 CAPACITOR SMT 0603 CER 4 7uF 6 3V 10 X5R 7 TAIYO YUDEN JMK107BJ106MA T C31 C38 CAPACITOR SMT 0603 CER 10uF 6 3V 20 X5R 8 MURATA GRM31CR60J476ME19B C44 CAPACITOR SMT CER 1206 47uF 6 3V 2096 X5R 9 AVX TACR475M020R C98 C99 CAP SMT TAN 0805 4 7uF 20V 20 R CASE 10 AVX TPSC226K016R0375 C39 C43 C48 C49 C50 C54 10 16V 22uF C57 C59 C61 C62 C65 8 11 SMA J P X ST EM1 J1 J2 J3 J5 J6 J7 J9 J10 SMA JACK EDGE J13 MOUNT 062PCB BRASS GOLD STRAIGHT 50 Q 12 SAMTEC SMA J P H ST TH1 J8 J11 2 SMA COAX STRAIGHT PCB JACK SMT 175TL 50 Q GOLD 13 TYCO 745781 4 P17 DSUB 9 PIN R A FEM ELECTRONICS 14 ADVANCED MNE20 5K5P10 P25 MINI AB USB OTG RECEPTACLE R A SMT TYPE CONNECTER 15 USCC HC 18 U 4 1943M Y1 4 194300 MHz 16 EPSON HF 372A UNINSTALLED F1 CRYSTAL FILTER UNINSTALLED TOYOCOM 17 TI N A U4 UNINSTALLED 18 Not Installed PAD0201 UN EP4 EP6 Uninstalled Part EMPTY PAD SMT 0201 19 Not Installed PAD0402 UN EP1 EP2 Uninstalled Part PAD SMT 0402 20 MURATA BLM15BD102SN1D FB2 FB3 FB4 FB8 FB22 FERRITE BEAD SMT 0402 1 kQ 200mA FB23 FB24 FB25 FB26 FB27 FB28 FB29 FB30 21 MURATA BLM18EG601SN1D FB31 FERRITE BEAD SMT 0603 600 Q at 100
13. 2 Appendix TSW1100 for Evaluating AFE5804 5 2 2 4 23 List of Figures 1 AFE5804EVM LED Locating u y a aaa au kakak ce da i apu aya waqa ayau q 3 2 AFE5804EVM Connectors and Locations 4 2 2 4 3 Locations of Jumpers JTAG and Switches on the AFE5804EVM 5 4 Default Setup w luas 5 5 AFE5804EVM USB SPI Interface for TGC Mode nnne nnn 7 6 5804 USB SPI Interface for CW 44 1 nn nenne 8 7 5804 USB SPI Interface for ADC 1 nnn nnn 9 8 Typical AFE58904 Bench 10 9 Clock Selection Jumper Configurations 10 10 T p Layer 0 0000 a e 11 11 Inner Layer 1 GOUNA 0 00 12 12 INE LAYER 2 1 1212 12 nasa me 12 12 2 12 2 2 2
14. 2 2 2 2 2 13 13 MAST Ey Se Nee cuisse SERES 14 14 Inner Layer 4 Ground 1 0 15 15 Bottom Layer Sig mall elm 16 16 TOP IK Sereen qu qan qaa aaa ako sau 17 17 Bottom Silk Sgreem Layer 0 0 18 18 Typical Performances of AFE5804 22 A 1 TSWINOO Mtera E EE 24 A 2 Analysis of Noncoherent Sampled Data 4 nnne 25 SPI is a trademark of Motorola Inc SLOU241 September 2008 AFE5804EVM 1 Submit Documentation Feedback 5 INSTRUMENTS Introduction www ti com List of Tables 1 AFE5804EVM Default Settings When Powered On 9 2 Channel to Channel Matching Between the AFE5804EVM and ADSDeSER 50EVM 10 3 Bill of Materials uuu 19 1 1 1 2 1 3 2 Introduction The 5804 includes an 8 channel voltage controlled amplifier VCA and an 8 channel 50 MSPS analog to digital converter ADC The outputs of the ADC are 8 channel LVDS outputs which can be deserialized by the ADSDeSer 50EVM The AFE5804 evaluation module EVM provides an easy way to examine the performance and functionalities of AFE5804 Features
15. 5804EVM SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Appendix A Appendix A TSW1100 for Evaluating AFE5804 5 This appendix describes the use of TSW1100 software to analyze data files acquired by logic analyzers As previously mentioned coherent sampling is recommended when HP8644s are used The calculation of coherent sampling rate and signal frequency can be found in the TSW1100 user s manual SLAU163 Users can set the calculated frequencies for signal generators acquire ADC data through a logic analyzer and save the data as a text file A typical data file captured by a logic analyzer must be modified to the following format i e containing only one column 1981 1615 1292 1046 895 852 927 1113 1394 1737 2110 2477 2798 3044 3196 3237 3162 2978 The AFE5804 5 performance analysis can be done as follows First add some header information to the modified logic analyzer data file as follows Example files are included in the TSW1100 software package Modify time sampling rate and frequency in based on your setup TSW1000 2 12 2007 12 38 Bits 12 Sampling Rate 40000000 000 Frequency in 1998291 0156 2s complement No Data Format Decimal Haw Captured Data 1981 1615 1292 1046 895 852 927 1113 1394 1737 2110 2477 2798 SLOU241 September 2008 TSW1100 for Evaluating AFE5804 5 23 Submit Documentation Feedback 24
16. ANALOG FRONT END 36 MAXIM MAX3221CAE U2 RS 232 TRANSCEIVERS 37 MOTOROLA MMBD7000LT1 D1 D2 DUAL SWITCHING DIODE 38 PHILIPS BAP50 04 D3 PIN DIODE SOT 23 SINGLE JUNCTION 39 Tl TPS79633DCQR U7 UNINSTALLED U8 ULTRALOW NOISE HI PSRR FAST RF 1 A LDO LINEAR REGULATOR 3 3V 40 TI BURR BROWN OPA820IDBV U1 UNITY GAIN STABLE LOW NOISE VOLTAGE FEEDBACK OPAMP 41 TI TPS79318DBV U6 1 8V ULTRALOW NOISE PSRR FAST RF 200mA LDO LINEAR REGULATOR 42 TPS79325DBV U9 2 5V ULTRALOW NOISE PSRR FAST RF 200mA LDO LINEAR REGULATOR 43 FUTURE FT245RL U10 USB FIFO IC INCORPORATE FTDICHIP ID SECURITY TECHNOLOGY DONGLE DEVICE INT 44 PANASONIC ELJFA221J L1 220uH 5 45 TAIYO YUDEN LK 1608 330M FB1 FB11 FB12 INDUCTOR SMTO0603 33 01H 2096 46 PANASONIC LNJ308G8PRA LED1 LED2 LED3 LED5 LED SMT 0603 PURE GREEN 2 03V 47 PANASONIC LNJ808R8ERA LED4 LED SMT 0603 ORANGE 1 8V 48 ECS ECS 3953M 400 BN U5 OSC SMT 3 3V 50ppm 40 85C 5nS 40 000 MHz 49 PANASONIC ERJ 2GE0R00X R26 R27 R40 R42 R44 R48 RESISTOR JUMPER SMT 0402 0 0 5 1 16 R53 R55 R56 R63 R65 50 PANASONIC ERJ 2GEJ0000 UN R6 R7 R29 R30 R31 R32 UNINSTALLED PART R34 R35 R36 R37 R39 R43 R46 R49 R54 R59 R60 R62 R64 51 PANASONIC ERJ 2GEJ131 R66 R69 RESISTOR SMT 0402 130 1 1 16W 52 PANASONIC ERJ 2GEJ49R9 UN R4 R9 R22 UNINSTALLED PART 53 PANASONIC ERJ 2RKF5602X R57 RESISTOR SMT 0402 56K Q 1 1 16W 54 PANASONIC ERJ 2GEJ820 R67 R68 RESISTOR SMT 0402 5 82 55 PANAS
17. ONIC ERJ 2RKF1000X R24 R25 RESISTOR SMT 0402 100 0 1 1 16 56 PANASONIC ERJ 2RKF1001X R13 R14 R18 R47 RESISTOR SMT 0402 1 00K 1 1 16W 57 PANASONIC ERJ 2RKF1002X R33 R58 RESISTOR SMT 0402 10 0K 1 1 16W 58 PANASONIC ERJ 2RKF2000X R52 RES SMT 0402 200 0 1 1 16W 59 PANASONIC ERJ 2RKF3320X R16 R20 R38 R45 RES SMT 0402 332 0 1 1 16W 60 PANASONIC ERJ 2RKF4020X RES SMT 0402 402 0 1 1 16W 61 PANASONIC ERJ 2RKF4992X R28 RESISTOR SMT 0402 49 9K 1 1 16W 62 PANASONIC ERJ 2RKF49R9X R1 R2 R5 R10 R11 R15 RESISTOR SMT 0402 49 9 0 1 1 16W R17 R21 R23 R61 63 PANASONIC ERJ 2RKF7500X R50 R51 RES SMT 0402 750 0 1 1 16 64 VISHAY CRCW06031742F R19 RES SMT 0603 17 4K 1 65 PANASONIC ERJ 6RQF5R1V R41 SMT RES 0805 1 8W 1 5 1 Q 66 PANASONIC 1 5 RESISTOR SMT 0201 THICK FILM 0 0 5 00 JUMPER 1 20W 67 C amp K TD06H0SK1 SW1 SW2 DIP SWITCH SMT 6POS SPST MINIATURE 68 PANASONIC EVQPE104K 51 SQUARE LIGHT TOUCH SWITCH SMT SPST 69 KEYSTONE 5005 TP8 TESTPOINT THU COMPACT 0 125LS 130TL RED ELECTRONICS 70 KEYSTONE 5006 TP1 TP2 TP5 TP6 TP10 TESTPOINT THU COMPACT 0 125LS 130TL BLACK ELECTRONICS 71 KEYSTONE 5006 UN TP3 TP4 TP7 TP9 UNINSTALLED PART TEST POINT ELECTRONICS 20 AFE5804EVM SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Schematics and Layout Table 3 Bill of Materials continued Item MFG MFG
18. Part Number RefDes Value or Function 72 KEYSTONE 5007 TP11 TESTPOINT THU COMPACT 0 125LS 130TL WHITE ELECTRONICS 73 MINI CIRCUITS ADTI 6T T1 UNINSTALLED 2 RF TRANSFORMER WIDEBAND 0 03 125 MHz 74 BOURNS 3296W 1 103 R12 TRIMPOT THU 10K 1096 0 5W 100ppm 25T 75 AMP 531220 2 P3 P8 P12 P21 P23 SHUNTS 76 KEYSTONE 1892 H1 H2 H3 H4 and STANDOFF 4 40 THR 0 375 L ALUM ELECTRONICS UNINSTALLED 77 BUILDING PMS 440 0025 SL H1 H2 H3 H4 and SCREW MACHINE SLOTTED 4 40x1 4 FASTENERS UNINSTALLED 5100241 September 2008 AFE5804EVM 21 Submit Documentation Feedback TExAS INSTRUMENTS Typical Performance www ti com 5 Typical Performance This section provides some typical performance characteristics of the AFE5804EVM to assist users in verifying their setup After analysis of the data file acquired by a logic analyzer the SNR of the AFE5804 should be better than 59 dB when the PGA is set to 30 dB the filter is set to 12 5 MHz the mode is set to TGC1 and Vctnl is set as 1 V A typical performance plot of the AFE5804 is shown in Figure 18 Performance Data Output FFT 5 Hi FO 1 074 8 Highest SNR spur 40 0 Highest SNR Spur 10 00 Highest 88 00 50 0 uns 9 58 Fri 30 2008 60 0 Fundamental 4875 1 08 1 2nd Harmonic Ampltude FS 72 46
19. T 0 5 I I OM 12 14M 16M 18M 20H Stop Freq 7 0 Inband Power 0 dem 8 a 90 2 19 Wc Power Spectrum w Plot Que EE adback Progress Status Message Remote control of Calculate and use Lab Instruments Coherent Freq FFT Window Type i None Calculate and use Harmoniceie SHFCT 5 Reference Value Prime Bins Only Notch Spurs a No window applied ADC Characteristics TSW1000 Number of Bits 12 2 s Complement Clock Fs Sampling Rate Fs 7 Capture Capture Statistics Data Read fromFile INT gt gt 3241 ure 2 16M 18M 20M Status Message Time Domain Algorithim being used For performance calculations spectrum information is ignored for the purpose of performance calculations coos i sms Notch Spurs 1 Y Axis 2 125 b Hanning window applied Note the DC artifact that is visible Figure A 2 Analysis of Noncoherent Sampled Data SLOU241 September 2008 TSW1100 for Evaluating AFE5804 5 25 Submit Documentation Feedback ew our 01
20. V to 1 2 V must be shorted when onboard is used 4 AFE5804EVM SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Board Configuration 2 2 Jumpers and Setup In the following detailed description the board has been set to default mode see Figure 3 Figure 3 Locations of Jumpers JTAG and Switches on the AFE5804EVM Figure 4 Default Setup for Jumpers e P5 Power down pin for the VCA section of the AFE5804 Grounded default mode or High 3 3 VD for power down mode e P10 AFE5804 ADC clock input selection Transformer based differential clock single ended LVCMOS clock or future clock option needs U4 for support The default mode uses the 5100241 September 2008 AFE5804EVM 5 Submit Documentation Feedback TExAS INSTRUMENTS Board Configuration www ti com 2 3 6 transformer based differential clock P7 MSP430 microcontroller JTAG interface P8 MAX3221 RS 232 power off jumper When the jumper is removed MAX3221 is completely powered off In the default mode the jumper is uninstalled because the USB interface is used e P9 SPI interface for U4 e P11 TI internal use Default is floating e P12 Power down pin for ADS Active High 3 3 VD Floating for default mode e P13 External ADS reference voltage inputs Floating in the internal reference mode e P14 EN SM In the default mode P14 connects to 3 3 VD and the
21. ck source or external clock source The best performance of this EVM is achieved when the low jitter clock source HP8644 is used P22 P23 and P18 must be removed in order to disable the onboard clock When 8644 or similar clock sources are unavailable the onboard 40 MHz clock is the desirable source The jumpers P22 P23 and P18 must be configured as shown in Figure 4 i e the default setup for AFE5804EVM In this mode the transformer based differential clock is used Data Analysis Based on the data file acquired by a logic analyzer the performance of AFE5804 can be evaluated Appendix A provides one solution TI 151 1100 software to analyze the data file captured by a logic analyzer Coherent sampling is recommended but is not mandatory Due to the frequency accuracy requirement of coherence sampling two HP8644s are required for generating an ADC clock and analog signal For most users this may be infeasible Data analysis based on windowing is a more suitable approach AFE5804EVM SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Schematics and Layout 4 Schematics and Layout This section provides the schematics the AFE5804EVM board layout and the bill of materials 4 1 Schematics The schematics appear at the end of the document 42 PCB Layout The AFE5804EVM uses a six layer printed circuit board The following figures show each layer Figure 10 Top Layer Signal
22. e date of delivery for a full refund THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the User s Guide and specifically the Warnings and Restrictions notice in the User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For additional information on 5 environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other
23. installation and operation are discussed 3 1 Software Installation and Operation The AFE5804EVM ships with the AFE5804EVM USB SPI software and AFE58XXEVM driver Run the AFE58XXEVM Driver install exe and the setup exe to install the driver and software respectively personal computer PC recognizes the EVM after software installation To launch the software after successful installation click Start Menu All Programs Texas Instruments AFE5804EVM USB SPI gt AFE5804EVM USB SPI Three different modes are shown in Figure 5 Figure 6 and Figure 7 The software updates the AFE5804 registers as soon as users change any current setup i e the program sends out new register values due to any value change It is recommended that users change at least one register value before measurement Therefore the register values in a device can be synchronized to the displayed values on the software interface In most cases users only need to change the VCA setup The ADC setup can remain the same as the integrated circuit IC is powered up 2i TI ADC SPI Interface Address Byte s Jio d Data Byte s 20 PRESS ENTER TO SEND DATA 0 17 Register 0 Ox18 Register 8 Figure 5 AFE5804EVM USB SPI Interface for Mode SLOU241 September 2008 AFE5804EVM 7 Submit Documentation Feedback Board Operation ADC SPI Interface TW SEE YT TY TE SE a AE 6 8 10 1214 16 18 20 22 24 CH2 CW Ma
24. intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used FCC Warning This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 4 75 V to 5 25 V and the output voltage range of 5 V to 5 V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the input range please contact a TI field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM outp
25. ith TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with al
26. ments of the AFE5804 5100241 September 2008 AFE5804EVM 9 Submit Documentation Feedback 3 3 3 4 TExAS INSTRUMENTS Board Operation www ti com PC GPIB LabVIEW Log Analyzer 16500C Fun Gen AFES804EVM Signal BPF ADSDeSER LabVIEW is a trademark of National Instruments Corporation Figure 8 Typical AFE5804 Bench Setup 4i Fun Gen CLK The channel order of the AFE5804 outputs is not the same as that of the ADS527x outputs Consequently the channel number on the ADSDeSER 50EVM or AFE5804EVM can be misleading Table 1 provides channel to channel sequence matching between the ADSDeSER 50EVM and the AFE5804EVM Table 2 Channel to Channel Matching Between the AFE5804EVM and ADSDeSER 50EVM 5804 FCLK CH4 CH3 CH2 CH1 CH5 CH6 CH7 CH8 LCLK ADSDESER FCLK CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 LCLK For example when an analog signal is present on CH1 of the AFE5804EVM the corresponding 12 bit digital output can be seen on CH4 of the ADSDeSER 50EVM Clock Selection The AFE5804 can be clocked through a transformer based differential clock single ended clock or future clock input options provided by U4 as Figure 9 shows a Transformer Default b Single Ended Clock c Future CLK Input Option Based on U4 Figure 9 Clock Selection Jumper Configurations The clock source of the EVM can be the onboard 40 MHz clock HP8644 low jitter clo
27. ony www ti com telephony and ZigBee Solutions www ti com Iprf Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2008 Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Texas Instruments AFE5804EVM
28. teration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or en
29. trix cwo i CH3 CW Matrix cwo CH4 CW Matrix CWO X CH6 CW Matrix i CH7 CW Matrix cwo Figure 6 AFE5804EVM USB SPI Interface for CW Mode 8 AFE5804EVM CH8 CW Matrix TEXAS INSTRUMENTS www ti com 0x17 Register lo 0x18 Register 0 SLOU241 September 2008 Submit Documentation Feedback 5 INSTRUMENTS www ti com Board Operation a TI ADC SPI Interface Register Interface ADC 5100 Address Byte s hd 0 ya Data Byte s Ho g PRESS ENTER TO SEND DATA PD POWERDOWN CLOCK Single Ended Offset Binary SNR Enhance OFF Figure 7 AFE5804EVM USB SPI Interface for ADC Setup 3 2 Hardware Setup When the AFE5804EVM is powered on in the default mode the AFE5804 is set as described in Table 1 Table 1 AFE5804EVM Default Settings When Powered VCA ADS TGC mode 1 Single End Clock PGA 20 dB Digital Gain 0 Filter 17 MHz Other parameters are as stated in data sheet Initial measurements can be made under these default settings See the AFE5804 data sheet SBOS442 for additional settings As previously mentioned the deserializer ADSDeSER 50EVM is required See details in the ADSDeSER 50EVM user s guide 5 91 An example bench setup is shown in Figure 7 Band pass filters are required for signal source in order to ensure the correct SNR measure
30. unctionalities of inputs outputs jumpers and test points of the AFE5804EVM 2 1 IO and Power Connectors Pin A1 of the AFE5804 is marked by a white dot on its package as well as a white dot on the board The positions and functions of the AFE5804EVM connectors are discussed in this section Figure 2 AFE5804EVM I O Connectors and Locations Analog Inputs Ch1 Ch8 J1 J3 J5 J7 J9 J10 Single ended analog signal inputs with 50 Q termination and AC coupling CW Output J4 CW output after I V translator Vent Input J8 optional gain control voltage of AFE5804 0 V to 1 2 V when this SMA connector is used shunt P3 must be removed Low Jitter CLK Source Input J11 This input accepts clocks with low jitter noise such as HP8644 output 20 to 50 MHz 50 duty cycle clock with 1 to 2 Vrms amplitude can be used When J11 is used ensure that shunts P18 P23 and P22 are removed External CLK Input J13 ADC Clock input such as FPGA outputs However the AFE5804 does not achieve satisfactory performances due to the high jitter noise of the clock 5 V PWR connector P2 Power supply input Regulated power supply outputs P1 P4 and P24 3 3 VA 3 3 VD 2 5 VA 1 8 VD outputs Connectors need to be installed RS 232 Input P17 PC serial port interface for setting AFE5804 USB input P25 USB interface to control the AFE5804 default LVDS Outputs Ch1 Ch8 P26 Differential LVDS data outputs R12 is used to adjust the onboard Vcntl from 0
31. ut If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 85 The EVM is designed to operate properly with certain components above 0 as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These types of devices can be identified using the EVM schematic located in the EVM User s Guide When placing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655308 Dallas Texas 75265 Copyright 2008 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance w
32. vironments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Clocks and Timers www ti com clocks Digital Control www ti com digitalcontrol Interface interface ti com Medical www ti com medical Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Teleph
Download Pdf Manuals
Related Search