SuperHTM Family E10A-USB Emulator Additional
Contents
1. 2 2 7 Interrupts During emulation any interrupt to the SH7751R can be used Whether or not to process interrupts during emulator command execution or in command input wait state can be specified When no interrupt is processed during user program break While the emulator is executing the user program or is in command input wait state interrupts are not processed generally However if an internal interrupt or an edge sensitive external interrupt occurs in command input wait state the emulator holds the interrupt and executes the interrupt processing routine when the GO command is entered When interrupts are processed during user program break Notes 38 Use the INTERRUPT command to execute an interrupt during a user program break This function is supported only with the command lines 1 Execute only non maskable interrupt Sets the priority and executes only interrupts with high priority Check that the interrupt handler operates normally before using this function In addition do not execute a non limited loop or the sleep instruction in the interrupt handler If the processing of the handler does not end the emulator generates a Communication Timeout error When interrupts are accepted during user program break user interrupt processing is not traced In this case continuous trace is not enabled Use the NOP instruction at the delay slot after the RTE instruction in the interrupt handler If a2. Clock and AUD Clock AUDCK 27 2 2 4 Notes on Setting the Breakpoint Dialog Box ee 27 2 2 5 Notes on Setting the Break Condition Dialog Box and the BREAKCONDITION SET Command eee 29 2 2 6 Performance Measurement Functions esee 30 2 2 7 38 2 2 8 CPU Stat s ACqUISIDOD iine net e 39 RENESAS RENESAS Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator The E10A USB emulator supports the SH7751R Table 1 1 lists the components of the emulator Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks HS0005KCUO1H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 72 9 g or HS0005KCUO2H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 73 7 g Hard Emulator box ware User system interface gt 1 14 pin type cable Length 20 cm Mass 33 1 9 User system interface 1 36 pin type cable Length 20 cm Mass 49 2 g only for HS0005KCUO2H USB cable 1 Length 150 cm Mass 50 6 g Soft SH7751R E10A USB 1 HS0005KCUO 1 SR ware emulator setup C gt program SuperH Family HS0005KCUO1HJ E10A USB Emulator HS0005KCUO1HE User s Manual Supplementary HS7751RKCUO1HJ Information on Using HS7751RKCUO1HE the SH7751R and Test program manual HS0005TMO01HJ and for HS0005KCUO1H HS0005TMO1HE
3. Trace type AUD function Internal trace function Branch trace Window trace Channel B AUD mode AUD model Realtime trace Non realtime trace AUD mode2 Trace continue C Trace stop AUD trace display range Start pointer 2255 End pointer po Figure 2 1 Trace mode Page When the AUD trace function is used select the AUD function radio button in the Trace type group box of the Trace mode page 14 NE S AS 21 Branch Trace Function The branch source and destination addresses and their source lines are displayed Branch trace can be acquired by selecting the Branch trace check box in the AUD function group box of the Trace mode page b Window Trace Function Memory access in the specified range can be acquired by trace Two memory ranges can be specified for channels A and B The read write or read write cycle can be selected as the bus cycle for trace acquisition Setting Method 1 Select the Channel A and Channel B check boxes in the AUD function group box of the Trace mode page Each channel will become valid ii Open the Window trace page and specify the bus cycle and memory range that are to be set for each channel Acquisition Trace mode Window trace Channel Read Write Read C Write c Start address Ho End address Ho Channel B Read Wr
4. and HS0005KCUO2H provided on a CD R Note Additional document for the MPUs supported by the emulator is included Check the target MPU and refer to its additional document 14 NE S AS 1 2 Connecting the E10A USB Emulator with the User System To connect the E10A USB emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user system interface cable When designing the user system refer to the recommended circuit between the H UDI port connector and the MCU In addition read the E10A USB emulator user s manual and hardware manual for the related device Table 1 2 shows the type number of the emulator the corresponding connector type and the use of AUD function Table 1 2 Type Number AUD Function and Connector Type Type Number Connector AUD Function HS0005KCUO2H 36 pin connector Available HS0005KCUO1H HSOOO5KCU02H 14 pin connector Not available The H UDI port connector has the 36 pin and 14 pin types as described below Use them according to the purpose of the usage 1 36 pin type with AUD function The AUD trace function is supported A large amount of trace information can be acquired in realtime The window trace function is also supported for acquiring memory access in the specified range memory access address or memory access data by tracing 2 14 pin type without AUD function The AUD trace function cannot be used because only the H UDI
5. normal INT The number of interrupts generally except for NMI Interrupt count NMI NMI The number of NMI interrupts UBC A match count UA The number of times channel A of UBC is satisfied UBC B match count UB The number of times channel B of UBC is satisfied Instruction cache fill cycle ECF The number of instruction cache fill cycles Operand cache fill cycle OCF The number of operand cache fill cycles Elapsed time cycle The number of cycles for elapsed time Pipeline freeze by cache miss or instruction Pipeline freeze cycle due to instruction cache misses Pipeline freeze by cache PFCD miss or data Pipeline freeze cycle due to operand cache misses Pipeline freeze by branch PFB instruction interrupt Pipeline freeze cycle due to branch instructions or exceptions Note For the non cache operand accesses due to the PREF instruction or TLB c 0 the correct value cannot be counted The events can be counted even in the conditions shown in table 2 11 in addition to the normal count conditions 35 7tENESAS Table 2 11 Performance Count Conditions Event Instruction cache miss count Count Condition Target Mode e Includes instruction fetch for the cache off area to EC count the number of times the instruction has not been fetched in one cycle e When a cache miss occurs during an overrun fetch generated at exception TLB miss count When the TLB miss
6. user system to the UVCC pin reduces the leakage current from the emulator to the user system A level shifter that is activated by the internal power supply or user power supply changed by the switch is installed in the interface circuit of the emulator If the user power is supplied to the UVCC pin the level shifter is not activated as long as no user power is supplied When the power supply of the user system is turned off no current flows from the user interface The I O voltage level of the user system interface can be the same as that of the VccQ To operate the emulator with low voltage lower than 3 3 V the VccQ must be supplied to the UVCC pin Make the emulator s switch settings so that the VccQ will be supplied SW2 1 and SW3 1 as shown in figure 1 3 The resistance values shown in figures 1 3 and 1 4 are recommended For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MPU 13 NE S AS When the circuit is connected as shown in figure 1 3 the switches of the emulator are set as SW2 and SW3 1 For details refer to section 3 8 Setting the Switches in the SuperH Family E10A USB Emulator User s Manual VccQ 3 3 V power supply Pulled up at 4 7 kQ or more all VccQ VccQ VccQ H UDI port connector SH7751R 36 pin type QFP256 1 AUDCK AUDCK AUDATAO AUDATAO AUDATA1 AUDATA1 AUDATA2 AUDATA2 AUDATA3 AUDATAS AUDSY
7. user interrupt is inserted while the user program breaks until the processing ends do not set a BREAKPOINT in the interrupt handler The emulator may generate a Communication Timeout error Use the Break Condition function For details on command line syntax refer to the online help 14 NE S AS 2 2 8 CPU Status Acquisition The emulator can display the SH7751R status during user program execution in realtime It displays the items selected in the Extended Monitor Configuration dialog box in the Extended Monitor window during user program execution The emulator can display the state of the moment when a command is input for the specified register through the command line function Notes 1 This function is only valid during user program execution If this function is used during a user program break an undefined value is displayed 2 A read value during reset is not guaranteed 3 Inthe sleep or deep sleep mode only the STATUS or FRQCR can be read 4 The display is updated in the 100 ms interval Table 2 12 shows the details of the items that can be displayed Table 2 12 Display Status Item Example Description PC H A0000104 Displays the PC value SR H 000000FO Displays the SR register value FPSCR H O00000FO Displays the FPSCR register value INTEVT H 00000100 Displays the INTEVT register value EXPEVT H 00000600 Displays the EXPEVT register value FRQCR register H 00000102 Display
8. 10 12 and 13 14 UVCC GND Output 3 ES GND Output Notes 1 Input to or output from the user system 2 The slash means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 If the VccQ pin is not connected to the UVCC the I O voltage of the user system interface will be fixed to 3 3 V 5 This pin can be connected to GND Pin 1 mark H UDI port connector top view SS fai ff oe SS P d H UDI port connector 23 0 top view 6 x 2 54 15 24 es Pin 1 mark Unit mm Figure 1 2 Pin Assignments of the H UDI Port Connector 14 Pins 14 NE S AS 1 5 1 5 1 Recommended Circuit between the H UDI Port Connector and the MPU Recommended Circuit 36 Pin Type Figure 1 3 shows a recommended circuit for connection between the H UDI and AUD port connectors 36 pins and the MPU when the emulator is in use Figure 1 4 shows a circuit for connection when UVCC is not connected Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect the signal lines to other components on the board When the power supply of the user system is turned off supplying VccQ of the
9. 24 TDI GND GND AUDATA2 Output TDO GND GND BR Ww P AUDATA3 Output ASEBRK BRKACK E o GND 28 GND 11 12 AUDSYNC GND Output 294 30 UVCC GND Output 13 NC 31 RESETP Output User reset 14 GND 32 GND 15 NC E 333 GND Output 16 GND 34 GND 17 TCK Input 35 NC 18 GND 36 GND Notes 1 Input to or output from the user system 2 The slash means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 If the VccQ pin is not connected to the UVCC the I O voltage of the user system interface will be fixed to 3 3 V Edge of the board connected to the connector 36 000000000 000000000 900000000 fee ey 3 4 21 59 37 61 43 51 LJ Pattern inhibited area H UDI port connector top view 0 1 0 75 Pin 1 mark 1 27 M2 6 x 0 45 H UDI port connector top view H UDI port connector front view Figure 1 1 Pin Assignments of the H UDI Port Connector 36 Pins 14 NE S AS Pin No Signal TRST TDO ASEBRK BRKACK Input Output Input SH7751R Pin No 2 199 246 245 Note Input Output Output 5 TMS Input TDI RESETP N C GND 6 7 8 9 Input Output User reset 11
10. ASID Breaks when the SH7751R ASID value matches the specified condition Bus state condition Bus State There are two bus state condition settings Read write condition Breaks at the read or write cycle Bus state condition Breaks when the operating state in an SH7751R bus cycle matches the specified condition LDTLB instruction break condition Breaks when the SH7751R executes the LDTLB instruction Internal I O break condition Breaks when the SH7751R accesses the internal I O Note For details on window function and command line syntax refer to the online help 17 14 NE S AS Table 2 4 lists the combinations of conditions that can be set under Break Condition 1 2 3 4 5 6 7 8 Table 2 4 Dialog Boxes for Setting Break Conditions Dialog Box Break Break Break Break Condition 1 5 Condition 2 3 Condition 7 Condition 8 Dialog Box 4 6 Dialog Box Dialog Box Dialog Box Address bus condition O O X X Address Data bus condition O X X X Data ASID condition ASID O O X X Read write O O X X specification Data access O O X X Before after execution O O X X Sequential break O O X X LDTLB instruction X X X O break Internal I O break X X O X Note be set the dialog box X Cannot be set in the dialog box 13 NE S AS The emulator has sequential break functions Table 2 5 lists the sequential break conditions Table 2 5 Sequential Break Co
11. CPU Performance dialog box Maximum two conditions can be specified at the same time Table 2 10 shows the measurement items Options in table 2 10 are parameters for mode of the PERFORMANCE SET command They are displayed for NAME in the Performance Analysis window 14 NE S AS 33 Table 2 10 Measurement Items Event Keyword Description Operand access count OAR The number of times the operand access is performed on read with cache the cacheable area when the cache is enabled read access only Operand access count OAW The number of times the operand access is performed on write with cache the cacheable area when the cache is enabled write access only Operand access count read OARW The number of times the operand access is performed on and write with cache the cacheable area when the cache is enabled both read and write accesses Internal RAM operand OARAM The number of times the internal RAM area is accessed access count All operand access count OA The number of all operand accesses Internal I O area access IOA The number of times the internal I O area is accessed count Operand cache read miss DCR The number of times operand cache misses occur at data count reading Operand cache write miss DCW The number of times operand cache misses occur at data count writing Operand cache read and DCRW The number of times operand cache misses occur at data wr
12. CUO1H Not supported HS0005KCUO2H Supported AUD Trace Functions This function is operational when the AUD pin of the device is connected to the emulator Table 2 8 shows the AUD trace acquisition mode that can be set in each trace function Table 2 8 AUD Trace Acquisition Mode Type Mode Description Continuous Realtime trace When the next branch occurs while the trace information is trace occurs being output the trace information being output is output but the next trace information is not output The user program can be executed in realtime but some trace information may be lost Non realtime trace When the next branch occurs while the trace information is being output the CPU stops operations until the information is output The user program is not executed in realtime Trace buffer Trace continue This function overwrites the oldest trace information to store full the latest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed 20 12 NE S AS To set the AUD trace acquisition mode click the Trace window with the right mouse button and select Setting from the pop up menu to display the Acquisition dialog box The AUD trace acquisition mode can be set in the AUD model or AUD mode2 group box in the Trace mode page of the Acquisition dialog box Acquisition Trace mode Window trace
13. MMU during program execution After setting the MMU is returned to the original state When a break occurs at the corresponding virtual address the cause of termination displayed in the status bar and the Status window is ILLEGAL INSTRUCTION not BREAKPOINT 9 When the Virtual option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a virtual address A BREAKPOINT is set after enabling the SH7751R MMU during program execution After setting the MMU is returned to the original state When an ASID value is specified the BREAKPOINT is set to the virtual address corresponding to the ASID value The emulator sets the BREAKPOINT after rewriting the ASID value to the specified value and returns the ASID value to its original value after setting When no ASID value is specified the BREAKPOINT is set to a virtual address corresponding to the ASID value at command input 10 TLB error occurs during virtual address setting the following message box will be displayed N TLB ERROR EXPEVT 00000040 Figure 2 4 Message Box for Clearing a TLB Error 28 13 NE S AS If a program is executed again without clearing the BREAKPOINT set at the address in which the TLB error occurs a TLB error will occur again Accordingly clear the BREAKPOINT before execution An address physical address to which a BREAKPOINT is set is determined when the BREAKPOINT is set Accordi
14. NC AUDSYNC N C ASEBRKAK ASEBRK UVCC BRKACK RESET RESETP N C Reset signal User system Figure 1 3 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 36 Pin Type UVCC Connected 14 NE S AS When the circuit is connected as shown in figure 1 4 the switches of the emulator are set as SW2 0 and SW3 1 For details refer to section 3 8 Setting the Switches in the SuperH Family E10A USB Emulator User s Manual VccQ 3 3 V I O power supply Pulled up at 4 7 kQ or more all VccQ VecQ VccQ VccQ H UDI port connector SH7751R 36 pin type QFP256 AUDATAO AUDATAO AUDATA1 AUDATA1 AUDATA2 AUDATA2 AUDATA3 AUDATA3 AUDSYNC ASEBRK BRKACK RESETP Reset signal User system Figure 1 4 Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 36 Pin Type UVCC Not Connected 14 NE S AS Note When UVCC is not connected and the user system is turned off note that the leakage current flows from the emulator to the user system 14 NE S AS 1 5 2 Recommended Circuit 14 Pin Figure 1 5 shows a recommended circuit for connection between the H UDI and AUD port connectors 14 pins and the MPU when the emulator is in use Figure 1 6 shows a circuit for connection when UVCC is not connected Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 When a netw
15. REJ10B0119 0200 Everywhere you imagine 2 NESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7751R Renesas Microcomputer Development Environment System SuperH Family SH7750 Series E10A USB for 7751 HS7751RKCUO1HE Rev 2 00 Revision Date Mar 19 2007 Renesas Technology www renesas com Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document 2 Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples 3 You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or tec
16. annel B correspond to Break Condition 6 and Break Condition 5 respectively This bit is 1 when Break Condition 6 has been satisfied and Break Condition 5 has not been satisfied BC4 0 When Sequential break condition 4 3 2 1 is selected this bit is 1 when Break Condition 4 has been satisfied and Break Condition 3 has not been satisfied It is also 1 when Break Condition 4 is satisfied again after Break Condition 3 has been satisfied 41 7tENESAS Table 2 12 Display Status cont Item Example Description Condition match BC3 0 When Sequential break condition 4 3 2 1 and Sequential flag for sequential break condition 3 2 1 are selected this bit is 1 when Break break cont Condition 3 has been satisfied and Break Condition 2 has not been satisfied It is also 1 when Break Condition 3 is satisfied again after Break Condition 2 has been satisfied BC2 0 When Sequential break condition 4 3 2 1 Sequential break condition 3 2 1 and Sequential break condition 2 1 are selected this bit is 1 when Break Condition 2 has been satisfied and Break Condition 1 has not been satisfied It is also 1 when Break Condition 2 is satisfied again after Break Condition 1 has been satisfied a Window function To use the window function the Extended Monitor window is displayed Open the Extended Monitor window by selecting Display gt CPU gt Extended Monitor or click the Extended Monitor toolbar button fel Set the items to be dis
17. can be measured and the cache hit ratio in the executed user program can be obtained ii Measuring ratio of execution time in specified program area to total execution time Specify measurement channel 1 to measure the elapsed cycle count from the start to the end of user program execution Specify measurement channel 2 to measure the elapsed cycle count during execution from the specified start PC to the specified end PC With both the channels the total elapsed cycle and the elapsed cycle for the specified program area can be measured and the ratio of the execution time in the specified program area to the total execution time can be obtained Notes 1 The counter for performance measurement has 48 bits A maximum of 2 2 8 x 10 counts and 11 6 day cycles when the CPU operating frequency is 267 MHz can be measured If a counter overflow occurs the count becomes invalid 2 For details on command line syntax refer to the online help 37 14 NE S AS 2 Displaying the measured result The measured result is displayed in the Performance Analysis window or the PERFORMANCE ANALYSIS command with hexadecimal 32 bits Note If a performance counter overflows as a result of measurement will be displayed 3 Initializing the measured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE ANALYSIS command
18. cs operands or source may not be correct The AUD trace function outputs the differences between newly output branch source addresses and previously output branch source addresses The window trace function outputs the differences between newly output addresses and previously output addresses If the previous branch source address is the same as the upper 16 bits the lower 16 bits are output If it matches the upper 24 bits the lower 8 bits are output If it matches the upper 28 bits the lower 4 bits are output The emulator regenerates the 32 bit address from these differences and displays it in the Trace window If the emulator cannot display the 32 bit address it displays the difference from the previously displayed 32 bit address If the 32 bit address cannot be displayed the source line is not displayed In the emulator when multiple loops are performed to reduce the number of AUD trace displays only the IP counts up When the SH7751R is used the maximum number of trace display pointers is D 32767 to 0 However the maximum number of trace display pointers differs according to the AUD trace information to be output Therefore the above pointers cannot be always acquired 23 14 NE S AS Internal Trace Function This function is activated by selecting the Internal trace radio button in the Trace type group box of the Trace mode page See figure 2 1 Trace mode Page The internal trace functions are also activat
19. d Ignore this address because it is not a user program address If a completion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired When a user interrupt is enabled by the INTERRUPT command during the emulator command wait state or user program execution an interrupt that is generated at the program execution start or end including a step operation can be traced in realtime When the Acquire continuous trace check box is selected do not perform memory access during emulation When internal I O trace or LDTLB instruction trace is performed select the Acquire continuous trace check box When the Acquire continuous trace check box is selected 32 trace information data can be acquired In this case however since the user program stops at constant intervals the processing speed is decreased compared with the case where the Acquire continuous trace check box is not selected Trace information cannot be acquired for the following branch instructions e The BF and BT instructions whose displacement value is 0 e Branch to H A0000000 by reset 13 NE S AS 9 When the Acquire continuous trace check box is selected and when either the Get trace information of internal I O area radio button internal I O trace enabled or the Get trace information of LDTLB instruction radio button is selected LDTLB instruction trace enabled with the Break Condition 5
20. dialog box e An internal I O trace cannot be made with the Step In function e The LDTLB instruction and internal I O trace cannot be performed with the Step Over function 10 When continuous trace is used do not enable user interrupt by the INTERRUPT command during the emulator command wait state or user program execution 2 2 3 Notes on Using the JTAG Clock TCK and AUD Clock AUDCK 1 Setthe JTAG clock frequency to lower than the frequency of the SH7751R peripheral module clock CKP 2 Setthe AUD clock AUDCK frequency to 50 MHz or lower 2 2 4 Notes on Setting the Breakpoint Dialog Box 1 When an odd address is set the next lowest even address is used 2 A BREAKPOINT is accomplished by replacing instructions of the specified address Accordingly it can be set only to the internal RAM area However a BREAKPOINT cannot be set to the following addresses e address whose memory content is H 003B e An area other than the internal RAM e An instruction in which Break Condition 3 is satisfied e A slot instruction of a delayed branch instruction In addition do not perform memory write BREAKPOINT or download even if the memory space can only be written by the MMU 3 During step operation a BREAKPOINT is disabled 4 Conditions set at Break Condition 3 are disabled when an instruction to which a BREAKPOINT has been set is executed Do not set a BREAKPOINT to an instruction in which Break Condition 3 is sat
21. ed by selecting each check box on the Branch trace page Acquisition Trace mode Branch trace Acquire subroutine branch instruction trace Acquire exception branch instruction trace Acquire continuous trace Figure 2 3 Branch trace Page 24 13 NE S AS Table 2 9 shows the internal trace functions Table 2 9 Internal Trace Functions Function Branch instruction trace Description Traces and displays the branch instructions The branch source address and branch destination address for the eight latest branch instructions are displayed There are three kinds of branch instruction trace e Normal branch instruction trace Traces and displays the normal branch instructions The normal branch instructions are the BF BF S BT S BRA BRAF and JMP instructions To use this function select the Acquire normal branch instruction trace check box in the Branch trace page e Subroutine branch instruction trace Traces and displays the subroutine branch instructions The subroutine branch instructions are the BSR BSRF JSR and RTS instructions To use this function select the Acquire subroutine branch instruction trace check box in the Branch trace page e Exception branch instruction trace Traces and displays the exception branch instruction The exception branch instruction is the RTE instruction In addition all the exception and interrupt operations are traced To use this function selec
22. ed from your products Renesas shall have no liability for damages arising out of such detachment 12 This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas 13 Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries Contents Section 1 Connecting the Emulator with the User 1 1 1 Components of the Emulator 1 1 2 Connecting the E10A USB Emulator with the User System sees 2 1 3 Installing the H UDI Port Connector on the User System seen 3 1 4 Pin Assignments of the H UDI Port 3 1 5 Recommended Circuit between the H UDI Port Connector and the MPU 6 1 5 1 Recommended Circuit 36 Pin Type essere 6 1 5 2 Recommended Circuit 14 Pin Type eene 10 Section 2 Specifications of the Software when Using the SH7751R 13 2 Differences between the SH7751R and the Emulator eee 13 2 2 Specific Functions for the Emulator when Using the 5 7751 17 2 2 1 Break Condition Functions 1 nennen eene 17 2 2 2 Trace Functions 19 2 2 3 Notes on Using the JTAG
23. edded Workshop After the I O register definition file is created the MPU s specification may be changed If each I O register in the I O register definition file differs from addresses described in the hardware manual change the I O register definition file according to the description in the hardware manual The I O register definition file can be customized depending on its format Note that however the emulator does not support the bit field function Verify In the IO window the verify function of the input value is disabled 13 Illegal Instructions If illegal instructions are executed by STEP type commands the emulator cannot go to the next program counter 13 NE S AS 2 2 Specific Functions for the Emulator when Using the SH7751R 2 2 1 Break Condition Functions In addition to BREAKPOINT functions the emulator has Break Condition functions Eight types of conditions can be set Break Condition 1 2 3 4 5 6 7 8 Break Condition 5 6 use the user break controller UBC Table 2 3 lists these conditions of Break Condition Table 2 3 Types of Break Conditions Break Condition Type Description Breaks when the SH7751R address bus value or the Address bus condition Address program counter value matches the specified value Data bus condition Data Breaks when the SH7751R data bus value matches the specified value Byte word or longword can be specified as the access data size ASID condition
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25. from the emulator cannot be used or the state cannot be cancelled by the STOP button 4 When the SLEEP instruction is executed by STEP type commands set Rate to 6 to use Step from the Run menu If Rate is 5 or less COMMUNICATION TIMEOUT error occurs Reset Signals The SH7751R reset signals are only valid during emulation started with clicking the GO or STEP type button If these signals are enabled on the user system in command input wait state they are not sent to the SH7751R Note Do not break the user program when the RESET MRESET or BREQ signal is being 5 low or the RDY signal is being high A TIMEOUT error will occur If the BREQ signal is fixed to low or the RDY signal is fixed to high during break a TIMEOUT error will at memory access Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer Memory Access during User Program Execution When a memory is accessed from the memory window etc during user program execution the user program is resumed after it has stopped in the emulator to access the memory Therefore realtime emulation cannot be performed 7tENESAS The stopping time of the user program is as follows Environment Host computer 1 GHz Pentium OS Windows 2000 SH7751R 267 MHz CPU clock JTAG clock 16 5 MHz When a one byte memory is read from the co
26. function is supported For tracing only the internal trace function is supported Since the 14 pin type connector is smaller than the 36 pin type 1 2 5 the area where the connector is installed on the user system can be reduced 13 NE S AS 1 3 Installing the H UDI Port Connector on the User System Table 1 3 shows the recommended H UDI port connectors for the emulator Table 1 3 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 36 pin connector DX10M 36S Hirose Electric Co Ltd Screw type DX10M 36SE Lock pin type DX10G1M 36SE 14 pin connector 2514 6002 Minnesota Mining amp 14 pin straight type Manufacturing Ltd Note When designing the 36 pin connector layout on the user board do not connect any components under the H UDI connector When designing the 14 pin connector layout on the user board do not place any components within 3 mm of the H UDI port connector 1 4 Pin Assignments of the H UDI Port Connector Figures 1 1 and 1 2 show the pin assignments of the 36 pin and 14 pin H UDI port connectors respectively Note Note that the pin number assignments of the H UDI port connector shown on the following pages differ from those of the connector manufacturer 2tENESAS Input Output 1 Output SH7751R Pin No 220 Signal AUDCK Note SH7751R Pin No TMS 1 Signal GND GND AUDATAO Output 223 TRST GND GND AUDATA1 Output 2
27. he products described herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges 10 Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you 11 In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detach
28. hnology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations 4 All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com 5 Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document 6 When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas product
29. instruction cache the delay after the second cycle is counted by the ECF In the PFB all branch instructions can be counted 14 NE S AS c Counting method One of the following methods can be specified by each of measurement channels 1 and 2 1 Counted by the CPU operating clock 2 Counted by the ratio of the CPU operating clock to the bus clock When the above method is specified one CPU operating clock cycle is counted as one When method 2 is specified the count is incremented by 3 4 6 8 12 or 24 according to the clock frequency ratio ratio of the CPU clock to the bus clock In this case the execution time can be calculated by the following expression T CxB 24 T Execution time B Time of one bus clock cycle C Count When the ratio of the CPU clock to the bus clock is changed in the user program it is recommended to select method 2 above to count the number of cycles The following shows examples to measure the performance of the user program by the performance measurement function i Measuring cache hit ratio Specify measurement channel 1 to count the cache misses for data read and write and specify measurement channel 2 to count operand accesses read and write to the cacheable area while the cache is enabled Specify with both the channels the measurement from the start to the end of user program execution With the above command settings the cache miss count and the access count to the cacheable area
30. is canceled by an exception DT and ET having a higher priority than that of the TLB miss Instruction fetch count When the instruction fetch request by the CPU is EF and EA accepted Instruction issue count Counts one when two instructions are issued at the E same time Counts one to three when instruction fetch exception E and E2 instruction address error instruction TLB miss exception or instruction TLB protection violation exception occurs FPU instruction issue count e Counts one when two instructions are issued at EFP the same time e The following shows the FPU instructions LDS Rm FPUL LDS L Rm FPUL LDS Rm FPSCR LDS L Rm FPSCR STS FPUL Rn STS L FPUL Rn STS FPSCR Rn STS L FPSCR Rn Others instructions that the instruction code is H Fxxx UBC satisfaction count Also counts when the emulator uses the UBC as UA and UB Break Condition 5 6 Pipeline freeze due to cache miss Includes the following freeze times PFCE and PFCD e At internal RAM or internal I O space access e Atinstruction or operand access without cache Pipeline freeze cycle due to branch instruction or exception 36 Counts only one cycle at branch instruction execution PFB except when the delay slot instruction is executed with one cycle delay One instruction is executed in one cycle which is similar to the branch count When the instruction in the branch destination does not exist in the
31. isfied 5 When execution resumes from the address where a BREAKPOINT is specified single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed 6 When a BREAKPOINT is set to the slot instruction of a delayed branch instruction the PC value becomes an illegal value Accordingly do not set a BREAKPOINT to the slot instruction of a delayed branch instruction 27 14 NE S AS 7 When the Normal option is selected in the Memory area group box in the General page of the Configuration dialog a BREAKPOINT is set to a physical address or a virtual address according to the SH7751R MMU status during command input when the VPMAP SET command setting is disabled The ASID value of the SH7751R PTEH register during command input is used When VPMAP SET command setting is enabled BREAKPOINT is set to a physical address into which address translation is made according to the VP MAP table However for addresses out of the range of the VP MAP table the address to which a BREAKPOINT is set depends on the SH7751R MMU status during command input Even when the MAP table is modified after BREAKPOINT setting the address translated at BREAKPOINT setting is valid 8 When the Physical option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address A BREAKPOINT is set after disabling the SH7751R
32. ite C Read Write Read Write Start address Ho End address Ho Figure 2 2 Window trace Page 22 12 NE S AS c Software Trace Function Note This function can be supported with SHC compiler manufactured by Renesas Technology Corp including OEM and bundle products V6 0 or later When a specific instruction is executed the PC value at execution and the contents of one general register are acquired by trace Describe the Trace x function x is a variable name to be compiled and linked beforehand For details refer to the SuperH RISC engine C C Compiler Assembler Optimizing Linkage Editor User s Manual When the load module is loaded on the emulator and a valid software trace function is executed the PC value that has executed the Trace x function the general register value for x and the source lines are displayed To activate the software trace function select the Software trace check box in the AUD function group box of the Trace mode page Notes on AUD Trace 1 If a TLB error occurs in the trace acquisition information display the Trace window displays the contents However mnemonics operands or source is not displayed When the trace display is performed during user program execution the mnemonics operands or source is not displayed When MMU settings are modified or when a user program is changed after GO command completion before trace display the displayed mnemoni
33. ite miss count reading or writing Instruction cache miss count EC The number of times instruction cache misses UTLB miss count DT The number of times UTLB misses occur at data access Instruction TLB miss count ET The number of times UTLB and ITLB misses occur at ITLB and UTLB misses instruction access Instruction cache miss count EF The number of times instructions are fetched from the cacheable area when the cache is enabled All instruction fetch count EA The number of times all instructions are fetched Branch instruction execution B The number of times branch instructions are issued count instructions to be counted BF other than displacement 0 BF S and BT other than displacement 0 BT S BRA BRAF and JMP Branch taken count BT The number of times branches are taken branches to be counted are the same as mode B BSR BSRF JSR instruction BBJ The number of times the BSR BSRF or JSR instruction is execution count issued Instruction execution count The number of times instructions are issued 34 13 NE S AS Table 2 10 Measurement Items cont Event Keyword Description Two instruction concurrent E2 execution count The number of times two instructions are issued at the same time FPU instruction execution EFP count The number of times FPU instruction is issued TRAPA instruction ETR execution count The number of times the TRAPA instruction is executed Interrupt count
34. mmand line window the stopping time will be about 8 ms 7 Interrupt When the NMIB bit in the ICR register is 1 the NMI interrupt is accepted during break and the program is executed from the NMI interrupt vector If the program cannot return normally from the NMI interrupt routine or the value in the general purpose register is not guaranteed a communication timeout error will occur 8 Memory Access during User Program Break The emulator can download the program for the flash memory area refer to section 6 22 Download Function to the Flash Memory Area in the SuperH Family E10A USB Emulator User s Manual Other memory write operations are enabled for the RAM area Therefore an operation such as memory write or BREAKPOINT should be set only for the RAM area When the memory area can be written by the MMU do not perform memory write BREAKPOINT break or downloading 9 Cache Operation during User Program Break When cache is enabled the emulator accesses the memory by the following methods e At memory write Writes through the cache then writes to the memory e At memory read Does not change the cache write mode that has been set Therefore when memory read or write is performed during user program break the cache state will be changed When the half of operand cache is used as an internal RAM and memory fill is performed in this area the verify option must be disabled Memory fill is not performed correctly if the verify option i
35. n executed 4 Ifa PC break before execution is set to the slot instruction after a delayed branch instruction user program execution cannot be terminated before the slot instruction execution execution stops before the branch destination instruction 5 Break Condition 5 6 use the UBC When the UBC is used in the user program change the UBC setting for users by using mode list box in the Configuration dialog box or the UBC mode command 6 Break Condition 1 4 are used as the measurement range in the performance measurement function when PA 1 start point and PA 1 end point are displayed on the Action part in the Break condition sheet of the Event window For setting the performance measurement function refer to section 2 2 6 Performance Measurement Functions This applies when the Break Condition is displayed with the BREAKCONDITION DISPLAY command in the 29 14 NE S AS command line function In this case a break does not occur when Break Condition 1 4 are satisfied Action conditiDisable 1 start point conditiDisable Break conditiDisable Break conditiDisable P l end point conditiDisable Break conditiDisable Break conditiDisable Break conditiDisable Break 4 Breakpoint Break condition Figure 2 5 Event Window 2 2 6 Performance Measurement Functions The emulator supports the performance measurement function 1 Setting the performance measurement conditions To set the perf
36. nditions No Break Condition 1 Sequential break condition 2 1 Description Program is halted when Break Condition 2 and Break Condition 1 are satisfied in that order Break Condition 2 1 should be set 2 Sequential break condition 3 2 1 Program is halted when Break Condition 3 Break Condition 2 and Break Condition 1 are satisfied in that order Break Condition 3 2 1 should be set 3 Sequential break condition 4 3 2 1 Program is halted when Break Condition 4 Break Condition 3 Break Condition 2 and Break Condition 1 are satisfied in that order Break Condition 4 3 2 1 should be set 4 Sequential break condition 6 5 2 3 2 Trace Functions Program is halted when Break Condition 6 and Break Condition 5 are satisfied in that order Break Condition 6 5 should be set The emulator supports the trace functions listed in table 2 6 Table 2 6 Trace Functions Function Internal Trace AUD Trace Branch trace Supported eight branches Supported 32 branches at continuous trace Internal I O access trace Supported non realtime Not supported LDTLB instruction execution trace Supported non realtime Not supported Range memory access trace Not supported Supported Software trace Not supported 14 NE S AS Supported 19 Table 2 7 shows the type numbers that the AUD function can be used Table 2 7 Type Number and AUD Function Type Number AUD Function HS0005K
37. ngly even if the MAP table is modified after BREAKPOINT setting the BREAKPOINT address remains unchanged When a BREAKPOINT is satisfied with the modified address in the VP MAP table the cause of termination displayed in the status bar and the Status window is ILLEGAL INSTRUCTION not BREAKPOINT 12 When a BREAKPOINT is set to the cacheable area the cache block containing the BREAKPOINT address is filled immediately before and after user program execution 13 While a BREAKPOINT is set the contents of the instruction cache are disabled at execution completion 14 If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area a mark will be displayed in the BP area of the address on the Source or Disassembly window by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the break condition the mark disappears 1 2 2 5 Notes on Setting the Break Condition Dialog Box and the BREAKCONDITION SET Command 1 When Go to cursor Step In Step Over or Step Out is selected the settings of Break Condition 3 are disabled 2 Break Condition 3 15 disabled when an instruction to which a BREAKPOINT has been set is executed Accordingly do not set a BREAKPOINT to an instruction which satisfies Break Condition 3 3 When a Break Condition is satisfied emulation may stop after two or more instructions have bee
38. on 5 6 are used as the UBC The condition match flag is 1 when each channel in the UBC is satisfied until the flag is cleared 2 CPU status acquisition function during standby The read value during standby cannot be guaranteed 44 2tENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7751R Publication Date Rev 1 00 March 15 2004 Rev 2 00 March 19 2007 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2007 Renesas Technology Corp All rights reserved Printed in Japan RenesasTechnology Corp Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan 5 5 SALES OFFICES http www renesas com Refer to http www renesas com en network for the latest and detailed information Renesas Technology America Inc 450 Holger Way San Jose CA 95134 1368 U S A Tel 1 408 382 7500 Fax 1 408 382 7501 Renesas Technology Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax lt 44 gt 1628 585 900 Renesas Technology Shanghai Co Ltd Unit 204 205 AZIACenter No 1233 Lujiazui Ring Rd Pudong District Shanghai China 200120 Tel 86 21 5877 1818 Fax 86 21 6887 7898 Ren
39. one user program execution Therefore do not specify this range when the step is to be executed In addition the user program execution stops when continuous trace is used again do not specify the first range in this case 31 14 NE S AS In the second range PA 1 start point and PA 1 end point are displayed on the Action part in the Break condition sheet of the Event window Action conditiDisable 1 start point conditiDisable Break conditiDisable Break conditiDisable 1 end point conditiDisable Break conditiDisable Break conditiDisable Break conditiDisable Break 4 Breakpoint Break condition Figure 2 7 Event Window Break condition Sheet In this case break will not occur when the conditions of Break Condition 1 and Break Condition 4 are satisfied Note When the range is specified be sure to set the measurement start and end conditions for Break Condition 1 and Break Condition 4 respectively and then execute the user program If Break Condition 1 or Break Condition 4 is not set and the user program is executed performance is not measured normally In this case the following dialog box is displayed High performance Embedded Workshop 1 is not available No ND Figure 2 8 High performance Embedded Workshop Dialog Box Q Break condition or 4 is not setting Continue 32 RENESAS b Measurement item Items are measured with Channel 1 to 2 in the
40. ork resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect the signal lines to other components on the board When the power supply of the user system is turned off supplying VccQ of the user system to the UVCC pin reduces the leakage current from the emulator to the user system A level shifter that is activated by the internal power supply or user power supply changed by the switch is installed in the interface circuit of the emulator If the user power is supplied to the UVCC pin the level shifter is not activated as long as no user power is supplied When the power supply of the user system is turned off no current flows from the user interface The I O voltage level of the user system interface can be the same as that of the VccQ To operate the emulator with low voltage lower than 3 3 V the VccQ must be supplied to the UVCC pin Make the emulator s switch settings so that the VccQ will be supplied SW2 1 and SW3 1 as shown in figure 1 5 The resistance values shown in figures 1 5 and 1 6 are recommended For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MPU 13 NE S AS When the circuit is connected as shown in figure 1 5 the switches of the emulator are set SW2 and SW3 1 For details refer to section 3 8 Se
41. ormance measurement conditions use the CPU Performance dialog box and the PERFORMANCE SET command When any line on the Performance Analysis window is clicked with the right mouse button the popup menu is displayed and the CPU Performance dialog box is displayed by selecting Setting 30 RENESAS GPU Performance GPU performance OPU performance Channel 1 Dont care Mode Operand access countlread with cache Count clock clock Ratio for Cpu and Bus clock v Use range Channel 2 Dont care Mode Operand ss countread with cache Count clock 6 Cou cioci C Ratio tor and Bus cloc USe range Set range Start point End point Figure 2 6 CPU Performance Dialog Box Note For the command line syntax refer to the online help The emulator measures how many times the conditions of the user program specified with the performance analysis function are satisfied For this function two events can be measured simultaneously and the following conditions can be specified a Measurement range One of the following ranges can be specified by either of measurement channels 1 and 2 1 From the start to the end of the user program execution 2 From the satisfaction of the condition set in Break Condition 1 to the satisfaction of the condition set in Break Condition 4 When the first range is specified the measurement result includes a several cycle error for
42. played by selecting Property from the popup menu with the right mouse button to display the Extended Monitor Configuration dialog box Select the check boxes in the Settings group box for the items that are to be displayed 42 7tENESAS Extended Monitor Configuration 00000000 00000000 00000000 00000000 00000000 00000000 v MMUCR AT 2 Figure 2 9 Extended Monitor Configuration Dialog Box 43 13 NE SAS The items that have been selected are displayed in the Extended Monitor window Extended Monitor PC 00000000 SR 00000000 FPSCR 00000000 INTEVT 00000000 EXPEVT 00000000 FRQCR 00000000 MMUCR AT H O ASID 00 00000000 SBUS 00000000 EBUS 00000000 SBTYPE 0000 00000000 STATUS 00 Condition matcl i 0 0 4 0 BC3 0 2 0 Condition matcli 0 BC4 0 3 0 2 0 Figure 2 10 Extended Monitor Window Notes 1 CPU status acquisition function Condition match flag The Break Condition function clears the condition match flag after a break occurred Therefore note that there are following limitations on measurement of this function Break Condition 1 4 Have meaning when they are used as the measurement start end condition in the performance measurement function In other cases they are invalid in this product Break Condition 2 3 5 6 Are invalid in this product When Break Conditi
43. s 7 With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above 8 Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications 9 You should use t
44. s enabled 10 UBC When User is specified in the UBC mode list box in the Configuration dialog box the UBC can be used in the user program Do not use the UBC in the user program as it is used by the emulator when EML is specified in the UBC mode list box in the Configuration dialog box 13 NE S AS 11 Loading Sessions Information in JTAG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be 0 625 MHz 12 IO Window Display and modification Do not change values of the User Break Controller because it is used by the emulator For each watchdog timer register there are two registers to be separately used for write and read operations Table 2 2 Watchdog Timer Register Register Name Usage Register WTCSR W Write Watchdog timer control status register WTCNT W Write Watchdog timer counter WTCSR R Read Watchdog timer control status register WTCNT R Read Watchdog timer counter The watchdog timer operates only when the user program is executed Do not change the value of the frequency change register in the IO window or Memory window The internal I O registers can be accessed from the IO window However note the following when accessing the SDMR register of the bus state controller Before accessing the SDMR register specify addresses to be accessed in the I O register definition file SH7751R IO and then activate the High performance Emb
45. s initiated from the workspace a value to be entered is saved in a session Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP H 00000000 RO BANK to R7 BANK H 00000000 PC H A0000000 SR H 700000F0 GBR H 00000000 VBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 DBR H 00000000 SGR H 00000000 SPC H 00000000 SSR H 000000F0 FPUL H 00000000 FPSCR H 00040001 FRO to FR15 H 00000000 XFO to XF15 H 00000000 2 The emulator uses the H UDI do not access the H UDI 14 NE S AS 3 Low Power States Sleep Standby and Module Standby For low power consumption the SH7751R has sleep standby and module standby modes The sleep and standby modes are switched using the SLEEP instruction When the emulator is used the sleep and standby modes can be cleared by either normal clearing or with the STOP button Note that however if a command has been entered in standby mode or module standby mode the TIMEOUT error is displayed Notes 1 After the sleep mode is cleared by a break execution restarts at the instruction 4 following the SLEEP instruction 2 Ifthe memory is accessed or modified in sleep mode the sleep mode is cleared and execution starts at the instruction following the SLEEP instruction 3 If an operation such as the command input is performed in the hardware standby state the command
46. s the FRQCR register value MMUCR AT H 0 Displays the AT bit value in the MMUCR register ASID H 01 Displays the ASID value in the PTEH register CCR H 00000001 Displays the CCR register value SBUS H 00000000 Displays the load store bus address internal bus EBUS H 0000000 Displays the external bus address SBTYPE B 1101 Displays the internal bus state Each bit has the following meanings Bit3 Bus access 0 Without bus access 1 With bus access If bit 3 is O other bits of SBTYPE and all bits of SBUS are invalid 39 14 NE S AS Table 2 12 Display Status cont Item Example Description SBTYPE cont B 1101 Bit2 Read or write cycle 0 Read cycle 1 Write cycle Bit1 0 Bus width Bit1 0 BitO 0 8 bit bus width Bit1 0 BitO 1 16 bit bus width 1 1 BitO 0 32 bit bus width 1 1 BitO 1 64 bit bus width EBTYPE B 0000000 Displays the external bus state Each bit has the following meanings 5 Bus mode at DMA transfer Displays an invalid value in the CPU access 0 Burst mode 1 Cycle steal mode Bit4 CPU access or DMAC access 0 Access from CPU 1 Access from DMAC Bit6 3 2 One transfer unit in DMA transfer Bit6 0 Bit3 0 Bit2 0 64 bits Bit6 1 Bit3 0 Bit2 0 32 bytes Bit6 0 1 Bit8 0 Bit2 1 8 bits Bit6 0 1 Bit8 1 Bit2 0 16 bits Bit6 0 1 Bit8 1 Bit2 1 32 bits These bits indicate memory access in the chip instead of the bus width Bit1 Read or write cycle 0 Read cycle 1 Wri
47. t the Acquire exception branch instruction trace check box in the Branch trace page Continuous trace Acquires the trace information continuously This is called continuous trace For the branch instruction trace eight branch information can be repeatedly acquired a maximum of four times Select the Acquire continuous trace check box in the Branch trace page If continuous trace is selected realtime trace cannot be performed 25 14 NE S AS Table 2 9 Internal Trace Functions cont Function Description Internal I O trace Traces and displays the address and data that access the internal I O area To use this function select the Get trace information of internal I O Area radio button in the Break Condition 7 dialog box and the Acquire continuous trace check box in the Branch trace page LDTLB instruction execution trace Traces and displays the address that executes the LDTLB Notes 26 1 instruction To use this function select the Get trace information of LDTLB instruction radio button in the Break Condition 8 dialog box and the Acquire continuous trace check box in the Branch trace page When the continuous trace is not used trace acquisition of the eight latest branch instructions is enabled If an interrupt is generated at the program execution start or end including a step operation the emulator address may be acquired In such a case the following message will be displaye
48. te cycle Bit0 Bus access 0 Without bus access 1 With bus access If bit O is O other bits of EBTYPE and all bits of EBUS are invalid Note When bit 0 is 1 and bit 4 is 0 bits 5 and 6 become invalid STATUS B 00 Displays the STATUS pin state 40 13 NE S AS Table 2 12 Display Status cont Item Example Description Condition match A 0 Displays whether the channel A condition of the UBC has flag been satisfied When the UBC is used as a Break Condition it displays whether Break Condition 6 has been satisfied 0 Not satisfied 1 Satisfied B 0 Displays whether the channel B condition of the UBC has been satisfied When the UBC is used as a Break Condition it displays whether Break Condition 5 has been satisfied 0 Not satisfied 1 Satisfied BC1 0 Displays whether Break Condition 1 has been satisfied 0 Not satisfied 1 Satisfied BC2 0 Displays whether Break Condition 2 has been satisfied 0 Not satisfied 1 Satisfied BC3 0 Displays whether Break Condition 3 has been satisfied 0 Not satisfied 1 Satisfied BC4 0 Displays whether Break Condition 4 has been satisfied 0 Not satisfied 1 Satisfied Condition match A 0 When the sequential break condition of the UBC is flag for sequential selected this bit is 1 when the channel A condition has break been satisfied and the channel B condition has not been satisfied When the UBC is used as a Break Condition channel A and ch
49. tting the Switches in the SuperH Family E10A USB Emulator User s Manual VccQ 3 3 V I O power supply Pulled up at 4 7 kQ or more all VccQ VccQ VccQ VccQ H UDI port connector SH7751R 14 pin type QFP256 TCK TRST TMS TDI RESETP Reset signal User system Figure 1 5 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 14 Pin Type UVCC Connected 11 14 NE S AS When the circuit is connected as shown in figure 1 6 the switches of the emulator are set SW2 0 and SW3 1 For details refer to section 3 8 Setting the Switches in the SuperH Family E10A USB Emulator User s Manual VccQ 3 3 V I O power supply Pulled up at 4 7 KQ or more all VccQ VccQ VccQ VccQ H UDI port connector SH7751R 14 pin type QFP256 lt Reset signal User system Figure 1 6 Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 14 Pin Type UVCC Not Connected Note When UVCC is not connected and the user system is turned off note that the leakage current flows from the emulator to the user system 12 13 NE S AS Section 2 Specifications of the Software when Using the SH7751R 2 1 Differences between the SH7751R and the Emulator 1 When the emulator system is initiated it initializes the general registers and part of the control registers as shown in table 2 1 When the emulator i
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