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User Manual MIC-3396

1. 75 J5 amaca ere NUI 76 Table A 5 J5 CompactPCI I O 76 Other Connector Su 77 Table A 6 SATA1 Daughter Board Connector 77 Table A 7 J15 P15 XMC1 77 Table A 8 VGA1 Connector 77 Table A 9 1 RJ45 Connector 78 Table A 10 USB2CN1 USB3CN1 4 0583 2 78 Table A 11 BH1 CMOS 5031 661 78 Table A 12 RJ45 LAN Connector 78 6 1 PWR BMC HDD and Hot swap LEDs 79 Programming the Watchdog Timer 81 eI 84 84 FPGA wie 84 Table 1 LPC I O registers 84 GOSS ENV M uuu O5 Hardware Configuration This chapter describes how to configure MIC 3396 hardware 11 Introduction The MIC 3396 is a high performance power efficient CompactPCl single board com puter based on the Intel Core i3 i5 i7 microprocessors The MIC 3396 delivers breakthrough energy efficient performance for CompactPCI platforms The Intel Core i3 i5 i7 provides enhanced energy efficient
2. 34 Figure 2 15Out of Band Mgmt 35 Figure 2 16Terminal Type 35 Figure 2 17 Network 36 Figure 2 18NIC Configuration Settings 37 Figure 2 19Link Speed aaa 37 Figure 2 20NIC Configuration Settings 38 Figure 2 21 Link Speed ise sescenti rende 38 2 3 3 Chipset Configuration Setting 39 Figure 2 22Chipset Configuration Settings 39 Figure 2 293V 1 2 EGS ia ga Ear a ER ER 39 Figure 2 24Graphics 40 Figure 2 25L CD Control tts 41 Figure 2 26NB PCle Configuration esses 42 Figure 2 27 Memory Configuration 43 Figure 2 28PCI Express Configuration 43 Figure 2 29USB Configuration 44 Figure 2 30PCH Azalia 44 2 3 4 Boot Configuration sse 45 Figure 2 31Boot Configuration 45 Figure 2 32Hard Drive BBS Priorities 46 Figure 2 33CSM16 46 F
3. 58 EI erc 58 3 7 1 Sensor e 58 Table 3 3 BMC sensor list 58 3 7 2 Threshold based 59 Table 3 4 Sensor Threshold description 59 3 7 3 Voltage Sensors iiit ede ee 59 Table 3 5 Voltage Sensor 59 3 7 4 Temperature Sensors 60 Table 3 6 Temperature Sensor List 60 3 7 5 Integrity oit tt erdt eee HE ettet pene tid 60 Table 3 7 Integrity Sensor event data table 60 OEM IPMI 5 2 a 61 Table 3 8 OEM command llist 61 3 8 1 Store Configuration Command 62 Table 3 9 Store Configuration Settings Command 62 3 8 2 Read Configuration Command 64 Table 3 10 Read Configuration Settings Command 64 3 8 3 Read Port 80 Command 66 Table 3 11 Read Port 80 command BIOS POST code 66 3 8 4 Read MAC Address 66 Table 3 12 Read MAC Address Command 66 3 8 5 Reload BMC Default Configuration Command
4. 1 SATA Support 1 1 1 i KI ot gt lt Select Screen v Select Item Enter Select Change F1 General Help F2 Previous Values F3 Optimized Defaults F4 Save 5 Exit v ESC Exit Figure 2 8 SATA configuration This items allow users to enable or disable SATA function m Disabled Disable SATA function MIC 3396 User Manual 28 SATA Mode Selection This item allows users to determine how SATA controller s operate It can be configured as IDE AHCI or RAID mode IDE mode Set to IDE mode when you want to use the serial ATA hard disk drives as Par allel ATA physical storage devices ACHI mode Set to AHCI mode when you want the SATA hard disk drives to use the AHCI Advanced Host Controller Interface The AHCI allows the onboard storage driver to enable advanced serial ATA features that increase storage perfor mance on random workloads by allowing the drive to internally optimize the order of commands RAID mode Set to RAID mode when you want the SATA hard disk drives to use the RAID mode The Intel RAID function allows the user to build up RAIDO RAID1 29 MIC 3396 User Manual 2 19429 dmes 5018 INY Press Ctrl I into Intel Rapid Storage Technology Option ROM on RAID Disk Non RAID Disk MIC 3396 User Manual 30 Figure 2 9 RAID mode 2 3 2 6 8 COMO PuTTY LUu x USB Configuration 1 Keyboard 2
5. 66 Table 3 13 Reload BMC Default Configuration Command 66 HPM 1 Upgrade 67 Table 3 14 Supported HPM 1 components 67 3 9 1 Bootloader updat J ttd a as 67 3 9 2 Firmware upgrade eii o a 67 3 9 3 FPGA upgrade ice d 67 29 04 BIOS ei eL o ER Pit Ra nga xa 67 Board Informatiof et ett oet Le ue 68 3 10 1 Board 68 Table 3 15 Board Info Area 68 3 10 2 Product 69 Table 3 16 Product Info 69 JA COMME COR sais NU 72 Table A 1 J1 CompactPCI I O 72 ix MIC 3396 User Manual A 2 A 3 4 5 6 Appendix C 1 2 C 3 Appendix D MIC 3396 User Manual J2 heat 73 Table A 2 J2 CompactPCI 73 CONNECCION 74 Table A 3 J3 CompactPCI I O LAN2 LANS 2 16 74 CONNEC e uns LS NI II 75 Table A 4 J4 CompactPCI I O
6. Figure 2 10 USB configuration Legacy USB Support Enables support for legacy USB Auto option disables legacy support if no USB devices are connected Disable option will keep USB device available only for EFI applications USB3 0 support Enable or disable USB3 0 Controller support m XHCI Hand off This is a workaround for OSes without XHCI hand off support 31 MIC 3396 User Manual m Hand off This is just a workaround item under OS without EHCI hand off support m USB Mass Storage Drive Enable or disable USB Mass Storage Driver Support USB transfer time out The time out value for Control Bulk and Interrupt transfers Device reset time out USB mass storage device start unit command time out Device power up delay Maximum time the device will take before it properly reports itself to the host controller 2 3 2 7 Super I O Configuration Port 0 Configuration DET OI arar TN L Port 1 Configuratio MIC 3396 User Manual 32 Serial Port 0 1 Configuration For serial port 0 1 IRQ IO mode resource configuration users can choose IRQ IO and MODE ti setup Advanced Port 0 Configuration Enable or Disable Serial Port COM Settings 0 IRQ 4 Settings gt lt Select Screen 79 Select Item Enter Select 1 Change Opt IF1 General Help F2 Prev ous Values F3 Optimized Defaults F4 Save amp Exit 5 Exit Port 1 Configurat
7. MIC 3396 User Manual 82 Appendix C FPGA This appendix describes FPGA configuration C 1 Overview Advantech BMC solution combines a NXP LPC1768 ARM Cortex M3 based 32 bit microcontroller and a Lattice XP2 series FPGA The FPGA mainly integrates hard ware interfaces which are not available or not available in the right amount inside the LPC1768 like or KCS As the MIC 3396 will be available in versions both with and without the BMC some functions will be implemented redundant inside the FPGA and BMC If the BMC is populated a simple register inside the FPGA is used to control the regarding function from the BMC On a MIC 3396 without BMC the FPGA controls the function by itself in the same way as before C 2 Features Drone Mode Hot Swap Hot insertion and removal control CompactPCI Backplane CompactPCI slot Addressing LPC Interface Provides LPC Bus access KCS Interface Standard IPMI payload interface from x86 to BMC Watchdog Debug Message Boot time POST message FPGA I O Registers The Advantech MIC 3396 FPGA communicates with main I O spaces The LPC unit is used to interconnect the Intel QM87 LPC signals The Debug Port Unit is used to decode POST codes The Hot Swap Out Of Service LED Control Unit is used to con trol the blue LED during Hot Insert and Hot Remove The Drone Mode Unit is used to disable the CPCI Bridge The other signals in the Miscellaneous Unit are for interfac ing with corr
8. or Non recoverable NR This classification is possible in both directions lower and upper When different thresholds are reached different actions may be executed by shelf manager accordingly Table 3 4 Sensor Threshold description Threshold Description UNR Upper Non Recoverable UCR Upper Critical UNC Upper Non Critical LNC Lower Non Critical LCR Lower Critical LNR Lower Non Recoverable Voltage Sensors The management power voltages and all other payload power voltages are moni tored by the BMC Table 3 5 Voltage Sensor List Sensor Name Nominal LNR LCR LNC UNC UCR UNR BAT 3 0 VOL 3 00 2 15 2 40 2 60 3 45 3 60 3 70 SB 3 3 VOL 3 30 2 90 3 00 3 15 3 45 3 60 3 70 SB 5 0 VOL 5 00 4 40 4 50 4 75 5 25 5 50 5 60 PAY 3 3 VOL 3 30 2 90 3 00 3 15 3 45 3 60 3 70 PAY 5 0 VOL 5 00 4 40 4 50 4 75 5 25 5 50 5 60 PAY 12 VOL 12 0 9 90 10 2 10 8 13 2 13 8 14 1 PCH 1 05 VOL 1 05 0 88 0 945 0 99 1 11 1 155 1 22 PCH 1 5 VOL 1 5 1 26 1 35 1 425 1 575 1 65 1 74 PCH_1_0 VOL 1 00 0 88 0 90 0 93 1 07 1 10 1 12 CPU_CORE VOL 1 80 1 58 1 62 1 71 1 89 1 98 2 02 AUX 3 3 VOL 3 30 2 90 3 00 3 15 3 45 3 60 3 70 HP 3 3 VOL 3 30 2 90 3 00 3 15 3 45 3 60 3 70 HP 5 0 VOL 5 00 4 40 4 50 4 75 5 25 5 50 5 60 HP 12 0 VOL 12 0 9 90 10 2 10 8 13 2 13 8 14 1 59 MIC 3396 User Manual 3 7 4 Temperature Sensors Several temperature sensors are supported either via board populated IC s or Intel PECI r
9. CPU C6 state Supported F2 Prev ous Values CPU C7 state Supported F3 Optimized Defaults 4 Save 5 Exit v ESC Exit en oe ee ee ee MIC 3396 User Manual 26 x s nter Select lt Figure 2 7 CPU configuration Hyper Threading This item allows you to enable or disable Intel Hyper Threading technology Active Processor Cores It allows you to choose the number of CPU cores to activate in each processor package Limit CPUID Maximum This item allows you to limit CPUID maximum value Execute Disable Bit This item allows you to enable or disable the No Execution page protection technology Intel Virtualization Intel Virtualization Technology Intel VT is a set of hardware enhancements to Intel server and client platforms that provide software based virtualization solu tions Intel VT allows a platform to run multiple operating systems and applications in independent partitions allowing one computer system to function as multiple vir tual systems Hardware Prefetcher The processor fetches data and instructions from the memory into the cache are likely to be required in the near future This reduces the latency associated with memory reads Adjacent Cache Line Prefetcher This item allows users to enable or disable the adjacent cache line prefetcher feature EIST This item allows users to enable or disable Intel Spee
10. 0 GND VGA_BLUE GND RTMA LINK _ 2 16 LINK10 18 GND ACTH ACTH 00 UART2 RTS GND GND 19 GND COM1_RX COM1 CTS COM2_DCD COM2_TX GND 20 GND COM1_TX COM1_DSR RTM PRESZ COM2_RTS COM2_DTR GND 21 GND COM1_RTS COM1_DTR UART2_TXD COM2_CTS 2 GND 22 GND COM1_DCD COM1 RI UART2 RXD COM2_DSR COM2_RX GND Note NC No Connection as Active Low MIC 3396 User Manual 76 A 6 Other Connector Table 6 SATA1 Daughter Board Connector 1 GND 2 GND 3 SATA0_TX 4 NC 5 SATA0_TX 6 NC 7 GND 8 GND 9 SATA0_RX 10 NC 11 SATA0_RX 12 NC 13 GND 14 GND 15 GND 16 GND 17 VCC5 18 VCC3 19 VCC5 20 VCC3 Table A 7 J15 P15 XMC1 Connector Pin A B 0 D E F 1 PO PETX NO 3 3 1 1 VPWR 5V 2 GND NC JRST GND GND PRST PETX P2 PETX N2 3 3 VPWR 5V 4 GND GND NC JTCK GND NC MRSTO 5 PETX_P4 PETX_N4 3 3 _ 5 5 VPWR 5V 6 GND NC JTMS GND GND 12V 7 PETX P6 PETX N6 3 3 _ 7 PETX_N7 VPWR 5V 8 GND GND NC JTDI GND GND 12V NC NC NC NC VPWR 5V 10 GND GND NC JTDO GND GAO 11 PERX PO PERX NO NC MBIST PERX PERX N1 VPWR 5V 12 GND GND GND MPRESENT 13 PERX_P2 PERX_N2 22 PERX_P3 PERX_N3 VPWR 5V 14 GND GND
11. 2 1210 2x SATA II 6GB s gt USB 3 0 1x Intel ynx Poin A DVI x2 SPI SP 8MByte USB 3 0 2 USB 1x 20 Bem UART 2 M SATA II 3GB FPGA 2x gt From Super m AER rto ET EET 1 mm NVRAM Yer Handle SW 27 2 5 SSD SATA NRA nc Figure 1 1 MIC 3396 functional block diagram 7 MIC 3396 User Manual 1 4 1 4 1 Jumpers and Switches Table 1 4 and table 1 5 list the jumper and switch functions Read this section care fully before changing the jumper and switch settings on your MIC 3396 board Table 1 4 MIC 3396 jumper descriptions Number Function CN1 Clear CMOS J5 Switch VGA output to front panel or to rear Number Function SW1 1 PCI Bridge Master Drone Mode SW1 2 Drone Mode PCI bus Reset SW2 Front COM amp RTM COM1 COM2 ports selection for BMC SIO UART Clear CMOS CN1 This jumper is used to erase CMOS data Follow the procedures below to clear the CMOS 1 Turn off the system 2 Close jumper CN1 for about 3 seconds 3 Setjumper CN1 as Normal 4 Turn on the system The BIOS is reset to its default setting Table 1 6 CN1 Clear RTC Closed Clear RTC Default Open Normal MIC 3396 User Manual 8 1 4 2 VGA Output JP5 This jumper is used to switch VGA output from front panel to rear Table 1 7 5 Default 1 2 Front Panel 2 3 Rear IO 3V3_S8 10
12. 3 3V AD 6 AD 5 GND 21 GND 3 3V AD 9 AD 8 M66EN C BE 0 GND 20 GND AD 12 GND V I O AD 11 AD 10 GND 19 GND AD 15 AD 14 GND AD 13 GND 18 GND SERR GND 3 3V PAR C BE 1 GND 17 GND 3 3V SCL IPMB SDA GND PERR GND 16 GND DEVSEL PCIXCAP STOP LOCK GND 15 GND 3 3V FRAME IRDY BD SELZ GND 12 14 KEY AREA 11 GND 18 AD 17 AD 16 GND 2 GND 10 GND AD 21 GND 3 3V AD 20 AD 19 GND 9 GND C BE 3 IDSEL AD 23 GND AD 22 GND 8 GND AD 26 GND V I O AD 25 AD 24 GND 7 GND _ 0 30 0 29 AD 28 GND AD 27 GND 6 GND REQO PRESENT 3 3V CLKO AD 31 GND 5 GND NC NC PCI GND GNTO GND 4 GND IPMB_PWR INTP INTS GND 3 GND INTA INTB INTC 5V INTD GND 2 GND TCK 5V TMS TDO TDI GND 1 GND 5V 12V TRST 12V 5V GND Pin Z A B C D E F Note No Connection Active Low MIC 3396 User Manual 72 2 2 Connector Table A 2 42 CompactPCI I O Pin 7 A B 0 D E F 22 GND GA4 GA3 GA2 GAO GND 21 GND CLK6 GND NC NC NC GND 20 GND 5 GND NC GND 49 GND NC GND SMB SDA SMB SCL SMB ALERT GND 18 GND NC NC GND NC GND 17 GND GND PRST REQ6 GNT6 GND 16 GND NC DEG GND NC GND 15 GND GND FAL REQ5 GNT5 GND 14 GND AD 35 AD 34 AD 33 GND AD 32 GND 13 GND AD 38 GND AD 37 AD 36 GND 12 GND 1 0 42 AD 41 AD
13. 40 GND AD 39 GND 11 GND 0 45 GND AD 44 43 GND 10 GND AD 49 48 AD 47 GND AD 46 GND 9 GND 0 52 GND V IO AD 51 AD 50 GND 8 GND AD 56 AD 55 AD 54 GND AD 53 GND 7 GND AD 59 GND V IO AD 58 AD 57 GND 6 GND AD 63 AD 62 AD 61 GND AD 60 GND 5 GND C BE 5 GND 64EN V I O C BE 4M PAR64 GND 4 GND C BE 7 GND C BE 6 GND 3 GND CLK4 GND GNT3 4 gt O GNT4 GND 2 GND CLK2 CLK3 SYSEN GNT2 REQ3 GND 1 GND CLK1 GND REQi GNT1 REQ2 GND Pin 7 A B 0 D E F Note NC No Connection Active Low E 73 MIC 3396 User Manual A 3 J3 Connector PCle port only support X8 link Table 3 CompactPCI I O LAN2 LAN3 2 16 Pin F A B C D E Z 1 GND 12 PCIE_TX12 VCC5 PCIE RX12 PCIE_RX12 GND 2 GND PCIE_TX8 PCIE RX8 VCC5 PCIE TX9 PCIE 9 GND 3 GND TX8 PCIE RX8 VCC5 PCIE TX9 PCIE RX9 GND 4 GND 13 13 VCC5 PCIE RX13 PCIE_RX13 GND 5 GND PCIE_TX10 PCIE_RX10 PLTRST PCIE_TX11 PCIE_RX11 GND 6 GND PCIE_TX10 PCIE_RX10 TMS PCIE TX11 RX11 GND 7 GND TX14 14 PCIE RX14 PCIE_RX14 GND 8 GND PCIE_CLK USB3_6TX TAP_TRST USB3_2TX USB3_2RX GND 9 GND PCIE_CLk USB3_6TX TAP_TDI USB3 2TX USB3
14. GA2 GND GND TBD_SDA 15 _ 4 PERX_N4 NC PERX P5 PERX N5 VPWR 5V 16 GND GND NC MVMRO GND GND TBD_SCLK 17 PERX P6 PERX N6 NC PERX P7 PERX N7 NC 18 GND GND 1 GND GND NC 19 100Mhz CLK_100Mhz FPGAIO2 NC WAKE NC Table 8 VGA1 Connector 1 RED 9 5V 2 GREEN 10 GND 3 BLUE 11 NC 4 NC 12 DDC_DATA 5 DET 13 HSYNC 6 GND 14 VSYNC 7 GND 15 DDC_CLK 8 GND MIC 3396 User Manual Table A 9 COM1 RJ45 Connector 1 DCD 6 DSR 2 SIN RX 7 RTS 3 SOUT TX 8 CTS 4 DTR 5 GND Table A 10 USB2CN1 USB3CN1 amp USB3CN2 USB2CN1 USB3CN1 USB3CN2 1 5V fused 1 5V fused 1 5V fused 2 USBDO 2 USBD1 2 USBD1 3 USBDO 3 USBD1 3 USBD1 4 GND 4 GND 4 GND 5 SSRX 5 SSRX 6 SSRX 6 SSRX 7 GND 7 GND 8 SSTX 8 SSTX 9 SSTX 9 SSTX Table A 11 BH1 CMOS battery 1 BAT_VCC GND Table A 12 RJ45 LAN Connector 1 LAN_0 5 2 2 0 6 LAN 1 3 LAN 1 7 LAN_3 4 LAN 2 8 LAN 3 SPEED LED 10Mbps 100M pps MIC 3396 User Manual OFF GREEN ORANGE 78 LINK ACTIVITY LED LINK GREEN ACTIVITY BLINK 6 1 PWR BMC HDD and Hot swap LEDs Name Description M D Green Indicates Master or Drone mode status PWR Green Indicates power status HDD Yellow I
15. General Help F2 Previous Values 1 3 Optimized Defaults IF4 Save 5 Exit 5 Exit Figure 2 21 Link Speed m Link Speed Specifies the port speed used for the selected boot protocol m Wake On LAN This item allows users to enable the server to be powered on MIC 3396 User Manual 38 2 3 3 Chipset Configuration Setting Select the chipset tab from the BIOS setup screen to enter the Chipset Setup screen Users can select any item in the left frame of the screen to go to the sub menu for that item Users can display a Chipset Setup option by highlighting it using the lt Arrow gt keys All Chipset Setup options are described in this section The Chipset Setup screens are shown below The sub menus are described on the following pages System Agent SA gt South Bridge Parameters 1 v Select Item jEnter Select Change Opt IF1 General Help 2 Previous Values 3 Optimized Defaults 4 Save 5 Exit I I 1 l l gt lt Select Screen l I 5 Figure 2 22 Chipset Configuration Settings 2 3 3 1 North Bridge Configuration VT d Capability System Agent Bridge N Haswell Check to enable VI d System Agent RC Versi 1 3 0 0 function Capability Supported 1 I Enable NB CRID Disabied 1 gt Graphics Configuration I gt NB PCIe Configuration gt Memory configuration I gt lt Select S
16. Gigabit Ethernet ports one RJ 45 COM port two USB 3 0 and one USB 2 0 ports one VGA connector and one XMC PMC knockout Its onboard I O consists of one SATA channel can be connected to a daughter board for 2 5 SATA HDD and CFast slot An on board flash is as option Rear I O connectivity is available via the following CompactPCI connectors 3 uses UHM connector which can support USB3 0 SATA Gen and PCI Express x8 Two Gigabit Ethernet links to the backplane for PICMG 2 16 packet switch two SATA Gen III ports one PClex8 and two USB 3 0 ports on the RTM 4 one LVDS Audio output MIC input and one DVI J5 One Gigabit Ethernet LAN port one GbE can be switched from front panel two COM ports four USB 2 0 one PS 2 for keyboard mouse and one DVI port 1 2 18 PMC PCI Mezzanine Card IEEE1386 1 Compliant Additional or co processing functionality is supported by add on PMC modules The MIC 3396 supports one PMC site that is fully compliant with the IEEE1386 1 PCI Mezzanine Card specification PMC supports both 64bit 66 MHz and 32 bit 33 MHz PCI bus interface and both 3 3 V and 5 V VIO depending on usage MIC 3396 User Manual 6 The two layer front panel design complies with IEEE 1101 10 Connectors are firmly screwed to the front panel and a shielding gasket is attached to the panel edge This reduces emissions and increases protection from external interference 1 2 19 Hardware Monitor
17. ay aa ena Re 4 1 2 11 LED l u aS b ge c 4 1 212 Watchdog TMe ssa 5 1 2 13 Optional Rear I O 5 Table 1 3 RIO 3316 5 1 2 14 Mechanical and Environmental 5 5 1 2 15 Compact Mechanical Design 5 1 2 16 CompactPCl Bridge u rtt eet ete 6 1 217 VO Connectivity iE eerte Gita tu ated 6 1 2 18 PCI Mezzanine IEEE1386 1 Compliant 6 1 2 19 Hardware 6 1 2 20 S per VO eere 7 1 2 21 RIC and Battery iie as Bc 7 JE 7 Functional Block iint iani vetet aera bb etes 7 Figure 1 1 MIC 3396 functional block diagram 7 Jumpers and 8 Table 1 4 MIC 3396 jumper descriptions 8 Table 1 5 MIC 3396 switch descriptions 8 1 4 1 Clear CMOS CN1 8 Table 1 6 1 Clear RTC 8 1 4 2 VOA Output 9 Table 4 72 PS e detti bete 9 1 4 3 SSWILCM SOUINGS 10 Table 1 8 SW1 1 PCI Bridge Ma
18. info fields 0xC1 00h unused space 0x00 0x00 0x00 0x00 0x00 Board area checksum calculated MIC 3396 User Manual 68 3 10 2 Product Information Table 3 16 Product Info Area Field description Product information Format version 0x01 Product area length calculated Language code 0x19 English Product Manufacturer type length 0xC9 Product manufacturer Advantech Product name type length 0xC8 Product name MIC 3396 Product part model number type length 8 Product part model number MIC 3396 Product version type length 0xC5 Product version Hardware Version Product serial number type length Product serial number Assert Tag type length 10 characters written during manufacturing 0xC0 Assert Tag unused FRU File ID type length 0xCB FRU File ID frudata xml Custom product info area fields unused C1h no more info fields 0xC1 00h any remaining unused space 0x00 Product area checksum calculated 69 MIC 3396 User Manual MIC 3396 User Manual 70 Pin Assignments This appendix describes pin assignments 1 Connector Table A 1 J1 CompactPCI I O Pin Z A B C D E F 25 GND 5V REQ64 ENUM 3 3V 5V GND 24 GND AD 1 5V V I O AD 0 ACK64 GND 23 GND 1 3 3 AD 4 AD 3 5V AD 2 GND 22 GND AD 7 GND
19. 2RX GND 10 GND PCIE_TX15 PCIE_TX15 USB3 6RX USB3_6RX GND 11 GND GND GND VCC3 PCIE RX15 PCIE_RX15 GND 12 GND 5 4 SATA4 RX VCC3 SATA5 TX 5 RX GND 13 GND 5 4 TX SATA4_RX VCC3 SATA5_TX SATA5_RX GND 14 GND GND GND VCC3 GND GND GND 15 GND 1 MDIB1 GND MDIB3 MDIB3 GND 16 GND MDIBO MDIBO GND MDIB2 MDIB2 GND 17 GND MDIA1 MDIA1 GND MDIA3 MDIA3 GND 18 GND MDIAO MDIAO GND MDIA2 MDIA2 GND 19 GND INC NC SATA_LED NC NC GND Note No Connection Active Low 74 MIC 3396 User Manual Connector 4 4 Table 4 CompactPCI I O port Pin 7 A B D E F 1 GND TXD3 GND DDI2_AUX USB1_VCC GND 2 GND UART_RXD3 NC GND DDI2_AUX USBD1 GND 3 GND UART_RTS3 GND GND NC USBD1 GND 4 GND NC NC GND DDI2_PAIRO GND GND 5 GND NC GND 19012 USB3_VCC GND 6 GND NC GND 0012 1 USBD3 GND 7 GND NC NC GND DDI2_PAIR1 USBD3 GND 8 GND NC NC GND 0012 2 GND GND 9 GND NC NC GND DDI2_PAIR2 DDI2 DDC CLK GND 10 GND NC GND 0012 DDI2 DDC DAT GND 11 GND INC NC GND 19012 DDI2_HPD GND 12 14 15 GND NC NC GND AUDIO_GND MIC_L GND 16 GND INC NC GND NC MIC_R GND 17 GND NC GND GND LINE_JD LINEIN_L GND 18 GND NC GND LINEOUT_L LINEIN_R GND 19 GND NC GND LINEOUT_R TBD LOUT_L GND 20 GND NC GND A
20. Advanced BIOS features setup screen 2 3 2 1 PCI Subsystem Setting Value to be programmed linto PCI Latency Timer Register PCI Common Settings 1 VGA Palette Snoop Disabled PERRE Generation Disabled SERR Generation Disabled gt PCI Express Settings gt lt Select Screen Iv Select Item jEnter Select 1 Change Opt 1 1 General Help 1 2 Previous Values F3 Optimized Defaults F4 Save 5 Exit 5 Exit m Fr n e I 23 MIC 3396 User Manual Maximum Payload Request Maximum Read Figure 2 4 PCI Setting m Latency Timer Value to be programmed into PCI Latency Timer Register VGA Palette Snoop This item allows user to enables or disables VGA Palette Register Snooping Express Settings Set Maximum Payload of PCI Express Device or allow System BIOS to select the value Maximum Payload Set Maximum Payload of PCI Express Device or allow System BIOS to select the value m Maximum Read Request Set Maximum Read Request Size of PCI Express Device or allow system BIOS to select the value MIC 3396 User Manual 24 2 3 2 2 ACPI Setting Enable Hibernation fEnabled Sleep State 153 only Suspend to System ACPI Parameters Enable Hibernation Enable or Disable System Hibernation OS S4 Sleep State This option may be not effective with some OS ACPI Sleep State Select the ACPI sleep state the system will enter when the SUSPEND button is pre
21. Hz 3 5 37W 30 I7 4700EQ 4 8 2 2GHz 6MB 5GT s 47W FCBGA 30 Note Because power consumption and thermal restrictions vary between dif ferent CompactPCI systems please double check these items before B installing a higher speed CPU not listed in the table above BIOS An 8 MB SPI flash contain a board specific BIOS from AMI designed to meet indus trial and embedded system requirements Chipset The Intel Mobile QM87 chipset provides excellent flexibility for developers of embed ded applications by offering improved graphics and increased I O bandwidth over previous Intel chipsets as well as remote asset management capabilities and improved storage speed and reliability The Mobile Intel QM87 chipset offers up to 5 GT s for fast access to peripheral devices It delivers outstanding system performance through high bandwidth interfaces such as PCI Express Serial ATA and Hi Speed USB 2 0 and USB 3 0 Memory The MIC 3396 has up to 8 GB of onboard with ECC support DDR3L memory It also has one 240 pin SO DIMM socket that can accommodate an additional 2GB max to 8GB of memory The following table shows a list of SO DIMM modules that have been tested on the MIC 3396 Table 1 2 Memory Type Brand Size Speed Vendor PN ECC Pin Count aL ATP 8 GB DDR3L 1600 AW24P7228BLKOS 204 pin Samsung 8 GB DDR3L 1600 XW1628E8GSP9 AV Yes 1 204 Sams
22. I19 Trap Response Immediace Select Screen Select Item Enter Select 1 Change Opt IF1 General Help IF2 Previous Values F3 Optimized Defaults IF4 Save 5 Exit 5 Exit Figure 2 33 CSM16 Parameters This item allows users to set display mode for Option ROM MIC 3396 User Manual 46 Parameters This option controls if Boot option filter UEFI and Legacy CSM will be launched Launch PXE OpROM poli Do not launch Launch Storage OpROM Legacy only Launch Video OpROM po Legacy only Other PCI device ROM UEFI OpROM Select Screen Select Item Enter Select Change Opt IF1 General Help F2 Previous Values 3 Optimized Defaults IF4 Save 5 Exit 5 Exit Figure 2 34 CSM Parameters This option controls if CSM will be launched 2 3 5 PXE Boot Setting Enter into Boot setting and choose CSM parameters m Launch PXE OpROM policy Enabled Controls the execution Boot option filter UEFI and Legacy Jof UEFI and Legacy PXE OpROM Launch Storage OpROM Legacy only Launch Video OpROM po Legacy only Other PCI device RO lect Screen Enter Select 1 Change Opt 1 Fi General Help IF2 Previous Values 1 Optimized Defaults F4 Save 5 Exit 1 5 Exit Figure 2 35 Launch OpROM pol
23. K 15 1 18W 49 JP VGAOUT SEL PH 3 1 2 00mm 1 2 Front Panel Default 2 3 Rear IO 9 MIC 3396 User Manual 1 4 3 Switch Settings Note wm represents the key Table 1 8 SW1 1 PCI Bridge Master Drone Mode Default Master Mode Drone Mode Table 1 9 5 1 2 DRONE_PCISRT _SW Default Drone Mode w o J1 RST Default Drone Mode w J1 RST MIC 3396 User Manual 10 Table 1 10 SW2 Front COM amp RTM 1 2 ports selection for BMC SIO UART Front COM for BMC Default RTM COM1 for SIO COM1 RTM COM2 for SIO COM2 Front COM SIO COM1 RTM for BMC RTM COM2 for SIO COM2 Front COM for SIO COM2 RTM SIO COM1 RTM for BMC 1 4 4 RIO 3316 C1E DIP Switch Setting Table 1 11 SW3 amp SW4 for Internal COM1 Default RS232 RS422 RS485 11 MIC 3396 User Manual Table 1 12 SW5 amp SW6 for COM2 SWS Default RS232 1 4 3 4 5 6 RS422 RS485 11 31 1011 These switches are only available for the RIO 3316 C1E model MIC 3396 User Manual 12 1 5 Connector Definitions Table 1 14 lists the function of each connector and Figure 1 3 and 1 4 illustrate each connector location Table 1 13 MIC 3396 connector descriptions Number Function SATA1 SATA HDD daughter board CFAST1 CFAST Socket J15 XMC SODIMM1 SODIMM socket J1 J2 P
24. RMCP IPMI over LAN IOL uses RMCP as messaging protocol as defined in the IPMI spec ifications RMCP messages consist of the basic IPMI message with some RMCP specific overhead and use the UDP protocol for data transmission UDP in turn uses the IP protocol for data transport so the network stack needs to support the IP and UDP protocols along with RMCP was added in the v2 0 specification It s an enhanced protocol for trans ferring IPMI messages and other types of payloads e g serial data MIC 3396 User Manual 56 3 4 3 5 3 5 1 Command Line Interface The Advantech IPMI core supports besides the IPMI defined interfaces a command line interface to grant easy and fast human readable system information This can be used for debugging and error recovery as well as showing information about the board and firmware status The command line interface CLI is implemented on UART 0 and accepts high level commands as well as IPMI messages in Serial Ter minal Mode as specified in IPMI 1 5 The CLI uses a baud rate of 115200 8 data bits 1 stop bit and no parity Table 3 2 Standard CLI Commands Command Description Any value between this brackets will be interpreted as IPMI message lt Enter gt Confirm Input lt Up gt Step through history bios_hist Show BIOS POST code history debug Switch to serial debug console q or x to exit help Print command ove
25. Steps The MIC 3396 supports 2 5 SATA hard disk drive The SATA HDD daughter board is assembled on the MIC 3396 but the SATA HDD brackets are not assembled on the MIC 3396 The brackets and screws are packed as accessories in the package Fol lowing steps illustrate the installation of the SATA HDD Figure 1 4 Complete assembly of MIC 3396 15 MIC 3396 User Manual 1 Align the HDD bracket on the side of HDD and fasten 4pcs M2 5 screw on the on the bracket Figure 1 5 Fasten screws on the SATA HDD bracket 2 Put the SATA HDD with bracket on the post and introduce SATA HDD into SATA connector Figure 1 6 Introduce SATA HDD into SATA connector MIC 3396 User Manual 16 1 8 Battery Replacement 1 9 The battery model number is BR2032 a 3V 195 mAH battery Replacement batteries may be purchased from Advantech When ordering the battery please contact your local sales office to check availability 1750199011 BATTERY 3V 195 mAH BR2032 Software Support Windows 7 Windows 8 Windows 2008 Enterprise R2 SP1 VxWorks 6 8 6 9 and RHEL 6 4 have been fully tested on the MIC 3396 Please contact your local sales representative for details on support for other operating systems 17 MIC 3396 User Manual MIC 3396 User Manual 18 AMI BIOS Setup This chapter describes how to configure the AMI BIOS 21 Introduction The AMI BIOS has been customized and integrated into many industrial and embed ded motherboar
26. The BMC is not accessible to any service while acti vation stage BIOS upgrade Like the FPGA component the BIOS component requires a payload reboot or power cycle in order to perform the activation stage The component follows the HPM 1 standard 67 MIC 3396 User Manual 3 10 Board Information The BMC provides IPMI defined Field Replaceable Unit FRU information about the CPCI board and the connected extension modules The MIC 3396 FRU data include general board information s such as product name HW version or serial number A total of 2 non volatile storage space is reserved for the FRU data The boards IPMI FRU information can be made accessible via all BMC interfaces and the infor mation can be retrieved at any time 3 10 1 Board Information Table 3 15 Board Info Area Field description Board information Format version 0x01 Board area length calculated Language code 0x19 English Manufacturer date time based on manufacturing date Board manufacturer type length 0xC9 Board manufacturer Advantech Board product name type length 0xC8 Board product name MIC 3396 Board serial number type length Board serial number 10 characters written during manufacturing Board part number type length 0xC8 Board part number MIC 3396 FRU file ID type length FRU file ID frudata xml Additional custom Mfg Info fields unused C1h No more
27. The SuperlO used by MIC 3396 includes the function of Hardware Monitor which monitors the critical hardware parameters for the system level The Hardware Moni tor NCT7904 is attached to the BMC to monitor CPU temperature and core voltage information when BMC is available 1 2 20 Super I O The MIC 3396 Super I O device provides the following legacy PC devices E Serial port COM1 and are connected to the rear I O module or front panel via multiplexer in the FPGA W The PS2 keyboard mouse is routed to the rear I O module 1 2 21 RTC and Battery The RTC module keeps the date and time On the MIC 3396 model the RTC circuitry is connected to battery sources CR2032M1S8 LF 3V 210mAH 1 2 22 The MIC 3396 uses the Intelligent Platform Management Interface IPMI to monitor the health of an entire system LPC 1768 microcontroller provides BMC functional ity to interface between system management software and platform hardware The MIC 3396 implements fully compliant IPMI 2 0 functionality and conforms to the PICMG 2 9 R1 0 specification The IPMI firmware is based on proven technology from Advantech Full IPMI details are covered in Chapter 3 1 3 Functional Block Diagram CPU must be BGA type to support DDR3 On board 1600 I mu XMC PMC DDR3 SO UDIMM LI Up to 8GB I E PICMG 2 16 I 210 an 2 PICMG 2 16 LAN
28. UDIO_GND TBD LOUT GND 21 GND INC NC GND DDI2_DVIPWR AUDIO_GND GND 22 GND NC GND NC NC GND 23 GND INC NC GND NC NC GND 24 GND J4_GPIO1 NC GND VBAT NC GND 25 GND 4 2 NC GND NC GND Note NC No Connection z Active Low eo 75 MIC 3396 User Manual 5 J5 Connector Table 5 45 CompactPCI port Pin F A B C D E Z 1 GND MDIAO RTM MDIAO GND RTM MDIA1 RTM_MDIA1 GND 2 GND MDIA2 RTM MDIA2 GND RTM_MDIA3 MDIA3 GND 3 GND MDIBO RTM MDIBO GND RTM MDIB1 MDIB1 GND 4 GND MDIB2 RTM MDIB2 GND RTM MDIB3 MDIB3 GND 5 GND NC GND DDI1 DVIPWR NC NC GND 6 GND DDI1_AUX GND 22 USB11 PWR 05 10 PWR GND 7 GND DDI1 AUX GND USBD11 USBD10 GND 8 GND DDI1_PAIRO GND MSDAT USBD11 USBD10 GND 9 GND DDI1_PAIRO GND MSCLK GND GND GND 10 GND DDI1_PAIR1 GND PS2PWR USB12_PWR GND 11 GND DDI1_PAIR1 GND KBDAT USBD12 2 GND 12 GND DDI1_PAIR2 GND KBCLK USBD12 VGA_PWR GND 13 GND DDI1_PAIR2 GND DDI1_HPD GND VGA VSYNC GND 14 DDI1_PAIR3 GND USB13 PWR VGA_HSYNC GND 15 GND DDI1_PAIR3 GND 2 16A LIN100 USBD13 VGA RED GND RTMA LINK10 RTMB LINK10 2 16 16 GND 008 0 ACT USBD13 VGA GREEN GND RTMA LINK10 RTMB_LINK10 2 16 LINK10 17 GND 0 00
29. Update Aborted 0 02 0 02 Recovery Finished 0 02 0 0 BIOS Update Successful 0x03 0x00 Update Timeout 0x03 0x04 Update Aborted 0x03 0x02 Flash 0 Boot Failed 00 0x03 0x29 Flash 1 Boot Failed 0x03 0x31 MIC 3396 User Manual 60 3 8 OEM IPMI Commands To provide custom board specific functionality the BMC supports additional com mands that are not covered by the PICMG or IPMI specification Advantech management solutions support extended OEM IPMI command sets based on the IPMI defined OEM Group Network Function NetFn Codes 2Eh 2Fh The first three data bytes of IPMI requests and responses under the OEM Group Net work Function explicitly identify the OEM vendor that specifies the command func tionality To be more precise the vendor IANA Enterprise Number for the defining body occupies the first three data bytes in a request and the first three data bytes fol lowing the completion code position in a response Advantech s IANA Enterprise Number used for OEM commands is 002839h The BMC supports all Advantech IPMI OEM commands listed in below table Table 3 8 OEM command list Command NetFn CMD Store Configuration Settings 2Eh 40h Read Configuration Settings 2Eh 41h Read Port 80 BIOS POST Code 2Eh 80h Reload NVRAM defaults 2Eh 81h Read MAC Address 2Eh E2h Load Default Configuration 2Eh F2h 61 MIC 3396 User Manual 3 8 1 Store Configuration Command T
30. User Manual MIC 3396 60 CompactPCI 4th Generation Intel Core 13 15 17 Processor Blade with ECC support AD ANTECH Enabling an Intelligent Planet Copyright The documentation and the software included with this product are copyrighted 2015 by Advantech Co Ltd All rights are reserved Advantech Co Ltd reserves the right to make improvements in the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reliable How ever Advantech Co Ltd assumes no responsibility for its use nor for any infringe ments of the rights of third parties which may result from its use Acknowledgements All other product names or trademarks are properties of their respective owners Product Warranty 2 years Advantech warrants to you the original purchaser that each of its products will be free from defects in materials and workmanship for two years from the date of pur chase This warranty does not apply to any products which have been repaired or altered by persons other than repair personnel authorized by Advantech or which have been subject to misuse abuse accident or improper installation Advantech assumes no liability under the terms of this warranty as a consequence of such events Bec
31. WATCHDOG Watchdog 2 Discrete IPMI BMC Watchdog sensor 1 FW_PROGRESS System Firmware IPMI FW Progress sensor Progress Discrete 2 VERSION CHANGE Version Change IPMI Version Change sensor Discrete Processor HOT status and SEM 56 Voltage regulator HOT Status 4 THERM_TRIP OEM Discrete CPU Thermal Trip 5 BAT_3_0 VOL Voltage Threshold Battery voltage 6 SB 3 3 VOL Voltage Threshold Standby Power voltage 3 3V 7 SB 5 0 VOL Voltage Threshold Standby Power voltage 5V 8 PAY 3 3 VOL Voltage Threshold Payload Power voltage 3 3V 9 PAY 5 0 VOL Voltage Threshold Payload Power voltage 5V 10 PAY 12 VOL Voltage Threshold Payload Power voltage 12V 11 PCH 1 05 VOL Voltage Threshold PCH supply voltage 12 PCH 1 5 VOL Voltage Threshold PCH supply voltage 13 PCH 1 0 VOL Voltage Threshold PCH supply voltage 14 CPU CORE VOL Voltage Threshold CPU Core voltage 15 AUX 3 3 VOL Voltage Threshold Auxiliary voltage 3 3V MIC 3396 User Manual 58 3 7 2 3 7 3 Table 3 3 BMC sensor list 16 HP 3 3 VOL Voltage Threshold 3 3V on the CPCI Connector 17 HP 12 0 VOL Voltage Threshold 12V 0 on the CPCI Connector 18 HP 5 0 VOL Voltage Threshold 5 0V on the CPCI Connector 19 CPU TMP Temperature Threshold CPU temperature PECI 20 INTEGRITY OEM OEM Integrity sensor Threshold based sensors Sensor event thresholds are classifies as Non critical NC Critical CR
32. anel miniUSB 03h RTM 1 04h RTM 2 CLI BMC UART Baudrate 006 9600 01h 14400 02h 19200 03h 38400 04h 57600 05h 115200 IRQ PROC hot IRQ enabled 00h disabled 01h enabled 65 MIC 3396 User Manual 3 8 3 Read Port 80 Command This command is used to read out the actual POST code of the UEFI BIOS Table 3 11 Read Port 80 command BIOS POST code byte data field Request Data 1 3 Advantech IANA ID 392800h Response Data 1 Completion Code 2 4 Advantech IANA ID 392800h 5 POST code 3 8 4 Read MAC Address Command This command can be used to get the Product MAC addresses Table 3 12 Read MAC Address Command byte data field Request Data 1 3 Advantech IANA ID 392800h MAC address number LAN1 01h LAN2 02h LAN3 03h 04h LAN5 05h BMC NCSI MAC Completion Code D5h not supported in present state 2 4 Advantech IANA ID 392800h 5 MAC address Response 1 3 8 5 Reload BMC Default Configuration Command This command is reloads the Product specific settings Table 3 13 Reload BMC Default Configuration Command byte data field Request Data 1 3 Advantech IANA ID 392800h Response Data 1 Completion Code 2 4 Advantech IANA ID 392800h MIC 3396 User Manual 66 3 9 3 9 1 3 9 2 3 9 3 3 9 4 HPM 1 Upgrade Support The PICMG HPM 1 Hardware Platform Management specification defines a stan dard wa
33. anual ii Declaration of Conformity CE This product has passed the CE test for environmental specifications when shielded cables are used for external wiring We recommend the use of shielded cables FCC Class A Note This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Opera tion of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense FM This equipment has passed the FM certification According to the National Fire Pro tection Association work sites are classified into different classes divisions and groups based on hazard considerations This equipment is compliant with the speci fications of Class Division 2 Groups A and D indoor hazards Technical Support and Assistance 1 Visit the Advantech website at http support advantech com where you can find the latest information about the product 2 Contact your distributor sales representative or Advantech s customer service center
34. ause of Advantech s high quality control standards and rigorous testing most of our customers never need to use our repair service If an Advantech product is defec tive it will be repaired or replaced at no charge during the warranty period For out of warranty repairs you will be billed according to the cost of replacement materials service time and freight Please consult your dealer for more details If you think you have a defective product follow these steps 1 Collect all the information about the problem encountered For example CPU speed Advantech products used other hardware and software used etc Note anything abnormal and list any onscreen messages you get when the problem OCCUIS 2 Call your dealer and describe the problem Please have your manual product and any helpful information readily available 3 If your product is diagnosed as defective obtain an RMA return merchandize authorization number from your dealer This allows us to process your return more quickly 4 Carefully pack the defective product a fully completed Repair and Replacement Order Card and a photocopy proof of purchase date such as your sales receipt in a shippable container A product returned without proof of the purchase date is not eligible for warranty service 5 Write the RMA number visibly on the outside of the package and ship it prepaid to your dealer Part No 2002339600 Edition 1 Printed in Taiwan July 2015 MIC 3396 User M
35. creen v Select Item Enter Select Change Opt 1 1 General Help F2 Prev ous Values 1 3 Optimized Defaults F4 Save amp Exit ESC Exit Figure 2 23 VT d 39 MIC 3396 User Manual VT d This item allows users to enable or disable VT d Graphics Configuration a a Figure 2 24 Graphics Configuration GTT Size This item allows users to select the GTT Size Aperture Size This item allows users to select the Aperture Size DVMT Pre Allocated This item allows users to select DVMT 5 0 Pre Allocated fixed Graphics mem ory size used by the internal graphics device DVMT Total Gfx Mem This item allows users to select DVMT5 0 total Graphic memory size used by the internal graphic device MIC 3396 User Manual 40 LCD Control Figure 2 25 LCD Control Primary IGFX Boot Dis This item allows users to select the Video Device which will be activated during POST This has no effect if external graphics present Secondary boot display selection will appear based on your selection LCD Panel Type This item allows users to select panel resolution Panel Scaling This item allows users to enable or disable panel scaling 41 MIC 3396 User Manual 19 deuo dn8S 5018 INY m NB PCle Configuration NB PCIe Configuration Configure PEGO 50 D1 Fo PEGO Not Pr
36. dStep CPU C States This item allows users to enable or disable CPU C states 27 MIC 3396 User Manual c Jaydeyud dmes m Intel TXT LT support Enables or Disables Intel TXT LT support 2 3 2 5 SATA Configuration SATA Mode Selection SATA Controller Speed Serial ATA Port 0 Software Preserve Port 0 External SATA Serial ATA Port 2 Software Preserve Port 2 External SATA Seriai ATA Port 3 Software Preserve Port 3 External SATA Serial ATA Port 4 Software Preserve Software Preserve Port 0 External SATA Serial ATA Port 2 Software Preserve Port 2 External SATA Serial ATA Port 3 Software Preserve Port 3 External SATA Serial ATA Port 4 Software Preserve Port 4 External SATA Serial ATA Port S Software Preserve SATA Controller AHCI Default Empty Unknown Enabied Disabled Empty Unknown Enabled Disabled SGB NANDrive NOT SUPPORTED Enabled Disabled Empty Unknown 8 028 Enabled Disabled Empty Unknown Enabled Disabled 208 NANDrive NOT SUPPORTED Enabled Disabled Empty Unknown Enabled Disabled Empty Unknown Enabled 8 028 Enable or disable SATA Device 71 t 5 KI ot 1 gt lt Select Screen v Select Item Enter Select Change Opt 1 General Help F2 Prev ous Values F3 Optimized Defaults F4 Save 5 Exit SC Exit
37. ds for decades This section describes the BIOS which has been specifically adapted for the MIC 3396 With the AMI UEFI BIOS Setup Utility you can modify BIOS settings and control the special features of the MIC 3396 The Setup program uses a number of menus for making changes and turning the special fea tures on or off This chapter describes the basic navigation of the MIC 3396 setup screens System Language English Figure 2 1 Setup program initial screen MIC 3396 User Manual 20 2 2 2 3 BIOS Setup The MIC 3396 Series system has AMI BIOS built in with a CMOS SETUP utility that allows users to configure required settings or to activate certain system features The CMOS SETUP saves the configuration in the CMOS RAM of the motherboard When the power is turned off the battery on the board supplies the necessary power to preserve the CMOS RAM But there is a CMOS backup mechanism in the MIC 3396 to protect the user s personal settings which allows final BIOS setup informa tion to be retained always except for date time and user password which are reset when CMOS battery is removed or password only erased using the clear jumper When the power is turned on press the Del button during the BIOS POST Power On Self Test to access the CMOS SETUP screen Control Keys lt 1 gt lt gt lt gt lt gt Move to select item lt gt gt lt lt gt Select Screen 791 Select ite
38. e WD 120GB Gen Ill WD1200BEVS 00USTO HDD Intel SSD 520 Series 240GB Gen Ill SSDSC2CW240A3 SSD Plextor 32G Gen PX 32G5Le 72 SSD Plextor 1TB Gen PX 1TG7Se 72 SSD Serial ports One 45 1 port RS 232 interface is provided on the front panel Two COM ports are routed to a rear I O module via the J5 connector 1 2 10 USB Port Two USB 3 0 and one USB 2 0 compliant ports with fuse protection are provided All ports are routed to front panel connectors on the MIC 3396 One USB 3 0 and four USB 2 0 are routed to the rear I O module via the J3 and J5 connector 1 2 11 LEDs Four LEDs are provided on the front panel as follows One blue LED indicates hot swap activity The blue color indicates that the board may be safely removed from the system MIC 3396 User Manual 4 One yellow color LED indicates HDD activity WB One green color LED provides power status When the LED is green it means power is provided to the board m One green color LED indicates Master or Drone mode The green color stands for Master mode When the LED is off the board is in Drone mode W green color LED indicates BMC status When the LED is green it means BMC is active 1 2 12 Watchdog Timer An onboard watchdog timer provides system reset capabilities via software control The programmable time interval is from 1 to 255 seconds 1 2 13 Optional Rear I O Modules The RIO 3316 is the optional RTM also known as
39. eadings from CPU Table 3 6 Temperature Sensor List Sensor Name Nominal LNR LCR LNC UNC UCR UNR CPU TMP 40 15 10 5 80 90 105 3 7 5 Integrity Sensor The Integrity Sensor is an OEM sensor according to the SDR Sensor Data Record definitions in the IPMI specification It is used to observe the system while operating In case of the occurrence of predefined conditions or actions it throws events Con sequently there are generated entries in the System Event Log So the user is able to trace back detailed possible errors or executed actions of the firmware The event message contains three bytes of event data Byte 1 is the IPMI header which is a fixed value Byte 2 satisfies the logical component while byte 3 stands for its action The table below shows the supported event code structure gen erated by the integrity sensors on the MIC 3396 Table 3 7 Integrity Sensor event data table Component Action Subcomponent Result Byte 1 2 3 BMC FW Update Successful 0x01 0x00 Update Timeout 0 01 0x04 Update Aborted 0 01 0 02 Activation Failed 0 01 0 21 Manual Rollback Initiated 0 01 0 15 Automatic Rollback Initiated 0 01 0 1 Rollback Finished 0 01 0x0E Rollback Failed 0x01 0x09 Graceful Shutdown Timeout 0 01 0 74 FPGA Update Successful 0 02 0x00 Update Timeout 0 02 0 04
40. ed Enabled Azal a will be unconditionally Enabled jAuto Azalia will be gt lt Select Screen Iv Select Item 185 Select Change Opt 1 General Help F2 Prev ous Values 3 Optimized Defaults 4 Save 5 Exit 5 Exit Figure 2 30 PCH Azalia Configuration Control Detection of the Azalia device MIC 3396 User Manual 44 Boot Configuration Prompt Timeout mLock Stat Figure 2 31 Boot Configuration Quiet Boot If this option is set to Disabled the BIOS display normal POST messages If enabled an OEM Logo is shown instead of POST messages Bootup NumLock State By ON the keyboard NumLock state will stay ON after booting By OFF the keyboard NumLock state will stay OFF after booting Boot Option Priority Boot Option 1 Boot Option 2 Show the boot device choices Hard Drive BBS Priorities Select the main hard disk device type to be a boot hard drive 45 MIC 3396 User Manual 2 19429 dmes 5018 INY Sets the system boot order 1 gt lt Select Screen Select Item Enter Select 1 Change Opt IF1 General Help F2 Prev ous Values 1 3 Optimized Defaults IF4 Save 5 Exit 5 Exit Figure 2 32 Hard Drive BBS Priorities CSM16 Parameters CSM16 Parameters Set display mode for lOption ROM C5M16 Module Version IN
41. eed and VLAN Specifies the port used for the Enabled selected boot protocol I gt lt Select Screen Iv Select Item Enter Select Change Opt 1 General Help F2 Prev ous Values 3 Optimized Defaults 4 Save 5 Exit 5 Figure 2 19 Link Speed Link Speed Specifies the port speed used for the selected boot protocol m Wake On LAN This item allows users to enable the server to be powered on 37 MIC 3396 User Manual 2 3 2 12 Intel 1210 Gigabit Network Connection Advanced Configure Boot PORT CONFIGURATION MENU Protocol Wake on LAN Link Speed and VLAN 1 Blink LEDs 0 PORT CONFIGURATION INFORMATION UEFI Driver Intel R PRO 1000 Adapter PBA 000300 000 Chip Type Intel 1210 PCI Device ID 1533 Select Screen Bus Device Function 00 Select Item Link Status Disconnected Enter Select MAC Address 00 00 29 0 8 Change Opt Virtual MAC Address 00 D0 C9 B0 AC A8 IF1 General Help IF2 Previous Values 1 3 Optimized Defaults F4 Save 5 Exit Figure 2 20 NIC Configuration Settings NIC Configuration Configure Boot Protocol Wake on LAN Link Speed and VLAN Specifies the port speed used for the Enabled selected boot protocol I gt lt Select Screen Iv Select Item Enter Select Change Opt IF1
42. ered in Chapter 2 provides a user interface for features such as enabling or disabling the ports and setting the port address Many serial devices implement the RS 232 standard in different ways If you have prob lems with a serial device be sure to check pin assignments on Table 1 11 for the con nectors The IRQ and address range for these ports are fixed However if you wish to disable the port or change these parameters later you can do this in the system BIOS setup 1 5 3 Ethernet Configuration The MIC 3396 is equipped with two high performances PCI Express based network interface controllers which provide fully compliant IEEE802 3 10 100 1000Base TX Ethernet interfaces QM87 built in PHY chip which also provides 10 100 1000Base TX Ethernet interface Users can choose the LAN1 and LAN2 either the front panel RJ 45 connectors or the LAN3 and LAN4 on the rear I O module Furthermore the MIC 3396 supports the PICMG 2 16 Packet Switching Backplane Specification via the J3 connector 1 5 4 SATA Daughter Board Connector SATA1 and Extension Module The MIC 3396 provides one SATA interface via SATA1 connector for either a daugh ter board for SATA HDD It is optional as onboard HDD Two SATA interfaces are connected to RTM for extra SATA HDDs request 1 5 5 System Rest and BMC Reset Button The MIC 3396 provides a system reset button located on the front panel The system reset button resets all payload and application related circu
43. esent Geni Gen3 1 PEGI Not Present Gen X Auto C7 Allowed Disabied Enable PEG Enabled gt lt Select Screen Iv Select Item Enter Select Change Opt IF1 General Help IF2 Previous Values 1 3 Optimized Defaults F4 Save 5 Exit ESC Exit Figure 2 26 NB PCle Configuration PEGO Gen x Select PEGO speed Enabled PEG This item allows users to enable or disable PEG Memory Configuration Memory Information Maximum Memory Frequency Selections in Memory RC Version 1 Mhz Memory Frequency 1 Total Memory MB DDR3 Memory Voltage L I 0090 MB DDR3 01102 Present CAS Latency tCL j Minimum delay cime CAS to RAS tRCDm i gt lt Select Screen Row Precharge tR v Select Item Active Precher jEnter Select Profile 1 Not Supported Change Opt Profile 2 Not Supported 1 General Help F2 Previous Values F3 Optimized Defaults Support Enabled 1 4 Save 5 Exit Incerleave Suppor Exit MIC 3396 User Manual 42 Memory RC Version Memory Frequency Total Memory Memory Voltage 2 CAS Latency tCL Minimum delay time CAS to RAS tRCDm Row Precharge tR Active to Prechar XMP Profile 1 XMP Profile 2 Memory Frequency Limi ECC Support Enh Interleave Suppor 1 3 0 0 1600 Mhz 8192 MB DDR3 1 35v 6292 MB DDR3 Noc Present 11 22 11 28 Not Supported Not Suppo
44. esponding I O interface signals Table C 1 LPC I O registers address LPC Address Type Description Ox 80 Port 80 Display 0x440 R FPGA Minor Version 0x442 R UART_MUX Switch 0x443 0x444 RW Watchdog Register 0x445 R FPGA Major Version 0x446 R BIOS Flash Control 0x447 R Geographical Address GA 0x448 R HW Revision 0x44A RW GPIO Control 0x44C R FPGA ID 0x44F RW Scratch Register 0 4 0 0x4A7 RW 2 Interface amp Control 0 4 0 0x4B8 RW SPI Interface amp Control OxCA2 RW KCS Interface MIC 3396 User Manual 84 Appendix D Glossary ACPI BMC CF CPU DMA DRAM ECC EDMA EEPROM EMC ESD FCBGA FSB HDD HW IC IMCH LED LPC LV MAC OS PCB PCle PHY RASUM RIO RS 232 RTC RTM SBC SDRAM SFP SPD SW ULV XTM MIC 3396 User Manual Advanced Configuration and Power Interface Baseboard Management Controller CompactFlash Central Processing Unit CompactPCl Direct Memory Access Dynamic Random Access Memory Error Checking and Correction Enhanced DMA Electrically Erasable Programmable Read Only Memory Electro Magnetic Compatibility Electro Static Discharge Flip Chip BGA Front Side Bus Hard Disk Drive HardWare Input Output Integrated Circuit Integrated Memory Controller Hub Light Emitting Diode Low Pin Count Low Voltage Medium Access Control Operating System Printed Wiring Board Peripheral Comp
45. etting Failure Retries 00h Power failure retries 01h UNR Temperature retries Setting FPGA 00h COM1 UART multiplexer 01h COM2 UART multiplexer 02h BMC UART multiplexer 5 Setting USB Reserved Setting Clock Ekeying Reserved Setting PCle Reserved Setting CLI 00h BMC UART Baudrate Setting IRQ 00h PROC hot IRQ enabled Completion Code C7h request data length invalid Response 1 C9h parameter out of range CBh requested data not present D5h not supported in present state 2 4 Advantech IANA ID 392800h Setting MIC 3396 User Manual 64 Table 3 10 Read Configuration Settings byte data field Setting Port Bytes Bios Switch Bios Flash 00h Active BIOS flash Failure Retries Power failure retries 00h FEh number of failure retries FFh infinite retries Failure Retries UNR Temperature retries 00h FEh number of failure retries FFh infinite retries Misc Power budgeting 00h Dynamic Power Budgeting disabled 01h Dynamic Power Budgeting enabled FPGA COM1 UART multiplexer 00h not connected 01h Serial over LAN 02h Frontpanel RJ45 03h Frontpanel miniUSB 04h RTM 1 05h RTM 2 FFh automatic mode FPGA COM2 UART multiplexer 00h not connected 01h Frontpanel RJ45 02h Frontpanel miniUSB 03h RTM 1 04h RTM 2 FPGA BMC UART multiplexer 0061 not connected 01h Frontpanel RJ45 02h Frontp
46. ews the SATA HDD bracket 16 Figure 1 6 Introduce SATA HDD into SATA connector 16 Battery 17 Software Support 17 AMI BIOS Setup 19 InitroOdUuCtlom En tt ar E t E ad pde elas 20 Figure 2 1 Setup program initial 20 BIOS Setup acce cene e a a ea Ea 21 21 2 9 1 a 22 Figure 2 2 Main setup screen 22 2 3 2 Advanced BIOS Features 23 Figure 2 3 Advanced BIOS features setup screen 23 Figure 2 4 PCI Setting eene 24 Figure 2 5 ACPI Settlfigs uuu uuu eene 25 Figure 2 6 Trusted Computing 26 Figure 2 7 CPU configuration 2 27 Figure 2 8 SATA configuration 2222 00 28 Figure 2 9 RAID mode rod tre pe ttr etd secet 31 Figure 2 10USB configuration 31 Figure 2 11Super IO Configurations 32 Figure 2 12Serial Port 0 1 Configurations 33 Figure 2 13PC Health Status 34 Figure 2 14Console redirection Settings
47. for technical support if you need additional assistance Please have the following information ready before you call Product name and serial number Description of your peripheral attachments Description of your software operating system version application software etc A complete description of the problem The exact wording of any error messages iii MIC 3396 User Manual Warnings Cautions and Notes Warning Warnings indicate conditions which if not observed can cause personal injury Caution Cautions are included to help you avoid damaging hardware or losing data e g A There is a danger of a new battery exploding if it is incorrectly installed Do not attempt to recharge force open or heat the battery Replace the battery only with the same or equivalent type recommended by the man ufacturer Discard used batteries according to the manufacturer s instructions Note Notes provide optional additional information E Document Feedback To assist us in making improvements to this manual we would welcome comments and constructive criticism Please send all such in writing to support advan tech com Packing List Before setting up the system check that the items listed below are included and in good condition If any item is not accord with the table please contact your dealer immediately MIC 3396 all in one single board computer CPU heatsink and PCH heatsink included x1 Dau
48. ghter board for SATA HDD x1 Assembled HDD tray and screws package x 1 Solder side cover Assembled x1 RJ45 to 089 cable x1 Warranty certificate document x1 Safety Warnings CE FCC class A If any of these items are missing or damaged contact your distributor or sales repre sentative immediately MIC 3396 User Manual iv Safety Instructions 10 11 12 13 14 15 16 Read these safety instructions carefully Keep this User Manual for later reference Disconnect this equipment from any AC outlet before cleaning Use a damp cloth Do not use liquid or spray detergents for cleaning For plug in equipment the power outlet socket must be located near the equip ment and must be easily accessible Keep this equipment away from humidity Put this equipment on a reliable surface during installation Dropping it or letting it fall may cause damage The openings on the enclosure are for air convection Protect the equipment from overheating DO NOT COVER THE OPENINGS Make sure the voltage of the power source is correct before connecting the equipment to the power outlet Position the power cord so that people cannot step on it Do not place anything over the power cord All cautions and warnings on the equipment should be noted If the equipment is not used for a long time disconnect it from the power source to avoid damage by transient overvoltage Never pour any liquid into an opening This may cause fi
49. his command is used to set Product specific settings The first two bytes Setting Port are used to select the item that should be changed the last byte contains the new setting value Table 3 9 Store Configuration Settings Command byte data field Request Data 1 3 Advantech IANA ID 392800h Setting 02h reserved 03h Bios 04h Lan controller 055 Failure retries 066 Misc 07h RTC 08h FPGA 09h USB Clock Ekeying OBh PCle 0Ch BMC CLI ODh IRQ OEh Carrier Manager Setting Bios 00h Switch Bios Flash Setting Lan controller Reserved Setting Failure Retries 00h Power failure retries 01h UNR Temperature retries Setting Misc Reserved Setting RTC Reserved Setting FPGA 00h COM1 UART multiplexer 5 01h COM2 UART multiplexer 02h BMC UART multiplexer Setting USB Reserved Setting Clock Ekeying Reserved Setting PCle Reserved Setting CLI 00h BMC UART Baudrate Setting IRQ 00h PROC hot IRQ enabled Setting Carrier Manager Reserved MIC 3396 User Manual 62 Table 3 9 Store Configuration Settings Command byte data field Setting value that is written to the selected Setting Port Bytes Bios Switch Bios Flash 00h Switch Bios Flashes Lan controller Lan interface selection Reserved Failure Retries Power failure retries 00h FEh number of failure retries FFh infinite retries Failure Retries UNR Temperature retr
50. icy Choose Legacy only UEFI only for launch OpROM policy 47 MIC 3396 User Manual Save and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Options Save Changes Discard Changes Restore Defaults Save as User Defaults Restore User Defaults Boot Override UEFI Built in EFI Shell SATA 55 8GB NANDrive Exit system setup after saving the changes gt lt Select Screen Select Item Enter Select Change Opt F1 General Help F2 Previous Values F3 Optimized Defaults 4 Save 5 Exit Exit Figure 2 36 Save and Exit Choose boot option priority The Network device BBS Priorities will be shown after enabled PXE OpROM Boot Configuration Bootup NumLock State Quiet Boot Disabled Boot Option Priorities Boot Option 1 SATA 55 NANDr Boot Option 2 IBA GE Slot 00 8 1410 Boot Option 3 UEFI Built in EFI Li 242 m Network Device BBS Priorities gt 5 16 Parameters CSM parameters MIC 3396 User Manual 48 Number of seconds to wait for setup activation key 165535 means indefinite waiting I Select Screen Select Item jEnter Select 1 Change Opt IF1 General Help F2 Prev ous Values F3 Optimized Defaults 1 4 Save 5 Exit Boot Option 2 Boot Option 3 Boot Opticn 4 Boot Option 5 Boot Configuration Setup Prompt Timeou
51. ies 00h FEh number of failure retries FFh infinite retries RTC synchronization Reserved FPGA COM1 UART multiplexer 00h not connected 01h Serial over LAN 02h Frontpanel RJ45 03h RTM 1 04h RTM 2 OBh BMC_MUX FPGA COM2 UART multiplexer 6 00h not connected 01h Serial over LAN 02h Frontpanel RJ45 03h RTM 1 04h RTM 2 OBh BMC FPGA BMC UART multiplexer 00h not connected 01h Frontpanel RJ45 02h RTM 1 03h RTM 2 OBh 5101 or 2 CLI BMC UART Baudrate 006 9600 01h 14400 02 19200 03h 38400 04h 57600 05h 115200 IRQ PROC hot IRQ enabled 00h disabled 01h enabled Response Data Completion Code C7h request data length invalid 1 C9h parameter out of range CBh requested data not present D5h not supported in present state 2 4 Advantech IANA ID 392800h 5 Setting 63 MIC 3396 User Manual 3 8 2 Read Configuration Command This command is used to read Product specific settings The first two bytes Setting Port are used to select the item that should be read out the answer contains the set ting value Table 3 10 Read Configuration Settings Command byte data field Request Data 1 3 Advantech IANA ID 392800h Setting 00h 02h reserved 03h Bios 04h Lan controller 05h Failure retries 06h Misc 4 07h 08h FPGA 09h USB OBh PCle OCh BMC CLI IRQ 5 Port Setting Bios 00h Active Bios Flash S
52. igure 2 34CSM Pararneters 47 29 5 PXE BOOT SENN 47 Figure 2 35Launch PXE OpROM 47 Figure 2 36Save and 48 Figure 2 37 Boot option priority 49 Figure 2 38Save changes and 50 Figure 2 39Start page of PXE Server 50 viii Chapter 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 Appendix A A 1 2 9 0 Security Setting etaed ne 51 Figure 2 40Security Setting 51 2 37 Save amp iit eerie d 52 Figure 2 415 and Exit 52 for the MIC 3396 53 54 Terms and Definitions 54 IPM Interfaces 55 Figure 3 1 Management part block diagram 55 3 31 MEI co 55 OMIT 56 3 3 3 LAN Qu a as iei rta aba tye 56 Table 3 1 Supported Network Protocols 56 Command Line Interface 57 Table 3 2 Standard Commands 57 BMC Watchdog TT 57 3 5 1 BIOS Boot Watchdog seen 57 System Event Log SEL idest ecd Ha ied
53. ion Enable or Disable Serial Port COM Settings 10 2 8 IRQ 3 Settings gt lt Select Screen Iv Select Item Enter Select Change Opt IF1 General Help F2 Previous Values 3 Optimized Defaults F4 Save amp Exit 5 Exit Figure 2 12 Serial Port 0 1 Configurations 33 MIC 3396 User Manual 2 3 2 8 H W Monitor Configuration System temperature CPU temperature and voltage status can be checked in PC Health Status PuTTY Pe Health Status System temperaturel System temperature2 System temperatures VCORE 12V Memory 5V Select Screen Select Item Enter Select Change Opt IF1 General Help 1 2 Previous Values 1 3 Optimized Defaults 1 4 Save 5 Exit 5 Exit Figure 2 13 PC Health Status 2 3 2 9 Serial Port Console Redirection Setting Console Redirection Settings COMI Console Redirection Disabled Console Redirection Settings COM2 Pci Bus0 DevO FuncO Disabled Console Redirection Port Is Disabled Serial Port for Out of Band Management Windows Emergency Management Services EMS Console Redirection IEnabled gt Console Redirection Settings Console Redirection Enable or Disable 1 Select Screen Select Item 185 Select Change Opt 1 1 General Help 1 2 Previous Values Optimized Defaults IF4 Save 5 Exit 5 Exit Figure 2 14 Console redirec
54. itry It does not reset the system management IPMI related circuitry A separate BMC reset button on the front panel is provided for the BMC and related hardware 1 6 Safety Precautions Follow these simple precautions to protect yourself from harm and the products from damage To avoid electric shock always disconnect the power from your CompactPCI chassis before you work on it Don t touch any components on the CPU board or other boards while the CompactPCI chassis is powered m Disconnect power before making any configuration changes The sudden rush of power as you connect a jumper or install a board may damage sensitive elec tronic components Always ground yourself to remove any static charge before you touch your CPU board Be particularly careful not to touch the chip connectors Modern integrated electronic devices especially CPUs and memory chips are extremely sensitive to static electric discharges and fields Keep the board in its antistatic packaging when it is not installed in the chassis and place it on a static dissipative mat when you are working with it Wear a grounding wrist strap for continuous protection MIC 3396 User Manual 14 1 7 Installation Steps The MIC 3396 contains electro statically sensitive devices Please discharge your clothing before touching the assembly Do not touch components or connector pins We recommend that you perform assembly at an anti static workbench 171 HDD Installation
55. m Enter Select lt gt Change Option lt F1 gt General help for Setup Sub Menu lt F2 gt Previous values lt F3 gt Optimized defaults lt F4 gt Save amp exit lt Esc gt Exit Entering Setup Turn on the computer and there should be a POST Power On Self Test screen that shows the BIOS supporting the CPU If there is no number assigned to the patch code please contact an Advantech application engineer to obtain an up to date patch code file This will ensure that the CPU s system status is valid After ensuring that you have a number assigned to the patch code press lt DEL gt and you will imme diately be allowed to enter Setup 21 MIC 3396 User Manual 2 3 4 Main Setup When you first enter the BIOS Setup Utility you will enter the Main setup screen You can always return to the Main setup screen by selecting the Main tab Two main setup options are described in this section The main BIOS setup screen is shown below System Language English Figure 2 2 Main setup screen The main BIOS setup menu screen has two main frames The left frame displays all the options that can be configured Grayed out options cannot be configured while options in blue can The right frame displays the key legend Above the key legend is an area reserved for a text message When an option is selected in the left frame it is highlighted in white Often a text message will accompany it System Time System Date Use
56. ndicates BMC status heart beat to indicate BMC active Hot Swap Blue Indicates the board is ready to be hot swapped BMC Green Indicates BMC status 79 MIC 3396 User Manual MIC 3396 User Manual 80 Programming the Watchdog Timer This appendix describes how to program the watchdog timer Watchdog Timer Programming Procedure To program the watchdog timer you must execute a program that writes value to O port address 443 444 hex for Enable Disable This output value represents time interval The value range is from 01 hex to FF hex and the related time interval is 1 to 255 seconds Data Time Interval 01 1 sec 02 2 sec 03 3 sec 04 4 sec 3F 63 sec After data entry your program must refresh the watchdog timer by rewriting the I O port 443 and 443 hex while simultaneously setting it When you want to disable the watchdog timer your program should read I O port 444 hex The following example shows how you might program the watchdog timer in BASIC 10 REM Watchdog timer example program 20 OUT amp H443 data REM Start and restart the watchdog 30 GOSUB 1000 REM Your application task 1 40 OUT amp H443 data REM Reset the timer 50 GOSUB 2000 REM Your application task 2 60 OUT amp H443 data REM Reset the timer 70 X INP amp H444 REM Disable the watchdog timer 80 END 1000 REM Subroutine 1 your application task 1070 RETURN 2000 REM Subroutine 2 your application task 2090 RETURN
57. nect the power from your PC chassis before you work on it Don t touch any components on the CPU card or other cards while the PC is on Disconnect power before making any configuration changes The sudden rush of power as you connect a jumper or install a card may damage sensitive elec tronic components We Appreciate Your Input Please let us know of any aspect of this product including the manual which could use improvement or correction We appreciate your valuable input in helping make our products better MIC 3396 User Manual vi Contents Chapter 1 N 1 3 1 4 1 5 Hardware Contfiguration 1 2 D 2 1 2 1 CompactPCI Bus Interface 2 1 22 CPU e ite sedg 2 12 37 PIOGCOSSOF se lie e hh e Ren AR RR REP 3 Table 1 1 Processor Type 3 1 24 BIOS iiie ee iem al a ides 3 1 25 3 1 2 6 Memo 3 Table 1 2 Memory 6 3 1 27 Ethernet deed 4 12 6 Storage Interface uu uuu a 4 1 2 9 Serial ports t e e 4 1210 OSB POM t
58. of 12 bus clocked at a frequency of 100 kHz using IPMI compliant messaging 55 MIC 3396 User Manual 3 3 2 3 3 3 3 3 3 1 3 3 3 2 3 3 3 3 KCS The BMC s KCS interface is implemented according to the IPMI 2 0 specification Keyboard Controller Style KCS interfacing describes a legacy system interface based around a bidirectional set of a status command and data register This kind of interface has been adopted as system interface in IPMI and provides the benefits of m Higher bandwidth than IC RS232 based interfaces Robustness m Auto discovery options LAN The BMC FW supports a LAN interface providing NSCI according to the IPMI 2 0 specification The BMC is attached to an Intel 1210 network controller LAN2 that is supporting a sideband interface 5 The table below lists the supported network protocols Table 3 1 Supported Network Protocols Mnemonic Protocol ARP Address Resolution Protocol ICMP Internet Control Message Protocol IP Internet Protocol UDP User Datagram Protocol RMCP RMCP Remote Management Control Protocol ARP Both standard ARP requests and reply ARP opcodes 0x01 and 0x02 are supported to propagate the BMC s IP address in the system Gratious ARP is supported for dynamic address changes or failover scenarios Other ARP opcodes are not sup ported and will be ignored ICMP ICMP is supported to allow network pings to from the BMC RMCP
59. onent Interconnect Peripheral Component Interconnect Express Physical layer Interface Reliability Availability Serviceability Usability and Manageability Rear Input Output An Interface specified by Electronic Industries Alliance Real Time Clock Rear Transition Module Single Board Computer Synchronous DRAM Small Form factor Pluggable Serial Presence Detect SoftWare Ultra Low Voltage Extension Module 86 87 MIC 3396 User Manual AD ANTECH Enabling an Intelligent Planet www advantech com Please verify specifications before quoting This guide is intended for reference purposes only All product specifications are subject to change without notice No part of this publication may be reproduced in any form or by any means electronic photocopying recording or otherwise without prior written permis sion of the publisher All brand and product names are trademarks or registered trademarks of their respective companies Advantech Co Ltd 2015
60. pecification The BMC solution is based on the Advantech IPMI Core 602 and it is designed around a combination of a NXP LPC1768 ARM Cortex M3 based 32 bit microcontroller and a Lattice MachXO2 series FPGA The microcontroller is running FreeRTOS as basic OS with Advantech s own hard ware abstraction layer HAL and IPMI stack The BMC s key features and functions are listed below Advantech Integrity Sensor Based on Advantech Core designed for CPCI WB 2 0 Specification compliant B IPMI over LAN Serial over LAN KCS interface for direct communication between Operating System BMC Full BMC watchdog support as defines in IPMI specification System Event Log SEL m HPM 1 for in field updates supporting Bootloader Firmware FPGA BIOS Automatic UART muxing between all serial interfaces for easy console access Additional sensors for hardware monitoring 3 2 Terms and Definitions Term Definition AMC Advanced Mezzanine Card API Application Programming Interface ATCA Advanced Telecommunications Computing Architecture BIOS Basic Input Output System BMC Baseboard Management Controller CLI Command Line Interface CompactPCl CPU Central Processing Unit DDR3 Double Data Rate 3 DIMM Dual In line Memory Module DIP Dual In line Package EEPROM Electrically Erasable Programmable Read Only Memory EMAC Ethernet Media Access Con
61. performance to help equipment manufacturers optimally balance processing capabilities within power and space con straints The advanced smart cache of Core i3 i5 i7 dynamically allocates the shared L2 cache across cores and optimizes use of memory subsystem bandwidth to accelerate out of order execution A prediction mechanism reduces the time in flight instructions have to wait for data The new pre fetch algorithms move data from sys tem memory into fast L2 cache in advance of execution The Core 13 15 17 combines the benefits of two high performance execution cores with intelligent power management features to deliver significantly greater perfor mance per watt over previous Intel processors The two execution cores share a high performance power optimized 5GT s DMI bus to access the same system memory To save power address and data buffers are turned off when there is no activity MIC 3396 maximizes I O throughput with PCI Express PCle technology An on board 8 GB of 1600 MHz DDR3L memory is provided with a combination of SO DIMM up to max 8 GB of 1600 MHz DDR3L as option It supports a fast Serial ATA interface to an on board hard drive 1 2 Specifications 1 2 1 CompactPCI Bus Interface The MIC 3396 is compliant with PICMG 2 0 Rev 3 0 It supports a 64 bit 66 MHz or 33MHz PCI bus for up to 7 CompactPCI slots at 3 3 V or 5 V VIO MIC 3396 is hot swap compliant PICMG 2 1 and conforms to the CompactPCI Packe
62. re or electrical shock Never open the equipment For safety reasons the equipment should be opened only by qualified service personnel If one of the following situations arises get the equipment checked by service personnel m The power cord or plug is damaged Liquid has penetrated into the equipment B The equipment has been exposed to moisture m The equipment does not work well or you cannot get it to work according to the user s manual m The equipment has been dropped and damaged B The equipment has obvious signs of breakage DO NOT LEAVE THIS EQUIPMENT IN AN ENVIRONMENT WHERE THE STORAGE TEMPERATURE MAY GO BELOW 20 C 4 F OR ABOVE 60 C 140 F THIS COULD DAMAGE THE EQUIPMENT THE EQUIPMENT SHOULD BE IN A CONTROLLED ENVIRONMENT CAUTION DANGER OF EXPLOSION IF BATTERY IS INCORRECTLY REPLACED REPLACE ONLY WITH THE SAME OR EQUIVALENT TYPE RECOMMENDED BY THE MANUFACTURER DISCARD USED BATTERIES ACCORDING TO THE MANUFACTURER S INSTRUCTIONS The sound pressure level at the operator s position according to IEC 704 1 1982 is no more than 70 dB A DISCLAIMER This set of instructions is given according to IEC 704 1 Advantech disclaims all responsibility for the accuracy of any statements contained herein MIC 3396 User Manual Safety Precaution Static Electricity Follow these simple precautions to protect yourself from harm and the products from damage B To avoid electrical shock always discon
63. rear I O module for the MIC 3396 It offers a wide variety of I O features such as two or four RJ45 LAN ports two COM ports two DVI ports one USB3 0 one USB2 0 port one P S2 port RIO 3316 D1E can carrier an on board 2 5 HDD which support SATA Gen 11 and provide two GbE LAN ports one PS 2 two USB2 0 and one display port Rear I O modules are avail able with following different I O options Table 1 3 RIO 3316 Configuration Rear Panel On board Header Socket Connector RTM Model SAS Number LAN COM DVI I DVI D 5 2 USB USB Mini USB SATA Conn 2 0 3 0 SAS interface RIO 3316 C1E 4 1 1 1 1 1 1 2 2 J3 J4 J5 RIO 3316 D1E 2 1 2 2 2 J3 J4 J5 1 2 14 Mechanical and Environmental Specifications Operating temperature 0 55 C 32 122 F Note The operating temperature range of the MIC 3396 depends on the P installed processor and the airflow through the chassis l Storage Temperature 40 85 C 40 185 F Humidity 95 40 C non condensing Humidity Non operating 95 60 C non condensing Vibration 5 100Hz 2Grms without on board 2 5 SATA HDD Shock 10G without on board 2 5 SATA HDD Bump 25G 6ms Altitude 15000ft above sea level at 55 C Board size 233 35 x 160 mm 6U size 1 slot 4 TE wide Weight 0 8 kg 1 76 Ib 1 2 15 Compact Mechanical Design The MIC 3396 has a specially de
64. rimary CompactPCI bus J3 J4 J5 Rear I O transition HDD Hot Swap LED blue BMC ics LAN2 USB3 0 s co m DD yellow x 8 VGA USB2 0 XMC PMC Platform Reset Power LED BMC LED green Master Drone Mode LED Figure 1 2 MIC 3396 Front Panel Ports Indicators and Buttons USB2 0 PS 2 DVI D LAN3 Power LED green 2 16 USB3 0 COM DVI I HDD LED Figure 1 3 RIO 3316 C1E Front Panel Ports and Indicators 1 5 1 USB Connectors The MIC 3396 provides up to six Universal Serial Bus USB 2 0 and three Universal Serial Bus USB 3 0 channels Two USB 3 0 and one USB 2 0 ports are on the front panel of MIC 3396 Four other USB 2 0 and one other USB 3 0 channels are routed to rear I O via the J3 J5 connector One USB2 0 and one USB3 0 ports are on the front panel of RIO 3316 C1E the other three are on board connectors The USB interface provides complete plug and play hot attach detach for up to 127 external devices The MIC 3396 USB interface complies with USB specification R2 0 and R3 0 and is fuse protected 5 V 1 1 A 13 MIC 3396 User Manual 1 5 2 Serial Ports The MIC 3396 provides one serial port and the RIO 3316 provides two serial ports The serial port is available as RS 232 interfaces via RJ 45 connectors on the front panel of MIC 3396 An RJ 45 to DB 9 adaptor cable is provided in the MIC 3396 accessories to facilitate connectivity to external console or modem devices The BIOS Advanced Setup program cov
65. rted Auto Enabled Enabled Enabled Enable or disable Memory Scrambler support 54 5 Select Screen Select Item jEnter Select 1 Change Opt 1 General Help F2 Prev ous Values F3 Optimized Defaults F4 Save 5 Exit v ESC Exit Figure 2 27 Memory Configuration 2 3 3 2 South Bridge Configuration PCI Express Configuration Settings Allow enable or disable PCI Express Root Port Intel PCH RC Version Intel PCH SKU Name Intel PCH Rev ID USB Configuration Configuration Controller LAN2 to Front Rear SB CRID Enabled Front Disabled IPCI Express Configuration settings gt lt Select Screen Iv Select Item Enter Select 1 Change Opt IF1 General Help 1 2 Previous Values F3 Optimized Defaults 4 Save 5 Exit ESC Exit Figure 2 28 PCI Express Configuration 43 MIC 3396 User Manual USB Configuration Mode of operation of controller 1 gt lt Select Screen 79 Select Item Enter Select Change Opt IF1 General Help F2 Prev ous Values IF3 Optimized Defaults IF4 Save 5 Exit 5 Exit Figure 2 29 USB Configuration Mode of operation of xHCI controller allows user to enable or disable USB port Azalia Configuration Control Detection of the Azalia device Disabled Azalia will Ibe unconditionally disabl
66. rview info Print FW and product information memory pres Show memory DIMM presence status ncsi status Print detailed NC SI status ncsi table Print NC SI link status table reboot Reboot spidump Dump all FPGA SPI registers switch debug Switch On Off messaging interfaces in Debug output BMC Watchdog The BMC provides an IPMI 2 0 compliant BMC Watchdog to monitor the OS during runtime or to observe the BIOS boot progress BIOS Boot Watchdog The IPMI compliant BMC Watchdog is used to monitor BIOS boot progress and initi ate a rollback when a BIOS is found to be corrupt It is set to a predefined value of 180 seconds and automatically starts when the pay load power for the x86 subsystem is being turned on The time out action is set to hardware reset with the timer use indicating BIOS use If the watchdog timer times out with this configuration it triggers a BIOS chip failover followed by a system reset and restart of the watchdog timer The mechanism runs in an endless loop and logs timeouts failovers to the SEL through the Integrity Sensor BIOS does not touch the watchdog timer except for two situations 1 Itdisables the watchdog right before jumping into the boot loader so it doesn t trigger after BIOS execution It could alternatively reconfigure the watchdog to act as boot watchdog i e change timeout action 2 Ittemporarily disables the watchdog once the setup menu is manually activated for debugging purpose
67. s 57 MIC 3396 User Manual 3 6 3 7 3 7 1 System Event Log SEL A 64 kB System Event Log SEL is implemented in the BMC It stores all events that are either generated by the BMC or that are passed to it from the system interface The events are physically stored in the external attached SPI flash All received events are passed to the default event receiver which typically is the CMM in PICMG2 9 environments if one is present regardless of being stored in the SEL This means that local events will show up in the local BMC s SEL as well as in the CMMs shelf wide SEL unless there is no filter enabled on the CMM side The size of 64 kB is sufficient to hold exactly 4096 entries of 16 bytes each Once the SEL is full it will not store new entries so that existing data is not overwrit ten The SBC or System managers can query the SEL usage at any time and it is their responsibility to issue a SEL Clear from time to time to avoid local SEL over flow Sensors All important voltages and temperatures are connected to the BMC management system in different ways Moreover the BMC also registers some logical sensors listed below m Watchdog sensor FW Progress sensor B Version change sensor Advantech OEM Sensor Integrity Sensor Sensor List The following table specifies all sensors provided by the BMC Table 3 3 BMC sensor list Sensor Type No Sensor ID Event Reading Type Description 0 BMC
68. signed CPU heatsink to enable fanless operation However forced air cooling in the chassis is needed for operational stability and reli ability 5 MIC 3396 User Manual 1 2 16 Bridge The MIC 3396 uses a Pericom PI7C9X130D universal bridge as a gateway to an intelligent subsystem When configured as a system controller the bridge acts as a standard transparent PCI Express to PCI PCI X Bridge As a peripheral controller it allows the local MIC 3396 processor to configure and control the onboard local sub system independently from the CompactPCI bus host processor The MIC 3396 local PCI subsystem is presented to the CompactPCI bus host as a single CompactPCI device When the MIC 3396 is in drone mode the Pericom PI7C9X130D is electri cally isolated from the CompactPCI bus MIC 3396 receives power from the backplane and supports rear I O The Pericom PI7C9X130D PCI Bridge offers the following features PCI Interface Full compliance with the PCI Local Bus Specification Revision 3 0 Supports 3 3V PCI signaling with 5V I O tolerance Supports transparent mode operations Supports forward bridging 64 bit 66MHz asynchronous operation Provides two level arbitration support for 7 PCI Bus masters 16 bit address decode for VGA Usable in CompactPCI system slot Please consult the Pericom PI7C9X130D data book for details 1 2 17 I O Connectivity For MIC 3396 the front panel I O is provided by two RJ 45
69. ssed 25 MIC 3396 User Manual c 19 deuo dn8S 5018 INY 2 3 2 3 Trusted Computing Configuration Enables or Disables 18105 support for security device 0 5 Iwill not show Security Current Status Information Device TCG EFI SUPPORT TURNED OFF protocol and INTIA janterfece will not be available Select Screen v Select Item Enter Select Change Opt IF1 General Help 1 2 Previous Values 3 Optimized Defaults 4 Save 5 Exit l I I I I Exit Figure 2 6 Trusted Computing Trusted Computing settings wm Enable Disable Trusted Computing Enables or Disables BIOS support for security device OS will not show Security Device TCG EFI protocol and INT1A interface will not be available 2 3 2 4 CPU Configuration CPU Configuration Enabled for Windows XP land Linux OS optimized Intel R Core TM 15 4400 CPU 8 2 70GHz for Hyper Ihreading CPU Signature 306c3 Technology and Microcode Patch 8 Disabled for other OS Max CPU Speed 2700 MHz OS not optimized for Min CPU Speed 800 MHz Hyper Threading CPU Speed 2700 MHz Iechnology When Processor Cores 2 Disabled only one Intel HT Technology Supported Intel Technology Supported gt lt Select Screen Intel SMX Technology Supported v Select Item 64 bit Supported jEnter Select EIST Technology Supported 1 Change Opt CPU C3 state Supported 1 1 General Help
70. ster Drone Mode 10 Table 1 9 SW1 2 DRONE_PCISRT SW 10 Table 1 10 SW2 Front amp RTM 1 60 2 ports selection for BMC SIO UART sss 11 1 4 4 RIO 3316 C1E DIP Switch Setting 11 Table 1 11 SW3 amp SW4 for Internal COMI 11 Table 1 12 SW5 amp SW6 2 12 Connector 13 Table 1 13 3396 connector descriptions 13 Figure 1 2 MIC 3396 Front Panel Ports Indicators and Buttons 13 Figure 1 3 RIO 3316 C1E Front Panel Ports and Indicators 13 1 5 1 USB tes sad 13 5 2 14 5 3 Ethernet Configuration 14 5 4 SATA Daughter Board Connector SATA1 and Extension Module 14 vii MIC 3396 User Manual NO Chapter 2 MIC 3396 User Manual 1 5 5 System Rest and BMC Reset 14 Safety 14 Installation aaa ee 15 1 7 1 HDD Installation 15 Figure 1 4 Complete assembly of MIC 3396 15 Figure 1 5 Fasten scr
71. t Built in EFI Sheil IF1 General Help 55 828 NANDrive F2 Previous Values Figure 2 38 Save changes and reset Start PXE Server xf COMI2 PaTTY poration GUID Figure 2 39 Start page of PXE Server MIC 3396 User Manual 50 2 3 6 Security Setting t Administrator Password User Password Figure 2 40 Security Setting Administrator Password Select this option and press ENTER to access the sub menu and then type in the password Set the Administrator password User Password Select this option and press ENTER to access the sub menu and then type in the password Set the User Password 51 MIC 3396 User Manual c 19 deuo dmes 5018 INY 2 3 Save amp Exit Option Exit system setup after Discard Changes and Exit saving the changes Save Changes and Reset 1 Discard Changes and Reset Save Options Save Changes Discard Changes Restore Defaults Save as User Defaults gt lt Select Screen Restore User Defauits Iv Select Item Enter Select Boot Override Change Opt UEFI Built in EFI Shell 1 1 General Help SATA SS 8GB NANDr ve 1 2 Previous Values F3 Optimized Defaults F4 Save amp Exit Figure 2 41 Save and Exit Save Changes and Exit When users have completed system configuration select this option to save changes exit BIOS setup menu and reboot the computer to take effect all s
72. t Bootup NumLock State Quiet Boot Boot Option Priorit Boot Option 2 Boot Option 3 Hard Drive BBS Priori Network Device 885 Priorities CSM16 Parameters CSM parameters IBA GE Slot IBA GE Slot IBA GE Slot IBA GE Slot v1410 v1410 v1410 v1410 Sets the system boot jorder 1 l Select Screen v Select Item Enter Select 1 Change Opt 1 1 General Help IF2 Previous Values 1 3 Optimized Defaults F4 Save amp Exit Sets the system boot lect Item Select Change Opt IF1 General Help IF2 Previous Values 1 Optimized Defaults F4 Save 5 Exit 5 Note 2 Hard Drive BBS Priorities Figure 2 37 Boot option priority 49 MIC 3396 User Manual Save Changes and Reset again Copyright 2012 American Megatrends Inc Aptio Setup Utility C JExit system setup after Discard Changes and Exit saving the changes Save Changes and Reset Discard Changes and Reset Save Options Save Changes Discard Changes IF3 Optimized Defaults F4 Save amp Exit Restore Defaults Exit Save as User Defaults gt lt Select Screen Restore User Defaults v Select Item Enter Select Boot Override Change Op
73. t Switching Backplane specification PICMG 2 16 as well as the CompactPCI System Manage ment Specification PICMG 2 9 The board can be configured as a system master or a drone board In drone mode it only draws power from the CompactPCI backplane and is not active on the Compact PCI bus However PICMG 2 16 is still fully supported in this mode 1 2 2 CPU The MIC 3396 supports Intel 4th generation Core i3 i5 i7 Haswell processor fam ily with clock frequencies up to 2 7 GHz and a Direct Media Interface DMI up to 5GT s Intel 4th generation Core i3 i5 i7 processors are validated with Intel mobile 87 chipset This chipset provides greater flexibility by deploying the latest virtual ization multi threading and I OAT acceleration techniques as well as remote asset management capabilities and improved storage speed and reliability Supported processors are listed in the table below The Intel 4th generation Core i3 i5 i7 processors support up to two cores four threads at 2 7 GHz 2 4 GHz and MB 6MB cache MIC 3396 User Manual 2 1 2 3 Processor 1 2 4 1 2 5 1 2 6 Table 1 1 Processor Type Intel CPU CPU CPU Required Model architec Cores Threads Freq Cache DMI TDP Package airflow Number ture i3 4100E Pee 2 4 2 4 GHz 5GT s 37W FCBGA 30 15 4402 2 2 4 1 6 GHz 3MB 5 25W 30 15 4400 2 2 4 2 7G
74. this option to change the system time and date Highlight System Time or System Date using the Arrow keys Enter new values through the keyboard Press the Tab key or the Arrow keys to move between fields The date must be entered in MM DD YY format The time is entered in HH MM SS format MIC 3396 User Manual 22 2 3 2 Advanced BIOS Features Setup Select the Advanced tab from the MIC 3396 setup screen to enter the Advanced BIOS Setup screen You can select any of the items in the left frame of the screen such as CPU Configuration to go to the sub menu for that item You can display an Advanced BIOS Setup option by highlighting it using the lt Arrow gt keys All Advanced BIOS Setup options are described in this section The Advanced BIOS Setup screen is shown below The sub menus are described on the following pages PCI PCI X and PCI ACPI Settings Express Settings Trusted Computing 1 Configuration SATA Configuration USB Configuration Super IO Configuration H W Monitor Serial Port Console Redirection Network Stack gt lt Select Screen Intel R Ethernet Connection 1217 00 D v Select Item Intel R I210 Gigabit Network Connection gt Enter Select Intel R 1210 Gigabit Network Connection Change Opt Intel R 1210 Gigabit Network Connection IF1 General Help Intel R 1210 Gigabit Network Connection IF2 Previous Values 3 Optimized Defaults 4 Save 5 Exit ESC Exit Figure 2 3
75. tion Settings MIC 3396 User Manual 34 Console Redirection Settings This item allows users to enable or disable console redirection or Microsoft Win dows Emergency Management Services EMS Advanced Emulation ANSI Console Redirection Settings Extended ASCII char VI100 ASCII char Iset VI1004 Extends Bits per second 125200 100 to support color Data Bits 8 function keys etc Parity Nonej IVI UIF8 Uses 8 Stop Bits 1 jencoding to map Unicode Flow Control None chars onto 1 or more VI UIF8 Combo Key Sup Enabled Recorder Mode Disabled Select Screen Resolucion 100x31 Disabled Select Item Legacy OS Redirection 80x24 Enter Select Putty KeyPad VT100 1 Change Opt 1 1 General Help 1 2 Previous Values 1 3 Optimized Defaults IF4 Save 5 Exit ESC Exit Figure 2 15 Out of Band Mgmt Port Out of Band Mgmt Port Select the port for Microsoft Windows Emergency Management Services EMS to allow for remote management of a Windows Server OS Microsoft Windows Terminal Type Emergency Management Bits per second 1115200 Services EMS allows Fiow Control None Ifor remote management Data Bits 6 lof a Windows Server OS Parity None through serial port Stop Bits 1 Select Screen Select Item jEnter Select 1 Change Opt IF1 General Help IF2 Previous Values 3 Optimized Defaults IF4 Save 5 Exit 5 Exit Figure 2 16 Terminal Type Terminal T
76. troller FLASH Flash memory FPGA Field Programmable Gate Array FRU Field Replaceable Unit GbE Gigabit Ethernet GPIO General Purpose Input Output HPM 1 Hardware Platform Management 1 MIC 3396 User Manual 54 3 3 3 3 1 2 Inter Integrated Circuit IPMB Intelligent Platform Management Bus BMC Intelligent Platform Management Controller IPMI Intelligent Platform Management Interface KCS Keyboard Controller Style LPC Low Pin Count Bus NCSI Network Controller Sideband Interface NIC Network Interface Controller PLD Programmable Logic Device RMCP Remote Management Communication Protocol RS232 Recommended Standard 232 SAS Serial Attached Storage SATA Serial Advanced Technology Attachment SDR Sensor Data Record Sensor Data Repository SEL System Event Log SPI Serial Peripheral Interface UART Universal Asynchronus Receiver Transmitter USB Universal Serial Bus XMC XMC mezzanine card Vita 42 0 IPMI Interfaces The MIC 3396 provides three main IPMI messaging interfaces to connect to the BMC There the IPMB 0 for main messaging interface between CPCI boards the LAN side band interface NCSI and the on board payload interface to x86 KCS 1210 LAN Ctrl loL NCSI KCS LPC IPMB O 120 Figure 3 1 Management part block diagram IPMB 0 IPMB 0 is the I2 C based PICMG 2 9 R1 0 defined main messaging interface between CPCI boards It consists
77. ung Transcend 4 GB IDDR3L 1600 A63873 0011 Yes 204 pin Samsung 3 MIC 3396 User Manual 1 2 7 1 2 8 1 2 9 Table 1 2 Memory Type 8 GB DDR3L 1600 42 Yes 204 Samsung 0 0 AQD SD3L8GE16 8 GB DDR3L 1600 I Yes 204 pin Samsung Note 4GB on board memory is optional Please inform your local sales Ethernet The MIC 3396 uses one Intel 1210 AT and one Intel 1217 LM LAN chips to provide 10 100 1000Base T Ethernet connectivity LAN1 amp LAN2 and three Intel 1210 LAN chips to provide 10 100 1000Base T Ethernet connectivity LAN3 LANS via rear I O one 10 100 1000Base T Ethernet be switched from LAN2 to rear I O LAN6 Optional settings for the source of each individual Gigabit Ethernet port can be selected in the BIOS menu These are mutually exclusive and can be any one of Frontl O RJ 45 W Rear I O Rear Transition Module PICMG 2 16 Storage Interface The MIC 3396 supports six SATA Ill interfaces One SATA III interface is routed to an onboard 2 5 SATA hard disk drive one is routed to support an on board flash optional one is CFast connector two are routed to the rear I O module via the J3 connector Currently Advantech s compatible RIO modules support the SATA II and SATA III devices The following table shows a list of SATA HDD and SSD that have been tested on the MIC 3396 Brand Size Speed Vendor PN Typ
78. y of updating BMC firmware components over IPMI based interfaces Among the mechanism itself it defines a common update file format and IPMI based commands for the update procedure HPM 1 is the de facto standard for firmware updates in PICMG based environments Advanced features in HPM 1 address redundancy mechanisms supporting both automatic and manual rollbacks to properly support the high availability require ments in platforms like CompactPCl The Advantech IPMI Core G02 supports HPM 1 updates over any of its IPMI inter faces See the following tables for a list of HPM 1 components implemented on the CPCI blade and their respective description Table 3 14 Supported HPM 1 components Component Number BMC Firmware 0 BMC Boot loader 1 FPGA 2 BIOS 3 Bootloader update The bootloader HPM 1 upgrade is written to the LPC1768 flash directly Means there is no recovery existing for the bootloader image It is not recommended to upgrade the bootloader in the field Firmware upgrade The firmware upgrade component follows the HPM 1 specification and the upgrade and activation stage can be performed while the payload is running In case of an update the BMC is not accessible to any service while activation stage FPGA upgrade The firmware upgrade component follows the HPM 1 specification The upgrade can be performed while the payload is running For the activation stage a payload part reboot and power off is required
79. ype VT UTF8 is the preferred terminal type for out of band management The next best choice is VT100 and then VT100 35 MIC 3396 User Manual 2 3 2 10 Network Stack Enable Disable UEFI network stack Select Screen Select Item Enter Select Change Opt IF1 General Help IF2 Previous Values 1 3 Optimized Defaults F4 Save 5 Exit 5 Exit Enable Di sable UEFI Ipv4 PXE Support Enabled Inetwork stack Ipv6 PXE Support Enabled Select Screen Select Item jEnter Select Change Opt IF1 General Help IF2 Previous Values 1 3 Optimized Defaults F4 Save 5 Exit 5 Exit Figure 2 17 Network Stack B Network Stack This item allows users to enable or disable network stack MIC 3396 User Manual 36 2 3 2 11 Intel Ethernet Connection 217 1 3 Setup Advanced Configure Boot PORT CONFIGURATION MENU Protocol Wake on LAN Link Speed and VLAN I Blink LEDs 0 PORT CONFIGURATION INFORMATION UEFI Driver Intel R PRO 1000 5 5 19 Adapter PBA FFFFFF OFF Chip Type Intel PCH LPT PCI Device ID 153A gt lt Select Screen Bus Device function 19 0 Iv Select Item Link Status Disconnected Select MAC Address 00 D0 C9 80 AC A7 Change Opt IF1 General Help F2 Prev ous Values F3 Optimized Defaults F4 Save 5 Exit Figure 2 18 NIC Configuration Settings B NIC Configuration Configure Boot Protocol Wake on LAN Link Sp
80. ys tem configuration parameters 1 Select Exit Saving Changes from the Exit menu and press lt Enter gt The fol lowing message appears Save Configuration Changes and Exit Now Ok Cancel 2 Select Ok or cancel m Discard Changes and Exit Select this option to quit Setup without making any permanent changes to the system configuration 1 Select Exit Discarding Changes from the Exit menu and press lt Enter gt The following message appears Discard Changes and Exit Setup Now Ok Cancel 2 Select Ok to discard changes and exit Discard Changes Select Discard Changes from the Exit menu and press lt Enter gt Restore Default The BIOS automatically configures all setup items to optimal settings when users select this option Defaults are designed for maximum system perfor mance but may not work best for all computer applications In particular do not use the Defaults if the user s computer is experiencing system configuration problems Select Restore Defaults from the Exit menu and press lt Enter gt Save as User Default Save the all current settings as a user default Restore User Default Restore all settings to user default values m Boot Override Show the boot device types on the system MIC 3396 User Manual 52 IPMI for the MIC 3396 This chapter describes IPMI con figuration for the MIC 3396 3 1 Introduction The MIC 3396 fully supports the major IPMI 2 0 interface and the PICMG 2 9 R1 0 s

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