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System and a method for obtaining a mask programmable device

1. ERE E GN13PD BUFINTTL 2170113 NI3PD GNIIPD BUFINTTL PINIINIIPD GNIOPD BUFINTTL PIN10 NIOPD GN9PD BUFINTTL N9PD GN8PD BUFINTTL GN7PD BUFINTTL PIN N7PD GN6PD BUFINTTL PIN6 N6PD GNSPD BUFINTTL PINS NS5PD GN4PD BUFINTTL PIN4 GN3PD BUFINTTL PIN3 N3PD GN2PD BUFINTTL PIN2 N2PD GZ1271 INVP 21301 71271 GZ1281 INVP Z1301 21281 GZ1291 INVP 21301 21291 GZ1301 INVP NIPD Z1301 GNIPD BUFINTTL PINI NIPD GZ1311 INVP 271401 21311 GZ1011 BO3N4 71381 71021 PIN21 GZ1021 NAND2 21235 71031 71021 9321321 DFFRNI 21112 21291 21311 2 GZ1001 BO3N4 Z1331 Z1021 PIN22 GZ951 AODW22 21331 Z1211 N3PD 71113 Z951 351404 7 173 GZ1331 GZ97 GZ1341 GZ1091 621101 GZIN GZ121 GZ1131 GZ 141 GZ1161 GZH71 GZ1351 GZI191 GZ1201 GZ1211 GZ1031 GNI4MX 0571361 021151 GNNI9MX GZ1371 GZ1071 GZ1081 0781 GZ1381 GZ1391 GZ1401 GZ1231 GNINPWR DFFRNI NANDI3 DFFRNI ANDIZ BO3N4 ORI2 BO3N4 BO3N4 BO3N4 BO3N4 BO3N4 DFFRNI INV2 AODW22 NAND3 NORI3 OAI2W22 DFFRNI BO3N4 AOI2W21 DFFRNI INV2 NORI3 AOI2W22 DFFRNI INVP ANDI2 POR 5 717 928 174 7972 21271 21391 21331
2. KEEN method MUX 4 not implemented method GASPDFFR GASPDFFR DFFRNI method GASPDFFS gt GASPDFFS DFFSNI method DFFRS gt GASPDFFRS DFFRNSN1 method SCANDFF gt SCANDFF expanded method SCANDFFR gt SCANDFFR expanded method SCANDFFS gt SCANDFFS expanded method SCANDFFRS gt SCANDFFRS expanded method SCANJKFF gt SCANJKFF expanded method SCANJKFFR gt SCANJKFFR expanded method SCANJKFFRS gt SCANJKFFRS expanded method SCANJKFFS gt SCANJKFFS expanded method BUF3STA GASPBUF3STA BFU3STA method BUFIOTTL GASPBUFIOTTL BUFIOTTL special cell to implement GASPDFFR method must be removed by the expert system and replaced by a DFF RN with inverter on RAZ cell GASPDFFR is record in D CK R out Q QN class seq put same area than DFFRNI used for synthesis area 6 fan in 1 1 1 delay 0 0 fan out factor 0 0 max fan out 8 function D CK R D CK R hilo order D CK R Q QN method GASPDFFR Q D CK R DFFR Q QN D CK R end record special cell to implement GASPDFFS method must be removed by the expert system and replace by a with inverter on SET c
3. ac 5 717 928 23 o C e end m1712 01 25 ath 351404 351404 25 5 717 928 Appendix A 2 the MPL File Matra Design Semiconductor Inc 1989 id 7 5 717 928 27 WITH PLDMethods PLD 22 1018 inputs 1 is clock 1 Pin In Feed Eqn PD Attributes Pos Fixed SR Eqn 25 RE Eqn 25 Eqn 26 MX PR Eqn 26 Netlist POR NPWR 1 INV PWR NPWR OR PWRRE PWR RE BUFINTTL IN PD 2 11 Pin In Feed Eqn PD Attributes Pos Fixed 12 Notice the Feed definition Feed is make equivalent to PD to override the default behavior of Abel To Gasp which in that case would lead to Feed In e g some assoicated name Netlist BUFINTTL In PD X GND input Pin In Feed Eqn PD Attributes Pos Fixed Netlist BUFINTTL In PD y registered outputs 14 23 Pin In Out Feed Feed_Pin Feed_Reg Attributes Neg Pos Default Com Reg Reg d Default Attributes Neg Pos Default Com Defualt Reg Reg 4 MX Default 0 0 Default is not mandatory for clarity reason SR Eqn 25 MX RE Eqn 25 AP Eqn 26 MX PR Eqn 26 MX Preset and Reset signals are redirectioned to Node 25 and 26 each p
4. Date Wed Oct 10 12 32 22 PDT1990 Device p22v10 Technology md Path ust desdisk2 design bill From Abel R eval abl To Hilo R eval cct ke EE ck sc koe ek ook ee KOR e PIN gt clk25 PIN2 gt db00 PIN3 gt db01 PIN 4 gt db02 PINS gt vsync PIN 6 gt PIN7 gt hweyc_ PINS gt ba02 PIN 9 gt rd_ 10 gt res_ PINII ate_ PIN 13 gt ba04 PIN 14 gt intenb PIN 15 gt csdone_ PIN 16 gt PIN 17 gt rdcntl PIN 18 gt rdstat_ PIN 19 gt vihld_ PIN 20 wi PIN 21 gt vien PIN 22 gt sien PIN 23 gt vidon dk KOR CCT CMOS PS 100 EVAL PINI PIN2 PIN3 PIN4 PINS PIN6 PIN7 PIN8 PIN9 PIN10 PIN13 PIN14 PIN15 PIN16 PIN17 PIN18 19 PIN20 PIN21 PIN22 23 BUFINTTL GN13PD PINI3 NI3PD
5. amp 04 amp cycntl_ assert done amp ba04 amp ate ba04 ba02 19 Ihwcyc hwcyc hwcyc enable sien amp ba04 amp 25_ enable vien thwcyc_ amp 04 amp TEST VECTORS CONTROL enable csdone tcsdone enable vi enable out 0 00000 000009 22 Uh 351404 5 717 928 22 21 en nm n OO lt ec TEST_VECTORS VERTICAL SYNC HOLD rd res gt vihld J vsync hwcyc ba02 25 clk a n o n on lt DONOR gt m tot n 2 gt a n f 5 QO 5 5 x lt 53 475 82 z s Qs ob e ES OB nnno gt g n 3 EAR Ss TEST VECTORS INTERUPTS 1 1 1 1 7 gt gt gt gt 1 1 1 1 res sccint vsync ate gt intenb X i THOS lt lt m ooo gt o z SONNAN Al Qovvv gt 2 4 351404 _
6. Z GEN END IF END RULE FORK_INV1_OUT gt 8 lt 15 IN I A OUT B C BEGIN IF B A INVI THEN Z INVI A B 7 END IF END 351404 48 5 717 928 93 94 RULE FORK_INV1_OUT_GEN lt 8 gt IS IN DAI OUT GENERIC OUT GEN BEGIN IF B INVI A C INVI A GEN THEN Z INVI A 8 Z 2 GEN END IF END RULE FORK IN OUT GEN lt 8 gt IS IN A OUT B GENERIC_OUT GEN BEGIN IF GEN INV1 A B INVI GEN THEN GEN INVI B A END IF END rule FIN_DFFRN1_CK_QNQ lt 11 gt is in D RN out 0 QN generic_out begin if Q QN DFFRNI D CK RN then FANIN FAN3 CK 0 DFFRNI D FANIN RN end if end rule FIN DFFRNI CK lt 11 gt is in D CK RN out generic out CK begin if Q DFFRNI D CK RN then 351404 26 5 717 928 95 FANIN FAN3 CK 0 DFFRNI D FANIN RN end if end rule FIN DFFRNI CK 11 is in D CK RN out QN generic out CK begin if G QN DFFRNI D RN then FANIN QN DFFRNI D FANIN RN end if end rule FIN DFFRNI RN lt 11 gt is in D CK RN out Q QN generic_ out RN begin if Q QN DFFRN1 D CK RN then FANIN
7. trdstat_ thweyc_ amp ba04 amp ba02 amp trd_ enable stat reg buffs trdentl hweyc_ amp ba04 amp ba02 amp trd_ enable ent reg buffs lintenb_ sien amp sccint_ vien amp vi enable int buff vi vsync tvihld_ Chweyc_ amp ba04 amp ba02 amp rd_ latch vysnc tvibld vsync vihld_ amp hwcyc_ amp ba04 amp 2 amp rd hold vi vidon db00 amp hweye_ amp 04 amp csdone amp ba02 amp rd vidon amp amp ba04 amp csdone_ amp ba02 amp rd enable vid tsien 14601 amp hwcyc_ amp ba04 amp csdone amp ba02 amp rd sien amp hwcyc_ amp ba04 amp csdone_ amp ba02 amp rd disable sccints lvien 19602 amp hwcyc amp ba04 amp Icsdone amp ba02 amp rd Ivien amp thweyc_ amp ba04 amp csdone_ amp ba02 amp rd_ disable vsync ints teyentl_ fhwcyc amp 1ba04 control done 351404 4 32 gt 11 13 1 d 11 1 1 1 gt gt gt enable on control reg read enable on control reg read enable on control reg read 0 1 1 1 1 1 gt 3 5 717 928 ate_ gt vidon sien vien x 1 1 1 0 0 x amp ba02 amp ba02 gt amp ba02 EG write read rd res c amp ba04 enable done when cycle valid enable outputs unless low
8. B FAN2 then D FAN6 A B D end if end rule F3F3 F6 GEN gt 4 lt is in out B C generic_out begin if C FAN3 B FAN3 A then FANG B end if end 351404 ne 73 5 717 928 101 102 rule F8 lt 4 gt is in DA out FAN generic out GEN begin if FAN FANS GEN then 2451 IDI A GEN D11 2451 FAN D11 2451 end if end rule F8_REM2 lt 4 gt is m out generic out begin if NA GEN FAN then NA FAN GEN end if end rule ID11 REM 14 is in out begin if FAN then FAN end if end rule F2 REM 14 i in out begin if FAN 351404 FAN NA GEN 1011 A NA FANS GEN 011 A IDII IDI NA FAN ID11 A A FAN2 457 5 717 928 103 104 then FAN A end if end rule REM lt 14 gt is in FAN begin if FAN FAN3 A then FAN A end if end rule REM lt 14 gt is in out FAN begin if FAN FAN6 then FAN end if end rule F8 lt 14 gt is in A out FAN begin if FAN FAN8 A then FAN A end if end rule NOFAN_REM lt 14 gt is m o
9. METHOD DFFRS IS IN D CLK SET RAZ OUT Q NQ ASK Q NQ D CLK SET RAZ END METHOD METHOD SCANDFFRS IS IN D CLK SET RAZ SCAN MODE OUT Q NQ ASK Q NQ D CLK SET RAZ SCAN MODE END METHOD METHOD DFFNRNS IS IN D CLK NSET NRAZ OUT Q NQ ASK Q NQ D CLK NSET NRAZ END METHOD METHOD TRIINV IS IN I CTRL OUT O ASK O CTRL I END METHOD METHOD TRI IS IN I CTRL OUT O ASK O CTRL I END METHOD METHOD TFF IS IN T CLK PE PIN OUT Q NQ ASK Q NQ T CLK PE PIN END METHOD METHOD JKFF IS IN J CLK OUT NQ ASK 7 CLK END METHOD 351404 44 12 2 5 717 928 39 METHOD SCANJKFF IS IN J K CLK SCAN MODE OUT Q ASK J CLK SCAN MODE END METHOD METHOD JKFFNR IS IN J K CLK NRAZ OUT Q NQ ASK Q NQ J K CLK NRAZ END METHOD METHOD JKFFNRNS IS IN J K CLK NRAZ NSET OUT Q NQ ASK Q NQ J K CLK NRAZ NSET END METHOD METHOD JKFFNS IS IN J K CLK NSET OUT Q NQ ASK Q NQ J K CLK NSET END METHOD METHOD JKFFR IS IN J K CLK RAZ OUT Q NQ ASK Q NQ J K CLK RAZ END METHOD METHOD SCANJKFFR IS IN J K CLK RAZ SCAN MODE OUT Q NQ ASK Q NQ J K CLK RAZ SCAN MODE END METHOD METHOD JKFFRS IS IN J K CLK RAZ SET OUT Q NQ ASK Q NQ J K CLK RAZ SET END METHOD METHOD SCANJKFFRS IS IN J K CLK RAZ SET SCAN
10. U S Patent NOISHSANO9 806 310 005 lt H c de 0110 LINVS 9417 NOISH3ANOO LSTILIN voc 0 19 OH OL 1307 8 9 NNS NOISU3ANOO 3114 0 11 3 ANY NOISH3ANOO eae NOISHSANOO 3714 ON 787 50916 __ XXXOLNY 98 1110 ONY 30710 102 1000 606 SWI 3 0 108 Sud 030 30 NNS HO Dd 3 IWNOLLONNA NOISH3ANOO 3 03f WIS 9NISS300Hd Nid 5 717 928 Sheet 5 of 8 Feb 10 1998 U S Patent ge 918 913 O1 A35 U S Patent Feb 10 1998 Sheet 6 of 8 5 717 928 ZH 00 OUTPUT INN FIG 4 INPUT A INPUT B iD OUT INPUT C INPUT 0 FIG 5 OUTPUT OUTPUT INPUT A INPUT B INPUT C INPUT E UTPUT FIG 7 U S Patent INPUT A Feb 10 1998 Sheet 7 of 8 INPUT B INPUT C FIG 8 INPUT A INPUT B INPUT INPUT E gt FIG 9 OUTPUT INPUT A bis OUTPUT INPUT 8 INPUT E FIG 10 NPUTA gt INPUTB gt BN FIG 11 OUT 5 717 928 U S Patent Feb 10 1998 Sheet 8 of 8 5 717 928 OUTPUT NAN n opr INPUT B INPUT E 9001 FIG 12 INPUT A INPUT B INPUT C
11. 0 PINI 1 learn incremental yes display yes store_all_edges yes constraint 1 x constraint 2 PIN13 x end pal 351404 pie 50 ay 132 351404 133 5 717 928 Appendix A 9 the DWL File Matra Design Semiconductor Inc 1989 134 5 717 928 135 136 WAVEFORM EVAL INPUT PIN11 PIN10 PINS PINS PIN7 PIN6 PINS PIN4 PIN3 PIN2 PIN1 OUTPUT PIN23 PIN22 PIN21 PIN20 PIN19 PIN18 PIN17 PIN16 PINI5 PIN14 BASE BIN INTERVAL 100 STROBEOFFSET 70 BEGIN PIN13 0 0 PINIO 0 PIN9 0 PIN8 PIN7 PIN6 PINS PIN4 PIN3 PIN2 PIN1 0 learn testgen pal PIN13 1 testgen pal learn END ENDWAVEFORM 351404 62 4 i eh EE 5 i 5 717 928 137 138 Appendix A 10 the TAB File Matra Design Semiconductor Inc 1989 351404 148 55 gt 5 717 928 139 PPPPPPPPPPPPP 222 111 70 1 1 222211111111 INNNNNNNNN219 32109876543 10987654321 112 TIME 0 Z000ZZZZ1Z000000000000001 2000 211 111011110110 4000 02777111171011111011111110 4041 0ZZZ0111ZI011111011111110 7000 ZZZZZZ2222001111011111111 8000 ZZZZZZZZZ2001111011110111 9000 ZZZZZZZZZZ001111011111111 12000 ZZZZZZ22212001110011111101 13000 222201 14000 72722220 1 14041 77222227001 1 17000 ZZZZZZZZ02001100011111101 18000 7777700 71 1900
12. Aharon Tran et al IBM Research and Development vol 26 No 4 Jul 1982 p 475 484 The Weighted Random Test Pattern Generator Daniel Schmurmann et al IEEE transaction of computer vol c 24 No 7 Jul 1975 pp 695 700 Dan Powers FGPA to Gate Array Migration The Best of Both Worlds May 1990 pp 345 348 Electro Conference Record vol 15 No 9 11 Primary Examiner Meng Ai T An Attorney Agent or Firm Skjerven Morrill MacPherson Franklin amp Friel Edward C Kwok 57 ABSTRACT In accordance with the present invention a system and method for converting an implementation of a logic descrip tion describing a field programmable device into an imple mentation of the same logic in a factory programmed device are provided In one embodiment of the present invention an expert system synthesizes a logic circuit model based on the logic description An automatic test pattern generator provides test vectors including expected response signals for the logic circuit model generated by the expert system The automatically generated test vectors are provided to a tester which applies the test vectors as input stimuli to the field programmable device The output signals of the field pro grammable device are verified against the expected response signals If the output signals of the field programmable device match the expected response signals the computer model is considered correct and mask layout may b
13. BUFINTTL GN11PD PINI1 N11PD BUFINTTL GNIOPD PIN10 N10PD BUFINTTL GN9PD PIN9 N9PD BUFINTTL GN8PD PIN8 N8PD BUFINTTL GN7PD PIN7 N7PD BUFINTTL GN6PD PIN6 BUFINTTL GNSPD PINS NSPD BUFINTTL GN4PD PIN4 BUFINTTL GN3PD PIN3 N3PD BUFINTTL GN2PD PIN2 N2PD 621271 21301 21271 621281 21301 21281 71291 21301 21291 621301 NIPD 21301 BUFINTTL GNIPD NIPD INVP GZ1311 21401 21311 BO3N4 621011 21381 21021 PIN21 NAND2 GZ1021 21233 21031 21021 DFFRNI GZ1321 21112 21291 21311 21322 BO3N4 GZ1001 21331 21021 PIN22 AOI2W22 67951 21331 21211 N3PD 21113 2951 351404 37 0 8 NANDI3 DFFRNI ANDI2 BO3N4 ORI2 BO3N4 BO3N4 BO3N4 BO3N4 BO3N4 DFFRNI INV2 AODW22 NAND3 NORI3 OAI2W22 BO3N4 DFFRNI BO3N4 AODW21 DFFRNI INV2 AOI2W22 DFFRNI INVP INVP ANDI2 POR SUPPLY 127 021331 67971 671341 GZ1091 671101 621111 621121 GZ1131 GZ141 21161 021171 621351 GZ1191 GZ1201 GZ1211 GZ1031 GNI4MX GZ1041 GZ1361 GZ1151 GNN19MX GZ1371 GZ1071 GZ1081 GZ981 GZ1381 GZ1391 071401 671231 5 717 928 128 2972 71271 21391 71331 71332 N8PD 71233 2112 2971 7951 2972 21091 21271 21311 21341 71342 21322 21112 21091 21021 21093 21342 21111 PIN15 N7PD N13PD 21111 21112 71211 21113 21032 21192 PIN14 7102
14. DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY 351404 231 71401 2951 2951 2971 Z971 Z972 Z972 Z981 Z981 ZPORNODI ZPORNODI ZPORNODI ZPORNOD2 ZPORNOD2 ZPORNOD2 ZPORNOD2 ZPORNOD2 ZPORNOD3 ZPORNOD3 ZPORNOD4 ZPORNOD4 ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP ZPORNODCAP GZ1401 02951 GZ971 GZ971 GZ981 POR2 POR2 POR4 POR4 POR4 POR4 6 PORS PORS PORS PORS 8 PORS PORS PORS 8 PORS PORS PORS PORS PORS POR8 POR8 POR8 PORS PORS PORS PORS PORS PORS 8 POR8 PORS 8 5 717 928 INN OUT NAN EN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 21391 GZ971 671161 621331 GZ1081 PORIN POR2 9 POR7 POR6 POR3 POR4 201 6 POR2 POR4 PORS POR3 POR28 11 12 15 16 17 20 18 POR13 19 14 21 POR22 POR34 POR23 POR33 POR24 POR32 POR25 POR31 POR26 POR30 7 IN IN Z tn
15. SET cell GASPDFFRS is record 351404 47 5 717 928 51 52 in D CK R S out Q QN class seq put same area than DFFRNSNI used for synthesis area 7 fan_in 1 1 1 1 delay 0 0 fan out factor 0 0 max fan out 8 function D CK AR S A D CK AR S hilo_order D CK R S Q QN method DFFRS Q QN D CK S R end record cell SCANDFFRS is record in D CK R S SC MOJ out 9 03 class seq area 6 fan_in 1 2 2 2 1 1 delay 10 11 fan out factor 1 1 max fan out function MO SC MO D CK R S MO SC MO D CK R S hilo order D CK R S Q QN SC MO be careful R and S reverted with method method SCANDFFS Q QN D CK S R SC MO end record cell SCANJKFF is record in J K CK SC MO out Q QN class seq area 7 fan_in 1 1 3 1 1 delay 6 7 fan out factor lt 1 1 max fan out 8 function MO SC MO JSK CK MO SC MO J K CK hilo_order J K CK Q QN SC MO method SCANJKFF Q QN J K CK SC MO end record cell SCANJKFFR is record in 5 out class seq area 8 fan_in 1 1 3 2 1 1 delay 8 10 fan out factor 2 2 1 351404 Lip 20 47 5 717 928 53 54 max_fan_out 8 function MO SC4 MO SK CK R MO SC MO J K CK R hilo order J K CK R Q QN SC MO method SCANJKFFR Q QN J K CK R SC MO end record cell SCANJKF
16. 18 24 12 18 24 12 18 24 12 18 24 12 18 24 24 204 1 7 1 7 1 7 1 7 17 17 1 7 17 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 177 177 177 1 7 1 7 1 7 1 7 1 7 351404 205 5 717 928 Appendix A 19 the SET File Matra Design Semiconductor Inc 1989 A 206 5 717 928 207 208 Rem ID Logic Master HS 2 1 Options Standard Rem IMS BOARD 20R Init SRQ 7 FAST verify disable sample disable Cik Internal OOns Event 0 Off Event l User 1 Off Event 2 BeginTest Off Event 3 Error On Config 1 STM 16 8K Force PGM PGM 1A PGM 1C Config 2 STM 16 8K Force PGM PGM ID PGM 1F Config 3 STM 16 8K Force PGM PGM 11 PGM 1J Config 16 8K Force PGM PGM 1G PGM 1L Config 5 5 16 8K Compare Expect Config 6 ACQ 16 8K Compare Acquire INP PGM 1B PGM 1B Config 7 STM 16 8K Compare Expect Config 8 ACQ 16 8K Compare Acquire INP PGM 1E PGM 1E Config 741 16 8K Compare Expect Config 10 ACQ 16 8K Compare Acquire INP PGM 1H PGM 1H Config 3 16 8K Compare Expect Config 12 ACQ 16 8K Compare Acquire INP PGM PGM Resource ingroupl Force TXT 1 A7 PIN11 1 A6 PIN22 1 A5 PIN33 1 A4 PIN4 4 1 A3 PINS 5 1 A2 PIN6 6 1 Al PIN7 7 1 AO PINS 8 Resource End Radix ingroup Bin Polarity ingroupl Pos Hidrive ingroupl 5 00V Lodrive 1 0 Form
17. 928 56 65 5 717 928 85 NAND2_NOR2_GEN _ NAND3_INV1_IN3 NOR2 INV1_11 NOR2 NAND2_GEN NORI3_ MACRO MUXI REM OR2 EXPAND2 OR2 INVI OR3 EXPAND2 rule AB E MAC2 lt 6 gt is in A B E out AND EN begin if Z6 1 NAND2 B AND INV2 Z6 1 then AND EN ANDD A B E end if end rule AB E MAC2 GEN 6 is in A B E out AND EN generic out NAN begin if NAN NAND2 B AND EN INV2 NAN E then AND NAN EN ANDI2 B E end if end rule AB E MAC3 gt 6 lt is in AND EN begin if Z6 1 NAND2 AND INV2 E 2651 then AND ANDI2 A E end if end rule MAC3 GEN lt 6 gt is 351404 37 CC 5 717 928 87 in out AND EN generic out NAN begin if NAN NAND2 A B EN AND INV2 then AND NAN EN 2 A E end if end rule AND3 EXPAND lt 1 gt is IN A B E OUT C D begin if D AND3 B then NAND3 A B E D INVI end if end rule AND3 EXPAND2 1 is IN B E OUT D begin if D AND3 A then C NAND3 B D INVI end if end AND3_OUT2 lt 1 gt is IN A E OUT DCs begin if C AND3 A then C NAND3 B E end if e
18. A B end record cell AND3 is record class combi in A B C out AND NAN area 2 fan_in delay 6 6 fan out factor 1 1 max_fan_out 8 function hilo_order A B C AND NAN end record cell AND4 is record class combi in A B C D out AND NAN area 3 fan_in 1 1 1 1 delay 7 7 fan out factor 1 1 max fan out 8 function A B C D XA B C D hilo order A B C D AND NAN end record cell ANDI2 is record replaced combi by unknown to avoid use at lucas synthesis level because it is used when only two inputs conencted class combi class unknown in A B E out area 2 fan_in 1 1 1 delay 5 5 3 fan out factor 1 1 1 E fan out 8 function A B A B E hilo_order A B AND NAN E EN method AND AND A B end record cell ANDM is record replaced combi by unkonwn to avoid use at lucas synthesis level because it is used when only four inputs connected class combi class unknown in 351404 Mh 26 55 5 717 928 65 out AND NAN EN area 3 fan_in 1 1 1 1 1 delay 7 7 3 fan out factor 1 1 1 max_fan_out 8 function A B C D A B C D E hilo_order A B C D AND NAN E EN end record cell OR2 is record class combi in A B out OR NOR area 2
19. BO3N4 21322 21192 671161 PIN18 BO3N4 Z971 Z1192 921171 PIN23 BO3N4 21351 21192 021351 Z1351 21352 21191 21281 71391 671191 21191 21192 INV2 21201 Gz1201 21201 AOI2W22 21351 21211 N2PD 21113 GZ1211 21211 NAND3 21341 N9PD 21031 671031 Z1031 Z1032 NI3PD N7PD N8PD NI4MX GN14MX NI4MX OAI2W22 NOPD 71332 71382 71362 GZ1041 PIN20 BO3N4 Z1361 Z1021 GZ1361 21361 21362 DFFRNI 21072 21291 21391 021151 19 BO3N4 21372 21192 GNNI9MX NNI9MX AOI2W21 NSPD 21371 21021 621371 21371 21372 DFFRNI 21071 21291 21311 021071 21071 21072 2 19 21081 621081 Z1081 Z1082 NORI3 21371 21093 N5PD 2981 62981 2981 AOI2W22 21381 21211 21113 021381 21381 21382 DFFRN1 21082 21271 21391 921391 21391 INVP 21401 GZ1401 21401 INVP 21231 071231 71231 21232 21233 ANDI2 N10PD NINPWR N9PD GNINPWR NINPWR POR SONE END 351404 55 SE 5 717 928 123 124 Appendix A 7 the File Matra Design Semiconductor Inc 1989 351404 Ath 56 55 5 717 928 125 126 FIRST PAGE OF SCAN k 5k 3 ok ke 9k de 9k ke o jc ke ak i 3k ke
20. FAN2 RN Q QN DFFRNI D FANIN end if end rule FIN DFFRNI RN lt 11 gt is in D CK RN out QN generic out RN begin if QN DFFRNI D CK RN then FANIN FAN2 RN GON DFFRNI D FANIN end if end rule NOFAN SUPPI lt 11 gt is supplyl ONEIN out ONEOUT 351404 p 9 7 as i mmo 97 generic_out begin if ONEOUT GEN then GEN end if end rule F3F3F3 ID13 in out generic out begin if D C B then B C D end if end rule ID13 F8 gt 4 lt is in out begin if B C D then D B C end if end rule ID14 F8 4 is in out begin if B C D E then E B C D 351404 5 717 928 GEN ONEIN ONEIN ONEIN _GEN lt 11 gt is B C D A FAN3 A FAN3 FAN3 A ID13 A B C D 1013 FANS A 0 A 1D14 A FANS E E nthe 3 22 5 717 928 99 100 end if end rule F2F2 FA GEN 4 is in AI out B C generic out A begin if C 2 8 2 then C FAN4 B end if end rule F2F2F2 F6 MRG GEN gt 4 lt is in 7 out generic_out iA begin if D FAN2 FAN2
21. Fault analysis ended took 0 40 secs total 7 73 secs Running PLD PAL with 10 active faults Exposing fault N6PD stuck at 0 Exposing fault 21371 stuck at 0 Exposing fault Z1081 stuck at 0 TG eee TG PLD PAL TG Dynamic problem inserted Name Spot Faults Use Current State Yes Raps YES backtracks 5 Overwriting value of USE CURRENT STATE in frame SPOT FAULTS Overwriting value of RAPS in frame SPOT FAULTS Overwriting value of MAX BACKTRACKS in frame SPOT FAULTS TG Problem SPOT FAULTS TG Constraint PIN X TG Constraint PINI3 X TG Working in Combinational Area Default TG Trying to catch stuck at 0 on N6PD TG Trying to catch stuck at 0 on Z1081 TG Trying to catch 2 faults TG Applying RAPS to combinational area Default TG End problem SPOT FAULTS At time 58700 number of active faults is 8 TG see See TG Task PAL repeated TG Dynamic problem inserted Name Spot_Faults Use_Current_State YES Raps YES Max_backtracks 5 Overwriting value of USE CURRENT STATE in frame SPOT FAULTS Overwriting value of RAPS in frame SPOT FAULTS Overwriting value of MAX BACKTRACKS in frame SPOT FAULTS TG Problem SPOT FAULTS TG Constraint PINI X TG Constraint PIN13 X Spot faults was specified for problem SPOT FAULTS but no f
22. Inc 1989 351404 E 53 lt 2 5 717 928 119 120 o E OE Date T Wed Oct 10 12 32 22 PDT 1990 Device p22v10 Technology md Path usr desdisk2 design bfll From Abel R eval abl To Hilo R eval cct PIN 1 gt clk25 PIN 2 gt db00 PIN 3 gt 4501 PIN 4 gt db02 PIN 5 gt vsync PIN 6 gt sccint_ PIN 7 gt hwcyc_ PIN 8 gt ba02 PIN 9 rd_ PIN 10 gt res_ PIN 11 gt ate_ PIN 13 gt ba04 PIN 14 gt intenb PIN 15 gt csdone PIN 16 gt cycntl_ 17 gt rdentl_ PIN 18 gt rdstat_ PIN 19 gt vihld_ PIN 20 gt vi PIN 21 gt vien PIN 22 7 sien PIN 23 vidon WITH LIB MD CIRCUIT EVAL IS IN PIN1 PIN2 PIN3 PIN4 P
23. MODE OUT Q NQ ASK 7 K CLK RAZ SET SCAN MODE END METHOD 351404 Ah 4 5 717 928 41 METHOD JKFFS IS IN J K CLK SET OUT Q NQ ASK Q NQ J K CLK SET END METHOD METHOD SCANJKFFS IS IN J K CLK SET SCAN MODE OUT Q NQ ASK Q NQ J K CLK SET SCAN MODE END METHOD METHOD RSNAND IS IN RN SN OUT Q NQ ASK Q NQ RN SN END METHOD METHOD RSNOR IS INR 5 OUT Q ASK Q 5 END METHOD METHOD LATCH 18 IN D OUT Q NQ ASK Q NQ D ENA END METHOD METHOD BUF3STA IS IN IN1 ENA OUT XXX ASK ENA END METHOD METHOD BUFIOTTL IS IN INI ENA QUT 001 ASK OUT INI ENA END METHOD METHOD BUFOUT IS IN INI OUT XXX ASK XXX INI END METHOD 351404 45 fu 42 43 METHOD BUFINTTL IS IN XXX OUT OUT ASK OUTI END METHOD METHOD BUFINDIR IS IN XXX OUT OUT 1 ASK XXX 0011 END METHOD 351404 5 717 928 S P P e 351404 45 5 717 928 Appendix A 4 the MD CEL File Matra Design Semiconductor Inc 1989 5 717 928 47 48 EE special cells for implementing virtual components not mapped by regular cells
24. OUT INPUT D FIG 13 5 717 928 1 SYSTEM AND A METHOD FOR OBTAINING A MASK PROGRAMMABLE DEVICE USING A LOGIC DESCRIPTION AND A FIELD PROGRAMMABLE DEVICE IMPLEMENTING THE LOGIC DESCRIPTION FIELD OF THE INVENTION This invention relates to the field of integrated circuits In particular this invention relates to the field of programmable logic devices BACKGROUND OF THE INVENTION Field programmable logic devices also commonly known as programmable logic devices PLDs are programmable integrated circuits sold to the user unprogrammed The user then programs the device to provide logic functions required by his her application Examples of PLDs are discussed in the PAL Device Data Book third edition 1988 pub lished by Advanced Micro Devices Inc of Sunnyvale Calif incorporated herein by reference in its entirety PALs and FPLAs are types of PLDs Because a PLD can be conveniently programmed using commercially available programming equipment PLDs pro vide design flexibility and quick turn around which are important advantages for certain applications For example in the development of a product prototype debugging in the field environment can be accomplished by simply replacing a faulty PLD by one implementing the correct logic However because each PLD must be individually programmed PLDs are more expensive than factory programmed devices which are mask programmed in large batches during the fabrication
25. PIN14 PIN15 PIN16 PIN17 PINI8 19 PIN20 PIN21 PIN22 PIN23 VDD VDD PIN1 PIN2 PIN3 PIN4 PINS PIN6 PIN PINS 5 L b2 9 N WIAA We 351404 197 5 717 928 b 722 198 331404 199 5 717 928 Appendix A 18 the MD PAD File Matra Design Semiconductor Inc 1989 0739512 ea 200 5 717 928 201 202 MASK_NO OMxx JDD STATIC ua 8 DYNAMIC 20 REVISION A PACKAGE XXXX TG LIST TG 10 10 TG2 12 10 This is 10 In Out gt with a width of 10 TG3 TG4 TGS TG6 20 10 This is 10 ln Out spec with a width of 10 TG8 TR 100 PIN LIST Signal Pad Pin Test BUF Type Type 101 JOH TG Control Name No Pad fun Input Pin ua ua ma ma Signal kkk BERK Kk beo component BUF Type Type IL IOL IOH TG name fun input Pin ua ua ma ma kkk 5 BUFINDDN PD 45 9 1 BUFINDUP PU 9 4 5 1 BUFINDIR I 4 5 45 1 BUF3STA O Z 4 5 4 5 6 6 7 BO3N2 0 7 45 4 5 12 12 7 BO3N3 O Z 4 5 4 5 18 18 7 BO3N4 OZ 4 5 4 5 24 24 7 BUF
26. PINS 178 PING PINS PIN14 PIN15 PIN16 PIN17 PIN18 PIN19 PIN20 PIN21 PIN22 PIN23 71192 211171021 POC PINS PIN10 PINH PIN13 PIN2 PIN3 PIN4 PINS PIN6 PIN7 PIN8 PIN14 PINIS PIN16 PIN17 PINI8 PIN19 PIN20 PIN21 PIN22 PIN23 21192 71111 21021 SPATTERN PIN PIN10 PINS PINS PIN7 PING PINS PIN3 PIN2 PIN1 2001 000000000000 4001 011111011110 6001 011111011111 8001 001111011111 10001 001111011110 12001 001111011111 14001 001110011111 16001 001110011110 18001 001110011111 20001 001100011111 22001 001100011110 24001 001100011111 26001 101100011111 28001 101100011110 30001 101100011111 32001 001100011111 34001 001100011110 36001 001100011111 38001 001000001111 351404 B 3 M Y en 5 717 928 179 40001 001000001110 42001 001000001111 44001 011000001111 46001 011000001110 48001 011000001111 50001 011100001111 52001 011100001110 54001 011100001111 56001 011100001110 58001 011100001111 60001 011100001110 62001 011100001111 64001 111100001111 66001 111111101111 68001 111111101110 70001 111111101111 72001 111111111111 74001 111111111110 78001 111111101111 80001 111111101110 82001 111111101111 84001 111111101110 SEOP STIME 87000 2000 SEND Simulation using MD library 1 edis PRINT Listing of selected signal outputs as a function of time 351404 TIME 200
27. frame SPOT_FAULTS Overwriting value of MAX_BACKTRACKS in frame SPOT_F AULTS TG Problem SPOT_FAULTS TG Constraint PINI X TG Constraint PIN13 X Spot_faults was specified for problem SPOT_F AULTS but no faults were found that could be detected in the current state of the circuit TG No faults spotted TG Applying RAPS to combinational area Default TG End problem SPOT FAULTS TG TG Task PAL repeated TG Dynamic problem inserted Name Spot_Faults Use_Current_State NO Raps NO Max_backtracks 5 Overwriting value of USE CURRENT STATE in frame SPOT_FAULTS Overwriting value of RAPS in frame SPOT_FAULTS Overwriting value of MAX_BACKTRACKS in frame SPOT_FAULTS TG Problem SPOT_FAULTS TG Constraint PINI X TG Constraint PIN13 X TG Working in Combinational Area Default TG Trying to catch stuck at 0 21381 TG Trying to catch stuck at 0 21331 TG Trying to catch stuck at 0 14 TG Trying to catch stuck at 1 on 21322 TG Trying to catch stuck at 0 71 TG Trying to catch stuck at 0 on NNI9MX TG Trying to catch 6 faults TG Using state machine knowledge TG To change PAL TG From 0000110 TG To 11X1101 Trying to
28. input files described below These programs can be executed on an IBM Personal Computer or a machine compatible with an IBM Personal Computer hereinafter IBM PC or a Sun Microsystems Model Sun 3 worksta tion hereinafter Sun 3 However other computers or workstations may also be used As shown in FIG 2 a method in accordance with our invention commences when the customer provides a logic description representing the logic functions implemented in a PLD The logic description can be expressed in a logic equation description language such as ABEL Details con cerning ABEL can be found in ABEL 3 0 published by Data I O Corporation Redmond Wash incorporated herein by reference in its entirety In other embodiments other logic description languages may be used Also in other embodiments other methods are used to provide a logic description such as truth tables or schematic representa tions of logic circuits An example of an input file containing ABEL logic equations is included in Appendix A 1 attached hereto These equations describe logic to be implemented in an AMD 22V10 logic array available from Advanced Micro Devices Inc of Sunnyvale Calif However in other embodiments other logic equations are used which describe PLDs other than the 22V10 10 15 35 45 4 If the customer s logic description is not in the ABEL format an optional conversion program can be provided such as shown i
29. is used at the place of INV1 class class in out area fan_in delay fan_out_factor max_fan_out 351404 combi unknown IN INN MAE 29 55 70 71 5 717 928 72 function IN hilo_order IN INN end record class combi in out 1 fan in 1 delay 3 fan out factor 1 max fan out 8 function A hilo_order AAN method INV AN A end record cell AOI2W44 is record class combi in A B C D E F G H out OUT area 4 fan_in 1 1 1 1 1 1 1 1 delay 16 fan out factor 2 max fan out 8 function A B C D E F G H hilo_order A B C D E F G H OUT end record cell AOI2W33 is record class combi in A B C D E F out OUT area 3 fan_in 1 1 1 1 1 1 delay 12 fan out factor 2 max fan out 8 function hilo_order A B C D E F OUT end record cell OAI2W33 is record class combi in A B C D E F out OUT area 3 fan in 1 1 1 1 1 1 delay 13 fan_out_factor 3 max_fan_out 8 351404 4 20 51 73 function hilo_order end record 5 717 928 74 X A B C D E F A B C D E F OUT cell AOI2W22 is record class in out area fan in delay fan out factor max fan out function hilo order end record combi A
30. layout generated for back annotation purpose This program provides an output file DLY Appendix A 21 which describes parasitic impedances from the layout generated As shown in the listing of Appendix A 21 each path of an electrical node is provided with a delay For example on the first line of file DLY is shown LOAD N10PD indicating that the delay path or paths of node N10PD is to follow and that the total capacitive load on node N10PD is 156fF In this instance N10PD has only one path which is indicated on the next line preceded by DELAY N10PD As shown therein the electrical path between the OUT output of cell GN10PD and the A input of cell GZ1231 is estimated to have a delay of 20 ps Xf an electrical node has multiple paths such as node 21021 shown on lines 36 42 cach path is shown sepa rately The parasitic impedances are used to perform post layout simulation Such a post layout simulation is desirable because parasitic impedances estimated from the actual 10 15 35 40 45 55 10 geometry of the circuit provides more accurate estimates of circuit performance than are attainable from the previous pre layout simulation performed by ARCIS If another simu lator other than ARCIS is used it will be necessary to use the back annotation technique for that simulator Such conver sion techniques are also known in the art The post layout simulation is carried out in the same
31. manner as the pre layout simulation described above The results of the post layout simulation are analyzed against the timing specified in the PLD manufacturer s data sheet in the present embodiment the 22V10 data sheet available from Advanced Micro Devices Inc of Sunnyvale Calif Again if the simulation yields results which do not match those provided by the PLD data sheet the ASIC vendor modifies the layout generated and resimulates the circuit without the customer s intervention until an acceptable layout is obtained When the ASIC vendor is satisfied with the functional and timing verifications a final design rule check is performed to provide confidence that the final design complies with the design rules of the intended fabrication process At this point the physical layout is completed by merging the placement and routing information obtained above with the physical layout libraries specific to the ASIC vendor s circuit technology Although this step is normally done manually on a layout workstation an automated program can be used Whether the mask data implements the logic circuit netlist provided to generate the layout may also be checked at this point These verifications are accomplished respectively in block 212 this embodiment by DRC design rule checker and LVS logic verification system both obtainable from Cadence Design Systems Inc San Jose Calif DRC and LVS systems take as inputs the netlist and the com
32. out function IN ENA IN ENA hilo_order IN ENA XXX OUT method BUFIOTTL OUT XXX IN ENA end record MoE IEE EG eae cell POR is record class unknown in POWER out POR area 0 fan_in 1 delay 0 fan out factor 0 max fan out 8 function POWER hilo_order POWER POR method POR POR POWR end record cell NAND2 is record class combi in out NAN area gt fan_in 1 1 delay 3 fan out_factor 1 max_fan_out 8 function A B hilo_order A B NAN method NAND NAN A B end record NAND3 is record class combi in A B C out NAN area 2 fan_in 1 1 1 351404 22 51 5 717 928 57 delay 5 fan out factor 1 max fan out 8 function hilo_order A B C NAN end record cell NAND4 is record class combi in A B C D out 7 NAN area 2 fan_in 1 1 1 1 delay 6 fan out factor 1 max fan out 8 function hilo_order A lt
33. process without additional cost It is therefore cost effective when a product is in high volume production to replace a PLD with a pin for pin compatible factory programmed device after product devel opment is stabilized A gate array circuit is a popular factory programmed substitute for a PLD A gate array circuit is typically programmed by providing during fabrication a customized pattern of interconnect metallization to interconnect the underlying generic array of transistors The pattern of inter connect metallization is provided using customized photo masks The gate array circuit emerging from the fabrication process implements application specific logic functions Presently the conversion from a PLD circuit to a factory programmed circuit involves close cooperation between the supplier of the factory programmed circuit hereinafter the ASIC vendor and the user of the PLD hereinafter the customer FIG 1 shows the steps required to accomplish the conversion Referring to FIG 1 the customer provides to the ASIC vendor at step 100 the logic description implemented in the PLD As illustrated by step 101 this logic description is then translated into a schematic representation of a logic circuit This step is often accomplished using a software schematic capture program From this schematic representation a netlist is generated for use with simulators and verifiers at step 102 These simulators and verifiers are s
34. the KDB and the DWL files are attached hereto as Appendices A 8 and A 9 respectively The examples of the KDB and DWL files are appropriate when converting a device implemented in an AMD 22V 10 to a gate array implementation If one were to convert from other generic device types e g 2 10 available from AMD one would have to modify the KDB and DWL files appropriately The above described input files aliow the HITEST pro gram to provide an output file including a set of test vectors This TAB file Appendix A 10 is intended for use as stimuli in testing the logic circuit described in the CCT file Fault detection analysis is used at this step illustrated by block 204 to ensure proper fault coverage by the test vectors HITEST provides a log file identified by file name extension LOG Appendix A 11 which summarizes any exception condition encountered during fault simulation and test vector generation The LOG file is merely a user report which is not used as an input file for any programs Optionally the HITEST module may also receive a set of seed test vectors e g generated by the customer HITEST learns from and builds upon these seed vectors to more rapidly generate a set of test vectors which include the seed vectors to test the customer provided PLD In one embodiment the CCT and TAB files are input to a program ARCIS block 207 which estimates the propa gation delays of signal
35. the pin is an input or output pin the type of output buffer provided the type of input or output buffer provided e g if the pin is an input pin TTL or CMOS compatible and or including a pullup or pulldown or IOL IOH current limits if the pin is an input pin the input current limits when the input signal is low and high respectively or if the pin is an output pin output current limits when the output signal is low and high respectively and which timing generator TG of the tester is assigned Of importance since the IN file indicates which buffer type is connected to each input pin PADPIN merely retrieves the DC parameter information from a library MD PAD Appendix A 18 which contains parameter information for each type of buffer The abbreviations PU PD and ON in the MD PAD stand for pullup pulldown and open drain respectively O Z is a tristate output YO is a bidirectional pin The NP1 output file of the PADPIN is provided to a program NPITOSET block 208 to provide NPITOSET output files identified by file extensions SET and PIN for tester set up The SET file is the IMS tester program and defines in the tester s supported format the tester resource allocation and each attribute An example of a SET file is attached hereto as Appendix A 19 NPITOSET is pro vided for interfacing the NP1 file with the IMS tester of this embodiment If another tester
36. which describe for GASP rules for efficiently converting the logic description into a netlist describing interconnected logic cells of the types listed in the MD CEL library In response to these input files GASP provides therefrom a netlist of a logic circuit which performs the functions described in the ABL file Information con cerning the operation and use of GASP can be obtained from GenRad Incorporated Fareham U K As is known in the art a netlist is a type of circuit description which lists all circuit components for example the gates buffers and flip flops in a circuit The netlist identifies the input and output leads of each circuit component and its connections to other circuit components As mentioned above the MPL file models the generic PLD type For example to model an AMD 22 10 one would provide a file such as provided in Appendix A 2 attached hereto If one were to use the present invention to convert a device implemented in a different PAL type into a mask programmable device one would modify the MPL file appropriately Attached as Appendix A 6 is a netlist file the NET file which GASP prepares from the MD CEL MET and RCP files discussed above In the NET file of Appendix A 7 after the line which states BEGIN is the listing describing the logic performed by the circuit The first term on each line in the listing is a label associated with the logic gate being described the seco
37. 0 4000 6000 8000 10000 12000 14000 16000 PPPPPPPPPPPPPPPPPPPPPPZZZ NNNNNNNNNNNNNNNNNNNNNNIIO 9111123456781111112222912 013 4567890123211 0000000000002 0 0000000000002Z1ZZZZ000Z 100 000000000000Z1ZZZZ000Z100 1110011110111Z1111ZZZ0011 11091111101 11ZIIIZZZ0011 110011111011ZZZZZZZZZZ111 110001111011ZZZZZZZZZZ111 110011111011ZZZZZZZZZZl11 110011111001ZIZZZZZZZZ101 13 180 181 18000 20000 22000 24000 26000 28000 30000 32000 34000 36000 38000 40000 42000 44000 46000 48000 50000 52000 54000 56000 58000 60000 62000 64000 66000 68000 70000 72000 74000 76000 78000 80000 82000 84000 86000 5 717 928 110001111001Z1ZZZZZZZZ101 110011111001Z1ZZZZZZZZ101 1100111110002172222227101 110001111000Z1ZZZZZZZ2101 110011111000ZIZZZZZZZZ101 110111111000ZZZZZZZZZ2111 110101111000ZZZZZZZZZZ111 110111111000ZZZZZZZZZZ111 110011111000Z1ZZZZZZZZ101 110001111000Z1ZZZZZZZZ101 110011111000271272222272101 0100111100007127272770007100 010001 110000Z1ZZZZ0007 100 01001 1 110000Z1ZZZZ000Z100 0110111100001 1 10110000000 0110011100001 1 10110000000 0110111100001 110110000000 111011110000111 111ZZZ0001 111001110000111111ZZZ0001 111011110000111111ZZZ0001 11100111000011111122720001 111011110000111111ZZZ0001 111001110000111111ZZZ0001 111011110000111111ZZZ0001 1111111100001Z1111ZZZ0011 1111111101111Z1111ZZZ0011 1111011101111Z1111ZZZ0011 1111111101111Z1111ZZ20011 1111111111111Z1111ZZZ0011 1111011111111
38. 0 ZZZZZZZZ0Z001100011111101 19041 2277711111 22000 ZZZZZZZZZ7101100011111111 23000 ZZZZZZZZZZ101100011110111 24000 2222222222101100011111111 27000 2777227722127001100011111101 28000 7272272722212001100011110101 29000 7772222212 001100011111101 351404 jaf CF 45 351404 5 717 928 141 29041 32000 33000 34000 34041 37000 38000 39000 42000 43000 44000 48000 49000 53000 54000 57000 58000 59000 60000 60041 63000 64000 65000 65041 68000 69000 22222722207001100011111101 Z111ZZZZ0Z001000001111001 Z111ZZZZ0Z001000001 110001 2111222202001000001 111001 2111222212001000001111001 1111110010011000001111000 1111110010011000001110000 1111110010011000001111000 1ZZZ111010011100001111100 1777111 110100 1222 11101001110000111 1100 1ZZZ11t01001 1100001110100 1ZZZ111010011 00001111100 1ZZZ111010011100001110100 1ZZZ111010011100001111100 1ZZZ1110Z0111100001 111110 272727 IZZZ1110Z1111111101110110 1222111021111111101111110 1222111121111111101111110 0 12 1 122 12221 0 122 20 170 11101111110 1ZZZ0111Z0111111101110110 ath 65 9G 142 351404 5 717 928 143 144 70000 1ZZZ0111Z0111111101111110 74000 1ZZZ0111Z0111111101110110 75000 177701 0 5 717 928 145 146 Appendix A 11 the LOG file Matra Design Semiconductor Inc 1989 351404 4 267 9 5 717 928 147 148 Log of si
39. 1 21192 PIN17 21322 21192 16 2971 21192 PIN18 21351 21192 PIN23 21191 21281 21391 21351 21201 21191 21192 21351 21211 N2PD 71113 21201 21341 NOPD 71031 21211 N13PD N7PD N8PD 71031 14 71032 N6PD 21332 21382 21362 NI4MX Z1361 Z1021 PIN20 21072 21291 213191 71361 21362 21372 71192 PIN19 NSPD Z1371 21021 NN19MX 21071 Z1291 21311 21371 21372 NNI9MX 71071 71081 71072 21371 21093 N5PD 21081 2981 71082 21381 21211 21113 7981 2 1082 21271 21391 21381 71382 21401 21391 21231 71401 100 NINPWR 21231 N9PD 21233 GNINPWR SONE NINPWR SONE WIRE N13PD NIIPD N10PD N9PD N8PD N7PD N6PD NSPD N4PD N3PD N2PD Z1271 71281 71291 71301 NIPD 71311 21021 213222951 21331 21332 2971 2972 21341 71342 71091 71093 Z1111 21112 71113 21351 21191 21192 2 1201 21211 71031 Z1032 NI4MX Z1361 Z1362 NNI9MX 21371 Z1372 Z1071 21072 21081 21082 2981 Z1381 Z1382 Z1391 Z1401 Z1231 Z1233 NINPWR INPUT PIN13 PIN11 PIN10 PINS PINS PIN7 PING PINS PIN4 PIN3 PIN2 PINI WIRE PIN23 PIN22 PIN21 PIN20 PIN19 PIN18 PIN17 PINI6 PIN15 PIN14 351404 D 58 57 5 717 928 129 130 Appendix A 8 the KDB File Matra Design Semiconductor Inc 1989 351404 sth 5 717 928 131 pld pal type DFFRNSN data out term q data bar out term nq data in term d clock waveform t PINI
40. 1 OUT 921031 OUT 7971 OUT GZ1231 OUT 0921211 OUT 021071 NAN 921011 GZ1001 921131 621041 NAN 9 021091 NOR 071211 NOR 921021 EN 011 rey 26 ENA ENA IN ENA wo IN 156 20 192 54 295 29 29 199 55 157 184 59 218 65 232 71 294 266 344 345 352 257 101 349 37 37 320 82 82 298 41 39 126 881 571 563 281 654 174 211 198 199 38 34 226 fF PS fF PS fF PS PS fF PS fF PS fF PS fF PS fF PS fF PS fF PS PS PS fF PS PS fF PS PS fF PS PS fF PS fF PS PS PS PS PS PS fF PS PS PS fF DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY DELAY DELAY LOAD DELAY DELAY DELAY LOAD DELAY LOAD DELAY DELAY DELAY DELAY DELAY DELAY LOAD DELAY LOAD DELAY DELAY DELAY DELAY LOAD DELAY LOAD DELAY DELAY LOAD DELAY DELAY DELAY LOAD DELAY 351404 227 Z1071 Z1072 21072 21081 21081 Z1082 21082 71091 71091 71093 21093 21111 71111 21112 71112 21112 71112 71113 71113 71113 71113 71191 71191 21192 71192 21192 21192 21192 71192 71192 21201 71201 71211 71211 71211 71211 71211 71231 71231 21233 21233 21233 21271 71271 21271 21271 7 1281 71281 GZ1071 GZ1071 GZ1081 GZ1081 GZ1091 GZ1091 GZ1111 6271111 971111 671111 GZ1111 671111 GZ1191 GZ1
41. 1 3 VSS 4 12 4 VSS 5 12 5 PINI3 6 13 6 PINI4 7 14 7 PINIS 8 15 8 6 9 16 9 PINI7 10 17 10 PINI8 11 18 PINI9 15 PIN20 16 20 16 17 21 17 PIN22 18 22 18 PIN23 19 23 19 VDD 20 24 20 VDD 21 24 21 22 1 22 PIN2 23 2 23 PIN3 24 3 24 PIN4 25 4 25 PINS 26 5 26 PIN6 27 6 27 PIN 30 7 30 351404 5 717 928 192 10 10 1990 12 58 MD250 30 N OMxx 8 20 A 8024 BUF Type Type IH IOL 10H TG fun Input Pin ua ua ma ma eee ES TIL I 45 45 TIL I 45 45 1 TIL 1 45 45 1 VSS VSS TTL 1 45 45 1 OZ 45 45 24 24 7 OZ 45 45 24 24 7 O Z 45 45 24 24 7 O Z 45 45 24 24 7 O Z 45 45 24 24 7 O Z 45 45 24 24 7 0 2 45 45 24 24 7 OZ 45 45 24 24 7 0 7 45 45 24 24 7 OZ 45 45 24 24 7 VDD VDD TIL 1 45 45 2 TTL I 45 45 i TTL I 45 45 1 TTL 45 45 1 TTL 45 45 1 TTL 1 45 45 1 TIL 1 45 45 1 17 Control Signal 5 717 928 193 194 PINS 31 8 TIL 45 45 1 2192 0 0 0 C a oe 21111 0 0 0 lt 5 C xL s 21021 0 0 0 SSR 351404 tth Ot 20 5 717 928 195 196 Appendix A 17 the PAD File Matra Design Semiconductor Inc 1989 351404 m 4 PINS PINI0 PIN11 VSS VSS PIN13
42. 1 QN Z1382 GZ1391 IN Z1401 INN Z1391 GZ1401 IN Z1231 INN Z1401 351404 Pu 232 5 717 928 221 222 GZ1231 A NIOPD B NINPWR AND Z1231 E N9PD EN Z1233 POR9 A ZPORNOD2 AN NINPWR PORIN IN ZPORNODI E VDD EN VDD OUT VDD POR2 IN ZPORNODCAP E ZPORNODI EN VDD OUT ZPORNODI POR3 IN ZPORNOD2 E GND EN ZPORNODCAP OUT VDD POR4 IN ZPORNOD3 E ZPORNODCAP EN VDD OUT ZPORNOD 2 PORS IN GND E ZPORNODCAP EN VDD OUT ZPORNOD3 POR6 IN ZPORNOD4 E ZPORNOD2 EN VDD OUT ZPORNOD3 POR IN VDD E ZPORNOD2 EN VDD OUT ZPORNODA4 PORS IN GND E GND EN VDD OUT ZPORNODCAP PORII IN GND E ZPORNODCAP EN GND OUT GND PORI2 IN GND E ZPORNODCAP EN GND OUT GND 13 IN GND E ZPORNODCAP EN GND OUT GND 04 IN GND E ZPORNODCAP EN GND OUT GND PORIS IN GND E ZPORNODCAP EN GND OUT GND PORI6 IN GND E ZPORNODCAP EN GND OUT GND 17 IN GND E ZPORNODCAP EN GND OUT GND 18 IN GND E ZPORNODCAP EN GND OUT GND 19 IN GND E ZPORNODCAP EN GND OUT GND POR20 IN GND E ZPORNODCAP EN GND OUT GND 21 IN GND E ZPORNODCAP EN GND OUT GND POR22 IN GND E ZPORNODCAP EN GND OUT GND POR23 IN GND E ZPORNODCAP EN GND OUT GND POR24 IN GND E ZPORNODCAP EN GND OUT GND 25 IN GND E ZPORNODCAP EN GND OUT GND POR26 IN GND E ZPORNODCAP EN GND OUT GND POR27 IN GND E ZPORNODCAP EN GND OUT GND POR28 IN GND E ZPORNODCAP EN GND OUT GND POR29 IN GND E ZPORNODCAP EN GND OUT GND POR30 IN GND E ZPORNODCAP EN GND OUT GND POR31 IN GND E ZPO
43. 11 66001 111111101111 68001 111111101110 70001 111111101111 7200 111111111111 74001 111111111110 76001 111111111111 78001 111111101111 80001 111111101110 82001 111111101111 84001 111111101110 SEOP STIME 87000 2000 END 351404 Att 5 717 928 75 27 168 5 717 928 169 170 Appendix A 13 the IN File Matra Design Semiconductor Inc 1989 351404 39 5 717 928 171 172 Hilo2Arcis v1 01 Sept 89 Revised Date 12 57 10 10 1990 SARRAY MD SVERIFY E Date Wed Oct 10 12 32 22 PDT 1990 Device 22 10 Technology md Path usr desdisk2 design bill From Abel R eval abl To Hilo R eval cct IRE A REE PIN 1 gt clk25_ PIN 2 gt db00 PIN 3 gt 01 PIN 4 gt db02 PINS gt vsync PIN 6 gt sccint_ PIN7 gt hweyc_ PIN 8 gt ba02 9 gt rd_ PIN 10 gt res PIN 11 gt _ PIN 13 gt 04 PIN 14 gt intenb_ PIN 15 gt csdone_ PIN 16 gt cycntl_ PIN 17 gt rdenti_ PIN 18 gt rdstat_ PIN 19 gt vihld_ PIN 20 gt vi PIN 21 gt vien PIN 22 gt sien PIN 23 gt vidon
44. 1301 21301 21301 2131 2431 21311 21311 71322 21322 21322 21331 21331 71331 71332 21332 21341 7 1341 21342 71342 21351 21351 21351 21361 21361 21362 71362 21371 21371 21371 21372 71372 21381 21381 71381 21382 21382 21391 21391 21391 21391 21391 71401 21401 GZ1291 GZ1291 GZ1291 GZ1301 GZ1301 GZ1301 GZ1311 021311 671311 621321 6271321 621331 621331 6271331 671341 671341 GZ1351 621351 671361 621361 821371 621371 621371 GZ1381 GZ1381 GZ1381 GZ1391 GZ1391 GZ1391 GZ1391 GZI401 5 717 928 INN 921361 INN GZ132i INN GZ1371 INN 81 INN 621271 INN 671291 INN GZ1341 INN 621321 INN 621371 QN 621141 QN GZ1091 Q GZ1001 Q GZ951 QN GN14MX Q GZ1211 QN 02101 621171 Q GZ1201 Q GZ1041 QN GNI4MX Q GZ1081 Q GNN19MX QN GZ1151 Q QZ1011 Q GZ981 QN GN14MX INN 621351 INN 31 INN 971381 INN 921361 INN 621311 me 7 CK CK CK IN IN IN RN RN IN IN IN IN A IN 437 6l 127 108 353 42 48 48 445 44 41 395 152 17 365 114 31 120 11 139 15 16 321 66 262 128 141 238 16 16 286 107 320 45 142 11 569 38 107 108 298 47 230 DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY DELAY LOAD DELAY DELAY DELAY DELAY LOAD DELAY LOAD DELAY LOAD DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY
45. 17 928 163 164 Appendix A 12 the SIM File Matra Design Semiconductor Inc 1989 304 4 25 05 5 717 928 165 Vector interval 200 ns TABTOARC REV 0 02 conversion for 50 0 1 NOSPIKE SACTIVITY LOAD 50 T PIN23 PIN22 PIN21 PIN20 9 8 PINI7 PIN16 PINIS PIN14 VCC CLKO 100 SPRINT POC PINS PIN10 PINII PIN13 PIN2 PIN3 PIN4 PINS PIN6 PIN7 PIN8 4 PINIS PIN16 PIN17 PIN18 PIN19 PIN20 PIN21 PIN22 PIN23 21192 2111 21021 PIN9 PINIO PINII PIN13 PIN PIN2 PIN3 PIN4 PINS PIN6 PIN8 PIN14 PINIS PIN16 PIN17 PIN18 PIN19 PIN20 21 PIN22 PIN23 21192 71111 21021 166 SPATTERN 10 PINS PINS PIN6 PINS PIN4 PIN3 PIN2 2001 4001 6001 8001 10001 12001 14001 16001 18001 20001 22001 24001 26001 28001 30001 32001 34001 36001 38001 40001 42001 44001 46001 48001 50001 52001 54001 351404 000000000000 011111011110 01111011111 001111011111 001111011110 001111011111 001110011111 001110011110 001110011111 001100011111 001100011110 001100011111 101100011111 101100011110 101100011111 001100011111 001100011110 001100011111 001000001111 001000001110 001000001111 011000001111 011000001110 011000001111 011100001111 011100001110 011100001111 Ath T 167 56001 011100001110 58001 011100001111 60001 011100001110 62001 011100001111 64001 1111000011
46. 191 GZ1191 GZ119t GZ191 021191 GZli91 621201 6271211 GZ1211 GZ1211 GZ1211 GZ1231 GZ1231 GZ1231 GZ1271 GZ1271 GZ1271 GZ1281 5 717 928 AN BN NOR EN AND EN OR NOR NOR NOR EN EN BN BN BN BN BN BN OUT NAN NAN NAN NAN AND EN EN INN INN INN INN GZ1371 GZ1361 GZ1071 GZ1381 GZ1341 GZ1081 21101 621321 071091 7971 GZ981 GZ1201 GZ951 GZ1351 GZ1171 621121 621141 21131 671161 671151 071191 071111 GZ981 GZ1201 GZ951 GZ1401 GZ1021 02971 GZ1331 GZ1341 GZ1381 621351 127 D 0 75 D 6 147 B 0 109 D 6 107 D 7 185 B 27 196 34 308 D 9 B 12 C 5 361 D 98 D 98 98 105 D 8 637 ENA 760 ENA 1080 ENA 1172 ENA 1105 ENA 1077 ENA 793 164 A 23 440 E 0 B 114 B 114 B 114 127 IN 4 273 A 9 B 1 464 CK 12 CK 72 CK 25 124 CK 8 228 PS fF PS fF PS fF PS fF PS fF PS fF PS fF PS PS PS fF PS PS PS fF PS fF PS PS PS PS PS PS fF PS fF PS PS PS PS fF PS fF PS PS fF PS PS PS fF PS LOAD DELAY DELAY DELAY LOAD DELAY DELAY DELAY LOAD DELAY DELAY DELAY LOAD DELAY DELAY LOAD DELAY DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY DELAY LOAD DELAY LOAD DELAY LOAD DELAY DELAY LOAD DELAY LOAD DELAY DELAY LOAD DELAY LOAD DELAY DELAY DELAY DELAY LOAD DELAY 351404 229 21291 21291 21291 21291 21301 7
47. 21332 N8PD 71233 21112 2971 7951 7972 71091 21271 71311 21341 71342 21322 21112 21091 21021 21093 21342 71111 PINIS N7PD 71111 21112 21211 21113 21032 21192 14 21021 71192 7 21322 71192 6 2971 21192 PIN18 71351 71192 PIN23 21191 21281 71391 71351 2 71201 21191 71192 21351 21211 N2PD 21113 21201 71341 N9PD 21031 21211 N13PD N8PD 21031 4 21032 21332 21382 21362 NI4MX 21072 21291 71391 21361 21367 21372 21192 PIN19 NSPD 21371 21021 NN19MX 71071 21291 21311 21371 71372 9 21071 21081 21072 21371 71093 N5PD 21081 2981 21082 21381 21211 N4PD 71113 7981 21082 71271 21391 21381 71382 21401 21391 21231 21401 NIOPD NINPWR 7 1231 N 3 N9PD 71233 VCC NINPWR SINPUT PIN PINIO PIN13 PIN2 IN3 PINS PIN6 PINS PINS OUTPUT PIN14 PIN15 PIN16 PIN17 PIN18 PIN19 PIN20 PIN21 PIN22 PIN23 5 SEND 351404 5 717 928 175 176 Appendix A 14 the OUT File Matra Design Semiconductor 351404 5 717 928 177 Inc 1989 ARCIS timing simulation version SUN 4B 0 Sept 89 input EVAL sim Wed Oct 10 13 14 36 1990 WORST CASE VDD 450 TEMP 70 00 Vector interval 200 ns TABTOARC REV 0 02 conversion for CYCLEI NOSPIKE SACTIVITY LOAD 50 23 PIN22 PIN21 PIN20 PIN19 PIN18 PIN17 PIN16 PIN1S 74 VCC CLKO 100 SPRINT PINS PINIO PIN11 PIN13 PIN PIN2PIN3 PIN4
48. 50V Sample outgroupl 35 00ns Resource outgroup2 Compare TXT 6 PINIS 15 Resource End Radix outgroup2 Bin Polarity outgroup2 Pos Threshold outgroup2 1 50V Sample outgroup2 35 00ns Resource outgroup3 Compare TXT 8 A3 PIN16 16 Resource End Radix outgroup3 Bin Polarity outgroup3 Pos Threshold outgroup3 1 50V Sample outgroup3 35 00ns Resource outgroup4 Compare TXT 8 B3 PIN2121 Resource End Radix outgroup4 Bin Polarity outgroup4 Pos Threshold outgroup4 1 50V Sample outgroup4 35 00ns Resource outgroup5 Compare TXT 10 A3 PIN22 22 Resource End Radix outgroup5 Bin Polarity outgroup5 Pos Threshold outgroup5 1 50V Sample outgroup5 35 00ns Resource outgroup6 Compare TXT 10 B3 PIN23 23 Resource End Radix outgroup6 Bin Polarity outgroup6 Pos Threshold outgroup6 1 50V Sample outgroup6 35 00ns Resource outgroup7 Compare TXT 12 A3 7 12 A2 PIN18 18 12 Al PINI9 19 12 A0 PIN20 20 Resource End 351404 5 717 928 ts 188 nj 212 5 717 928 213 Radix outgroup7 Bin Polarity outgroup7 Pos Threshold outgroup7 1 50V Sample outgroup7 35 00ns Resource veedeedee Power 1 V0 vdd 24 Resource End Power veedeedee 5 00V 250mA 0s HIZ Aclk System Fail 0 Mask 1111111111 End 351404 fet De 214 351404 215 5 717 928 Appendix 20 the SDL File Matra Design Semiconductor Inc 1989 ST 216 5 717 928 217 218
49. ARCIS 5 PATTERN is a truth table format for the input signals The lines immediately following PATTERN list the order in which input signals are provided in the SIM file The PATTERN information terminates at the line marked EOP end of pattern 6 TIME 87000 2000 instructs ARCIS to simulate and print at intervals of 200 ns until 8700 ns have elapsed Times listed in the SIM file are expressed in tenths of nanoseconds As mentioned above it is also necessary to put the CCT file into a format that can be accepted by ARCIS Block 203 represents a program which converts file CCT to file Appendix 13 As can readily be seen the file contains all the information of CCT but the input output order is re arranged slightly ARCIS also receives informa tion from a built in library which contains all of the gate buffer and flip flop propagation delays and calculates there from signal changes at various nodes and output leads throughout the device taking into account the number of input leads each device must drive i e fan out Thus if the input file SIM instructs ARCIS that at time T 1000 ns a signal applied to an input buffer goes high ARCIS looks up in a library parameters regarding the buffer delay and drive capabilities and determines the propagation delay exhibited by the buffer based on buffer characteristics and the number of input leads the buffer drives If based on the buffer fan out that buffer ha
50. B C D OUT 2 1 1 1 1 8 2 8 l XA B4C D A B C D OUT 0 012072 is record class in out area fan_in delay fan_out_factor max_fan_out function hilo_order end record combi A B C D OUT 2 1 1 1 1 12 A B CHD I A B C D OUT u II 8 AOI2W21 is record class in out area fan in delay fan out factor max fan out function hilo order end record cell OGO is record class in out area fan in delay fan out factor max fan out 351404 combi A B C OUT 1 1 1 6 2 8 MA B C A B C OUT combi A B C D E F G HL I J OUT 5 1 1 1 1 1 1 1 1 1 1 6 4 8 be 75 function hilo_order end record cell 001 is record 351404 5 717 928 76 1 A B C D E F GH 1 J OUT class combi in A B C D E out OUT area 3 fan_in 1 1 1 1 1 delay 9 fan out factor 2 max fan out 8 function A B C E E hilo order A B C D e OUT end record cell 72 class combi in A B C D out OUT area 2 fan_in 1 1 1 1 delay 5 fan out factor 2 max fan out 8 function A A B C D hilo_order A B C D OUT end record cell AOOIW22 is record class co
51. B C D NAN end record cell NANDS is record class combi in A B C D E out area 3 fan_in 1 1 1 1 1 delay 6 fan out factor 2 max fan out 8 function hilo_order A B C D E NAN end record cell NANDS is record class combi in A B lt C D E F G H out NAN area 6 fan_in 5 1 1 1 1 1 1 1 1 delay 9 fan out factor 1 max fan out 8 function hilo order A B C D E F G H NAN end record cell NANDI3 is record replaced combi by unknown to avoid use at lucas syntesis level because it is used when only three inputs connected class combi class unknown in A B C E 351404 Ak 28 52 5 717 928 59 out NAN EN area 2 fan_in 1 1 1 1 delay 5 3 fan out factor 1 1 max fan out 8 function hilo_order end record cell NOR2 is record class combi in A B out NOR area ml fan in 1 1 delay 3 fan out factor 2 max fan out 8 function CAB hilo_order A B NOR method end record cell NOR3 is record class combi in out NOR area 2 fan_in 1 1 1 delay 4 fan out factor 3 max fan out 8 function A B C hilo_order A B C NOR end record cell N
52. C D E hilo_order A B C D OR NOR E EN end record cell EXOR is record class combi in A B out XOR NOR area 3 fan_in 1 1 delay 2 2 fan out factor lt 22 max fan out 8 function A B A B A B hilo_order A B XOR NOR method EXOR XOR A B end record cell EXNOR is record class combi in A B out XNO NAN area 3 fan_in 4 351404 4 28 57 69 delay fan_out_factor max_fan_out function hilo order end record 5 717 928 4 4 1 1 8 A B XNO NAN cell INV2 is record replaced combi by unkonwn to avoid use of lucas synthesis level because it is used when only one input connected class combi class unknown in A B out AN BN area 1 fan in 1 1 delay 3 3 fan out factor lt 1 1 fan out 8 function A B hilo_order A AN B BN end record cell INVS is record replaced combi by unknown to avoid use at lucas synthesis level because it is used when only one input connected class cimbi class unknown in out AN OUT area 1 fan_in 1 delay 4 5 fan out factor 1 1 max fan out 8 function 7 hilo_order AIN AN OUT end record cell INVP is record replaced combi by unknown to avoid use at lucas synthesis level because it
53. E INVI INVI NOR lt I gt IS IN OUT B BEGIN IF Z 1 1 A B 2 THEN B END IF END RULE INV1_SUPP2_GEN lt 3 gt IS 351404 Ath 48 77 5 717 928 109 SUPPLY One SUPPLYO Zero OUT A One GENERIC OUT Zero BEGIN IF A INVI Zero THEN A One END IF END RULE INVI INV2 6 IS TN A B OUT NA NB BEGIN IF NA INVI A NB THEN NA NB INV2 A END IF END RULE INV1_INV1 lt 8 gt IS IN TAS OUT B BEGIN IF Z INVI A B THEN B A END IF END RULE NAND22_NAND2_GEN3 8 IS IN ALB OUT C D GENERIC OUT A B BEGIN IF NAND2 D NAND2 2 NAND2 A C 2 D 2 END IF END 351404 110 INVI INVI 2 77 5 717 928 111 112 RULE NAND2_NOR2_GEN lt 8 gt IS IN A B OUT GENERIC OUT GEN BEGIN IF 7 INVI GEN NAND2 Z INVI GEN THEN Z INVI NOR2 A Z GEN INVI C END IF END RULE NANDI3 MACROI 6 IS IN A B C E OUT NAN EN BEGIN IF NAN NAND3 A C EN INVI THEN NAN EN NANDI3 A B C E END IF END RULE NAND3 INVI IN3 lt 8 gt IS IN OUT D BEGIN JF NA A NB INVI NC INVI D NAND3 NB NC THEN 2 NOR3 A D INVI 2 END IF
54. END RULE NOR2 INVI 11 8 IS IN OUT BEGIN IF 21 INVI Z2 INVI NOR2 Z1 Z2 THEN 351404 MR 5977 5 717 928 113 114 Z1 NAND2 A INVI 21 END IF END RULE NOR2 NAND2 GEN 8 IS IN OUT 2C GENERIC OUT GEN BEGIN IF 2 INVI A GEN NOR2 Z B INV 2 INV NAND2 Z GEN INVI END IF END RULE NORI3 MACRO lt 6 gt IS IN A B C E OUT NOR EN BEGIN IF NOR NOR3 A B EN INVI E THEN NOR EN NORI3 B C END IF END rule REM gt lt is in E out OUTI begin if OUTI MUXI A B E then NE INVI E NOUTI AOI2W22 A E B NE 0711 INVI NOUTI end if end rule OR2 EXPAND2 gt 1 lt is IN A B OUT D begin 351404 th 150 5 717 928 115 116 if D OR2 A then C NOR D INVI end if end rule OR2 INVI 8 is IN OUT begin if E INVI Z A C INVI Z then Z INVI C NAND2 Z B end end rule OR3 EXPAND gt 1 lt is IN A B E OUT D begin if D OR3 A B E then NOR3 B D INVI end if end 351404 pH 2 5 717 928 117 118 Appendix A 6 the NET File Matra Design Semiconductor
55. FRS is record in J K CK R S SC MO out 0 03 class seq area 9 fan_in 1 1 3 2 2 1 1 delay 8 10 fan out factor 2 1 max fan out 8 function MO SC MO U K CK R S MO SC MO J K CK R S hilo order J K CK R S Q QN SC MO method SCANJKFFRS Q QN J K CK R S SC MO end record cell SCANJKFFS is record in J K CK S SC MO out 9 0 class seq area 8 fan in 1 1 3 2 1 1 delay 9 12 fan out factor 1 1 max fan out 8 function MO SC MO J K CK S MO SC MO J K CK S hilo_order J K CK S Q QN SC MO method SCANJKFFS Q QN J K CK S SC MO end record special cell to implement BUF3STA method must be removed by the expert system and replaced by a BUF3STA with inverter on ENA GASPBUF3STA is record in out XXX class buff area 0 fan_in 1 1 delay 15 fan out factor 17 max fan out 8 function IN ENA hilo_order IN ENA XXX method BUF3STA XXX IN ENA end record special cell to implement BUFIOTTL method must be removed by 351404 5 5 717 928 55 the expert system and replaced by a BUF IOTTL with inverter on ENA GASBUFIOTTL is record 56 in IN ENA out XXX OUT class buff area 0 fan_in 21 1 delay 15 8 fan out factor 17 1 max fan
56. INS PINS PIN7 PINS PINS 10 11 PIN1 SUPPLYO SZERO SUPPLY SONE OUT SZERO SONE 18 PIN19 PIN16 PIN20 PIN15 PIN21 21117 PIN22 PIN23 PIN14 BEGIN GN13PD N13PD BUFINTTL PIN13 GNIIPD N11PD BUFINTTL GN10PD N10PD BUFINTTL PIN10 GN9PD N9PD BUFINTIL PIN9 GN8PD NSPD BUFINTIL GN7PD N7PD BUFINTTL 7 GN6PD N6PD BUFINTTL PIN6 GNSPD NSPD BUFINTTL PINS GN4PD N4PD BUFINTIL PIN4 GN3PD N3PD BUFINTIL PIN3 GN2PD N2PD BUFINTTL PIN2 GZ1271 21271 INVP 21301 GZ1281 21281 INVP 21301 GZ1291 21291 INVP 21301 GZ1301 21301 INVP NIPD 351404 5 717 928 121 122 GNIPD BUFINTTL PIN1 GZ1311 Z1311 INVP 21401 GZ1011 PIN21 BO3N4 71381 71021 GZ1021 21021 21233 21031 621321 21321 21322 DFFRNI 27112 21291 71311 GZ1001 PIN22 BO3N4 21331 21021 GZ951 Z951 AOI2W22 21331 21211 N3PD 71113 GZ1331 21331 21332 DFFRNI 2972 21271 21391 GZ971 Z971 Z972 NANDI3 N8PD 21233 21112 7951 021341 21341 21342 DFFRNI 21091 21271 21311 021091 21091 21092 21093 ANDI2 21322 7112 71021 971101 PIN15 21342 ZINN GZI 21 2112 2113 ORI2 N7PD Ni3PD 21211 621121 PIN14 BO3N4 71032 21192 GZ1131 PIN17 BO3N4 Z1021 Z1192 GZ1141 PIN16
57. INTTL TTL 1 45 4 5 1 BUFINTDN PD TTL I 45 9 1 BUFINTUP PU TTL 1 9 4 5 1 BUFIONT ON TTL Uo 9 9 6 6 1 7 BIONTN2 ON TIL I O 9 9 12 12 17 BIONTN3 ON TTL 9 9 18 18 1 7 BIONTN4 ON TIL IO 9 9 24 24 17 BUFIOTTL TTL WO 9 9 6 6 1 7 BIOTN2 TTL VO 9 9 12 12 1 7 BIOTN3 TTL I O 9 9 18 18 1 7 BIOTN4 TTL VO 9 9 24 24 1 7 BUFOUT 0 6 6 7 BON2 0 12 12 7 BON3 18 18 7 BON4 O 24 24 7 BUFINCUP I 9 45 1 351404 95 26 203 BUFINCDN PD BUFINMOS BUFIOTUP PU BIOTUPN2 PU BIOTUPN3 PU BIOTUPN4 PU BUFPOR BUFIOCUP PU BIOCUPN2 PU BIOCUPN3 PU BIOCUPN4 PU BUFIODIR BIODN2 PD BIODN3 PD BIODN4 PD BUFIODUP PU BIODUPN2 PU BIODUPN3 PU BIODUPN4 PU BUFIOMOS BIOMN2 BIOMN3 BIOMN4 BUFIONC ON BIONCN2 ON BIONCN3 ON BIONCN4 ON BUFIOND ON BIONDN2 ON BIONDN3 ON BIONDN4 ON BUFOUTN ON BONN2 ON BONN3 ON BONN4 ON BIT 2 24 351404 TIL WO TIL IO TIL IO TIL WO VO VO VO VO IO VO yo 10 Uo LO WO VO VO IO Uo VO Uo Lo VO VO yo VO 1 5 717 928 45 9 4 5 4 5 9 9 9 9 9 9 9 9 9999 9999090909090090909099909 99 xO XO 0 ND D 0 o G O XO O0 O O0 O O O O LI LI 4 5 45 6 12 18 24 12 18 24 12 18 24 12 18 24 12 18 24 12 18 24 12 18 24 12 18 24 24 6 12 18 24 12 18 24 12 18 24 12
58. N2PD GZ1271 IN Z1301 INN Z1271 621281 IN Z1301 INN Z1281 GZ1291 IN Z1301 INN Z1291 GZ1301 IN NIPD INN Z1301 GNIPD OUT NIPD GZ1311 IN Z1401 INN Z1311 621011 IN Z1381 ENA Z1021 GZ1021 A 71233 B Z1031 NAN Z1021 GZ1321 D Z1112 CK Z1291 RN Z1311 QN Z1322 GZ1001 IN Z1331 ENA Z 1021 GZ951 A Z1331 B Z1211 C N3PD D Z1113 0UT Z951 GZ1331 D Z972 CK Z1271 RN Z1391 Q Z1331 QN Z1332 GZ971 A N8PD B Z1233 C Z1112 NAN Z971 E Z951 EN Z972 GZ1341 D Z1091 CK Z1271 RN Z1311 Q Z1341 QN Z1342 GZ1091 A Z1322 B Z1112 AND Z1091 E Z1021 EN Z1093 GZ1101 IN Z1342 ENA Z1111 GZ1111 A N7PD B N13PD OR Z1111 NOR Z1112 E Z1211 EN Z1 113 97121 IN Z1032 ENA ZI1192 0011 7IN ZIO21 ENA Z1192 2141 IN Z1322 ENA Z1192 00161 IN Z971 ENA Z1192 001 IN Z1351 ENA Z1192 GZ1351 D Z1191 CK Z1281 RN Z1391 Q Z1351 GZ1191 A Z1201 AN Z1191 B N11PD BN Z1192 GZ1201 A Z1351 B Z1211 C N2PD D Z1113 0UT Z1201 GZ1211 A Z1341 B N9PD C Z1031 NAN Z1211 GZ1031 A NI3PD B N7PD C N8PD NOR ZIO31 E N14MX EN Z1032 GNI4MX A N6PD B Z1332 C Z1382 D Z1362 0UT N14MX GZ1041 IN Z1361 ENA Z1021 GZ1361 D ZIO72 CK Z1291 RN Z1391 Q Z1361 QN 71362 071151 IN Z1372 ENA Z1192 GNN19MX A NSPD B Z1371 C ZI021 OUT NN19MX GZ1371 D ZIO71 CK Z1291 RN 21311 Q Z1371 QN Z1372 GZ1071 A NN19MX AN ZI071 B Z1081 BN Z1072 GZ1081 A Z1371 B Z1093 C N5PD NOR ZIOS1 E Z981 EN Z1082 GZ981 A Z1381 B Z1211 C N4PD D Z1113 0UT Z981 GZ1381 D ZIO82 CK Z1271 RN Z1391 Q Z138
59. OR4 is record class combi in A B C D out NOR area 2 fan_in 1 1 1 1 delay 11 fan out factor 3 max fan out 8 function 0 hilo_order A B C D NOR end record cell NORS is record class combi 351404 24 53 5 717 928 61 62 in A B C D E out OR NOR area 4 fan_in 1 1 1 1 1 delay 14 14 fan out factor 1 1 max fan out 8 function hilo order A B C D E end record cell NORS is record class combi in A B C D E F G HE out NOR area 6 fan_in 1 1 1 1 1 1 1 1 delay 15 fan out factor l max fan out 8 function A B C D E F G H hilo order A B C D E F G H NOR end record cell NORI3 is record replaced combi by unknown to avoid use at lucas syntesis level because it is used when only three inputs connected class combi class unknown in out NOR EN area 2 fan_in 1 1 1 1 delay 4 3 fan out factor lt 3 1 max fan out 8 function A B C E hilo_order A B C NOR E EN end record cell AND2 is record class combi in A B out AND NAN area 2 fan_in 1 1 delay 5 5 fan out factor 1 1 max fan out 8 function A B A B hilo_order A B AND NAN 351404 Ath 25 54 5 717 928 63 method AND AND
60. R POWER END METHOD METHOD IS IN E OUT ASK NE E END METHOD METHOD MUX IS IN 11 12 CTRL OUT O ASK D CTRL END METHOD METHOD IS IN I1 12 13 14 CTRL2 OUT O ASK O 12 13 14 CTRLI CTRL2 END METHOD METHOD AND IS IN I 12 OUT O ASK 11 12 END METHOD METHOD NAND IS IN I1 12 OUT 0 ASK O I1 I2 END METHOD METHOD OR IS IN 12 OUT O ASK 11 12 END METHOD METHOD NOR IS IN I1 12 OUT 0 ASK 0 I1 12 END METHOD 351404 4 5 717 928 35 METHOD EXOR IS IN 11 12 OUT ASK 11 12 END METHOD METHOD DFF IS IN D CLE OUT ASK Q D CLK END METHOD METHOD SCANDFF IS IN D CLK SCAN MODE OUT Q NQ ASK Q D CLK SCAN MODE END METHOD METHOD DFFR IS IN D CLK RAZ OUT Q NQ ASK CLK RAZ END METHOD METHOD SCANDFFR IS IN D CLK RAZ SCAN MODE OUT Q NQ ASK Q NQ D CLK RAZ SCAN MODE END METHOD METHOD DFFNR IS IN D CLK NRAZ OUT Q NQ ASK 0 170 D CLK NRAZ END METHOD METHOD DFFS IS IN D CLK SET OUT Q NQ ASK Q NQ D CLK SET END METHOD METHOD SCANDFFS IS IN D CLK SET SCAN MODE OUT ASK Q NQ D CLK SET SCAN END METHOD 351404 12 4 5 717 928 37 METHOD DFFNS IS IN D CLK NSET OUT Q NQ ASK Q NQ D CLK NSET END METHOD
61. R Q QN end record cell LATCHS is record in D E EN S out Q QN class Seq area 3 fan in 1 1 1 1 delay 5 5 fan out factor 1 2 max fan out 8 function D E S D E S hilo_order D E EN S Q QN end record cell LATCHRN is record in D E EN RN out Q QNT class seq area 3 fan_in 1 1 1 1 delay 5 6 fan out factor 1 1 max fan out 8 function D E RN D E RN hilo order D E EN RN Q QN 351404 4 x 65 351404 81 5 717 928 Appendix A 5 The BAS file Matra Design Semiconductor Inc 1989 wd 55 64 82 83 _ 2 _AB E_MAC2_GEN _ GEN AND3_EXPANDI AND3_EXPAND2 AND3_OUT2 GASPBUF3STA_REMOVE BUF3STA_BO3N4 GASPDFFRS_REMOVE1 GASPDFFRS_REMOVE3 DFFRNSN1_NQ SUPP DFFRNSNI QNQ SUPPI FORK INVI OUT GEN NOR FORK OUT FORK INVI OUT GEN FORK INVI IN OUT GEN FIN DFFRNI QNQ FIN DFFRNI CK Q FIN DFFRN CK FIN DFFRNI RN QNQ FIN_DFFRNI_RN_NQ NOFAN_SUPP1 ID13_MRG_GEN IDI3_F8 IDI4_F8 F2F2 F4 MRG GEN F2F2F2 F6 MRG GEN F6 MRG GEN F8 REMI F8 REM2 IDI1 REM F2 REM F3 REM F6 REM REM REM ASS_DFFRN1_Q GEN ASS DFFRNI Q QN 58 DFFRNI QN GEN ASS DFFRNI QN Q ASS DFFRNI QN Q GEN ASS_DFFRSNi_QN_GEN INVI INVI NOR INVI SUPP2 GEN INVI INV2 INVI INVI NAND22 2 GEN3 351404 5 717
62. RNODCAP EN GND OUT GND POR32 IN GND E ZPORNODCAP EN GND OUT GND POR33 IN GND E ZPORNODCAP EN GND OUT GND POR34 IN GND E ZPORNODCAP EN GND OUT GND ENDC END OF FILE 351404 5 136 223 5 717 928 224 Appendix A 21 the DLY File Matra Design Semiconductor Inc 1989 351404 my 106 25 LOAD DELAY LOAD DELAY LOAD DELAY DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY LOAD DELAY DELAY LOAD DELAY LOAD DELAY DELAY LOAD DELAY DELAY LOAD DELAY DELAY LOAD DELAY LOAD DELAY DELAY DELAY DELAY DELAY DELAY LOAD DELAY DELAY LOAD DELAY LOAD 351404 225 N10PD NIOPD NI3PD NI3PD N13PD N14MX NI4MX NINPWR NINPWR NIPD NIPD N2PD N2PD N3PD N3PD N4PD N4PD NSPD 10 N5PD N6PD N6PD N7PD N7PD N7PD N8PD N8PD N8PD N9PD N9PD N9PD NN19MX NN19MX 21021 71021 21021 21021 21021 21021 21021 71031 71031 71031 21032 71032 21071 GNIOPD GNI IPD GN13PD GNI3PD GNI4MX 9 GNIPD GN2PD GN3PD GN4PD GNSPD GNSPD GN6PD GN7PD GN7PD GN8PD GN8PD GN9PD GN9PD GNN19MX GZ1021 GZ1021 GZ1021 GZ1021 GZ1021 21021 621031 GZ1031 GZ1031 5 717 928 OUT 9021231 OUT 921191 OUT 971031 OUT 14 OUT 971031 AN 921231 OUT 0921301 OUT 921201 OUT 62951 OUT 07981 OUT 071081 OUT GNNI9MX OUT GNI4MX OUT GZ1031 OUT 92111
63. USER MATRA DESIGN NAME SDL PURPOSE SL2000 LAYOUT LEVEL CIRCUIT TYPES NAND2 NANDI3 NAND3 NORI3 ANDI2 ORI2 INVLINTV2 INVP AOI2W22 AODW21 0AIDW22 TGATE DFFRN1 BUFINTTL BO3N4 VDD GND CHIP NAND2 GZ1021 NANDI3 GZ971 NAND3 GZ1211 NORI3 GZ1031 GZ1081 ANDI2 GZ1091 GZ1231 ORI2 GZ1111 INV PORI 9 iNV2 GZ1191 071071 INVP 621271 GZ1281 621291 671301 621311 621391 621401 AOI2W22 GZ951 GZ1201 62981 AODW21 GNN19MX OAIW22 GNI14MX TGATE PORIN POR2 POR3 5 POR6 POR71 PORS POR11 POR12 PORI3 14 POR15 POR16 PORI7 POR18 19 POR20 POR21 POR22 POR23 POR24 POR25 POR26 POR27 POR28 POR29 POR30 POR31 POR32 POR33 POR34 DFFRNI GZ1321 621331 GZ1341 GZ1351 GZ1361 GZ1371 GZ1381 BUFINTTL GNI3PD GNIIPD GN10PD GN9PDr GN8PD GN7PD GN6PD GN5PD GN4PD GN3PD GN2PD GNIPD BO3N4 GZ1011 GZ1001 671101 621121 GZ1131 621141 621161 671171 21041 671151 VDD VDDI 0102 GND GND2 END COMPSEGMENT CHIPI VDDPIN VDD GNDPIN GND VDDI VDDPIN VDDNULI VDD2 VDDPIN VDDNUL2 GNDI GNDPIN GNDNULI GND2 GNDPIN GNDNUL2 A VDD AN PORS GNI3PD OUT NIS3PD GNIIPD OUT NIIPD 351404 wh RS 22 5 717 928 219 220 GN10PD OUT NIOPD GN9PD OUT N9PD GN8PD OUT N8PD GN7PD OUT N7PD GN6PD OUT N6PD GNSPD OUT NSPD GN4PD OUT N4PD GN3PD OUT N3PD GN2PD OUT
64. United States Patent Campmas et al US005717928A 5 717 928 Feb 10 1998 Patent Number 1451 Date of Patent 54 SYSTEM AND A METHOD FOR OBTAINING A MASK PROGRAMMABLE DEVICE USING A LOGIC DESCRIPTION AND A FIELD PROGRAMMABLE DEVICE IMPLEMENTING THE LOGIC DESCRIPTION 75 Inventors Michel J Campmas Palo Alto William A Johnston San Jose Gai Bing Chen Cupertino all of Calif 731 Assignee Matra Hachette SA Paris France 21 Appl No 610 479 22 Filed Nov 7 1990 51 Tat aurai enia GO6F 15 60 52 U S 395 701 395 500 395 185 06 395 183 13 58 Field of Search 395 500 600 395 700 364 578 488 451 452 56 References Cited U S PATENT DOCUMENTS 4 590 581 5 1986 Widdoes Jr 364 578 4 829 427 5 1989 Green 395 600 4 901259 2 1990 Watkins 364 578 4 967 386 10 1990 Maeda et al 5 051 938 9 1991 Hyduke 364 578 5 089 985 2 1992 Chang et al 395 600 5 201 046 4 1993 Goldberg et al 395 600 5 202 889 4 1993 Aharon et al 371 27 5 258 919 11 1993 Yamanouchi et al 364 489 OTHER PUBLICATIONS Dynamic process for generation of biased pseudo random test patterns for the functional verificaiton of hardware designs Aharon et al Apr 1990 Isarael A VLSI Design Verification Strategy
65. ZI111ZZZ0011 11110100111771 1111111101111171 11110111011117111122720011 1111111101111Z11112ZZ0011 111101110111171111272270011 TOGGLE STATISTICS Maximum simulation time 87000 End of simulation time 87000 Total number of internal signals 204 Toggled signals during sequence 95 46 PERCENT 351404 the BS _ 182 351404 183 5 717 928 Appendix A 15 the 1MS File Matra Design Semiconductor Inc 1989 tte 86 gt 184 5 717 928 185 ALL 4TXT RESTORE DEFAULTS units Ins timebase 100ns DEFINE n 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 4200 4400 4600 4800 5000 5200 5400 5600 5800 6000 6200 6400 6600 6800 7000 7200 351404 1111 NNNNNNNNNNNNNNNNNNNNNNNNNNNN 1234567891111112221112221112 0134561234561237890 000000000000ZZZZZZZ1Z00ZZZZ0 000000000000ZZZZZZZ1Z00ZZZZ0 000000000000ZZZZ2721200ZZZZ0 77777 727 11111011111022722221212201112 1111101111007722222272272222 011110111100ZZZZZZZZZZZZZZ2Z 111110111100222222227227727777 1111100111002772222271272272772 0111100111002222222122222222 11111001110022222221222227222 11111000110022222221222227227 011110001100ZZZZZZZ1ZZZZZZZZ 111110001100ZZZZZZZ1ZZZZZZZZ 111110001101ZZZZZZZZZZZZZZZZ 011110001101ZZZZZZZZZZZZZ
66. ZZZ 111110001101ZZZZZZZZZZZZZZ7Z 111110001100ZZZZZZZlZZZZZZZZ 011110001100ZZZZZZZlZZZZZZ77 1111100011002222222122272222 111100000100ZZZZZZ2Z1Z00ZZZZ0 011100000100ZZZZZZZ1Z00ZZZZ0 111100000100ZZZZZZZ1200ZZ22Z0 111100000110ZZZZZZ1110000110 01 1 1000001 LOZZZZZZ1 110000110 1111000001102722221110000110 111100001110ZZZZZZ111Z220111Z 011100001110ZZZZZZ111ZZ0111Z 111100001110ZZZZZZ111ZZ0111Z 011100001110ZZZZZZ111ZZ0111Z 111100001110ZZZZZZ111ZZ0111Z 0111000011102222221112201112 1111000011102ZZZZZ111ZZ0111Z 111100001111ZZZZZZIZ1ZZ0111Z 111101111111222722712717201112 011101111111ZZZZZZIZIZZO111Z 1111011111112222221717201112 BT 76 186 7400 7600 7800 8000 8200 8400 8600 8600 5 717 928 187 1111 11111112272 011111111111227222217127201112 1111111111112722271717201112 1111011111112222771712201112 011101111111222227217127701112 21111011111112222722127127201112 727 7 1 2 1111 CVT END 351404 188 lt 351404 189 5 717 928 Appendix A 16 the NPI File Matra Design Semiconductor Inc 1989 Aih 190 191 EVAL ARRAY PROBE CARD POR MASK NO ADD_STATIC ua IDD_DYNAMIC ma REVISION PACKAGE TG LIST 10 10 TG2 12 10 TG3 TG4 5 TG6 20 10 TG8 TR 100 PINLIST Signal Pad Pin Test Pad kkk eet PIN9 1 9 1 PINIO 2 10 2 11 3 1
67. al Creation Rev 0 02 09 23 87 P Treen Modified to adhere to naming standard Rev A 11 30 87 P Treen D Formal Release Device Type eval device P22V10 Input Pins clk25 _ pinl inverted 25MHZ clock db00 pin2 buffered data bit 0 dbo 3 buffered data bit 1 db02 pin4 buffered data bit 2 vsync pin5 vertical sync bit sccint _ pin6 SCC chip interupt hweyc_ pin 7 decode of CS register ba02 pin8 buffered address bit 2 selects stat or cntl reg rd_ pin 9 read low active res_ 10 system reset ate_ 11 tristate enable disable for ate ba04 pin 13 buffered address bit 4 lo to select hwcyc Output Pins 351404 5 717 928 17 18 vidon pin 23 pos reg feed_reg video enable sien 22 pos reg feed sccint mask vien pin 21 pos reg feed_reg vsync int mask vi pin 20 pos reg feed latched vsync vihld_ pin 19 neg reg feed_reg int sig holds vi cycntl_ pin 16 neg reg feed_reg int sig to gen done csdone_ pin 15 neg reg done to gen ready rdstat_ pin 18 neg com status reg buff enable _ 17 neg com control reg buff enable intenb_ pin 14 neg com interupt buff enable Internal Nodes ASYNC_RESET node 25 Constant Declarations data db02 db01 db00 H L X C Z 1 0 X C 2 5 out rdstat_ rdentl_ intenb_ vihid_ vidon cyentl_ EQUATIONS ASYNC_RESET
68. at ingroupl NRZ Resource ingroup2 Force TXT 1 B7 PINS 9 1 B6 PIN10 10 1 B5 PINII 11 1 B4 PIN13 13 Resource End Radix ingroup2 Bin Polarity ingroup2 Pos Hidrive ingroup2 5 00V Lodrive ingroup2 0V Format ingroup2 NRZ 3 1404 Mae 37 209 Resource ingroup3 Force 7 2 3 PINIA 14 Resource End Radix ingroup3 Bin Polarity ingroup3 Pos Hidrive ingroup3 5 00V Lodrive ingroup3 0V Format ingroup3 NRZ Resource ingroup4 Force TXT 283 PIN15 15 Resource End Radix ingroup4 Bin Polarity ingroup4 Pos Hidrive ingroup4 5 00V Lodrive ingroup4 0V Format ingroup4 NRZ Resource ingroup5 Force TXT 3 A3 PINI6 16 Resource End Radix ingroup5 Bin Polarity zngroup5 Pos Hidrive ingroup5 5 00V Lodrive ingroup5 0V Format ingroup5 NRZ Resource ingroup6 Force 3 83 PIN21 21 Resource End Radix ingroup6 Bin Polarity zngroup6 Pos Hidrive ingroup6 5 00V Lodrive ingroup6 0V Format ingroup6 NRZ Resource ingroup7 Force TXT 4 PIN22 22 Resource End Radix ingroup7 Bin Polarity ingroup7 Pos Hidrive ingroup7 5 00V Lodrive ingroup7 0V Format ingroup7 NRZ Resource Ingroup8 Force TXT 4 B3 PIN23 23 Resource End Radix ingroup8 Bin Polarity Ingroup8 Pos Hidrive ingroup8 5 00V Lodrive ingroup8 0V Format ingroup8 NRZ 351404 5 717 928 99 25 210 211 Resource outgroup8 Compare 6 PINI4 14 Resource End Radix outgroupl Bin Polarity outgroupl Pos Threshold outgroup171
69. aults spotted TG End problem SPOT FAULTS Failed to reach fault limit of 1 TG TG End PLD PAL TG Test Generator Fault analysis starting time 8 45 secs Using a value of 50 for Max_backtracks There are 7 active faults 7 faults left 0 undetectable faults dropped Fault Analysis Summary Detectable Faults 17 Possibly Detectable 0 Asynchronous Loops 0 Undetectable Faults 3 Test Generator Fault analysis ended took 0 35 secs total 8 80 secs Finish simulation took 4 57 secs total 8 80 secs Simulator finished took 0 01 secs total 8 81 secs Written Fault Dictionary took 0 05 secs total 8 86 secs 351404 V 34 5 717 928 161 Fault Dictionary Summary all faults fault total dropd pdetd catas total Stuck0 78 76 75 1 0 65 Stuckl 78 65 63 3 0 46 All 156 141 138 4 0 111 s 928 908 2 6 0 0 s are of detectable faults only Decompiling waveform produced into eval tgo DWL Decompiler Decompiling knowledge data base to eval kbo Command on SIMULATOR page selected 351404 p 75 162 simulated faults dropd 64 37 101 93 5 det d 63 36 99 91 7 pdetd 1 2 3 2 8 5 7
70. aults were found that could be detected in the current state of the circuit TG NO faults spotted TG Applying RAPS to combinational area Default TG End problem SPOT FAULTS TG TG Task PAL repeated 351404 44 73 02 5 717 928 159 160 Dynamic problem inserted Name Spot_Faults Use Current State NO Raps NO Max backtracks 5 Overwriting value of USE CURRENT STATE in frame SPOT FAULTS Overwriting value of RAPS in frame SPOT FAULTS Overwriting value of MAX BACKTRACKS in frame SPOT FAULTS TG Problem SPOT FAULTS TG Constraint PIN X TG Constraint PIN13 X TG Working in Combinational Area Default TG Trying to catch stuck at 0 on Z1371 TG Trying to catch 1 fault TG End problem SPOT FAULTS At time 71700 number of active faults is 7 TG gt TG Task PAL repeated Dynamic problem inserted Name Spot_Faults Use_Current_State NO Raps NO Max_backtracks 5 Overwriting value of USE CURRENT STATE in frame SPOT FAULTS Overwriting value of RAPS in frame SPOT FAULTS Overwriting value of MAX BACKTRACKS in frame SPOT FAULTS TG Problem SPOT FAULTS TG Constraint PIN X TG Constraint PIN13 X Spot faults was specified for problem SPOT FAULTS but no faults were found that could be detected in the current state of the circuit TG No f
71. egin for the building a mask programmable circuit which performs the functions described in the logic description 8 Claims 8 Drawing Sheets U S Patent Feb 10 1998 Sheet 1 of 8 TIMING amp LOGIC VERIFICATION YES LAYOUT GENERATION POST LAYOUT SIMULATON TIMING amp LOGIC VERIFICATION FIG 1 YES MANUFACTURE MASKS 5 717 928 5 717 928 Sheet 2 of 8 Feb 10 1998 U S Patent wre 912 60 SW NolsdaANoo 102 XXXOLNV 01 8 03 31600 SWI NS 3 NnS HO Od TWNOLLONN STIS NOISH3ANOO 313 SNI 9NISS300dd Nid NNS Od 00 38 d 1931 IH OHVEOTIH NNS 0 155 Old OL 1387 5 NAS 3 07131 13901 9d NOISHSANOO 314 ON YSWOLSND SWI ONISN NOLLVOIdIH3A 83 00 0023 102 Od LINVS ANY Od LV INOISH3ANOO LSTLLIN 602 h 5 717 928 Sheet 3 of 8 Feb 10 1998 U S Patent 915 2 91 5 01 AY 5 717 928 Sheet 4 of 8 Feb 10 1998
72. ell GASPDFFS is record in D CK S out 10 03 class seq put same area than DFFSNI used for synthesis area 6 fan_in 1 1 11 delay 0 0 351404 4 7 5 717 928 49 50 fan out factor 0 0 max fan out 8 function D CK S D CK S hilo_order D CK S Q QN method GASPDFFS Q D CK S DFFS Q QN D CK S end record cell SCANDFF is record in D CK SC MO out class seq area 4 fan_in 1 2 1 1 delay 5 5 fan out factor 5 1 1 max fan out 8 function MO SC MO D CK MO SC MO D CK hilo_order D CK Q QN SC MO method SCANDFF Q QN D CK SC MO end record cell SCANDFFR is record in D CK R SC MO out Q ON class seg area 5 fan_in 1 2 2 1 1 delay 6 8 fan out factor 5 2 1 max fan out 8 function MO SC MO D CK R MO SC MO D CK R hilo order D CK R Q QN SC MO method SCANDFFR Q QN D CK R SC MO end record cell SCANDFFS is record in D CK S SC MO out Q ON class seq area 5 fan_in 1 2 2 1 1 delay 10 6 fan out factor 1 2 max fan out 8 function MO SC MO D CK S MO SC MO D CK S hilo_order D CK S Q QN SC MO method SCANDFFS Q QN D CK S SC MO end record special cell to implement GASPDFFRS method must be removed by the expert system and replaced by a DFFRNSN1 with inverter on RAZ amp
73. endix A 1 requires only devices listed in Table I Additional logic devices are described in GATELIB Macrocell and Macro Function Libraries pub lished by Matra Design Semiconductor Inc of Santa Clara Calif in 1987 As can be seen the NET file includes a circuit element POR used for a power on reset of output register flip flops in the output circuitry of the 22V 10 For simulation purpose POR can be modeled as a delay line As implemented in this embodiment POR is a circuit with a large capacitance Part of the software represented by block 202 includes a conversion program which receives the NET file and gen erates therefrom a file CCT Appendix A 7 As can be seen from a cursory examination of the NET and CCT files from Appendices A 6 and A 7 respectively this conversion soft ware merely rearranges in a manner readily apparent the positions of the gate names types and signal names on each line After the CCT file has been prepared it is necessary to generate test vectors which can be used to test a sample PLD provided by the customer As is well known in the art test vectors which are often expressed in table form are stimu lus input signals provided to a circuit and the expected circuit output signals responding to the input signals A program known as SYSTEM HILO block 204 is used to generate test vectors from the netlist SYSTEM HILO is available from Genrad Limited of Fareham U K A test pattern generatio
74. extension SDL An example of the SDL file is attached hereto as Appendix A 20 The SDL format is described in SDL The Structured Design Language Reference Manual published in Jul 1984 Document No M 037 2 available from Silvar Lisco is hereby incorporated by reference in its entirety Of course if another vendor s layout generation software is used in place of GARDS a conversion program to convert the IN file to the layout generation software s accepted format may be needed GARDS also uses the PAD file Appendix A 17 which contains pin out information The GARDS system is provided with the design rules and the designations of the mask layers The design rules and mask layer designations are specific to the ASIC vendor s intended manufacturing process The GARDS system also allows manual intervention in the place and route process to allow the layout designer to manually provide placement and routing to suit specific needs The output of the place ment and routing process is provided in a file identified by file extension SLGDS which is in the CALMA stream format well known in the art The SLGDS file contains only cell placement and routing information As described below in order to generate the actual mask data the physical layouts of the cells and array will be merged after timing verification according to the placement and routing infor mation A software program is provided to extract parasitic impedances from the
75. fan_in 1 1 delay 5 5 fan out factor 1 1 max fan out 8 function A B A B hilo_order A B OR NOR method OR OR A B end record cell OR3 is record class combi in A B C out OR NOR area 2 fan_in 1 1 1 delay 6 6 fan out factor 1 1 max fan out 8 function AtBt C A B C hilo_order A B C OR NOR end record cell is record class combi in A B C D out OR NOR area 3 fan_in 1 1 1 1 delay 9 9 fan out factor 1 1 max out 8 function A B C D A B C D hilo_order A B C D OR NOR end record cell ORI2 is record replaced combi by unknown to avoid use at lucas synthesis level 351404 3 5C 5 717 928 67 because it is used when only two inputs connected class combi class unkonwn in out OR NOR EN area fan_in 1 1 1 delay 5 5 3 fan out factor 1 1 1 max fan out 8 function A B A B E hilo_order A B OR NOR E EN method OR OR A B end record cell ORI4 is record replaced combi by unknown to avoid use at lucas synthesis level because it is used when only four inputs connected class combi class unknown in A B C D E out OR NOR EN area 3 fan_in 1 1 1 1 1 delay 9 9 3 fan out factor 1 1 1 max fan out 8 function A B C D A B
76. in contribution e g an equation is logicallhy Ored with the Eqn Node OE No default is set to OE it will be done automatically by the linker using the following ruless If Mode pin In Then OE 0 1f Mode Pin Out Then OE 1 f Mode IN Tri In Tri Out Tri In Out Then OE User Defined If Mode Not defined Then OE 1 Notice that Feed connection is defined in a way that is consistent with output polarity when mode is Feeda Reg e g Output and Feed signals have the same polarity It has to be done even if the wiring is slightly different from those one of the data bood because Feed Reg is a buried signal those it s not directly controlable by the user 351404 27 5 717 928 29 X 24 VCC Preset and reset signals 25 26 Node Attributes Pos Fixed Default 0 y 27 36 Node 100 PIN Name SCANIN In Feed Eqn PD Attributes Pos FIXED Netlist BUFINTTL IN PD y 101 PIN SCANMODE In Feed Eqn PD Attributes Pos FIXED Netlist BUFINTTL IN PD y 102 PIN Name SCANOUT Out Attributes Pos FIXED MX Default 0 Netlist BUFOUT OUT MX END PLD 351404 4 g 3 351404 31 5 717 928 Appendix A 3 the File Matra Design Semiconductor Inc 1989 31 32 5 717 928 33 METHOD FOR IS IN POWER OUT POR ASK PO
77. is to be used a similar software program may be needed to provide the tester interface The techniques used to convert the information contained in the NP1 file to the accepted format of each tester is known in the art The IMS tester requires a second file IMS which contains test vectors This is provided by the translation software of block 216 which receives the input and output waveforms from the ARCIS simulation and the PIN file from NPITOSET and generates therefrom an output file identi fied by the file name extension SIM which is acceptable as an input file by the IMS tester An example of IMS file is attached hereto as Appendix A 15 This IMS file will provide to the tester the input waveforms to apply to the PLD under test and the expected output waveforms which the tester uses to verify the functional correctness of the GASP generated logic circuit by comparing the expected output waveforms with the actual output waveforms of the PLD device Based on the input stimulus waveforms provided in the IMS file and configuration information from the SET and PIN files the tester applies the stimulus waveforms to the pins of the PLD provided by the customer The response of the PLD is compared against the expected output waveforms in the IMS file This step is known as functional verification If the logic circuit provided by GASP is an acceptable replacement for the PLD device using a set of test vectors with a high level of fault c
78. ive faults is 13 TG End problem SPOT FAULTS TG TG Task PAL repeated TG Dynamic problem inserted Name Spot_Faults Use_Current_State NO Raps NO Max_backtracks 5 Overwriting value of USE CURRENT STATE in frame SPOT FAULTS Overwriting value of RAPS in frame SPOT FAULTS Overwriting value of MAX BACKTRACKS in frame SPOT FAULTS TG Problen SPOT FAULTS TG Constraint PIN1 X TG Constraint PIN13 X TG Working in Combinational Area Default TG Trying to catch stuck at 0 on Z1081 TG Trying to catch 1 fault TG End_problem SPOT FAULTS Failed to reach my fault limit of 1 TG TG End_PLD PAL TG Test Generator Fault analysis starting time 7 33 secs Using a value of 50 for Max_backtracks There are 13 active faults 10 faults left 3 undetectable faults dropped Fault Analysis Summary 351404 72 5 717 928 157 158 Detectable Faults 10 Possibly Detectable 0 Asynchronous Loops 0 Undetectable Faults 3 Test Generator
79. le device and iii compares said expected output signals with said output signals from said sample device 2 A system as in claim 1 further comprising means coupled to said means for generating a computer model and said means for testing said sample device for generating a physical circuit layout from said computer model when said expected output signals and said output signals from said sample device are compared to be substantially equal in said means for testing 3 A system as in claim 1 wherein said means for generating a computer model comprises an expert system 10 15 236 4 A system as in claim 1 wherein said means for generating a test program further comprises means for simulating faults 5 A process for creating a factory programmed device using a sample device and a logic description of said sample device comprising the steps of generating from said logic description a computer model of a logic circuit generating a test program from said computer model said test program including data representing stimulus sig nals for testing said sample device and expected output signals of said sample device when said stimulus signals are applied to said sample device applying said stimulus signals to said sample device in accordance with said test program to obtain output signals of said sample device and comparing said output signals with said expected output signals 6 A process as in claim 5 further comp
80. mbi in A B C D out OUT area 2 1 1 1 1 delay 5 fan out factor 2 max fan out function 6 0 8 hilo_order A B C D OUT end record cell OAI2W21 is record class combi in A B C out OUT area 2 fan_in 1 1 1 delay 3 fan out factor 2 max fan out 8 6 55 4 5 717 928 77 78 function 8 0 hilo order A B C OUT end record cell AOAI2W2 is record class combi in A B C D out OUT area 2 fan_in 1 1 1 1 delay 6 fan out factor 2 max fan out 8 function 0 hilo_order A B C D OUT end record cell AOAI2W22 is record class combi in A B C D out OUT area gt fan_in 1 1 1 1 delay 7 fan out factor 2 max fan out 8 function A B C D hilo_order A B C D OUT end record cell LATCH is record in D E EN out Q QN class seq area 2 fan_in 1 1 1 delay 6 5 fan out factor 5 1 1 max fan out D E CD E hilo_order D E EN Q QN end record cell LATCHR is record in out 0 00 class seq area 3 fan_in 1 1 1 1 delay 6 9 fan factor 2 1 max fan out 8 351404 m 62 5 717 928 79 function D E D E R hilo_order D E EN
81. me 1700 number of active faults is 78 Running PLD PAL with 78 active faults TG TG PLD PAL t Dynamic problem inserted Name Spot Faults Use Current State Yes Raps YES Max_backtracks 5 Overwriting value of USE CURRENT STATE in frame SPOT FAULTS Overwriting value of RAPT in frame SPOT FAULTS Overwriting value of MAX BACKTRACKS in frame SPOT FAULTS TG Problem SPOT FAULTS TG Constraint PIN X TG Constraint PIN13 X TG Working in Combinational Area Default TG Trying to catch stuck at 0 on Trying to catch stuck at 0 on 71071 TG Trying to catch 2 faults TG Applying RAPS to combinational area Default TG End problem SPOT FAULTS Attime 2700 number of active faults is 63 Attime 5700 number of active faults is 47 TG Task PAL repeated TG Dynamic problem inserted Name Spot_Faults Use_Current_State YES Raps YES Max_backtracks 5 Overwriting value of USE_CURRENT_STATE in frame SPOT_FAULTS 351404 69 99 5 717 928 151 152 Overwriting value of RAPS in
82. move from state 0000110 to 11X1101 Searching state machine PAL Input Wires Old State New State PPPPPPPPPPPP 7777777 7777777 1111111111 1111111 1911111 NNNNNNNNNNNN 3333333 1701000 111987654321 2345678 1299778 310 2111111 211212 0XX000XOXXXX 01 1101 1 0111XXI OXXXXOXXXXXX 1 0111 1 OXXIO0XX111X 101XXXX 0 1 71 1101 351404 30 5 717 928 153 154 OXX100XX111X 01 OXX100XX111X X0IXXXX OLXIXX1 XXXXXXXXXXXX K101XX1 OXXIOOXXXIXX 011XXXX OXX100XXXIXX IOIXXXX OLIXXXX OXXXXOXXXXXX OLLXXXX OXXXXOXXXXXX 1000110 00101 0 TG transition from State 0000110 to State 01 TG transition from State X01 XXXX to State XIXIXXI TG transition from State XIX1XXI1 to State 0101 XX1 TG transition from State 0101 XX1 to State X11IXXI TG transition from State X111 XX1 to State 11 X1101 At time 12700 number of active faults is 46 At time 15700 number of active faults is 42 Attime 17700 number of active faults is 40 Attime 20700 number of active faults is 39 At time 22700 number of active faults is 38 At time 32700 number of active faults is 24 TG End problem SPOT FAULTS At time 37700 number of active faults is 16 At time 40700 number of active faults is 15 TG e TG Task PAL repeated TG aF Dynamic problem inserted Name Spot_Faults Use_Cu
83. mulation run on 10 OCT 90 at time 12 36 48 Running the HITEST test generator Running the HIFAULT simulator Loading the default version of circuit EVAL time 0 50 secs WARNING delay cell evaluated to ZERO on REGISTER GZ1321 Q1 Q1 Q1 from rise fall delays 0 0 0 0 0 0 0 0 its delay cell will be defaulted to UNIT WARNING delay cell evaluated to ZERO on REGISTER 021331 Q1 Q1 Q1 from rise fall delays 0 0 0 0 0 0 0 0 its delay cell will be defaulted to UNIT WARNING delay cell evaluated to ZERO on REGISTER GZi 341 01 01 01 from rise fall delays 0 0 0 0 0 0 0 0 its delay cell will be defaulted to UNIT WARNING delay cell evaluated to ZERO on REGISTER GZ1351 Q1 Q1 Q1 from rise fall delays 0 0 0 0 0 0 0 0 its delay cell will be defaulted to UNIT WARNING delay cell evaluated to ZERO on REGISTER GZ1361 Q1 Q1 401 from rise fall delays 0 0 0 0 0 0 0 0 its delay cell will be defaulted to UNIT WARNING delay cell evaluated to ZERO on REGISTER GZ1371 Q1 Q1 Q1 from rise fall delays 0 0 0 0 0 0 0 0 its delay cell will be defaulted to UNIT WARNING delay cell evaluated to ZERO on REGISTER 021381 01 01 01 from rise fall delays 0 0 0 0 0 0 0 0 its delay cell will be defaulted to UNIT Circuit Loading Complete took 1 33 secs time 1 83 secs Circuit EVAL has 100 picosecs scaling Number of subcircuit elements loaded 69 size 8784 bytes Number of primitive gates loaded 92 3912 bytes 14 declaration ex
84. n block 201 of FIG 2 For example in one embodiment a program TOABEL represented by block 201 translates PALASM format equations obtained from a file having file name extension PAL to ABEL format and place the output ABEL logic equations in a file having file name extension ABL PALASM is well known in the art and is described in PAL Device Data Book incorporated herein by reference in its entirety above The program TOABEL is well known in the art and is available also from DATA I O Corporation mentioned above TOABEL runs on IBM PC machines and Sun workstations Block 202 shows the ABL file i c ABEL file being provided to an expert system known as GASP for generating a netlist of a logic circuit A script or command file ABEL TO is used to execute the various components of GASP GASP also called GASP LUCAS is a rule based expert system available from Genrad Limited Fareham U K The GASP program takes as input files 1 a file containing the logic description in the ABEL format Appendix A 1 2 a file MPL which models the PLD device type Appendix A 2 3 a methods library file MET Appendix A 3 which describes how logic devices are constructed in the ASIC vendor s circuit technology 4 a MD CEL library Appendix A 4 which lists logic func tions that are available in the ASIC vendor s circuit tech nology and 5 a rule base file RCP compiled from a set of BAS files Appendix A 5
85. n module HITEST and a fault simulator HIFAULT are separately purchased parts of SYS TEM HILO The operation of the HITEST module is described in SYSTEM HILO HITEST Plus Reference Manual which is hereby incorporated by reference in its entirety obtainable from GenRad Incorporated Fareham U K The HIFAULT fault simulator which is described in the HIFAULT Reference Manual hereby incorporated by reference in its entirety is also obtainable from Genrad Incorporated Fareham U K Of course other automatic test pattern generation systems and fault simulators may also be used Appropriate format conversion programs may be needed when another automatic test pattern generation sys 10 35 45 55 60 6 tem or fault simulator is used The SYSTEM HILO program runs on the Sun 3 The HITEST program takes as inputs the CCT netlist file described above a KDB file containing a knowledge base description used in test vector generation and a DWL file containing parameters of input and output waveforms The definition and use of the KDB file is provided in the HITEST Test Generator Reference Manual which is hereby incorporated by reference in its entirety is obtainable from GenRad Fareham Limited Fareham U K The defini tion and use of the DWL file is described in the HITEST DWL Reference Manual which is hereby incorporated by reference in its entirety is obtainable also from GenRad Fareham Limited An example each of
86. nd rule GASPBUF3STA_REMOVE 12 is in inl ena out 1 351404 A 38 67 5 717 928 89 begin if GASPBUF3STA inl ena then nena INVI ena BUF3STA inl nena end if end rule BUF3STA_BO3N4 lt 2 gt is in inl ena out outl begin if 1 BUF3STA inl then outl BO3N4 inl ena end if end rule GASPDFFRS_REMOVEI lt I gt is in d ck s out 4 begin if q nq GASPDFFRS d ck s then rn INVI sn INVI DFFRNSNI d ck rn sn end if end rule GASPDFFRS REMOVES gt 1 lt is in d ck s out begin if GASPDFFRS d ck s then rn INVI r sn INVI s ng DFFRNSNI d ck rn sn end if end rule DFFRNSNI 5 lt 3 gt is in d ck m supplyl 280 nq 351404 6 39 C5 5 717 928 91 92 generic_out sn begin if DFFRNSNI d ck rn sn then DFFRNI d ck m end if end rule 0 1 QNQ SUPPI lt 3 gt is in d ck supplyl sn q ng generic_out sn begin if nq DFFRNSNI d ck rn sn then g nq DFFRNI d ck rn end if end RULE FORK INVI OUT GEN NOR lt I gt IS IN PAS OUT B C GENERIC_OUT GEN BEGIN IF B INVI INVI A GEN THEN 7 INV1 A 2
87. nd item enclosed in parentheses is the name or names of the output signal or signals provided by the gate the third item after the punctuation is the type of logic device represented by the line and the fourth item is the name or names of the input signal or signals Thus for the device described in the first line following BEGIN the gate is labeled GNI3PD its output signal is N13PD it is of device type BUFINTTL a TTL input buffer which receives input signal PIN13 Table I below lists the device types and abbreviations used in the NET file of Appendix A 6 5 717 928 5 TABLE I Device Type Symbol BUFINTIL TIL compatible input buffer INVP Two parallel inverters see Figure 4 BO3N4 Tristate output buffer with 24 mA output drive NAND2 2 input NAND gate AOI2W22 2 wide 2 2 input AND OR INVERT see Figure 5 DFFRNI D Flip Flop See Figure 6 7 3 3 input NAND Gate with an inverter see Figure 7 AOI2W21 2 wide 2 1 input AND OR INVERT see Figure 8 NORI3 3 input NOR gate with an inverter see Figure 9 ORI 2 input OR gate with an inverter see Figure 10 INV2 Two inverters see Figure 11 ANDI2 2 input AND gate with an inverter see Figure 12 NAND3 3 input NAND gate POR Power on reset OAI2W22 2 wide 2 input OR AND OR INVERT see Figure 13 The library of logic devices used with GASP may contain other logic devices However the circuit specified by the ABL file of App
88. oftware pro grams which simulate the operation of the circuit repre sented by the netlist to ensure that the intended logic functions are correctly provided Often at this step propa gation delays exhibited by the logic circuit represented by the netlist are estimated to determine if timing performance targets are met The process of generating an acceptable schematic rep resentation from logic descriptions as illustrated by the 10 15 35 40 45 55 2 mode shown in FIG 1 is not always straight forward For example it is common for a schematic representation to be corrected and resimulated multiple times before arriving at an acceptable final representation At this point as illustrated by decision point 110 the customer typically provides a sign off to the ASIC vendor indicating permission to go ahead to the next step 103 during which the layout of the customized mask is generated layout generation The customer bases his her go ahead decision upon careful perusal of the simulation and verification results Layout generation step 103 requires taking the netlist of the schematic representation to create patterns of geometric shapes on the customized mask layers The customized masks created from these patterns are used in some of the photolithographic steps in the circuit fabrication process These masks are generated according to the design rules of the ASIC vendor s fabrication process and circ
89. on version from a PLD device to a factory programmed device in the prior art FIG 2 is a block diagram showing a first embodiment of a system for converting a PLD device to a factory programmed device in accordance with the present inven tion FIG 3 is a block diagram showing a second embodiment of a system for converting a PLD device to a factory programmed device in accordance with the present inven tion FIGS 4 5 6 7 8 9 10 11 12 and 13 schematically illustrate logic devices used in an example of a program mable logic device being converted to a mask programmable device DETAILED DESCRIPTION In accordance with the present invention a system and a method of designing a factory programmed circuit to replace a PLD are provided using the logic description of the PLD circuit and a functioning PLD device FIG 2 is a block diagram of a first embodiment of the system in accordance with the present invention In accor dance with the present invention the customer needs only provide the ASIC vendor with a logic description and a functioning PLD device in which the logic description is implemented With substantially no further involvement by the customer the ASIC vendor provides the customer a factory programmed circuit suitable for mass production and which is pin for pin compatible with the PLD device In the embodiment shown in FIG 2 block nos 201 to 208 211 to 213 and 216 represent execution of programs on data
90. or accurately converting a PLD to a factory programmed device suitable for mass production Furthermore since the process is highly automated the throughput time from the customer s providing a functional PLD and the logic description thereof to the point when mask layers are synthesized is shortened from a matter of weeks in the prior art to a few days or even a few hours in accordance with 5 717 928 11 the present invention depending upon the complexity of the PLD device The advantages of such savings in time and cost are self evident FIG 3 illustrates a second embodiment of the present invention using a PLD Programmer obtainable from Data 1 0 Corporation This PLD PROGRAMMER is described in USUSERMAN Document No 98100 14008 published Apr 1 1990 by Data I O which is hereby incorporated by reference in its entirety The difference between the first and second embodiments in FIGS 2 and 3 is in the tester used i e IMS vs Data I O For ease of comparison blocks in FIG 3 identical to those in FIG 2 are given the same reference numerals as their counterparts in FIG 2 For the same reason the descriptions of these corresponding blocks are not provided below to avoid repetition Only blocks 308 and 309 which are different implementations of the blocks 208 216 and 209 of FIG 2 are described As shown in FIG 3 a conversion program block 308 operates on the ARCIS output file and the PADPIN output file NP1 f
91. or assembling the tester input file JED which contains not only configuration directives to the tester but also the input stimulus waveforms to be applied to the PLD device and the output waveforms with which to compare the output of the PLD device Block 309 is the Data 7 0 PLD programmer obtainable from Data VO Corp of Beaverton Oreg Other than the differences specifically provided above the operation of the embodiment illustrated in FIG 3 is identical to the embodiment illustrated by FIG 2 The above detailed description is intended to illustrate the specific embodiments of the present invention described above Numerous modifications and variations within the scope of the present invention are possible Some examples 10 15 12 within the scope of the present invention are i the auto matic layout generation software can be any other automati cally layout generation software commercially available ii the tester used in verifying the previously programmed PLD device against the software model can also be any commer cially available tester and iii the various file conversion programs can be any commercially available or other file conversion programs as discussed above The PLD can be a fuse programmable device an antifuse programmable device or a floating gate programmable device The circuit to be a mask programmed substitute for the PLD may be NMOS PMOS CMOS BICMOS bipolar or any other technology The per
92. overage 96 100 the PLD output waveforms and the expected output waveforms pro vided by the circuit simulator ARCIS or equivalent circuit 5 717 928 9 simulator will be the same Otherwise the netlist must be debugged and resimulated Because the synthesized circuit is compared against the actual PLD device using a set of test vectors with a high level of fault coverage 96 100 the accepted synthesized circuit is necessarily an accurate model of the PLD device It can then be inferred that the implementation of this model in the factory programmed device will be a correct substi tute for the PLD device provided the characteristics of this model is preserved through the layout generation process The layout generation process is illustrated by block 211 In this embodiment the layout of the customized mask layer is synthesized by GARDS which is a program commer cially available from Silvar Lisco Corporation Menlo Park Calif Of course other layout generation tools suitable for application specific integrated circuit technologies such as gate arrays may also be used The GARDS system is described in Silvar Lisco GARDS Command Reference Manual Vol 1 Document No M GDS 6 0 C1A Jul 1988 is hereby incorporated by reference in its entirety A software program ARCTOSDL translates the logic netlist provided in the IN file to the SDL format accepted by the GARDS system The SDL Format file is identified by the file
93. plete physical circuit layout discussed above and provide error reports for any design rule violations or circuit mismatch as the case may be For comparing the netlist with the mask data in this embodiment it is necessary to convert the IN netlist file into the LOGIS netlist format acceptable by the LVS system The LOGIS format is obtainable from Cadence Design Systems The technique for such conversion is well known The DRC system also provides resized mask layers adjusted for the intended fabrication process in an output file identified by the file extension SIZED GDS which are expressed in the popular GDS II format It should be noted that the DRC and LVS systems may also be substituted by any other systems providing comparable functionalities Both DRC and LVS systems require libraries which are specific to the circuit technology of the ASIC vendor Techniques for providing such libraries are known in the art Finally the SIZED GDS format is fractured to the input specifications of the mask manufacturing equipment and provided in MEBES output files readable by such equipment block 213 The fracturing techniques are well known in the art and many commercially available pack ages are suitable for this purpose The output files are provided to the mask vendor over a suitable medium Masks are then produced and used to build integrated circuits for delivery to the customer In summary the present invention provides a process f
94. pressions 14 event statements total size 3112 bytes Memory used for symbols and objects by loader 23666 bytes Memory used for simulator structures by loader 38344 bytes DWL Compiler Waveform EVAL compiled successfully DWL to Circuit Linker Reading circuit specific knowledge Compiling PLD frame PAL Blocking off PAL element GZ1321 Q1 Q1 Blocking off PAL element GZ1331 Q1 Q1 Blocking off PAL element GZ1341 Q1 Q1 Blocking off PAL element GZ1351 Q1 Q1 Blocking off PAL element GZ1361 Q1 Q1 Blocking off PAL element GZ1371 Q1 Q1 Blocking off PAL element 07138111 Writing Q Qbar signal relationships to knowledge data base Initialising simulator time 3 46 secs 351404 4 68 97 5 717 928 149 150 Default set of faults contains 156 top level stuck faults Fault dictionary statistics 156 entries Loading of faults completed took 0 17 secs total 3 63 secs Full analysis of faults completed took 0 05 secs total 3 68 secs DWL Execution 111 faults to be simulated Simulator initialised took 0 20 secs total 3 88 secs Trying to find stuck gates to block off Dropping 0 undetectable stuck gate faults Dropping 0 undetectable fuse faults No stuck gates found There 12 real Pls and 12 Pseudo PIs There are 10 real POs and 19 Pseudo POs Decompiling knowledge data base to eval kbo Tabular 2 3 PRINTCHNGE with eval tnm at time 4 16 secs Start simulation took 0 35 secs total 4 23 secs SIMULATOR START number of faults 111 At ti
95. rising the step of generating a physical circuit layout of said logic circuit from said computer model when said step of comparing indicates that said output signals and said expected output signals are substantially equal 7 Aprocess as in claim 5 wherein said step of generating a computer model comprises the step of using an expert system 8 A process as in claim 5 wherein said step of generating a test program further comprises the step of simulating faults
96. rrent_State NO Raps NO Max_backtracks 5 Overwriting value of USE_CURRENT_STATE in frame SPOT_FAULTS Overwriting value of RAPS in frame SPOT_FAULTS Overwriting value of MAX_BACKTRACKS in frame SPOT_FAULTS TG Problem SPOT_FAULTS TG Constraint PIN X 7G Constraint PIN13 X TG Working in Combinational Area Default TG Trying to catch stuck at 0 TG Trying to catch stuck at 0 on Z1371 Trying to catch 2 faults TG Using state machine knowledge TG To change PAL TG From 1101101 TG To XIXX01X Trying to move from state 1101101 to XIXXOIX Searching state machine PAL Search failed Trying to resolve problem TG End problem SPOT FAULTS TG Problem SPOT FAULTS TG Constraint PINI X TG Constraint PIN13 X 351404 Lt Troc 5 717 928 155 156 TG Working in Combinational Area Default TG Trying to catch stuck at 1 N6PD TG Trying to catch stuck at 1 21371 TG Trying to catch 2 faults TG Using state machine knowledge TG To change PAL TG From 1101101 TG To XIXX00X Trying to move from state 1101101 to XIXXOOX Searching state machine PAL Input Wires Old State New State PPPPPPPPPPPP 7727777 2777777 11 1111111 1911111 NNNNNNNNNNNN 3333333 1701000 111987654321 2345678 1299778 310 2111111 211212 XXXIXXXOXXXX 0101101 X101001 TG transition from State 1101101 to State 00 At time 45700 number of act
97. rsion from a PLD implementation to a factory programmed circuit implementation expensive engineering time is often expended by the customer Throughput time of the conver sion process is also prolonged by the time necessary for the customer to verify that the simulation results are acceptable Such engineering and verification costs add to the cost and time required to build the final device Hence it is highly desirable to have an automated mechanism by which the customer s involvement expensive engineering time as well as simulation verification is minimized if not elimi nated SUMMARY OF THE INVENTION In accordance with the present invention a system and a method for converting a PLD device to a factory programmed circuit are provided wherein a logic descrip tion of a PLD is used to generate a netlist This netlist in turn is used to generate a test program including test vectors for testing the PLD The test program is then used to test a PLD provided by the customer and if the PLD successfully passes the test it is known that the netlist accurately describes the PLD Thus the netlist can be used 5 717 928 3 to construct masks and it is not necessary to involve the customer in simulation verification The present invention is better understood in light of the following detailed description and accompanying drawings BRIEF DESCRIPTION OF THE DRAWINGS FIG 1 illustrates the steps necessary to achieve a c
98. s In addition to ARCIS other gate level simulator may be used e g HILO VIEWSIM available from ViewLogic Inc of Santa Clara Calif etc The next step in the method is to generate the actual test program used to test the PLD To accomplish this the OUT test vectors are converted to a format used by IMS tester 209 using a format conversion program block 216 In this embodiment the tester used is an IMS tester IMS testers are available from IMS Inc located in Beaverton Oreg However other testers such as Sentry testers obtainable from Schlumberger Corporation may also be used Of course format conversion may need to be provided for cach tester type used 10 15 35 40 45 55 65 8 conversion program represented by block 203 receives file CCT and in response thereto generates a IN file which contain the same netlist information as the CCT file Of importance the IN file is in a format which is received by a conversion program PADPIN block 205 The PADPIN program extracts from a data base MD PAD and netlist file IN pin and pad layout information to provide an output file NP1 Appendix A 16 which provides test set up informa tion PADPIN also generates a file PAD such as the one listed in Appendix A 17 which is used during the device layout process described below As shown in the listing of Appendix A 16 the information provided in the NP1 file includes for each pin number whether
99. s a delay time of 5 ns ARCIS then calculates that the output signal of that buffer will change state at a time T 1005 ns ARCIS makes similar calculations concerning the propa gation of signals throughout the circuit ARCIS can provide output files in various formats For example ARCIS can provide an output file which indicates the time of every signal transition in the circuit This may be used to determine if the device being simulated meets device timing targets ARCIS may also be used to provide an output file indicating the state of the output signals at regular intervals e g every 200 ns Attached as Appendix A 14 is ARCIS output file OUT indicating the states of each input and output pin at 200 ns intervals The OUT file is used to generate the test vectors to test the customer provided PLD It is noted that because OUT merely contains the state of the device every 200 ns it contains essentially no informa tion concerning the timing performance of the device pro vided in the netlist file IN described above Thus the OUT file provided by ARCIS does not reflect timing tests on the PLD This is because at this point only functional testing is performed While ARCIS is used to generate functional vectors to test the PLD it is noted that HITEST also provides test vectors that can be used to test the PLD Thus one can practice the present invention using either the HITEST generated test vectors or the ARCIS generated vector
100. s through a circuit having the logic elements described in the CCT file when the stimulus signals provided in the TAB file are applied to the circuit The operation and use of ARCIS as discussed in GATEAID PLUS PC 2 0 User s Manual second edition 1988 pub lished by Matra Design Semiconductor hereby incorporated by reference in its entirety Prior to running ARCIS it is necessary to convert the CCT and TAB files into a format that ARCIS can accept Thus block 206 represents a conversion program that receives file and generates therefrom file SIM Appendix A 12 As can be seen the conversion program represented by block 206 deletes the expected output signals from file because ARCIS will recalculate these sig nals The conversion program also causes the columns of the SIM file to be in an order different from that in the file Further as shown in Appendix A 12 the SIM file includes the following commands to the ARCIS program 1 CYCLE1 is a multiplier in this case 1 0 for the times listed in the SIM file 2 LOAD 50 indicates that 50 pF loads are present on pins 14 to 23 3 VCC CLKO 100 describes the power input waveform necessary to correctly simulate the POR function Specifically the VCC input signal is initiaily low for 10 ns then goes high and remains high thereby providing a signal transition to the POR function 5 717 928 7 4 PRINT lists the output signals to be printed by
101. sonalization of the mask programmed device may be accomplished by mask patterning interconnect metallization providing vias in mask programmed locations providing contacts at mask programmed locations providing transistor gates at mask programmed locations or any combination of the above mask programming techniques The mask programmable device may be a gate array mask programmable PAL a custom cell logic circuit or a full custom logic circuit Also the present invention may be used to construct a mask programmed device to be substituted for another mask programmed device instead of a PLD Although in the above described embodiment the ASIC vendor receives logic equations from the customer in other embodiments the ASIC vendor receives other types of logic circuit descriptions e g a truth table or a schematic descrip tion It should also be noted that the invention may also be practiced such that the user of the PLD is not a customer from another company but within the same company as the ASIC design group 351404 13 5 717 928 Appendix A 1 the ABL File Matra Design Semiconductor Inc 1987 14 5 717 928 15 16 module m1712_01 flag 3 2 U203 MFB U303 CFB Hwregs Frame buffer CONTROL STATUS register Rev A 11 30 87 22 10 Cypress 28 28 this pal implements the Control and Status registers and generates interrupts Revision History Rev 0 01 06 16 87 P Treen Origin
102. tn gt IN z tn tm m tn tr tr Eri mm rn tn m tn to tn tn t ta t m n Z t m 37 198 50 283 68 118 198 35 131 383 42 42 42 58 34 2960 NAY d tA Anon oo 184 184 198 232 PS fF PS fF PS fF PS fF PS fF PS PS fF PS PS PS PS fF PS fF PS fF PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 5 717 928 233 234 DELAY ZPORNODCAP PORS OUT 0 7 E 0 PS DELAY ZPORNODCAP PORS OUT POR29 E 198 PS 351404 A FT tu 5 717 928 235 We claim 1 A system for creating a factory programmed device using a sample device and a logic description of said sample device comprising means receiving said logic description for generating a computer model of a logic circuit therefrom means coupled to said means for generating a computer model for generating a test program from said com puter model said test program including data repre senting stimulus signals to said sample device and expected output signals of said sample device when said stimulus signals are applied to said sample device and means coupled to said means for generating a test program for testing said sample device wherein said means for testing i applies said stimulus signals in accordance with said test program ii obtains output signals from said samp
103. uit technol ogy The layout generation step 103 is also typically achieved using a variety of design software programs and databases Some examples of these software programs and databases are place and route programs and cell component libraries The layout generated by step 103 is provided to a simulation and verification program at step 104 to ensure that logic functions and timing parameters are accurately preserved during the translation from the netlist representa tion to the layout representation These simulation and verification programs may be the same as those used in step 102 discussed above At this point many parameters specific to the physical implementation of the circuit such as timing may be more accurately estimated Once again the layout generation process is not always straight forward Several iterations of the layout generation and post layout simula tion and verification steps 103 and 104 are often necessary After the customer is satisfied with the layout generated another sign off represented in FIG 1 as decision step 120 is provided to the ASIC vendor to indicate permission to begin manufacturing the device Again the customer bases his her decision upon careful perusal of the simulation and verification results The generated layout of step 104 is then used to build photolithographic masks which are used to manufacture the gate array step 106 As can be readily seen to achieve the conve
104. ut NFI NF2 begin if NF1 NF2 A then NF1 NF2 351404 1h 46 79 105 5 717 928 106 end if end rule ASS DFFRN1 Q GEN lt 8 gt is in D RN out QN generic out Q begin if Q DFFRNI D CK RN QN INVI then DFFRNI D CK RN end if end rule ASS DFFRNI QN lt 8 gt is in D CK RN out QN begin if Q QN DFFRNI D CK RN NOTQ INVI Q then QN DFFRNI D CK NOTQ QN end if end rule ASS_DFFRN1_QN_GEN lt 8 gt is in D RN out Q generic_out QN begin if QN DFFRNI D RN Q INVI then Q QN DFFRN1 D CK RN end if end rule ASS_DFFRNI_QN_Q lt 8 gt is in D CK RN out 0 NOTQN begin if Q QN DFFRNI D 351404 m 4T De 5 717 928 107 108 NOTQN INVI QN then 0 DFFRNI D RN NOTQN end if end rule 55 QN 0 GEN lt 8 gt is D CK RN out generic_out begin if Q QN DFFRNI D CK RN NOTQN INVI then Q QN DFFRNI D CK RN NOTQN end if end rule ASS_DFFRNSN1_QN_GEN lt 8 gt is in D CK RN SN out Q generic_out QN begin if QN DFFRNSNI D CK RN SN Q INVI QN then QN DFFRNSNI D RN SN end if end RUL

System and a method for obtaining a mask programmable device

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