FASTCOM™: ESCC-104-ET HARDWARE MANUAL
Contents
1. Bum BOARD LAYOUT SEND RECEIVE TEHMINATIDN STATUS LED RESISTORS R6 25 R20 un 0 Dm O ma SAF82532 eed lt LATCH at LOCK CONNECTOR mm T 02 CHANNEL cp 1 SELECT 70 lt 2 104 CONNECTORS TERMINATION REFERENCE CHANNEL 1 CHANNEL 2 BASE ADDRESS BASE ADDRESS 4 ica IRQ LEVEL FASTCOM ESCC 104ET b u4 SIGNAL REF RT R12 RD R13 CTS R14 ST R15 DCD R16 RT R7 RD R8 CTS R9 ST R10 DCD R11 PACKING LIST FASTCOM ESCC 104 ET CARD FASTCOM CD If an omission has been made please call technical support for a replacement LED INDICATORS RED TRANSMIT ACTIVE GREEN RECEIVE ACTIVE RED TRANSMIT ACTIVE GREEN RECEIVE ACTIVE N CO gt 20 N a A EY pum A x DH 1 40 PIN LATCH LOCK HEADER DESCRIPTION The Fastcom ESCC 104 ET comes with a 40 pin latch lock header This requires the use of a ribbon cable rather than the DB style shielded cable normally supplied Following is the pin out description of the 2x20 header POLARIZING KEY 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 0002. 28 TECHNICAL SUPPORT All products manufactured by Commtech are warranted against defective materials and workmanship for the lifetime of the product This warranty is available only to the original purchaser Any product found to be defective will at the option of Commtech be repaired or replaced with no charge for labor or parts not excluded by the warranty This warranty does not apply to any products that have been subjected to misuse abuse or accident or as a result of service or modification by anyone other than Commtech In no case shall Commtech liability exceed the original product purchase price If any Commtech product is damaged such that it cannot be repaired you can return it to Commtech for replacement under our Non Repairable Replacement policy regardless of the cause of damage Commtech will replace the unit at 6096 of the then current list price Commtech provides extensive technical support and application suggestions Most of the problems that occur with the FASTCOM ESCC 104 ET be corrected by double checking the switch positions your cables and your program We recommend that you build the loop back plug that is described in the Programming section of this manual With that plug you can quickly isolate the problem to the board cables or software If you still have unresolved questions use the following procedure to get technical support 2 Ask for technical support for the FASTCOM ESCC 104 ET Be
3. 18c0h 6336 1900h 64000 1940h 6464 1980h 6528 1900h 6592 1008 6656 6720 6784 lacoh 6848 6912 1408 6976 7040 7104 Hoch 7232 7296 73600 7424 7552 7616 76800 1744 7808 Hec h 7872 LEMON 8000 8064 LECOR 8128 2000h 8192 2040h 8256 2080h 8320 I20c0h 8384 234567 8 0444004 00111001 11011001 01011001 10011001 00011001 11101001 Hex Decimal 2100h 8448 12140h 8512 2345678 6008 bao 01011110 Leo re Te 20014410 Le 01101110 10101110 00101110 11001110 01001110 10001110 00001110 1110110 Qd 0 6 10110110 00110110 020101160 01010110 10010110 00010110 11100110 01100110 10100110 00100110 11000110 01000110 10000110 00000110 01111010 10111010 00111010 5014010 01011010 Hex Decimal 2345678 16911049 00011010 11101010 01101010 10101010 00101010 11001010 01001010 10001010 00001010 11110010 10110010 00110010 11010010 01010010 10010010 00010010 11100010 01100010 10100010 00100010 11000010 01000
4. CCR1 CCR1 28EH CCR2 CCR2 CCR2 CCR2 CCR2 CCR2 28FH CCR3 CCR3 CCR3 CCR3 290H d 291H TSAR 292H XCCR 293H RCCR do 294H VSTR BGR VSTR BGR VSTR BGR 295H 296H PRE PRE PRE PRE 297H 298H GIS IVA GIS IVA GIS IVA 299H IPC IPC IPC IPC IPC IPC 29AH ISRO IMRO ISRO IMRO ISRO IMRO 29BH ISR1 IMR1 ISR1 IMR1 ISR1 IMR1 29CH PVR PVR PVR PVR PVR PVR 29DH PIS PIM PIS PIM PIS PIM 29EH PCR PCR PCR PCR PCR PCR 29FH 2 FIFO FIFO FIFO FIFO FIFO FIFO PVR Register The 82532 has 8 bit I O port PVR that has the following functions on the FASTCOM ESCC 104 ET Bit 0 Channel select 0 channel 1 1 channel 2 1 ICD2053B clock 2 ICD2053B data 3 DTR channel 1 4 DTR channel 2 5 DSR channel 1 input 6 DSR channel 2 input 7 TC from PC104 bus from PC s DMA controller input 292122 IESEE LLOCOU CL CEBEQI Q LALLUL LLLLLAETEEDPEELLILLLLLLI B ILIIIA gt output output APPENDIX B ADDRESS SETTINGS 32 ADDRESS SETTINGS The FASTCOM ESCC 104 ET requires 34 contiguous bytes of address space You may use any address that is not used by a device insta
5. signals to the RD signals internally so you don t have to make the connection on your cable It also controls the CTS disable feature and the output of the clock in RS 485 mode Since the 82532 will only transmit when its CTS pin is active this switch allows the 82532 to see the CTS input as active all the CTS Disable Channel 2 CTS Disable Channel 1 SD RD loopback Channel 2 SD RD loopback Channel 2 SD RD loopback Channel 1 SD RD loopback Channel 1 time regardless of the signal at the connector The loopback switch positions are provided for RS 485 mode and should be used in pairs Positions 1 and 2 should either be on creating a loopback for RS 485 mode or off for RS 422 mode Likewise positions 3 and 4 should either both be on or both off The CTS disable switch in the on position is used to force CTS into the active state to allow the 82532 to transmit data if the CTS signal line is not used In the off position the CTS signal from the connector is connected to the 82532 and the 82532 will not transmit unless the external CTS signal is active The 485 clock control switch selects 422 or 485 clock output mode In the off position default the TXCLK is selected as an output for RS 422 TT lines are always clocking If a gated clock is required the on position will connect the RTS line of the channel to the driver enable and it will become RS 485 similar to the 50 lines on Switch 5
6. 29 ESCC 104 ET REGISTER 000 29 APPENDIX Boon EHE ETE EPFL 31 DEC ADDRESS SET TIENS weiss dert ocior cardo cd c D aad DR 31 APRENDO ev P isan A 37 SIEMENS SAF 82532 DATA 5 ar INTRODUCTION The new FASTCOM ESCC 104 ET is a very high speed dual channel synchronous asynchronous serial communications adapter based upon the Siemens 82532 Enhanced Serial Communication Controller ESCC FASTCOM ESCC 104 ET is designed to support data rates up to 10 Mbits second maximum data rates are affected by many factors including computer performance cable quality and software overhead and to reduce the hardware and software overhead needed for serial communications Each sync async channel on the FASTCOM ESCC 104 ET has its own DPLL encoder decoder and programmable protocol support In addition a built in 64 byte FIFO provides the FASTCOM ESCC PCI with a very high throughput as well as requiring less system CPU time than any other HDLC adapter The FASTCOM ESCC 104 ET directly supports HDLC X 25 LAP B ISDN LAP D SDLC ASYNC and BISYNC protocols and features a high speed RS 422 RS 485 interface HDLC features include choice of CRC polynomial CRC CCITT or CRC 32 expanded line encoding methods FM and Manchester and preamble transmission Many engineers
7. Observe Electrostatic Discharge ESD precautions when handling the FASTCOM ESCC 104 ET board Unpack the FASTCOM ESCC 104 ET Keep the box and static bag for warranty repair returns Checkthe switches to be sure that they are set as illustrated below Factory Switch Settings FACTORY SWITCH SETTINGS ADDRESS SELECT SW1 280H IRQ SELECT SW2 amp SW3 5 DMA SELECT 5 4 DMA MODE 1 CONFIG SW5 RS 422 DISABLED TXCLK IS OUTPUT MODE 2 CONFIG SW6 NO LOOPBACK 485 CTS DISABLED 422 CLOCK MODE INSTALLING THE WINDOWS NT 2000 ESCC DRIVER The NT 2000 driver for the ESCC is the ESCCDRV SYS file It is a kernel mode driver The NTINSTALL EXE program is intended to simplify the process of adding registry information about the base address interrupt and DMA information about each channel INSTALL DRIVER Pressing this button will copy the ESCCDRV SYS file to your C winntisystem32 drivers subdirectory It will create the following subkey in the registry HKEY_LOCAL_MACHINE SYSTEM CurrentControlSet Services esccdrv In that key it adds the following information DisplayName REG_SZ esccdrv ErrorControl REG_DWORD 0x01 ImagePath REG_EXPAND_SZ C WINNT System32 Drivers esccdrv sys Start REG_DWORD 0x02 Type REG_DWORD 0x01 These values are actually created by the CreateService API call gt The CAWINNT part of the image path will should reflect your
8. 2 Set ICD2053b ICD2053B set to 16MHz starting settings INIT OK Getting VSTR VSTR contents 82 WRITE REG CMDR gt XRES Write Reg successful check status STATUS DECODE Transmit Done flushing rx RX flushed flushing tx TX flushed read frame The operation is pending write frame 1 7 gt 12 Write successful WAIT OBJECT O0 post GET OVERLAPPED RESULT 01234567890123456789012346 Read returned 26 bytes Valid CRC OK write frame 1 Write 1successful write frame 2 Write 2 successful write frame 3 should pend no more tbufs The I O operation is pending write frame 4 should fail bufs full Tx buffers full try again later read frame should get 4001 bytes The I O operation is pending Read Timeout WAIT_OBJECT_0 post GET OVERLAPPED RESULT 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890 12345678901 2345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 012345678901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 12345678901 23456789012345678901234 56789012345678901234567890 12345678901 234567890 1234567890123456789012345678901234567890123456789012345678901234567890123456789 012345678901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890123456789012345678901234
9. 7 On On Off Off Channel 1 RX DMA Select xo Position 1 On off Off Position 3 On On Off Off Channel 2 TX DMA Select Channel 2 TX DMA Select 17 SWITCH 5 MODE 1 SWITCH The Mode 1 switch serves three functions it selects either RS 422 or RS 485 driver mode enables or disables DMA and selects the direction of the transmit clock input or output TXCLK input Channel 2 TXCLK output Channel 2 TXCLK input Channel 1 TXCLK output Channel 1 DMA Enable Channel 2 DMA Enable Channel 1 485 Driver Control Channel 2 485 Driver Control Channel 1 The 485 driver control switch controls the transmitter enable for the SD signals In the on position the RTS output controls the enable RS 485 mode in the off position the SD driver is always on RS 422 mode The DMA enable switch controls the connection to the PC104 DMA channels In the on position DMA is enabled for that channel both RX and TX DMA channel selects will be active for that channel In the off position DMA is disabled The TXCLK input output switches connect the TXCLK pin to either the TT signal lines to output the transmit timing or the ST signal lines to input the transmit timing If the input selection is made with position 6 or 8 on do not configure the 82532 TXCLK pin as an output SWITCH 6 MODE 2 SWITCH The Mode 2 switch controls the RS 485 loopback feature connecting the SD
10. can occupy the network at a time This means that each station on the network must control the enabling disabling of their drivers in order to avoid network conflicts If two drivers engage the network at the same time data from both will be corrupted In RS 485 mode the receivers are always enabled For a more detailed description of RS 422 and RS 485 we recommend the following references LINEAR AND INTERFACE CIRCUITS APPLICATIONS Volume 2 Line Circuits Display Drivers By Pippenger and E J Tobaben Published 1985 by Texas Instruments ISBN 0 89512 185 9 Note This book may be difficult to find in a bookstore The best place to get it is directly from Texas Instruments or from one their component dealers Publication SLYAOO2 Driver Receiver Family Extends Data Link Performance ELECTRONIC PRODUCTS January 15 1985 By Dale Pippenger and Joe Miller 20 TERMINATION RESISTANCE In both the RS 422 and the RS 485 mode the receiver end of the cable between two stations must be terminated with a resistor equal to the characteristic impedance of the wire This is to prevent signal reflections in the wire and to improve noise rejection However you do not need to add a terminator resistor to your cables when you use the FASTCOM ESCC 104 ET The termination resistance is built in We have installed a terminator resistor for each receiver between each and RD and between CTS and CTS for each channel If you are using
11. esccdrv svs file from your winntisystem32 drivers directory If you want to completely remove the driver you must delete this file manually The intended sequence of events is Press Install Driver button Press Add Board button 2 times per board installed Fill in address irq dma information Press Start Esccdrv button Press OK Exit If you want to change add a board later you would need to follow the following sequence Press Stop Esccdrv button Press Add Board Remove Board as necessary Press Start Esccdrv button Press OK Exit If you do not have any boards channels installed and press the start button you must manually delete the esccdrv sys and the esccdrv subkey before rebooting or any attempt to stop the driver could cause Windows to go into its bug check mode Blue Screen of Death The NTINSTALL EXE program does not do any checking on the values that you enter If you enter unreasonable values for address irq dma there is a very good chance that Windows will become unstable bug check mode The driver only looks at the registry information on startup If you add boards while the driver is running the new devices will not exist until the system is restarted or you stop and restart the driver For example if you Press Install Driver Press Add Board enter channel 0 info Press Add Board enter channel 1 info Press Start Esccdrv Press Add Board enter channel 0 info Press Add Board enter channel 1 info Run e
12. have avoided using synchronous communication adapters because of their programming complexity FASTCOM ESCC 104 ET provides high speed data communications to designers and engineers while greatly reducing development time and system complexity The FASTCOM ESCC 104 ET is also available in a PCI bus version FASTCOM ESCC PCI an ISA bus version FASTCOM ESCC ISA The following diagram illustrates the basic structure of the FASTCOM ESCC 104 ET PC 104 BUS CHANNEL 1 OF 2 1851 154 82532 Q prse uj O G SD JJ a LLI zB COMMUNICATION 2 RD A13 lt ba CONTROLLER 8 LL RD YO RTS Nr RTS 0 5 NY 9 0 5 CTS DO e CTS gt DCD f DATA DCD 07 DSR D15 DTR RT o 2 2 IRQ 2 o 2E 229 T gt G E reo _ of INTERRUPT IUE ST P TP IRQ 15 lt 5 2 O 1 E DMA 3 ER 5 lt 9 DMA5 8 28 5 DMA7 SPECIFICATIONS COMMUNICATION CONTROLLER SIEMENS 82532 DRIVERS RECEIVERS RS 422 RS 485 CONNECTOR CONFIGURATION 100 X 100 Latch Ejector Header POWER REQUIREMENTS 5V 0 300 typical BUS INTERFACE PC 104 ENVIRONMENT Storage Temperature Range 55C to 125 C Operating Temperature Range 40 C to 85 C Humidity 0 to 909
13. installed system directory i e the system drive and where your Windows files are installed and could be different depending on how you originally installed Windows Start parameter is set to automatic This will load and run the driver every time that Windows is started If you want to start and stop it manually you can change the start type by using the Control Panel gt Devices Startup button after the driver is installed Type parameter is kernel mode ADD BOARD Pressing this button will add the information to the registry about where a particular ESCC channel is located It will create a subkey under the esccdrv parameters such as esccdrv parameters 5 The dialog that appears when you press ADD BOARD needs to have the Base Address Interrupt and DMA information for the card you are installing For example if you use the factory defaults do not change any of the switch settings you would press the ADD BOARD button two times The first time you would enter Base 0x280 5 DMAR 0 0 Channel 0 The second time you would enter Base 0x280 5 0 lt 0 Channel 1 This will create two subkeys esccdrviparametersiESCCO and esccdrv Parameters ESCC1 The value that you enter for Base should match setting of the base address switch on the board The value that you enter for IRQ should match the setting of the IRQ LEVEL switch on the board The valu
14. mode TEST 2 1 From the Start button menu select Run Enter D fastcom_disks escc nt setfs6131clock setfs6131clock 0 2000000 11 2 Press the Start Button select the Run command Enter D fastcom_disks escc nt esccmfc esccmfc Click OK 3 From the main menu select Options gt Port Enter 0 click OK make sure you have your port 0 loopback on 3 From the main menu select Options Settings the settings dialog will open Click OK the TXD status indicator on the screen should turn green 4 Type a short message on the keyboard press enter to send it The message you typed should appear in the lower window and the RXD RFS and ALLS status indicators should turn green if it was a short message 32 bytes or so a long message will likely only get a RXD status indicator If when running any of these tests you do not get the expected result check your switch settings and the driver install settings to make sure that they match f it still doesn t work try a different address irq combination to remove a possible address or irq conflict Troubleshooting tips 1 Incorrect loopback faulty wiring 2 Interrupt conflict 3 Address conflict Fastcom ESCC 104 ET Windows 9x Test Install port O loopback ESCCO portO From the Start button menu select Run Enter D fastcom_disks escc w9x escctest Click OK 4 The display should be obtained handle to esccdrv try to add port port added ports active
15. ready to describe the problem your computer system your application and your software 3 If necessary our staff will give you an RMA number Return Material Authorization Use this number on the mailing label and in all references to your board Put the board back in its static bag and in its box Ship the board back to us as directed 4 If you prefer you may FAX a description of the problem to us at 010 6851 9889 APPENDIX A FASTCOM ESCC 104 ET REGISTER MAP 30 FASTCOM ESCC 104 ET REGISTER MAP The following chart illustrates the register map of the FASTCOM ESCC 104 ET using the factory default address of 280H Refer to the Siemens SAF 82532 User s Manual for additional information on the registers HDLC SDLC ASYNC BISYNC Address Read Write Read Write Read Write 280H STAR CMDR STAR CMDR STAR CMDR 281H RSTA 282H MODE MODE MODE MODE MODE MODE 283H TIMR TIMR TIMR TIMR TIMR TIMR 284H XAD1 XAD1 d o SYNL SYNL 285H XAD2 XAD2 d SYNH SYNH 286H TCR TCR TCR 287H RAH20 DAFO DAFO DAFO 288H RAL1 RAL1 RFC RFC RFC 289H RHCR RAL2 do 28AH RBCL XBCL RBCL XBCL RBCL XBCL 28BH RBCH XBCHH RBCH XBC RBCH XBCH 28CH CCRO CCRO CCRO CCRO CCR CCRO 28DH CCR1 CCR1 CCR1 CCR1
16. the FASTCOM ESCC 104 ET in a multi drop network the termination resistor should be removed from all units except the first and last see the RS 485 illustration below Call for technical support if you need to modify the resistor You may also order the FASTCOM ESCC 104 ET without the termination resistor installed it is easier to add the resistor than to remove it Observe the resistors in the following drawings and remember that they are built into the FASTCOM ESCC 104 ET Typical RS 422 DRIVERS R2 eRX Rx RI TX RECEIVERS R1 amp R2 Line Termination 100 Ohms Typical RS 485 21 jissa PROGRAMMABLE CLOCK GENERATOR AMI FS6131 01 The FASTCOM ESCC 104 ET features the FS6131 01 Programmable Clock Generator which offers a fully user programmable phase locked loop in a single 8 pin package The output may be changed on the fly to any desired frequency value up to 130 MHz the FASTCOM ESCC 104 ET maximum is 33 MHz The ability to dynamically change the output frequency adds a whole new degree of freedom for the designer Programming the FS6131 01 is simple requiring only setfs6131clock exe program This program is provided on the Fastcom CD FEATURES e Clock outputs up to a maximum of 130 MHz the FASTCOM ESCC 104 ET maximum is 33 MHz e Phase Locked Loop oscillator input derived from external reference clock 18 432 MHz on the FASTCO
17. used The timer is in external mode RTS is handled by the 82532 active while transmitting Timer resolution is 32768 clocks CCRO 0xCO This sets the 82532 in power up mode Master clock mode is enabled NRZ is the encoding type HDLC mode is selected CCR1 0x10 This selects clock mode O b The tx pin is using a push pull output required Time fill is all 1 s idle pattern Oxff CCR2 0x38 This selects the N 1 2 divisor Selects txclk to be an output Selects clock mode Ob the B part Enables the CRC CCITT polynomial 25 CCR3 0x00 No preamble output reset level Oxffff CRC is in use both transmit and receive not including CRC in received Data not returned to the user Not using extended window for DPLL CCR4 0x00 Not using master clock 4 Not using enhanced baud rate generator FIFO threshold is 32 bytes mandatory for NT driver in HDLC mode This sets the output clock rate to 19200 given that the input clock was previously set to 7 3728 MHz and the above registers are set as shown CCRO CCR1 4 and are the most critical registers that effect the bitrate the rest are shown for completeness and depending on the system you can easily change some parameters without affecting the bitrate i e line encoding address recognition crc type etc And now for something a bit more difficult Let s say that you want to run one channel asynchronously at 38400 bps a
18. will find 115200 32E6 16 N 1 2 7 68 Using N 7 bitrate 32E6 16 7 1 2 125000 bps Using N 8 bitrate 32E6 16 8 1 2 111111 bps The ideal situation would be to adjust the 32 MHz clock such that the deviation between the desired and actual rates is spread between both channels with the DPLL recovering the clock the actual clock that feeds it is not as critical as a clock mode that uses the clock directly Clock modes Ob 3b 4 and 7b are more sensitive to the selected rate in synchronous modes as there is no oversampling The rate you select is the rate you will get whereas oversampling modes using the DPLL or ASYNC BCR are more tolerant to differences between the rate you set and the rate you want On the following page is a block diagram representation of the clocking concept 27 CLOCKING CONCEPT BLOCK DIAGRAM E EE 17 Clock Generator ICD2053B Channel1 3 Switch positions 5 amp 6 EJ Channel2 Switch positions 7 amp 8 Oscillator f BRG f TXCLK 2 4 y 0 o c c x N c e a a a E a 4 2b 1 Oa 4 2alb3b 3b 6 5 2a 7b 1 7b 6a 6a b 5 fREC CCRO 1 0 Transmitter Receiver
19. 000000000 0 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 PIN SIGNAL PIN SIGNAL 1 GND 21 157 2 2RT 22 1DCD 2 23 1DCD 4 2DSR 24 280 5 1RT 25 280 6 1RT 26 2RTS 7 1DSR 27 2RTS 8 2RD 28 2TT4 9 2RD 29 2TT 10 2CTS 30 2DTR 41 2 31 1SD 12 2ST 32 180 13 2ST 33 1RTS 14 2DCD4 34 1RTS 15 2DCD 35 1 16 180 36 1TT 17 A1RD 37 1DTR 18 1CTS 38 19 1CTS 39 20 15 40 GND PIN OUT DESCRIPTION Signal Pin Descriptions Channel 1 Pin Number Pin Number Name 1 40 31 32 17 16 33 34 19 18 7 37 Channel 2 1 40 25 24 9 8 27 26 11 10 4 30 Clock Signal Pin Descriptions Channel 1 Channel 2 Pin Number Pin Number 23 15 22 14 35 29 36 28 5 3 6 2 21 13 20 12 GND GND SD 50 RTS RTS CTS CTS DSR DTR Name DCD DCD TT TT RT RT ST ST Pin Description 422 Circuit Ground Ground Transmit Data Transmit Data Receive Data Receive Data Request to Send Request to Send Clear to Send Clear to Send DCE Ready DTE Ready Pin Description Data Carrier Detect Data Carrier Detect Transmit Clock Out Transmit Clock Out Receive Clock In Receive Clock In Transmit Clock In Transmit Clock In NOTE The DTR and DSR signals are single ended unbalanced AA AB BA BA BB BB CA CA CB CB CC CD 422 Circuit CF CF DA DA DD DD DB DB INSTALLATION Important
20. 010 10000010 00000010 01111100 00111100 11011100 01011100 10011100 00011100 35 36 Hex De cimal Hex De cimal APPENDIX C SIEMENS SAF 82532 DATA SHEET
21. 0100111 3712 101000 6c0h 1728 00100111 eco 3770 001000 7000 1792 11000111 2008 3840 110000 7406 1850 01000111 40h 3904 010000 7800 1920 10000111 80h 3968 100000 Teoh 1984 00000111 fc h 4032 000000 Hex Decimal 1000h 4096 1008 4160 1080h 4224 4288 1100h 4352 H140h 4416 111808 4480 1200h 4608 112408 4672 112808 4736 4800 1300h 4864 113408 4928 1380h 4992 1 5056 1400h 51200 1440h 5184 1480h 5248 14c0h 5312 H500h 5376 1540h 5440 1580h 5504 15c0h 5568 1600h 5632 1640h 5696 1680h 5760 16c0h 5824 1700h 5888 17408 5952 1780h 6016 17e0h 6080 1800h 6144 1840h 6208 234567 8 eee EN 10111101 IEEE EOI 01011101 10011101 00011101 ere v 01101101 10101101 135902301 01001101 10001101 00001101 1010201 EN 10110101 00110101 oa on d 01010101 28043904591 00010101 LERS TADE 01100101 10100101 00100101 11000101 UTEM 10000101 00000101 01111001 Hex Decimal 1880h 6272
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25. 6 non condensing FEATURES High speed up to 10Mbits s dependent upon system capabilities Much easier to program and use than other HDLC adapters Supports HDLC SDLC ISDN LAP D and X 25 LAP B ASYNC BISYNC Uses extended temperature components Designed for operation in more extreme environments Drivers RS 422 RS 485 multi drop Excellent noise rejection cable lengths up to 4000 feet Use low cost twisted pair cable RS 485 mode Up to 32 FASTCOM ESCC 104 ET adapters can share the same twisted pair Driver control is automatic via the RTS line Serial Interface Internal or External Clock Source Asynchronous Monosync Bisync and HDLC SDLC data formatting 1X isosynchronous or 16X oversampling for Asynchronous format Different modes of data encoding NRZ NRZI FMO FM1 Manchester CRC CCITT or CRC 32 for HDLC SDLC modes CRC CCITT or CRC 16 for BISYNC mode Modem control lines RTS CTS DTR DCD DSR Collision resolution Programmable bit inversion Transparent RD SD of data bytes without HDLC framing Protocol Support HDLC SDLC Types of protocol support Automatic Manual and Transparent Handling of bit oriented functions in all modes Handling of and S frames in Auto mode Modulo 8 and 128 operation 64 byte FIFOs per direction Storage of up to 17 short received frames
26. 8 nn nr rent nn 6 TESTING THE INSTALLATION 0 222 0 0 1 11 1 reisen sen tina sent possesso ipsas serra sen 9 FASTCOM ESCC 104 ET WINDOWS NT 2000 TEST nanna nanna 9 FAsTCOM ESCC 104 ET WINDOWS 9X 11 SWITCH DESCRIPTION PERRA RIGRREPERISRUR 14 MISES M BE ID RI NEM BE 14 SWITCHES 2 AND 3 20 022000 15 INTERRUPT 1 1 1 1 rn 15 SWITCH 4 DMA CHANNEL SELECT asa aii 16 SWITCH 5 MODE 1 17 SWITCH 6 MODE 2 aii 17 FPROGRAMMING 18 i EIE 19 TERMINATION RESISTANCE urinaria 20 PROGRAMMABLE CLOCK GENERATOR AMI 56131 01 2 2 21 FE TURE S aca dd eaa uM M M MM SUM 21 DETERMINING AND SELECTING BAUD RATES 10 001 1 re tre rri re iri 21 MASTER CLOCK MODE re E Ra Ra a RR ERR A 22 AN IMPORTANT FACT ABOUT THE CLOCK 44 re re 23 EXAMPLES AND EXPLANATIONS inca sta gh 23 CLOCKING CONCEPT BLOCK DIAGRAM iii ea a o a dada 27 TECHNICAL SUPPORT css tent I ita 28 APPENDIX
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28. 89012345678901234567890123456789012345678901234567890123456789012345678901234567896 Read returned 2001 bytes Valid CRC OK check status STATUS DECODE Sent Transmit Done Press a key to send again esc to exit exiting prog This program assumes the factory default switch settings address 0x280 IRQ 5 If you do not have those resources available you must recompile the example with the address and IRQ to match your board settings Troubleshooting tips 1 Incorrect loopback faulty wiring 2 IRQ conflict with other hardware 3 Address conflict with other hardware 14 SWITCH DESCRIPTIONS There are six dip switches on the FASTCOM ESCC 104 ET labeled SW1 SW2 SW3 SW4 SW5 and SW6 See Board Layout Illustration for location Switch 1 labeled ADDRESS is used to set the I O address of the FASTCOM ESCC 104 ET board Switches 2 and 3 labeled IRQ SELECT serve two functions they select the IRQ level for the board and are used to enable disable interrupt sharing Switch 4 DMA CHANNEL SELECT selects the channels to be used by each ESCC port Switch 5 MODE 1 CONFIG selects either RS 422 or RS 485 mode enables DMA and determines the direction of the TXCLK signal if the transmit clock is received or transmitted Switch 6 MODE 2 CONFIG controls the loopback function for RS 485 and the CTS disable feature SWITCH 1 ADDRESS Switch 1 decodes the PC address lines as follows Address lines A6 th
29. 901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 Read returned 3001 bytes Valid CRC OK check status STATUS DECODE Receive Frame Start Transmit Done read frame should get 2001 bytes The operation is pending WAIT OBJECT 0 post GET OVERLAPPED RESULT 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 5678901234567890123456789012345678901234567890123456789012345678901
30. 901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890123456789012345678901234 56789012345678901234567890 12345678901 2345678901 2345678901 23456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890 12345678901 2345678901 2345678901 234567890123456789012345678901234567890123456789012345678901234567896 Read returned 4001 bytes Valid CRC OK check status STATUS DECODE Receive Frame Start All Sent read frame should get 3001 bytes The I O operation is pending Read Timeout OBJECT 0 post GET OVERLAPPED RESULT 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 5678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890
31. FASTCOM ADAPTERS FASTCOM ESCC 104 ET High Speed Dual Channel Sync Async Extended Temperature Interface for PC 104 Bus Hardware Reference M anual M anufactured by CONWVTECH CONWNVTECH http www commtech com cn COPVRIGHT C 2003 All rights reserved including those to reproduce this document or parts thereof in any form without permission in writing from Commtech Inc FASTCOM and SMART 14 are trademarks of Commtech Inc IBM is a registered trademark of International Business Machines Corporation Microsoft is a registered trademark of Microsoft Corporation WINDOWS is a trademark of Microsoft Corporation REVISION NOTES REVISION PAGE NUMBER CHANGES MADE 1 0 All Created document 1 1 29 Changed warranty period to lifetime 1 2 All Fixed all references to non ET board 1 3 22 Fixed BDF error CONTENTS 1 0 CI i 1 UO E A 2 FESTES E E ME RE LI 2 BOARD LAYOUT ba ib E ge deo cara 3 40 PIN LATCH LOCK HEADER 4 PINOUT DESCRIPTION e di Sap an 5 INSTALLATION M 6 FACTORY SWITCH SETTINGS He NOR A QE UNE aiii 6 INSTALLING THE WINDOWS NT 2000 ESCC 2 040
32. GR bit 2 BGR bit 1 BGR bit 0 m CCR2 8 7 7 BGR 6 N CCR2 8 CCR2 7 BGR 7 BGR 6 BGR 5 BGR 4 BGR BGR 2 BGR 1 BGR O Some things to keep in mind The range on the ICD2053B output is 391kHz to 90MHz The usable range if the master clock enable bit is clear not using master clock is 391kHz to 33Mhz the master clock is set then the range is from 391kHz to 10MHz Using master clock mode also places a restriction on the ratio of receive transmit clock to the master clock frequency as per note 2 on page 84 of the 82532 data sheet Fmaster Ftransmit gt 2 5 Freceive Fmaster 3 or 1 5 if CCR3 bit 4 RADD is set and an address recognition mode is used in HDLC MASTER CLOCK MODE To use Master clock mode or not to use Master clock mode that is the question The 82532 operating in standard non master clock mode uses the transmit clock source refer to table 5 page 84 of the data sheet to run the internal timing of the chip If your transmit clock source is running very slow or it is not running continuously if external clock is supplied then it is a good idea to switch to master clock mode Each command issued to the 82532 any write to the CMDR register can take up to 2 5 clocks to complete If the clock is very slow or stops from time to time this can be a significant amount of time and allows for the possibility of a command being lost written but not executed because a previous command is not complete If
33. M ESCC 104 ET Three State output control disables output for test purposes Sophisticated internal loop filter requires no external components or manufacturing tweaks as commonly required with external filters Low power consumption makes device ideal for power and space critical applications Programmable using the FASTCOM ESCC 104 ET PVR register bits 1 and 2 see page 34 5 operation High speed CMOS technology DETERMINING AND SELECTING BAUD RATES Selecting the bit rate can either be very easy or quite complicated depending on a number of factors The best place to start is to determine the big picture broad perspective and narrow down the options using the various constraints that the hardware imposes There are four basic things that make up what the actual bitrate will be They are 1 Register settings of the 82532 chip These include A Operating mode HDLC Bisync Async 1 If async is used is it truly async oversampled BCR 1 or 2 isosynchronous async format with no oversampling B Clock mode internal or external clocks 1 If internal clocks does it use clock recovery DPLL 2 If BGR is used is the BDF bit 1 or O 2 The setting of the clock generator ICD2053B that feeds the OSC input to the 82532 only a factor if an internal clock mode is used i e BGR or DPLL is involved 3 The physical switch settings of the Fastcom ESCC 104 ET A The switch determines the routing of the TXCLK pin as either an input
34. Selecting 485 clock output mode will disable the DTR line at the connector 18 PROGRAMMING Refer to the ESCC 104 ET Tools on the enclosed FASTCOM CD for example programs product updates and software for testing your installation Refer to the Siemens SAF 82532 User s Manual for register information NOTES Do not select the same channel for both DMA receive and DMA transmit Always set the 82532 port configuration register PCR to Always set the 82532 interrupt port configuration IPC to 03H Always set the 82532 CCR1 ODS bit to 1 Revision 3 2A of the Siemens 82532 utilizes both standard and enhanced modes of the Baud Rate Generator Register BGR In standard mode the following formula is used to calculate the divisor for baud rate generation N 1 2 The following hexadecimal values of N are equivalent to N equaling zero 0x000 0x100 0x200 0x300 0x040 0x140 0x240 0x340 0x080 0x180 0x280 0x380 0x0CO 1 0 2 0 0x3C0 This is a known bug of the 82532 19 e RS 422 RS 485 Most engineers have worked with RS 232 devices at least once in their career If you have never worked with RS 422 or RS 485 devices you will be pleased to know that working with the FASTCOM ESCC 104 ET is not much different from working with an RS 232 device The RS 422 standard was developed to correct some of the deficiencies of RS 232 In commercial and industrial applications RS 232 has some significant problem
35. aaaaaaaa 12 complete lines and one partial line of a s 1024 of them The last character is not an a 7 Press esc to exit the program You can test channel 1 in a similar manner by running D fastcom_disks escc nt escctest escctest 1 he You can test other operating modes by changing the last letter async test D fastcom_disks escc nt escctest escctest 0 a HDLC test D fastcom_disks escc nt escctest escctest 0 h Bisvnc test D fastcom_disks escc nt escctest escctest O b In async you will get a STATUS Receive Timeout after the All sent message and possibly at the beginning before you press a key The bisync test will get a STATUS SYN detected instead of a receive frame start message The async test should receive 1024 bytes displayed as 12 8 lines of the key you pressed The HDLC test should receive 1025 bytes displayed as 12 8 lines of the key you pressed The bisync test should receive 1025 bytes displayed as 12 8 lines of the key you pressed The exceptions to this are the keys t r i p and h pressing t will reset the transmitter and flush the transmit queue pressing r will reset the receiver and flush the receive queue pressing i will start the timer which will eventually result in a STATUS Timer expired message It takes about a minute in HDLC mode for the timer to timeout pressing p will stop the timer which will prevent the STATUS Timer expired message pressing h will issue a hunt command in bisync
36. e looped back However we recommend that you make the loop back plug for two reasons one the clock circuit can be tested and two you will not have to change switch settings from the factory defaults In addition our technical support engineers can better service your technical questions if you have made the loop back plug If you have made the loop back plug do not change the setting of the Mode switch Fastcom ESCC 104 ET Windows NT 2000 Test 1 Make sure that the driver was installed with DMAT DMAR 0 as the test program was compiled to run in interrupt mode 2 Attach a loopback plug to the cable 1 ESCCO port 0 3 From the Start button menu select Run Enter Difastcom diskstesccintisetfs6131clockisetfs6131clock O 2000000 4 From the Start button menu select Run 10 Enter D fastcom_disks escc nt escctest escctest he Click the OK button 5 After answering the question about the clock you should see Created esccdrv ESCCO 5 82532 version status 82 receive buffers 0 resetting HDLC settings SETTINGS SUCCESSFUL 168 DTR SET DSR not SET DTR not SET DSR not SET waiting for a key read thread started status thread started The first DSR not SET could be a DSR SET if you have a DTR DSR loopback wired 6 Press the letter a on the keyboard You should see WRITEFILE esccdrv1024 returned TRUE waiting for a key STATUS Receive Frame Start STATUS All Sent received 1025 bytes aaaaa
37. e s that you enter for DMAR and DMAT will determine if the driver uses DMA or not If they are both zero then DMA is not used interrupt only mode If they are both nonzero and not equal i e DMAR DMAT 0 then DMA mode is used The example program is compiled assuming that DMA is not used i e DMAR DMAT 0 Specifically the DMA bit in the XBCH register of the 82532 is clear indicating that the 82532 should operate in interrupt only mode You can manually add delete these registry entries if you wish But earlier version s of the driver will crash if you do not define any boards and start stop start the driver You can manually add a value in the esccdrv parameters ESCCx subkey Buffers REG DWORD OxYY This controls the number of receive buffers frames that the driver will allocate and use The default value is 10 and can be any value from 2 to 100 REMOVE BOARD Pressing this button will delete the subkey and its values for the selected board channel START Pressing this button will load the driver It is equivalent to using Control Panel gt Devices Start with the esccdrv selected STOP Pressing this button will stop unload the driver It is equivalent to using Control Panel Devices Stop gt with the esccdrv selected REMOVE DRIVER Pressing this button will attempt to stop the driver if it is started and will delete the esccdrv subkev and all of its subkeys It will not delete the
38. es a clock with its data receive clock and that we need to generate transmit a clock that matches our transmitted data To achieve this we should set the 82532 to clock mode Ob Set the mode switch position 5 or 7 to on enabling the txclk output driver selecting txclk as an output on The baudrate function bitrate input clock N 1 2 will be used If there are no other constraints other than operating one channel at 19200 bps then we can select both the input clock and N arbitrarily so long as we do not violate any of the notes So by selecting a value for input clock that is less than 10 MHz since the bit rate is slow we will want to use master clock mode which will require a 10 MHz or less clock we can then calculate the value needed for N to get a 19200 output will pick 7 372800 MHz for the input clock Solving for N we get 19200 7 3728E6 N 1 2 191 OxOBF Checking the notes to make sure we did not violate anything Fm Fx 7 3728E6 19200 384 gt 2 5 we are OK on this one Fr Fm rxclk input 7 3728E6 3 assuming a 19200 clock input 19200 7 3728E6 0026 3 we are OK on this one OxOBF amp Ox3f lt 0 checking the value of n to make sure it isn t forced to zero due to the glitch in the 82532 Important Register Settings MODE 0x88 This sets the 82532 in transparent HDLC mode 0 This will use a frame structure as Ox7E data CRC CRC 0 7 No address recognition is
39. functions are similar to the async case If you are not using a clock mode that uses the DPLL the formula is bitrate input clock BGR If you are using the DPLL the formula is bitrate input clock BGR 16 The input clock will depend on the clock mode It is usually either the OSC input or the RXCLK RT input see table 5 page 84 of the 82532 data sheet If BDF 1 BGR 1 If BDF 0 BGR N 1 2 If BDF 0 and EBRG 1 BGR 1 2 V 3 x of the 82532 silicon only The BDF bit is in CCR2 bit 5 CCR280xC0 lt lt 2 BGR or if you prefer Most significant bit Least significant bit m CCR2 bit 8 CCR2 bit 7 BGR bit 7 BGR bit 6 n BGR 5 BGR 4 BGR 3 BGR 2 BGR 1 BGR 0 N CCR2 8 CCR2 7 BGR 7 BGR 6 BGR 5 BGR A BGR 3 2 BGR 1 BGR 0 If you are using the DPLL you should try to set its input clock to be as close to the actual bit frequency as possible This will allow for optimal clock recovery Also clock recovery relies on edges in the data stream if you gt 24 Ta aa transmit long segments of Os or 1s using an encoding method that produces no edges the results will be non optimal The ideal encoding for clock recoverv is Manchester or a non 1 idle pattern i e constant flag sequences on idle if HDLC is used etc Let s start with something easv Let s sav that vou want to set up an ESCC channel to run in HDLC mode at 19200 bps that the device in question suppli
40. lled in your system FASTCOM ESCC 104 ET ADDRESS SWITCH SETTINGS ADDRESS SWITCH 1 POSITION 1 ON 0 OFF Hex Decimal 2345678 Hex Decimal 12345678 b f Go didaddda 8005 2048 11111011 40 6 01111111 8400 2112 011110 80 128 10111111 880b 217 101110 ch 192 00111111 8cOh 2240 001110 1008 256 11011111 900h 2304 110110 1406 320 01011111 940h 2368 010110 1800 385 10011111 9806 2432 100110 1208 448 00011111 9c0h 2496 000110 a300 512 11101111 00 2560 111010 2406 576 01101111 40 2624 011010 280b 640 10101111 2688 101010 2c0h 700 00101111 2752 001010 3006 768 11001111 boh 2816 110010 3406 832 01001111 b40h 2880 010010 380h 890 10001111 bB0h 2944 100010 3e0h 960 00001111 beoh 3008 000010 400h 1024 11110111 c00h 3072 111100 4406 1088 01110111 40 3136 011100 4806 1152 10110111 3200 101100 1216 00110111 ech 326 001100 5006 1280 11010111 dob 3328 110100 5406 1344 01010111 40 3392 010100 580h 1400 10010111 3456 100100 Sch 14722 00010111 35200 000100 600h 1536 11100111 e00h 3584 111000 6406 1600 01100111 e40h 36489 011000 680h 166 1
41. nd the second channel synchronously using HDLC at 2 Mbps How would you go about it Start with the fastest bit rate and determine if there is an external clock that is received with that data or if the clock must be recovered DPLL mode Let s say that you want to recover the clock from the data there are no clock lines in the system and that the data is Manchester encoded To get a 2 Mbps clock rate using a DPLL we will need to use the bitrate input clock 1 16 function This will require a 32 MHz input clock Use the following register settings MODE 0x88 CCRO 0x98 CCR1 0x16 CCR2 0x18 CCR3 0x00 CCRA 0x00 The receive source will be recovered from the data stream The transmit source will be the BGR 16 output Now for the async channel We are locked into the 32 MHz input clock so we will try to find a value for N that gets our desired 38400 bps 38400 32E6 16 N 1 2 25 04 we cannot attain non integer values for If we use 25 we would get bitrate 32E6 16 25 1 2 38462 bps If we use 26 we would get bitrate 32E6 16 26 1 2 37037 bps Using the closest value and setting the registers to MODE 0x08 CCRO 0xC3 CCR1 Ox1F CCR2 0x38 CCR3 0x00 7 gt 26 CCRA 0x80 and BGR 0x19 will yield an asynchronous data format with 16X oversampling at about 38400 bps If later you decide that you need to get 115200 bps on the async channel you
42. or output B The switch also determines if the OSC is fed the output of the clock generator or just the output of the onboard clock an option on the ESCC PCI and the HSCX the ESCC 104 ET does not have this option 4 revision of the ESCC 82532 chip silicon A Therev 3 2 silicon incorporates an enhanced baud rate mode We will start with the simplest case If you are using the Asynchronous data mode then the most likely clock mode that you should use is 7b It is possible to use the other clock modes however mode 7b is the most straightforward to work with The bitrate will be determined by the output of the baud rate generator The baud 9 2291 II P LLP C UGCILLLLLGCOLLLL e KC L LLLUL L B LL 7 gt 22 DO DDIOL L BLLDLDLDLLL BLL T ILLLLILIu rate generator is clocked by the OSC input which is set by the ICD2053B clock generator So you have If you are not using oversampling BCR 0 the formula is bitrate input clock If you are using oversampling BCR 1 the normal case for async the formula is bitrate input clock BGR 16 If BDF 0 then BGR 1 If BDF 1 then BGR N 1 2 If BDF 1 and EBRG 1 then BGR 1 2 The BCR bit is in CCR1 bit 3 The BDF bit is in CCR2 bit 5 The EGRG bit is in CCR4 bit 6 N CCR2 amp 0xC0 2 BGR or if you prefer Most significant bit nn Least significant bit n BGR bit 5 BGR bit 4 BGR bit 3 B
43. rough A13 are decoded by the setting of SW1 and set the base address of the FASTCOM ESCC 104 ET Address lines 0 5 are used on the board to select configuration and control registers on the 82532 chip Address Line Hex value A13 2000 The above diagram illustrates a base address of 280 Hex factory A12 1000 default Note that when a switch is ON it represents a in the 11 800 corresponding bit position not 1 as you might expect Also a 10 400 Switch that is OFF represents a 1 in the corresponding bit A9 200 position If you would like to know why this is reversed read the A8 100 technical data for the address decoder chip 7415682 AT 80 A6 40 So the SW1 diagram can be decoded as follows 2 11 0 2 AG o 0 O 1 1 0 You can determine the address of the board by adding the Hex values for each address line that is set to 1 In the illustration only address lines A9 and A7 are set to 1 So add the Hex value of A9 200H and A7 80H and the result is the base address 200H 80H 280 We have provided a comprehensive guide to setting the address switch in Appendix B Please note that not all of the address space in a PC is available for your use We have selected 280H as a default because it does not conflict with devices normally installed in a PC However if you wish to select another address select an address that does not conflict with devices in
44. s First the cable length between RS 232 devices must be short usually less than 50 feet at 9600 Baud Second many RS 232 errors are the result of cables picking up normal industrial electrical noises such as fluorescent lights motors transformers and other EMF sources Third RS 232 data rates are functionally limited to 19 2K Baud On the other hand the newer RS 422 standard makes cable lengths up to 5000 feet possible and is highly immune to most industrial noises Data rates are also improved the FASTCOM ESCC 104 ET features data rates up to 10 Mega Baud These improvements were made possible by differentially driving and receiving the data as opposed to the single ended method employed by the RS 232 standard With the RS 422 standard the transmit signal TX in RS 232 is a differential signal consisting of SD and SD the receive signal RX RS 232 consists of RD and RD Another draw back of RS 232 is that more than two devices cannot share a single cable This is also true of RS 422 and that s why the RS 485 standard was developed RS 485 offers all of the benefits of RS 422 and also allows multiple units up to 32 to share the same twisted pair RS 485 is often referred to as a multi drop or two wire half duplex network because the drivers transmitters and receivers share the same two lines In fact up to 32 stations can share the same twisted pair In order for an RS 485 system to work only one driver transmitter
45. s the same part The result is that while the baud rate generators are unique on a per channel basis the OSC input is not i e the baud rate generators are independent but the clock that feeds them is the same If you change the clock generator output you will change the input clock to both channels The practical thing to note about this is that if you have multiple baud rates that must be generated on multiple channels you should select the input clock FS6131 01 output such that all baud rates can be derived from one clock value Changing the clock generator output will affect the baud rates of both channels 5 EXAMPLES AND EXPLANATIONS If you are using HDLC or Bisync as a data format there is not a BCR setting no oversampling However if you select a clock mode that uses the DPLL as a source it will effectively add a divide by 16 to your function Selecting the appropriate clock mode is a matter of identifying what clock signals are available external to the Fastcom card and what clock signals are required by the external device The simplest mode is using external clocks only mode 0a in this mode both the receive and transmit timing are taken from the connector RT for receive ST for transmit The rest of the modes are a mix of external signals and internally generated clocks clock recovery The DPLL modes only operate up to 2 MHz If the bitrate is above that you should use a non DPLL mode The bitrate
46. stalled in your PC Keep in mind that the FASTCOM ESCC 104 ET requires 34 contiguous bytes of address space If you want to install more than one FASTCOM ESCC 104 ET board in your computer be sure to set each to a unique address We recommend the following addresses for a multi board system FASTCOM ESCC 104 ET BOARD 1 280H FASTCOM ESCC 104 ET BOARD 2 2C0H FASTCOM ESCC 104 ET BOARD 3 300H Remember that a single IRQ level can be shared by multiple FASTCOM ESCC 104 ET boards in a PC and that DMA channels cannot be shared 15 e SWITCHES 2 AND 3 INTERRUPTS Switches 2 and 3 serve two functions they select the IRQ level for the FASTCOM ESCC 104 ET and enable disable interrupt sharing The following illustrates the IRQ select switch on the FASTCOM ESCC 104 ET IRQ SELECT ON ON 1234 12345 678 IRQ LEVELS IRQ LEVELS BOARD BOARD 1 SHARE Select only 1 IRQ level at a time SWITCH PC AT 386 POSITION IRQ Assigned 2 9 UNUSED 3 3 COM2 4 4 1 5 5 UNUSED LPT2 6 6 FLOPPY 7 7 LPT1 1 10 UNUSED 2 11 UNUSED SAA 3 12 UNUSED 4 15 UNUSED You can use any IRQ that is not assigned to a device installed in your PC INTERRUPT SHARING An important feature of the FASTCOM ESCC 104 ET is its ability to share one IRQ level with several FASTCOM ESCC 104 ET boards in the same compu
47. ter This is important because there are very few unassigned in the PC Switch 3 positions 1 and 8 control the interrupt sharing circuit on the FASTCOM ESCC 104 ET Position 1 Enables interrupt sharing in the OFF position and Disables sharing in the ON position Position 8 is called the Board 1 switch In the interrupt sharing mode this switch must be ON for the first FASTCOM ESCC 104 ET board in your system and OFF on all other FASTCOM M ESCC 104 ET boards Switch 3 Position 1 8 ON OFF Disables sharing OFF Enables IRQ sharing first board OFF OFF Enables IRQ sharing second board For example let s assume that you have two FASTCOM ESCC 104 ET boards in your PC and want to share IRQ 5 Set Switch 3 as follows for the first board Any additional FASTCOM ESCC 104 ET boards that share IRQ5 would be set the same as the second board SwiTCH 4 DMA CHANNEL SELECT The DMA Select switch sets the DMA receive and transmit channels Do not set the transmit and receive channels to be the same It is not possible to set and use the transmit and receive channels as the same DMA channel If the same DMA channel is selected for more than one function TX RX Channel 1 Channel 2 that DMA channel will be disabled DMA Channel 1 3 5 7 Tiansmit4 Position 5 On On Off Off 12345 67 8 Position 6 On Off On Off l Position
48. xample program esccmfc The only devices that would be available would be ESCCO and If you try to open ESCC2 or ESCC3 you will get a can t get a handle message To use ESCC2 or ESCC3 you must press the STOP ESCCDRV button and then press the START button or reboot to allow the driver to recognize the additional board TESTING THE INSTALLATION To fully test the installation of your FASTCOM ESCC 104 ET you will need to build two loop back plugs Materials needed are two 40 pin female receptacles 24 pins and 12 short pieces of 20 or 24 AWG stranded wire Jumper the pins together on the 40 pin connecter according to the diagram below in order to loop the signals on both channels 0 and 1 LOOPBACK CONNECTOR CONFIGURATION BLUE CH1 RED 4 L SEL m HERA ree Th p 39 37 35 33 31 29 27 25 23 21 19 17 15 13 40 38 36 34 32 30 28 26 24 22 20 18 16 14 zzz CHANNEL 0 SIGNALS 16 17RD 6RT 5 7DSR 23DCD BLUE 3250 31SD 36 TT 35TT 37DTR 40 CHANNEL 1 SIGNALS 8RD 9RD 2RT 4DSR 15DCD RED 2450 25SD 28TT 29TT 30DTR 1GND NOTE You can also create a loop back condition on the FASTCOM ESCC 104 ET without building an adapter plug by setting the Mode 2 Switch SW6 as follows MODE 2 1234567 8 Both ESCC channels ar
49. your baud rate is slow 1MHz or you are using a gated external clock you should use master clock mode to allow the interface to the 82532 to continue to execute quickly If this mode is used then the OSC input must be less than 10MHz the speed rating of the internals of the 82532 If you have a 82532 rev 3 x silicon then you can cause the master clock to be OSC 4 by setting CCR4 bit 7 MCKA thus allowing the 10MHz restriction to be lifted If you are using a clock mode that uses external clocks you should respect the restriction on the ratio of receive to transmit clock frequency given in note 2 of table 5 Freceive Ftransmit 3 or 1 5 If you are running in not extended baud rate mode do not set BGR bits 5 0 to all 0 or the chip will assume that all of the BGR bits are O This is a glitch in the 82532 rev 3 2 and makes the following values for N identical 0 000 0 040 0 080 0 0 0 0x100 0x140 0x180 0x1C0 0x200 0x240 0x280 0x2C0 0x300 0x340 0x380 0x3C0 EE AAA gt 23 Setting the baud rate generator to any of these values will produce the same affect as setting it to 0 000 If you use the Enhanced baud rate generator and set m 0 the clock output will be asymmetric non 50 50 duty cycle AN IMPORTANT FACT ABOUT THE CLOCK GENERATOR There is only one FS6131 01 part and only 1 OSC input to the 82532 chip The clock generator can be programmed from either channel ESCCO or ESCC1 but it program
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