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5.1 Programming the SMCS116SpW

1. All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS ASTD UM 116 EADS sii U M l Rev 1 2 Ssstriom ser Manua Date 16 06 2008 Page 23 of 157 5 2 Programming the SMCS116SpW with STUP The STUP Serial Transfer Universal Protocol is implemented to support logical addressing The protocol identifier PID of STUP is 239 dec or OxEF hex 5 2 1 Switching between STUP Mode and old SMCS116 protocol mode The SMCS116SpW will start in the SMCS116 mode after reset and has to be switched to the STUP Mode if desired This is necessary to be compliant with existing software that controls the SMCS116SpW over the SpaceWire The SMCS116SpW can be switched into STUP Mode see figure below by the following steps 1 via SpaceWire e first packet should be a READ command to register Ox7C This READ command has to be at least 4 or more bytes long with the logical address OxFE and the protocol identifier OXEF c Bit DO of Protocol Control Register 0x79 is set to 1 automatically Read Command OxFE OxEF OxXX OxFC 0 or more bytes EOP e setting Bit DO of Protocol Control Register 0x79 to 1 with an write command 2 via Host IF e setting Bit DO of Protocol Control Register 0x79 to 1 All Rights Reserved Copyright per DIN 34
2. All Rights Reserved Copyright per DIN 34 SMCS116SpW Doc No Rev Astrium GmbH SMCS_ASTD_UM_116 EADS Deg User Manual pe Address Register Description r w 0x6B RES5 reserved r 0x6C RES6 reserved r 0x6D RES7 reserved r 7 1 16 UART2 Registers Address Register Description r w Ox6E UART2_TD TxD2 Transmit data over signal TxD2 W Ox6F UART2_RD RxD2 Received data from signal RxD2 r 0x70 UART2 BR1 Baud rate 1 Byte low r w 0x71 UART2_BR2 Baud rate 2 Byte high r w 0x72 UART2 CTRL Control Register r w 0x73 UART2_ST Status r 0x74 UART2_PORT UART2 port address link only 7 1 17 SpaceWire TIMECODE Registers Address Register Description r w 0x75 TIME_CNTRL Time code control register r w 0x76 TIME CODE Time code value register r w 0x77 RES8 reserved r All Rights Reserved Copyright per DIN 34 EADS _ eeabri rnm Astrium GmbH SMCS116SpW DocNo SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 41 of 157 7 1 18 STUP Registers Address Register Description r w 0x78 P MODE EN Protocol Mode Enable Register r w 0x79 P_CONTROL Protocol Control Register r w Ox7A P ART ADDR Alternative Return Address Register default r w OxFE Ox7B P RT SELECT Return Select Register r w Ox7C P LOG ADDR Logical Address R
3. Astrium GmbH SMCS116SpW B No SOS ASTON 16 EADS User Manual Date 16 08 2008 eezbrium Page 24 of 157 SMCS116Spw RESET Read command to 0x7C 4 Bytes or more second byte Protocol ID First Sow Packet v New Protocol Old SMCS116 m Nad Mode H otocol Sele Set Four aS DO 5 2 2 Write internal SMCS116SpW registers Write on SMCS116SpW Register Logical Address Protocol ID Return Address Command amp Register Address Data 1 or more Checksum Checksum EOP byte Note SMCS116SpW ignores dummy bytes Byte 4 defines whether a write D7 0 or a read D7 1 command is performed Checksum is appended when checksum generation is enabled All Rights Reserved Copyright per DIN 34 SMCS116SpW Doc No SMOS ASTD UM 1 16 EADS E rot User Manual p 16 08 2008 Example Enable RAM IF Ox7E OxEF 0x20 0x00 0x98 EOP Ox7E Ox74 0x20 0x01 0x01 EOP Write on SMCS116SpW Port Logical Address Protocol ID Return Address Port Address Data Data Data Data Data Data Data Data or more byte Checksum Checksum EOP Example Write on RAM IF Data PORT Ox7E OxEF 0x20 0x43 OxAA OxAA OxAA OxAA OxAA OxAA OxAA EOP All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS116SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS brni User Manual p 16 08 2008 5 2 3 Read internal SMCS1
4. Astrium GmbH Doc No SMCS_ASTD_UM_116 SMCS116SpW a LE EADS _ User Manual Date 16 06 2008 asb riur Page 1 of 157 SMCS116SpW ty C nntrnlla wf BZ BS RSR d se KS Beie User Manual Prepared U Liebst ckel ASE232 Date by System Engineer 7 6 0f Checked P Rastetter ASE232 by System Engineer P Castitas zum Ad 6 og Checked J Holthaus ASQ22 5 ate by PA P2 f o6 ov GE Released Dr S Fischer ASE213 Date by Project Manager Lgs 4 6 74 Ok All Rights Reserved Copyright per DIN 34 EADS _ aa aseritum SMCS116SpW User Manual Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 2 of 157 Document Revision History Revision Date Responsible Modifications 1 0 July 2007 P Rastetter First release 1 1 October U Liebst ckel Update in chapter 8 6 time code 2007 control register TIME CNTRL Chapter 12 14 and 12 15 Add new timing figures for FIFO interface passive write and FIFO interface passive read 1 2 June 2008 U Liebst ckel Chapter 5 2 1 Replace Protocol Select Register by Protocol Control Register Chapter 7 1 4 Replace Header x register by Packet Header x register Chapter 7 1 6 Replace ADC PSIZE by ADC TEST Chapter 8 2 3 Table change description of D1 in register ISR 1 Add description of D1 in re
5. HFIFO_PORT Host FIFO port address link only 7 1 12 UART1 Registers UART1_BR2 Baud rate 2 Byte high UART1_CTRL Control Register sone i en r Sms UART1 PORT UART 1 port address only All Rights Reserved Copyright per DIN 34 EADS a eeabri rm Astrium GmbH Doc No Rev Date Page SMCS116SpW 1 2 User Manual 16 06 2008 39 of 157 SMCS ASTD UM 116 7 1 13 Interrupt Mask Registers Address Register Description r w 0x5C IMR O Interrupt mask register bit 7 0 r w Ox5D IMR 1 Interrupt mask register bit 15 8 r w Ox5E IMR 2 Interrupt mask register bit 19 16 r w 7 1 14 Interrupt Status Registers Address Register Description r w Ox5F ISR 0 Interrupt status register bit 7 0 r 0x60 ISR 1 Interrupt status register bit 15 8 r 0x61 ISR 2 Interrupt status register bit 19 16 r 7 1 15 GPIO Registers Address Register Description r w 0x62 GPIOO DIR GPIOO direction register mapped on GPIO7 GPIOO r w 0x63 GPIOO DOUT GPIOO data out register r w 0x64 GPIOO DIN GPIOO data in register r w 0x65 GPIO1 DIR GPIO1 direction register mapped onto IOB7 IOBO r w 0x66 GPIO1 DOUT GPIO1 data out register r w 0x67 GPIO1 DIN GPIO1 data in register r w 0x68 GPIO2 DIR GPIO2 direction register mapped onto hdata r w 0x69 GPIO2 DOUT GPIO2 data out register r w Ox6A GPIO2 DIN GPIO2 data in register r w
6. amp GPIO Output Enable1 All Rights Reserved Copyright per DIN 34 EADS ada eeabri rnm SMCS116SpW User Manual Astrium GmbH Doc No SMCS ASTD UM 116 Rev 1 2 Date 16 06 2008 Page 149 of 157 62 63 64 72 T3 74 82 83 84 BC 1 GPIO 1 output3 X 58 BC 1 GPIO 1 input X amp BC 1 BC 1 GPIO 0 output3 X 61 BC 1 GPIO 0 input X amp BC 1 control 0 BC 1 DATA 15 output3 X 64 BC 1 DATA 15 input X amp BC 1 DATA 14 output3 X 64 BC 1 DATA 14 input X amp BC 1 DATA 13 output3 X 64 BC 1 DATA 13 input X amp BC 1 DATA 12 output3 X 64 BC 1 DATA 12 input X amp BC 1 DATA 11 output3 X 64 BC 1 DATA 11 input X amp BC 1 DATA 10 output3 X 64 BC 1 DATA 10 input X amp BC 1 DATA 9 output3 X 64 BC 1 DATA 9 input X amp BC 1 DATA 8 output3 X 64 BC 1 DATA 8 input X amp BC 1 DATA 7 output3 X 64 BC 1 DATA 7 input X amp BC 1 DATA 6 output3 X 64 BC 1 DATA 6 input X amp BC 1 DATA 5 output3 X 64 BC 1 DATA 5 input X amp BC 1 DATA 4 output3 X 64 BC 1 DATA 4 input X amp BC 1 DATA 3 output3 X 64 BC 1 DATA 3 input X amp BC 1 DATA 2 output3 X 64 BC 1 DATA 2 input X amp 0 0 0 0 Hre control 0 amp GPIO Output Enabled Z amp amp DAT
7. amp IOB Output Enable 119 BC 1 I1OB18 output3 X 118 0 Z amp 120 BC_1 10B18 input X amp 121 BC 1 control 0 amp IOB Output Enable 122 BC 1 1OB17 output3 X 121 0 Z amp 123 BC 1 1OB16 output3 X 121 0 Z amp 124 BC 1 control 0 amp IOB Output Enable 125 BC 1 IOB15 output3 X 124 0 Z amp 126 BC 1 IOB15 input X amp All Rights Reserved Copyright per DIN 34 EADS asbmrium SMCS116SpW User Manual Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 151 of 157 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 BC_1 BC_1 I10B14 BC_1 BC_1 10B13 BC_1 10B12 BC 1 IOB11 BC_1 10B10 BC_1 IOB9 BC_1 IOB8 BC 1 BC 1 IOB7 BC 1 IOB7 BC 1 BC 1 lOB6 BC 1 IOB6 BC 1 BC 1 lOB5 BC 1 lOB5 BC 1 BC 1 OB4 BC 1 OB4 BC 1 BC_1 IOB3 BC 1 IOB3 BC 1 BC 1 lIOB2 BC 1 lIOB2 BC 1 BC 1 IOB1 BC 1 IOB1 157 BC 1 158 BC 1 IOBO 159 BC 1 IOBO end SMCS116SPW eee eee eee output3 X 127 output3 X 129 output3 X 129 output3 X 129 output3 X 129 output3 X 129 output3 X 129 output3 X 136 input X amp output3 X 139 input X amp output3 X 142 input X amp output3 X 145 input
8. 1 2 EADS rent User Manual Date 16 06 2008 Page 88 of 157 9 6 5 ADC timing requirements If an Analogue Digital converter requires a minimum pulse width and or a minimum setup time bit 3 0 of register ADC_CTRL1 0x22 can be used to fulfil these requirements If the values for minimum pulse width and minimum setup are different the longer value has to be taken because there is only one counter to generate both timings The minimum pulse of ADC CS is one clock cycle nom 40 ns The minimum setup of ADC R C before falling edge of ADC CS is one clock cycle nom 40 ns To generate extended timings the wait state register can be loaded with any value between 0x1 and OxF For example a value of 2 generates a minimum setup and minimum pulse of 120 ns formula 1 2 x 40 ns 120 ns The maximum setup and pulse width which can be generated is 640 ns ADC CTRL1 D3 DO IlOBS ADC CS ADC_CTRL1 D3 DO setup IOB9 ADC R C 9 6 6 Sequence for Analogue Digital Conversion 9 6 6 1 Sequence for scanning multiple analogue signals with an external analogue multiplexer channel 1 10 Enable the ADC I F 1 write 0x98 to register ENABLE 0x00 2 set bits D2 1 and DO 0 in register IFCONF 0x01 xxxx x1x0 Configure ADC I F 3 write 0x40 to register ADC_CTRLO 0x21 o send port address ADC_SEL EOP 16 Bit o enable mux address generation Load number of first channel 4 write 0x01 to registe
9. 31 DATA0 15 inen IOB25 Sch ber BUS REQ Description Symbol Min 5 V t 3 3 V e CS0 o ag WR RD ADDRO 15 and DATAO tRBRS 184 ws 40 84 356 ws 80 ns 15 disable after BUS EE active low CS0 3 WR RD ADDRO 15 and DATAO tRBRA 15 enable after BUS_REQ inactive high Note ws wait states 0 7 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 125 of 157 12 10 RAM interface external control read RETH IOB26 START_TRM CS0 3 RD IOB23 TRM RDY Description Symbol Min 5 V me E SS START START_TRM high active pulse with START_TRM high active pulse with active pulse width mem men Je fos START_TRM low inactive pulse width tRETL Gr first read access CS0 3 RD low active after tRETC 120 1 240 ns START TRM high TRM RDY transmit ready high active after the tRETR 160 1 320 1 ns last read from memory time between the rising edge of TRM_RDY and tRETS the next start rising edge from START_TRM TRM_RDY hold after START_TRM high mem mem im pe Note 1 Depends on o data bandwidth over the SpaceWire link o simultaneous read from the memory with wait states All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMC
10. All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS ASTD UM 116 EADS sot User Manual ds aT asSsCrmium Page 141 of 157 Bom m Je Jk Jess B es Jk ck ms B ee ke km B fen k Jk fe B ees e emm je ow Bo ees fe Je pe B je k je Bo Jee je em 1 1 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS so User Manual Date 16 06 2008 aescCrmium Page 142 of 157 14 Additional Information 14 1 BSDL File for the SMCS116SpW BSDL for SMCS116SpW Uses HP s BSDL format and compiles correctly using HP s parser or compiler of JTAG Technologies Author Paul Rastetter Astrium GmbH Tel 49 89 607 25015 Fax 49 89 607 28964 e mail paul rastetter astrium eads net date entity SMCS116SPW is generic PHYSICAL PIN MAP string UNDEFINED PORT CLK IN bit HDATNADR IN bit HWRNRD IN bit LDI IN bit LSI IN bit NHSEL IN bit NRESET IN bit TRST IN bit RXD IN bit TCK INbit TDI IN bit TMR1 CLK IN bit TMR2 CLK IN bit TMS INbit iob25 IN bit iob26 IN bit iob27 IN bit LDO OUT bit All Rights Reserved Copyright per DIN 34 EADS asbmrium SMCS116SpW User Manual Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 143 of 157 LSO OUT bit NHINTR O
11. 0 old SMCS116 mode default after Reset 1 STUP Protocol Mode D1 enable transmit the new former return logical address twice since at the SMCS332SpW in Routing mode the first byte is deleted This would destroy the data to be WORD aligned and lead to a wrong Checksum D2 0 HOST FIFO transparent mode 1 At the start of a HOST FIFO packet a STUP protocol header is set D6 D3 reserved D7 test mode read write current return address r w Ox7A P ART ADD R Alternative Return Address Register D7 DO Alternative Return Address default OXFE r w All Rights Reserved Copyright per DIN 34 EADS a eeabriL rm Astrium GmbH SMCS116SpW DocNo SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 50 of 157 Address Register Description r w 0x7B P_RT_SELEC T D1 D7 DO D2 D3 D4 D5 D6 Return Select Register Default 0x00 selects the return address 0 last received return address default 1 content of Alternative Return Address Register for the SMCS116SpW interfaces RAM IF FIFO IF ADC IF HOST FIFO UART1 IF UART2 IF Interrupt controller always 0 r w Ox7C P LOG ADD R Logical Address Register D7 DO logical Address default OXFE r w All Rights Reserved Copyright per DIN 34 EAD
12. 1 2 EADS User Manual Date 16 06 2008 aseritum Page 78 of 157 9 5 3 FIFO interface signals 9 5 3 1 Active mode In the SMCS116SpW FIFO active mode the SMCS116SpW FIFO controller reads and writes from to an external FIFO Register FIFO CTNRL 0x1B DO 01 9 5 3 1 1 Read data from the FIFO Signal FIFO I F UO Description signal IOB 18 RD O Read strobe IOB 20 FIFO EMPTY FIFO empty signal IOB 15 EOPL UO When F CTRL D4 1 Marker signal of the EOP EEP character on the low data byte DO D7 IOB 27 TRM PAR When E CTRL D4 0 Data parity signal if parity check enabled Register F TRM OCNTL 0x19 Bit D6 1 EOPH UO When F CTRL D4 1 Marker signal of the EOP EEP character on the high data byte D8 D15 DATAO DATAO 15 l O Z Data lines 0 15 15 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 astcrmitum Page 79 of 157 The signals below are enabled active when F TRM CNTL Bit D3 0 and F_CTRL Bit D4 0 IOB 24 TRMEOP End of packet signal if FIFO EMPTY active low the FIFO controller generates an EOP character for the SpW link IOB 25 TRMEEP Error End of packet signal if FIFO EMPTY active low the FIFO controller generates an EEP character for the SpW link IOB 14 TRM EOP ACK TRMEOP TRMEEP acknowledg
13. 5 V 3 3 V 3 3 V mme Je eee p o meme m EE ELE ADC ADC_RDY high to ADC_R C high ADC_RDY high to ADC_RIC high to ADC_R C high ADCR low hus dL EECHER ECG fs i zsm k KL Note ws wait states 0 to 15 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 asterium Page 132 of 157 12 17 DAC interface IOB10 DAC WR toacs tpacwr force ADDRO 2 DAC ADDRO 2 Addr vaid DATAO 15 Data valid Description Symbol Min Max Min Max 5 V 5 V 3 3 V 3 3 V DAC ADDR 0 2 and DATA 0 15 setup tDACS 34 ws 40 38 ws 40 63 ws 80 80 ws 80 ns before DAC_WR low DAC WR low pulse width HDACWR 40 ws 40 HDACWR 40 ws 40 41 ws 40 80 ws 80 B4 ws 8o ns B4 ws 8o ns Note ws wait states 0 to 15 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 EADS Rev 1 2 Sec User Manual Date 16 06 2008 E ES Page 133 of 157 12 18 Timer box TMRx_CLK TMRx EXP TCONFIG Bit D3 0 TMRx EXP TCONFIG Bit D3 1 Description Symbol Min 5 V ep ee SS KEEN EE mus e E EE TMRx EXP ccc NN after TMRx CLK tTEXP e high All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS ASTD UM 116 EADS WI U M l
14. 8 bit mode t t wg RRL wa RRH IOB18 CSO lopiycsi IT IOB20 CS2 IOB21 CS3 IOB16 WR lBI7ZRD III a RRA pja RRA p e Jan vatia addr eg addr vatia taps vL RA valid addr valid DATAO 7 UE o vai All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 123 of 157 16 bit mode Lon Lon 10B18 CSO IOB19 CS1 J IOB20 CS2 IOB21 CS3 IOB16 WR IOB17 RD Ate Bac mm aa taps La DATAO 15 lgl lgl Description Symbol Min 5 V me 3 3 V been oo 3 WR RD and ADDR valid active tRRL 41 ws 40 83 ws 80 2 low oo width CS0 3 WR RD and ADDR valid tRRH ns inactive high pulse width ADDRESS change tRRA 39 41 ws 40 78 84 ws 80 DATA setup before CS0 3 RD high or tRDS 14 30 ns new address on ADDRO 15 valid DATA hold after CS0 3 RD high or new tRDH address on ADDRO 15 Note ws wait states 0 7 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS rent User Manual Date 16 06 2008 Page 124 of 157 12 9 RAM interface external bus request oB LH L ioBigeS1 CH L iogocs2 L jopavess Ci as se KN FN lopiewR O J o L E IOB17 RD IOBO 15 ADDRO 15
15. Register ess 0x19 F_TRM_CTRL Description FIFO I F Transmit Control Register old SMCS116 mode F CTRL bit D4 0 DO Transmit START STOP bit 0 Stop transmit to SpaceWire UE 1 Start transmit to SpaceWire I F D1 External data bus width 0 8 Bit 1 16 bit D2 EOP selector not used D3 External control and status signals 0 enable 1 disable external control signals send packets of size F_PSIZE until DO 0 stop or send only one packet when D4 1 D4 Internal control D3 1 packet mode 0 continuous send more than one packet 1 single shot send only one packet reset bit DO D5 Header selection 0 send FIFO port address 0x1C as header byte 1 send no header D6 Parity check 0 no parity check 1 parity check odd parity over 8 16 bit D1 D7 reserved DO D1 D2 D4 D5 D6 D7 r w r w new SMCS116SpW F_CTRL bit D4 1 Transmit START STOP bit 0 Stop transmit to SpaceWire UE 1 Start transmit to SpaceWire I F External data bus width 0 8 Bit 1 16 bit EOP selector not used Packet mode enable 0 disable 1 enable send packets of size F PSIZE not used reserved Header selection 0 send FIFO port address 0x1C as header byte 1 send no header not used reserved All Rights Reserved Copyright per DIN 34 EADS aseritum SMCS116SpW User Manual Astrium
16. TMS TDI GPIO2 7 0 EXT IREQO EXT_IREQ1 TxD2 RxD2 GPIO1 7 0 ADC ADDR 7 O RAM ADDR 7 0 ADC CS RAM ADDR8 ADC BIC RAM ADDR9 DAC WR RAM ADDR10 DAC ADDRO RAM ADDR11 DAC_ADDR1 RAM_ADDR12 DAC ADDR2 RAM ADDR13 FIFO TRM EOP ACK RAM ADDR14 FIFO EOPL FIFO RCV PAR RAM ADDR15 FIFO RCVEOP RAM WR FIFO RCVEEP RAM RD RAM CSO FIFO RD RAM CS1 FIFO WR RAM CS2 FIFO EMPTY RAM CS3 FIFO FULL RAM TEST ADC RDY RAM TRM RDY ADC TRIG RAM RCV RDY FIFO TRMEOP RAM BUS REQ FIFO TRMEEP RAM START TRM FIFO BOCH EOP ACK RAM START RCV FIFO TRM PAR FIFO EOPH LDO LSO TMR1 EXP TMR2 EXP TxD1 IOB 7 0 IOB8 IOB9 IOB10 IOB11 IOB12 IOB13 IOB14 IOB15 IOB16 IOB17 TDO All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 106 of 157 BEEN pr HSEL when low the external host selects the SMCS116SpW host interface HWRnRD host interface write read signal if HWRnRD is high during HSEL low the host writes data to the address register or to the SMCS116SpW registers if HWRnRD is low during HSEL low the host reads data from the address register or the SMCS116SpW registers HDATnADR host interface data address signal if HDATnADR is high during read the host reads writes data from to the internal SMCS116SpW data registers if HDATnADR is low duri
17. j interface configuration register 7 1 2 Clock Control Registers Address Register Description r w 0x02 BITRATE select bit rate on SpaceWire link reset value 0x02 r w 0x03 RES1 Reserved r 0x04 RES2 Reserved r 0x05 RESS3 Reserved reset value 0x90 r 0x06 RES4 Reserved reset value 0x72 r All Rights Reserved Copyright per DIN 34 EADS a aseritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 33 of 157 7 1 3 SpaceWire Link Registers Address Register Description r w 0x07 MODE link mode register r w 0x08 START link start register r w 0x09 STATUS link status register r Ox0A LINKTEST link test register r w 7 1 4 Packet Header Registers Address Register Description r w OxOB HDRO Packet Header 0 register r w 0Ox0C HDR1 Packet Header 1 register r w OxOD HDR2 Packet Header 2 register r w OxOE HDR3 Packet Header 3 register r w OxOF HDR4 Packet Header 4 register r w 0x10 HDR5 Packet Header 5 register r w 0x11 HDR6 Packet Header 6 register r w 0x12 HDR7 Packet Header 7 register r w 0x13 HDRCTRL Packet Header control register r w 0x14 CHKEN Enable Checksum generation r w All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS Kapi User Manual
18. means transmit full data received parity error stop bit received parity error stop bit error error transmit FIFO empty D1 UART2 interrupt D1 UART2 interrupt note means transmit full data note means transmit full data received parity error stop bit received parity error stop bit error error transmit FIFO empty D3 reserved D3 tick in received interrupt 0x72 UART2_CTRL D6 transmit EOP D6 reserved send always EOP 0 EOP1 1 EOP2 0x73 UART2_ST D4 reserved D4 transmit FIFO empty All Rights Reserved Copyright per DIN 34 EADS eeabriL r SMCS116SpW User Manual Astrium GmbH Doc No SMCS ASTD UM 116 Rev 1 2 Date 16 06 2008 Page 155 of 157 Addr Register Description SMCS116 Description SMCS116SpW 0x75 TIME_CNTRL reserved time code control register 0x76 TIME_CODE reserved time code value register 0x78 P_MODE_EN reserved Protocol Mode Enable Register 0x79 P_CONTROL reserved Protocol Control Register Ox7A P ART ADDR reserved Alternative Return Address Register Ox7B P RT SELECT reserved Return Select Register Ox7C P LOG ADDR reserved Logical Address Register All Rights Reserved Copyright per DIN 34 EADS aseritum SMCS116SpW User Manual Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 156 of 157 15 3 1 FIFO interface register modifications Addr
19. 60 9 2 1 HOST atelier 60 93 HOST FIFO E 61 9 3 1 Transmit receive host data over from the SpaceWire link 62 94 RAM MENACE ROREM 63 9 4 1 RAM interface Slab lee 63 9427 RAM Kin ee E 63 OAS EE e EN 64 9 4 4 GEI 64 945 RAM I F Control RegiSlgk ouo Gei 65 9 4 6 Transmit data over SpaceWire link EE 65 9 4 7 Receive data over SpaceWire link ccccccceeeeeeeeeeeeeeeeeceeeesseeeeeeeeeeeeeaeeeess 67 mE dc MEE T cn 68 9 4 9 RAM I F wait etates E 69 9 4 10 SMCS116SpW protocol RAM interface port 69 Sq 1 RAM I F CESSARE ERN RE cS UE ER MD ENDO MERE 70 MEOS Ce imamate 74 9 5 1 FIFO Interface E 74 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS rere User Manual Date 16 06 2008 Page 6 of 157 9 5 2 FIFO interface TegislelS occorre epu cce cEEEE Eb PEEE EH P deuewcueveuewcue cepewcueveuewcuecenencee 74 9 5 3 FlFOinterface EES 78 96 EEN 84 9 6 1 ADC interface enable sssssesseseeenem em enhn hene rere tette retra tri triti reni 84 9 6 2 ADC interface signals AER nnne enne nnne 84 9 6 3 ADC interface control registers oiii ei eek ERR E EE RE ERRE Y RXRRRXRERXEPRXR REN HA 85 9 6 4 Packet composition and forming wisseisecsnt ieapictedsipieds aa a rte Sb Qu io eK Sp eg Fg 87 G ER leren 88 9 6 6 Sequence for Analogue Digital Conversion c cccccccceeeeeeeeeeeeeeeeeeeeeeeeees
20. 88 9 7 DAC Interface sssssssssssseese enne nennen nenne nenne rhet ies iiir sss ire psa sss ipsa sss sper sara sip ssa 91 9 7 1 DAC mmtertaceenable Ime nemen nere rre triti rer re triti rir riii 91 Br Ri en 91 9 7 3 DAC Interface Control Registers ccccccececccece rece eere ee ec ere eere eene 92 9 7 4 DAC Timing Requirements AA 92 9 7 55 Sequence for Digital Analogue conversion ssssssssrrrrrrrrrrnnrrrrrtrrreenennn nn 93 9 8 UART Interface ee 94 Sar VE 94 9 8 2 VARIT e E 94 9 8 9 UAR IZ e EE 96 9 8 4 UART BaudRate ccc cccccccccccecccecceccceececeececeececeneeceecaueceeceeeaueceeeaeesseseeeaeeserens 96 9 8 5 UART Ri e E 97 9 8 6 UART Protocol 0c cccccccccccecceeccecceceucececeecececceceneeceecaueceeceeeaeeceeseeseesereneeseeens 98 9 8 7 UART SpacewVire DACKC Uc ceccseceresexecececsneredbocserddeoensedveoesexedoepssaenexexbeseearneeeseastos 98 OD TEE eege 99 991 NEE 99 9 9 2 Timer REJIS ErS e ERR 99 9 9 3 Timer Config rati n sesistssscessaeciacsicessenasteiacansdeaiacssdedsanaidesdanasdandnedsdensanadieadedsal 101 994 MEIN Es rieimeee 101 CRI MEC SP TREE 103 9 11 JIAGIniertace enne hen nen hhe rien ien rrsa ses irs ases irs r sas es ipsins sss sns 104 10 Signal Description E 105 10 1 JOB control bus 109 FOZ GPIO Signals EE 110 11 Electrical SDeCIHCal ODDS suanixiadUan xac Ea IREK RA uva EAD ECCE FREE aA DECRE DAMM REGES iaaa 111 III PC Fiiter 113 TL2 3 3 VON S Volt Operating Vollaga ii
21. Astrium GmbH The contents are for confidential use only and are not to be disclosed to any others in any manner in whole or in part except with the express written approval of Astrium GmbH or to the provision of the relevant contract All Rights Reserved Copyright per DIN 34 EADS d asbrium Astrium GmbH SMCS116SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 User Manual Date 16 06 2008 Page 4 of 157 Table of Contents NL VT E 8 1 1 Scope and EE 8 1 2 LIST OF ADD UCADIS COCO AIS eege 9 La Listo Abbreviation rennararnir LIRE aad Ea ERA IA EO ERA Ja ERR DAR 10 2 The need for SMCS116SpW eran cusu cuna tutaikita uasa du ia uuu cu da Load asas RR UE ANN ERA ME EE ERE EE EVA nne 12 4 SMCS116SpW FedllilBSuucuodiikprndipEtinu dE cibbnrisdd indt dE rona EI m ESCEU edili red E En MV RE 12 4 The SpaceWire link and protocols eeeeeeeeeeeeeeeeeeeeeee nennen 16 41 TIALS ORS PI RR T data ad 16 42 Character level flow EE 18 4 3 LINK Spo dS D 18 44 Ee 19 5 The le RER e ET 20 5 1 Programming the SMCS116SpW ssssssssssssseeeesneseneneeeeneeensenseeneesscesnsesseneeees 20 5 1 1 Read internal SMCS116SpW registers Lcceeeecceccceceeccccceceses 22 5 1 2 Write to internal SMCS116SpW registers eeeeeeeceeeceecceecceeseeesss 22 5 1 3 Write to SMCS116SpW POMS eee raodo edi X ok beo I0
22. Date 16 06 2008 E I LJ ITI Page 34 of 157 7 1 5 FIFO Interface Registers F CURTRM1 Transmitted Number Register 1 F_TRM_CTRL Transmit control register CH F_RCV_CTRL Receive control register GE F CTRL FIFO control FIFO control register FIFO_PORT fifo port address Gr 7 1 6 ADC Interface Registers Address Register Description r w Ox1D ADC STR ADC Start Address r w Ox1E ADC END ADC End Address r w Ox1F ADC CUR Current ADC Address r 0x20 ADC TEST reserved r 0x21 ADC CTRLO ADC control register 0 r w 0x22 ADC CTRL1 ADC control register 1 r w 0x23 ADC CTRL2 ADC control register 2 r w 0x24 ADC PORT ADC port address e only All Rights Reserved Copyright per DIN 34 EADS asc FAKE SMCS116SpW Beene Rev User Manual Date Page Astrium GmbH SMCS ASTD UM 116 7 1 7 DAC Interface Registers Address Register Description r w 0x25 DAC DATAO DAC RegisterO r w 0x26 DAC DATA DAC Register1 r w 0x27 DAC_ADR DAC Address Register r w 0x28 DAC_CTRLO DAC control register 0 r w 0x29 DAC CTRL1 DAC control register 1 r w 7 1 8 RAM Interface Registers Address Register Description r w Ox2A RAM_TST_ADRO Transmit Start Address Register 0 r w 0x2B RAM TST ADR1 Transmit Start Address Register 1 r w 0x2C RAM TST ADR2 Transmit Start Address Register 2 r w Ox2D RAM TED
23. EADS me U M l Rev 1 2 SssStrium ser Manua Date 16 06 2008 Page 31 of 157 Communication device for microprocessors Many applications require a link front end providing one link but no controller instance on that unit Due to the communication memory interface of the SMCS116SpW it is also satisfying the requirements of these applications Due to its small package and low power consumption it is an excellent alternative to FPGA based solutions A system using the SMCS116SpW as a communication front end for a microcontroller is shown in the following figure HDATA T 0 SpaceWire SMCS116SpW DATA 15 0 IOB 27 0 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 32 of 157 7 Register Set This chapter describes the SMCS116SpW registers General Conventions bit O DO least significant bit bit 7 D7 most significant bit Dx 0 means data bit x until bit 0 7 1 Register Address Map The tables in the sections below give a reference description of the SMCS116SpW All registers are 8 bits wide all registers contain the value 0x00 after reset except where stated differently Register addresses given are in hexadecimal notation 7 1 1 General Control Registers ENABLE enable register for the interface configuration register IFCONF
24. GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 157 of 157 Addr Register ess Oxt1A F_RCV_CTRL Description FIFO I F Receive Control Register old SMCS116 mode F_CTRL bit D4 0 r w new SMCS116SpW F CTRL bit D4 1 DO Receive START STOP bit 0 Stop receive from SpaceWire UE 1 Start receive from SpaceWire UE D1 External data bus width 0 8 Bit 1 16 bit D2 Receive mode 0 do not stop receive on EOPx 1 stop receive on EOP EEP and reset bit DO D3 External control and status signals 0 enable 1 disable D4 EOP Status read only reset with the next packet 0 no EOP received 1 EOP received D5 EEP Status read only reset with the next packet 0 no EEP received 1 EEP received D6 internal FIFO empty Status 0 not empty 1 empty D7 reserved DO Receive START STOP bit 0 Stop receive from SpaceWire UE 1 Start receive from SpaceWire UE D1 External data bus width 0 8 Bit 1 16 bit D2 Write EOP EEP mode 0 write the received EOP EEP to the external or internal passive mode FIFO 1 write NOT the received EOP EEP to the external or internal passive mode FIFO D3 not used reserved D4 EOP Status read only reset with the next packet 0 no EOP received 1 EOP received D5 EEP Status read only reset with the next packet 0 no EEP received 1 EEP received D6 internal FIFO empty Status
25. GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS so User Manual Date 16 06 2008 aseritum Page 84 of 157 9 6 ADC Interface SMCS116SpW ADC DATA 15 0 4 DATA IOBB ADC CS CS IOBS ADC R C gt RIC SpaceWire 10B22 ADC_RDY READY IOBO 7 ADC ADDRO 7 IOB23 ADC TRIG EXTERNAL TRIGGER 9 6 1 ADC interface enable The ADC interface is enabled with the following sequence of register writes 1 write 0x98 to register ENABLE 0x00 2 set bits D2 1 and DO 0 in register IFCONF 0x01 xxxx x1x0 9 6 2 ADC interface signals The pin allocation of the SMCS116SpW signals used for the ADC interface is shown below IOB 7 0 ADC ADDR 7 0 address select lines to an external analogue multiplexer These signals are driven after address generation is enabled ADC CTRLO 0x21 D6 0 B If an analogue multiplexer is not required these lines can be used as GPIOs GPIO1 lIOB 8 ADC CS adc chip select active low select signal for the ADC device IOB 9 ADC R C read convert if the signal ADC_R C is low and adc cs is active low the ADC device starts conversion of the analogue value if the signal ADC_R C is high and adc cs is active low the SMCS116SpW reads the converted value from the ADC device All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Ges No SMCS_ASTD_UM_1 16 EADS weg User Manual Date 16
26. ISR 1 ISR 2 EOP Note Return Address has to be set before 5 2 4 Return Address The SMCS116SpW stores the last received return address This return address is used for e all register read replies e data transmitted from RAM FIFO ADC UART and Interrupt controller if this is selected in the Return Select Register An alternative Return Address can be written to the Alternative Return Address Register This return address is used only for e data transmitted from RAM FIFO ADC UART and Interrupt controller if this is selected in the Return Select Register All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS so User Manual Date 16 06 2008 aescCrmium Page 28 of 157 5 2 5 Protocol error interrupts In the case of a protocol error like wrong logical address wrong protocol identifier wrong register address example read of a data port Bit 1 in the interrupt status register ISR O will be set In the case of a packet length lt 4 byte bit 2 in the interrupt status register ISR 0 will be set The wrong packet will be ignored by the SMCS116SpW All Rights Reserved Copyright per DIN 34 Astrium GmbH L SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aseritum Page 29 of 157 6 SMCS116SpW Applications The SMCS116SpW is targeted at
27. KEE CAR Re i e 38 7 1 13 Interrupt EE 39 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS be paren User Manual Date 16 06 2008 Page 5 of 157 7 1 14 Interrupt Status Registers cccoccceccceecceccceccee ccce ce eee cee eere eee ree ce 39 TAIS GPIO REgIStErS e e 39 7 14 16 JEAIRSTZ e E 40 7 1 17 SpaceWire TIMECODE Registers ccccecc ccce eee eere 40 K nn EA UE FS nC 41 7 1 19 Semaphore Control REGIS sdmgensgg geed gege 41 1 1420 e E 41 8 General E E 42 GC Wee 42 8 2 EE 43 swe WE e sce E 43 8 22 Jnemupt Massi 9594 99999495994 99 994 9 2 9 0 9 9 5 9 0 0 gus duds 43 8 2 3 Interrupt Status E 43 ER ROSES e mance t E E Gal 48 E WR e E 48 84 lee E 48 B5 STUP AGOISIClS sirsiran E RR Ku LR Ad Aa DR 49 8 6 Time interface registered rra i eR EES 51 9 SMCS116SpW Modules and Interfaces eee 53 CREE 4 etc r NU ULM 53 9 1 1 Linkinterfa e SII AS Mee M M 53 9 1 2 Space Vine Link eebe 53 9 1 3 SpaceWire Link Speed Register ssc deccei isenicinaccwsnceatendednacendnes ad quaa pde Sp addis 55 9 1 4 Packet Header Registers eeeEEEEESESESENEEESEERESESESENEEEEESESESESESENEEESESENEEEgeeg 57 9 1 5 Packet Header Checksum Generation and Wormhole Routing 58 9 2 Host internat catered eas cia irda E A e E a
28. Manual Saserium Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 113 of 157 11 1 PLL Filter The pin PLLOUT should be connected as shown below SMCS116SpW PLLOUT R1 1 5 KQ 596 YW C1 22 pF 596 C2 1 8nF 5 11 2 3 3 Volt 5 Volt Operating Voltage E R1 C2 The signal VCC 3VOLT is a select signal for the PLL It changes the internal configuration of the PLL If VCC is connected to 5 volt then this signal should be connected to GND If VCC is connected to 3 3 volt then this signal should be connected to VCC All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS rent User Manual Date 16 06 2008 Page 114 of 157 11 3 Power and Ground Guidelines To achieve its fast cycle time the SMCS116SpW is designed with high speed drivers on output pins Large peak currents may pass through a circuit board s ground and power lines especially when many output drivers are simultaneously charging or discharging their load capacitances These transient currents can cause disturbances on the power and ground lines To minimize these effects the SMCS116SpW provides separate supply pins for its internal logic and for its external drivers All GND pins should have a low impedance path to ground A ground plane is required in SMCS116SpW systems to reduce this impedance minimizing nois
29. RAM data width 8 bit 16 bit STOP NOT ON RECEIVED EOP stop on a received EOP do not stop on a received EOP see Note External RECEIVE control signals disable enable EOP Status All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 E E rium Page 68 of 157 Address Register Description r w bit D3 in register ISR_1 0x60 is set 0 no EOP received 1 EOP received D5 EEP Status bit D3 in register ISR_1 0x60 is set 0 no EEP received T EEP received D7 D6 reserved Note If STOP NOT ON RECEIVED EOP is enabled then the received data bytes over the SpaceWire must be equal or lower then the receive memory area Otherwise the link will be blocked The remove of the blockage could only possible by reprogramming of the receive area by host interface or by stop of the Space Wire link 9 4 8 Bank select Four registers exist to program the memory bank select boundaries RAM BNDO D7 DO BoundaryO Register default Oxff RAM BND1 D7 DO Boundary1 Register default Oxff RAM BND2 D7 DO Boundary2 Register default Oxff RAM BND3 D7 DO Boundary3 Register default Oxff Note it is mandatory that RAM BNDO RAM BND1 s RAM BND2 lt RAM BND3 The result of the comparison between the upper internal memory addresses iADDR17 10 and the boundary registers activates the CS3 0 sig
30. address interrupt D2 RAM interface receive error D3 RAM interface receive EOP EEP D4 Timer1 expired D5 Timer2 expired D6 External interrupt O D7 External interrupt 1 0x61 ISR 2 D3 D0 Interrupt status register 19 16 r DO UART 1 interrupt D1 UART 2 interrupt D2 HOST FIFO interrupt D3 tick in received interrupt D7 D4 reserved All Rights Reserved Copyright per DIN 34 EADS m aseritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 45 of 157 ISR 0 register DO D1 D2 D3 D4 D5 D6 Checksum error When bit DO of the checksum enable register CHKEN 0x14 is set the link interface compares the received checksum the last two bytes of the received packet with its internal generated checksum If the checksum is not equal the link generates the checksum error interrupt Protocol command error When the received SMCS116SpW protocol packet was wrong the link generates the protocol command error A packet is wrong when the received address is not enabled for the received command i e write read to form UART2 but UART2 is disabled Protocol command length error The received SMCS116SpW protocol packet is too short This is the case if a write command is only one byte long Longer command packets than necessary e g a read command with two and more bytes length are tolerated by SMC
31. address will be incremented All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 86 of 157 Address Register Description ADC TEST reserved for test only 0x21 ADC CTRLO DO send ADC port address 0x24 over link send send not ADC ADDR send over link do not send reserved write 0 reserved write 0 SEND EOP EOP ADC sample data width 16 Bit 8 Bit multiplexer address generation disabled enabled if disabled the ADC ADDR lines can be used as GPIO1 otherwise they are in tri state D7 reserved 0x22 ADC CTRL1 D3 O wait state Register for setup and pulse width timing D4 select conversion trigger source 0 start conversion by bit 0 of ADC_CTRL2 0x23 external trigger signal connected to IOB 23 starts conversion D5 reserved write 0 D6 select ready source 0 on chip timer1 external ready signal connected to IOB 22 terminates conversion and starts read of converted value D7 reserved write 0 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 87 of 157 Address Register Description 0x23 ADC_CTRL2 DO starts conversion will be reset after conversion has started D7 1 reserved ADC PORT ADC
32. below Calculation is based on an internal clock of 25 MHz 5 Volt For 3 3 Volt environment please calculate with 12 5 MHz 80 ns only write access 16 Bit databus 3 WS cycles 0 5 byte 40 ns 60ns byte gt 16 6 Mbyte s WS wait states 0 7 only read access 16 Bit databus 1 WS cycles 0 5 byte 40 ns 20ns byte gt 50 Mbyte s Simultaneous read write access 16 Bit databus 2 WS cycles 0 5 byte 40 ns 40ns byte gt 25 Mbyte s 9 4 11 2 Read access with external control signals The RAM TCNTRL 0x33 specifies whether external control signals are enabled or not D3 0 external control signals disabled D3 1 external control signals enabled Wi IOB18 21 sd E KU MEME mul CS0 3 4 FH IOB16 WR EE EX IOB17 RD IOBO 15 tp p ADDRO 15 19 O ES UNI DATAO S M Ai CL 1 RR IOB26 Si START TRM ET A IOB23 E ETEN TRM RDY This figure shows an external controller memory read access Before transmitting data from the memory over the SpaceWire link the registers RAM TST ADRx and RAM TED ADRx and bit D1 D4 not DO of register RAM TCNTRL need to be programmed 1 the time between the rising edge of the START TRM IOB23 pin and the first read access of the memory depends on o whether the internal RAM FIFO is empty or full All Rights Reserved Copyright per DIN 34 Astrium GmbH L SM
33. changes level when the data does not clock recovery and data synchronisation can be achieved by XOR ing of data and strobe signals without having the need to run the strobe at very high frequencies The exchange layer of the protocol is used to implement flow control which avoids overflow of the front end buffers Error detection is provided by implemented parity checks during transmission and by timeout supervision in case of inter connect failures The SpaceWire standard aims only to define a transport medium between two nodes and covers the protocol layers only up to the packetization layer This has two consequences 1 packetization with address headers allow to use this link standard in networks using routers 2 since the standard does not define the data payload within the packets an efficient transaction layer definition is missing To compensate for these deficiencies of the SpaceWire specification the SMCS116SpW implementation introduces an optional transaction layer extension to the SpaceWire protocol standard This high level protocol extension supports applications in fault tolerant systems heterogeneous architectures feature power saving modes and remote configuration of the communication controller and autonomous command execution With this flexible and powerful protocol the SpaceWire link has many advantages over commonly used interface solutions such as RS 485 etc 4 1 Data Strobe links The SpaceWire links use a prot
34. config register IFCONF 0x01 is set the falling edge of signal GPIO2 EXT IREQO generates an interrupt D7 External interrupt 1 When the external interrupt input is enabled bit D6 of the interface config register IFCONF 0x01 is set the falling edge of signal GPIO3 EXT_IREQ1 generates an interrupt ISR 2 register DO D1 D2 D3 UART interrupt UART1 generates a status interrupt For more information please refer to the UART1 status register UART1 ST 0x54 UART2 interrupt When UART 2 is enabled bit D7 of the interface config register IFCONF 0x01 is set UART2 generates an status interrupt For more information please refer to the UART2 status register UART2 ST 0x73 HOST FIFO interrupt The HOST FIFO module generates an interrupt when the receive fifo is not empty tick in received interrupt The time interface generates an interrupt when a valid tick in is received When reading the Interrupt Status Registers the following need to be observed All three ISR registers must be read only then their contents will be reset Register ISR 0 Ox5F must be read first and register ISR 2 0x61 last When bit D4 of the register IFCONF 0x01 is zero the above ISRs will automatically be sent over the SpaceWire link and reset after transmission In this case a header byte with the value Ox5F is sent When this bit is set 1 these ISRs will not be transmitted over the link All Rights R
35. d p REEF AERE Ra aaa 113 11 3 Power and Ground Guidelines essc nnne nennen nnn r nns aen 114 12 Timing NEE 115 E E ele 115 1232 3 116 12 2 Host write e TE 117 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS ritr User Manual Date 16 06 2008 Page 7 of 157 PG HS e EE 118 125 Host read Eed 119 12 6 Hostread dal E nia a anaana 120 12 7 E 121 128 BAM MCT ACE EE 122 12 9 RAM interface external bus reguest eene nnn 124 12 10 RAM interface external control read 125 12 11 RAM interface external control write essen 126 12 12 FIFO i terfac E 127 NEED SN CO TCA 128 12 14 FIFO interface passive write eese 129 12 15 FIFO interface passive read 130 1216 EE 131 E SE D OaE E E 132 E Ge 133 EI MEEE EE 134 1220 LINKS e ETT TT Tte 135 1221 Jes POM JTAG sedeicnt terin ditare ene eee eens 136 LEN MEME Ns E 137 BN iri gucm 138 13 0 Package DIMENSIONS acnonnenvdoosneA enema 138 132 PUT ASSIGDEDBI E 140 14 Additional B e ee ET EEN 142 14 1 BSDL File for the SMCS E 142 15 Differences between the SMCS116SpW and the old SMCS116 152 ON MEE Ee 152 e EE S sitaduiutubusui ui ai but ut it i bata Rv beca rv bala v bet vu Pal ina es 152 15 3 Summary of changed modified added registierg 15
36. independent UARTs are included in the SMCS116SpW as well One UART uses dedicated UO lines whereas the second UART is sharing its pins with the GPIO port The transmit rate of the UARTs in bps can be programmed via a 12 bit wide register with a maximum bit rate of about 780 kbit s The UARTs can optionally use hardware handshake rts cts Host Interface Although the SMCS116SpW is primarily designed to be remotely controlled it can nevertheless be programmed and controlled by a local host if required For that purpose a host interface provides 8 multiplexed data and address lines Timers Event Counter Two 32 bit on chip timers are available on the SMCS116SpW Each timer provides a 32 bit counter and a 32 bit reload register The two timers can be operated independently or cascaded The timers can also be used to set an external signal when the timeout value is reached Configuration After a chip reset the SMCS116SpW is configured by the internal controller This can be either by receiving the configuration data from the SpaceWire link or by an external controller connected to the host port of the SMCS116SpW Shared I O Some of the functions of the SMCS116SpW presented above share the same UO pins This means that some functions are mutually exclusive As an example the GPIO port shares some of its I O pins with the host interface If the host interface is not used these pins are available for GPIO otherwise they are used as the ho
37. is stopped the bits DO D3 and D4 are not reset Therefore on a new start of the link these bits do not reflect the current situation of the link For this reason it is necessary to read the register before the start of the link Then only bit 4 shall be checked whether the link is in the Run state or not 9 1 3 SpaceWire Link Speed Register Address Register Description r w 0x02 BITRATE select bit rate on SpaceWire link reset value 0x02 r w 0x03 RES1 Reserved r 0x04 RES2 Reserved r 0x05 RES3 Reserved reset value 0x90 r 0x06 RES4 Reserved reset value 0x72 r The SpaceWire links can support a range of communication speeds which are programmed by writing to registers At reset all links are configured to run at the base speed of 10 Mbits sec Only the transmission speed of a link is programmed as reception is asynchronous This means that links running at different speeds can be connected provided that each device is capable of receiving at the speed of the connected transmitter The transmission speeds of the SpaceWire link of the SMCS116SpW is programmed by the register BITRATE 0x02 Possible link speeds are BITRATE Register Link Speed 5 V Link Speed 3 3 V D3 D0 Mbit s Mbit s 0000 2 5 2 5 0001 5 5 0010 10 default 10 default 0011 20 25 All Rights Reserved Copyright per DIN 34 EADS a eeabri r
38. of 157 The ports of the SMCS116SpW such as the FIFO UART ADC and RAM interface are accessed by a read write command to the corresponding port address In the case of FIFO Host UART and memory interface a packet oriented access is also possible meaning transferring multiple data bytes with a single command The read write selection of a command is done by setting bit7 MSB of the first byte to one read or zero write All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 22 of 157 5 1 1 Read internal SMCS116SpW registers Read Command Byte 0 defines whether a write D7 0 or a read D7 1 command is performed 1 amp Register XB 0 or more EOP Address D6 0 bytes Note SMCS116SpW ignores dummy bytes Read reply packet is sent after a read command 0 amp Register Register Value EOP Address 5 1 2 Write to internal SMCS116SpW registers 0 amp Register New Register XB 0 or more EOP Address D6 0 Value bytes 5 1 3 Write to SMCS116SpW ports 0 amp Port Address Data byteO Data byte1 Data byte1 Data byte Data byte N 1 Data byte N EOP 5 1 4 Data read from SMCS116SpW ports 0 amp Port Address Data byteO Data byte1 Data byte1 Data byte Data byte N 1 Data byte N EOP
39. the following sequence of register writes 1 write 0x98 to register ENABLE 0x00 2 set bit D3 1 and DO 0 in register IFCONF 0x01 xxxx 1xx0 9 7 2 DAC interface signals The signal allocation of the SMCS116SpW signals used for the DAC interface is as follows IOB 10 DAC WR DAC write signal active low select signal for writes to DAC device IOB 13 11 DAC ADDR 2 0 address lines could be used for external generation of multiple dac write Sek or if a DAC device contains more than one DAC to select one of them IOB 9 8 Po NOTE These signals are asserted driven after the DAC interface is enabled All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 92 of 157 9 7 3 DAC Interface Control Registers The following registers are needed to control the DAC I F 0x25 DAC DATAO D7 DO Data to be converted to an analogue value the contents of this register will appear on SMCS116SpW DATAT 0 0x26 DAC DATA D7 DO Data to be converted to an analogue value the contents of this register will appear on SMCS116SpW DATA15 8 0x27 DAC ADDR D2 D0 DAC address the contents of this register will appear on SMCS116SpW IOB13 11 D7 D3 reserved 0x28 DAC CTRLO DO Starts conversion will be reset after conversion has started D7 D1 reserved 0x29 DAC CTRL1 D3 DO Wait state register for set
40. 0 not empty 1 empty D7 reserved All Rights Reserved Copyright per DIN 34
41. 06 2008 Page 85 of 157 ADC I F signal Description IOB 22 ADC RDY external conversion ready a high on this input signals the ADC HE controller that the conversion is completed and that the converted value can be read Also an on chip timer can be used for this purpose eeabriL rnm IOB 23 ADC TRIG external trigger to start convert sequence a high pulse on this input triggers the ADC I F controller to start a new conversion Also an on chip timer can be used for this purpose IOB 13 10 NOTE These signals are asserted driven after the ADC interface is enabled 9 6 3 ADC interface control registers The following registers are needed to control the ADC I F Ox1D ADC STR D 7 0 Start Address Register the contents of this register defines the starting address of the analogue multiplexer Ox1E ADC END D7 0 End Address Register the contents of this register defines the ending address of the analogue multiplexer Ox1F ADC CUR D 7 0 Current Address Register shows the actual value of the multiplexer select The ADC STR and ADC END registers can be used to convert several analogue values autonomous by the ADC I F controller scanning The analogue multiplexer starts at the contents of register ADC STR The value written to the ADC STR register defines the multiplexer start address The end point address for the analogue multiplexer can be every value between 0x00 and Oxff After each conversion the
42. 08 eebrium Page 111 of 157 11 Electrical Specifications Absolute Maximum Ratings Fee en me mi povas JL ees v coin Tones nare ormen x ec e Junction Temperature m Tj lt TA 20 SG Storage Temperature Range 65 to 150 Thermal Resistance Stresses above those listed may cause permanent damage to the device DC Electrical Characteristics SMCS116SpW can work with Vcc 5 V 0 5V and Vcc 3 3 V 0 3V Peano we one es Operating Voltage 4 5 5 5 3 0 3 6 Output HIGH Voltage won ja v max output current Output LOW Voltage a DR max output current Output Short circuit current mA Output current 3 mA 180 mA Output current 6 mA mA Output current 12 mA Note see also the signal description in section 10 All Rights Reserved Copyright per DIN 34 Astrium GmbH e SMCS116SpW Doc No SMES ASTD UMG 16 weg User Manual Date 16 06 2008 eebrium Page 112 of 157 SMCS116SpW Power Consumption Although specified for TTL outputs all SMCS116SpW outputs are CMOS compatible and will drive VCC and GND assuming no DC loads The maximum power consumption figures are at 5 5V 55 C Operating Mode Symbol Max Unit wmm m om E 5 m mew je 3 6V 55 C Operating Mode Symbol Max Unit me o m m Mw p e m wem e le All Rights Reserved Copyright per DIN 34 SMCS116SpW EADS User
43. 0i Ier Re thx goa Dna cf oap obe t aida 22 5 1 4 Data read from SMCS116SpW ports 0 cc ccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeees 22 5 2 Programming the SMCS116SpW with STUP sssssssssssss 23 5 2 1 Switching between STUP Mode and old SMCS116 protocol mode 23 5 2 2 Write internal SMCS116SpW registers Lcceecceeceeecceeccee ccce 24 5 2 8 Read internal SMCS116SpW reotsterg EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEN 26 524 MEL gie e 27 5 29 Protocol SION iei TOES dudsicdeicicicdedbies deicioiodqadciotbdedddescdediictsded diviqude 28 6 SMCSTIBSDW Applications oiu cnius dp iai eda Ri ao REEL C Rl MN EH 29 SEENEN 32 7 1 Register Address Map iiss snscssectesninsssssntenstevssnnciessieyntnsaxeetessteysaescieeataenien ey soeectensla 32 7 1 1 General Control Registers cece seecceccccecceceseecceceteeeseecseecteectcextuereeeceuerteecseevseeesecupue 32 11 2 Clock Control FREQ NS UN ee 32 7 1 3 SpaceWire Link EC 33 Fe e TEE 33 TAS FIFO Interface Registers acne eee ee ees 34 7 1 6 ADC Interface Registers c cccececceeeeceseeeeeceeceeeeeeeeneeeceeeeeenenes 34 7 14 7 DAC Interface eelere egene dek 35 7 1 8 RAM Interface Reglslels coercere cece eee eee 35 FP MEET Bo o e EEEEEEEEEEEEEeEe 37 1 4 10 Timer TS mc EC 37 7 1 11 Host FIFO Interface Registers eeeeeeeeeeeeeeceeecececeeececececeeeeee 38 Tei
44. 1 1 EOP2 Ox3D RAM RCTRL REG D4 EOP 1 Status D4 EOP Status 0 no EOP1 received 0 no EOP received 1 EOP1 received 1 EOP received D5 EOP2 Status D5 EEP Status All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS116SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS User Manual Date 16 06 2008 eezbrium Page 154 of 157 Addr Register Description SMCS116 Description SMCS116SpW 0 no EOP2 received 0 no EEP received 1 EOP2 received 1 EEP received 0x51 HFTREOP Transmit EOPx Transmit EOP DO EOP1 D1 EOP2 0x53 HFSTR Status register Status register DO EOP1 received DO EOP received D1 EOP2 received D1 EEP received 0x59 UART1 CTRL D6 transmit EOP D6 reserved send always EOP 0 EOP1 1 EOP2 OxXBA UART1 ST D4 reserved D4 transmit FIFO empty Ox5E IMR 2 D3 reserved D3 0 disables masks tick in received interrupt 1 enables unmasks tick in received interrupt Ox5F ISR 0 D3 IEEE 1355 link error D3 SpaceWire link error note means parity or disconnect note means parity disconnect error ESC or credit error D5 FIFO interface transmit EOPx D5 FIFO interface transmit EOP D7 FIFO interface receive EOPx D7 FIFO interface receive EOP EEP 0x60 ISR_1 DO RAM interface transmit EOPx DO RAM interface transmit EOP D3 RAM interface receive EOPx D3 RAM interface receive EOP EEP 0x61 ISR 2 DO UART interrupt DO UART interrupt note means transmit full data note
45. 1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 117 of 157 12 3 Host write address a tas a tush HSEL tuwnrs wa EX WnRH HWRnRD tuonas les m RAM HDATnADR HDATA regi ster address valid Description HSEL active low pulse width tHSL 150 SEE 295 HSEL inactive high pulse width tHSH e 100 HWRnRD setup before HSEL active tHWnRS 5 ns low HDATnADR setup before HSEL active tHWnRH el Poi ns low HWRnRD hold after HSEL inactive tHWnRH ns high HDATnADR hold after HSEL inactive tHDnAH ns high HDATA valid after HSEL active low and tHDWV 25 25 HWRnRD high All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS so User Manual Date 16 06 2008 aescCrmium Page 118 of 157 12 4 Host write data 2 De pa nt HSEL baus he y ven HWRnRD Lang w Jk thonan y HDATnADR tHowv oan HDATA data valid Description Symbol Min BE V E SS 3 es ZS 3 SC HSEL active low DEEL active low pulse width width ra HSEL inactive high pulse width nen HWRnRD setup before HSEL active tHWnRS low HDATnADR setup before HSEL active tHWnRH kk low HWRnRD hold after HSEL inactive tHWnRH ns high HDATnADR hold after HSEL inactive tHDnAH ANNE NEN JI high HDATA valid after HSEL active low and tHDWV 25 25 ns HWRnRD high HDATA hold
46. 16SpW registers Read Command Logical Address Protocol ID Return Address Command amp Register Address XB 0 or more Checksum Checksum EOP bytes Note SMCS116SpW ignores dummy bytes Byte 4 defines whether a write D7 0 or a read D7 1 command is performed Checksum is interpreted when checksum generation is enabled Read Reply Read reply packet is sent after a read command Return Address Protocol ID Logical Address Register Address Data Checksum Checksum EOP Checksum is appended when checksum generation is enabled Example Read IFCONF Register 0x01 Command Ox7E OxEF 0x20 0x81 EOP Read IFCONF Register 0x01 Reply Packet 0x20 OxEF Ox7E 0x01 Data EOP All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS ec User Manual Date 16 06 2008 Page 27 of 157 Interface data packet interrupt packet An interface data packet or an interrupt packet is sent autonomously because of an interrupt or a FIFO RAM ADC or UART Interface data transmission Return Address Protocol ID Logical Address Port Address or OR Interrupt Status Alternative Return Register Address Address Data Checksum Checksum EOP Checksum is appended when checksum generation is enabled Example Interrupt Packet OxAB OxEF Ox7E Ox5F ISR 0
47. 2 15 FIFO interface passive read t IOB18 R EP eet wa IOB19 WR tepRFE IOB20 FIFO EMPTY IOB16 RCVEOP terco a m IOB17 RCVEEP IOB26 RCV_EOP_ACK e d Parity not valid IOB15 RCV PAR DATAO0 15 EOPL EOPH es gt Lata valid Ua valid Description Symbol Min 5 V SE 3 3 V 3 3 V RD active low pulse width active low RD active low pulse width width mmm mmm lo on o EE EE ke FIFO_EMPTY active after RD low FIFO_EMPTY active after RD low active after RD low MFPREE PRE Im e IOB16 IOB17 high after last read and RD tFPREOP RF high ROV EOP ACK active high pulse width tFPREOPA LI E IOB16 IOB17 low after RCV_EOP_ACK high tFPREOPH LSU NN HCH PAR DATAO 15 EOPL EOPH valid tFPRDV after RD low DATAO 15 EOPL EOPH enable after RD tFPRDE 23820 2002 low DATAO 15 EOPL EOPH hold after RD high tFPRDH 2 o pm ode Note 1 depends on the data bandwidth over the SpaceWire link All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS e User Manual Date 16 06 2008 Page 131 of 157 12 16 ADC interface EE tances tapccs IOBS ADC CS tapcr tancs IOB9 ADC_R C IOB22 ADC_RDY tapctcs IOB23 ADC TRIG d 4 ta t peps tapcpH DATAO 15 data valid Description Symbol Min Max Min Max 5 V
48. 3 15 3 4 FIFO interface register modifications ccce 156 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS rent User Manual Date 16 06 2008 Page 8 of 157 1 Introduction Advanced sensor interfaces such as CCD cameras spectrometers etc introduce ever increasing data rates between the sensor front end and the signal processing unit Often interfaces have to be designed specifically causing high development costs and long development times The higher data rates involved in modern sensor types additionally introduce design issues such as noise fault tolerance command and data handling limited pin count and power consumption issues A communication controller using the SpaceWire standard was identified as an important element and implemented in the SMCS providing the communication interfaces in a network of multiple processing elements Since SpaceWire has been introduced for inter processor communication the logical consequence was to use SpaceWire for connecting sensor interfaces as well The SMCS116SpW is using a simple protocol protocol of SMCS116 or the STUP for efficient packet oriented data transfer The SMCS116SpW is implemented in the radiation tolerant technology MG2RT from Atmel The SMCS116SpW can be operated in a 5 V or in a 3 3 V environment 1 1 Scope and Objectives This document describes in det
49. 31 amp IOB13 32 amp IOB14 33 amp All Rights Reserved Copyright per DIN 34 EADS asbmrium SMCS116SpW User Manual Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 145 of 157 IOB15 34 amp IOB16 35 amp IOB17 36 amp IOB18 37 amp IOB19 38 amp IOB20 39 amp IOB21 40 amp IOB22 41 amp IOB23 42 amp IOB24 43 amp IOB25 44 amp IOB26 45 amp IOB27 46 amp DATA 47 48 49 50 51 52 53 54 55 58 59 60 63 64 65 66 amp GPIO 67 68 69 70 71 72 73 74 amp TMR1_CLK 75 amp TMR2_CLK 76 amp RXD 77 amp TMR1_EXP 78 amp TMR2_EXP 79 amp TXD 80 amp HDATA 81 82 83 84 85 86 87 90 amp HDATNADR 91 amp NHSEL 92 amp HWRNRD 93 amp NHINTR 94 amp NRESET 95 amp CLK 96 amp VCC 3VOLT 97 amp VDD 3 4 16 27 56 61 88 100 amp GND 2 9 15 28 57 62 89 97 98 99 amp NC 1 for completeness pllout attribute TAP SCAN IN of TDI signal is true All Rights Reserved Copyright per DIN 34 Astrium GmbH Kos SMCS116SpW Doc No SESCH 16 weg User Manual Date 16 06 2008 Sserium Page 146 of 157 attribute TAP SCAN MODE of TMS signal is true attribute TAP SCAN OUT of TDO signal is true attribute TAP SCAN RESET of TRST signal is true attribute TA
50. 57 9 4 11 RAM I F access 9 4 11 1 Read write access intemal clock enor Ail Se qu ure IOB18 CSO ge ri E IOB19 CS1 IOB20 CS2 SE Kc IOB21 CS3 e 3 IOB16 WR V a 36ydes IOB1Z RD oo SE IE IOBO 15 ADDRO 15 esvani LI pArAG tea Uri HH I The figure above shows a simultaneous read write access with no wait states to the external ram The internal clock runs with 25 MHz 5 V and with 12 5 MHz 3 3 V 1 after set from Bit DO in the interface config register the external signals are asserted 2 asingle write cycle always needs 3 clock cycles may be extended by wait state cycles more than one subsequent write access only needs two clock cycles per access 3 during a read access only the address increments CS0 3 and RD signals remain active low until o the internal FIFO is full or o the interface needs a write cycle 4 fair arbitration between read and write access or o change between two ram banks 5 4 the ram i f needs 1 cycle for the change between read and write access 5 the ram i f needs 1 cycle for the change between two banks All Rights Reserved Copyright per DIN 34 Astrium GmbH L SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS rot User Manual Date 16 06 2008 Page 71 of 157 An example of data bandwidth calculation is given
51. 6 Rev 1 2 User Manual Date 16 06 2008 Page 60 of 157 9 2 Host interface The host interface is enabled by the following sequence 1 write 0x98 to the register ENABLE 0x00 2 set bit D5 of register IFCONF 0x01 to 0 xxOx xxxx After reset the host interface is enabled HSEL data wr HWRnRD HDATnADR Y addr wr a a gt KEE d d e EE ee j SMCS 116SpW E register E o HDATA zc g 9 2 1 HOST interface signals Signal UO Description HSEL when active low the host selects the SMCS116SpW host interface HWRnRD this signal is high when the host writes data to the address register or to the SMCS116SpW registers this signal is low when the host reads data from the address register or the SMCS116SpW registers HDATnADR this signal is high when the host reads writes data from to the internal SMCS116SpW register bank this signal is low when the host reads writes the address from to the address register HDATA7 0 I O Z data lines 7 0 HDATAO LSB HDATA7 MSB If the host interface is not required set bit D5 of the interface enable register IFCONF 0x01 to 1 this will disable the host interface and hold HSEL high inactive The signals All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS116SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS brnir U
52. 7 DO0 Period Count value Register2 TPERIODx 2 TCOUNTx 3 D7 DO0 Period Count value Register3 MSB r w TPERIODx 3 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 100 of 157 DO start stop timer 0 stop timer 1 start timer D7 D1 reserved TCONFIGx D1 DO select timer clock source 00 internal clock 5 volt mode 12 5 MHz 3 3 volt mode 6 25 MHz 01 trigger from other timer 10 external signal TMRx CLK 11 reserved D2 stop at interrupt 0 run cyclic 1 stop after timer expired single shot mode D3 TIMERx_expired_toggle bit 0 generate low pulse on signal TMRx_EXP 1 toggle signal TMRx EXP D4 read period value counter value 0 read counter value 1 read period value D5 select timer start stop source 0 start stop bit register TCTRLx bit DO 1 tmr start adc for timer1 tmr start amuxer fortimer2 D7 D6 reserved Note x 1 or 2 for TIMER1 or TIMER2 The TPERIOD TCONFIG and TCTRL registers can be read and written through internal register commands The TCOUNT registers can be read only The TCOUNT value is read if D4 0 of TCONFIG and the TPERIOD value is read if D4 1 Register TCOUNTx 0 must be read first because reading of TCOUNTx_0 stores the 32 bit counter value All Rights Reserved Copyright per DIN 34 Astrium Gmb
53. A Output Enable Z amp zik Z amp AE Z amp SS SMS Z amp SES Z amp 2 5 amp Zu amp Z amp Z amp All Rights Reserved Copyright per DIN 34 me eis ILInm Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 150 of 157 BC 1 DATA BC 1 DATA Output3 X 64 0 Z amp input X amp 1 1 BC 1 DATA 0 output3 X 64 0 Z amp 0 BC 1 DATA 0 input X amp BC 1 control 0 amp IOB Output Enable BC 1 IOB27 output3 X 97 0 Z amp BC 1 IOB27 input X amp 100 BC 1 1OB26 input X amp 101 BC 1 10B25 input X amp 102 BC 1 control 0 amp IOB Output Enable 103 BC 1 IOB24 output3 X 102 0 Z amp 104 BC 1 IOB24 input X amp 105 BC 1 10B23 output3 X 102 0 Z amp 106 BC 1 IOB23 input X amp 107 BC 1 10B22 output3 X 102 0 Z amp 108 BC 1 I1OB22 input X amp 109 BC 1 control 0 amp IOB Output Enable 110 BC 1 IOB21 output3 X 109 0 Z amp 111 BC 1 IOB21 input X amp 112 BC 1 control 0 amp IOB Output Enable BC 1 IOB20 output3 X 112 0 Z amp 114 BC 1 IOB20 input X amp 115 BC 1 control 0 amp IOB Output Enable 116 BC 1 IOB19 output3 X 115 0 Z amp 117 BC 1 IOB19 input X amp 118 BC 1 control 0
54. ADRO Transmit End Address Register 0 r w Ox2E RAM TED ADR Transmit End Address Register 1 r w Ox2F RAM TED ADR2 Transmit End Address Register 2 r w 0x30 RAM_TCR_ADRO Transmit Current Address Register 0 r 0x31 RAM_TCR_ADR1 Transmit Current Address Register 1 r 0x32 RAM_TCR_ADR2 Transmit Current Address Register 2 r 0x33 RAM TCTRL REG _ Transmit control register r w 0x34 RAM RST ADRO Receive Start Address Register 0 r w 0x35 RAM RST ADR1 Receive Start Address Register 1 r w 0x36 RAM RST ADR2 Receive Start Address Register 2 r w 0x37 RAM_RED_ADRO Receive End Address Register 0 r w All Rights Reserved Copyright per DIN 34 SMCS11 6SpW Doc No SMOS ASTD UM 1 16 EADS Ke Gamme User Manual p 16 06 2008 Address Register Description r w 0x38 RAM RED ADR1 Receive End Address Register 1 r w 0x39 RAM RED ADR2 Receive End Address Register 2 r w Ox3A RAM RCR ADRO Current Receive Address Register 0 r Ox3B RAM RCR ADR1 Current Receive Address Register 1 r eg RAM_RCR_ADR2 Current Receive Address Register 2 r Ox3D RAM RCTRL REG Receive control register r w Ox3E RAM BNDO BoundaryO Register default Oxff r w Ox3F RAM BND1 Boundary1 Register default Oxff r w 0x40 RAM BND2 Boundary2 Register default Oxff r w 0x41 RAM_BND3 Boundary3 Register default Oxff r w 0x42 RAM WS REG Wait state control register r w 0x43 RAM_PORT RAM port address de only All
55. All Rights Reserved Copyright per DIN 34 EADS asbrium SMCS116SpW User Manual Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 73 of 157 4 After the last write the signal TRM_RDY goes high 5 after the rising edge of START TRM the signal TRM_RDY goes to inactive low All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 74 of 157 9 5 FIFO interface The FIFO interface has now two modes The old SMCS116 mode and a new mode In the new mode the EOP EEP character is like a normal data 9 5 1 FIFO Interface enable The FIFO interface is enabled by 1 writing 0x98 to the register ENABLE 0x00 2 setting bit DO 0 and D1 1 in register IFCONF 0x01 xxxx xx10 9 5 2 FIFO interface registers Note the value of D7 D1 of F TRM CTRL register 0x19 should not be changed when DO is set to 1 the value of D7 D1 of F RCV CTRL register 0x1A should not be changed when DO is set to 1 bee me See 0x15 F PSIZEO Packet size register 0 lower byte of transmit packet size 0x16 F PSIZE1 Packet size register 1 upper byte of transmit packet size 0x17 F_CURTRMO Transmitted Number Register 0 lower byte of the current transmitted bytes 0x18 F_CURTRM1 Transmitted Number Register 1 upper byte of the current transmitted bytes
56. All Rights Reserved Copyright per DIN 34 EADS 0 eeabriL rm SMCS116SpW User Manual Astrium GmbH Doc No SMCS ASTD UM 116 Rev 1 2 Date 16 06 2008 Page 75 of 157 Address old SMCS116 mode F_CTRL bit D4 0 DO Transmit START STOP bit 0 Stop transmit to SpW I F 1 Start transmit to SpW I F D1 External data bus width 0 8 Bit 1 16 bit D2 EOP selector not used D3 External control and status signals 0 enable 1 disable external control signals send packets of size F PSIZE until DO 0 stop or send only one packet when D4 1 D4 Internal control D3 1 packet mode 0 continuous send more than one packet 1 single shot send only one packet reset bit DO D5 Header selection 0 send FIFO port address 0x1C as header byte 1 send no header D6 Parity check 0 no parity check 1 parity check odd parity over 8 16 bit D1 D7 reserved F TRM CTRL FIFO I F Transmit Control Register new SMCS116SpW F CTRL bit DA 1 DO Transmit START STOP bit 0 Stop transmit to SpW I F 1 Start transmit to SpW I F D1 External data bus width 0 8 Bit 1 16 bit D2 EOP selector not used D3 Packet mode enable 0 disable 1 enable send packets of size F PSIZE D4 not used D5 Header selection 0 send FIFO port address 0x1C as header byte 1 send no header D6 not used D7 reserved All Rights Reserved
57. CS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS err User Manual Date 16 06 2008 Page 72 of 157 o whether there is another ongoing data transfer over the SpaceWire link e g over the UART or Host interfaces First read access address RAM TST ADR Last read access address RAM TED ADR After the last read the signal TRM RDY goes high after the rising edge of START TRM the signal TRM RDY goes to inactive low SH e ues Ie 9 4 11 3 Write access with external control signals The register RAM RCNTRL 0x3D specifies whether external control signals are enabled or not D3 0 external control D3 1 external control signals enabled 1OB18 21 I 7 4e CS0 3 m Hu um d d IOB16 WR eJ dei IOB17 RD IOBO 15 mg e IOB27 O EE START ROV 5 A IOB24 Sr 0 RCV RDY This figure shows an external controller memory write access Before transmitting data from the memory over the SpaceWire link the registers RAM RST ADRx and RAM RED ADRx and bit D1 D4 not DO of register RAM TCNTRL need to be programmed 1 the time between the rising edge of the START TRM IOB23 pin and the first write access of the memory depends on o whether the internal RAM FIFO is empty or full o whether there is another ongoing data transfer over the SpaceWire link e g over the UART or Host interfaces 2 First write access address RAM RST ADR 3 Last write access address RAM RED ADR
58. CS116SpW The interfaces of the SMCS116SpW such as the FIFO UART ADC DAC and memory interface are accessed by a simple read or write operation to the corresponding interface address In the case of FIFO Host UART and memory interface a packet oriented access is also possible meaning transferring multiple bytes with a single command In case a communication memory is connected to the SMCS116SpW this can be read and written to via the link using the RAM TST ADRx RAM_RST_ADRx and RAM TED ADRx RAM RED ADRx registers 5 1 Programming the SMCS116SpW Programming the SMCS116SpW internal registers is done via a simple protocol over the SpaceWire link or STUP or directly via the host interface The simple protocol requires a command byte and if necessary one or more data bytes it ignores following bytes if more bytes are sent The STUP used 4 bytes for commanding and supports also logical addressing All internal registers are 8 bit wide addressable Two commands read and write suffice to access all registers of the SMCS116SpW The SMCS116SpW provides registers and ports a register contains exactly one byte read write whereas a port e g a FIFO interface behaves like a FIFO meaning that multiple data bytes can be read or written from to the port All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 EADS WEI U M l Rev 1 2 Ssstrium ser Manua Date 16 06 2008 Page 21
59. Copyright per DIN 34 EADS 0 eeabriL rm SMCS116SpW User Manual Astrium GmbH Doc No SMCS ASTD UM 116 Rev 1 2 Date 16 06 2008 Page 76 of 157 old SMCS116 mode F_CTRL bit D4 0 DO Receive START STOP bit 0 Stop receive from SpW I F 1 Start receive from SpW I F D1 External data bus width 0 8 Bit 1 16 bit D2 Receive mode 0 do not stop receive on EOP EEP 1 stop receive on EOP EEP and reset bit DO D3 External control and status signals 0 enable 1 disable D4 EOP Status read only reset with the next packet 0 no EOP received 1 EOP received D5 EEP Status read only reset with the next packet 0 no EEP received 1 EEP received D6 internal FIFO empty Status 0 not empty 1 empty Ox1A F RCV CTRL FIFO I F Receive Control Register D7 reserved D7 reserved r w new SMCS116SpW F CTRL bit DA 1 DO Receive START STOP bit 0 Stop receive from SpaceWire I F 1 Start receive from SpaceWire I F D1 External data bus width 0 8 Bit 1 16 bit D2 Write EOP EEP mode 0 write the received EOP EEP to the external or internal passive mode FIFO 1 write NOT the received EOP EEP to the external or internal passive mode FIFO D3 not used D4 EOP Status read only reset with the next packet 0 no EOP received 1 EOP received D5 EEP Status read only reset with the next packet 0 no EEP
60. H L SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS rot User Manual Date 16 06 2008 Page 101 of 157 Reading the registers has no effect on the timer function All register are affected by a reset and set to zero 9 9 3 Timer Configuration The TCONFIG registers store the configuration of the timer The selection of the timer clock source bit 1 0 defines whether the timer is triggered by the internal clock 12 5 MHz an external clock via the input TMR CLK or the other timer The last option means that the two timers are cascaded If bit 3 of the TCONFIG register is set the signal TMR EXP toggles its value each time the timer has expired rather than generating an pulse The selection of the timer start stop source bit 5 defines if the timer is controlled by bit O of TCTRL register or by the ADC interface The second configuration is selected if the timer is used to determine the conversion time 9 9 4 Timer Operation The figure below shows a block diagram of the timer The TPERIOD register controls the timer interval The TCOUNT register contains the timer counter The timer increments the TCOUNT register each timer_clock cycle interna data bus 1 a TCOUNT START TIMER A TPERIOD TCONFIG D2 0 A MBR EXP pulseor toggle WE equal 4 TIMER interrupt 9 9 4 1 Timer Start and Stop To st
61. IOB 27 TRM_PAR l TRM_PAR l EOPH 1 0 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS116SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS User Manual Date 16 06 2008 eezbrium Page 153 of 157 15 3 Summary of changed modified added registers Addr Register Description SMCS116 Description SMCS116SpW 0x07 MODE DO power save mode DO power save mode 0 disable Unused reserved 1 enable 0x09 STATUS D5 reserved D5 ESC error D6 reserved D6 credit FCT error Ox0A LINKTEST D4 reserved D4 link output mute D5 reserved D5 send EEP instead of EOP 0x19 F_TRM_CTRL See table FIFO I F register below See table FIFO I F register below 0x1A F_RCV_CTRL See table FIFO I F register below See table FIFO I F register below 0x1B F_CTRL D4 reserved D4 FIFO mode selector 0 old SMCS116 mode 1 new SMCS116SpW mode 0x21 ADC CTRLO D4 SEND D4 reserved send always EOP 0 EOP1 1 EOP2 0x22 ADC CTRL1 D5 4 select conversion trigger source D4 select conversion trigger source 00 start conversion by bit 0 start conversion by bit 01 external trigger 1 external trigger 10 on chip timer1 D5 reserved 11 on chip timer2 D7 6 select ready source D6 select ready source 00 on chip timer1 0 on chip timer1 01 on chip timer2 1 external ready 10 external ready D7 reserved 11 reserved on chip timer1 0x33 RAM TCTRL REG D2 EOP selector D2 reserved send always EOP 0 EOP
62. L EOPH setup tFRDV ns before RD inactive high TRM PAR DATAO 15 EOPL EOPH hold tFRDH ns after RD inactive high Notes 1 ws 7 wait states 0 7 2 depends on the data bandwidth over the SpaceWire link All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 129 of 157 12 14 FIFO interface passive write tepwi IOB18 WR IOB19 RD tepwrr IOB21 FIFO FULL IOB24 TRMEOP IOB25 TRMEEP tepwacka gt Jreweorn tepwackH 10B14 TRM_EOP_ACK TE e tepwou pant y y valid valid IOB27 TRM PAR DATAO 15 EOPL EOPH Description Symbol ie SS I CUN WR active low pulsewidth active low WR active low pulsewidth width em TRM_EOP_ACK active high after tFPWACKA 83 TRMEOP TRMEEP high AND FIFO FULL inactive high IOB24 10B25 hold after TRM EOP ACK tFPWEOPH ns high TRM EOP ACK hold after tFPWACKH 83 131 164 252 ns TRMEOP TRMEEP low TRM PAR DATAO 15 EOPL EOPH valid tFPWDV 22 44 ns after WR active low TRM PAR DATAO 15 EOPL EOPH hold tFPWDH ns after WR inactive high Note 1 depends on the data bandwidth over the SpaceWire link All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 130 of 157 1
63. P SCAN CLOCK of TCK signal is 10 066 BOTH attribute INSTRUCTION LENGTH of SMCS116SPW entity is 3 attribute INSTRUCTION OPCODE of SMCS116SPW entity is BYPASS 111 110 101 amp EXTEST 000 amp SAMPLE 001 amp IDCODE 010 amp HIGHZ 011 PLL LOCK EN 100 attribute INSTRUCTION CAPTURE of SMCS116SPW entity is 101 attribute INSTRUCTION DISABLE of SMCS116SPW entity is HIGHZ attribute IDCODE REGISTER of SMCS116SPW entity is 0010 amp Version 0101001101001100 amp Part number 534C SL 00001011000 amp ID of manufacturer MATRA MHS is 58 hex ZE required by IEEE Std 1149 1 1990 LSB attribute REGISTER ACCESS of SMCS116SPW entity is A BSREG EXTEST SAMPLE amp BOUNDARY EXTEST SAMPLE amp IDREG IDCODE amp BYPASS BYPASS HIGHZ BPREG BYPASS HIGHZ All Rights Reserved Copyright per DIN 34 Astrium GmbH Rev 1 2 SMCS11 6SpW Doc No SMCS ASTD UM 116 EADS User Manual Date 16 06 2008 eeabri rnm attribute BOUNDARY CELLS of SMCS116SPW entity is BC 1 j BC 1 output control BC_1 input attribute BOUNDARY LENGTH of SMCS116SPW entity is 160 attribute BOUNDARY REGISTER of SMCS116SPW entity is num cell port func safe ccell disval rslt BC 1 LSI input X amp BC 1 LDI input X amp BC 1 LSO output2 X amp BC 1 LDO output2 X
64. P and IOB17 RCVEEP are always inactive low All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 81 of 157 9 5 3 2 Passive mode In the SMCS116SpW FIFO passive mode an external controller writes data to the internal SMCS116SpW FIFO 4 Bytes in 8 Bit mode 8 bytes in 16 bit mode Register F_CTRL 0x1B DO 1 9 5 3 2 1 Write data to the internal SMCS116SpW FIFO FIFO I F UO Description signal IOB 21 FIFO_FULL o FIFO full signal IOB 15 EOPL UO Marker signal of the EOP EEP character on the low data byte DO D7 when F CTRL D4 1 IOB 27 TRM_PAR Data parity signal if parity check enabled F_TRM_CNTL 0x19 Bit D6 1 when F CTRL D4 0 EOPH UO Marker signal of the EOP EEP character on the high data byte D8 D15 when F CTRL D4 1 DATAO 15 DATAO 15 I O Z Data lines 0 15 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 82 of 157 The signals below are enabled active when F TRM CNTL Bit D3 0 and F_CTRL Bit D4 0 IOB 24 TRMEOP End of packet signal if active high after or during the last data byte the SMCS116SpW generates an EOP character for the SpaceWire link IOB 25 TRMEEP Error End of packet signal if active high
65. Rev 1 2 Ssstriom ser Manua Date 16 06 2008 Page 134 of 157 12 19 External Interrupt EXT TREOX a Eg Description Symbol a n Bm hl EXT_IREQx low pulsewidth IREQx low EXT_IREQx low pulsewidth width ear je All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS ASTD UM 116 EADS Er U M l Rev 1 2 SsSstrium ser Manua Date 16 06 2008 Page 135 of 157 12 20 Links herz L SOx LDOx tours Doug LDIx tips tios L Six Description Symbol Min 5 V Se SE SC Ee Note 1 Output skew includes jitter 2 Max link speed 200 MBit s 5 Volt 100 Mbit s 3 3 Volt All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS so User Manual Date 16 06 2008 aescCrmium Page 136 of 157 12 21 Test Port JTAG trek TCK gt TrokH trek Dos tun Wo 1 1 liL TDI troo TDO tsyss tsysu INPUTS tsyso OUTPUTS Description Symbol is ne er SCH TCK TCK period 0 tTCK OK Im m fe Ee meme m jm je memeeme mem m B e e pemen m fe e e memwwecue me fe e P messer s fe e i Sensor Jee fe fe i messer je pm gt i All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 R
66. Rights Reserved Copyright per DIN 34 EADS asc F ILJTTI Astrium GmbH SMCS116SpW DocNo SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 37 of 157 7 1 9 Timer1 Registers Address Register Description r w 0x44 TCOUNT1_0 Counter Period value RegisterO LSB r w TPERIOD1 0 0x45 TCOUNT1 1 Counter Period value Register1 r w TPERIOD1 1 0x46 TCOUNT1 2 Counter Period value Register2 r w TPERIOD1 2 0x47 TCOUNT1_3 Counter Period value Register3 MSB r w TPERIOD1 3 0x48 TCTRL1 Timer control register r w 0x49 TCONFIG1 Timer configuration register r w 7 1 10 Timer2 Registers Address Register Description r w Ox4A TCOUNT2 0 Counter Period value RegisterO LSB r w TPERIOD2 0 0x4B TCOUNT2_1 Counter Period value Register r w TPERIOD2 1 Ox4C TCOUNT2 2 Counter Period value Register2 r w TPERIOD2 2 Ox4D TCOUNT2 3 Counter Period value Register3 MSB r w TPERIOD2 3 Ox4E TCTRL2 Timer control register r w Ox4F TCONFIG2 Timer configuration register r w All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 38 of 157 7 1 11 Host FIFO Interface Registers HFTRD Transmit data register HFTREOP Transmit EOP Register wo HFRVD Receive data register Ed 0x53 HFSTR Status register
67. S aseritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 51 of 157 8 6 Time interface registers The SMCS116SpW is able to send and receive time code characters Address Register Description rw 0x75 TIME_CNTRL Time code control register D1 DO Interrupt control bits 00 No interrupt signal to the interrupt controller 01 Enable the internal interrupt signal gene ration to the interrupt controller only for a correct received TIME CODE character received from the Space Wire links 1X Enable the internal interrupt signal gene ration to the interrupt controller for all received TIME CODE characters D2 Time code value register control bit 07 overwrite the time code register with a received time code 17 Nooverwrite of the time code value register with a received time code D3 TIME CODE SYNC signal control bitO GPIO 3 input TIME CODE SYNC signal 0 TheTIME CODE SYNC signal is disabled 17 Afalling edge of the TIME CODE SYNC signal sends the time code register value over the Space Wire links D4 TIME CODE SYNC signal control bit1 0 7 No increment of the time code value register 17 Afalling edge of the TIME CODE SYNC signal increments the time code register D7 5 reserved r w All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW D
68. S a eeabriL rm Astrium GmbH SMCS116SpW DocNo SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 95 of 157 0x59 UART1 CTRL Control Register r w DO run UART enable 0 stop 1 run D1 select source destination 0 data from to host 1 data from to link automatic D2 parity check insert enable 0 disable parity check insert 1 enable parity check insert D3 parity polarity only valid when D2 1 0 even parity le odd parity number of ones in a byte including parity is odd D4 Stop bit 0 use and check one stop bit 1 use and check two stop bits D5 send UART port address 0x5B over link 0 enable 1 disable D6 reserved In the SMCS116 version this bit controls the End of Packet marker EOP1 2 In the new SMCS116SpW version the End of Packet marker is always EOP D7 0 1 RTS CTS enable disable RTS CTS use RTS CTS control signals see Note All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 96 of 157 Ox5A UART1_ST Status register if any of those bits is set this will generate the corresponding UART1 UART2 interrupt DO transmit full D1 data received D2 parity error D3 stop bit error D4 transmit FIFO empty D7 D5 reserved UART1 PORT UART1 port address only Note Don t use the RTS signal if the data t
69. S ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aseritum Page 126 of 157 12 11 RAM interface external control write trERH IOB27 START ROV CS0 3 WR IOB24 DCH RDY Description Symbol Min 5 V es 3 3 V 3 3 V START ROV START_RCV high active pulse width active pulse width START_RCV high active pulse width IRERH men Je fos START ROV low inactive pulse width nen E NM first write access CS0 3 WR low active after tRERC START RCV high ROV RDY receive ready high inactive after the tRERR ns last write to memory time between the rising edge of RCV RDY and tRERS the next start rising edge from START RCV ROV RDY hold after START RCV high MRERD MERO lem lan Note 1 Depends on o data bandwidth over the SpaceWire link o simultaneous write to the memory with wait states o internal write to fifo full All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 127 of 157 12 12 FIFO interface write IOB9 WR kd Biet IOB18 RD EN IOB21 irs FIFO FULL IOB16 RCVEOP ac IOB17 RCVEEP IOB26 RCV EOP ACK tewov ELEM valid I DATAO 15 dais EOPL EOPH tww amp iai Description Symbol em ae em M WR active low pulsewidth active low WR active low pulsewidth wid
70. S116SpW They are causing no error SpaceWire link error When a disconnect or parity error on the SpaceWire link occurs the link interface generates the SpaceWire link error interrupt For more information please refer to the register STATUS 0x09 Write to the protected register IFCONF Write to the interface enabled register IFCONF 0x01 without prior enabling of the conf register FIFO interface transmit EOP When the FIFO interface is enabled the FIFO interface module generates an interrupt after the transmission of the EOP marker FIFO interface data parity error When the FIFO interface is enabled and when bit D6 of the fifo transmit control register F TRM CTRL 0x19 is set the FIFO interface generates from the incoming data a parity bit and compares it with the signal IOB27 FIFO TRM PAR If the signal and the bit are not equal the interface generates the fifo data parity error interrupt All Rights Reserved Copyright per DIN 34 EADS aseritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 46 of 157 D7 ISR_1 DO D1 D2 D3 D4 D5 FIFO interface receive EOP EEP When the FIFO interface is enabled the FIFO interface module generates an interrupt after the receipt of the EOP EEP marker register RAM interface transmit EOP When the RAM interface is enabled the RAM interface module generat
71. UT bit TDO OUT bit TMR1_EXP OUT bit TMR2_EXP OUT bit TXD OUT bit IOB8 OUT bit IOB9 OUT bit iob10 OUT bit iob11 OUT bit iob12 OUT bit iob13 OUT bit iob14 OUT bit iob15 OUT bit iob16 OUT bit iob17 OUT bit DATA INOUT bit vector 0 TO 15 GPIO INOUT bit vector 0 TO 7 HDATA INOUT bit vector 0 TO 7 IOBO INOUT bit iob1 INOUT bit iob2 INOUT bit iob3 INOUT bit iob4 INOUT bit iob5 INOUT bit iob6 INOUT bit iob7 INOUT bit iob18 INOUT bit iob19 INOUT bit iob20 INOUT bit iob21 INOUT bit iob22 INOUT bit iob23 INOUT bit iob24 INOUT bit All Rights Reserved Copyright per DIN 34 EADS d asbrium SMCS116SpW User Manual Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 144 of 157 VCC 3VOLT VDD linkage bit vector O to 7 GND linkage bit vector O to 9 NC linkage bit use STD 1149 1 1990 all attribute PIN MAP of SMCS116SPW entity is PHYSICAL PIN MAP constant MCQFP PACKAGE PIN MAP STRING LDO 5 amp LSO 6 amp LDI 7 amp LS 8 amp TCK 10 amp TMS 11 amp TOI 12 amp TRST 13 amp TDO 14 amp IOBO 17 amp IOB1 18 amp IOB2 19 amp IOB3 20 amp IOB4 21 amp OBS 22 amp IlOBe 23 amp IOB7 24 amp IlOB8 25 amp IOB9 26 amp IOB10 29 amp IOB11 30 amp IOB12
72. X amp output3 X 148 input X amp output3 X 151 input X amp output3 X 154 input X amp output3 X 157 input X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 control 0 amp IOB Output Enable 258 control 0 amp IOB Output Enable SAM control OUT amp IOB Output Enable Z amp control 0 amp IOB Output Enable 2 amp control 0 amp IOB Output Enable 2 amp control 0 amp IOB Output Enable Z amp control 0 amp IOB Output Enable Z g control 0 amp IOB Output Enable ZA control 0 amp IOB Output Enable Z amp control 0 amp IOB Output Enable Z g All Rights Reserved Copyright per DIN 34 EADS a aseritum SMCS116SpW User Manual Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 152 of 157 15Differences between the SMCS116SpW and the old SMCS116 15 1 Pin Modifications Pin number Description SMCS116 Description SMCS116SpW 1 VCC PLLOUT 3 GND VCC 97 GND VCC_3VOLT 99 VCC GND 100 PLLOUT VCC 15 2 Signal Modifications Signal TRMEOP2 is no longer used and signal TRMEOP 1 is renamed to TRMEOP FIFO interface signals Signal SMCS116 mode SMCS116SpW Name I O Name UO IOB 15 RCVPAR O RCVPAR O EOPL UO
73. X amp 8 BC 1 control 0 amp HOCI Data Output Enable1 9 BC 1 HDATA 1 output3 X 28 0 Z amp 0 BC 1 HDATA 1 input X amp 1 BC 1 control 0 amp HOCI Data Output EnableO BC 1 HDATA 0 output3 X 31 0 Z amp BC 1 HDATA 0 input X amp BC 1 TXD output2 X amp output2 for internal tristate 5 BC 1 TMR2 EXP output2 X amp output2 for internal tristate 6 BC 1 TMR1 EXP output2 X amp output2 for internal tristate 7 BC 1 RXD input X amp 8 BC 1 TMR2 CLK input X amp 9 BC 1 TMR1 CLK input X amp 0 BC 1 control 0 amp GPIO Output Enable7 1 BC 1 GPIO 7 output3 X 40 0 Z amp BC 1 GPIO 7 input X amp BC 1 control 0 amp GPIO Output Enable6 BC 1 GPIO 6 output3 X 43 0 2Z amp 5 BC 1 GPIO 6 input X amp 6 BC 1 control 0 amp GPIO Output Enabled 7 BC 1 GPIO 5 output3 X 46 0 Z amp 8 BC 1 GPIO 5 input X amp 9 BC 1 control 0 amp GPIO Output Enable4 0 BC 1 GPIO 4 output3 X 49 0 2Z amp 1 BC 1 GPIO 4 input X amp BC 1 control 0 amp GPIO Output Enable3 BC 1 GPIO 3 output3 X 52 0 2Z amp BC 1 GPIO 3 input X amp 5 BC 1 control 0 amp GPIO Output Enable2 6 BC 1 GPIO 2 output3 X 55 0 Z amp 7 BC 1 GPIO 2 input X amp 8 BC 1 control 0
74. after HSEL inactive high tHDWH o o jw IIe All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 119 of 157 12 5 Host read address tus lusu HSEL tuwnrs lies p w luwnRH HWRnRD tupnas ce p iq lHDnAH HDATnADR E thov p ig btn register address valid HDATA Description Symbol E ei e EN HSEL active low DEEL active low pulse width DEEL active low pulse width me HWRnRD setup before HSEL active low tHWnRS E E HDATnADR setup before HSEL active low tHWnRH s Jp pj HWRnRD hold after HSEL inactive high tHWnRH ONS HDATnADR hold after HSEL inactive high AHDNAH HDATA enable after HSEL active low and tHDE HWRnRD low HDATA valid after HSEL active low and tHDV HWRnRD low HDATA hold after HSEL inactive high HDH All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 120 of 157 12 6 Host read data tus Ka tHsH HSEL tHwnrs PS M HWnRH HWRnRD HDmAS g Si HDnAH HDATnADR HDATA NN register data valid Description Symbol Min 5 V E WE we HSEL active low DEEL active low pulse with DEEL active low pulse with ns le TI ei m ecm pa
75. after or during the last data byte the SMCS116SpW generates an EEP character for the SpaceWire link IOB 14 TRM EOP ACK TRMEOP TRMEEP acknowledge signal FIFO controller sent EOP EEP character 9 5 3 2 2 Read data from the internal SMCS116SpW FIFO eler e signal en Je o menm 0000000 oem women o rooms oe EOPL UO Marker signal of the EOP EEP character on the low data byte DO D7 when F_CTRL D4 1 IOB 27 EOPH UO Marker signal of the EOP EEP character on the high data byte D8 D15 when F_CTRL D4 1 DATA 0 15 DATA O 15 I O Z Data lines 0 15 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS Li User Manual Date 16 06 2008 E E Lr iLum Page 83 of 157 The signals below are enabled active when F RCV CNTL Bit D3 0 and F_CTRL Bit D4 0 IOB 16 RCVEOP The FIFO controller generates an end of packet EOP signal after the last data byte of the received packet IOB 17 RCVEEP The FIFO controller generates an end of packet EEP signal after the last data byte of the received packet IOB 26 RCV_EOP_ACK a RCVEOP RCVEEP acknowledge signal The external control is disabled when E RCV CNTL 0x1A Bit D3 1 then Input signal IOB26 RCV EOP ACK is internally disabled Output signals IOB16 RCVEOP and IOB17 RCVEEP are always inactive low All Rights Reserved Copyright per DIN 34 Astrium
76. ail the SMCS116SpW chip The SMCS116SpW provides an interface between a SpaceWire link according to the SpaceWire Standard ECSS E 50 12A and several different interfaces Host interface FIFO interface ADC interface DAC interface RAM interface UART interface JTAG IEEE 1149 1 General purpose UO E E x NM M E d Timer Event Counter A top level block diagram of the SMC116SpW is given in the figure below All Rights Reserved Copyright per DIN 34 SMCS116SpW User Manual Astrium GmbH Rev 1 2 Date 16 06 2008 Page 9 of 157 Link Interface address command bus Host Interface 1 2 List of applicable documents da ADC a VF DAC Lu internal Controller F Control Bus Data Bus Figure 1 SMCS116SpW Block Diagram AD Title Doc No AD1 SpaceWire Links nodes routers and network 24 January 2003 ECSS E 50 12A AD2 SMCS116SpW Requirements Specification SMCS116SpW_RS 01 AD3 SMCSlite User Manual 09 03 2001 DIPSAPII DAS 31 07 Issue 1 1 All Rights Reserved Copyright per DIN 34 DocNo SMCS ASTD UM 116 EADS aseritum Doc No Rev Date Page SMCS116SpW User Manual 1 3 List of Abbreviations Acronym Description AD Applicable Document ASIC Application Specific Integrated Circuit BSDL Boundary S
77. alue of the data out register is read When working with active low signals it is recommended to first write a one to the corresponding bit in the GPIO DOUT register and than second to configure the corresponding pin as output The other way round there may be an unexpected low to high transition because the GPIO DOUT register is set to zero during reset Address Register Description 0x62 GPIOO DIR GPIOO direction register mapped on GPIO7 GPIOO D7 DO each bit defines the I O direction of the corresponding GPIO pin e g DO GPIOO input GAGNE 3 0x63 GPIOO DOUT GPIOO data out E ooo 0x64 GPIOO DIN GPIOO data in GPIOOdatainregister 0 0x65 GPIO1 DIR GPIO1 direction register mapped onto IOB7 IOBO D7 DO each bit defines the I O direction of the corresponding GPIO pin e g D 1OB3 input output 0x66 GPIO1 DOUT GPIO1 data out register r w All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 104 of 157 GPIO1_DIN GPIO1 data in register a 0x68 GPIO2 DIR GPIO2 direction register mapped onto HDATA D7 DO each bit defines the I O direction of the corresponding GPIO pin e g D7 HDATA7 input output GPIO2 DOUT GPIO2 data out register GPIO2 DIN GPIO2 data in register The GPIOO interface is directly mapped on the GPIO7 0 lines The number of avai
78. amp BC 1 CLK input X amp BC 1 NRESET input X amp BC 1 NHINTR output2 X amp output2 for internal tristate BC 1 HWRNRD input X amp BC 1 NHSEL input X amp BC 1 HDATNADR input X amp BC 1 control 0 amp HOCI Data Output Enable7 BC 1 HDATA 7 output3 X 10 0 Z amp BC 1 HDATA 7 input X amp BC 1 control 0 amp HOCI Data Output Enable6 BC 1 HDATA 6 output3 X 13 0 Z amp BC 1 HDATA 6 input X amp BC 1 control 0 amp HOCI Data Output Enable5 0 1 2 3 4 5 6 7 8 9 10 11 4 5 6 7 BC 1 HDATA 5 output3 X 16 0 Z amp 8 9 0 T4 0 1 12 13 BC 1 HDATA 5 input X amp BC 1 control 0 amp HOCI Data Output Enable4 BC 1 HDATA 4 output3 X 19 0 Z amp BC 1 HDATA 4 input X amp BC 1 control 0 amp HOCI Data Output Enable3 BC 1 HDATA 3 output3 X22 0 Z amp BC 1 HDATA 3 input X amp 22 23 24 All Rights Reserved Copyright per DIN 34 Page 147 of 157 EADS me asteritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 148 of 157 32 33 34 42 43 44 52 53 54 5 BC 1 control 0 amp HOCI Data Output Enable2 6 BC 1 HDATA 2 output3 X 25 0 Z amp 7 BC 1 HDATA 2 input
79. aracters 16 characters of buffering is in fact provided Normal characters are data character and EOP EEP Whenever the link input has sufficient buffering available to consume a further 8 normal characters a FCT is transmitted on the associated link output and this FCT gives the sender permission to transmit a further 8 normal characters Once the sender has transmitted a further 8 normal characters it waits until it receives another FCT before transmitting any more characters The provision of more than 8 normal characters of buffering on each link input ensures that in practice the next FCT is received before the previous block of 8 normal characters has been fully transmitted so the character level flow control does not restrict the maximum bandwidth of the link 4 3 Link speeds The SpaceWire links can support a range of communication speeds which are programmed by writing to registers At reset all links are configured to run at the base speed of 10 Mbits sec Only the transmission speed of a link is programmed as reception is asynchronous This means that links running at different speeds can be connected provided that each device is capable of receiving at the speed of the connected transmitter The transmission speeds of the SpaceWire link of the SMCS116SpW is programmed by the register BITRATE 0x02 Possible link speeds are The maximum receive bit rate is 200 MBit s at 5 Volt and 100 MBit s at 3 3 Volt All Rights Reserved Co
80. art and stop the timer it is enabled and disabled with bit O in the TCTRL register With the timer stopped TCOUNT is loaded with the initial count value zero and TPERIOD with the number of cycles for the required interval Then the timer is started when it shall start to count At reset the timer start stop bit in the TCTRL register is cleared so the timer is stopped When the timer is stopped it does not increment the TCOUNT register and it generates no interrupts When the timer start stop is set the timer starts incrementing the TCOUNT register at the end of the next timer clock cycle All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS erna User Manual Date 16 06 2008 Page 102 of 157 9 9 4 2 Timer Interrupt When the value of TCOUNT is equal to the value of TPERIOD the timer generates an interrupt if unmasked in the ISR 9 9 4 3 Timer Output TMR_EXP When the TCOUNT value is equal the TPERIOD value the timer asserts the TMR_EXP output low The duration of TMR_EXP low depends on the configuration Configured to generate periodic interrupts If the timer is configured to generate periodic interrupts bit 2 of TCONFIG is cleared the TMR_EXP output is low for one timer_clock cycle On the next timer_clock cycle after TCOUNT was equal to TPERIOD the timer automatically resets TCOUNT to zero The TPERIOD value specifies the frequency of the
81. can Description Language CPU Central Processing Unit DPRAM Dual Port RAM EEP Error End Of Packet EOP End Of Packet ESC Escape FCT Flow Control Token FIFO First In First Out FPGA Field Programmable Gate Array GPIO General Purpose Input Output HOCI Host Control Interface HW Hardware JTAG Joint Testing Action Group LSB Least Significant Bit LVDS Low Voltage Differential Signalling MSB Most Significant Bit PLL Phase Locked Loop SMCS Scalable Multichannel Communication Subsystem SpW SpaceWire SRAM Static Random Access Memory All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS ASTD UM 116 Astrium GmbH SMCS11 6SpW Doc No SMCS ASTD UM 116 EADS WEI U M l Rev 1 2 Ssstriuom ser Manua Date 16 06 2008 Page 11 of 157 STUP Serial Transfer Universal Protocol UART Universal Asynchronous Receiver Transmitter All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS rent User Manual Date 16 06 2008 Page 12 of 157 2 The need for SMCS116SpW Connecting a non intelligent node to a processing element requires not only the communication controller but usually a controlling instance for the communication circuitry The latter has to be configured for settings like bit rate packet sizes handshake protocols etc Should the non intelligent node require remote control via comman
82. cter over the SpaceWire link EOP EOP External TRANSMIT control signals disable enable SEND RAM PORT ADDRESS over link the controller sends the ram port address register RAM PORT 0x43 as first byte no ramport address is sent D7 D5 reserved All Rights Reserved Copyright per DIN 34 EADS _ aa aseritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 67 of 157 9 4 7 Receive data over SpaceWire link The following registers are needed to transmit data from the SpaceWire link in the memory Address Register Description r w 0x34 RAM RST ADRO D7 DO Receive Start Address Register 0 r w 0x35 RAM RST ADR1 D7 DO Receive Start Address Register 1 r w 0x36 RAM_RST_ADR2 D1 DO Receive Start Address Register 2 r w D7 D2 reserved 0x37 RAM RED ADRO D7 D0 Receive End Address Register 0 r w 0x38 RAM RED ADR1 D7 DO Receive End Address Register 1 r w 0x39 RAM RED ADR2 D1 DO Receive End Address Register 2 rw D7 D2 reserved Ox3A RAM HCH ADRO D7 D0 Current Receive Address Register O r Ox3B RAM RCR ADR1 D7 DO Current Receive Address Register 1 r Ox3C RAM RCR ADR2 D1 D0 Current Receive Address Register 2 r D7 D2 reserved Ox3D RAM RCTRL REG DO Receive start bit no STOP possible r w receive controller starts the transmission of data from the SpaceWire controller to the memory
83. ds usually a second link dedicated for commands is introduced Using a SpaceWire link for that purpose eliminates the need for separate data and control paths since the communication controller can differentiate between the two entities In addition it can be remotely configured can execute simple commands and provides special I O pins to control the interface unit Nevertheless the SMCS332SpW with its three links may be over dimensioned for some applications or a special controlling instance such as an FPGA is still required on the interface node to e g control Analogue to Digital converters etc Thus the need for a smaller with one link only SMCS with more system support for non intelligent nodes was identified and the SMCS116SpW introduced Target requirements for the design were e small package 100 pins e low power consumption e provide sufficient control lines to configure and operate I O devices e provide a configurable memory interface to address standard SRAM memory e g for data buffers and FIFOs e provide additional system support such as timers etc e be manufactured in a radiation tolerant technology 3 SMCS116SpW Features The SMCS116SpW provides one SpaceWire serial communication link with 2 5 to 200 Mbit s data transmit rate It features a link disconnect detection and parity check at character level as well as an additional checksum generation check at packet level Besides the serial SpaceWire link t
84. e The VCC pins should be bypassed to the ground plane using 8 high frequency capacitors 0 1 uF ceramic Keep each capacitors lead and trace length to the pins as short as possible This low inductive path provides the SMCS116SpW with the peak currents required when its output drivers switch The capacitors ground leads should also be short and connect directly to the ground plane This provides a low impedance return path for the load capacitance of the SMCS116SpW output drivers The following pins must have a capacitor 3 4 16 27 56 61 88 and 100 All Rights Reserved Copyright per DIN 34 Astrium GmbH Ta SMCS116SpW Doc No SUCSUASTD LUNGS 16 wg User Manual Date 16 06 2008 eebrium Page 115 of 157 12 Timing Parameters 12 1 Clock la tak CLK la toku tek 5 Volts Description Symbol Es E ES n 3 E Em 3 P CLK CLK period ek 1 Nominal 5 0000 MHz 1 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 asErium Page 116 of 157 12 2 os cio pata Lok DS TMRx_EXP LSO LDO NEN Description Symbol EI M IT ET 3 e ES 3 m RESET setup before CLK high setup before CLK RESET setup before CLK high mes All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS
85. e signal FIFO controller sent EOP EEP character The external control is disabled when register F_TRM_CNTL 0x19 Bit D3 1 then Input signals IOB24 TRMEOP and IOB25 TRMEEP are internally disabled Output signal IOB14 TRM EOP ACK is always inactive low not high impedance 9 5 3 1 2 Write data to the FIFO en e o pes IOB 21 FIFO_FULL E FIFO full signal IOB 15 RCV PAR Data parity signal when F CTRL D4 EOPL UO Marker signal of the EOP EEP character on the low data byte DO D7 when F CTRL D4 1 IOB 27 EOPH UO Marker signal of the EOP EEP character on the high data byte D8 D15 when F CTRL D4 1 DATAO 15 DATAO 15 l O Z Data lines 0 15 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS Li User Manual Date 16 06 2008 aescCrmium Page 80 of 157 The signals below are enabled active when F RCV CNTL Bit D3 0 and F_CTRL Bit D4 0 IOB 16 RCVEOP The FIFO controller generates an end of packet EOP signal after the last data byte of the received packet IOB 17 RCVEEP The FIFO controller generates an end of packet EEP signal after the last data byte of the received packet IOB 26 RCV_EOP_ACK a RCVEOP RCVEEP acknowledge signal The external control is disabled when register F RCV CNTL 0x1A Bit D3 1 then Input signal IOB26 RCV EOP ACK is internally disabled Output signals IOB16 RCVEO
86. egister default OxFE rw 7 1 19 Semaphore Control Register 7 1 20 Reset Registers RST EN Reset enable register RST REG Reset register All Rights Reserved Copyright per DIN 34 EADS aseritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 42 of 157 8 General Registers 8 1 Interface enable Address Register Description r w 0x00 ENABLE enable register for the interface configuration register r w 0x98 expected will be reset after a write to the interface config register 0x01 IFCONF interface configuration register rw DO RAM interface 0 disabled 1 enabled D1 FIFO interface 0 disabled 1 enabled D2 ADC interface 0 disabled 1 enabled D3 DAC interface 0 disabled 1 enabled D4 Send ISR interrupt status register via SpaceWire link 0 enabled 1 disabled D5 Host interface 0 enabled 1 disabled D6 External interrupt 0 disabled 1 enabled All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS ni User Manual Date 16 06 2008 E E L r icum Page 43 of 157 Address Register Description r w D7 UART 2 interface 0 disabled 1 enabled 8 2 Interrupts When a specific interrupt is enabled corresponding bit set to one by the interrupt mask r
87. egisters the signal HINTR of the host interface will be activated or the interrupt status registers will be sent over the SpaceWire link depending on the setting of bit D4 of the interface configuration register IFCONF 0x01 8 2 1 Interrupt Signal HINTR o host interrupt request line 8 2 2 Interrupt Masking All SMCS116SpW interrupts can be masked using the registers below Address Register Description r w 0x5C IMR O D7 DO Interrupt mask register bit 7 0 r w Ox5D IMR 1 D7 DO Interrupt mask register bit 15 8 r w Ox5E IMR 2 D3 D0 Interrupt mask register bit 19 16 r w D7 D4 reserved 8 2 3 Interrupt Status Registers When an interrupts is raised by the SMCS116SpW the corresponding interrupt source is flagged in the Interrupt Status Registers All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 44 of 157 Address Register Description r w Ox5F ISR 0 D7 DO Interrupt status register 7 0 r DO Checksum error D1 Protocol command error D2 Protocol command length error D3 SpaceWire link error D4 Write to protected register IFCONF D5 FIFO interface transmit EOP D6 FIFO interface data parity error D7 FIFO interface receive EOP EEP 0x60 ISR 1 D7 D0 Interrupt status register 15 8 r DO RAM interface transmit EOP D1 RAM receive end
88. er Please check bit D1 of the status register whether or not there are data in the FIFO Bit D1 of the status register HFSTR is set when the input FIFO is not empty Bit D2 of the status register HFSTR is set when the host FIFO received the EOP marker Bit D3 of the status register HFSTR is set when the host FIFO received the EEP marker The status register is reset after each read HFIFO PORT is the port address for the SMCS116SpW protocol All Rights Reserved Copyright per DIN 34 EADS aseritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 63 of 157 9 4 RAM interface 9 4 1 RAM Interface enable The RAM interface is enabled with the following sequence of register writes 1 write 0x98 to register ENABLE 0x00 2 set lower nibble of register IFCONF 0x01 to 1 bit pattern xxxx 0001 9 4 2 RAM interface signals The pin allocation of the SMCS116SpW signals used for the RAM interface is shown below Signal RAM I F signal UO Description IOB 15 0 RAM ADDR 15 0 O address lines 15 0 IOB 16 WR O write strobe IOB 17 RD O read strobe IOB 18 CSO O chip bank select 0 IOB 19 CS1 O chip bank select 1 IOB 20 CS2 O chip bank select 2 IOB 21 CS3 O chip bank select 3 DATA 15 0 RAMDATA 15 0 O Z data lines 15 0 IOB22 RAM TEST O only for test do not connect this signal All Rights Rese
89. es an interrupt after the transmission of the EOP marker RAM interface receive end address interrupt When the RAM interface is enabled the RAM interface receive module generates an interrupt when the ram current address register RAM RCR ADDRx 0x3A Ox3C is equal to the ram end address register RAM RED ADDRXx 0x37 0x39 RAM interface receive error When the RAM interface is enabled the RAM interface receive module generates an interrupt when a the ram current address register RAM RCR ADDRx 0x3A 0x3C is equal to the ram end address register RAM RED ADDRx 0x37 0x39 b The ram receives 1 or more additional bytes RAM interface receive EOP EEP When the RAM interface is enabled the RAM interface module generates an interrupt after the receipt of the EOP EEP marker Timer 1 expired Timer 1 generates an interrupt when the value of the timer count register TCOUNT 1 x 0x44 0x47 is equal to the value of the timer period register TPERIOD1 x 0x44 0x47 Timer 2 expired Timer 2 generates an interrupt when the value of the timer count register TCOUNT2 x 0x4A Ox4D is equal to the value of the timer period register TPERIOD2 x 0x4A Ox4D All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS116SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS ros User Manual pue 16 06 2008 D6 External interrupt 0 When the external interrupt input is enabled bit D6 of the interface
90. eserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aseritum Page 48 of 157 8 3 Resets The SMCS116SpW can be reset by writing register RST_REG 0x7F or can be reset automatically on a link disconnect or parity error These two reset sources can be enabled separately by writing register Ox7E 8 3 4 Reset Registers uem aee teme e Ox7E RST EN DO enable access to the reset register D1 enable automatic reset if SMCS116SpW if disconnect or parity error occurred D7 D2 reserved Ox7F RST REG DO Reset SMCS116SpW auto reset D7 D1 reserved 8 4 Semaphore The SMCS116SpW provides a semaphore register 0x7D The semaphore is an 8 bit wide read write register The semaphore can be used to exchange information between the SpaceWire link interface and the host control interface The semaphore register is D7 DO semaphore register All Rights Reserved Copyright per DIN 34 EADS aseritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 49 of 157 8 5 STUP Registers Address Register Description r w 0x78 P MODE EN Protocol Mode Enable Register A write access with the value 0x24 enables one write access to the following registers r w 0x79 P_CONTROL Protocol Control Register DO
91. ev 1 2 EADS at User Manual Date 16 06 2008 aescCrmium Page 137 of 157 12 21 1 Test Port Reset TDO trooz TRST trrst Description Symbol Min 5 V il 3 3 V 3 3 V TDO disable after TRST actvelow disable after TRST active low TDO disable after TRST acivelw Jop me le EE All Rights Reserved Copyright per DIN 34 Astrium GmbH EADS SMCS11 6SpW Ges No lege 16 we User Manual Date 16 06 2008 aserium Page 138 of 157 13 Mechanical Data 13 1 Package Dimensions D DI NI yY gt gt T ro viH 25 C lt A Index Corner 100 Pin Ceramic Quad Flat Pack MQFPF SYMBOL All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 116 Rev 1 2 User Manual Date 16 06 2008 Page 139 of 157 EADS eeabriL rm SYMBOL MILLIMETERS INCHES MIN MAX MIN MAX p Dem 0025 p 0 254 ref 0 010 ref K pe o be je SSES LC ke Je ke 25 25 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS ASTD UM 116 EADS User Manual ds 15092005 zmEirium Page 140 of 157 13 2 Pin Assignment The table below lists the pins of the SMCS116SpW and their function be Co Rope Jk Je bk mp Bom Jk Jee m ma Bom Jk e em Mo Te je e km ko mw jm eme bw m em B pem B eme E eme
92. gister ISR_1 Update description of D2 in register ISR_1 Chapter 8 6 add description for bit D3 amp D4 Chapter 9 1 4 Add note to the HDRCTRL register description Add bit D1 in register description of CHKEN Chapter 9 1 5 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS ni User Manual Date 16 06 2008 aseritum Page 3 of 157 Revision Date Responsible Modifications Add additional information about the checksum generation Chapter 9 4 7 Add a note Chapter 9 6 2 Update of the signal table Chapter 9 8 2 Add note for the use of the RTS singal Chapter 9 8 4 Add additional information for the 3 3 volt mode Chapter 9 9 2 Add additional information for the 3 3 volt mode Chapter 12 8 Add new timing figures for RAM interface read in 16 bit mode Contributions from Lars Stopfkuchen Mohsin Syed Isaac Tejerina All Rights Reserved Copyright per DIN 34 Copying of this document and giving it to others and the use or communication of the contents thereof are forbidden without express authority Offenders are liable to the payment of damages All rights are reserved in the event of the grant of a patent or the registration of a utility model or design Proprietary Notice This document is the property of Astrium GmbH and contains material proprietary to
93. he SMCS116SpW provides several different interface types e Host interface e FIFO interface e ADC interface e DAC interface e RAM interface e UART interface All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS ros User Manual Date 16 06 2008 Page 13 of 157 e JTAG IEEE 1149 1 e General purpose UO e Timer Event Counter FIFO interface The FIFO interface provides the control signals full write empty and read depending on the direction of the data flow receive transmit Data received from the FIFO interface is sent over the SpaceWire link grouped in packets The length of a packet in bytes can be specified either by setting an internal counter or by external signals This interface can be programmed to use 0 to 7 wait states ADC DAC interface The ADC interface allows connecting an ADC with a width of up to 16 bits directly to the SMCS116SpW The AD conversion can be started by request via link or in a cyclic manner triggered by the on chip timers When the AD conversion is ready this is recognized by an external signal like ready or by an internal trigger for example from the on chip timer After reading the sample from the ADC it is then sent over the link An 8 bit address generator is provided to allow multiplexing of analog signals The address generator will start at a pre programmed start address and will be incremented afte
94. hts Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS ros User Manual Date 16 06 2008 Page 17 of 157 see following figure always contain an odd number of 1 s The coding of the characters is shown in the table below To ensure the immediate detection of parity errors and to enable link disconnection to be detected NULL characters are sent in the absence of other characters Data token Control token Parity bit Parity bit Data flag Control flag Token type Data eg FCT TENEO 1 2 ug a 0 0 Data A Y Bits covered by parity bit in control token RSA Strobe EE Control codes Null NULL ESC FCT P1110100 Time Code ESC DATA P11110DDDDDDDD P Parity bit D Data bit All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS ros User Manual Date 16 06 2008 Page 18 of 157 4 2 Character level flow control Character level flow control is performed in each DS Link module and the additional flow control characters used are not visible to the higher level packet protocol The character level flow control mechanism prevents a sender from overrunning the input buffer of a receiving link Each receiving link input contains a buffer for at least 8 ch
95. ite 0x08 to register DAC DATAO 0x25 5 write 0x18 to register DAC DATA register 0x26 6 write 0x02 to register DAC ADDR 0x27 Start DA conversion 7 write 0x01 to register DAC CTRLO 0x28 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS User Manual Date 16 06 2008 zmEirium Page 94 of 157 9 8 UART Interface The SMCS116SpW provides two UARTs Each UART can be configured and controlled independently The UART baud rate will be programmed by writing the 2 baud rate registers UART BR1 and UART BR2 The configuration of the UART protocol is done by writing the UART_CTRL register The UART status can be read via the UART status register UART ST Each UART has a 4 byte FIFO in transmit and a 4 byte FIFO in receive direction 9 8 1 UART Signals Signal UO Description RxD1 receive data to UART1 TxD1 O transmit data from UART1 RTS1 O Ready to send UART1 CTS1 Clear to send UART1 RxD2 receive data to UART2 TxD2 O transmit data from UART2 RTS2 O Ready to send UART2 CTS2 Clear to send UART2 9 8 2 UART1 Registers pase e eme UART1_TD D7 DO TRANSMIT DATA OVER SIGNAL TXD UART1 RD D7 DO RECEIVED DATA FROM SIGNAL RXD UART1 BR1 D7 DO BAUD RATE 1 BYTE LOW S 0x58 UART1 BR2 D3 D0 BAUD RATE 2 BYTE HIGH D7 D4 reserved All Rights Reserved Copyright per DIN 34 EAD
96. ksum generation is enabled Note In the old SMCS116 AD3 user manual the description was not correct 0x14 CHKEN Enable Checksum generation r w DO 0 Disable checksum generation default Enable checksum generation D1 0 Enable SMCS332SpW mode checksum generation default 1 Disable SMCS332SpW mode checksum generation D7 D2 reserved Examples 1 The header bytes could be use to build the destination addresses if wormhole routing is in place All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS be paren User Manual Date 16 06 2008 Page 58 of 157 2 Another possibility is to load the header register 0 HDRO with a port address of the SMCS116SpW e g FIFO port address 0x1C 9 1 5 Packet Header Checksum Generation and Wormhole Routing In case checksum generation is enabled bit O of the CHKEN register 0x14 is set a two byte checksum is appended to each transmit packet If checksum generation and wormhole routing with header deletion is combined in a system the destination address es must be excluded from the checksum If not the two checksums will never be equal because the destination address es is deleted on the receiving side The contents of bit D7 D4 of HDRCTRL register defines how many header bytes are excluded from the checksum generation The figure below shows the result of the f
97. l Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 99 of 157 9 9 Timers The SMCS116SpW has two programmable interval timers Each timer can generate periodic interrupts or only one interrupt depending on configuration The timer will be programmed by writing the 4 bytes of the 32 bit TPERIOD registers The configuration is done by writing the TCONFIG register The timer operation is controlled through a bit in the TCTRL register An external output TMR EXP signals to other devices that the timer count has expired An external input TMR_CLK is provided which can be used as trigger source for the timer 9 9 1 Timer Signals sient o em TMR1 CLK imer clock max 12 5 MHz 5V max 6 MHz 3 3V TMR1 EXP timer1 expired Asserted for one cycle or toggle depends on bit D3 of TCONFIG if the value of counter1 is equal to the content of register TPERIOD1 3 0 starts with high level TMR2 CLK Weer clock max 12 5 MHz max 6 MHz 3 3V TMR2 EXP timer2 expired Asserted for one cycle or toggle depends on bit D3 of TCONFIG if the value of counter2 is equal to the content of register TPERIOD2 3 0 9 9 2 Timer Registers Register Description TCOUNTx 0 D7 DO Period Count value RegisterO LSB TPERIODx 0 TCOUNTx 1 D7 DO0 Period Count value Register1 TPERIODx 1 TCOUNTx 2 D
98. lable lines depends mainly on the configuration of the two UARTS Please also see the section 4 2 on GPIO signals The availibity of the GPIO1 interface depends on the configuration of the ADC interface There are two possibilities to enable GPIO1 First the ADC interface is disabled in register IFCONF 0x01 Second the ADC interface is enabled but an external analog multiplexer is not used bit 6 of ADC CTRLO 0x21 is cleared In both cases the GPIO1 interface is mapped on the pins IOB 7 0 If an application does not require a host interface the host interface can be disabled in register IFCONF 0x01 In this case the GPIO2 interface is mapped on the HDATA pins 9 11 JTAG Interface For testing purposes a standard IEEE 1149 1 interface is provided It supports the JTAG functions Bypass Extest Sample Preload All Tristate and IDCode All Rights Reserved Copyright per DIN 34 EADS aseritum SMCS116SpW User Manual Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 105 of 157 10 Signal Description This section describes the signals of the SMCS116SpW Groups of signals represent busses where the highest number is the MSB RESET CLK HSEL HWRnRD HDATnADR HDATA 7 0 LDI LSI TMR1 CLK TMR2 CLK RxD1 DATA 15 0 GPIOO GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 IOB18 IOB19 IOB20 IOB21 IOB22 IOB23 IOB24 IOB25 IOB26 IOB27 TRST TCK
99. m SMCS116SpW User Manual Astrium GmbH Rev 1 2 Date 16 06 2008 Page 56 of 157 BITRATE Register Link Speed 5V Link Speed 3 3 V D3 DO Mbit s Mbit s 0100 25 50 0101 33 100 0110 50 100 0111 100 100 1000 150 100 1001 200 100 1010 to 1111 reserved reserved All Rights Reserved Copyright per DIN 34 DocNo SMCS ASTD UM 116 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 57 of 157 9 1 4 Packet Header Registers The packet header registers are used to form a packet header from 0 to 8 bytes This packet header will be sent in front of each transmit packet Bit 7 4 of the header control register HDRCTRL contains the number of header bytes Address Register Description r w 0x0B HDRO D7 DO Packet Header 0 register r w 0x0C HDR1 D7 DO Packet Header 1 register r w OxOD HDR2 D7 DO Packet Header 2 register r w OxOE HDR3 D7 DO Packet Header 3 register rw OxOF HDR4 D7 DO Packet Header 4 register r w 0x10 HDR5 D7 DO Packet Header 5 register r w 0x11 HDR6 D7 DO Packet Header 6 register r w 0x12 HDR7 D7 DO Packet Header 7 register r w 0x13 HDRCTRL Packet Header control register r w D3 D0 total number of header bytes 0 to 8 D7 D4 Number of header bytes excluded from transmit checksum generation if chec
100. nals if 0x00 lt iADDR9 17 RAM BNDO then CSO is active else if RAM BNDO lt iADDR9 17 RAM BND1 then CS1 is active else if RAM BND1 lt iADDR9 17 RAM BND2 then CS2 is active else if RAM BND2 lt iADDR9 17 RAM BND3 then CS3 is active else no chip select is active RAM BND3 lt iADDR9 17 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aseritum Page 69 of 157 9 4 9 RAM I F wait states This register is used to program the number of wait states 0 to 7 for read write access to the external RAM N NENNEN e 0x42 RAM WS REG Wait state control register DO wait states default 0x0 D3 reserved 9 4 10 SMCS116SpW protocol RAM interface port This address forms the destination address for data sent over the SpaceWire link to the memory and the header address if enabled for data from the memory Address Register Description r w 0x43 RAM_PORT RAM port address link only If data is received via the SpaceWire link the destination address byte 0x43 is stripped off deleted This means that the destination byte is not forwarded written to the memory All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS116SpW DocNo SMCS ASTD UM 116 Rev 1 2 EADS 1 User Manual Date 16 06 2008 Saserium Page 70 of 1
101. nals go from the high impedance state in the inactive state 9 4 5 RAM I F Control Register The internal RAM I F address bus iADDRO 17 is 18 bit wide the lower address signals iADDRO 15 are connected with the RAM I F address signals RAM ADDRO 15 The upper address signals iADDR9 17 are used for generating the bank chip select signals CS0 3 9 4 6 Transmit data over SpaceWire link The following registers are needed for transmitting data from the memory over the SpaceWire link r w Ox2C RAM TST ADR2 Transmit Start Address Register 2 D2 D7 reserved RAM TED ADRO Transmit End Address Register 0 r w RAM TED ADR Transmit End Address Register 1 Ox2F RAM TED ADR2 Transmit End Address Register 2 r w D2 D7 reserved RAM TCR ADRO Transmit Current Address Register 0 RAM_TCR_ADR1_ Transmit Current Address Register 1 0x32 RAM TCR ADR2 D1 D0 Transmit Current Address Register 2 r D2 D7 reserved All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 66 of 157 0x33 RAM_TCTRL_REG D0O Transmit start bit stop the transmit controller starts the transmission of data from the memory to the SpaceWire controller RAM data bus width 8Bit 16Bit If the current memory address is equal with the end address the controller stops the transmission of data and sends an EOP chara
102. ng read the host reads writes address from to the address register HDATA T 0 UO SMCS116SpW data bus 3 50 This data lines will be used to access the SMCS116SpW registers HDATA 7 0 can also be used as GPIO 2 if Host interface is disabled HINTR o host interrupt request line TMR1 CLK timer clock max 12 5 MHz EMEN TMR1 EXP timer1 expired Asserted for one cycle if the 3 50 value of counter1 is equal to the content of register TPERIOD1 3 0 TMR2 CLK timer2 clock max 12 5 MHz All Rights Reserved Copyright per DIN 34 Astrium GmbH e SMCS116SpW Doc No SUCSUASTD ING 16 we User Manual Date 16 06 2008 eebrium Page 107 of 157 wo m pe TMR2 EXP timer2 expired Asserted for one cycle if the 3 value of counter2 is equal to the content of register TPERIOD2 3 0 Rm p jeeemewm 1 por e kenen NN NN o Lane o jp one II e o apen ek o p bann ek crore e Esser 2 IOB 27 0 Control bus The SMCS116SpW controls the see note 25 connected interface via these lines The 1 function of each control signal is described in a cni table mer 1 Test Reset Resets the test state machine Reset Resets the test state machine Test Clock Provides an asynchronous clock for JTAG boundary scan Test Mode Select Used to control the test state machine This input should be left unconnected or tied to ground during normal operation Test Data Input Provides serial data for the bo
103. o ensure that there is space for another byte Otherwise data could be lost Data received on RxD can be read out by reading the UARTx_RD register Received data must be read in time to prevent data overflow UART connected to SpW link The other possibility is to connect the UART to the SpW link In this case each byte received on RxD is directly forwarded as single packet to the SpW link To transmit data via the signal TxD a packet is sent to the UART port This means that the first byte of the transmit packet has to contain the UART port address The packet length is unlimited It could be one to several bytes All Rights Reserved Copyright per DIN 34 Astrium GmbH L SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS rot User Manual Date 16 06 2008 Page 98 of 157 9 8 6 UART Protocol The figure below shows the protocol of the UART start bit parity bit En sa 4 DO D1 D2 D3 D4 D5 D6 D7 P LSB MSB stop bit1 The UART protocol is defined by writing bit 2 bit 3 and or bit 4 of the UART_CTRL register Bit 7 of the UART_CTRL register defines if the control lines RTS CTS are used or not 9 8 7 UART SpaceWire packet Each byte received from the signal RxD is sent via the SpaceWire link as a single packet To add the UART PORT Address in front of the received byte bit 5 of the UART_CTRL register must be set Al
104. oc No SMCS ASTD UM 116 EADS User Manual e m murium sd 52 of 157 Address Register Description r w 0x76 TIME CODE _ time code value register r w D7 DO After a write access to this register the new value will be send as a time code character over the Space Wire link All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 53 of 157 9 SMCS116SpW Modules and Interfaces This chapter describes the individual SMCS116SpW modules and interfaces and their operation modes The interfaces can be programmed either via the SpaceWire link or the host interface 9 1 Link interface 9 1 1 Link interface signals sw vm kso o Late ouput 9 1 2 SpaceWire Link Registers Address Register Description r w 0x07 MODE link mode register DO reserved always 0 D6 D1 reserved D7 test mode if set enables access to register LINKTEST 0x0A 0 disable 1 enable r w All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS w ec User Manual Date 16 06 2008 Page 54 of 157 Address Register Description r w 0x08 START link start register r w DO if set the SpaceWire cell goes in the Error Reset state See AD1 This bit is autoreset by i
105. ocol with two wires in each direction one for data and one to carry a strobe signal and are also referred to as data strobe DS Links Each DS pair carries characters and an encoded clock The characters can be data or control characters The figure below shows the format of data and control characters on the data and strobe wires Data characters are 10 bits long and consist of a parity bit a flag which is set to 0 to indicate a data character and 8 bits of data Control characters are 4 bits long and consist of a parity bit a flag which is set to 1 to indicate a control character and 2 bits to indicate the type of control character The DS Link protocol ensures that only one of the two wires of the data strobe pair has an edge in each bit time The levels on the data wire give the data bits transmitted The strobe signal changes whenever the data signal does not These two signals encode a clock together with the data bits permitting asynchronous detection of the data at the receiving end The data and control characters are of different lengths for this reason the parity bit in any character covers the parity of the data or control bits in the previous character and the data control flag in the same character as shown in the above figure This allows single bit errors in the character type flag to be detected Odd parity checking is used Thus the parity bit is set unset to ensure that the bits covered inclusive of the parity bit All Rig
106. ollowing configuration EE packet header SpaceWire 4 oxBA OxBE OxCA OxFE Ox12 data byteO data byte1 e a e data byteN chks byteO chks bie EOPx Covered by checksum Note HDRCTRL D3 0 5 the value of HDRO first until HDR4 last will be sent over the SpaceWire at the beginning of the packet HDRCTRL D7 4 2 the value of HDRO amp HDR1 will be excluded from the checksum generation All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS rent User Manual Date 16 06 2008 Page 59 of 157 The Checksum generation adds all data bytes and if not excluded the packet header bytes in the following manner When register CHKEN D1 0 then checksum 16 0 checksum 16 0 data 7 0 checksum 16 When register CHKEN D1 1 then checksum 16 0 checksum 16 0 data 7 0 The checksum is generated as shown in the following figure CHKEN D1 0 DATA GE EE af CS 17 The first checksum byte chks byteO send over SpaceWire contains the value of checksum 7 0 The second checksum chks byteO byte send over SpaceWire contains the value of checksum 15 8 All Rights Reserved Copyright per DIN 34 EADS m aseritum Astrium GmbH SMCS116SpW Doc No SMCS ASTD UM 11
107. port address 9 6 3 1 ADC sample data width Register ADC CTRLO 0x21 bit D5 defines if a single sample consists of up to 8 or more than 8 bits up to 16 bits This implies that a sample can be transmitted by one byte or that two bytes have to be used Register ADC CTRLO 0x21 bit D5 can be configured to be 8 bit or 16 bit In the case of 8 bit width the content read on the SMCS116SpW signals data 7 0 are transmitted via link In the case of 16 bit width the content read on the SMCS116SpW signals data 7 0 are transmitted as sample byteO and the content read on the SMCS116SpW signals data 15 8 are transmitted as sample byte1 It depends on user requirements how to connect the ADC to the SMCS116SpW for example a 12 bit ADC to the 16 bit data bus of the SMCS116SpW 9 6 4 Packet composition and forming The bits D4 DO of the register ADC CTRLO 0x21 are used to compose build the packets which are transmitted via the link Bit 5 of the ADC CTRLO is used to define if a sample converted analogue value consists of one byte or two bytes The following are some examples of composed packets D5 DO 0x00 0x24 ADR ADDR ByteO Byte1 EOP D5 DO 0x02 0x24 ByteO Byte1 EOP D5 D0 0x13 0x03 ByteO Byte1 EOP D5 DO 0x33 0x23 ByteO EOP All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS_ASTD_UM_116 Rev
108. pyright per DIN 34 EADS m aseritum SMCS116SpW User Manual Astrium GmbH Doc No Rev 1 2 Date 16 06 2008 Page 19 of 157 SMCS ASTD UM 116 BITRATE Register Link Speed 5 V Link Speed 3 3 V D3 DO Mbit s Mbit s 0000 2 5 2 5 0001 5 5 0010 10 default 10 default 0011 20 25 0100 25 50 0101 33 100 0110 50 100 0111 100 100 1000 150 100 1001 200 100 1010 to 1111 reserved reserved 4 4 Errors on links Link inputs can detect parity and disconnection conditions as errors A single bit odd parity system will detect single bit errors at the link character level The protocol to transmit NULL characters in the absence of other characters enables disconnection of a link to be detected A disconnection error indicates that 1 the link has been physically disconnected 2 an error has occurred on the link or at the other end of the link which may have then stopped transmitting The status bits in the STATUS register flag a parity and or disconnection error that has occurred on the link A parity and a disconnect error can be detected independently When a SpW link detects a parity error on its input it halts its output This is detected as a disconnect error at the other end of the link causing this to halt its output also Detection of an error causes the link to be stopped Thus the disconnect behaviour ensures tha
109. r ADC_STR 0x1D Load number of last channel 5 write OxOA to register ADC_END 0x1E All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS rent User Manual Date 16 06 2008 Page 89 of 157 Configure ADC HE 6 write 0x06 to register ADC CTRL1 0x22 o 280 ns setup and pulse width o Start conversion if bit of ADC CTRL2 0x23 is set o conversion ready terminated by on chip timer1 Load conversion time to Timer1 This example uses a conversion time of 35 us and an internal clock of 12 5 MHz 80 ns The resulting conversion time for register TCOUNT1 0x44 is therefore 35us 80ns 0x1B6 7 write OxB6 to register TCOUNT1_0 0x44 8 write 0x01 to register TCOUNT1_1 0x45 Configure Timer1 9 write 0x24 to register TCONFIG1 0x49 o clock source 12 5 MHz o Stop at interrupt o start timer by adc Load analogue multiplexer propagation delay to Timer2 In this example this is 266 us 80 ns OxCFD 10 write OXFD to register TCOUNT2 D 0x4A 11 write OxOC to register TCOUNT2 1 0x4B Configure Timer2 12 write 0x24 to register TCONFIG2 addr Ox4F o clock source 12 5 MHz o Stop at interrupt o Start timer2 by start stop bit DO of TCTRL2 Ox4E Start AD conversion 13 write 0x01 to register ADC_CTRL2 0x23 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Re
110. r each conversion The DAC interface is very similar to the ADC interface It provides up to 16 data lines and the required control signals The data to be sent to the DAC is received from the link and is stored in a register until the command start DAC is received After that command the register values will be put to the DAC Memory Interface The RAM interface provides a 16 bit data bus and 16 bit address bus Four chip select lines allow addressing four different memory partitions banks This partitioning into different banks is done using 4 internal address boundary registers These are 8 bit wide and provide a minimum page size of 1024 words The memory interface can be programmed to use 0 to 7 wait states GPIO Interface The general purpose UO GPIO Interface provides up to 24 bidirectional signal lines The direction input or output of each GPIO line can be set individually via register Data to from the GPIO lines is written read via the GPIO data register The GPIO provides 8 dedicated UO lines the remaining 16 lines of the port are shared with the ADC address and host data bus These GPIO lines are available when the corresponding unit e g the host data bus of the SMCS116SpW is not being used disabled UART interface All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS e User Manual Date 16 06 2008 Page 14 of 157 Two
111. ransfer goes via the SpaceWire link 9 8 3 UART2 Registers These registers have the same functionality as those for UART1 9 8 4 UART Baud Rate The formula for the calculation of the values of the baud rate registers is In 5 volt mode Baud rate register value 25000000 32 baud rate 1 In 3 3 volt mode Baud rate register value 12500000 32 baud rate 1 The table below shows the values of the baud rate registers for the most important baud rates in the 5 and 3 3 Volt mode Baud rate bits s Baud rate bits s 5 volt mode 3 3 volt mode 2400 1200 0X44 4800 2400 OXA2 9600 4800 0X50 19200 9600 0x00 0X28 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescrmium Page 97 of 157 Baud rate bits s Baud rate bits s 5 volt mode 3 3 volt mode 38400 19200 0X13 56000 28000 OXOD 115200 57600 0x00 0x06 9 8 5 UART Configuration The UART_CTRL register stores the configuration of the UART The UART itself can be connected to the host interface or to the SpaceWire link This connection is made by setting or clearing bit 1 of the UART_CTRL register UART connected to host interface If the UART is connected to host interface D1 0 UART_CTRL data is transmitted by writing data to the UARTx_TD register Before writing any data to UARTx_TD the bit DO in the UARTx_ST register must be checked t
112. received 1 EEP received D6 internal FIFO empty Status 0 not empty 1 empty All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS so User Manual Date 16 06 2008 aescCrmium Page 77 of 157 NI NN ANNE Ox1B F CTRL FIFO I F control register DO FIFO mode selector 0 active FIFO mode r w to an external FIFO 1 passive FIFO mode external controller writes to internal FIFO D3 D1 waitstates 0 7 D4 FIFO mode selector 0 old SMCS116 mode 1 new SMCS116SpW mode D7 D5 reserved 0x1C FIFO_PORT FIFO I F port address Destination address for incoming data over the SpaceWire link header byte for the transmit packet NOTE 1 The size of the packet to be transmitted is always one byte more than written to the F PSIZEx registers A packet with a size of one byte therefore requires the value O in the register F PSIZEO and F_PSIZE1 2 Single shot mode send only one packet that means that after the internal generation of the EOP character all internal FIFO s will be cleared 3 old SMCS116 mode external control and status signals are disabled In this mode the EOP EEP character will be written in the external active mode or internal passive mode FIFO without a signal RCVEOP RCVEEP are disabled All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev
113. rved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 64 of 157 9 4 3 External status signals The status signals of the SMCS116SpW for the RAM interface are used as shown below depending on the actual settings WHEN external transmit control enabled REGISTER 0x33 Bit D3 IOB 23 TRM RDY transmit ready if active high transmit current address transmit end address WHEN external receive control enabled REGISTER 0x3D Bit D3 IOB 24 RCV_RDY receive ready if active high Receive current address receive end address 9 4 4 External control signals IOB25 BUS REQ bus request active low if active low all ram I F signals goes in the high impedance state the ram I F stops When external transmit control signals are enabled register RAM TCTRL REG 0x33 bit D3 1 IOB26 START TRM start signal active high transmit packet read data from RAM When external receive control signals are enabled register RAM RCTRL REG 0x3d bit D3 1 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 65 of 157 IOB26 START RCV start signal activ high receive packet write data to RAM After the RAM interface is enabled the RAM interface sig
114. s opem o bes bauer ler o ies bauer o fonc aona o eg RAM Appen O FIFO TRM EOP ACK ol loB 5 RAM_ADDR15 Io FIFO RCV PAR FIFO EOPL I ee RAM wR Io FIFO RCVEOP ber ba opro bee peres o pro es bauer ie ken bar ies ke peres ie bes peces opec jos bam o poc eng RAM RCV RDY Io FIFO TRMEOP bes pansus near v pro ben baam 1 piro rev corae ber sw START rov 1 piro ram Panero tors fro All Rights Reserved Copyright per DIN 34 UO der ME LL pepe CFo ET NN NE ELT MMC MUN BFOUREWCPAREEGEES HE Wl Jd Lc ele LL Br E MEE L1 EM LL Kl LC NN E NENNEN NN L1 Astrium GmbH SMCS11 6SpW Doc No SMCS ASTD UM 116 EADS E weg User Manual Ge 10082005 ascrium Page 110 of 157 10 2 GPIO Signals The pins GPIOO to GPIO7 are either mapped on register GPIOO 0x63 0x64 or miscellaneous UO signals depending on the register settings as shown in the table below KSE epon RTSUUARM o UART1 CTRL 0x59 D7 ena CTS1 UARTA ju UART1_CTRL 0x59 D 7 IgPlon ExrIREQ IFCONF 0x01 D6 ep ExT IREA jh IFCONF 0x01 D 6 IGPlos mb2 UART2 lo IFCONF 0x01 D7 opge RxD2UART2 i IFCONF 0x01 D7 opge RTSZ UARTI2 o UART2_CTRL 0x72 D7 IaPlo CTS2 UART2 i UART2_CTRL 0x72 D7 All Rights Reserved Copyright per DIN 34 Astrium GmbH e SMCS116SpW Doc No SESCH 16 we User Manual Date 16 06 20
115. ser Manual p 16 08 2008 HDATAT 0 are now GPIC2 7 0 Signal UO Description HSEL hold HSEL high inactive HWRnRD disabled HDATnADR disabled HDATAT 0 l O Z data lines from GPIO2 register HINTR O do not connect this signal the level is undefined 9 3 Host FIFO Address Register Description r w 0x50 HFTRD D7 DO Transmit data register W 0x51 HFTREOP Transmit EOP Register w A write on this register sends an EOP over the Space Wire link D7 DO OxXX 0x52 HFRVD D7 DO Receive data register r 0x53 HFSTR D3 D0 Status register r DO Transmit FIFO full D1 Receive FIFO not empty generates an interrupt D2 EOP received D3 EEP received D7 D4 reserved 0x54 HFIFO PORT Host FIFO port address link only All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS116SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS User Manual Date 16 06 2008 eeabriL rm Page 62 of 157 9 3 1 Transmit receive host data over from the SpaceWire link Write to the transmit data register HFTRD transmits the host data over the SpaceWire link Write to the transmit EOP register HFTREOP transmits the EOP marker over the SpaceWire link Write 0x01 or 0x02 for EOP Write only to the registers HFTRD and HFTREOP when bit DO of the host FIFO status register HFSTR is not set FIFO not full The host can read received data from the SpaceWire link from the HFRVD regist
116. st address and data bus The selection of which functions are being used is made by programming the appropriate registers after a chip reset A short overview of the pin allocation and combinations of functions is given in the table below Interface Example Mode Type 1 2 3 Host GPIO2 Timer1 Timer2 UART1 All Rights Reserved Copyright per DIN 34 SMCS11 6SpW Doc No SMOS ASTD UM 1 16 EADS brni User Manual p 16 06 2008 Interface Example Mode Type 1 2 3 UART2 GPIOO GPIO7 0 GPIO7 0 GPIO1 IOB7 0 IOB7 0 FIFO active mode passive mode RAM ADC DAC Note that if the passive FIFO mode is used on the SMCS116SpW the ADC and DAC interfaces can then not be used JTAG interface For testing purposes a standard IEEE 1149 1 interface is provided It supports the JTAG functions Bypass Extest Sample Preload All Tristate and IDCode All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS so User Manual Date 16 06 2008 aseritum Page 16 of 157 4 The SpaceWire link and protocols The SpaceWire DS Link standard defines a full duplex bit serial point to point link with a raw transmit rate of up to 400 Mbit sec The link consists of 2 signals in each direction one for strobe and one for data By coding the strobe that it only
117. t both ends are stopped Each end can then be restarted All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS rent User Manual Date 16 06 2008 Page 20 of 157 5 The SMCS116SpW Protocols The SMCS116SpW supports both the standard SpaceWire link protocol transparent mode as well as the header generation required for the enhanced transaction layer of the SMCS116SpW This protocol uses specific protocol headers that can be generated by the SMCS116SpW without requiring an external host controller These headers are stored in specific header registers which allows headers with a length of 0 equalling the transparent mode to eight bytes per packet Packetization of data sent by the SMCS116SpW over the link is also done automatically according to the settings of a packet length register Another feature provided by the transaction layer supported by the SMCS116SpW is an automatic checksum generation on the link This is generated and checked automatically by the SMCS116SpW without requiring support from a host or other external source Errors on the link are flagged and a special error packet is sent over the link to signal the error condition Programming the SMCS116SpW internal registers is done via the SpaceWire link All internal registers are 8 bit wide addressable Two simple commands read and write suffice to access all functions and registers of the SM
118. th ram Luzern essen FIFO FULL setup before WR high wes parity valid IOB15 RCV PAR a IOB16 IOB17 high after last write and WR high tFWEOP E ERE RCV EOP ACK active high pulse width rosen DATAO 15 EOPL EOPH enable after WR low rage RCV_PAR DATAO 15 EOPL EOPH valid before tFWDV WE high DATAO 15 EOPL EOPH hold after WR high mM Notes 1 ws wait states 0 o 2 depends on the data bandwidth over the SpaceWire link All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 128 of 157 12 13 FIFO interface read IOB18 RD NS IOB19 WR IOB20 FIFO EMPTY IOB24 TRMEOP IOB25 TRMEEP IOB14 TRM EOP ACK teREOPA pd FREOPH teRackH is teRDH Parity y valid valid Description Symbol Min 5 V leri 3 3 V 3 3 V RD active low pulse width em LN UE 41 ws 40 83 ws 80 m FIFO FIFO_EMPTY setup before RD hih setup before RD FIFO_EMPTY setup before RD high tFES EIL TRM EOP ACK active high after TRMEOP tFREOPA 83 high AND FIFO EMPTY active low IOB27 TRM PAR DATAO 15 IOB24 IOB25 hold after TRM EOP ACK tFREOPH high TRM EOP ACKholdafterTRMEOP low TRM EOP ACKholdafterTRMEOP low ACK hold after TRMEOP low HFRACKH a NEN TRM PAR DATAO 15 EOP
119. timer interrupts The number of cycles between interrupts is TPERIOD 1 The maximum value of TPERIOD is 2 exp 32 1 so if the timer_clock cycle is 80 160 ns using an internal clock of 12 5 6 25 MHz 5 3 3V the maximum interval between interrupts is 343 6 687 2 seconds Configured in single shot mode If the timer is configured in single shot mode bit 2 of TCONFIG is set the TMR_EXP output remains low until the timer is stopped or mode is changed To generate another single shot the timer must be first stopped bit O of TCTRL register is cleared before the timer can be started again All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS User Manual Date 16 06 2008 aescCrmium Page 103 of 157 9 10 GPIO Interface A GPIO interface is formed by three registers and 8 external signals The three registers are GPIO_DIR The direction register GPIO_DOUT The data out register GPIO_DIN The data in register The direction register GPIO_DIR defines for each pin if it functions as input or as output After reset all pins are configured as inputs Data written to the data out register GPIO_DOUT is forwarded to these GPIO pins which are configured as outputs Reading the data in register GPIO_DIN shows the values carried on the external signals if the corresponding GPIO pin is configured as input Otherwise if configured as output the v
120. tself D1 start the link auto reset Start the transmission of NULL characters D7 D2 reserved 0x09 STATUS link status register r DO link is running D1 disconnect error will raise an interrupt D2 parity error will raise an interrupt D3 null characters are being received D4 FCTs have been received D5 ESC error D6 FCT error D7 reserved Ox0A LINKTEST link test register only accessible when bit D7 of r w register MODE 0x07 is set DO enable internal feedback of transmit link to receive link data will also be transmitted externally D1 disable disconnect error D2 input mute D3 insert wrong parity if set inverts the transmitted parity and so invokes a parity error at the other end D4 link output mute D5 send EEP instead of EOP D7 D6 reserved Note The auto start signal is internal always set This means that it is not possible to disable the SpaceWire cell See AD1 Differences between the SMCS116 and the SMCS116SpW for the bits DO D3 and D4 When DO D3 and D4 are set the SpaceWire link is was in the Run state See AD1 All Rights Reserved Copyright per DIN 34 EADS ada eeabri rnm SMCS116SpW User Manual Astrium GmbH Doc No Rev 1 2 Date Page 16 06 2008 55 of 157 SMCS ASTD UM 116 On an Space Wire link error i e disconnect parity these bits will be cleared However if the running link
121. two main different application areas 1 Embedded systems 2 Communication device for processor systems Embedded Systems The main application targets of the SMCS116SpW are modules and units without any built in communication features such as special image compression chips application specific programmable logic or mass memory The SMCS116SpW is perfectly suited to be used on non intelligent modules such as A D converter or sensor interfaces due to its control by link feature and system control facilities In addition its fault tolerance feature makes the device very interesting for many critical industrial measurement and control systems Example applications of the SMCS116SpW as communication and system controller on an interface node consisting of an ADC and DAC and one where the SMCS116SpW is connected to four banks of memory are given in the figures below IOB10 DAC WR 10B11 13 DAC_ADDR Data 15 0 SpaceWire SMCS116SpW IOBO 7 ADC SEL All Rights Reserved Copyright per DIN 34 Astrium GmbH Bi SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS Ke geg wd User Manual Date 16 06 2008 Page 30 of 157 CS3 PD DATA 15 0 mummmumuuumm gt 16 a SpaceWire SMCS116SpW CS1 CTRL BUS V ores 16 4 64k 16 All Rights Reserved Copyright per DIN 34 Astrium GmbH r SMCS11 6SpW Doc No SMCS_ASTD_UM_116
122. undary scan logic Test Data Output Serial scan output of the boundary scan path All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS weg User Manual Date 16 06 2008 aescCrmium Page 108 of 157 Ww mm pou SMCS116SpW Reset Sets the SMCS116SpW to a known state This input must be asserted low at power up The minimum width of RESET low is 2 cycles when CLK is running External clock input to SMCS116SpW max 5 MHz PLLOUT Output of internal PLL Used to connect a network of external RC devices See chapter11 1 VCC 3VOLT PLL Control signal enable 3 3 Volt mode VCC 5 Volt connect this signal with GND VCC 3 3 Volt connect this signal with VCC e rose ae po ews SYS Notes 1 10B21 0 6 mA IOB24 22 3mA IOB26 25 input only IOB27 3 mA All inputs have an internal pull up resistor with the following exceptions which have an internal pull down resistor LDI LSI TRST TMS All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS11 6SpW Doc No SMCS_ASTD_UM_116 Rev 1 2 EADS weg User Manual Date 16 06 2008 asSsCrmium Page 109 of 157 10 1 IOB control bus The allocation of the I O busses is shown in the table below Function RAM Interface l O ADC DAC FIFO Interface I O l O eruere Ile o newer ro kw bam oes ei 1 bm baren owene e ber pmrwome opere jor perwem
123. up and pulse width timing D7 D4 reserved 9 7 4 DAC Timing Requirements If a DA converter requires a minimum pulse width or a minimum setup or both bit 3 0 of register DAC CTRL1 0x29 can be used to fulfil these requirements If the values for min pulse width and min setup are different the longer value has to be taken because there is only one counter to generate both timings The minimum pulse of DAC_WR is one clock cycle The minimum setup of DAC ADDR and DATA before falling edge of DAC WR is one clock cycle To generate extended timings the wait state register can be loaded with any value between 0x1 and OxF For example a value of 2 generates a minimum setup and minimum pulse of 120 ns formula 1 2 x 40 ns 120 ns The maximum setup and pulse width which can be generated is 640 ns The hold time after rising edge of DAC WR is one clock cycle All Rights Reserved Copyright per DIN 34 Astrium GmbH L SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS Kagepe User Manual Date 16 06 2008 Page 93 of 157 DAC_CTRL1 IOB10 DAC WR DAC CTRL IOB11 13 DAC ADDRO 2 DATAO 15 9 7 5 Sequence for Digital Analogue conversion Enable DAC I F 1 write 0x98 to register ENABLE 0x00 2 set bit D3 1 and DO 0 in register IFCONF 0x01 xxxx 1xx0 Configure DAC I F 3 write 0x01 to register DAC CTRL1 0x29 o 80ns min setup and pulse width Write DAC data to DAC I F 4 wr
124. v 1 2 EADS rent User Manual Date 16 06 2008 Page 90 of 157 Stop AD conversion Stops automatically Starting next scan channel 3 14 Enable ADC I F 1 write 0x98 to register ENABLE 0x00 2 set bits D2 1 and DO 0 in register IFCONF 0x01 xxxx x1x0 Configure ADC I F 3 write 0x40 to register ADC_CTRLO 0x21 o send port address mux address EOP 16 Bit o enable mux address generation Load number of first channel 4 write 0x03 to register ADC_STR 0x1D Load number of last channel 5 write OxOE to register ADC END 0x1E Configure ADC HE 6 write 0x36 to register ADC_CTRL1 0x22 o 280 ns setup and pulse width o Start conversion if bit of ADC CTRL2 0x23 is set o conversion ready terminated by on chip timer1 Start AD conversion 7 write 0x01 to register ADC CTRL2 0x23 After the AD conversion is completed one packet will be directly transmitted and the mux address will be incremented After all packets have been received AD conversion can be stopped by stopping timer2 Stop AD conversion 8 AD conversion can be stopped by stopping timer2 All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS so User Manual Date 16 06 2008 aescCrmium Page 91 of 157 9 7 DAC Interface SMCS116SpW SpaceWire ee IOB10 DAC WR 10B11 13 DAC_ADDRO 2 9 7 1 DAC interface enable The DAC interface is enabled with
125. wn m m e e EECHER EREECHEN HWRnRD hold after HSEL inactive high tHWnRH Py OR oe HDATNADR hold after HSEL inactive high AHDNAH E MN NN NN HDATA enable after HSEL active low and tHDE HWRnRD low HDATA valid after HSEL active low and tHDV HWRnRD low HDATA hold after HSEL inactive high HDH SSE All Rights Reserved Copyright per DIN 34 Astrium GmbH SMCS1 1 6SpW Doc No SMCS ASTD UM 116 Rev 1 2 EADS rent User Manual Date 16 06 2008 Page 121 of 157 12 7 RAM interface write trw A EH Loun IOB18 CSO IOB19 CS1 IOB20 CS2 IOB21 CS3 IOB16 WR IOB17 RD trwas trwaH Moser d addr valid addr valid trwov Toun cata vdid B RWDE T Description Symbol Min in 5 V 5 m 3 3 V RAM I F write access time tRWA uu 120 ws 40 TM 80 CS0 3 WR active low pulse width tRWL ul 41 ws 40 Kl 0 DATAO 15 Address ADDRO 15 valid before CSO WR active tRWAS low Address ADDRO 15 hold after CS0 3 WR perre inactive high eap p k DATAO 15 valid before CS0 3 WR inactive high Geh E EC DATAO 15 hold after CSO 3 WR inactive high won n fa Iw Im fs Note ws wait states 0 7 All Rights Reserved Copyright per DIN 34 SMCS116SpW EADS User Manual aseritum Astrium GmbH Doc No SMCS_ASTD_UM_116 Rev 1 2 Date 16 06 2008 Page 122 of 157 12 8 RAM interface read

5.1 Programming the SMCS116SpW

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