aes220 High-Speed USB FPGA User Manual
Contents
1. 14 2 7 4 Pipeln receiving dla o ie 15 2 7 3 WE OC Writing A ee 17 SIS ne 21 3 1 LEDand STU WG RECENTE TTE 21 ee Be E EE T EREE E E E 22 SP M Connectors PO ep 23 3 5 Stack PME MICI m 25 4 Chararteristies a2 26 4 1 FPGA Power DESsipanon ss 26 4 1 1 FPGA Thermal Character ae 26 4 1 2 FPGA Power Lim T 26 4 2 INE ID CMT 29 TIES5ENT www aessent com technology Doc Nb UM220 01 A aes220 UserManual V1 4 1 Illustration Index Fig re 1 Mod le Top Yves 5 Figure 2 Daughter Boards Stack Up seen 5 PRUE 3 8885220 Block DEE a een 7 Figure 4 FX2 Interface and Pipes Block Diagram eeeeeeeee esee eene eene enne hnn neenon neta 11 Figure 5 User A pic AIM een 12 Figure 6 User Application and Test Bench ass 12 Figure 7 Reading from qui T S 15 Figure 8 Writing 198 DIPE sec toneis eiie seirinin neneeese ie RES EES eias Os ILI E 18 Figure 9 Writing to a pipe and pausing Retna 18 Figure 10 LED and Switches schematisch ne 21 Fig re TI Connector PI Mapping ondes adio vip a EH ege deatur siae pd eb RE xr d 23 Figure 12 Connector P2 Mapp Me ee 24 Figure 13 Daughter Boards Starke Up oscuras doge Sb UN trn E EH eS d wave ue n REDE SANDER pRU dS 25 Figure 14 Max Recommended Power odisse dud evdisa ts px be vd Peli estu asume E ni uM RE CRANE CR RR 27 Figure 15 Ab2. gt pi3 s P ADDR in gt 0000011 PAUSE in gt pauseP3 s READ RO out gt pipe3Rd s DATA out pipe3Data s Table 3 describes the various parameters of the instantiation Page 15 of 29 TIES5ENT www aessent com technology Doc Nb UM220 01 A aes220 UserManual V1 4 1 Instantiation Parameters Parameters Description Pipe 3 Data aes220 PipeIn ent Pipe 3 Data is an instance of the aes 220 Pipeln ent component IP in gt ip S ip s is the signal linking IP in port of the pipe to the IP out port of the interface ip s is declared in the 8es220 Package vhd file and hence does not need to be declared in the user application PI out gt pi3 s pi3 s is the signal linking the Pl out port of the pipe to the PI in port of the interface via a logical OR If only one pipe is used then pi s which is declared in the aes220_Package vhd file can be used instead Otherwise pi3 s need to be declared in the user application 10 bits wide signal P ADDR in gt 0000011 Used to set Pipe 3 address address 3 chosen arbitrarily as an example PAUSE in pauseP3 s The application can use the pauseP3 s signal to pause the transfer on Pipe 3 Tie up PAUSE in input to 0 if unused Note that pausing the transfer cannot go on forever as it will eventually time out the USB communication with the PC The time out is currently set to 5s READ RQ out gt pipe3Rd s pipe3Rd s is the
3. V1 4 1 Instantiation Parameters Parameters Description Pipe 4 Data aes220 PipeOut ent Pipe 4 Data is an instance of the aes 220 PipeOut ent component IP in gt ip S ip s is the signal linking IP in port of the pipe to the IP out port of the interface ip s is declared in the aes220_Package vhd file PI out gt pi4 s pi4 s is the signal linking the PI out port of the pipe to the PI in port of the interface via a logical OR if more than one pipe is used If only one pipe is used then pi s which is declared in the aes220 Package vhd file can be used instead Otherwise pi4 s need to be declared in the user application 10 bits wide signal P ADDR in gt 0000100 Pipe 4 Data address address 4 chosen arbitrarily PAUSE in gt pauseP4 s The application can use the pauseP4 s signal to pause the transfer on Pipe 4 Tie up PAUSE in input to 0 if unused Note that pausing the transfer cannot go on forever as it will eventually time out the USB communication with the PC The time out is currently set to 5s WRITE RQ out gt pipe4Wrs pipe4Wr s is the signal warning the rest of the application that Pipe 4 Data is expecting data on its data bus DATA in pipe4Data s Pipe 4 Data data bus 8 bits wide Table 4 aes220 PipeOut Parameters The entity declaration for aes220 PipeOut is as follow entity aes220 PipeOut ent is end aes220 PipeOut ent P
4. programmed as it can be used directly with already loaded firmware However it is worth keeping an eye for new versions of the firmware published on the website www aessent com When programming the micro controller it is possible to either overwrite the program present in the RAM of device or in the EEPROM If loaded into the RAM the program will revert to the original firmware or whatever firmware is present at that time in the EEPROM on a reset or power cycle If loaded into the EEPROM the program become permanent Note that if the program loaded in the EEPROM is faulty or does not set the USB communication properly then there is the possibility to brick the device That is the device looses USB communication and hence cannot be reprogrammed However there is a simple solution to this which is to remove the cap on jumper one and reset or power cycle the device See the chapter on recovering from a wrongly programmed EEPROM in the installation manual pertaining to your operating system Most Xilinx FPGA do not have intrinsic memory and need to be configured on or after power up The device used on the aes220 however incorporates some Flash memory that can be programmed with the FPGA configuration file At power on the FPGA will automatically fetch this configuration file from the memory and Page 9 of 29 RESSENT www aessent com Doc Nb UM220 01 A aes220 UserManual V1 4 1 boot up from it There is no particular requirement from the con
5. signal warning the rest of the application that Pipe 3 Data is providing data on its data bus DATA out gt pipe3Data s Pipe 3 Data data bus 8 bits wide Table 3 aes220 PipelIn Parameters The entity declaration for aes220 Pipeln is as follow entity aes220 PipeIn ent is PAUSE in in std logic end aes220 PipeIn ent Port Connections to the FX2 interface IP_in in std logic vector 18 downto 0 PI out out std logic vector 9 downto 0 User application connections P ADDR in in std logic vector 6 downto 0 The pipe address READ RQ out out std logic DATA out out std logic vector 7 downto 0 data to user app set by user app Pause input for pausing transfer Data available flag to user app NESSENT www aessent com Page 16 of 29 Doc Nb UM220 01 A aes220 UserManual V1 4 1 During simulation the data can be sent to the pipe using the function pipe out provided in the aes220_SimulationPackage vhd pipe out outChannel3 v dataSize v dataOut ar rst s fi s if s ifData s Where the signals on the bottom row are linking the function to the interface and are declared in the simulation package There is no need to change these The other three parameters in the function are in order The pipe address outChannel3_v The number of bytes to be sent dataSize v The data pre arranged in a byte array dataOut ar Note that the types byt
6. 29 TIESS5SENT www aessent com h Doc Nb UM220 01 A aes220 UserManual V1 4 1 2 3Start Up and Shut Down The module powers up automatically when any of the power supply is present No special step is required The micro controller will wake up first and only then allow the FPGA to configure from its internal flash if programmed Shutting down the module is a matter of cutting off the power supplies to it 2 4Reset There are two ways of resetting the module via a USB command or by pressing the reset switch on the board See the API documentation on how to perform an USB reset The reset whether software via USB or hardware via the reset switch resets the micro controller which in turns resets the FPGA 2 5Sleep Mode Both the micro controller and FPGA can be put into low power mode independently of each other The micro controller commands the SUSPEND pin of the FPGA An API function is used to send the relevant command to the micro controller Note however that to wake up the micro controller the W UP pin on the board has to be pulled low as USB communication is lost when the micro controller is in low power mode 2 6 Programming the FPGA and Micro controller Programming both the FPGA and the micro controller of the aes220 has been made very simple thanks to the aes220 Programmer It is a GUI based software that makes use of the functions present in the API to program both circuits The micro controller does not require to be
7. 7 28 29 30 31 32 BankF 33 34 N A 35 36 37 38 39 40 41 42 43 44 45 46 47 48 GND N A Differential pairs Connectors are standard 0 1 through hole footprint Figure 11 Connector P1 Mapping nt com technology www aessent co Funct mu BankD GCLK4 BankE GCLK10 BankF GCLK6 GCLK8 Page 23 of 29 Doc Nb UM220 01 A BankA BankB BankC Figure 12 Connector P2 Mapping Funct FPGA pin N A LHCLK7 LHCLK3 LHCLK5 N A LHCLK1 N A GND Connector P2 legend Connector pin legend 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Connectors are standard 0 1 through hole footprint aes220 UserManual V1 4 1 FPGA pin N A N A N A N A Funct uu BankA LHCLK6 BankB LHCLK2 LHCLK4 BankC To facilitate the use of the banks a constraint file aes220 Revxx Banks ucf for the ISE environment provided on the website www aessent com technology www aessent com Page 24 of 29 Doc Nb UM220 01 A 3 5Stack up format aes220 UserManual V1 4 1 The module can be stacked up with other boards modules very easily thanks to its versatile pin arrangement In addition to the 72 GPIO present on the connectors six 3 3Vpins six Vin pins and twe
8. 7 of 29 Doc Nb UM220 01 A Junction to ambient thermal resistance C W Still air 250LFM 500LFM 750LFM 29 23 8 23 22 3 a Absolute Max Power W 20 3 62 4 41 4 57 4 71 25 3 45 4 20 4 35 4 48 30 3 28 3 99 4 13 4 26 35 3 10 3 78 3 91 4 04 40 2 93 3 57 3 70 3 81 45 2 76 3 36 3 48 3 59 50 2 59 3 15 3 26 3 36 55 2 41 2 94 3 04 3 14 60 2 24 2 73 2 83 2 91 65 2 07 2 52 2 61 2 69 70 1 90 2 31 2 39 2 47 75 1 72 2 10 2 17 2 24 80 1 55 1 89 1 96 2 02 85 1 38 1 68 1 74 1 79 90 1 21 1 47 1 52 1 57 95 1 03 1 26 1 30 1 35 100 0 86 1 05 1 09 1 12 105 0 69 0 84 0 87 0 90 110 0 52 0 63 0 65 0 67 115 0 34 0 42 0 43 0 45 120 0 17 0 21 0 22 0 22 125 0 00 0 00 0 00 0 00 Table 7 Absolute Maximum Power Absolute Max Power 5 00 4 50 4 00 3 50 3 00 2 50 2 00 1 50 1 00 0 50 0 00 Power W mm Stil air mm 250LFM 500LFM mm 750LFM 30 50 70 90 110 20 40 60 80 100 120 Ambient Temperature C Figure 15 Absolute Maximum Power technology www aessent com aes220 UserManual V1 4 1 Page 28 of 29 Doc Nb UM220 01 A aes220 UserManual V1 4 1 4 2 Board Dimensions 43 180 mm Figure 16 aes220 Board Dimensions Page 29 of 29 TIES5ENT www aessent com tarhbenin technology Doc Nb UM220 01 A
9. FPGA Global Clocks Buffers GCLK The 36 GPIO on connector P1 including the clocks can be used single ended or as 18 differential pairs The two 48 pin 0 1 pitch through hole connectors footprints on either side of the module allow for it to be stacked up either on top bottom or both sides BESSENT technology 3 92 a ds P3 OOOQOQO s M OO ro SOS www aessent com uj 61mm To add to the flexible GPIO Figure 1 Module Top View scheme power and grounds pins are spread symmetrically among the two main connectors This feature allows for modules a third of its size to be directly interfaced to the aes220 Each slot hence connecting to power supply pins and interfacing with 24 GPIO 4 of which usable as clock signals to the FPGA 19 8mm Figure 2 Daughter Boards Stack Up Page 5 of 29 TIES5ENT www aessent com technology Doc Nb UM220 01 A aes220 UserManual V1 4 1 The module offers a flexible clock implementation with the micro controller clock connected to the FPGA and 16 GCLK inputs present on the external connectors allowing for multiple clock inputs for a 10MHz external reference for example but also for running buses or serial links requiring an external clock The FPGA possesses four Digital Frequency Synthesiser DFS to multiply any clock provided up to 334MHz Thanks to the FPGA 4Mb of internal Flash memory no external device is required for the FPGA to keep its configuration o
10. T ates A DIR Doc Nb UM220 01 A aes220 UserManual V1 4 1 2 7 2 FX2 Interface The micro controller deals with all the USB communications and offers a simplified FIFO interface directly connected to the FPGA The FX2 Interface joins this interface to the various pipes used in the application Only one FX2 Interface should be instantiated in the application and all pipes linked to it The FX2 interface should be instantiated and mapped as follow fx2 Interface aes220 FX2 Interface ent port map RST in gt RST in ifCLK out gt ifClk s User app FI in gt FI in IF out gt IF out FI io gt FI io PI in gt pi s IP out gt ip Ss Table 3 describes the various parameters of the instantiation Page 13 of 29 NESSENT www aessent com echnology Doc Nb UM220 01 A aes220 UserManual V1 4 1 Instantiation Parameters Parameters Description fx2 interface fxX2 interface is an instance of the aes 220 FX2 Interface ent aes220 FX2 Interface ent component the only one FX2 Interface to be instantiated RST in RST in Reset signal coming from the micro controller or the host PC Mapped straight to the top level port of the application The port is defined in the aes220 RevA1 FX2 Interface ucf constraint file IFCLK out gt ifclk s The 48MHz clock coming from the micro controller and transiting via the FX2 Interface This is the clock signal to use with the rest of the application when dea
11. aes220 User Manual High Speed USB FPGA Mini Module Aessent Technology Ltd Module ini Speed USB FPGA Mi igh aes220 H User Manual Version 1 4 1 Mini Module Series Doc Nb UM220 01 A www aessent com User Manual aes220 UserManual V1 4 1 Change History Version Changes Author V1 2 Original Version S bastien Saury V14 Update pipes interface introduction of PAUSE iin input S bastien Saury V1 41 Added note to clarify pipe direction convention and diagram of test bench S bastien Saury overview AESSENT Yolog www aessent com Doc Nb UM220 01 A aes220 UserManual V1 4 1 Table of Contents S uil P 5 UN WEE euro SR 5 1 2 Block Diane 7 2 Operati On TT 8 2 1 Not WEIT ee UU ee 8 2 2 Power SU PUGS T 8 2 3 Start Up and SEP DIOWEL ne en 9 2A Bl e 9 2 5 Sleep Mole ek E EEE AAS RE E EPERE SRS 9 2 6 Programming the FPGA and Miao tonfroller aan 9 2 7 Communicating with the Pe een 10 LANES uu P aie 10 272 Sea TEC 13 2 7 3 Logical OR n
12. e EEPROM storing the micro controller program and the on board DC DC converter are connected to the bus Their addresses are EEPROM I2C address 0x51 DC DC converter I2C address 0x60 These addresses should not be used by any other peripherals connecting to the bus Page 22 of 29 NESSENT www aessent com echnology Doc Nb UM220 01 A aes220 UserManual V1 4 1 3 4 Connectors pin out The main user connectors are standard two rows 48 pin 0 1 pitch connectors Connections to the FPGA have been arranged in six banks of 12 GPIO each including at least two GCLK inputs They are not to be confused with the FPGA own banks All the banks on connector P1 belong to the same FPGA bank bank 3 and all the banks on connector P2 belong to FPGA bank0 The banking arrangement on both connectors is only a naming convention to facilitate board stack up see paragraph 3 5 Stack up format and does not prevent from using all the banks on one connector as one Connector P1 Funct FPGA pin legend Connector pin legend FPGA pin BankD N A GND 1 2 N A IO LOIN O BankD1 3 4 BankDO IO LO1P O IO LO3N O BankD3 5 6 BankD2 IO LOS3P O IO LO2N O BankD5 7 8 BankD4 lO LO2P 0 IO LOAN O BankD7 9 10 BankD6 IO_LO4P_O IO_LO6N_O BankD9 11 12 BankD8 IO LO6P 0 GCLK5 1O LO9N O BankD11 13 14 BankD10 IO LO9P 0 N A 15 16 GND N A BankE N A GND 17 18 N A O5N_C k 19 20 21 22 23 24 25 26 2
13. e and byte array are also declared in the simulation package as subtype byte is std logic vector 7 downto 0 type byte array is array natural range lt gt of byte Note although it is the Pipeln component of the FPGA described here it is linked to the simulation function pipe out as this function emulates the function used on the host PC to send data to the FPGA Note please have look at the aes220 Loopback Example for a demonstration on how all these elements interact with each other 2 7 5 PipeOut Writing data The host PC initiates a write event by asserting the WRITE RQ signal for write required on the addressed pipe The FPGA user application must start providing the data on the DATA in bus on the following clock edge Once the data has been provided the pipe releases the WRITE RQ signal If the application is providing more data than the FIFO can hold 2048 bytes the pipe will de assert the WRITE RQ signal When this signal is de asserted the application must stop providing data until the signal is re asserted Figure 8 shows an example of a writing to a pipe and pausing while the WRITE signal is de asserted The transfer can also be paused from the user application side using the PAUSE in input of the pipe The application will still have to provide one more data when asserting the pause signal Like for the WRITE RQ signal the application will have to provide the data following a de assert
14. e signals from the different pipes to the interface pi s pil s or pi2 s or pi3 s or pi4 s Where pi s is linked directly to the port PI in of the FX2 Interface instance while pit s to pi4 s are linked each to a separate pipe on port PI out Note that pi1 s to pi4 s have to be declared in the user application Page 14 of 29 TIESS5SENT www aessent com h Doc Nb UM220 01 A aes220 UserManual V1 4 1 Note Unless there is only one pipe in the whole user application in which case pi s can be used directly without a logical OR there should be one piX s signal per pipe 2 74 Pipeln receiving data On the user application side of the FPGA incoming data is signalled on each pipe by the assertion of the READ RQ signal for read required When this signal is asserted the user application must immediately start reading the data synchronously with the provided interface clock IFCLK on the DATA bus until the READ RQ signal is de asserted However the user application can pause the transfer at any time by asserting the PAUSE signal at any time including before the transfer has started See Figure 7 for a graphical example IFCLK READ RQ e Pipe 4 Application AD3 XD4 Figure 7 Reading from a pipe A Pipeln is instantiated using the following declaration using an instance called Pipe 3 Data as an example Pipe 3 Data aes220 PipeIn ent port map IP in gt ip s PI out
15. e simulation functions provided to write test benches although written in vhdl Page 10 of 29 AESSENT www aessent com h Doc Nb UM220 01 A aes220 UserManual V1 4 1 and used in the ISE environment are emulating the PC side of the chain and hence adhere to the PC convention in is FPGA PC out is PC FPGA See below To simplify the simulation two functions Pipeln and PipeOut are available in the Simulation package provided The user application can hence be developed and simulated using the signals coming in and out of the pipes and does not have to contend with the handling of the FX2 micro controller FIFOs See Figures 4 5 and 6 fora graphical overview of the different modules RST in IFCLK l l l i l l FI in H IF out FI io l l l l i l l READ_RQ l PAUSE l DATA l l l i READ_RQ PAUSE i DATA l l i i WRITE_RQ PAUSE DATA I FX2 FPGA FPGA I Connections Interface Application I Figure 4 FX2 Interface and Pipes Block Diagram Page 11 of 29 www aessent com technology Doc Nb UM220 01 A aes220 UserManual V1 4 1 BANKB BANKC Switches BANKE Figure 5 User Application I O Banks BANKA BANKB BANKC 4 4 4 Test Bench USB a Comms Ro M M Y Y Y e w o ANKE we I O Banks Figure 6 User Application and Test Bench Page 12 of 29 technology MN
16. figuration file in order to achieve this The boot up process is handled by the micro controller It is not a requirement to program the Flash memory The device can also be configured and simply run from this configuration until it is powered off or reset at which point the configuration will be lost 2 7 Communicating with the PC Communicating between a FPGA and a PC via a USB link can be a tricky matter However thanks to the API and VHDL interface provided it needs not be The micro controller which handles the whole USB communication channel is programmed in such a way as to create a simple yet versatile interface between the FPGA and the PC No in depth knowledge of USB communication is required to transfer data back and forth between the two The interface allows high speed data channels between the PC and the FPGA as well as six user general purpose pins which can be used for example as control or status pins for the user application if required 2 7 1 Overview A USB communication channel is usually called a pipe On the PC side sending data out from the PC to the FPGA will be done using the function pipe_Out and receiving data from the FPGA will be done via the function pipe_In The exact syntax for both functions is described in the API documentation but each function requires a buffer of 8 bit unsigned integers the size of the buffer and a pipe address Note in a USB communication the host is the PC and is the master There is
17. ich the recommended max junction temperature is 100C while its max temperature is 125C This gives a maximum power dissipation of Pmax Tj Ta Rja In still air at 25 C Pmax recommended 100 25 29 2 75W Pmax absolute 125 25 29 3 3W Note that these figures do not take into account the heat dispersion through the PCB itself so in practice the power dissipation figures should be slightly better Page 26 of 29 TIE5S5ENT www aessent com hnolos Doc Nb UM220 01 A Junction to ambient thermal resistance C W Still air 250LFM 500LFM 750LFM 29 23 8 23 22 3 Ambient Temp C Max Recommended Power W 20 2 76 3 36 3 48 3 59 25 2 59 3 15 3 26 3 36 30 2 41 2 94 3 04 3 14 35 2 24 2 73 2 83 2 91 40 2 07 2 52 2 61 2 69 45 1 90 2 31 2 39 2 47 50 1 72 2 10 2 17 2 24 55 1 55 1 89 1 96 2 02 60 1 38 1 68 1 74 1 79 65 1 21 1 47 1 52 1 57 70 1 03 1 26 1 30 1 35 75 0 86 1 05 1 09 1 12 80 0 69 0 84 0 87 0 90 85 0 52 0 63 0 65 0 67 90 0 34 0 42 0 43 0 45 95 0 17 0 21 0 22 0 22 100 0 00 0 00 0 00 0 00 Table 6 Max Recommenced Power Max Recommended Power 4 00 3 50 3 00 2 50 2 00 1 50 1 00 0 50 0 00 Power W mm Stil air mmm 250L FM 500LFM mm 750LFM 25 35 45 55 65 75 85 95 20 30 40 50 60 70 80 90100 Ambient Temperature C Figure 14 Max Recommended Power www aessent com aes220 UserManual V1 4 1 Page 2
18. ion of the pause signal on the following clock edge The pause signal can be asserted before receiving a WRITE RQ signal giving the application time to provide the data if not readily available See figure 9 for a graphical example of the use of the PAUSE iin input Page 17 of 29 NESSENT www aessent com h Doc Nb UM220 01 A aes220 UserManual V1 4 1 IFCLK m a WRITE_RQ FIN DATA in LL DOX DiX D2 ECC Figure 8 Writing to a pipe Note the FX2 micro controller is using a quad buffered FIFO What it means is that the FIFO is constituted of four 512 bytes FIFO When one fills up its contents are automatically sent to the host while the user data is being switched to the second FIFO and so on If the first FIFO hasn t been emptied by the time the last FIFO is full the WRITE RQ signal will be de asserted until the first FIFO becomes available again IFCLK WRITE RQ DATA n L x91 or esos Figure 9 Writing to a pipe and pausing the transfer A PipeOut is instantiated using the following declaration using an instance called Pipe 4 Data as an example Pipe 4 Data aes220 PipeOut ent port map IP in gt ip s PI out gt pi4 s P ADDR in gt 0000100 PAUSE in gt pauseP4 s WRITE RQ out gt pipe4Wr Ss DATA in pipe4Data s Table 4 describes the various parameters of the instantiation Page 18 of 29 technology WIDE RESSCREGOIR Doc Nb UM220 01 A aes220 UserManual
19. ling with the pipes FI in FI in Signal bus going from the FX2 to the FX2 Interface Mapped straight to the top level port of the application The port is defined in the aes220 RevA1 FX2 Interface ucf constraint file IF out IF out Signal bus going from the FX2 Interface to the FX2 Mapped straight to the top level port of the application The port is defined in the aes220 RevA1 FX2 Interface ucf constraint file FI io gt FI io Bi directional signal bus between the FX2 and the FX2 Interface Mapped straight to the top level port of the application The port is defined in the aes220 RevA1 FX2 Interface ucf constraint file IP out gt ip s ip s is the signal linking IP in port of the pipes to the IP out port of the interface ip s is declared in the aes220 Package vhd file ip s is declared in the aes220 Package vhd file PI in pi s pi s is the signal linking the Pl out port of the pipes to the PI in port of the interface If more than one pipe is used it is the signal coming out of a logical OR between the similar signals coming out of the pipes pi s is declared in the aes220 Package vhd file Table 2 aes220 FX2 Interface Parameters 2 7 3 Logical OR When more than one pipe is used the signals from the pipes to the FX2 Interface need to be tied together using a logical OR before being fed to the interface This is done very simply as shown in the following example Logical OR all th
20. lve ground pins are also provided at regular intervals All these pins are grouped into banks allowing an easy division of the board across the way into three smaller sections each able to accept a different daughter board Each sub section is therefore provided with 24 GPIO of which at least four can be used as clock inputs two Vin pins two 3 3V pins and four ground pins S SES 4 x HT C Figure 13 Daughter Boards Stack Up Note also that the power and ground pins as well as the clock inputs are symmetrical with regard to the centre of the board or sub sections This allows for a daughter board to be plug in either direction without damaging the modules nt com technology WWW aessent co Page 25 of 29 Doc Nb UM220 01 A aes220 UserManual V1 4 1 4 Characteristics 4 1 FPGA Power Dissipation 4 1 1 FPGA Thermal Characteristics The following values are for the FTG256 XC3S200AN package From Xilinx DS557 document Thermal resistances Value Unit Junction to case 7 4 C Watt Junction to board 23 3 C Watt Junction to ambient still air 29 0 C Watt Junction to ambient 250LFM 23 8 C Watt Junction to ambient 500LFM 23 0 C Watt Junction to ambient 750LFM 22 3 CNWatt Table 5 FPGA Thermal Characteristics LFM air velocity in Linear Feet per Minute 4 1 2 FPGA Power Limits The aes220 is fitted with the industrial grade package option for wh
21. m hnolog Doc Nb UM220 01 A aes220 UserManual V1 4 1 1 2Block Diagram Connector 1 banks A to C 36 GPIOs V x4 User Spec JTAG 36 GPIOs or 18 Diff Pairs v E x1 Done Pin User Specifics Connector 2 banks D to F ge 22 GPIOs GPIF signals uC reset Figure 3 aes220 Block Diagram Page 7 of 29 www aessent com technology Doc Nb UM220 01 A aes220 UserManual V1 4 1 2 Operation 2 1 Note to the user The operation described in this chapter are for the software firmware and VHDL code provided with the module As these are open source and freely modifiable by the user some part of this manual could stop being relevant and the onus would be on the user to document its own work The code and compiled modules required to set the module in its original condition are available on the website at www aessent com 2 2Power Supplies The module can be powered up directly from the USB power supply or from an external 4 5 to 5 5V supply provided via one or more of the six Vin pins available on the two main connectors P1 and P2 The two power supply paths i e USB and external supply paths can be swapped from one to the other without disrupting the functioning of the module When an external supply is detected the supply from the USB port is turned off By specification a USB 2 0 host can provide up to 500mA of current 1A if using a double connector cable As depending on the application a mod
22. no interrupt process for the slave to signal to the master it wants to communicate The host decides when to send and receive data using pipe Out and pipe In functions in this case as well as how much data is transferred On the micro controller side the data sent by the PC or about to be sent to the PC is stored into dedicated FIFO memories The FPGA interface provided handles the FIFO communication simplifying further the communication with the PC The interface is constituted of a main interface module FX2 Interface and as many as 128 pipes although in practice much fewer will be required Each pipe offers an 8 bit wide data bus with read write control signals as well as a pause signal so the user application can pause the transaction if required The user instantiates as many pipes as required in its application and gives them all a unique address This is depicted in figure 4 below Two sort of pipes are provided Pipeln and PipeOut Pipeln is used when receiving data into the FPGA and PipeOut when sending data to the host PC Note on the FPGA side the pipeln ent entity is used to receive data from the PC and the pipeOut ent entity to send data to the PC So pipe out function of the PC connects to the pipeln ent entity of the FPGA and pipe in function of the PC connects to pipeOut_ent entity of the FPGA The in out direction is always the one relating to the device being programmed PC or aes220 Keep in mind however that th
23. ort Connections to the FX2 interface IP in in std logic vector 18 downto 0 PI out out std logic vector 9 downto 0 User application connections P ADDR in in std logic vector 6 downto 0 The pipe address set by user app PAUSE in in std logic Pause input for pausing transfer WRITE RQ out out std logic Data available flag to user app DATA in in std logic vector 7 downto 0 data to user app NESSENT Page 19 of 29 www aessent com Doc Nb UM220 01 A aes220 UserManual V1 4 1 During simulation the data can be received from the pipe using the function pipe in provided in the aes220_SimulationPackage vhd pipe in inChannel v dataSize v dataln_ar rst s fi s if s ifData s Where the signals on the bottom row are linking the function to the interface and are declared in the simulation package There is no need to change these The other three parameters in the function are in order The pipe address inChannel v The number of bytes to be received dataSize v A pre arranged byte array to store the data coming in dataln ar Note that the types byte and byte array are also declared in the simulation package as subtype byte is std logic vector 7 downto 0 type byte array is array natural range lt gt of byte Note although it is the PipeOut component of the FPGA described here it is linked to the simulation function pipe in as this function emula
24. solute Maximum Power essen se eisen 28 Figure 16 aes220 Board Dimensions ccssssccsosssasssacevseerocscovsssvansvarstenesatacavasceacerorssaceveresotsnoeaseratoess 29 Index of Tables Table 1 Power Supply E apablilities roo Doa ee 8 Table 2 aes220 FX2 Interface Parameters ccccccccssssssssssssssssssssssssssssssssssssssssssesssessccccceeeeaesess 14 Table 3 388220 Ppeln Parmesan 16 Table 4 aes220 PipeOut Parameter une 19 Table 5 FPGA Thermal Characteristics una ee 26 Table 6 Max Recommenced Power a arb ke PRSE dba ERE qu PEU VAE IRE E MEER Hebe NUEVO dU gU tS Ard RMUE 27 Table 7 Absolute Maximum Power unse 28 hnology WWAOQESSBITLGDIR Doc Nb UM220 01 A aes220 UserManual V1 4 1 1 Overview 1 1 Description The aes220 is a high speed USB 2 0 480Mb s FPGA module for rapid prototyping and incorporation in other systems It combines a Cypress CYC7C68013A FX2LP High Speed USB 2 0 micro controller with a Xilinx Spartan 3AN device XC3S200AN connected to a 128Mb SDRAM The module includes its own DC DC converter and crystal oscillator All it requires is a 5bVdc power supply if disconnected from the USB Its tiny 43x61mm size allows fitting in confined spaces and thanks to its stackable interface it can easily be combined with other modules The device small size does not prevent it from offering a total of 72 General Purpose Inputs Outputs GPIO 12 of which can be used as clock inputs fed directly to the
25. tes the function used on the host PC to receive data from the FPGA Note please have look at the aes220 Loopback Example for a demonstration on how all these elements interact with each other Page 20 of 29 Anolog www aessent com Doc Nb UM220 01 A aes220 UserManual V1 4 1 3 Features 3 1 LED and switches There are four LED and two switches available to the user connected directly to the FPGA The LED are active low setting the FPGA pins to 0 turns them on while the switches are normally open and the corresponding FPGA pin reading them tied to ground via a pull down resistor See Figure 10 for the related schematics 3Vis Figure 10 LED and switches schematics Available on the website www aesent com is a constraint file provided for the FPGA ISE environment aes 220 Revxx LED ucf that can be used directly by the user 3 2 Page 21 of 29 AESSENT www aessent com Doc Nb UM220 01 A aes220 UserManual V1 4 1 3 3PC The 12C functions of the micro controller are available to the user The clock and data line of the bus are connected to the FPGA and can be used by the application within the FPGA or outputted to the outside world The micro controller acts as an I2C master There are three functions provided to the user via the API to communicate with resources attached to the bus readl2C writel2C and combinedl2C Please see the API documentation for more information Note however that both th
26. ule can draw more than that it is the responsibility of the user to ensure its application won t exceed the USB specification using Xilinx power estimator tools for example If it is the case a 5V external power supply via P1 or P2 must be used The on board power supply converter can provide up to 1 5A on the 3 3V rail used by the inputs outputs of the FPGA On the unlikely event that more power is required it is possible to turn off the on board power supply and provide the 3 3V directly to the FPGA please refer to the API on how to turn off the 3 3V rail Note however that for this amount of power the FPGA will require some form of cooling to be provided See table 1 below for the different supplies capabilities Note it might also be necessary to turn of the 3 3V rail if stacking up boards together Only one of the boards should provide the 3 3V to the rail or none if an external 3 3V power supply is used Power Supply Capability Demand Client Device Switching 3 3V 1 5A Design dependent max 4A FPGA I O Bank 0 2 3 Switching 1 2V 1 5A Design dependent max 600mA FPGA Core Linear 3 3V 300mA Design dependent max 150mA FPGA 85mA FPGA Aux micro controller uC Linear 1 8V 300mA 70mA SDRAM FPGA Bank 1 activity SDRAM FPGA Bank 1 I O Table 1 Power Supply Capabilities Power dissipation will limit how much current can be drawn to something lower than the power supply limits Page 8 of
27. ver power cycles The integrated flash memory can be used for device configuration with enough space for two different configurations or data storage or a mix of both In addition the SDRAM device provides 128Mb of RAM memory with fast access time 16bits parallel data bus and 100MHz clock See the Xilinx web site for more documentation on the FPGA itself The Cypress FX2LP micro controller provides the communication between the host computer and the FPGA The RAM and EEPROM of the micro controller are fully accessible allowing customisation of the communication link However the communication channel between the PC micro controller and FPGA is fully set up requiring no intervention from the user Both the micro controller and the FPGA can be configured using a simple USB cable or also using a JTAG programmer via standard Xilinx JTAG connector in the case of the FPGA VHDL or Verilog code synthesising for the FPGA is via Xilinx free ISE WebPACK or ISE Design Suite both downloadable from the Xilinx website There is no need for learning about USB communication protocols as libraries are provided for dealing with the communication between the host PC the micro controller and the FPGA All programs and libraries are free and Open Source so as not to be tied up with any proprietary tools and permitting customisation if required Examples tools and libraries are all available on both Windows and Linux platforms Page 6 of 29 AESSENT www aessent co
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