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VM1548C - VTI Instruments

1. TETE O VXI Technology Inc Regardless of whether the VM1548C is configured with other VM1548C modules or with other VMIP modules each group of 48 channels is treated as an independent instrument in the VXIbus chassis and as such each group has its own FAIL POWER and ACCESS ERROR indicators FEATURES e 48 channels 6 groups of 8 bits Up to 144 channels in a single C size card e Group wise programmable as an input or an output through user TTL input or VXI A16 registers e Group wise programmable polarity through VXI A16 registers as an active high or low e Input 0 V to 60 V gt 2 0 V Vinuow lt 1 5 V input impedance gt 65 e Output Open collector N DMOS 0 V to 60 V up to 300 mA continuous with over voltage and over current protection Data throughput 5 us typical system speeds 200 kilobytes per second using D8 access 400 kB per second using D16 access e Data Input Output Clock Sources For eac
2. 61 itte ene RU e EUER EU e nS 62 INP t REGister S OURCe rhe s tdi cm d eR Rc E ERR HERREN E 63 TIN Puts DEL LEES inire ett eer ves i eie e t e oco ml e i E 64 INPutETETrg S TATE terere epe om e e E dre eL UP NO ER REMITU 65 OUTPut GEOGCIENABle rrr o RW S Evi rie UD Her ge ee a reser TERRE Nn 66 OUTPut CEOCK PO LDarnty enrich ERE HEP ER OCA RED pce Rp LEUR Rd 67 OUTPutGCLOCkSOURGe mS Pe n BERG Rds 68 OUTP tREGisterPO Latrty ere ose e HORE esti c esi ette RI 69 OUTP t RBGister SOURCe aai aee E ei dte id PR e EE E 70 c ches 71 OUTPut T TETus POLarnty ternera terere ene prece artis 72 OQUTPUET TET ugsSOUReGe 2 nep teo tite e dei eo EO UR D 73 OUTPut TTL Tr g SPATE teet eee tee d tee eret dee d ds gei tede es 74 IRE ADD am RE IIR 75 READ CLOCK Sic losses eth n bck Oe EEN 76 ee 77 eene temo nto 78 RESeCISENSe inter ete eite eee ee menie tere P E tee eta 79 L M 80 SOURce DATA ENADBIe un SERERE ERRARE n n
3. SYSTem VER Sion Purpose Queries the SCPI version number with which the VM1548C complies Type Required SCPI command Command Syntax None query only N A RST Value N A Query Syntax SYSTem VERSion Query Parameters None Query Response Numeric ASCII value Description The System Version query reports version of the SCPI standard with which the VM1548C complies Examples Command Query Response Description SYST VERS 1994 0 Related Commands None VM1548C Command Dictionary VXI Technology Inc 96 VM1548C Command Dictionary www vxitech com SECTION 5 THEORY OF OPERATION INTRODUCTION The 1548 TTL I O module is a VXI message based device consisting of six channels of bi directional I O The six channels or ports are configured as inputs or outputs in groups of eight bits that can be clocked from internal or external sources The six channels can be remotely configured from the front panel connector I O signal or from the VMIP module through SCPI commands The clocking can be from one of eight VXI TTL trigger lines a word serial event or an externally supplied clock This clocking method allows for large parallel data words to be transmitted or received The VM1548C contains the capability to generate a TTL trigger onto the VXI backplane using a word serial event one of six front panel clock inputs or from a TTL Trigger input By utilizing the D16 access the VM1
4. VM1548C Command Dictionary 47 TABLE 4 2 INSTRUMENT SPECIFIC SCPI COMMANDS VXI Technology Inc Command Description RST Reset Value FORMat Sets the output format for digital queries X ASCII Decimal INPut REGister POLarity Sets the active edge of the clock for an input port X Rising Edge INPut REGister SOURce Selects the source to clock input data port X Disabled INPut TTL Trig Selects 1 of 8 VXI Trigger lines as the input X 0 trigger INPut TTLTrig STATE Enable disable MUX that selects an input trigger X Disabled OUTPput CLOCKk ENABlIe Sets the Clock pin to be an output or an input X Input OUTPut CLOCk POLarity Sets the active edge of a port s associated clock X Rising edge OUTPut CLOCk SOURce Sets the source of a port s associated clock X NONE OUTPut REGister POLarity Controls the polarity at which output data is X Riese latched to the specified port OUTPut REGister SOURce Controls the source of the clock that will latch n X Disabled output data to the specified port OUTPut TTL Trig Selects 1 of 8 VXI Trigger lines as the output X 0 trigger OUTPut TTL Trig POLarity Sets the active edge of the TTL trigger X NORMal OUTPut TTLTrig SOURce Selects the source for the internal signal TRIGOUT NONE OUTPut TTLTrig STATE Enable disable MUX that selects an output trigger X Off READ Queries an 8 bit input data port N A READ
5. 0 to 63 decimal Description The Read Control command queries and returns the I O control line levels The 6 bit response signifies a high or low on each control line 0 through 5 The control lines I O 0 through I O 5 are accessed from the front panel These signals are normally pulled high The user has the option of setting SOURce DATA ENABle to 0 or OFF which is the default and controlling the ports as inputs or outputs by driving the front panel control lines The following table shows the logic port outputs the T O control line input end up inverted Source Data Enable User I O Control Port 0 0 Output 0 1 Input Default condition 1 0 Output 1 1 Output Examples Command Query Response Description READ CONT 12 See table below Related Commands SOURce DATA ENABle 5 4 21110 Bits 0 1 1 01010 I O Control lines 2 and 3 would return a decimal value of 12 VM1548C Command Dictionary 77 VXI Technology Inc READ ISENse Purpose Queries the drive disable over current status level of each group of six lines Type Query Command Syntax N A N A RST Value N A Query Syntax READ ISENse Query Parameters N A Query Response 0 to 255 decimal Description The Read ISense command queries and returns the drive disabled status on each group of six lines The 8 bit respons
6. SOURce DATA Purpose Writes an 8 bit data value to the specified output port Type Event Command Syntax SOURce DATA lt port gt lt n gt port 0 1 2 3 4 5 lt n gt 0 255 RST Value 1 on all ports Query Syntax SOURce DATA lt port gt The query returns the last value written to the data register regardless of the direction the data register is currently being driven The format of the returned information is determined by the FORMat command Query Parameters port gt 0 1 2 3 4 5 Query Response 0 255 Description The Source Data command will write an 8 bit value to the specified output port This command requires that the register be enabled as an output port The operation mode of the register clocked or transparent can also affect what data is actually presented to the external connector Examples Command Query Response Description SOUR DATA 0 87 SOUR DATA 0 87 Related Commands SOURce DATA ENABIle port lt boolean gt OUTPut REGister SOURce lt port gt lt source gt FORMat type 80 VM1548C Command Dictionary www vxitech com SOURce DATA ENABle Purpose Sets the direction in which the module s ports will be driven Type Setting Command Syntax SOURce DATA ENABle lt port gt lt boolean gt lt port gt 0 1 2 3 4 5 boolean 011 OF ON RST
7. Technology VM1548C TTL I O MODULE USER S MANUAL P N 82 0045 000 Released June 15 2010 VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 949 955 1894 www vxitech com TABLE OF CONTENTS INTRODUCTION Limitation of Warranty Restricted Rights Legend Declaration of Conformity Terms and 5ymbols rp hereto a RAS NR Cay ns M armngszs ote af c n deo a stetit INTRODUCTION tr ee rre RR OI D REO GRAN UA QU IER evo RT xen Yo Wins eee RES dure pe ERR Mionpei ME sacs Eeaturesg iit rre RU REOR Spe eden e e PERO RU ere etre LR Des riptlon zie d ee ede tee ree ated caudate uten ety edet ede E deor eden le ge ds Programming and Data Access VM1548 Specifications PREPARATION FOR USE i oie tr RU RE RENI EQ TAE ENIRO Ee ES ette d i e rte Calculating System Power and Cooling Requirements Setting the Chassis Backplane Jumpers Setting the Logical Address iie eet ute ded e HU a e a Aa E REET Aana Front Panel Interface Wiring ener innen nennen entente tnter e rente nennen nennen enne PROGRAMMING TithOCUC HONS ERSTE TT EE INO CAE OTe e iere web ea etii den iU dep M T Oe ale EXAMPLES OF SCPE COMMANDS ee eee i ea e TTISERTGEG
8. 1 2 3 4 5 NONE TTLT EXT IMM GLOB The Input Register Source command controls what signal will be used for the specified port s input clock Source Parameter Description NONE This disables the specified port s input clock The data appearing on the specified port is read without any latching TTLTrig This selects the VXIbus TRIGIN as the clock source TRIGIN can be 1 of 8 TTL trigger lines on the VXI bus See INPut TTLTrig EXTernal This selects the port s associated CLK line coming from the 68 pin external connector as the clock source IMMediate This selects the Word Serial Event as the clock source See trigger sequence immediate GLOBal This selects TRIGOUT as the clock source See OUTPut TTLTrig SOURce Command Query Response Description INP REG SOUR 0 TTLT INP REG SOUR 0 INPut REGister POLarity lt port gt lt edge gt VM1548C Command Dictionary 63 VXI Technology Inc INPutTTLTrig Purpose To select a specific VXIbus trigger line as TRIGIN Type Setting Command Syntax INPut TTL Trig n 2 lt n gt 0 1 2 3 4 5 6 7 RST Value 0 Query Syntax INPut TTLTrig Query Parameters N A Query Response Numeric ASCH value between 0 and 7 Description The Input TTLTrig command controls which of the 8 VXI trigger lines will be selected as TRIGIN The 8 VXI trigger lines feed into an 8 to 1 multiplexer The se
9. CLOCks Queries the clock line levels N A READ CONTrol Queries the I O control line levels N A READ ISENse Queries the drive disable over current status level N A of each group of six lines RESet ISENse Resets drive disable of a group of six lines N A SOURce DATA Sets the value driven by an output port X 0 SOURce DATA ENABle Sets an eight bit port for input or output X Input SOURce DATA POLarity Sets the output polarity on an 8 bit port X NORMal STATus INTerrupt ENABle Enables or disables Interrupts to the backplane x NONE STATus INTerrupt PTRansition Sets Interrupts to occur on a positive transition x 1 STATus INTerrupt NTRansition Sets Interrupts to occur on a negative transition X 0 TRIGger SEQuence IMMediate A word serial event which generates a short pulse N A 48 VM1548C Command Dictionary www vxitech com TABLE 4 3 SCPI REQUIRED COMMANDS Command Description Reset Value STATus OPERation EVENt Queries the Operation Status Event Register N A STATus OPERation CONDition Queries the Operation Status Condition Register N A STATus OPERation ENABle Sets the Operation Status Enable Register 0 STATus QUEStionable EVENt Queries the Questionable Status Event Register N A STATus QUEStionable CONDition 2 0 STATus QUEStionable ENABle Sets the Questionable Status Enable Register N A STATus PRESet Presets the Status Register N A SYSTem ERRor Queries the Error
10. DEVICE TRANSFERS READ MODE DIRECTION When read transfers from the UUT are selected the VM1548C will select the direction of the transfer enable the clocks for the selected channel s latch the data into the I O Data Buffer if double buffering is selected using the appropriate triggering method and clock the I O Word Buffer This clock or trigger can be from either a TTL trigger input the front panel connector CLK input a word serial event or a TTL trigger out The front panel connector CLK input will be used to trigger the latching of data into the I O Data Buffer and then generate an Interrupt Request IRQ to the slot 0 controller Direction of transfer is controlled either from the front panel connector or from the Direction Control latch see Figure 5 3 Upon receipt of the SCPI command the Timing and Control FPGA decodes the VMIP address and issues the DOE signal to the Read Write Data Buffer allowing the data on the inputs to be available on the outputs when both signals are low The Timing and Control FPGA then generates the PORTENA signal that provides low signal to the Port Decoder Address bits AO Al and A2 are decoded causing the Port Decoder to provide a low going edge clocking the Direction Control latch This octal D latch provides the direction signal a low equates to read and a high equates to write This then is OR ed with the corresponding I O signal from the front panel connector The fr
11. If an X is found in the column titled RST then the value or setting controlled by this command is possibly changed by the execution of the RST command If no X is found then RST has no effect The Reset Value column gives the value of each command s setting when the unit is powered up or when a RST command is executed VM1548C Command Dictionary 45 TERMINOLOGY Port CLKO 5 TRIGOUT TTLTRIGGER IMMEDIATE Clocked Mode Transparent Mode Numbers Queries VXI Technology Inc One of six data registers accessible via the 68 pin external connector These registers are 8 bits wide and are programmable to be bi directional Port is also sometimes referred to as just register The 6 input clocks coming from the external connector The selected signal from the SCPI command This signal is referred to as GLOBAL throughout the command dictionary section This is due to the capabilities of this signal to trigger all ports at time OUTPUT TTLTRIG SOURCE The signal GLOBAL TRIGOUT after applying the polarity control OUTPUT TTLTRIG POLARITY This is an abbreviation for Word Serial Event IMMEDIATE refers to the SCPI Command TRIGger SEQuence IMMediate which will generate very short pulse This refers to the method of operation of a port The data will be latched out or in with reference to a clock source This refers to the method of operation of a port For example if the port is being used as an ou
12. lt boolean gt OUTPut CLOCk POLarity port edge 68 VM1548C Command Dictionary www vxitech com OUTPut REGister POLarity Purpose Controls the polarity at which output data is latched to the specified port Type Setting Command Syntax OUTPut REGister POLarity lt port gt lt edge gt lt port gt 0 1 2 3 4 5 edge NORMal INVert RST Value NORMal Query Syntax OUTPut REGister POLarity lt port gt Query Parameters port gt 0 1 2 3 4 5 Query Response NORM INV Description The Output Register Polarity command controls the polarity at which output data is latched to the specified port A polarity of NORMal would cause the data to be latched out on a rising edge of the clock A Polarity of INVert would cause the data to be latched out on a falling edge of the clock Note that it is important to remember that the output register must be operating in clocked mode in order for the polarity to affect the Output Register latching Examples Command Query OUTP REG POL 0 NORM OUTP REG POL 0 NORM Related Commands OUTPut REGister SOURce lt port gt lt source gt VM1548C Command Dictionary 69 VXI Technology Inc OUTPutREGister SOURce Purpose Controls the source of the clock that will latch output data to the specified port Type Setting Command Syntax OUTPut REGister SOURce po
13. 2 COMMON COMMANDS CLS Purpose Clears the Status Register Type IEEE 488 2 Common Command Command Syntax CLS None RST Value N A Query Syntax None Query Parameters N A Query Response N A Description This command clears all event registers clears the OPC flag and clears all queues except the output queue Examples Command Quer Response Description CLS Related Commands None VM1548C Command Dictionary 51 VXI Technology Inc ESE Purpose Sets the bits of the Event Status Enable Register Type IEEE 488 2 Common Command Command Syntax ESE lt mask gt mask numeric ASCII value from 0 to 255 RST Value None the parameter is required Query Syntax ESE Query Parameters None Query Response Numeric ASCII value from 0 to 255 Description The Event Status Enable command is used to set the bits of the Event Status Enable Register See ANSI IEEE 488 2 1987 section 11 5 1 for a complete description of the ESE register A value of 1 in a bit position of the ESE register enables generation of the ESB Event Status Bit in the Status Byte by the corresponding bit in the ESR If the ESB is set in the ESR register then an interrupt will be generated See the ESR command for details regarding the individual bits The ESE register layout is Bit 0 Operation Co
14. DATA ENAB 2 O SOUR DATA ENAB 3 OFF SOUR DATA ENAB 4 OFF SOUR DATA ENAB 5 OFF SOUR DATA 0 01 SOUR DATA 1 23 SOUR DATA 2 45 STAT INT ENAB EXT 5 STAT INT PTR O TRIG SEQ IMM READ 3 READ 4 READ 5 DESCRIPTION Selects External clock line as the clock source for port 3 Selects the inverted falling clock edge for port 3 Selects External clock line as the clock source for port 4 Selects the inverted falling clock edge for port 4 Selects External clock line as the clock source for port 5 Selects the inverted falling clock edge for port 5 Enables the output clock for port 0 Selects the IMM word serial event to drive the external clock for port 0 Selects the IMM word serial event as the clock source for port 0 I O data buffers Enables the output clock for port 1 Selects the IMM word serial event to drive the external clock for port 1 Selects the IMM word serial event as the clock source for port 1 I O data buffers Enables the output clock for port 1 Selects the IMM word serial event to drive the external clock for port 1 Selects the IMM word serial event as the clock source for port 1 I O data buffers Configures port 0 I O data buffers for write mode Configures port I I O data buffers for write mode Configures port 2 I O data buffers for write mode Configures port 3 I O data buffers for read mode Configures port 4 I O data buffers for read mode Configures port 5 I O data buffers for read mode Writes dat
15. Insulation Displacement Connector component and is available from a variety of sources The connector attaches to two 34 conductor 0 050 centers ribbon cable and the pin out has been selected to allow for using the twisted pair type of ribbon cable Some manufacturers also allow the use of discrete 30 gauge stranded wires TABLE 2 1 J200 J201 AND J202 PIN OUTS PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL 1 GND 18 DATA1 5 35 GND 52 DATA4 5 2 DATAO 0 19 DATA1 6 36 DATAS 0 53 DATA4 6 3 DATAO 1 20 DATA1 7 37 DATAS 1 54 DATA4 7 4 DATAO 2 21 O 1 38 DATA3 2 55 1 0 4 5 DATAO 3 22 CLK1 39 DATA3 3 56 CLK4 6 DATAO 4 23 GND 40 DATA3 4 57 GND 7 DATAO 5 24 DATA2 0 41 DATAS 5 58 DATAS 0 8 DATAO 6 25 DATA2 1 42 DATA3 6 59 DATAS 1 9 DATAO 7 26 DATA2 2 43 DATA3 7 60 DATA5 2 10 1 0 0 27 DATA2 3 44 1 0 3 61 DATA5 3 11 CLKO 28 DATA2 4 45 CLK3 62 DATA5 4 12 GND 29 DATA2 5 46 GND 63 DATAS 5 13 DATA1 0 30 DATA2 6 47 DATA4 0 64 DATA5 6 14 DATA1 1 31 DATA2 7 48 DATA4 1 65 DATA5 7 15 DATA1 2 32 2 49 DATA4 2 66 5 16 DATA1 3 33 CLK2 50 DATA4 3 67 CLK5 17 DATA1 4 34 GND 51 DATA4 4 68 GND VM1548C Preparation for Use 19 VXI Technology Inc The mating connector to J200 J201 or J202 is available from the following companies AMP Inc P N 749621 6 Connector assembled termination cover P N 749111 7 Connector unassembled termination cover P N 749204 2 Backshel
16. It is important to remember that the interrupt trigger source should be either GLOBAL or 1 of 6 external clocks for setting the interrupt trigger source to occur on a positive transition Examples Command Query STAT INT PTR 1 STAT INT STAT INT PTR O0 STAT INT STAT INT PTR PTR NTR Related Commands STATus INTerrupt ENABle lt source gt STATus INTerrupt NTRansition lt boolean gt VM1548C Command Dictionary 85 VXI Technology Inc TRIG ger SEQuence IMMediate Purpose A word serial event which generates a short pulse Type Event Command Syntax TRIGger SEQuence IMMediate None RST Value N A Query Syntax None Query Parameters N A Query Response N A Description This command generates a short pulse or a word serial event for the trigger signal Examples Command Query Response Description TRIG SEO IMM Related Commands TRG 86 VM1548C Command Dictionary www vxitech com SCPI REQUIRED COMMANDS STATus OPERation Purpose Queries the Operation Status Event Register Type Required SCPI command Command Syntax None query only N A RST Value N A Query Syntax STATus OPERation EVENt Query Parameters None Query Response 0 Description The Status Operation Event Register query is included for SCPI compliance The VM1548C does
17. N A N A The Reset command resets the module s hardware and software to a known state See the command index at the beginning of this section for the default parameter values used with this command Command Query Response Description RST None 56 VM1548C Command Dictionary www vxitech com STB Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands Queries the Status Byte Register 488 2 Common Command None query only N A N A STB None Numeric ASCII value from 0 to 255 The Read Status Byte query fetches the current contents of the Status Byte Register See the IEEE 488 2 specification for additional information regarding the Status byte Register and its use The layout of the Status Register is Bit 0 Unused Bit 1 Unused Bit 2 Error Queue Has Data Bit 4 Questionable Status Summary over current Bit 5 Message Available Bit 6 Master Summary Status Bit 7 Operation Status Summary Command Query Response Description STB 16 None VM1548C Command Dictionary 27 TRG VXI Technology Inc Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands Causes a trigger ev
18. Polarity 0 vtvm1548 POL INVERT Inverted Polarity 1 Vilntl16 data This parameter is used to specify the 8 bit data value that is to be written to the output port Valid Range vtvm1548 DATA MIN 0 to vtvm1548 255 Return Values Returns VI SUCCESS if successful Else returns error value Description This function is an application function that shows how the user can use core functions to set up the specified port as output and write the specified data value to it It then triggers the port to output its data KOR KKK KK KK I KCKCK KK A I ViStatus VI FUNC vtvm1548 setupAndWriteData ViSession instrHndl Vilntl16 portNumber ViInt16 clkSource ViBoolean polarity ViIntl6 data Variable used to store return status of the function ViStatus status VI_NULL Setup the specified port as output and configure the clock associated with it 7 status vtvm1548 configPort instrHndl portNumber vtvm1548 MODE OUTPUT vtvm1548 MODE OUT clkSource polarity if status VI SUCCESS return vtvm1548 ERROR SETTING PORT Set up the specified port s register source status vtvm1548 configRegister instrHndl portNumber vtvm1548 CLK SOURCE IMM VI NULL 40 VM1548C Programming www vxitech com if status lt VI_SUCCESS return vtvm1548 ERROR SETTING REGISTER Write the input 8 bit data to the speci
19. Queue Clears queue SYSTem VERSion Queries which version of the SCPI standard the N A module complies with VM1548C Command Dictionary 49 VXI Technology Inc COMMAND DICTIONARY The remainder of this section is devoted to the actual command dictionary Each command is fully described on its own page In defining how each command is used the following items are described Purpose Describes the purpose of the command Type Describes the type of command such as an event or setting Command Syntax Details the exact command format Command Parameters Describes the parameters sent with the command and their legal range Reset Value Describes the values assumed when the RST command is sent Query Syntax Details the exact query form of the command Query Parameters Describes the parameters sent with the command and their legal range The default parameter values are assumed the same as in the command form unless described otherwise Query Response Describes the format of the query response and the valid range of output Description Describes in detail what the command does and refers to additional sources Examples Present the proper use of each command and its query when available Related Commands Lists commands that affect the use of this command or commands that are affected by this command 50 VM1548C Command Dictionary www vxitech com IEEE 488
20. VMIP receives the SCPI command for writing data The Timing and Control FPGA decodes the address and control bits from the VMIP bus and generates the DOE signal to the Read Write Data Buffer The Timing and Control FPGA then issues the WRITEO signal to the selected I O Word Buffer thus latching the data The I O buffers are enabled and configured to transmit data from channel 0 to the UUT upon receipt of the proper clock or trigger from front panel Control Lines WRITEO Timing and 200K Control PORTENA PORT2 gt Port b Decoder Direction D8 D1 Control OUTENAO VMIP Bus Address 0 1 2 IN OUTO 7 CLKOUTENAO P Read 5 Clack Buffer Enable WRITEO D TA Data Bus Output to Front Panel Data Bus Data Bus FIGURE 5 1 WRITE MODE BUFFER CONFIGURATION VM1548C Theory Of Operation 99 VXI Technology Inc DEVICE TRIGGERING TTL INPUT TRIGGER The VM1548C is capable of both receiving and generating VXI TTL triggers The generated TTL triggers may be used to signal another VXI instrument that a VM1548C event has occurred The VM1548C can also receive any one of eight TTL triggers from the VXI backplane TTL trigout or a front panel connector clock line for use in triggering all six channels at once TRIGGER DECODE Upon receipt of the command that informs the Timing and Control FPGA that the input trigger feature has been selected The Timing and Control FPGA
21. Value 0 Query Syntax SOURce DATA ENABle lt port gt Query Parameters port gt 0 1 2 3 4 5 Query Response 011 Description The Source Data Enable command controls the direction of the I O data buffers as either read or write ON or sets the port as an output OFF or 0 sets the port as an input Examples Command Query SOUR DATA ENAB 0 SOUR DATA ENAB 0 Related Commands SOURce DATA lt n gt READ lt port gt VM1548C Command Dictionary 81 VXI Technology Inc SOURce DATA POLarity Purpose Sets the output polarity on an 8 bit port Type Setting Command Syntax SOURce DATA POLarity port gt NORMal INVert port 0 1 2 3 4 5 NORMal 1 in 1 out INVert 1 in 0O out RST Value NORMal on all ports Query Syntax SOURce DATA POLarity lt port gt Query Parameters port gt 0 1 2 3 4 5 Query Response NORM INV Description The Source Data Polarity command sets the output polarity on an 8 bit port Examples Command Quer SOUR DATA POL 1 INV SOUR DATA POL 1 Inverts the output on port 1 INV Related Commands SOURce DATA ENABle port boolean 82 VM1548C Command Dictionary www vxitech com STATus INTerrupt ENABle Purpose Enables and sets the interrupt trigger source or disables the interrupt to the backp
22. external clocks Command Query OUTP TTLT POL NORM OUTP TTLT POL OUTPut TTL Trig n OUTPut TTLTrig STATe boolean OUTPut TTLTrig SOURce source 72 VM1548C Command Dictionary www vxitech com OUTPut TTLTrig SOURce Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Selects the source for the internal signal TRIGOUT Setting OUTPut TTLTrig SOURce lt source gt lt source gt EXTernal0 5 IMMediate NONE NONE OUTPut TTLTrig SOURce N A 5 IMM NONE The Output TTL Trig Source command selects which signal EXTernal0 5 IMMediate or NONE will be used as the TRIGOUT signal The TRIGOUT signal is referred to throughout this manual as GLOBAL Source Parameter Description EXTernal0 5 Selects one of the six external clocks as TRIGOUT See the clock circuit description IMMediate This selects the Word Serial Trigger event as TRIGOUT See TRG and TRIGger SEQuence IMMediate NONE This parameter routes Ground to TRIGOUT thereby selecting no signal as TRIGOUT Examples Command Query Response Description Related Commands OUTP TTLT SOUR IMM OUTP TTLT SOUR IMM INPut REGister SOURce OUTPut CLOCk SOURce OUTPut REGister SOURce OUTPut TTLTrig OUTPut TTLTrig STATe OUTPut TTLTrig POLarity STATus INTerrupt ENA Ble VM1548C Co
23. generates the PORTENA signal that provides a low signal to the Port Decoder see Figure 5 2 Address bits AO Al and A2 are decoded causing the Port Decoder to provide a low going edge clocking the Trigger Select latch The Trigger Select latch then outputs the binary equivalent number that matches the desired trigger and the trigger input enable signal TINENA TRIGGER SELECT The select lines TINSELO TINSEL1 TINSEL2 and enable signal TINENA are then routed to the Trigger Input Mux This 8 1 mux will select the desired trigger The output of the Trigger Input Mux is the signal TRIGIN and is routed to the Timing and Control FPGA Once inside the Timing and Control FPGA the TRIGIN signal may be inverted to produce a falling edge if this feature has been selected or remain in the normal default state of a rising edge The signal is then muxed to the output clock circuitry in the Timing and Control FPGA and routed to the selected I O Data Buffer as CLKOUTO The rising edge of this signal then clocks the I O Data Buffer to drive the I O data outputs onto the UUT 100 VM1548C Theory Of Operation www vxitech com TRIGINO 7 Trigger In Mux e Control Lines WRITE Timing and Control CLKOUTO TINENA Port Address 0 1 2 Decoder Trigger Select CLKOUTO Data Buffer Data Bus Data Bus Data Bus FIGURE 5 2 TTL TRIGGER INPUT VM1548C Theory Of Operation 101 VXI Technology Inc
24. not alter any of the bits in this register and always reports a 0 Examples Command Quer Response Description STAT OPER 0 Related Commands None VM1548C Command Dictionary 87 VXI Technology Inc STATus OPERation CONDition Purpose Queries the Operation Status Condition Register Type Required SCPI command Command Syntax None query only S O IE N A RST Value N A Query Syntax STATus OPERation CONDition Query Parameters None Query Response 0 Description The Operation Status Condition Register query is provided for SCPI compliance only The VM1548C does not alter the state of any of the bits in this register and always reports a 0 Examples Command Query Response Description STAT OPER COND 0 Related Commands None 88 VM1548C Command Dictionary www vxitech com STATus OPERation ENABle Purpose Sets the Operation Status Enable Register Type Required SCPI command Command Syntax STATus OPERation ENABle lt NRf gt 2 lt NRf gt numeric ASCII value from 0 to 32767 RST Value 0 Query Syntax STATus OPERation ENABle Query Parameters None Query Response Numeric ASCII value from 0 to 32767 Description The Operation Status Enable Register is included for SCPI compatibility and the VM1548C does not alter any of the bits in this register The re
25. port gt ON enables the selected ports for a write in this case ports 0 1 and 2 The SOUR DATA ENAB lt port gt OFF enables the selected ports to read in this case ports 3 4 and 5 The SOUR DATA lt port gt lt data gt commands writes the data into the specified ports as previously described The STAT INT ENAB EXT 5 and STAT INT PTR ON commands enable the interrupt to occur when the CLK 5 signal is received and sets the polarity of this interrupt to the positive edge TRIG SEQ IMM command will generate a short pulse that will initiate the transfer of data from ports 0 1 and 2 to ports 3 4 and 5 When CLK 5 has been received the VM1548C module sends an Interrupt Request IRQ informing the slot 0 controller via the VMIP that the transfer has occurred The READ lt port gt will then fetch the data from the specified ports VM1548C Programming 35 TABLE 3 1 WRAP AROUND TEST CABLE FROM TO Signal Pin Signal Pin DATAO 0 2 DATA3 0 36 DATAO 1 3 DATA3 1 37 DATAO 2 4 DATA3 2 38 DATAO 3 5 DATA3 3 39 DATAO 4 6 DATA3 4 40 DATAO 5 7 DATA3 5 41 DATAO 6 8 DATA3 6 42 DATAO 7 9 DATA3 7 43 I O 0 10 I O 3 44 CLKO 11 CLK3 45 DATAI 0 13 DATA4 0 47 DATAI 1 14 DATAA 1 48 DATAI 2 15 DATA4 2 49 DATAI 3 16 DATA4 3 50 DATAI 4 17 DATA4 4 51 DATAI 5 18 DATA4 5 52 DATAI 6 19 DATA4 6 53 DATAI 7 20 DATAA 7 54 I O 1 21 I O 4 55 CLKI 22 CLK4 56
26. 4 Pointer High 38 VM1548C Programming www vxitech com VXIPLUG amp PLAY EXAMPLES KR KR KKK KK KK RI I RA I I I RK KR ke e x kx x T APPLICATION FUNCTION KR KR KKK KK KR RK I vtvm1548_setupAndWriteData Function Formal Parameters ViSession instrHndl A valid session handle to the instrument Vilntl16 portNumber This parameter is used to set the port and the clock associated with the specified port to which the 8 bit data value is to be written Valid Values Interpretation vtvm1548 PORT ZERO Port Zero vtvm1548 PORT ONE Port One vtvm1548 PORT TWO Port Two vtvm1548 PORT THREE Port Three vtvm1548 PORT FOUR Port Four vtvml1548 PORT FIVE Port Five Vilntl16 clkSource This parameter is used to set the source of the clock circuit associated with the specified port Valid Values vtvm1548 CLK SOURC vtvm1548 CLK SOURC vtvm1548 CLK SOURC vtvm1548 CLK SOURC ViBoolean polarity This parameter is used to set the polarity of the clock circuit associated with the specified port This parameter is considered only if the specified clock source is either vtvm1548 CLK SOURCE TTLT or tvm1548 CLK SOURCE GLOB I Interpretation E IMM Word Serial Event E TTLT VXIbus TRIGIN E GLOB TRIGOUT E NONE Ground VM1548C Programming 39 VXI Technology Inc Valid Values Interpretation vtvm1548 POL NORM Normal
27. 548C can achieve data throughput rates of 4 megabytes per second MB s The VM1548C contains 22 Q series damping resistors on all data lines to reduce ringing during data transition period and a RC network of a 120 Q resistor in series with a 100 pF capacitor for termination of clock lines All channels 0 through 5 on the VM1548C perform identically that is all buffers are loaded the same way all channels are accessed the same etc Because of this similarity for clarity the theory of operation will describe channel 0 for byte wide and channels 0 and 1 for word wide operations VM1548C Theory Of Operation 97 VXI Technology Inc VXI INTERFACE DEVICE TRANSFERS WRITE MODE DIRECTION When write transfers to the UUT are selected the VM1548C will select the direction of the transfer enable the clocks for the selected channel s latch the data into the I O word buffer and clock the I O data buffer using the appropriate triggering method Direction of transfer is controlled either from the front panel connector or from the Direction Control latch see Figure 5 1 Upon receipt of the SCPI command for setting the direction the Timing and Control FPGA decodes the VMIP address and issues the DOE signal to the read write data buffer This allows the transceiver Read Write Data Buffer to be configured to write data when both signals are low The Timing and Control FPGA then generates the PORTENA signal that provides a lo
28. BACKPLANE JUMPERS Please refer to the chassis User s Manual for further details on setting the backplane jumpers VM1548C Preparation for Use 17 VXI Technology Inc SETTING THE LOGICAL ADDRESS The logical address of the VM1548C is set by a single 8 position DIP switch located near the module s backplane connectors this is the only switch on the module The switch is labeled with positions through 8 and with an ON position A switch pushed toward the ON legend will signify a logic 1 switches pushed away from the ON legend will signify a logic 0 The switch located at position 1 is the least significant bit while the switch located at position 8 is the most significant bit See Figure 2 1 for examples of setting the logical address switch Switch Switch Position Value 1 1 2 2 3 4 4 8 5 16 6 32 7 64 8 128 FIGURE 2 1 LOGICAL ADDRESS SWITCH SETTING EXAMPLES The VMIP may contain three separate instruments and will allocate logical addresses as required by the VXIbus specification revisions 1 3 and 1 4 The logical address of the instrument is set on the VMIP carrier The VMIP logical addresses must be set to an even multiple of 4 unless dynamic addressing is used Switch positions 1 and 2 must always be set to the OFF position Therefore only addresses of 4 8 12 16 252 are allowed The address switch should be set for one of these legal addresses and the address for the second instrument the instrume
29. CLK SOURCE GLOB Valid Values Interpretation vtvm1548 POL NORM Normal Polarity 0 vtvm1548 POL INVERT Inverted Polarity 1 ViPIntl16 data This parameter returns the 8 bit data value that has been read from the specified input port Returns VI SUCCESS if successful Else returns error value Description This function is an application function that shows how the user can use core functions to set up the specified port as input It triggers the port to input the data and reads the same KOR KKK KK KK KK I KCKCKC I kokck ckckok ck kok ck ckok ck kok ck ke ke e kx ViStatus VI FUNC vtvm1548 setupAndReadData ViSession instrHndl status ViInt16 portNumber Vilntl16 clkSource ViBoolean polarity ViPInt16 data Variable used to store return status of the function 7 ViStatus status VI NULLI Setup the specified port as input and configure the clock associated with it vtvm1548 configPort instrHndl portNumber vtvml1548 MODE INPUT vtvm1548 CLK MODE IN clkSource polarity E 42 VM1548C Programming www vxitech com if status lt VI SUCCI ESS return v tvm1548 ERROR SETTING PORT Setup the specified port s register source status vtvm1548 configRegister instrHndl portNumber if status VI SUCCI ESS return v vtvm1548 CLK SOURCE IMM VI NULL I tvm1548 ER
30. DATA2 0 24 DATAS O 58 DATA2 1 25 DATAS 1 59 DATA2 2 26 DATAS 2 60 DATA2 3 27 DATAS 3 61 DATA2 4 28 DATAS 4 62 DATA2 5 29 DATAS 5 63 DATA2 6 30 DATAS 6 64 DATA2 7 31 DATAS 7 65 I O 2 32 I O 5 66 CLK2 33 CLK5 67 VXI Technology Inc 36 VM1548C Programming www vxitech com REGISTER ACCESS EXAMPLES Example 1 Example 2 The VM1548C module supports direct register access for very high speed data retrieval The register map is as specified in Table 3 2 As can be seen from the register map in Table 3 2 each 16 bit wide register is shared by two ports Therefore in order to program a particular port it must be ensured that the value of the other port is untouched This can be ensured by reading the value of the register and OR ing the obtained value with the value to be programmed This final value can then be written at the correct offset This is true assuming that the function used to write to the register performs 16 bit writes Similarly when a register is read it provides the data values of two ports Therefore the unwanted value must be OR ed with a proper mask This is again assuming that the function used to read the register performs 16 bit reads For example in order program Port 1 a First the register value at offset 0x20 is read Assume that the value read is as given below 1111000010101010 in binary format The lower 8 bits are the current value for Port 0 In order to maintain its val
31. ITGUI eret ere teur tomo tl e aen ade tror Be Interrupt Circuit bp Eden a egeat es Input Register Circuits E E E EE E Seni et Mate ese do eid oen aed ese Bi directional Clock Circuit APPEICATION BXAMPLEES e erede e pea eee PER E ModE EIE Modesto beant Write Redd Mod E teste tnit heben Pe ie REGISTER ACCESS EXAMPLES tease EXAMPLES hm eme a e d COMMAND DICTIONARY resist ve c ef ne ree eei e pepe er innere ert ences 45 Minos 45 Alphabetical Command Listing Terminology M HH 46 Command Diction ry ear ard bio E b mat pbtnaterstied 50 IEEE 488 2 COMMON COMMANDS 1 tace n p NR E 51 VM1548C Preface 3 VXI Technology Inc OP 55 ener 56 eR eae eee ee ne 57 SS SRE ee 58 EAE 59 WAM suk Ld I AM M ILU CREMA Riu LE E AN 60 INSTRUMENT SPECIFIC SCPI COMMANDS egina iiia aei a ae Eia ie nE EE EEO EE E EEE EEEE E Ea ania 6l EORMat decem E va EA ome atem esp
32. O port Timing to front panel and D8 D15 Control READ port CLKIN port 120 PORTENA T LL 100p VMIP 5 Bus TINENA Port Address 0 1 2 Decoder Trigger TINSELO 1 2 Select CLKIN lt port gt Input Data Buffers ports 3 4 5 Data Bus Data Bus FIGURE 3 2 READ MODE USING TTL TRIGGER IN VM1548C Programming 31 VXI Technology Inc The OUTP CLOC ENAB lt port gt ON command configures the front panel clock connection to the output mode This allows the VM1548C to drive these lines clocking the UUT The timing and control circuitry generates the IN OUT lt port gt signal to the I O data and word buffers configuring them as inputs when the SOUR DATA ENAB lt port gt 1 commands are received The INP REG SOUR lt port gt TTLT commands select the VXI TTL trigger in as the clock input for the trigger method to input data from the UUT This clock is transmitted from the front panel connectors clocking the data out of the UUT When the commands are received the VM1548C timing and control circuitry will generate the PORTENA signal to the port decoder The port decoder then clocks the write clock enable latch selecting the CLKINENA The CLKINENA signals are applied to the I O data and word buffers enabling the input clock line The INP REG POL lt port gt INV command causes the timing and control circuitry to select the falling edge of the TTL trigger in as the CLKIN lt port gt for th
33. READ signal to the previously enabled I O Word Buffer thus latching the data The Timing and Control FPGA generates the DOE signal to the Read Write Data Buffer This allows the input data from the UUT to be available on the VXI data bus Note that data inputs to the module do not contain pull up or down biasing resistors If the user does not provide active or passive biasing of the data inputs a read of the port may result in either a 1 or 0 being read from the data inputs 104 VM1548C Theory Of Operation www vxitech com INDEX B erri ieri 21 backplane jUmpetrs 17 Bi directional Clock Circuit eese 27 C CEROS m 23 46 clock circuit 427 clock signal 27 Clocked Mode eerte eee Rn REESE 46 command strings tee ere eto e tee ee 28 connector COONS D Device transfers ier eee eene eee Device triggering direct registet ACCESS 11 F FORMAE eese uoo ead 48 61 75 80 82 Front panel eR ERES ROI estan 12 I IEEE 488 2 commands 45 IEEE 488 2 Common Commands IMMEDIATE eerte input clock INPut REGister POLarity INPut REGister SOURce INPut TTL Trig s INPut TTL Trig STATS ett eet ree Ins
34. ROR SETTING REGISTER Trigger the input port using the IMMEDIATE pulse status vtvm1548 triggerSeqImmediate instrHndl if status VI SUCCESS return 5 tatus Read the 8 bit data from a specified input port status vtvm1548 readInstrument instrHndl portNumber data if status VI SUCCESS return status return VI SUCCI VM1548C Programming 43 VXI Technology Inc 44 VM1548C Programming www vxitech com SECTION 4 COMMAND DICTIONARY INTRODUCTION This section presents the instrument command set It begins with an alphabetical list of all the commands supported by the VM1548C divided into three sections IEEE 488 2 commands the instrument specific SCPI commands and the required SCPI commands With each command is a brief description of its function whether the command s value is affected by the RST command and its reset value The remainder of this section is devoted to describing each command one per page in detail The description is presented in a regular and orthogonal way assisting the user in the use of each command Every command entry describes the exact command and query syntax the use and range of parameters and a complete description of the command s purpose ALPHABETICAL COMMAND LISTING The following tables provide an alphabetical listing of each command supported by the VM1548C along with a brief description
35. STATus QUEStionable EVENt Query Parameters None Query Response 0 no over current condition 1 over current condition Description The Questionable Status Event Register query indicates if there is an over current condition Note Reading the Event Register clears the bit Examples Command Query Response Description STAT QUES 0 Related Commands None VM1548C Command Dictionary VXI Technology Inc SYSTem ERRor Purpose Queries the Error Queue Type Required SCPI command Command Syntax None query only S O IE N A RST Value N A Query Syntax SYSTem ERRor Query Parameters None Query Response ASCII string Description The System Error query is used to retrieve error messages from the error queue The error queue will maintain the two error messages If additional errors occur the queue will overflow and the second and subsequent error messages will be lost In the case of an overflow an overflow message will replace the second error message See the SCPI standard Volume 2 Command Reference for details on errors and reporting them Refer to the Error Messages section of this manual for specific details regarding the reported errors Examples Command Query Response Description SYST ERR 350 Queue overflow Related Commands None 94 VM1548C Command Dictionary www vxitech com
36. TATus QUEStionable EVENt 93 syntax 4 21 SYSTem ERROI aee SEINEN I Se HERES 94 SYSTem VERSiOn iisienacdis eiecit bester ine 95 T timing atid COME ee pee 24 Transparent Mode key WOEGQ ese CR P REIHE RR EHE 21 22 tree structured language 5 86 L 25 26 27 46 63 68 70 71 83 30 logical address 17 18 TTLTRIG M cheat 23 46 message Based BARRERA tee RS 21 VM1548C Index 105 V 11 12 30 97 98 102 104 ANXIE a esce t decens 11 30 32 38 97 98 100 103 104 VXI message based interface sss 13 Abb TTE 21 W WEEE en B WEE GR FERRE ERES 8 Write mode iu RESET PER NER CO EVER EORR ONE 28 Write read mode tv e a 33 VXI Technology Inc 106 VM1548 Index
37. TTLTrig Purpose To select a specific VXIbus trigger line as TRIGOUT Type Setting Command Syntax OUTPut TTLTrig n lt n gt 0 1 2 3 4 5 6 7 RST Value 0 Query Syntax OUTPut TTLTrig Query Parameters N A Query Response 0 1 2 3 4 5 Description The Output TTLTrig command controls which of the 8 VXI trigger lines will be configured as TRIGOUT Examples Command Query OUTP TTLT 0 OUTP TTLT Related Commands OUTPut TTLTrig STATE lt boolean gt OUTPut TTLTrig SOURce source VM1548C Command Dictionary 71 VXI Technology Inc OUTPut TTLTrig POLarity Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands To control the polarity of the TTL TRIGGER signal Setting OUTPut TTLTrig POLarity edge lt edge gt NORMal INVert NORMal OUTPut TTLTrig POLarity None NORM INV The Output TTLTrig polarity command controls the polarity of the TTL TRIGGER signal driving the VXI trigger line When polarity is NORMal the selected VXIbus trigger line will provide a rising edge trigger When polarity is INVerted the selected V XIbus trigger line will provide a falling edge trigger Note It is important to remember that the output TILT Source should be one of the six
38. a 01 to port 0 s I O data buffer Writes data 23 to port 8 I O data buffer Writes data 45 to port 2 s I O data buffer Set the interrupt trigger source as the port 5 clock Set the interrupt trigger source to the positive edge Generates a word serial event to transfer data and clocks from ports 0 1 and 2 Read data from port 3 Read data from port 4 Read data from port 5 See Figure 3 3 for the Write read block diagram VM1548C Programming 33 VXI Technology Inc TRIGINO 7 Trigger In Mux O VCC 47K 22 CLKfrm front panel 120 WRITEO Control Lines vOtrom Timing IN OUT port 100pF front panel and m Control READ port CLKIN lt port gt 200K PORTENA TINENA lt Bus Trigger Select ok L P 2 Address 0 1 2 PORT2 OUTENAQ Port gt Decoder Direction CLKOUT lt port gt x Control IN OUT lt gt vo l Data CLKOUTENAO Mad Write ports 22 Read Clock 0 1 2 E Write Enable WRITEO 71 Data Buffer Data Bus Data Bus CLKIN lt gt 5 IN OUT lt port gt iG READ lt port gt Data READ Buffers 22 VO Data Bus ports 2 Word 3 45 Data Bus Buffer FIGURE 3 3 WRITE READ The INP REG SOUR lt port gt EXT commands select the external clock for lt port gt as the clock
39. anual this manual All components should be immediately inspected for damage upon receipt of the unit Once the VM1548C is assessed to be in good condition it may be installed into an appropriate C size or D size VXIbus chassis in any slot other than slot 0 The chassis should be checked to ensure that it is capable of providing adequate power and cooling for the VM1548C Once the chassis is found to be adequate the VM1548C s logical address and the chassis backplane jumpers should be configured prior to the VM1548C s installation CALCULATING SYSTEM POWER AND COOLING REQUIREMENTS The power and cooling requirements of the VM4018 are given in the Specifications section of Section 1 in this manual It is imperative that the chassis provide adequate power and cooling for this module Referring to the chassis User s Manual confirm that the power budget for the system the chassis and all modules installed therein is not exceeded and that the cooling system can provide adequate airflow at the specified backpressure It should be noted that if the chassis cannot provide adequate power to the module the instrument might not perform to specification or possibly not operate at all In addition if adequate cooling is not provided the reliability of the instrument will be jeopardized and permanent damage may occur Damage found to have occurred due to inadequate cooling will void the warranty on the instrument in question SETTING THE CHASSIS
40. ata an dean a 81 SOURcGe DATA POLarity 1 ne eate te eg a ite e D bte re tp eder ete be e enero den 82 STATus INTerrupt ENABle tete tdt EU E t Heg Ferte e 83 STATus INTerrupt NTRansItiOn nre e EG Te DEO paa aaa E AE LEHRER REOR IRR RES 84 STATu s INTerr pt PTRansItlOn i icit recte rhet eite edet pec eot e i et 85 5 elected pb RR E REI PHI EM ED e en rep aerias 86 SCPI REQUIRED COMMANDS ensue eee Ev Vie aee eR ENT Vue ur e 87 SPAT Us OPERA ON use 87 STATus OPERation CONDition 88 STAT s OPBRation ENABle ee rero e er ee tm RR aban eR PE RET ae 89 STATuS PRESet EA aub eee eati et e laci tur ide enata Aan 90 STATus QOUBStonable CONDUtIOD ete e ec e eta t e Ui RO idee e 91 S TATus QUEStionable ENABle ir er rede e RE 92 STATus QUEStionable EVENt ccscccsssecssscessecsssecesscessaecesseecaecessecsesseseseecsascscsessaecsecsesaees sssecsaecsesseesaeenses 93 SYSTem ERROrF eic eee hee tete tede euet eie dece ede Se eee e landed 94 SYSTem VERSIOnDT E AE mete 95 SECTIONS ssssssssesssscssesssosecdansdoanesvosesseaxesveseonsoesscevhsecotsnesenscevensssestebtocdevedes
41. ay of synchronizing the module with its commander Examples Command Query Response Description Related Commands WAI OPC 60 VM1548C Command Dictionary www vxitech com INSTRUMENT SPECIFIC SCPI COMMANDS FORMat Purpose Sets the output format for digital queries Type Setting Command Syntax FORMat lt type gt HNN type ASCii HEXadecimal OCTal BINary RST Value ASCii Query Syntax FORMat Query Parameters None Query Response ASC HEX OCT BIN Description The Format command sets the form of returned data from the instrument This command applies only to the SOURce DATA and READ commands ASCii Specifies numbers expressed in decimal Leading zeros are suppressed HEXadecimal Expresses numbers in a 2 digit leading 0 alphanumeric format Numbers A F are in capitals OCTal Expresses numbers in a 3 digit leading 0 format BINary Expresses numbers in an 8 digit leading 0 format Examples Command Quer ASC Response Description DATA 0 58 DATA 0 58 HEX DATA 0 H3A OCT DATA 0 0072 FORM BIN FORM SOUR 0 B00111010 Related Commands SOURce DATA lt port gt READ lt port gt VM1548C Command Dictionary 61 VXI Technology Inc INPut REGister POLarity Purpose Selects the active clock edge of the input regis
42. consists of a 120 Q resistor in series with a 100 pF capacitor giving a time constant of 12 ns The VM1548C can be combined with any member of the VMIP family to form a customized and highly integrated instrument PROGRAMMING AND DATA ACCESS The data may be read or loaded by one of two different methods Word Serial Message based Data Access this mode the input or output data and all other functions are accessed via the VXI message based interface Commands are sent to set the I O ports as well as to initiate functions such as triggering an update or to query a port s input state This data access method is very clean from a programming perspective but it is also the slowest of the data access modes Register Based Data Access This mode offers the fastest throughput The I O ports are directly mapped into the VXI user definable registers Data access occurs in approximately 500 ns depending on the controller and software used VM1548C Introduction 13 VXI Technology Inc FRONT PANEL DATA VO yo DAMPING RESISTOR VMIP BUS OUTENA CLK OUT SEL TTL TIGGER 0 7 8 1 SELECT VXI BACKPLANE CLKOUTENA TTL TRIG OUT SEL FIGURE 1 3 VM1548C MODULE BLOCK DIAGRAM VM1548C Introduction www vxitech com VM1548 SPECIFICATIONS NUMBER OF CHANNELS VM1548C 1 48 6 groups of 8 bits VM1548C 2 96 12 groups of 8 bits VM1548C 3 144 18 group
43. e I O data buffers When INP TTLT STATE ON command is received the VM1548C timing and control circuitry generates the PORTENA signal to the port decoder This clocks the trigger select latch selecting the TINENA line The TINENA signal enables the trigger in mux INP TTLT 1 notifies the timing and control circuitry to select TTL trigger for the clock source The port decoder is again enabled to clock the trigger select latch selecting the TINSEL signals These signals are routed to the trigger in mux that enables TTL trigger 1 to be routed to the timing and control circuitry for clocking the UUT and the I O data buffers The normal polarity of the trigger is sent to the UUT and the inverted version is used for the I O data buffers The STAT INT ENAB command uses the default value of NONE ground to generate the status interrupt onto the VXI backplane and the STAT INT PTR ON command set the polarity of the interrupt When the TTL trigger 1 occurs the VM1548C will send a high going pulse to clock data out of the UUT The falling edge of this pulse is used to latch the data into the VM1548C s data buffers The VM1548C sends an Interrupt Request IRQ informing the slot 0 controller via the VMIP that the transfer has occurred and that the data in the I O data buffers is now available The READ lt port gt command causes the timing and control circuitry to generate two READ signals The first READ signal is routed to the I O word buffers thereb
44. e signifies a high or low on each 6 line grouping Each 6 line grouping corresponds with one hardware driver chip An over current condition occurs when the combined current through the six lines goes over 1 8 A If over current is detected a high for moe than 80 ms the drive is removed or disabled from all six lines Each group of six lines is associated with one or two ports as follows DRIVERS Over Current Lines Sense Lines 8 ea Port 6 ea Bit SS porto PORT 1 Examples Command Query Response Description EN READ ISE 0 Related Commands RESet ISENse STB 78 VM1548C Command Dictionary www vxitech com RESet ISENse Purpose Resets drive disable of a group of six lines Type Event Command Syntax RESet ISENse lt bits gt ODE lt bits gt to 255 decimal RST Value N A Query Syntax N A Query Parameters N A Query Response N A Description The Reset ISense command resets drive disable in a group of six lines after an over current condition is cleared Each bit corresponds to a group of six lines It wold be most common just to reset all the lines at once by entering 255 See READ ISENse for more information Examples Command Query Response Description RES ISEN 255 Resets all the 6 line groups Related Commands READ ISENse STB VM1548C Command Dictionary 79 VXI Technology Inc
45. ear on the product ATTENTION Important safety instructions Frame or chassis ground placed in accordance with EN 50419 Marking of electrical and electronic equipment in accordance with Article 11 2 of Directive 2002 96 EC WEEE End of life product can be returned to VTI by obtaining an RMA number Fees for take back and recycling will apply if not prohibited by national law Indicates that the product was manufactured after August 13 2005 This mark is Eni Follow these precautions to avoid injury or damage to the product Use Proper Power Cord To avoid hazard only use the power cord specified for this product Use Proper Power Source To avoid electrical overload electric shock or fire hazard do not use a power source that applies other than the specified voltage Use Proper Fuse To avoid fire hazard only use the type and rating fuse specified for this product VM1548C Preface www vxitech com WARNINGS CONT Avoid Electric Shock Ground the Product Operating Conditions Improper Use To avoid electric shock or fire hazard do not operate this product with the covers removed Do not connect or disconnect any cable probes test leads etc while they are connected to a voltage source Remove all power and unplug unit before performing any service Service should only be performed by qualified personnel This product is grounded through the grounding conductor of the power cord To avoid elect
46. ent to occur IEEE 488 2 Common Command TRG None N A None N A N A Command Query TRG This command generates a short pulse or a word serial event for the trigger signal Response Description See TRIGger SEQuence IMMediate 58 VM1548C Command Dictionary www vxitech com TST Purpose Causes a self test procedure to occur and queries the results Type IEEE 488 2 Common Command Command Syntax None query only OHNE BV eae N A RST Value N A Query Syntax TST Query Parameters None Query Response Numeric value Description The Self Test query causes the VM1548C to run its self test procedures and report on the results Examples Command Query Response Description TST 0 Related Commands None VM1548C Command Dictionary 59 VXI Technology Inc WAI Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Halts execution of commands and queries until the No Operation Pending message is true IEEE 488 2 Common Command WAI None N A None N A N A The Wait to Continue command halts the execution of commands and queries until the No Operation Pending message is true This command makes sure that all previous commands have been executed before proceeding It provides a w
47. fied port status vtvml548_sourceData instrHndl portNumber data if status lt VI_SUCCESS return vtvm1548 DATA OUT OF RANGE Trigger the output port using the IMMEDIATE pulse status vtvm1548 triggerSeqImmediate instrHndl if status VI SUCCESS return status return VI SUCCESS Function vtvm1548_setupAndReadData Formal Parameters ViSession instrHndl A valid session handle to the instrument Vilntl16 portNumber This parameter is used to specify the port which is to be configured as input Valid Values Interpretation vtvm1548 PORT ZERO Port Zero vtvm1548 PORT ONE Port One vtvm1548 PORT TWO Port Two vtvm1548 PORT THREE Port Three vtvm1548 PORT FOUR Port Four vtvm1548 PORT FIVE Port Five Vilntl16 clkSource This parameter is used to set the source of the clock circuit associated with the specified port Valid Values Interpretation vtvm1548 CLK SOURCE IMM Word Serial Event vtvm1548 CLK SOURCE TTLT VXIbus TRIGIN vtvm1548 CLK SOURCE GLOB TRIGOUT vtvm1548 CLK SOURCE NONE Ground VM1548C Programming 41 Return Values VXI Technology Inc ViBoolean polarity This parameter is used to set the polarity of the clock circuit associated with the specified port This parameter is considered only if the specified clock source is either vtvm1548 CLK SOURCE TTLT or vtvm1548
48. g specifications SAFETY EN61010 2001 EMC EN61326 1997 w A1 98 Class A CISPR 22 1997 Class A VCCI April 2000 Class A ICES 003 Class A ANSI C63 4 1992 AS NZS 3548 w A1 4 2 97 Class FCC Part 15 Subpart Class EN 61010 1 2001 The product was installed into a C size VXI mainframe chassis and tested in a typical configuration I hereby declare that the aforementioned product has been designed to be in compliance with the relevant sections of the specifications listed above as well as complying with all essential requirements of the Low Voltage Directive July 2007 c mn 2 i en Steve Mauga QA Manager VM1548C Preface 7 VXI Technology Inc GENERAL SAFETY INSTRUCTIONS Review the following safety precautions to avoid bodily injury and or damage to the product These precautions must be observed during all phases of operation or service of this product Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the product Service should only be performed by qualified personnel TERMS AND SYMBOLS WARNINGS These terms may appear in this manual WARNING Indicates that a procedure or condition may cause bodily injury or death CAUTION Indicates that a procedure or condition could possibly cause damage to equipment or loss of data These symbols may app
49. ger The following is an example of how to produce CLK2 as TTLTRIGA to the backplane OUTPut LTrig STATe O OUTPut TTLTrig POLarity NORMal OUTPut LTrig 4 OUTPut TTLTrig SOURce EXTERNAL2 If CLK2 is a logic low level then the following SCPI command would allow a logic high level on the backplane OUTPut TTLTrig POLarity INVERT TILTRIG 4 will not pull the line low Likewise continuing with this example the following command would produce a logic low level on the backplane OUTPut TTLTrig POLarity NORMal TTLTRIG 4 will pull the line low VM1548C Programming 23 INTERRUPT CIRCUIT VXI Technology Inc This section deals with the interrupt circuit The VM1548C has the capability to interrupt the slot 0 controller via the VMIP with either a high going edge or with a low going edge of the IRQ signal The timing and control circuitry can select one of the six EXTERNAL clocks GLOBAL TRIGOUT or NONE as the interrupt trigger The interrupt is selected and enabled using the following SCPI command STATus INTerrupt ENABle source Where source is EXTERNALO 5 GLOBAL or NONE The following SCPI command will trigger the status interrupt on a positive edge STATus INTerrupt PTRansition ON The following SCPI command will trigger the status interrupt on a negative edge STATus INTerrupt EXAMPLES NTRansition ON To use GLOBAL TRIGOUT out as the
50. gister layout is as follows Bit 0 Calibrating Bit 1 Setting Bit2 Ranging Bit 3 Sweeping Bit 4 Measuring Bit 5 Waiting for trigger Bit 6 Waiting for arm Bit 7 Correcting Examples Command Query STAT OPER ENAB 0 STAT OPER ENAB Related Commands None VM1548C Command Dictionary 89 VXI Technology Inc STATus PRESet Purpose Presets the Status Registers Type Required SCPI command Command Syntax STATus PRESet ee None RST Value N A Query Syntax None command only Query Parameters N A Query Response N A Description The Status Preset command enables the over current questionable event Examples Command Query Response Description STAT PRES Related Commands None 90 VM1548C Command Dictionary www vxitech com STATus QUEStionable C ONDition Purpose Queries the Questionable Status Condition Register Type Required SCPI command Command Syntax None query only S O IE N A RST Value N A Query Syntax STATus QUEStionable CONDition Query Parameters None Query Response 0 no over current condition 1 over current condition Description The Questionable Status Condition Register query returns one bit that indicates what the over current sense condition is 1 signifies there is over current condition a 0 signifies that there is no over current condi
51. h group from Front Panel clock input VXI TTL Trigger lines or word serial event command e Capture clock edge programmable as rising edge or falling edge e ASCII Hex Octal and Binary data output types e Message or Register based data access SCPI compatible FIGURE 1 2 FRONT PANEL LAYOUT VM1548C Introduction www vxitech com DESCRIPTION The VM1548C Open Collector Digital I O module is a high performance I O module that has been designed for high voltage current and data throughput The instrument uses the message based word serial interface for programming and data movement as well as allowing direct register access for very high speed The VM1548C provide 48 open collector digital I O line that are configurable as input or output in six groups of eight channels each The module can drive up to 60 V with sink current of up to 300 mA per channel Each group of 8 bits can be configured as an input or an output under program control The VM1548C has the flexibility to source the input and output clocks from either the front panel one input per group of 8 bits the backplane TTL Trigger bus or via a word serial command By using the appropriate clocking sources very large numbers of channels may by synchronized to collect or present data to a UUT unit under test Each clock input is internally pulled to a logic high level and has a RC termination network to reduce multiple clocking due to line ringing The RC network
52. he output clock signal is controlled with the following SCPI command OUTPut CLOCk POLarity edge Where edge is NORMAL or INVERT EXAMPLES To drive TRIGIN out as CLKI on the external connector the following SCPI commands would be issued OUTPut CLOCk ENABle 1 ON OUTPut CLOCk SOURce TTLTRIG To drive TRIGOUT out as CLK3 on the external connector the following SCPI commands would be issued OUTPut CLOCk ENABle 3 ON OUTPut CLOCk SOURce GLOBAL To drive IMMEDIATE out as CLKS on the external connector the following SCPI commands would be issued OUTPut CLOCk ENABle 5 ON OUTPut CLOCk SOURce IMMEDIATE To select no clock the NONE parameter is used This will always be a logic level low OUTPut CLOCk ENABle 5 ON OUTPut CLOCk SOURce NONE VM1548C Programming 27 VXI Technology Inc APPLICATION EXAMPLES WRITE MODE This section contains examples of using SCPI command strings for programming the VM1548C module The code is functional and will contain a brief description and block diagram of the operation In this example the VM1548C will be set up prior to receiving the UUT generated clock edge The VM1548C will output one 1 16 bit binary word to the UUT from ports 0 and 1 COMMANDS DESCRIPTION OUTP CLOC ENAB 0 0 Disables port 0 clock from driving front pane
53. input for the trigger method to input data from the UUT When the commands are received the VM1548C timing and control circuitry will generate the PORTENA signal to the port decoder The port decoder then clocks the write clock enable latch selecting the CLKINENA The CLKINENA signals are applied to the I O data and word buffers enabling the input clock line The INP REG POL lt port gt INV command causes the timing and control circuitry to select the falling edge of the external clock as the CLKIN lt port gt for the I O data buffers 34 VM1548C Programming www vxitech com OUTP CLOC ENAB lt port gt ON commands inform the timing and control circuitry that the front panel clock lines are used as outputs This allows the VM1548C to furnish the clock source OUTP CLOC SOUR lt port gt IMM commands inform the timing and control circuitry to drive the front panel clock lines using the immediate word serial event trigger The OUTP REG SOUR lt port gt IMM commands select the immediate word serial event clock as the trigger method for the selected ports to output data to UUT VM1548C through wrap around cable When these commands are received the VM1548C timing and control circuitry will generate the PORTENA signal to the port decoder The port decoder then clocks the write clock enable latch selecting the CLKOUTENA The CLKOUTENA signals are applied to the I O data and word buffers enabling the output clock line The SOUR DATA ENAB lt
54. l connector and enables this line as the clock input to port 0 OUTP CLOC ENAB 1 0 Same as previous command except for port 1 OUTP REG SOUR 0 EX Selects port 0 input clock CLKO as method of triggering OUTP REG SOUR 1 EX Same as previous command except for port 1 SOUR DATA ENAB 0 1 Selects and enables port 0 to write data to the UUT STAT I ENAB EXTO Set the interrupt trigger source as the port 0 clock STAT INT PTR O Set the interrupt trigger source to the positive edge SOUR DATA 0 48 Writes 48 data to port 0 for subsequent transfer to the UUT SOUR DATA ENAB 1 1 Selects and enables port I to write data to the UUT SOUR DATA 1 15 Writes 15 data to port 1 for subsequent transfer to the UUT Figure 3 1 and the description that follows illustrates the function of each of the commands above 28 VM1548C Programming www vxitech com CLK from front panel from front panel Control Lines 200K PORT2 Port piace Irection Address 0 1 2 Decoder D amp Dt5 Control Bus 9 5 IN OUT lt port gt CLKOUTENA Output Data Write Buffer Read Clock Write Enable Data VO Buffer Word Data Bus Buffer Data Bus ISENSE FIGURE 3 1 OUTPUT BLOCK DIAGRAM OUTP CLOC ENAB 0 0 and OUTP CLOC ENAB 1 0 commands inform the timing and control circuitry that the front panel clock lines are used as inputs This allows the UUT to furnish the clock source when read
55. l straight P N 749204 2 Backshell angled at 75 Circuit Assembly P N CA 68NDP 12GT Connector P N CA 68NDBS 1M Backshell P N DG01 Catalog covering this series of connectors The pin locations for J200 J201 and J202 are shown in Figure 2 2 PIN 1 BBHBHHHBHHBHHHHEHBHHBHHHHHBHBHHERBRHGR PIN 34 PIN 68 FIGURE 2 2 J200 J201 AND J202 PIN LOCATIONS 20 VM1548C Preparation for Use www vxitech com SECTION 3 PROGRAMMING INTRODUCTION The 1548 is a VXIbus message based device whose command set is compliant with the Standard Command for Programmable Instruments SCPI programming language All module commands are sent over the VXIbus backplane to the module Commands may be in upper lower or mixed case All numbers are sent in ASCII decimal unless otherwise noted The module recognizes SCPI commands SCPI is a tree structured language based on IEEE STD 488 2 Specifications It utilizes the IEEE STD 488 2 Standard command and the device dependent commands are structured to allow multiple branches off the same trunk to be used without repeating the trunk To use this facility terminate each branch with a semicolon See the Standard Command for Programmable Instruments SCPI Manual Volume 1 Syntax amp Style Section 6 for more information The SCPI commands are listed in upper and lower case Character case is used t
56. lane Type Setting Command Syntax STATus INTerrupt ENABle source ODE source EXTernal n GLOBal NONE RST Value NONE Query Syntax STATus INTerrupt ENA Ble Query Parameters N A Query Response EXT lt n gt GLOB NONE Description The Status Interrupt enable command selects a source for the interrupt trigger Source Parameter Description EXT 0 5 This selects 1 of 6 external clocks See the clock circuit description GLOB This selects TRIGOUT as the interrupt trigger See TTLTRIG diagram NONE This parameter will select GROUND as the interrupt trigger source thus providing a logic level low Examples Command Query STAT INT ENAB EXT3 STAT INT ENAB Related Commands STATus INTerrupt PTRansition lt boolean gt STATus INTerrupt NTRansition boolean VM1548C Command Dictionary 83 VXI Technology Inc STATus INTerrupt NTRansition Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands Sets the transition on which the interrupt trigger will occur Setting STATus INTerrupt NTRansition lt boolean gt boolean 0 1 OFF ON OFF STATus INTerrupt NTRransition N A boolean 011 OFF ON The Status Interrupt NTRansition set
57. lected signal is called TRIGIN Examples Command Query INP TTLT 0 INP TTLT Related Commands INPut TTLTrig STATe lt boolean gt 64 VM1548C Command Dictionary www vxitech com INPut TTLTrig S TATE Purpose To enable or disable the multiplexer that controls the selection of the VXI bus trigger line as TRIGIN Type Setting Command Syntax INPut TTLTrig STATE boolean boolean 0 1 OFF ON RST Value 0 Query Syntax INPut TTLTrig STATE Query Parameters N A Query Response 011 Description The Input TTLTrig state command enables or disables the multiplexer allowing the selection of a specific VXI trigger line as TRIGIN Examples Command Query INP TTLT STAT 0 INP TTLT STAT Related Commands INPut TTLTrig n VM1548C Command Dictionary 65 VXI Technology Inc OUTPut CLOCk ENABle Purpose Sets the direction in which the port s associated external clock line is driven Type Setting Command Syntax OUTPut CLOCK ENABle port gt lt boolean gt port 0 1 2 3 4 5 boolean 01 1 OFF ON RST Value 0 Query Syntax OUTPut CLOCK ENABle port gt Query Parameters port gt 20 1 2 3 4 5 Query Response 011 Description The output clock enable command determines which direction the associated p
58. lete bit is set when it receives an OPC command The Query Error bit is set when data is over written in the output queue This could occur if one query is followed by another without reading the data from the first query The Execution Error bit is set when an execution error is detected See the section in the manual covering Error Messages for a list of execution errors Errors that range from 200 to 299 are execution errors The Command Error bit is set when a command error is detected See the section in this manual covering Error Messages for a list of command errors Errors that range from 100 to 199 are command errors The Power On bit is set when the module is first powered on or after it receives a reset via the VXI Control Register Once the bit is cleared by executing the ESR command it will remain cleared Command Quer Response Description ESR 4 ESE mask VM1548C Command Dictionary 53 VXI Technology Inc IDN Purpose Queries the module for its identification string Type IEEE 488 2 Common Command Command Syntax None query only S O IE N A RST Value N A Query Syntax IDN Query Parameters None Query Response ASCII character string Description The Identification query returns the identification string of the VM1548C module The response is divided into four fields separated by commas The first field is the
59. llowing SCPI commands will clock the number 205 out of port 5 using the IMMEDIATE pulse SOURCe DATA ENABle 5 ON OUTPut REGister SOURce 5 IMMEDIATE SOURCe DATA 5 205 TRIGger SEQuence IMMediat This provides a rising edge clock The following is an example of writing to a port operating in transparent mode This method requires no clock edge for the data to be presented on the external connector SOURCe DATA ENABle 5 ON OUTPut REGister SOURce 5 NONE SOURCe DATA 5 205 205 Immediately appears on the External Connector The following example selects the external CLK5 line to clock the data port In this example it is assumed the external CLKS5 signal is a steady logic low and the clock edge is produced by toggling the clock polarity SOURCe DATA ENABle 5 ON OUTPut REGister SOURce 5 EXTERNAL OUTPut REGister POLarity 5 NORMAL SOURCe DATA 5 205 OUTPut REGister POLarity 5 INVERT This provides a rising edge clock VM1548C Programming 25 VXI Technology Inc INPUT REGISTER CIRCUIT This section refers to the bi directional port when configured as an input The SCPI command used to configure a port as an input is SOURce DATA ENABle lt port gt OFF The port is programmable to allow the data to be transparent or clocked If the port is clocked there are several choices for the clock source The method for selecting clocked mode and the so
60. m the UUT the I O data buffers latch the data word from the I O word buffer The data on the I O data buffer s outputs are now available to the UUT The STAT INT ENAB EXT 0 and STAT INT PTR ON commands enable the interrupt to occur when the CLK 0 signal is received and sets the polarity of this interrupt to the positive edge The VM1548C module sends an Interrupt Request IRQ informing the slot 0 controller that the transfer has occurred READ MODE In this example the VM1548C will be configured to clock the UUT and read 24 bits of data when the TTL Trigger line 1 is activated The TTL Trigger is assumed to be pulled by another instrument used during this test The UUT will output data on the rising edge of the received clock that is generated from the VM1548C VM1548C will capture or read data on the falling edge of this same clock When the VM1548C detects a TTL Trigger 1 the front panel clock lines to the UUT are activated The clock is sent the UUT transmits data on the rising edge and the data will be latched into the VM1548C on the falling edge An Interrupt Request is generated informing the slot 0 controller via the VMIP that data is ready to be read COMMANDS DESCRIPTION OUTP CLOC ENAB 3 ON Enables port 3 clock to drive the front panel connector OUTP CLOC ENAB 4 ON Same as previous command except for por
61. manufacturer s name the second field is the model number the third field is an optional serial number and the fourth field is the firmware revision number If a serial number is not supplied the third field is set to 0 zero Examples Command Query Response Description VXI Technology Inc VM1548C 0 1 01 The revision listed here is for reference only the response will always be the current revision of the instrument Related Commands 54 VM1548C Command Dictionary www vxitech com OPC Purpose Sets the OPC bit in the Event Status Register Type IEEE 488 2 Common Command Command Syntax OPC tenes None RST Value N A Query Syntax OPC Query Parameters None Query Response 1 Description The Operation Complete command sets the OPC bit in the Event Status Register when all pending operations have completed The Operation Complete query will return a to the output queue when all pending operations have completed Examples Command Query Related Commands VM1548C Command Dictionary 55 VXI Technology Inc RST Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands Resets the module s hardware and software to a known state IEEE 488 2 Common Command RST None N A None
62. mmand Dictionary 73 VXI Technology Inc OUTPut TTLTrig STATE Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands To enable or disable the TTL TRIGGER driving the VXIbus trigger lines Setting OUTPut TTLTrig STATE lt boolean gt boolean 011 OFF ON 0 OUTPut TTLTrig STATE N A 011 The Output TTLTrig State command enables disables the selected trigger line driven by the TTL TRIGGER onto the VXIbus Command Query OUTP TTLT STAT OFF OUTP STILLT STAT Response Description OUTPut TTLTrig lt n gt OUTPut TTLTrig SOURce lt source gt 74 VM1548C Command Dictionary www vxitech com READ Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands To obtain an 8 bit value from one of the input ports Query None query only N A N A READ lt port gt port gt 0 1 2 3 4 5 Numeric ASCII value from 0 to 255 The Read command will fetch data from the specified input port By definition this command is a query and will respond with the value read from the data register The format of the returned data is set with the FORMat command This command require
63. mplete Bit 1 Request Control not used in the VM1548C Bit 2 Query Error Bit 3 Device Dependent Error not used in the VM1548C Bit 4 Execution Error Bit 5 Command Error Bit 6 User Request not used in the VM1548C Bit 7 Power On The Event Status Enable query reports the current contents of the Event Status Enable Register Examples Command Query Response Description ESE 36 ESE 36 Related Commands ESR 52 VM1548C Command Dictionary www vxitech com ESR Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands Queries and clears the Standard Event Status Register 488 2 Common Command None Query only N A N A ESR None Numeric ASCII value from 0 to 255 The Event Status Register query queries and clears the contents of the Standard Event Status Register This register is used in conjunction with the ESE register to generate the ESB Event Status Bit in the Status Byte The layout of the ESR is Bit 0 Operation Complete Bit 1 Request Control not used in the VM1548C always 0 Bit 2 Query Error Bit 3 Device Dependent Error not used in the VM1548C always 0 Bit 4 Execution Error Bit 5 Command Error Bit 6 User Request not used in the VM1548C always 0 Bit 7 Power On The Operation Comp
64. neteobacssentsvbdesvntessees 97 THEORY OF OPERATION ERROR ROO ERREUR RAE E FU A et eer ERRORS 97 Hia POP 97 VXEINTERFEXCE 98 Device Transfers Write Mode asus aman tan a ete 98 Direction suere d e AERE rte te rua ai oo en ein are RE 98 Glock Brable Gp PEE Eme mie 98 Data 99 Device Triggering TTL Input Trigger ee aeee Tee ea enk nennen nennen nennen enne e e eA EEE SEES eka 100 n e raa ie ile ace Se Sd 100 Trigser Select aaa ee ae al at aie ei ae ia 100 Device Transfers Read Mode teet ee rt EORR E RENE PE EE ERE EER e SERES 102 aede aiat AE E Mur ce sehn E EL ER 102 4 VM1548C Preface www vxitech com 102 Latch Data 2 UR 104 VM1548C Preface 5 VXI Technology Inc CERTIFICATION VXI Technology Inc VTD certifies that this product met its published specifications at the time of shipment from the factory VTI further certifies that its calibration measurements are traceable to the United States National Institute
65. nt in the center position will automatically be set to the switch set address plus one while the third instrument the instrument in the lowest position will automatically be set to the switch set address plus two If dynamic address configuration is desired the address switch should be set for a value of 255 All switches set to ON Upon power up the slot 0 resource manager will assign the first available logical addresses to each instrument in the VMIP module If dynamic address configuration is desired the address switch should be set for a value of 255 Upon power up the slot 0 resource manager will assign logical addresses to each instrument in the VMIP module VM1548C Preparation for Use www vxitech com FRONT PANEL INTERFACE WIRING The VM1548C s module interface is made available on the front panel of the instrument The 48 channel version VM1548C 1 will have J201 which contains all signals for this instrument The 96 channel version VM1548C 2 will have J201 and J202 provided while the 144 channel version VM1548C 3 will have J200 J201 and J202 The wiring for each of these connectors is identical and since each group of 48 channels is treated as a separate instrument the module will have three Channel 1s three Channel 2s three Channel 3s etc The connector used in the VM1548C is a readily available 68 pin high density type commonly known as a 68 pin version of the SCSI 2 connector The mating connector is an IDC
66. ntal specifications for the product or improper site preparation or maintenance VXI Technology Inc shall not be liable for injury to property other than the goods themselves Other than the limited warranty stated above VXI Technology Inc makes no other warranties express or implied with respect to the quality of product beyond the description of the goods on the face of the contract VTI specifically disclaims the implied warranties of merchantability and fitness for a particular purpose RESTRICTED RIGHTS LEGEND Use duplication or disclosure by the Government is subject to restrictions as set forth in subdivision b 3 ii of the Rights in Technical Data and Computer Software clause in DFARS 252 227 7013 VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 U S A 6 VM1548C Preface www vxitech com DECLARATION OF CONFORMITY Declaration of Conformity According to ISO IEC Guide 22 and EN 45014 MANUFACTURER S NAME VXI Technology Inc MANUFACTURER S ADDRESS 2031 Main Street Irvine California 92614 6509 PRODUCT NAME TTL I O Module MODEL NUMBER S 1548 PRODUCT OPTIONS All PRODUCT CONFIGURATIONS All VXI Technology Inc declares that the aforementioned product conforms to the requirements of the Low Voltage Directive 73 23 EEC and the EMC Directive 89 366 EEC inclusive 93 68 EEC and carries the CE mark accordingly The product has been designed and manufactured according to the followin
67. ntrol polarity Examples Command Query OUTP CLOC POL 0 NORM OUTP CLOC POL 0 NORM Related Commands OUTPut CLOCK ENABle port boolean OUTPut CLOCk SOURce port source VM1548C Command Dictionary 67 VXI Technology Inc OUTPut CLOCk SOURce Purpose To select a signal to be used as the source for the output clock appearing on the 68 pin external connector Type Setting Command Syntax OUTPut CLOCk SOURce port source lt port gt 0 1 2 3 4 5 source NONE TTLT IMM GLOB RST Value NONE Query Syntax OUTPut CLOCK S OURce port gt Query Parameters port gt 0 1 2 3 4 5 Query Response NONE TTLT IMM GLOB Description The output clock source command selects a signal to be used as the source for the output clock appearing on the 68 pin external connector Source Parameter Description NONE This parameter will select GROUND as the clock source TTLTrig This selects the VXIbus TRIGIN as the clock source TRIGIN be 1 of 8 trigger lines on the VXI bus See INPut TTLTrig IMMediate This selects the Word Serial Event as the clock source See TRIGger SEQuence MMediate GLOBal This selects TRIGOUT as the clock source See OUTPut TTLTrig SOURce Examples Command Query Response Description OUTP CLOC SOUR 0 TTLT OUTP CLOC SOUR 0 TTLT Related Commands OUTPut CLOCK ENABle port
68. o indicate different forms of the same command Keywords can have both a short form and a long form some commands only have one form The short form uses just the keyword characters in uppercase The long form uses the keyword characters in uppercase plus the keyword characters in lowercase Either form is acceptable Note that there are no intermediate forms All characters of the short form or all characters of the long form must be used Short forms and long forms may be freely intermixed The actual commands sent can be in upper case lower case or mixed case case is only used to distinguish short and long form for the user As an example these commands are all correct and all have the same effect TRIGger SEQuence IMMediate trigger sequence immediate RIGGER SEQUENCE IMMEDIATE RIG SEQuence IMMediate RIG SEQ IMMediate RIG SEQ IMM trig seq IMM trig seq imm VM1548C Preparation for Use 21 NOTATION VXI Technology Inc The following command is not correct because it uses part of the long form of TRIGger but not all the characters of the long form Wow trigg seq imm incorrect syntax extra g only trig or trigger is correct AII of the SCPI commands also have a query form unless otherwise noted Query forms contain a question mark The query form allows the system to ask what the current setting of a parameter is The query form of the command generally replaces the
69. of Standards and Technology formerly National Bureau of Standards to the extent allowed by that organization s calibration facility and to the calibration facilities of other International Standards Organization members WARRANTY The product referred to herein is warranted against defects in material and workmanship for a period of three years from the receipt date of the product at customer s facility The sole and exclusive remedy for breach of any warranty concerning these goods shall be repair or replacement of defective parts or a refund of the purchase price to be determined at the option of VTI For warranty service or repair this product must be returned to a VXI Technology authorized service center The product shall be shipped prepaid to VTI and VTI shall prepay all returns of the product to the buyer However the buyer shall pay all shipping charges duties and taxes for products returned to VTI from another country VTI warrants that its software and firmware designated by VTI for use with a product will execute its programming when properly installed on that product VTI does not however warrant that the operation of the product or software or firmware will be uninterrupted or error free LIMITATION OF WARRANTY The warranty shall not apply to defects resulting from improper or inadequate maintenance by the buyer buyer supplied products or interfacing unauthorized modification or misuse operation outside the environme
70. ol Front Panel P Read Clock Enable Data Bus Data Bus FIGURE 5 3 READ MODE BUFFER CONFIGURATION CLKO input from the UUT is terminated in the VM1548C by a RC network of 120 Q to ground through a 100 pF capacitor and a 47 kQ resistor to VCC This termination value gives a time constant of 12 ns for fast rise times on input clocks and will not load the UUT driving source The received clock now referred to as CLOCKO is routed to the Timing and Control FPGA Once inside the Timing and Control FPGA the CLOCKO signal may be inverted to produce a falling edge if this feature has been selected or remain in the normal default state of a rising edge The signal is then muxed to the input clock circuitry in the Timing and Control FPGA and routed to the selected I O Data Buffer as CLKINO LATCH DATA The rising edge of this signal then clocks the I O Data Buffer to read data from the UUT The CLOCKO signal also causes the Timing and Control FPGA to generate an IRQ signal to the VXI backplane signaling incoming data from the UUT VM1548C Theory Of Operation 103 VXI Technology Inc READ DATA Upon receipt of the SCPI command to read the data the Timing and Control FPGA decodes the address and control bits from the VMIP bus and generates the READO signal to the OEBAI input of the I O Word Buffer This enables the I O Word Buffer to input data from the I O Data Buffer The Timing and Control FPGA then issues the
71. ont panel connector I O signal is active low and is pulled to VCC through a 47 kQ resistor The signal is then inverted and routed to the OR gate The result of OR ing these two signals together provides a low on I O Data Buffer direction enable lines GBA and GAB This signal is also routed to the I O Word Buffer output write enable line This is done to avoid READ WRITE contentions between the two buffers The I O buffers are now configured to receive data from the UUT or the read mode CLOCK ENABLE Input clock enabling is accomplished when the VMIP module receives the SCPI command for input clock enable The Timing and Control FPGA then decodes the address and control bits from the VMIP bus and generates the DOE signal to the Read Write Data Buffer The Timing and Control FPGA generates PORTENA enabling the Port Decoder as detailed previously This time the address bits decode to PORTO clocking the Read Clock Enable latch The output of this latch CLKINENAO is routed to the I O Data Buffer clock enable line SBA Loading of data into the I O Data Buffer occurs when 1548 receives the appropriate input clock or trigger as specified by the SCPI command 102 VM1548C Theory Of Operation www vxitech com CLOCKO CLKO from s WV front panel 100pF Control Lines alr T 1 00 from WRITE Timing B front panel and Control d D8 D15 VMIP Por Directi Decoder HeCUOn Bus Address 0 1 2 j Contr
72. ort s external clock line will be driven This clock line is a pin on the 68 pin external connector 0 or OFF Means the associated port s external clock line will be an input 1 or ON Means the associated port s external clock line will be an output Examples Command Query OUTP CLOC ENAB 0 OUTP CLOC ENAB 0 Related Commands OUTPut CLOCk POLarity lt port gt lt edge gt OUTPut CLOCk SOURce port source 66 VM1548C Command Dictionary www vxitech com OUTPut CLOCk POLarity Purpose To control the polarity of the specified port s external clock line Type Setting Command Syntax OUTPut CLOCk POLarity lt port gt lt edge gt lt port gt 0 1 2 3 4 5 edge NORMal I INVert RST Value NORMal Query Syntax OUTPut CLOCk POLarity lt port gt Query Parameters port gt 0 1 2 3 4 5 Query Response NORM INV Description The output clock polarity command controls the polarity of the specified port s external clock line There are six individual clock circuits see clock circuit description A polarity of NORMal will produce a rising edge clock on the 68 pin external connector A polarity of INVert will produce a falling edge clock on the 68 pin external connector Note It is important to remember that the output clock source should be either GLOBAL or one of the eight TTLTrigger lines to co
73. parameter with a question mark Query responses do not include the command header This means only the parameter is returned no part of the command or question is returned Keywords or parameters enclosed in square brackets are optional If the optional part is a keyword the keyword can be included or left out Omitting an optional parameter will cause its default to be used Parameters are enclosed by angle brackets gt Braces or curly brackets are used to enclose one or more parameters that may be included zero or more times A vertical bar I read as or is used to separate parameter alternatives 22 VM1548C Programming www vxitech com EXAMPLES OF SCPI COMMANDS TTLTRIG CIRCUIT A multiplexer is used to select 1 of 8 different sources as TTLTRIG The signal is selected using the following SCPI command OUTPut TTLTrig SOURce source Where source refers to one of the EXTERNAL CLK lines CLKO 5 IMMEDIATE or NONE The selected signal is called GLOBAL TRIGOUT and after a polarity control it is called TTLTRIGGER which is presented on the VXIbus as the selected TTL TRIGO 7 The specific TTLTRIG line is selected using the following SCPI command OUTPut TTLTrig n Where n refers to one of the 8 TTLTRIG lines The TTLTRIGGER is enabled or disabled using the following SCPI command OUTPut TTLTrig STATe ON Enables the Trigger OUTPut TTLTrig STATe OFF Disables the Trig
74. port sites and service plan information 10 VM1548C Preface www vxitech com SECTION 1 INTRODUCTION INTRODUCTION The VM1548C is a high performance I O module that has been designed for high data throughput and flexibility of configuration The instrument uses the message based word serial interface for programming and data movement as well as allowing direct register access for very high speed data input and retrieval VM1548C command set conforms to the SCPI standard for consistency and ease of programming The 1548 is a member of the VXI Technology VMIP VXI Modular Instrumentation Platform family and is available as a 48 96 or 144 channel singlewide V XIbus instrument Figure 1 1 and Figure 1 2 show the 144 channel version of the VM1548C The 96 channel version would not have J200 and its associated LED s and nomenclature while the 48 channel version would eliminate J202 as well In addition to these three standard configurations the VM1548C may be combined with any of the other members of the VMIP family to form a customized and highly integrated instrument see Figure 1 1 This allows the user to reduce system size and cost by combining the VM1548C with two other instrument functions in a single wide C size VXIbus module FIGURE 1 1 VMIPTM PLATFORM VM1548C Introduction 11 M VXI Technology
75. ric shock the grounding conductor must be connected to earth ground To avoid injury electric shock or fire hazard Do not operate in wet or damp conditions Do not operate in an explosive atmosphere Operate or store only in specified temperature range Provide proper clearance for product ventilation to prevent overheating DO NOT operate if any damage to this product is suspected Product should be inspected or serviced only by qualified personnel The operator of this instrument is advised that if the equipment is used in a manner not specified in this manual the protection provided by the equipment may be impaired Conformity is checked by inspection VM1548C Preface VXI Technology Inc SUPPORT RESOURCES Support resources for this product are available on the Internet and at VXI Technology customer support centers VXI Technology World Headquarters VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 Phone 949 955 1894 Fax 949 955 3041 VXI Technology Cleveland Instrument Division 5425 Warner Road Suite 13 Valley View OH 44125 Phone 216 447 8950 Fax 216 447 8951 VXI Technology Lake Stevens Instrument Division VXI Technology Inc 1924 203 Bickford Snohomish WA 98290 Phone 425 212 2285 Fax 425 212 2289 Technical Support Phone 949 955 1894 Fax 949 955 3041 E mail support vxitech com Visit http www vxitech com for worldwide sup
76. rt source CHE port 0 1 2 3 4 5 source NONE TTLTrig EXTernal IMMediate GLOBal RST Value NONE Query Syntax OUTPut REGister SOURce port gt Query Parameters port gt 0 1 2 3 4 5 Query Response NONE TTLT EXT IMM GLOB Description The Output Register Source command controls which clock source will be used to clock data to the output data port Source Parameter Description NONE This disables the specified port s output clock The data appearing on the specified port will latch out immediately TTLTrig This selects the VXIbus TRIGIN as the clock source TRIGIN can be 1 of 8 trigger lines on the VXI bus See INPut TTLTrig EXTernal This selects the port s associated CLK line coming from the 68 pin external connector as the clock source IMMediate _ This selects the Word Serial Event as the clock source See TRIGger SEQuence IMMediate GLOBal This selects TRIGOUT as the clock source See OUTPut TTLTrig SOURce Note The NONE selection is single buffered all other selections are double buffered Examples Command Query Response Description OUTP REG SOUR 0 IMM OUTP REG SOUR 0 IMM Related Commands OUTPut REGister POLarity INPut TTLTrigger INPut TTLTrig STATe TRG TRIGger SEQuence IMMediate OUTPut TTLTrig SOURce 70 VM1548C Command Dictionary www vxitech com OUTPut
77. s of 8 bits DIRECTION bi directional DATA THROUGHPUT 5 us typical system 500 us register cycle time 200 kB s using D8 access 400 kB s using D16 access PHYSICAL INTERFACE N channel DMOS transistor 2601 with a current protection circuit on the output side and a voltage divider and voltage comparator on the input side CHANNEL INPUT CHARACTERISTICS ViiN high gt 20 Vindow lt 1 5 Vinanax lt 60 V Input Impedance gt 65 CHANEL OUTPUT CHARACTERISTICS Voutimax lt 60 V Current Sink Max 300 mA Switch On Time Elus CLOCK AND CONTROL INPUT CHARACTERISTICS ViiN high gt 2 0 V Vindow 0 8 V Current In Vy 5 0 V lt 10 DATA INPUT CLOCK SOURCES 6 front panel TTL trigger bus 0 7 word serial command TTL TRIGGER OUTPUT SOURCES Front Panel Clock inputs 0 5 CLOCKED INPUT DATA SETUP gt 2 us CLOCKED INPUT DATA HOLD gt 0 CLOCKED DATA OUTPUT SKEW lt 2 us POWER REQUIREMENTS 5 V 9 864 mA 12 V 60 mA COOLING REQUIREMENTS VM1548C 1 0 4 L s VM1548C 2 0 8 L s VM1548C 3 1 2 L s VM1548C Introduction 15 VXI Technology Inc VM1548C Introduction www vxitech com SECTION 2 PREPARATION FOR USE INSTALLATION When the 1548 is unpacked from its shipping carton the contents should include the following items 1 VM1548C VXIbus module 1 VM1548C Open Collector Digital I O Module User s M
78. s that the register be enabled as an input port If the port is configured as an output the current value is returned The operation mode of the register clocked or transparent can also affect what data is currently in the register Command Query Response Description READ 2 The data currently in the register SOURce DATA ENABle port boolean INPut REGister SOURce port source FORMat type VM1548C Command Dictionary 75 VXI Technology Inc READ CLOCks Purpose Queries the clock line levels Type Query Command Syntax N A S O IE N A RST Value N A Query Syntax READ CLOCks Query Parameters N A Query Response 0 to 63 decimal Description The Read Clocks command queries and returns the clock line levels The 6 bit response signifies a high or low on each clock line 0 through 5 Examples Command Query Response Description READ CLOC 24 See table below Related Commands OUTPut CLOCk ENABle 51413121110 Bits 0111110 0 0 Clock lines 3 and 4 high would return a decimal value of 24 76 VM1548C Command Dictionary www vxitech com READ CONTrol Purpose Queries the I O control line levels Type Query Command Syntax N A Command Parameters N A RST Value N A Query Syntax READ CONTrol Query Parameters N A Query Response
79. s the transition on which the interrupt trigger will occur If the negative transition is set to on then a falling edge trigger will generate an interrupt If the negative transition is off then a rising edge trigger will generate an interrupt Note It is important to remember that the interrupt trigger source should be either GLOBAL or 1 of the 6 external clocks for setting the interrupt trigger source to occur on a negative transition Command Query STAT INT NTR 1 STAT INT STAT INT NTR 0 STAT INT STAT INT Response Description NTR NTR PTR STATus INTerrupt ENABle lt source gt STATus INTerrupt PTRansition lt boolean gt 84 VM1548C Command Dictionary www vxitech com STATus INTerrupt PTRansition Purpose Sets the transition on which the Interrupt Trigger will occur Type Setting Command Syntax STATus INTerrupt PTRansition lt boolean gt lt boolean gt 0 1 OFF ON RST Value ON Query Syntax STATus INTerrupt PTRransition Query Parameters N A Query Response boolean 0 1 OFF ON Description The Status Interrupt PTRansition sets the transition on which the interrupt trigger will occur If the positive transition is set to on then a rising edge trigger will generate an interrupt If the positive transition is off then a falling edge trigger will generate an interrupt Note
80. status interrupt trigger the following SCPI command would be issued STATus INTerrupt ENABle GLOBAL To trigger the status interrupt from a negative going edge external clock source from port 3 the following SCPI commands would be issued STATus INTerrupt STATus INTerrupt ENABle EXTERNAL3 NTRansition ON To trigger the status interrupt from a negative edge going external clock source from port 1 the following SCPI commands would be issued STATus INTerrupt ENABle EXTERNAL1 STATus INTerrupt NTRansition ON 24 VM1548C Programming www vxitech com OUTPUT REGISTER CIRCUIT This section refers to the bi directional port when configured as an output The SCPI command used to configure a port as an output is SOURce DATA ENABle lt port gt ON The port is programmable to allow the data to be transparent or clocked If the port is clocked there are several choices for the clock source The method for selecting clocked mode and the source of the clock is done with one SCPI command OUTPut REGister SOURce port gt source Where lt port gt is 1 of 6 data registers source is EXTERNAL TTLTRIG GLOBAL TRIGOUT or IMMEDIATE The method for selecting transparent mode is OUTPut REGister SOURce port 4 NONE Where port is 1 of 6 data registers and NONE means this data register is transparent EXAMPLES The fo
81. sumed the external CLK3 signal is a steady logic low and the clock edge is produced by toggling the clock polarity SOURCe DATA ENABle 3 OFF INPut REGister SOURce 3 EXTERNAL INPut REGister POLarity 3 NORMAL INPut REGister POLarity 3 INVERT This provides a rising edge clock FORMat HEX READ 3 Example of read value is 26 VM1548C Programming www vxitech com BI DIRECTIONAL CLOCK CIRCUIT There are six independent bi directional clock circuits connected to the 68 pin external connector Each clock is associated with one of the 6 ports previously described Therefore lt port gt terminology is used to refer to a specific clock When the circuit is configured as an output the clock signal will be sourced by the module When the circuit is configured as an input the clock signal is sourced by UUT This clock CLK0 5 may be used for many different purposes trigger source selections for the interrupt trigger a port s input clock a port s output clock The following SCPI command configures the clock line as an output OUTPut CLOCk ENABle ON The following SCPI command configures the clock line as an input OUTPut CLOCk ENABle OFF When the circuit is operating as an output the clock source is selectable using the following SCPI command OUTPut CLOCk SOURce port 4 source Where source is TTLTRIG IMMEDIATE GLOBAL TRIGOUT or NONE The polarity of t
82. t 4 OUTP CLOC ENAB 5 ON Same as previous command except for port 5 SOUR DATA ENAB 3 OFF Selects and enables port 3 to read data from the UUT SOUR DATA ENAB 4 OFF Selects and enables port 4 to read data from the UUT SOUR DATA ENAB 5 OFF Selects and enables port 5 to read data from the UUT INP REG POL 3 INV Selects the falling edge for clocking port 3 INP REG POL 4 INV Selects the falling edge for clocking port 4 INP REG POL 4 INV Selects the falling edge for clocking port 5 INP REG SOUR 3 TTL Selects VXI bus TRIGIN as the clock source for port 3 INP REG SOUR 4 L Same as previous command except for port 4 INP REG SOUR 5 TTL Same as previous command except for port 5 INP TTLT STATE ON Enables the TTL trigger selection mux INP TTLT 1 Selects VXI bus TTL trigger line 1 to be used as TRIGIN STAT INT ENAB Set the interrupt trigger source as the default value STAT INT NTR ON Set the interrupt trigger source to the negative edge The controller waits for the interrupt and then proceeds READ 3 Data is transferred from port 3 to the VMIP bus READ 4 Data is transferred from port 4 to the VMIP bus READ 5 Data is transferred from port 5 to the VMIP bus 30 VM1548C Programming www vxitech com Below Figure 3 2 illustrates what occurs when these commands are executed The description that follows illustrates the role of each command TRIGINO 7 Trigger In Mux Control Lines 47K WRITE IN OUT lt port gt 5 25 CLKI
83. ter Type Setting Command Syntax INPut REGister POLarity port gt edge lt port gt 0 1 2 3 4 5 edge NORMal INVert RST Value NORMal Query Syntax INPut REGister POLarity lt port gt Query Parameters port gt 0 1 2 3 4 5 Query Response NORM INV Description A Polarity of NORMal would cause the data to be latched in on a rising edge of the clock A Polarity of INVert would cause the data to be latched in on a falling edge of the clock Note that it is important to remember that the input register must be operating in clocked mode in order for the polarity to affect the Input Register latching Examples Command Query INP REG POL 0 NORM INP REG POL 0 NORM Related Commands INPut REGister SOURce lt port gt lt source gt 62 VM1548C Command Dictionary www vxitech com INPutREGister SOURce Purpose Type Command Syntax Command Parameters RST Value Query Syntax Query Parameters Query Response Description Examples Related Commands To control the selection of the signal to be used for the specified port s input clock source Setting INPut REGister SOURce lt port gt lt source gt port gt 0 1 2 3 4 5 source NONE TTLTrig EXTernal IMMediate GLOBal NONE INPut REGister SOURce port gt port gt 0
84. tion Note This is an internal latched over current condition The over current condition must be removed and the RESet ISENse command issued in order to reset this indication Examples Command Query Response Description STAT QURES COND 0 Related Commands None VM1548C Command Dictionary 91 VXI Technology Inc STATus QUEStionable ENABle Purpose Sets the Questionable Status Enable Register Type Required SCPI command Command Syntax STATus QUEStionable ENABle lt NRf gt 2 NR numeric ASCII value from 0 to 32767 RST Value NRf must be supplied Query Syntax STATus QUEStionable ENA Ble Query Parameters None Query Response Numeric ASCII value from 0 to 32767 Description The Status Questionable Enable command sets the bits in the Questionable Status Enable Register If this bit is set an over current can cause an interrupt The Status Questionable Enable query reports the contents of the Questionable Status Enable Register Examples Command Query STAT QUES ENAB 1 STAT QUES ENAB Response Description Related Commands None 92 VM1548C Command Dictionary www vxitech com STATus QUEStionable E VE Nt Purpose Queries the Questionable Status Event Register Type Required SCPI command Command Syntax None query only eae N A RST Value N A Query Syntax
85. tput then as soon as the data is written it will appear on the external connector Likewise if the port is being used as an input then the data appearing on the external connector is immediately available to be read Numbers can be received by the module in decimal hexadecimal octal or binary Numbers with no special leading characters are considered decimal Hexadecimal numbers are designated with a leading i e HFF is decimal 255 Octal numbers are designated with a leading 1 0177 is decimal 255 Binary numbers are designated with a leading B i e B 11111111 is decimal 255 A query will return a value the specified register was set to The query syntax is a command followed by 1 INPut TTLTrig is the set command and INPut TTLTrig is the query Query only commands do not have a set command associated with it 1 READ 46 VM1548C Command Dictionary www vxitech com Command TABLE 4 1 IEEE 488 2 COMMON COMMANDS Description CLS Clears the Status Register ESE Sets the Event Status Enable Register ESR Queries the Standard Event Status Register IDN Query the module Identification string OPC Set the OPC bit in the Event Status Register RST Resets the module to a known state STB Query the Status Byte Register TRG Causes a trigger event to occur TST Starts and reports a self test procedure WAI Halts execution and queries
86. trument Specific SCPI Commands sss 48 interr pt 4 5 5 n neret stet Interrupt Circuit K output clock 27 Output Register Circuit OUTPut CLOCK ENABle OUTPut CEOCK POLtIty itii i tro toten 67 OUTPUULCLOCK SOURCE E 68 OUTPut REGister POLarity OUTPut REGister SOURce OUTPut TTL Trig i OUTPut TTL Trig POLarity eese 72 OUTPut TTETrig SOURCe nnt ttes T3 OUTP t T TE Frig STA Tepiero in 74 P POTT dct ma enmt 25 26 30 38 46 48 READ READ CLOCks S READ CONTIOL tore teet tbe ie tens READ ISENSe enn RE RIPE EEG ees Required SCPI commands RESetUISENSe enini tein e HERI SCPI Required Commands 9 SOURCE DATA 22 SOURce DATA POLarity Specifications STATus INTerrupt ENABIe 2 83 5 2 84 5 0 85 STATus OPERation CONDition 2 88 STATus OPERation ENABIe 2 89 STATus OPERation 2 87 STATUS PRESEt ett RENS 90 5 5 91 STATus QUEStionable ENABle 92 S
87. ue an appropriate OR operation is required A bit shift operation may also be required depending on the port to be written to For example if the new value to be written to Port 1 is 00001111 then the final value to be written to the register is 1111000010101010 00001111 lt lt 8 For example in order read Port 1 Read the register at offset 0x20 This presents the values of Ports 0 and 1 However since the value Port 1 is of interest the following steps must be followed a Read the register at offset 0x20 Assume that the value read is as shown below 1010000011110000 in binary format b Since the upper 8 bits are of interest an appropriate mask has to be applied and the value right shifted The data value of port 1 is 1010000011110000 OxFF00 8 VM1548C Programming 37 VXI Technology Inc The Model VM1548C Digital I O Module supports direct access to the six 8 bit data ports via the Device Dependent Registers of VXIbus interface The specific registers are located 16 Memory at offsets 0x20 1 0x21 0x22 Port3 0x23 Port2 0x24 Port5 and 0x25 Port4 The following diagram shows A16 Memory and the Model VM1548C Data Port Map Offset 3E 3C 3A 38 36 34 32 30 NIN 22 TABLE 3 2 A16 MEMORY Event R W Port 1 Port 0 20 1E 1C 1A 18 16 14 12 10 2 A32 Pointer Low A32 Pointer High 24 Pointer Low A2
88. urce of the clock is done with one SCPI command INPut REGister SOURce lt port gt lt source gt Where lt port gt is 1 of 6 data registers source is EXTERNAL TTLTRIG GLOBAL TRIGOUT or IMMEDIATE Regardless of the port s input mode note that data inputs to the module do not contain pull up or down biasing resistors As such if the user does not provide either active or passive biasing of the data inputs a read of the port may result in either a 1 or a 0 being read from the data inputs The method for selecting transparent mode is INPut REGister SOURce port gt NONE Where port is 1 of 6 data registers and NONE means this data register is transparent EXAMPLES The following SCPI commands will clock the data in on port 43 using the IMMEDIATE pulse SOURCe DATA ENABle 3 OFF INPut REGister SOURce 3 IMMEDIATE TRIGger SEQuence IMMediat This provides a rising edge clock FORMat ASCII READ 3 Example of read value is 255 The following is an example of reading from a port operating in transparent mode This method requires no clock edge for the data to be available SOURCe DATA ENABle 5 OFF INPut REGister SOURce 5 NONE FORMat BINARY Example of read value is B11111111 READ 5 The data presented on the external connector is what will be read The following example selects the external CLK3 line to clock the data port In this example it is as
89. w signal to the Port Decoder Address bits AO Al and A2 are decoded causing the Port Decoder to provide a low going edge clocking the Direction Control latch This octal D latch provides the direction signal OUTENAO that is OR ed with the corresponding I O signal from the front panel connector The front panel I O signal is active low and is pulled to VCC through a 47 kQ resistor The signal is then inverted and routed to the OR gate The result of OR ing these two signals together provides a high on the I O Data Buffer direction enable lines GBA and GAB This signal is also routed to the I O Word Buffer output write enable line OEABI This is done to avoid READ WRITE contentions between the two buffers The I O buffers are now configured to drive the data to the UUT or the write mode CLOCK ENABLE Output clock enabling is accomplished when the VMIP module receives the SCPI command for output clock enable The Timing and Control FPGA then decodes the address and control bits from the VMIP bus and generates the DOE signal to the Read Write Data Buffer The Timing and Control FPGA generates PORTENA enabling the Port Decoder as detailed previously This time the address bits decode to PORTI clocking the Write Clock Enable latch The output of this latch CLKOUTENAQO is routed to the I O Data Buffer clock enable line SAB 98 VM1548C Theory Of Operation www vxitech com DATA LOAD Loading of data into the I O Word Buffer occurs when the
90. y enabling them to output data to the read write data buffer and onto the VMIP bus The second signal READ 0 2 4 then clocks the I O word buffer The I O word buffer will output one 16 bit word at a time Note that data inputs to the module do not contain pull up or down biasing resistors If the user does not provide active or passive biasing of the data inputs a read of the port may result in either 1 or 0 being read from the data inputs 32 VM1548C Programming www vxitech com WRITE READ MODE In this example a wrap around cable will be used to configure and transfer data from port 0 port 1 and port 2 to port 3 port 4 and port 5 The wrap around cable pin outs used are as defined in Table 3 1 The data to be sent is port 0 01 port 1 23 and port 2 45 The IRQ signal will be generated from the external clock received from port 5 COMMANDS INP REG SOUR 3 INP REG POL 3 INP REG INP REG SOUR 4 POL 4 INP REG SOUR 5 POL 5 OUTP CLOC SOUR 0 IMM OUTP REG SOUR OUTP CLOC ENAB OUTP C OUTP REG SOUR o 1 ia Q INV EX INV EX INV 00 0 IM 1 10 LOC SOUR 1 IMM 1 IM 20 OUTP CLOC SOUR 2 IMM OUTP REG SOUR 2 IM SOUR DATA ENAB 0 O SOUR DATA ENAB 1 O SOUR
91. y to receive data The OUTP REG SOUR 0 EXT and the OUTP REG SOUR 1 EXT commands select the external clock input as the trigger method to output data to the UUT When these commands are received the VM1548C timing and control circuitry will generate the PORTENA signal to the port decoder The port decoder then clocks the write clock enable latch selecting the CLKOUTENA The CLKOUTENA signals are applied to the I O data and word buffers enabling the output clock line The SOUR DATA ENAB 0 1 and SOUR DATA 0 48 command enables port 0 for a write and latches the data into the I O word buffer respectively VM1548C Programming 29 VXI Technology Inc The VM1548C timing and control circuitry generates the PORTENA signal to the port decoder This decoder in turn clocks the direction latch selecting the OUTENA This signal is OR ed with the external I O direction signal from the UUT The result is referred to as IN OUT and is applied to the I O data and word buffers configuring them as outputs The timing and control circuitry will generate a write pulse latching the data from the read write data buffer into the I O word buffer Port 0 is now ready to transmit the data byte 48 to the UUT The steps are repeated for the SOUR DATA ENAB 1 1 and SOUR DATA 1 15 commands with port 1 being enabled and loaded with the data byte 15 The 1548 is now ready to transmit the data word 1548C to the UUT When the CLK signals are received fro

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