Schematic Check List
Contents
1. 3 3V LDO ON OFF 1 VDDPLL M C PIOx output WAKEUPx External Wakeup signal i Signal Name Recommended Pin Connection Description 1 8V to 3 6V VDDIN Decoupling Filtering capacitor Powers the voltage regulator 10uF or higher ceramic capacitor Powers the peripheral I Os 1 62V to 3 6V Decoupling Filtering capacitors must be added to improve VDDIO Decoupling Filtering capacitors startup stability and reduce source voltage drop 100 nF and 2 2 pF Warning At power up VDDIO needs to reach 0 6V before VDDIN reaches 1 0V Decoupling Filtering capacitors VDDOUT 100 nF and 2 2uF 02 1 8V Output of the main voltage regulator 11061A ATARM 28 Jul 10 AMEL 7 AMEL M Signal Name Recommended Pin Connection Description 1 62V to 1 95V VDDCORE Connected to VDDOUT Supply Core embedded memories and peripherals power supply Decoupling capacitor 100 nF 1 62V to 1 95V VDDPLL Connected to VDDOUT Supply Decoupling capacitor 100 nF Powers PLLA PLLB the Farst RC and the 3 20 MHz oscillator Ground pins GND are common to VDDIO VDDPLL and GND Ground VDDCORE Note The two diodes provide a switchover circuit for illustration purpose between the backup battery and the main sup ply when the system is put in backup mode 8 Application Note memm 11061A ATARM 28 Jul 10 i 8 ADDTICATION Note Main Oscillator in Nor2. If debug mode is not required this pin can x ode TMS SWDIO PB6 be use as GPIO Internal pull up disabled Schmitt Trigger enabled Application dependant Reset State TDI PB4 If debug mode is not required this pin can SWJ DP Mode be use as GPIO Internal pull up disabled Schmitt Trigger enabled Reset State TDO Application dependant SWJ DP Mode TRACESWO PB5 If debug mode is not required this pin can Internal pull up disabled be use as GPIO Schmitt Trigger enabled Application dependant Must be tied to Vyppio to enter JTAG JTAGSEL Boundary Scan Permanent Internal pull down resistor 15 kOhm In harsh environments It is strongly recommended to tie this pin to GND Flash Memory Internal pull down resistor 100kOhm eT Must be tied to V to erase the General Purpose NVM Application d dant VDDIO pp ica ies epen an ot on bits GPNVMx the whole Flash content and the security ERASE PB12 If hardware erase is not required this pin bit b GPIO f PAES RE Reset state Erase Input with a 100 kOhm Internal pull down and Schmitt trigger enabled Minimum debouncing time is 220 ms Reset Test Application dependant By default the NRST pin is configured as an input MRa Can be connected to a pushbutton for Permanent internal pull up resistor to V 15 kOhm hardware reset purp VDDIO TST pin can be left unconnected in normal mode TST Toenterin KEPI mode TST pins be tiea Permanent internal pull down resistor 15 kOhm to Vvppio In harsh
3. any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life OWERED ARM 2010 Atmel Corporation All rights reserved Atmel Atmel logo SAM BA and combinations thereof and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries ARM the ARMPowered Logo Thumb Cortex and others are the registered trade marks or trademarks of ARM Ltd Other terms and product names may be trademarks of others 11061A ATARM 28 Jul 10
4. environments It is strongly recommended to tie this pin to GND 11061A ATARM 28 Jul 10 AMEL 11 AMEL mi Signal Name Recommended Pin Connection Description PIO At reset all PIOs are in IO or System IO mode with Schmitt trigger inputs and internal pull up enabled PAx PBx PCx Application Dependant a Pulled up on Vyppio To reduce power consumption if not used the concerned PIO can be configured as an output and driven at 0 with internal pull up disabled Parallel Capture Mode PIODCO PIODC7 Application Dependant Vyppio Parallel Mode capture Data PIODCCLK Application Dependant Vyppio Parallel Mode capture Clock PIODCEN1 2 Application Dependant Vyppio Parallel Mode capture mode enable Analog Reference 2 0V to Vppio ADVREF is a pure analog input Decoupling capacitor s ADVREF is the voltage reference for the ADC DAC and ADVREF Analog comparator 2 0V is used for 10 bit ADC resolution only In other case the minimum ADVREF To reduce power consumption if analog features are not value is 2 4V used connect ADVREF to GND 12 bit ADC ADO AD14 0 to ADVREF ADC Channels ADTRG Vppio ADC External Trigger input 10 bit ADC ADO AD14 0 to ADVREF ADC Channels ADTRG Vbpio ADC External Trigger input 12 bit DAC DACO DAC1 1 6 ADVREF to 5 6 ADVREF DACTRG Vppio DAC External Trigger input USB Device UDP Application dependent Reset St
5. part is integrated and formated according to the core integration in the Internal architecture of LAR gas tg at paca SAMBS series This information is fully detailed in the SAM3S Series Product Thumb2 instruction sets Datasheet Embedded in circuit emulator Cortex M3 Technical Reference Manual available from ARM Ltd Evaluation Kit User Guide SAM3S EK Evaluation Board User Guide 2 Application Note memm 11061A ATARM 28 Jul 10 Application Note 3 Schematic Check List Single Power Supply Strategy VDDIO USB gt Transceivers ADC DAC i Analog Comparator Main Supply 1 8V 3 6V VDDIN 7 T Voltage Single Power Supply Schematic Example m Signal Name Recommended Pin Connection Description 1 8V to 3 6V VDDIN Decoupling Filtering capacitor 10uF or higher ceramic capacitor Powers the voltage regulator ADC DAC and Analog comparator power supply Powers the peripheral I Os USB transceiver Backup 1 62V to 3 6V part 32kHz crystal oscillator and oscillator pads Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop Warning At power up VDDIO needs to reach 0 6V before VDDIN reaches 1 0V 1 8V Output of the main voltage regulator Decoupling Filtering capacitors must be added to guarantee stability VDDIO Decoupling Filtering capacitors 100 nF and 2 2uF 2 Decoupling Filtering capacitors VD
6. the peripheral I Os Decoupling Filtering capacitors must be added to improve C ted to Main Suppl VDDIO a E RARES startup stability and reduce source voltage drop Decoupling Filtering capacitors 100 nF and 2 2 yF Warning At power up VDDIO needs to reach 0 6V before VDDIN reaches 1 0V 1 8V Output of the main voltage regulator Decoupling Filtering capacitors must be added to guarantee stability Decoupling Filtering capacitors VDDOUT i 100 nF and 2 2pF 02 AMEL s 11061A ATARM 28 Jul 10 AMEL M Signal Name Recommended Pin Connection Description 1 62V to 1 95V VDDCORE connected t VODPEORE Supply Core embedded memories and peripherals power supply Decoupling capacitor 100 nF and 2 2uF O0 1 62V to 1 95V VDDPLL Connected to VDDCORE Supply Powers PLLA PLLB the Farst RC and the 3 20 MHz Decoupling capacitor 100 nF and oscillator 2 2uF 0 Ground pins GND are common to VDDIO VDDPLL and GND Ground VDDCORE Note Restrictions With Main Supply lt 2 0 V USB and ADC DAC and Analog comparator are not usable With Main Supply 2 0V and lt 3V USB is not usable With Main Supply 3V all peripherals are usable 6 Application Note memm 11061A ATARM 28 Jul 10 Application Note Backup Unit Externally Supplied VDDIO USB Backup p C Transceivers Battery L ADC DAC i Analog Comparator Voltage Regulator Main Supply
7. 0 00 Fax 33 1 30 60 71 11 Technical Support AT91SAM Support Atmel techincal support Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Sales Contacts www atmel com contacts Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at
8. DOUT i 100 nF and 2 2uF AMEL 3 11061A ATARM 28 Jul 10 AMEL Description Mw Signal Name Recommended Pin Connection Must be connected directly to VDDOUT pin Power the Core the embedded memories and the VDDCORE 1 62V to 1 95V peripherals power supply Decoupling capacitor 100 nF 1 62V to 1 95V Powers PLLA PLLB the Farst RC and the 3 20 MHz VDDPLL Decoupling capacitor 100 nF oscillator Ground pins GND are common to VDDIO VDDPLL and GND Ground VDDCORE Note Restrictions With Main Supply lt 2 0 V USB and ADC DAC and Analog comparator are not usable With Main Supply 2 0V and lt 3V USB is not usable With Main Supply 3V all peripherals are usable Application Note memm 4 11061A ATARM 28 Jul 10 E pplication Note Core Externally Supplied VDDIO i USB o HH Transceivers ADC DAC i Analog Comparator Main Supply 1 8V 3 6V VDDIN ome aan sir Voltage Regulator VDDOORE Supply 1 62V 1 95V VDDOORE H VDDPLL Core externally supplied Schematic Example Main Supply on VDDIO and VDDIN 1 8V to 3 6V VDDCORE Supply is between 1 62V and 1 95V Mw Signal Name Recommended Pin Connection Description shaken P the volt lator ADC DAC and Anal VDDIN Decoupling Filtering capacitor ee ene meee ee eee comparator power supply 10uF or higher ceramic capacitor 2 P P a 1 62V to 3 6V Powers
9. SAMS3S Microcontroller Series Schematic Check List 1 Introduction This Application Note is a schematic review check list for systems embedding Atmel s SAMBS series of ARM Cortex M3 Thumb 2 based microcontrollers It gives requirements concerning the different pin connections that must be consid ered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the SAM3S Series It does not consider PCB layout constraints It also gives advice regarding low power design constraints to minimize power consumption This Application Note is not intended to be exhaustive Its objective is to cover as many configurations of use as possible The Check List table has a column reserved for reviewing designers to verify that the line item has been checked AMEL T O AT91 ARM Thumb based Microcontrollers Application Note 11061A ATARM 28 Jul 10 AMEL 2 Associated Documentation Before going further into this Application Note it is strongly recommended to check the latest documents for the SAM3S Series Microcontrollers on Atmel s Web site Table 2 1 gives the associated documentation needed to support full understanding of this appli cation note Table 2 1 Associated Documentation Information Document Title User Manual Electrical Mechanical Ch teristi i ji ee mae ene SAM3S Series Product Datasheet Ordering Information Errata This
10. ate DDP PB10 If USB device support is not required this USB Mode pin can be use as GPIO Internal Pull down Application dependent IReset State DDM PB11 If USB device support is not required this USB Mode pin can be use as GPIO Internal Pull down 12 Application Note mee 11061A ATARM 28 Jul 10 i pplication Note Mv Signal Name Recommended Pin Connection Description Static Memory Controller SMC Data Bus DO to D15 Application dependent Note Data bus lines are multiplexed with DO D15 the PIOB controller Their I O line reset state is input with pull up enabled Address Bus AO to A23 Application dependent Note Data bus lines are multiplexed with A0 A23 the PIOB amp PIOC controllers Their I O line reset state is input with pull up enabled NWAIT pin is an active low input NWAIT Application dependent Note NWAIT is multiplexed with PC 18 Notes 1 These values are given only as a typical example 2 Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin 100nF GND 3 USB Device Typical connection copy of Figure 37 2 of the Datasheet Figure 37 2 Board Schematic to Interface Device Peripheral SV Bus Monitoring 27K PIO A 3 TypeB 4 EXT Connector 4 Note that the ADC voltages in 10 bit mode resolution ADC 12 bit in low resolution can descend to 2 0V Only one ADC is available on the SAM3S
11. mal Mode PB9 XIN crystal load capacitance dependant 1 kOhm resistor on XOUT only required for crystals with frequencies lower than 8 MHz MV Signal Name Recommended Pin Connection Description Clock Oscillator and PLL Internal Equivalent Load Capacitance C C 9 5 pF Crystal Load Capacitance ESR Drive Level and Shunt Capacitance to validate AT91SAM3S Crystals between 3 and 20 MHz PB9 XIN C ZINanaXOUT i Tyo PB8 XOUT apacitors on and XOU Ciext T Ciext bg The external load capacitance is calculated with the following formula CLext 2 Cerystar Cx Refer to the Crystal Oscillators Design Consideration Information section of the SAM3S Series Datasheet By default at startup the chip runs out of the Master Clock using the fast RC oscillator running at 4 MHz PB8 XOUT Main Oscillator in Bypass Mode PB9 XIN external clock source PB8 XOUT can be left unconnected or used as GPIO 1 62V to 3 6V Square wave signal VDDIO External Clock Source up to 50 MHz Duty Cycle 45 to 55 By default at startup the chip runs out of the Master Clock using the fast RC oscillator running at 4 MHz 4 8 12MHz Fast Internal RC Oscillator PB9 XIN and PB8 XOUT can be left unconnected or used as GPIO Powers up by VDDPLL 1 62V to 1 95V The output frequency is configurable through the PMC registers The Fast RC oscillator is calibrated in production The frequenc
12. series AMEL 13 11061A ATARM 28 Jul 10 AMEL 4 SAM3S Boot Program Hardware Constraints See AT91SAM Boot Program section of the SAM3S Series Datasheet for more details on the boot program 4 1 SAM BA Boot The SAM BA Boot Assistant supports serial communication via the UART or USB device port e UARTO Hardware Requirements none e USB Device Hardware Requirements External Crystal or External Clock with frequency of 11 289 MHz 12 000 MHz 16 000 MHz 18 432 MHz Note 1 Must be 2500 ppm and 1 8V Square Wave Signal Table 4 1 Pins driven during SAM BA Boot Program execution Peripheral Pin PIO Line UARTO URXD PAQ UARTO UTXD PA10 14 Application Note memm 11061A ATARM 28 Jul 10 Application Note 5 Revision History Table 5 1 Revision History Change Doc Rev Comments Request Ref 11061A 28 Jul 10 First issue AMEL 1s 11061A ATARM 28 Jul 10 AIMEL gt a O Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 International Atmel Asia Unit 1 5 amp 16 19 F BEA Tower Millennium City 5 418 Kwun Tong Road Kwun Tong Kowloon Hong Kong Tel 852 2245 6100 Fax 852 2722 1369 Product Contact Web Site www atmel com www atmel com AT91SAM Atmel Europe Le Krebs 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 7
13. y can be trimmed by softtware Duty Cycle 45 to 55 By default at startup the chip runs out of the Master Clock using the fast RC oscillator running at 4 MHz 11061A ATARM 28 Jul 10 AMEL AMEL M Signal Name Recommended Pin Connection Description Internal parasistic capacitance Cpara 1pF Crystal Load Capacitance ESR Drive Level and Shunt Capacitance to validate PA7 XIN32 XOUT32 PA8 XOUT32 32 768 kHz Crystal Capacitors on XIN32 and XOUT32 32 kHz Crystal crystal load capacitance dependent Sa rae used CLexrmax 20pF CLext 2X CorystarCpara Coc Refer to the Crystal Oscillators Design Consideration Information section of the SAM3S Series Datasheet By default at start up the chip runs out of the embeded 32 kHz RC oscillator PATANG oe PA8 XOUT32 PA7 XIN32 external clock source P Duty Cycle 45 to 55 PA8 XOUT32 can be left unconnectde or R 32 kHz Oscillator use a GPIO By default at start up the chip runs out of the embeded 32 kHz RC oscillator in bypass mode 10 Application Note me 11061A ATARM 28 Jul 10 E ADDIICATION Note mi Signal Name Recommended Pin Connection Description Serial Wire and JTAG Application dependant Reset State If debug mode is not required this pin can SWJ DP Mode TOR SWEER PB be use as GPIO Internal pull up disabled Schmitt Trigger enabled Application dependant ae
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