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User`s Manual 08.97 8-Bit CMOS Microcontroller http://www.siemens

1. C517A Special Function Registers COMSETL Address A1 Reset Value 00H Special Function Registers COMSETH Address A2 Reset Value 00H Special Function Registers COMCLRL Address A3 Reset Value 00H Special Function Registers COMCLRH Address A4p Reset Value 00H Special Function Registers SETMSK Address A5 Reset Value 00H Special Function Registers CLRMSK Address A6 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 Aly 7 6 5 A i3 2 A 0 COMSETL A2y 7 6 5 A id 2 1 0 COMSETH A3H oh 6 D 4 3 2 A 0 COMCLRL A4y 7 6 5 4 3 2 A 0 COMCLRH Ady H4 6 5 A id 2 A 0 SETMSK A6H 7 6 iD A jd 2 A 0 CLRMSK Bit Function COMSETL 7 0 Concurrent compare match set register low byte COMSETL contains the low byte of the 16 bit compare value for setting port 5 pins in concurrent compare mode COMSETH 7 0 Concurrent compare match set register high byte COMSETL contains the high byte of the 16 bit compare value for setting port 5 pins in concurrent compare mode COMCLRL 7 0 Concurrent compare match clear register low byte COMSETL contains the low byte of the 16 bit compare value for resetting port 5 pins in concurrent compare mode COMCLRH 7 0 Concurrent compare match clear register high byte COMSETL contains the high byte of the 16 bit compare value for resetting port 5 pins in concurrent compare mode SETMSK 7 0 Concurrent compare output set mask re
2. Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003H IEO Timer 0 Overflow 000BH TFO External Interrupt 1 0013H IE1 Timer 1 Overflow 001BH TF1 Serial Channel 0 00234 RIO TIO Timer 2 Overflow Ext Reload 002BH TF2 EXF2 A D Converter 0043H IADC External Interrupt 2 004By IEX2 External Interrupt 3 0053H IEX3 External Interrupt 4 005BH IEX4 External Interrupt 5 0063 IEXS External Interrupt 6 OO6BY IEX6 Serial Channel 1 0083 RH TM Compare Match Interupt of 0093H ICMPO ICMP7 Compare Registers CM0 CM7 assigned to Timer 2 Compare Timer Overflow OO9By CTF Compare Match Interupt of 00A3H ICS Compare Register COMSET Compare Match Interupt of 00ABH ICR Compare Register COMCLR Semiconductor Group 7 17 1997 08 01 SIEMENS Interrupt System C517A Execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control syst
3. ADDATH ADDATL 094 DAH Continuous Mode Converter Clock Conversion Prescaler 8 4 Clock fanc Input VAREF Clock fiy Vacno IND Start of P6 0 ADST Conversion Write to ADDATL internal B Shaded bit locations are not used in ADC functions Bus MCB03332 Figure 6 42 Block Diagram A D Converter Semiconductor Group 6 94 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 6 2 A D Converter Registers This section describes the bits functions of all registers which are used by the A D converter Special Function Registers ADDATH Address D9 Reset Value 00H Special Function Registers ADDATL Address DA Reset Value 00XXXXXXp Bit No MSB LSB 7 6 5 4 3 2 1 0 po MSB g 7 6 5 4 3 2 ADDATH LSB DAH 1 0 ADDATL The registers ADDATH and ADDATL hold the 10 bit conversion result in left justified data format The most significant bit of the 10 bit conversion result is bit 7 of ADDATH The least significant bit of the 10 bit conversion result is bit 6 of ADDATL To get a 10 bit conversion result both ADDAT register must be read If an 8 bit conversion result is required only the reading of ADDATH is necessary The data remain in ADDATH ADDATL until it is overwritten by the next converted data ADDAT can be read or written under software control
4. 5 3 Power supply current 10 8 Block diagram 00 8 7 PSEN signal e EEReREA E RES 4 3 OW Ai i acis iria ria o dd 2 4 3 17 PSW anaana 2 4 3 12 3 17 OW DS s sx aucta xo RES 3 16 8 8 HB8D 0 Si hata eins 3 15 6 71 6 72 eE AA EA ENEE 2 4 3 17 RB81 2 eee eee 3 15 6 80 POR ofer frs ues 3 14 3 15 D ig hd ele Sete trie E e Seca et aan EE 3 16 Sore S ER ERR P 3 14 3 15 Recommended oscillator circuits 10 16 Poi eee s owe ge gu disnei 3 14 3 15 RENO 0 sere eee 3 15 6 72 PR Mach whale Bola ee 3 14 3 16 BENTL pedum E E a E itn ine 6 80 MEER ee Bax ih a 3 14 3 18 Reset hendaid orep d patet 5 1 to 5 5 EETA ott oh oh bis 3 14 3 18 Fast power on reset 5 3 PO dete did eeu eoa seh 3 14 3 18 Hardware reset timing 5 5 HM HR 3 14 3 17 Power on reset timing 5 4 eae eS ae Cate societal coats 3 14 3 17 Reset circuitries 32 0 5 ah borse 5 2 Package information 10 17 MU 3 15 6 71 6 72 7 9 Parallel O 00 6 1 to 6 13 ME 3 15 6 80 7 9 PCON aLL 3 14 3 15 6 73 9 1 ROM protection 4 9 to 4 11 i E E E E 3 15 9 1 Protected ROM mode 4 10 PICO CMM 3 15 9 1 Protected ROM verification example 4 11 Pin configuration 0 1 4 Protected ROM verify timing 4 10 Pin Definitions and functions 1 5 to 1 10 Unprotected ROM mode 4 9 POMS PR 6 1 to 6 13 RSO ouaaa 2 4 3 17
5. Bit Function BD Baud rate generator enable When set the baud rate of serial interface 0 is derived from a dedicated programmable baud rate generator When cleared default after reset baud rate is derived from the timer 1 overflow rate SMOD Double baud rate When set the baud rate of serial interface 0 in modes 1 2 3 is doubled After reset this bit is cleared Figure 6 33 shows the configuration for the baud rate generation of serial channel 0 Semiconductor Group 6 73 1997 08 01 SIEMENS On Chip Peripheral Components C517A Timer 1 Overflow SOCON 7 SOCON 6 SM0 Baud Rate SM1 Generator SORELH SORELL Only one mode 6 can be selected Note The switch configuration shows the reset state MCS03329 Figure 6 33 Baud Rate Generation for Serial Channel 0 Depending on the programmed operating mode different paths are selected for the baud rate clock generation Table 6 12 shows the dependencies of the serial port 0 baud rate clock generation from the 3 control bits and from the mode which is selected in the special function register SOCON Table 6 12 Serial Interface 0 Baud Rate Dependencies Serial Interface 0 Active Control Bits Baud Rate Clock Generation Operating Modes BD SMOD Mode 0 Shift Register Fixed baud rate clock fosc 12 Mode 1 8 bit UART X X BD 0 Timer 1 overflow is used for baud rate Mode 3 9 bit UART ge
6. 6 3 4 Timer and Compare Register Configurations of the CCU The compare function and the reaction of the corresponding outputs depend on the timer compare register combination Table 6 5 shows the possible configurations of the CCU and the corresponding compare modes which can be selected The following sections describe the function of these configurations Table 6 5 CCU Configurations Assigned Compare Compare Output at Possible Modes Timer Register Timer 2 CRCH CRCL P1 0 INT3 CCO Compare mode 0 1 Reload CCH1 CCL1 P1 1 INT4 CC1 Compare mode 0 1 capture CCH2 CCL2 P1 2 INT5 CC2 Compare mode 0 1 capture CCH3 CCL3 P1 3 INT6 CC3 Compare mode 0 1 capture CCH4 CCL4 P1 4 INT2 CC4 Compare mode 0 1 capture see 6 3 4 1 and 6 3 4 2 CCH4 CCL4 P1 4 INT2 CC4 Compare mode 1 P5 0 CCMO Concurrent compare to P5 7 CCM7 see 6 3 4 3 CMHO0 CMLO P4 0 CMO Compare mode 0 to to CMH7 CML7 P4 7 CM7 see 6 3 4 4 and 6 3 4 4 2 COMSET P5 0 CCMO Compare mode 2 COMCLR to P5 7 CCM7 see 6 3 4 5 Compare CMHO CMLO P4 0 CMO Compare mode 1 Timer to to CMH7 CML7 P4 7 CM7 see 6 3 4 4 and 6 3 4 4 1 Semiconductor Group 6 41 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 4 1 Timer 2 Compare Function with Registers CRC CC1 to CC4 The compare function of registers CRC and CC1 to CC3 is completely compatible with the corresponding function of the C515 C515A Registers CRC CC1 to CC3 are pe
7. 000cc eee eee eee 6 35 6 3 3 Compare Functions of the CCU ocx ne coos awe GA doe Ed ede aed dt 6 36 6 3 3 1 Compare Mode Ori 2e prede eco cate a were a Uae ae E ewe ae oO 6 37 6 3 3 2 Compare Mode 1 ceu x daw ee ERG RES Ge eee tea eee ed cR ta 6 39 6 3 3 3 Compare Moda 2 512 s nete to reiten CSI kine URL R ae i ob UB B a ao 6 40 6 3 4 Timer and Compare Register Configurations of the CCU 6 41 6 3 4 1 Timer 2 Compare Function with Registers CRC CC1 to CC4 6 42 6 3 4 2 Timer 2 Capture Function with Registers CRC CC1 to CC4 6 45 6 3 4 3 Compare Function of Register CC4 Concurrent Compare 6 47 6 3 4 4 Compare Function of Registers CMO to CM7 020 2c eee eee ee 6 51 6 3 4 4 1 CMx Registers Assigned to the Compare Timer 00000e0 eee 6 52 6 3 4 4 2 CMx Registers Assigned to the Timer 2 00 000 eee eee 6 55 6 3 4 5 Timer 2 Operating in Compare Mode 2 000 cece eee eee 6 56 6 3 5 Modulation Range in Compare Mode O 20 0 e eee eee eee 6 57 6 3 6 Using Interrupts in Combination with the Compare Function 6 59 6 3 6 1 Advantages in Using Compare Interrupts 02000 e eee eee 6 59 6 3 6 2 Interrupt Enable Bits of the Compare Capture Unit 4 6 60 6 3 6 3 Interrupt Flags of the Compare Capture Unit 000 cc eee eee 6 61 Semiconductor Group I 2 1997 08 01 S
8. Figure 10 5 Data Memory Write Cycle MCT00033 Figure 10 6 External Clock Drive on XTAL2 Semiconductor Group 10 13 1997 08 01 SIEMENS Device Specifications C517A 10 6 ROM Verification Characteristics for the C517A 4R ROM Verification Mode 1 Parameter Symbol Limit Values Unit min max Address to valid data Tavav 10 fore ns P1 0 P1 7 P2 0 P2 6 Port 0 Data Addresses Figure 10 7 ROM Verification Mode 1 Semiconductor Group Address Data Out P0 0 P0 7 P1 0 P1 7 P2 0 P2 6 New Address New Data Out PSEN ALE EA RESET MCS03253 10 14 1997 08 01 SIEMENS Device Specifications C517A ROM Verification Mode 2 Parameter Symbol Limit Values Unit min typ max ALE pulse width Tawp 2 tora ns ALE period Tacy 12 tac ns Data valid after ALE pvA 4 toe ns Data stable after ALE losa 8 fcio m E ns P3 5 setup to ALE low Tas ToLeL ns Oscillator frequency 1 tact 3 5 24 MHz AAA Data Vaid MCT02613 Figure 10 8 ROM Verification Mode 2 Semiconductor Group 10 15 1997 08 01 SIEMENS Device Specifications C517A 0 2 Voc 0 9 Test Points 0 45 V MCT00039 AC Inputs during testing are driven at Voc 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measurements are made at Vihm for a logic 1 and V for a logic 0 Figur
9. Icc idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL2 driven with ci cH cucL 5 ns Vit Vss 0 5 V Vin Voc 0 5 V XTAL1 N C RESET Voc HWPD Port 0 Port 7 Port 8 Voc EA PE SWD Voz all other pins are disconnected D Icc active mode with slow down mode is measured with all output pins disconnected and with all peripherals disabled XTAL2 driven with tcicH gt cHcL 5ns y Vi Vss 0 5 V Viu Voc 0 5 V XTAL1 N C HWPD Voc RESET Voc Port 7 Port 8 Voc EA PE SWD Vas all other pins are disconnected zi Overload conditions occur if the standard operating conditions are exceeded ie the voltage on any pin exceeds the specified range i e Voy gt Vcc 0 5 V or Voy lt Vss 0 5 V The supply voltage Vcc and Vss must remain within the specified limits The absolute sum of input currents on all port pins may not exceed 50 mA 8 Not 100 tested guaranteed by design characterization 9 The typical Icc values are periodically measured at T4 25 C and Voc 5 V but not 100 tested 10 The maximum ec values are measured under worst case conditions T4 0 C or 40 C and Vec 5 5 V Semiconductor Group 10 3 1997 08 01 SIEMENS Device Specifications C517A MCD03338 Toc max 1A Toc typ Active Slow Down Figure 10 1 ICC Diagram Power Supply Cur
10. T2EX INT1 INTO TxDO RxD0O N1 N2 N3 N4 N6 6 CLKOUT T1 TO 100 5 P1 5 99 3 P1 6 98 5 P1 7 96 5 P3 6 95 5 P3 5 94 5 P34 93 5 P333 5 P3 2 91 5 P3 1 90 5 P3 0 86 5 P7 1 85 5 P7 2 84 5 P7 3 83 5 P7 4 81 L5 P7 6 CCA INT2 P1 4 N C N C N C N C CC3 INT6 P1 3 CC2 INT5 P1 2 N C CC1 INT4 P1 1 RESET CCO INT3 P1 0 P4 7 CM7 Vss P4 6 CM6 Vec P4 5 CM5 XTAL2 P4 4 CM4 XTAL1 P4 3 CM3 P2 0 A8 PE SWD P2 1 A9 P4 2 CM2 P7 7 AIN7 Vaan VAREF N C N C N C co 10 01 A Co n5 P2 2 A10 P4 1 CM1 P2 3 A11 P4 0 CMO P2 4 M2 Voc P2 5 A13 Veg P2 6 A14 RO P2 7 A15 P8 3 AIN11 PSEN P8 2 AIN10 ALE P8 1 AIN9 EA P8 0 AIN8 N C P6 7 P0 0 ADO P6 6 P0 1 AD1 P6 5 N C N C N C N C P0 2 AD2 N C AD4 32 AD5 Z 33 AD6 Z 34 P5 6 38 P5 5 0 39 P5 4 40 P5 3 Cc 41 P5 2 0 42 P5 1 2 43 P0 4 P0 5 P0 6 RxD1 P6 1 Z 47 TxD1 P6 2 Z 48 ADST P6 0 46 CCM6 CCMS5 CCM4 CCM3 CCM2 CCM1 MCP03319 Figure 1 3 Pin Configuration P MQFP 100 Package top view Semiconductor Group 1 4 1997 08 01 SIEMENS Introduction C517A 1 2 Pin Definitions and Functions This section describes all external signals of the C517A with its function Table 1 1 Pin Definitions and Functions Symbol Pin Number P MQFP 100 l O Function P1 0 P1 7 9 6 1 100 98 100 99 98 I O Port 1 is an 8 bit quasi bidirectional I O port with in
11. D CSU AL OO SIEMENS C51 A 8 Bit CM OS M icrocontroller User s M anual 08 97 C517A User s Manual Revision History Current Version 08 97 Previous Version none Page Page Subjects major changes since last revision in previous in current Version Version Edition 08 97 Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 M nchen Siemens AG 1997 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You
12. EADC IEN1 C74 C 6y C5y C4y C34 C24 Ciy Coy CO EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC IRCONO The shaded bits are not used for timer counter 2 Semiconductor Group 6 26 1997 08 01 SIEMENS On Chip Peripheral Components C517A Bit Symbol T2PS Timer 2 prescaler select bits T2PS1 Based on fosc 12 these bits define the prescaler divider ratio of the timer 2 input clock according the following table T2PS1 T2PS Timer 2 Input Clock 0 1 fosc 24 1 0 fosc 48 T2R1 Timer 2 reload mode selection T2RO T2R1 T2RO Reload Mode 0 X Reload disabled 1 0 Mode 0 auto reload upon timer 2 overflow TF2 1 1 Mode 1 reload upon falling edge at pin P1 5 T2EX T2l1 Timer 2 input selection T210 T211 T210 Input Mode 0 0 No input selected timer 2 stops 0 1 Timer function input frequency see table above 1 0 Counter function external input controlled by pin P1 7 T2 1 1 Gated timer function input controlled by pin T2 P1 7 ET2 Timer 2 Interrupt Enable If ET2 0 the timer 2 interrupt is disabled EXEN2 Timer 2 external reload interrupt enable If EXEN2 0 the timer 2 external reload interrupt is disabled The external reload function is not affected by EXEN2 EXF2 Timer 2 external reload flag Set when a reload is caused by a negative transition on pin T2EX while E
13. MD2 EBy MDU Data Register 2 MD3 ECy MDU Data Register 3 MD4 EDy MDU Data Register 4 MDS EEy MDU Data Register 5 Semiconductor Group 6 62 1997 08 01 On Chip Peripheral Components C517A SIEMENS The arithmetic control register ARCON contains control flags and the shift counter of the MDU It triggers a shift or a normalize operation in register MDO to MD3 when being written to Special Function Register ARCON Address EF Reset Value OXXXXXXXp Bit No EFH MSB 7 6 5 4 3 2 LSB 0 MDEF MDOV SLR SC 4 SC 3 SC 2 SC 1 SC 0 ARCON Bit Function MDEF Error flag Indicates an improperly performed operation MDEF is set by hardware when an operation is retriggered by a write access to MDx before the first operation has been completed MDEF is automatically cleared after being read MDOV Overflow flag Exclusively controlled by hardware MDOV is set by following events division by zero multiplication with a result greater than FFFF jj Shift direction bit When set shift right is performed SLR 0 selects shift left operation Shift counter bits When preset with 00000p normalizing is selected After operation SC 0 to SC 4 contain the number of normalizing shifts performed When set with a value 0 shift operation is started The number of shifts performed is determined by the count written to SC 0 to SC 4 S
14. The same applies to port 0 output buffers They do however require external pullups to drive floating inputs except when being used as the address data bus When used as inputs it must be noted that the ports 1 to 5 are not floating but have internal pullup transistors The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin the parameters and J in the DC characteristics specify these currents Port O as well as port 1 programmed to analog input function however have floating inputs when used for digital input Semiconductor Group 6 12 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 1 5 Read Modify Write Feature of Ports 0 to 6 Some port reading instructions read the latch and others read the pin The instructions reading the latch rather than the pin read a value possibly change it and then rewrite it to the latch These are called read modify write instructions which are listed in table 6 2 If the destination is a port or a port pin these instructions read the latch rather than the pin Note that all other instructions which can be used to read a port exclusively read the port pin In any case reading from latch or pin resp is performed by reading the SFR PO P2 and P3 for example MOV A P3 reads the value from port 3 pins while ANL P3 40AAH reads from the latch modifies the value and writes it back to the latch It is not obvious
15. Then for ports 1 to 6 the pin is pulled high by the internal pullups but can be pulled low by an external source When externally pulled low the port pins source current J or For this reason these ports are called quasi bidirectional Internal Pull Up Arrangement Int Bus Pin Write to Latch MCS01823 Figure 6 2 Basic Output Driver Circuit of Ports 1 to 6 Semiconductor Group 6 4 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 1 2 1 Port 0 Circuitry Port 0 in contrast to ports 1 to 4 is considered as true bidirectional because the port 0 pins float when configured as inputs Thus this port differs in not having internal pullups The pullup FET in the PO output driver see figure 6 3 is used only when the port is emitting 1 s during the external memory accesses Otherwise the pullup is always off Consequently PO lines that are used as output port lines are open drain lines Writing a 1 to the port latch leaves both output FETs off and the pin floats In that condition it can be used as high impedance input If port 0 is configured as general I O port and has to emit logic high level 1 external pullups are required Addr Data Control Int Bus Write to Latch MCS02434 Figure 6 3 Port 0 Circuitry Semiconductor Group 6 5 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 1 2 2 Port 1 Port 3 to Port 6 Circuitry The pins o
16. st g dA 9390 2t 99 SI 9 e S 19591 1291109 pue APIU XE ppe yo si OdMH ueemeq Kejep sri z dde eun Jojejjoso diuo uo dn uejs 1ojejjioso Dy anre JoTejioso sioeep GMO diyo uo sjoajap BopupieM Joje jioso uonejedo euJoN uondwnsuog Jamog p onp ay JojejiosQ Ou LL a Nc t0 SU0d 9jelS 160 3 jesoy jeuJeju ooo Ig QdMH A eAnoeuj QdMH 9 SS vS ES cS IS 9S Figure 9 2 Timing Diagram of Leaving Hardware Power Down Mode 1997 08 01 9 11 Semiconductor Group SIEMENS Power Saving Modes C517A MCT02759 Normal Operation P2 B P1 P2 Internal Reset Sequence 2 cycles Sample HWPD y HWPD active at least one cycle P1 P2 co o LO o T o co o N w T o co oN LO o T o co o N w T o co o LO o T o co o N o T o co N LO o Tk o co o N o T o co o LO o On Chip Oscillator Oscillator Normal Operation RC Figure 9 3 Timing Diagram of Hardware Power Down Mode HWPD Pin is active for only one cycle Semiconductor Group 9 12 1997 08 01 SIEMENS Device Specifications C517A 10 Device Specifications 10 1 Absolute Maximum Ratings Ambient temperature under bias T4 cccceceeeeeeeeeeeeeeeeeeeeeeeneeeeeeeeeeeeeenes 40 C to 110 C Storage temperature Ter c cccccecccccceeeeeneec
17. 9 data bits are received The 9th bit goes into RB81 Then a stop bit follows The port can be programmed such that when the stop bit is received the serial port 1 interrupt will be activated i e the request flag RI1 is set only if RB81 1 This feature is enabled by setting bit SM21 in S1CON A way to use this feature in multiprocessor communications is as follows If the master processor wants to transmit a block of data to one of the several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM21 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM21 bit and prepare to receive the data bytes that will be coming After having received a complete message the slave is setting SM21 again The slaves that were not addressed leave their SM21 set and go on about their business ignoring the incoming data bytes In mode B SM21 can be used to check the validity of the stop bit If SM21 1 in mode B the receive interrupt will not be activated unless a valid stop bit is received 6 5 2 3 Baud Rates of Serial Channel 1 As already mentioned serial interface 1 uses its own dedicated baud rate generator for baud rate generation in both operating mod
18. 9By SM SM21 REN1 TB81 RB81 TM RM S1CON 7 6 5 4 3 2 1 0 9Cy Serial Interface 1 Buffer Register S1BUF Bit Function SM Serial port 1 mode select bit SM 0 Serial mode A 9 bit UART SM 2 1 Serial mode B 8 bit UART SM21 Enable serial port 1 multiprocessor communication in mode A If SM21 is set to 1 in mode A RI1 will not be activated if the received 9th data bit RB81 is 0 In mode B if SM21 1 RI1 will not be activated if a valid stop bit was not received REN1 Enable receiver of serial port 1 Set by software to enable serial reception Cleared by software to disable reception TB81 Serial port 1 transmitter bit 9 TB81 is the 9th data bit that will be transmitted in mode A Set or cleared by software as desired RB81 Serial port 1 receiver bit 9 RB81 is the 9th data bit that was received in mode A In mode B if SM21 0 RB81 is the stop bit that was received TI Serial port 1 transmitter interrupt flag TI 1 is set by hardware at the beginning of the stop bit in any serial transmission Tl1 must be cleared by software H1 Serial port 1 receiver interrupt flag Hl1 is set by hardware at the halfway through the stop bit time in any serial reception RI1 must be cleared by software Semiconductor Group 6 80 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 5 2 2 Multiprocessor Communication Feature Mode A of the serial interface 1 has a special provision for multiprocessor communication In this mode
19. ADM MX2 MX1 MXO D94 ADDATH 00j 9 8 7 6 5 4 3 2 DAH ADDATL 00X i 0 XXXXp DB P7 a 6 5 4 3 2 1 0 DCH ADCON1 0XXX ADCL MX3 MX2 MX1 MXO 00005 DDy P8 3 2 1 0 DEy CTRELL 00 4 7 6 5 4 3 2 1 0 DFy CTRELH 00 4 7 6 5 4 3 2 1 0 E0 2 ACC 004 7 6 5 4 3 2 1 0 Et CTCON 0x00 T2PS1 ICR ICS CTF CLK2 CLKi CLKO 0000p E24 CML3 00y 7 6 5 4 3 2 1 0 1 X means that the value is undefined and the location is reserved 2 Shaded registers are bit addressable special function registers Semiconductor Group 3 17 1997 08 01 SIEM ENS Memory Organization C517A Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 after Reset E34 CMH3 loop 7 6 5 A 3 2 1 0 E4 CML4 loop 7 6 5 4 3 2 1 0 E54 CMH4 loop 7 6 5 4 3 2 1 0 E64 CML5 loop 7 6 5 4 3 2 1 0 E74 CMH5 loop 7 6 5 4 3 2 d 0 E842 P4 FFH CM7 CM6 CM5 CM4 CM3 CM2 CM1 CMO E94 MDO XX4 7 6 5 4 3 a 1 0 EA MD1 XXy 7 6 5 4 3 2 1 0 EB MD2 XXu 7 6 5 4 3 2 1 0 EC MD3 XXq 7 6 5 4 3 2 1 0 EDy MD4 XX4 7 6 5 4 3 2 1 0 EE MD5 xXXy_ 7 6 5 A 3 2 1 0 EFy ARCON OXXX MDEF MDOV SLR SC 4A SC3 SC 2 SC 1 SCO XXXXp FO B
20. C517A Table 1 1 Pin Definitions and Functions cont d Symbol Pin Number 1 O Function P MQFP 100 XTAL2 12 XTAL2 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL2 should be driven while XTAL1 is left unconnected Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed XTAL1 13 XTAL1 is the output of the inverting oscillator amplifier This pin is used for the oscillator operation with crystal or ceramic resonator P2 0 P2 7 14 21 O Port2 is an 8 bit quasi bidirectional I O port with internal pullup resistors Port 2 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 2 pins being externally pulled low will source current J i in the DC characteristics because of the internal pullup resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pullup resistors when issuing 1 s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register PSEN 22 O The Program Store Enable output is a control s
21. DPTR A transfer a byte from accumulator to an external location addressed by DPTR now uses this activated DPTRx Special Function Register DPSEL Address 924 Reset Value XXXXX000p Bit No MSB LSB 7 6 5 4 3 2 1 0 92H 2 3 0 DPSEL Bit Function Reserved bits for future use DPSEL 2 0 Data pointer select bits DPSEL 2 0 defines the number of the actual active data pointer DPTRO 7 Semiconductor Group 4 5 1997 08 01 SIEMENS External Bus Interface C517A DPSEL 92y DPSEL Selected Data pointer DPTR 0 DPTR 1 DPTR 2 DPL 821 DPTR 3 DPTR 4 DPTR 5 DPTR 6 DPTR 7 Eo a External Data Memory MCD00779 Figure 4 3 Accessing of External Data Memory via Multiple Datapointers 4 5 3 Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses Whenever the contents of the datapointer must be altered between two or more 16 bit addresses one single instruction which selects a new datapointer does this job If the program uses just one datapointer then it has to save the old value with two 8 bit instructions and load the new address byte by byte This not only takes more time it also requires additional space in the internal RAM 4 5 4 Application Example and Performance Analysis The following example shal
22. EXO External interrupt O enable If EXO 0 the external interrupt O is disabled Semiconductor Group 7 5 1997 08 01 SIEMENS Interrupt System C517A The SFR IEN1 includes the enable bits for the external interrupts 2 to 6 for the AD converter interrupt and for the timer 2 external reload interrupt Special Function Register IEN1 Address B81 Reset Value 00H MSB LSB BitNo BF BE BD BC BBy BA Bx B8 B84 EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC IEN1 The shaded bit is not used for interrupt control Bit Function EXEN2 Timer 2 external reload interrupt enable If EXEN2 0 the timer 2 external reload interrupt is disabled The external reload function is not affected by EXEN2 EX6 External interrupt 6 capture compare interrupt 3 enable If EX6 0 external interrupt 6 is disabled EX5 External interrupt 5 capture compare interrupt 2 enable If EX5 0 external interrupt 5 is disabled EX4 External interrupt 4 capture compare interrupt 1 enable If EX4 0 external interrupt 4 is disabled EX3 External interrupt 3 capture compare interrupt 0 enable If EX3 0 external interrupt 3 is disabled EX2 External interrupt 2 capture compare interrupt 4 enable If EX2 0 external interrupt 2 is disabled EADC Timer 2 external reload interrupt enable If EADC 0 the A D converter interrupt is disabled Semiconductor Group 7 6 199
23. ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMPO IRCON1 Bit Function ICMP7 0 Compare timer match with register CM7 CMO interrupt flags ICMPx is set by hardware when a compare match of the compare timer with the compare register CMx occurs but only if the compare function for CMx has been enabled ICMPx must be cleared by software CMSEL x 0 and CMEN x 1 Semiconductor Group 7 12 1997 08 01 SIEMENS Interrupt System C517A The compare timer interrupt is generated by bit CTF in register CTCON which is set by a rollover in the compare timer If a compare timer interrupt is generated flag CTF can be cleared by software The timer 2 compare match set and compare match clear interrupt is generated by bits ICS and ICR in register CTCON These flags are set by a match in registers COMSET and COMCLR when enabled As long as the match condition is valid the request flags can t be reset neither by hardware nor software Special Function Register CTCON Address E14 Reset Value 0X000000p MSB LSB Bit No 7 6 5 4 3 2 1 0 Eip T2PS1 ICR ICS CTF CLK2 CLK1 CLKO CTCON The shaded bits are not used for interrupt purposes Bit Function ICR Interrupt request flag for compare register COMCLR ICR is set when a compare match occured ICR is cleared ba hardware when the processor vectors to interrupt routine ICS Interru
24. If the A D converter of the C51 7A is not used register ADDATH can be used as an additional general purpose register Each A D conversion is started by writing to SFR ADDATL with dummy data If continuous conversion is selected ADDATL must be written only once to start continuous conversion Semiconductor Group 6 95 1997 08 01 SIEMENS On Chip Peripheral Components C517A Special Function Registers ADCONO Address D8 Reset Value 00H Special Function Registers ADCON1 Address DC Reset Value 0XXX0000p Bit No MSB LSB 7 6 5 4 3 2 1 0 D8H BD CLK ADEX BSY ADM MX2 MX1 MXO ADCONO DCy ADCL MX3 MX2 MX1 MXO ADCON1 The shaded bits are not used for A D converter control Bit Function Reserved bits for future use ADEX Internal external start of converrsion When set the external start of an A D conversion by a falling edge at pin P6 0 ADST is enabled BSY Busy flag This flag indicates whether a conversion is in progress BSY 1 The flag is cleared by hardware when the conversion is finished ADM A D conversion mode When set a continuous A D conversion is selected If cleared the converter stops after one A D conversion MX3 MXO A D converter input channel select bits Bits MX3 0 can be written or read either in ADCONO or ADCON1 The channel selection done by writing to ADCON 1 0 overwrites the selection in ADC
25. Serial Channel 1 Reload Reg Low Byte 9DH 00H S1RELH Serial Channel 1 Reload Reg High Byte BBH XXXX XX11p Watchdog IENO Interrupt Enable Register 0 A8 00H IEN1 Interrupt Enable Register 1 B84 00H IPO 9 Interrupt Priority Register 0 A9H 00H WDTREL Watchdog Timer Reload Register 86H 00H Pow PCON Power Control Register 87H 00H Sav Modes 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved Semiconductor Group 1997 08 01 SIEM ENS Memory Organization C517A Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 after Reset 8014 PO FFH Js 6 4 3 2 1 0 814 SP 07 7 6 5 4 3 2 1 0 82 DPL 001 7 6 5 4 3 2 1 0 834 DPH 00H 7 6 5 4 3 2 1 0 834 WDTREL 004 WDT 6 5 4 3 2 1 0 PSEL 874 PCON 00H SMOD IPDS IDLS SD GF1 GFO PDE IDLE 884 2 TCON 00H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 894 TMOD 00H GATE C T M1 MO GATE C T M1 MO 8Ay TLO 00H 4 6 5 4 3 2 1 0 8BH TL1 001 7 6 5 4 3 2 1 0 8Cy THO 001 7 6 5 4 3 2 1 0 8Dy TH1 00H a 6 5 4 3 2 1 0 90 4 P1 FFy T2 CLK T2EX INT2 INT6 INT5 JINT4 INTS3 OUT 914 XPAGE 00H y4 6 5 4 3 1 924 DPSEL XXX
26. XX11p COL IRCONO 00g EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC Cip CCEN 00H COCA COCAL COCA COCAL COCA COCAL COCA COCA H3 3 H2 2 H1 1 HO LO C24 CCL1 00H i 6 5 4 3 2 1 0 C34 CCH1 00H 7 6 5 4 i 2 1 0 C4y CCL2 00H 7 6 5 4 3 2 1 0 C5y CCH2 00H Jr 6 5 4 3 2 1 0 C6y CCL3 00H of 6 5 4 3 2 1 0 C7y CCH3 00H 7 6 5 4 3 2 1 0 C8p T2CON 00g T2PS I3FR Il2FR T2R1 T2RO T2CM T2l1 T210 C94 CCAEN 00g COCO COCO COCO COCO COCO COCA COCA COMO EN1 N2 N1 NO ENO H4 L4 1 X means that the value is undefined and the location is reserved 2 Shaded registers are bit addressable special function registers Semiconductor Group 3 16 1997 08 01 SIEM ENS Memory Organization C517A Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 after Reset CAy CRCL loog 7 6 5 4 3 2 1 0 CBQ CRCH loop 7 6 5 4 3 2 1 0 CCy TL2 00 7 6 5 A 3 F 1 0 CDy TH2 00H T 6 5 4 3 2 1 0 CEy cca foo 7 6 5 4 3 2 1 0 CFy ccH4 oo 7 6 5 A 3 2 1 0 Dop PSW loo ey Jac ro Rs Rso ov F PP Diu IRCON1 00H ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMPO D24 CMLO 00H T 6 5 4 3 2 1 0 D34 CMHO 004 7 6 5 4 3 2 1 0 D4y CML1 00H Fi 6 5 4 me 2 1 0 D54 CMH1 o l7 6 5 4 3 2 1 0 D6y CML2 00H 7 6 5 4 me 2 1 0 D7y CMH2 00H A 6 5 4 3 2 1 0 D84 ADCONO 00H BD CLK ADEX BSY
27. configuration when 8 of 16 bits are used Semiconductor Group 6 57 1997 08 01 SIEMENS On Chip Peripheral Components C517A In a compare timer CMx register configuration the compare output is set to a constant high level if the contents of the compare registers are equal to the reload register CTREL The compare output shows a high level for one timer clock period when a CMx register is set to FFFFy Thus the duty cycle can be varied from 0 xx to 100 depending on the resolution selected In figure 6 31 the maximum and minimum duty cycle of a compare output signal is illustrated One clock period of the compare timer is equal to one machine state 2 oscillator periods if the prescaler is off Thus at 12 MHz system clock the spike is approx 166 6 ns long a CMHx CMLx CTREL maximum duty cycle P4 x b CMHx CMLx FFFFy minimum duty cycle CTREL FFFFy One machine state or two oscillator cycle H 5K L MCT01854 Figure 6 31 Modulation Range of a PWM Signal Generated with a Compare Timer CMx Register Combination Semiconductor Group 6 58 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 6 Using Interrupts in Combination with the Compare Function The compare service of registers CRC CC1 CC2 CC3 and CC4 is assigned to alternate output functions at port pins P1 0 to P1 4 Another option of these pins is that they can be used as external interrupt inputs However when using the port l
28. internal data memory address space and the stack depth can be expanded up to 256 bytes The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16 bit or an 8 bit address The internal XRAM is located in the external address memory area at addresses F800 to FFFFjj Using MOVX instruction with addresses pointing to this address area alternatively internal XRAM or external data RAM are accessed 3 3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers GPRs each Only one of these banks may be enabled at a time Two bits in the program status word RS0 PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in chapter 2 This allows fast context switching which is useful when entering subroutines or interrupt service routines The 8 general purpose registers of the selected register bank may be accessed by register addressing With register addressing the instruction op code indicates which register is to be used For indirect addressing RO and R1 are used as pointer or index register to address internal or external memory e g MOV RO0 Reset initializes the stack pointer to location 074 and increments it once to start from location 084 which is also the first register RO of register bank 1 Thus if one is going to use more than one register bank the SP should be initialized to a di
29. match has requested the compare match interrupt The ICMPx flags must be cleared by software Only if timer 2 is assigned to the CMx registers compare mode 0 an ICMPx request flag is set by every match in the compare channel When the compare timer is assigned to the CMx registers compare mode 1 an ICMPx request flag will not be set by a compare match event Special Function Register IRCON1 Address D1 Reset Value 00H MSB LSB Bit No 7 6 5 4 3 2 1 0 Dip ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMPO IRCON1 Bit Function ICMP7 0 Compare timer match with register CM7 CMO interrupt flags ICMPx is set by hardware when a compare match of the compare timer with the compare register CMx occurs but only if the compare function for CMx has been enabled ICMPx must be cleared by software CMSEL x 0 and CMEN x 1 Semiconductor Group 6 61 1997 08 01 On Chip Peripheral Components C517A SIEMENS 6 4 Arithmetic Unit This on chip arithmetic unit of the C517A provides fast 32 bit division 16 bit multiplication as well as shift and normalize features All operations are unsigned integer operations The arithmetic unit further on also called MDU for Multiplication Division Unit has been integrated to support the C500 core of the C517A in real time control applications It can increase the execution speed of math intensive software routines by factor 5 to 10 The
30. no matter whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition in RxDO RxD1 Semiconductor Group 6 86 1997 08 01 SIEMENS On Chip Peripheral Components C517A g Internal Bus 2 Shift Data TX Control Tix Send Serial Port Interrupt RX Clock Rix Load SxBUF gt Transition RX Control Detector FE Shift Detector Input Shift Register 9Bits Lj Note x means that 0 or 1 can be inserted for interface 0 or interface 1 resp SxBUF Internal Bus MCS01833 Figure 6 38 Functional Diagram Serial Interfaces 0 and 1 Mode 1 Mode B Semiconductor Group 6 87 1997 08 01 SIEMENS On Chip Peripheral Components C517A Transmit MCT01936 0 o Oo w pen 0 4 c t xo 0 o x o mE 0 for serial interface 0 and x Bit Detector Note x EX amp lt Sample Times lt D Figure 6 39 Timing Diagram Serial Interfaces 0 and 1 Mode 1 Mode B Semiconductor Group 6 88 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 5 3 3 Mode 2 9 Bit UART Serial Interface 0 Mode 2 is functionally identical to mode 3 see below The only exception is that in mode 2 the baud rate can be programmed to two fixed quantities either 1 32 or 1 64 of the oscillator frequency Note that serial interface O cannot achieve this baud rate in mode 3 Its baud rate clock is gener
31. od e sng od e sng od e sng od e 3OVdX XAOMW pesn si pesn si joujeul1xe 9 pesn s Nvux 9 pesn si Nvux o Ayouieur xe 9 pesn si NvHX 9 pesn s AvHx 9 oDuej OAI oeul OAI oeul SSOJppe 9 9 HANVGH a e u e uw au a uw auta SAnOe gw data e u e uw au a uw au a INVHX eYeq HN au eeq uwaug erea uwqu z sng ed od e sna c zd od e O l lt Zd Od e sng e ed od e sng zd od e sng zd 0d e Hlda oDueiJ pesn si pesn s pesn si pesn si pesn s pesn si ssouppe AJOWOW X9 9 Kyoueur1xe o Kyoueul1xe o Kjoueul1xe o Kjoueur1xe o Kjoueul1xe o INVHX eAgo uw Qu d Aloe YM GH q endo uAvags a eue uw qau a ene HM GH G anoe uAvaus q gt Hldq sng zd od e sng zd od e sng ed od e sng zd od e sng ed od e sng zd od e Hldd XAON IX 0L 00 IX OL 00 OdVINX lL dVINX OdVINX lL dVINX L Wa 0 v3a 1997 08 01 3 10 Semiconductor Group SIEM ENS Memory Organization C517A 3 5 Special Function Registers The registers except the program counter and the four general purpose register banks reside in the special function register area All SFRs with addresses where address bits 0 2 are 0 e g 80H 88jj 90H 98H F8H FFH are bitaddressable The 93 special function registers SFRs in the SFR area include pointers and registers that provide an interface between the CPU and the other on chip peripherals The SFRs of the C517A are listed in table 3 1 and table 3
32. 3 13 3 18 6 25 B register Ls rox es eats RU EE 2 4 GMEZ cs e pe a a 3 13 3 18 6 25 Basic lIming sess wea m beue 2 5 CMSEL esses 3 13 3 18 6 51 Datapointers 4 5 to 4 8 COGAHO rere Eheu 3 16 6 43 Fetch execute diagram 2 6 COCAHT ranee Rs 3 16 6 43 Functionality a dc eee 2 3 GOGCAH 2 3 nies ane eat ee 3 16 6 43 Program status word 2 3 GOUANEIS cures quiu ederet 3 16 6 42 Stack pointer 2 4 COCAH4 ed to eeatiees 3 16 6 49 CPU timing asi at doo a TREATS 2 6 COCALO cad esed hehe od 3 16 6 43 GCHGH 5 amp 2 css 3 13 3 17 6 28 COGCGALI v da RRIERARTSSTS 3 16 6 43 CRG cave Ge Wes sve reed 3 13 3 17 6 28 GOUAL2 su saute me ES 3 16 6 43 CTCON 3 12 3 13 3 17 6 26 6 33 7 13 OOUALS S a4 eaten phot Sag 3 16 6 42 CTE m utra Seon Behe Rode See 3 17 6 33 7 13 GOGALA ra as auis ad ead 3 16 6 49 GTBREEH towel ax ful 3 13 3 17 6 34 COCOENO 5 tase aay ears 3 16 6 49 OTBEEL wv ys RES 3 13 3 17 6 34 COCOEN1 3 16 6 49 6 50 d qM 2 4 3 17 COGONG x ese hc av Sud 3 16 6 49 COCON 0 eee 3 16 6 49 Datapointers 4 5 to 4 8 COCON2 3 16 6 49 Access mechanism 4 6 COMCLRH 3 13 3 16 6 29 Basic operation 5 4 5 COMCLRL 3 13 3 15 6 29 Example using multiple DPTRs 4 8 COMO et oth etes e eset 3 16 6 49 Example using one DPTR 4 7
33. 81 6 5 2 3 Baud Rates of Serial Channel 1 anaa 6 81 6 5 3 Detailed Description of the Operating Modes 0 00 0c eee eeae 6 83 6 5 3 1 Mode 0 Synchronous Mode Serial Interface 0 0000 eee eee 6 83 6 5 3 2 Mode 1 Mode B 8 Bit UART Serial Interfaces 0 and 1 6 86 6 5 3 3 Mode 2 9 Bit UART Serial Interface 0 0 0002 ee 6 89 6 5 3 4 Mode 3 Mode A 9 Bit UART Serial Interfaces 0 and 1 6 89 6 6 10 bit A D Convener sirere nerenin I RERORERUNCHT NC UL ex ee Ree RES 6 93 6 6 1 A D Converter Operations cones uta orte et ee awed ele Se Pr eee LAS RR EH 6 93 6 6 2 A D Converter Registers 000 cece ete 6 95 6 6 3 A D Converter Clock Selection 0000 c eee eee 6 99 6 6 4 ALD Conversion TIMING a ode eese Ie PEE RE Ede RR ewes 6 100 6 6 5 A D Converter Calibration kr teen oie eel oh EUER Dex e 6 104 7 Interrupt System sou iu 939p ERR eR IMEEM LS ed 7 1 7 1 laterrupt HeglsterS x4 eese E REEESUA DEA TN EE Rau behead mele 7 5 7 1 1 Interrupt Enable Bledisters deese ida ted EORR ced PRODR CC ROS EORR 7 5 7 1 2 Interrupt Request Control Flags liliis 7 8 7 1 3 Interrupt Priority Registers s 3D tata aoe NSS MPSS ee redde 7 14 7 2 Interrupt Priority Level Structure lleliillselesslllleeren 7 15 7 3 How Interrupts are Handled 0 000 te tees 7 16 7 4 Extermal Intert pls i o2 cote c ect e Cacho etn ate Bel aad eae
34. A D conversion is stopped when the pin P6 0 ADST goes back to high level The last running A D conversion during P6 0 ADST low level will be completed The busy flag BSY ADCONO 4 is automatically set when an A D conversion is in progress After completion of the conversion it is reset by hardware This flag can be read only a write has no effect The interrupt request flag IADC IRCONO 0 is set when an A D conversion is completed The bits MXO to MX3 in special function register ADCONO and ADCON 1 are used for selection of the analog input channel The bits MXO to MX2 are represented in both registers ADCONO and ADCON 1 however these bits are present only once Therefore there are two methods of selecting an analog input channel If a new channel is selected in ADCON1 the change is automatically done in the corresponding bits MXO to MX2 in ADCONO and vice versa Port 7 and 8 are dual purpose input ports If the input voltage meets the specified logic levels it can also be used as digital inputs regardless of whether the pin levels are sampled by the A D converter at the same time Semiconductor Group 6 93 1997 08 01 SIEMENS On Chip Peripheral Components C517A internal IEN1 B8 H Bus seu Toe Tes Tee T T an IRCONO CO EXF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC P8 DD 4 SSS eee P7 DB ea re rs me ro re Pee ADCON DC H wa T TETeTeTe Tee ADCONO D8 H fege To Tos Te
35. Alternate functions 6 2 RS ipep e 2 4 3 17 Loading and interfacing 6 12 RxXDO oo 3 16 6 70 Output driver circuitry 6 9 to 6 10 PO ect Bestest ius Atel te frat Mahe ian d Se MEM 3 18 Output input sample timing 6 11 Read modify write operation 6 13 SOBUF 3 14 3 15 6 71 6 72 Types and structures SOCON 3 12 3 14 3 15 6 71 6 72 7 9 1997 08 01 SIEMENS Index C517A SOREL Fire veces e Su 3 14 3 16 6 76 IE cee Sie al ce hae a Ne ae a te 3 16 6 27 SORBEDI uctor acier 3 14 3 16 6 76 Upon er 3 16 6 27 SIBUP S i 66x0RU xS 3 14 3 15 6 80 TP EL Severe uL eun 3 16 6 27 STOON 223 3 12 3 14 3 15 6 80 7 9 T2PD1 ewe eaten ne SUI 3 17 6 27 SRE S ueris eee dhe 3 14 3 16 6 82 TRUS ed bas ot debts 3 16 6 27 SIRE 21 eee hp 3 14 3 15 6 82 MRED ios denen teet toys 3 16 6 27 SOUL os iade ibm odiis 6 63 BOO cx tres Sains ay ohare arith 2 3 15 6 71 6 72 SD vet cati eb ect Sex oh s elt 3 15 9 1 MBIT 2o ee dass ahis UL 3 15 6 80 Serial interface USART 6 70 to 6 92 TCON 3 12 3 15 6 16 7 8 Registers i eux cadre ERI PEG 6 71 TRON enusisaunses8r ese es 3 15 6 16 7 8 Serial interfaces TET 2 usu met Seine 8 3 15 6 16 7 8 Operating mode 0 6 83 to 6 85 TEZ 24 34 feb ee ee Pees 3 16 6 27 7 11 Operating mode 1 mode B 6 86 to 6 88 THO a en tres meets 3 12 3 15 6 15 Operating mode 2 and 3 mode A 6 89 to SELL tian vein Sede tah
36. Byte C2y 00H CCL2 Compare Capture Register 2 Low Byte C4y 00H CCL3 Compare Capture Register 3 Low Byte C6H 00H CCL4 Compare Capture Register 4 Low Byte CEy 00H CMEN Compare Enable Register F6H 00H CMHO Compare Register 0 High Byte D3y 00H CMH1 Compare Register 1 High Byte D5H 00H CMH2 Compare Register 2 High Byte D7H 00H CMH3 Compare Register 3 High Byte E3H 00H CMH4 Compare Register 4 High Byte E5H 00H CMH5 Compare Register 5 High Byte E7H 00H CMH6 Compare Register 6 High Byte F3H 00H CMH7 Compare Register 7 High Byte F5H 00H CMLO Compare Register 0 Low Byte D2y 00H CML1 Compare Register 1 Low Byte D4y 00H CML2 Compare Register 2 Low Byte D6y 00H CML3 Compare Register 3 Low Byte E2H 00H CML4 Compare Register 4 Low Byte E44 00H CML5 Compare Register 5 Low Byte E6H 00H CML6 Compare Register 6 Low Byte F2y 00H CML7 Compare Register 7 Low Byte F4H 00H CMSEL Compare Input Select F7H 00H CRCH Comp Rel Capt Register High Byte CBH 00H CRCL Comp Rel Capt Register Low Byte CAH 00H COMSETL Compare Set Register Low Byte Aly 00H COMSETH Compare Set Register High Byte A24 00H COMCLRL Compare Clear Register Low Byte A3H 00H COMCLRH Compare Clear Register High Byte A4y 00H SETMSK Compare Set Mask Register A5H 00H CLRMSK Compare Clear Mask Register A6H 00H CTCON Compare Timer Control Register Ely 0X00 0000p CTRELH Compare Timer Rel Register High Byte DFH 00H CTRELL Compare Timer Rel Register Low Byte DEH 0
37. Compare capture unit 6 22 DC characteristics 10 2 to 10 4 Alternate fucntions of pins 6 24 Device Characteristics 10 1 to 10 17 Block diagram 6 23 DPH LLL LLL LLL 3 12 3 15 4 5 Capture functions DPE adea me a a 3 12 3 15 4 5 Timer 2 with CRC CC1 to CC3 DPSEL de pphi ieot 3 12 3 15 4 5 Qut Pate RR Oa IER 6 45 to 6 46 Compare functions 6 36 EADC 3 16 6 98 7 6 MIX WIN COMMAS WINE eG EAD eena aeinn dine i pet 8 16 7 5 CMx with timer2 6 55 ECMP 3 15 6 60 7 7 SOMP A MOCE Peer eas Oe MEE MR MENE 3 15 6 60 7 7 Speo MOCE d Bene cent A MEE MPH 3 15 6 60 7 7 Conerentcompare MIT ic quera POT eaen Dini i 3 15 6 60 7 7 AD pw cg oeur Gr o Pan Emulation concept 44 Modulation range in compare mode 0 BO MEAM E 3 16 7 5 prose a E 99510995 I Spo e oosnratenon vested ODD Tuer compare mone d ner d DEMEURE DOE 3 16 7 5 TME 2 NUIT GING 5 CWO UU irtir SINCERE 3 16 7 5 MM DR RUM Ru ME CMM 3 16 6 27 7 5 Timer compare configurations 6 41 EO NORMA NE 3 16 7 5 peng MOTO EMT eis QA i EE DRE 3 16 7 5 Using interrupts 6 59 to 6 61 es Table of CCU SFR lt sss 625 eg LT 4674 COMSE a EE c con Cad eT pO ET Vi 3 16 7 6 COMS ED Aq an odios p c c HE P EE 3 16 7 6 Semiconductor Group 11 2 1997 08 01 SIEMENS Index C517A EXD Akt oan alight duas M erdt oes 3 16 7 6 WEN os
38. Example 2 Using Two Datapointers Code for an C517A Initialization Routine MOV DPSEL 06H Initialize DPTR6 with source pointer MOV DPTR 1FFFH MOV DPSEL 07H Initialize DPTR7 with destination pointer MOV DPTR 2FAOH Table Look up Routine under Real Time Conditions Number of cycles PUSH DPSEL Save old source pointer 2 MOV DPSEL 06H Load source pointer 2 INC DPTR Increment and check for end of table execution time CJNE not relevant for this consideration MOVC A DPTR Fetch source data byte from ROM table 2 MOV DPSEL 07H Save source pointer and sload destination pointer 2 MOVX QDPTR A Transfer byte to destination address 2 POP DPSEL Save destination pointer and restore old datapointer 2 Total execution time machine cycles 12 The above example shows that utilization of the C517A s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative Here four data variables in the internal RAM and two additional stack bytes were spared too This means for some applications where all eight datapointers are employed that an C517A program has up to 24 byte 16 variables and 8 stack bytes of the internal RAM free for other use Semiconductor Group 4 8 1997 08 01 SIEMENS External Bus Interface C517A 4 6 ROM Protection for the C517A The C517A 4R allows to protect the contents of the internal ROM against unauthorized read out The type of ROM protec
39. IEX3 External interrupt 3 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 0 INT3 CCO Cleared by hardware when processor vectors to interrupt routine IEX2 External interrupt 2 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 4 INT2 CC4 Cleared by hardware when processor vectors to interrupt routine IADC A D converter interrupt request flag Set by hardware at the end of a conversion Must be cleared by software Semiconductor Group 7 11 1997 08 01 SIEMENS Interrupt System C517A The compare timer match interrupt occurs on a compare match of the CMO to CM7 registers with the compare timer when compare mode 1 is selected for the corresponding channel There are 8 compare match interrupt flags available in SFR IRCON1 which are or ed together for a single interrupt request Thus a compare match interrupt service routine has to check which compare match has requested the compare match interrupt The ICMPx flags must be cleared by software Only if timer 2 is assigned to the CMx registers compare mode 0 an ICMPx request flag is set by every match in the compare channel When the compare timer is assigned to the CMx registers compare mode 1 an ICMPx request flag will not be set by a compare match event Special Function Register IRCON1 Address D1 Reset Value 00H MSB LSB Bit No 7 6 5 4 3 2 1 0 Dip
40. Idle Power Down ALE High Low High Low PSEN High Low High Low PORT 0 Data Data Float Float PORT 2 Data Data Address Data PORT 1 3 4 5 6 Data Data Data Data alternate outputs last output alternate outputs last output P7 0 Data Data Data Data Semiconductor Group 9 6 1997 08 01 SIEMENS Power Saving Modes C517A 9 6 Hardware Power Down Mode The power down mode of the C517A can also be initiated by an external signal at the pin HWPD Because this power down mode is activated by an external hardware signal it mode is referred to as hardware power down mode in opposite to the program controlled software power down mode Pin PE SWD has no control function for the hardware power down mode it enables and disables only the use of all software controlled power saving modes idle mode software power down mode The function of the hardware power down mode is as follows The pin HWPD controls this mode If it is on logic high level inactive the part is running in the normal operating modes If pin HWPD gets active low level the part enters the hardware power down mode as mentioned above this is independent of the state of pin PE SWD HWPD is sampled once per machine cycle If it is found active the device starts a complete internal reset sequence This takes two machine cycles all pins have their default reset states during this time This reset has exactly the same effects as a hardw
41. Io 11 6 16 2 mA 24 MHz Icc 14 6 20 4 mA Active mode with 18 MHz Io 9 5 13 1 mA slow down enabled 24 MHz ec 10 7 14 9 mA Power down mode Ipp 15 50 uA Voc 2 5 5 V9 Notes 1 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and port 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst case capacitive loading gt 100 pF the noise pulse on ALE line may exceed 0 8 V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input D Capacitive loading on ports 0 and 2 may cause the Vo on ALE and PSEN to momentarily fall below the 0 9 Voc specification when the address lines are stabilizing 9 Ipp power down mode is measured under following conditions EA RESET Port 0 Port 7 Port 8 Voc XTAL1 N C XTAL2 Vss PE SWD OWE Vas HWPD Vec for software power down mode Vaawp Vss Varer Voc all other pins are disconnected Ipp hardware power down mode is independent of any particular pin connection Eur Icc active mode is measured with XTAL2 driven with ci cH j toHcL 5ns 3 Vi Vss 0 5 V Vin Voc 0 5 V XTAL1 N C EA PE SWD Vss Port 0 Port 7 Port 8 Voc HWPD Vec RESET Voc all other pins are disconnected oO
42. MDU is handled by seven registers which are memory mapped as special function registers like any other registers for peripheral control Therefore the arithmetic unit allows operations concurrently to and independent of the CPU s activity Table 6 8 describes the four general operations the MDU is able to perform Table 6 8 MDU Operation Characteristics Operation Result Remainder Execution Time 32bit 16bit 32bit 16bit 6 toy 16bit 16bit 16bit 16bit 4 toy 16bit x 16bit 32bit 4 toy 32 bit normalize 6 toy 32 bit shift L R 6 toy 1 1 tey 12 facic 2 1 machine cycle 500 ns at 24 MHz oscillator frequency 2 The maximal shift speed is 6 shifts per machine cycle 6 4 1 MDU Register The seven SFRs of the MDU consist of registers MDO to MD5 which contain the operands and the result or the remainder resp and one control register called ARCON Thus MDO to MD5 are used twofold for the operands before a calculation has been started and for storage of the result or remainder after a calculation This means that any calculation of the MDU overwrites its operands If a program needs the original operands for further use they should be stored in general purpose registers in the internal RAM Table 6 8 list the MDU registers with its addresses Table 6 9 MDU Registers SFR Address Name ARCON EFy MDU Control Register MDO E9H MDU Data Register 0 MD1 EAH MDU Data Register 1
43. P1 5 T2EX but only if bit EXEN is set Since the external interrupt pins INT2 to INT6 are sampled once in each machine cycle an input high or low should be held for at least 12 oscillator periods to ensure sampling If the external inter rupt is transition activated the external source has to hold the request pin low high for INT2 and INTS if it is programmed to be negative transition active for at least one cycle and then hold it high low for at least one cycle to ensure that the transition is recognized so that the corresponding in terrupt request flag will be set see figure 7 5 The external interrupt request flags will automatically be cleared by the CPU when the service routine is called Semiconductor Group 7 18 1997 08 01 SIEMENS Interrupt System C517A a Level Activated Interrupt P3 x INTx Low Level Threshold 1 Machine Cycle b Transition Activated Interrupt High Level Threshold Y e g P3 x INTx Low Level Threshold 4 1 Machine Cycle 1 Machine Cycle MCD01860 Transition to be detected Figure 7 5 External Interrupt Detection 7 5 Interrupt Response Time If an external interrupt is recognized its corresponding request flag is set at S5P2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to
44. ROM verification mode 2 QUSE LES Qu RS IL ETE AC Testing P WASHER P Float waveforms 40 16 re tech na Wigs scs oye vm nt Input output waveforms 10 16 cus ae aad IU Sq UTIMS a Dig or eRe Od oak he 2 9 92 od A dan n rg mm bc 3 17 6 97 CME oes 2e 2 23 tok eaters IDEE er 3 18 ADCONO 3 12 3 14 3 17 5 8 6 73 6 96 Cub en eee EIE RCVERQURINT ERE 3 18 ADCON1 3 12 3 17 6 96 cs C M AT d ADBATEL 2528s tt howe 3 12 3 170957 ee UDIN TA ST Aa n ee ADDATL 22e teneas 3 12 3 17 6 95 em D NU EEUU um e E ADM iili apese OMM 3 13 3 17 625 ADST essnee oa Ee ae imi aa eis 3 18 CMH2 22 sees 9 19 9 17 6 29 ARCON 3 12 3 18 6 63 CMH3 Su ni eru E 3 13 3 18 6 25 GMH uds eR na Me 3 13 3 18 6 25 B CMHS S fovit oe pis 3 13 3 18 6 25 B ZEE Preis a Meet erudi 2 4 3 12 3 18 CMH6 3 13 3 18 6 25 Basic CPU timirig 24 0234 ner ade 2 5 CMH7 3 13 3 18 6 25 BD ZI LLL 3 17 6 73 CMLO 3 13 3 17 6 25 Block diagram ice vest oe wetter eed 2 2 CML1 3 13 3 17 6 25 BS wagm sed onan bemw semis ee 3 17 6 96 CML2 3 13 3 17 6 25 CMES is Fo ears eh ed 3 13 3 17 6 25 Semiconductor Group 11 1 1997 08 01 SIEMENS gee C517A CML4 ote tee eee at 3 13 3 18 6 25 CPU GMES to tiens 3 13 3 18 6 25 Accumulator 00 006 2 3 OMEDO 5 Ste RDtEGX Ses
45. T 0 Ts ero TLO TRO TFO Interrupt A oO 5 Bits 8 Bits C T 1 Gate fa H P3 2 INTO Control MCS02583 Figure 6 9 Timer Counter 0 Mode 0 13 Bit Timer Counter Semiconductor Group 6 18 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 2 1 3 Mode 1 Mode 1 is the same as mode 0 except that the timer register is running with all 16 bits Mode 1 is shown in figure 6 10 y CIT 0 Interrupt TLO THO TFO A 8 Bits 8 Bits C T 1 P3 4 T0 P3 2 INTO Control MCS02095 Figure 6 10 Timer Counter 0 Mode 1 16 Bit Timer Counter Semiconductor Group 6 19 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 2 1 4 Mode 2 Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in figure 6 11 Overflow from TLO not only sets TFO but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged Interrupt P3 4 T0 Gate P3 2 INTO MCS02140 Figure 6 11 Timer Counter 0 1 Mode 2 8 Bit Timer Counter with Auto Reload Semiconductor Group 6 20 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 2 1 5 Mode 3 Mode 3 has different effects on timer O and timer 1 Timer 1 in mode 3 simply holds its count The effect is the same as setting TR120 Timer 0 in mode 3 establishes TLO and THO as two seperate counters The logic for mode 3 on timer 0 i
46. TB80 or a second stop bit by setting TB80 to 1 On reception the 9th data bit goes into RB80 in special function register SOCON while the stop bit is ignored The baud rate is programmable to either 1 32 or 1 64 of the oscillator frequency See section 6 5 3 3 for more detailed information Mode 3 9 bit UART variable baud rate 11 bits are transmitted through TXDO or received through RXDO a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 On transmission the 9th data bit TB80 in SOCON can be assigned to the value of 0 or 1 For example the parity bit P in the PSW could be moved into TB80 or a second stop bit by setting TB80 to 1 On reception the 9th data bit goes into RB80 in special function register SOCON while the stop bit is ignored In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable See section 6 5 3 4 for more detailed information Semiconductor Group 6 70 1997 08 01 SIEMENS On Chip Peripheral Components C517A In all four modes transmission is initiated by any instruction that uses SOBUF as a destination register Reception is initiated in mode 0 by the condition RIO 0 and RENO 1 Reception is initiated in the other modes by the incoming start bit if RENO 1 The serial interfaces also provide interrupt requests when a transmission or a reception of a frame has completed The corresponding interrupt request flags for s
47. The whole operation is completed when the MSB most significant bit contains a 1 To select a normalize operation the five bit field ARCON O to ARCON 4 must be cleared That means a write to ARCON instruction with the value XXX0 0000p starts the operation After normalizing bits ARCON 0 to ARCON 4 contain the number of shift left operations which were done This number may further on be used as an exponent The maximum number of shifts in a normalize operation is 31 25 1 The operation takes six machine cycles at most that means 3 microseconds at 24 MHz Shifting In the same way by a write to ARCON instruction a shift left right operation can be started In this case register bit SLR ARCON 5 has to contain the shift direction and ARCON 0 to ARCON 4 the shift count which must not be 0 otherwise a normalize operation would be executed During shift zeroes come into the left or right end of the registers MDO or MD3 respectively The first machine cycle of a shift left right operation executes four shifts while all following cycles perform 6 shifts Hence a 31 bit shift takes 3 microseconds at 24 MHz After starting a shift left right operation by writing to ARCON at least one machine cycle delay e g a NOP instruction must be executed before accessing the MDO 3 result registers Completion of both operations normalize and shift can also be controlled by the error flag mechanism The error flag is set if one of the
48. and the compare timer are mainly dedicated to PWM applications The compare registers CMO to CM7 however are not permanently assigned to the compare timer each register may individually be configured to work either with timer 2 or the compare timer This flexible assignment of the CMx registers allows an independent use of two time bases whereby different application requirements can be met Any CMx register connected to the compare timer automatically works in compare mode 0 e g to provide fast PWM with low CPU intervention CMx registers which are assigned to timer 2 operate in comare mode 1 This allows the CPU to control the compare output transitions directly The assignment of the eight registers CMO to CM7 to either timer 2 or to the compare timer is done by a multiplexer which is controlled by the bits in the SFR CMSEL The compare function itself can individually be enabled in the SFR CMEN These two registers are not bit addressable This means that the value of single bits can only be changed by AND ing or OR ing the register with a certain mask Special Function Register CMSEL Address F7 Reset Value 00H Special Function Register CMEN Address F6jj Reset Value 00H MSB LSB Bit No 7 6 5 4 3 2 1 0 F7u sf 6 Es 4 3 2 0 CMSEL 7 6 3 2 1 F6H T 6 Es 4 3 2 0 CMEN Bit Function CMSEL 7 0 Select bits for CMx registers x 0 7 When set the CMLx CMH
49. approx 1 1 s at 12 MHz an oscillator watchdog OWD which monitors the on chip oscillator and forces the microcontroller into reset state in case the on chip oscillator fails it also provides the clock for a fast internal reset after power on 8 1 Programmable Watchdog Timer To protect the system against software upset the user s program has to clear this watchdog within a previously programmed time period If the software fails to do this periodical refresh of the watchdog timer an internal hardware reset will be initiated The software can be designed so that the watchdog times out if the program does not work properly It also times out if a software error is based on hardware related problems The watchdog timer in the C517A is a 15 bit timer which is incremented by a count rate of fosc 24 up to fos 384 The system clock of the C517A is divided by two prescalers a divide by two and a divide by 16 prescaler For programming of the watchdog timer overflow rate the upper 7 bit of the watchdog timer can be written Figure 8 1 shows the block diagram of the watchdog timer unit WDT Reset Request lt IPO 0A9 H WDTPSEL n External HW Reset B External HW Power Down 5 PE SWD MCB03336 Control Logic Figure 8 1 Block Diagram of the Programmable Watchdog Timer Semiconductor Group 8 1 1997 08 01 SIEMENS Fail Safe Mechanisms C517A 8 1 1 Input Clock Selection The input cloc
50. bits ITO and IT1 in SFR TCON The flags that actually generate these interrupts are bits IEO and IE1 in SFR TCON When an external interrupt is generated the flag that generated this interrupt is cleared by the hardware when the service routine is vectored to but only if the interrupt was transition activated If the interrupt was level activated then the requesting external source directly controls the request flag rather than the on chip hardware The timer 0 and timer 1 interrupts are generated by TFO and TF1 in register TCON which are set by a rollover in their respective timer counter registers exception is timer 0 in mode 3 When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to Special Function Register TCON Address 884 Reset Value 00H MSB LSB Bit No 8Fy 8Ey 8Dy 8Cy 8By 8Ay 89H 88H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO TCON The shaded bits are not used for interrupt purposes Bit Function TF1 Timer 1 overflow flag Set by hardware on timer counter 1 overflow Cleared by hardware when processor vectors to interrupt routine TFO Timer 0 overflow flag Set by hardware on timer counter 0 overflow Cleared by hardware when processor vectors to interrupt routine IE1 External interrupt 1 request flag Set by hardware Cleared by hardware when processor vectors to interrupt routine if IT1 1 or b
51. clock fApc 1 tapc and the input clock fiy 71 tjN Both clock signals are derived from the C517A system clock fosc which is applied at the XTAL pins The input clock fiy is always fosc 2 while the conversion clock must be adapted to the input clock fosc The conversion clock is limited to a maximum frequency of 2 MHz Therefore the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz The prescaler is selected by the bit ADCL in SFR ADCON1 The table in figure 6 43 shows the prescaler ratio which must be selected for typical system clock rates Up to 16 MHz system clock the prescaler ratio 4 is selected Using a system clock greater than 16 MHz max 24 MHz the prescaler ratio of at least 8 must be selected The prescaler ratio 8 is recommended when the input impedance of the analog source is to high to reach the maximum accuracy Conversion Clock fApc A D Converter Clock Prescaler Input Clock fin f Conditions fapcmax lt 2 MHz fin OSC 5 2 MCS03264 MCU System Clock fiw Prescaler Rate fosc MHz Ratio 3 5 MHz 1 75 4 12 MHz 6 4 16 MHz 8 4 18 MHz 9 8 24 MHz 8 Figure 6 43 A D Converter Clock Selection The duration of an A D conversion is a multiple of the period of the fiy clock signal The calculation of the A D conversion time is shown in the next section Semiconductor Group 6 99 1997 08 01 SIEMENS On Chip P
52. compare or capture functions Compare timer for compare capture functions Powerful 16 bit compare capture unt CCU with up to 21 high speed or PWM output channels and 5 capture inputs e 10 bit A D converter 12 multiplexed analog inputs Built in self calibration Extended watchdog facilities 15 bit programmable watchdog timer Oscillator watchdog Power saving modes Slow down mode dle mode can be combined with slow down mode Software power down mode Hardware power down mode 17 interrupt sources 7 external 10 internal selectable at 4 priority levels On chip emulation support logic Enhanced Hooks Technology e P MQFP 100 package e Temperature Ranges SAB C517A 7 0to 70 C SAF C517A T 40 to 85 C SAH C517A T4 40to 110 C Semiconductor Group 1 2 1997 08 01 SIEMENS Introduction C517A Port 7 8 bit Analog Digital Input Port 0 Port 8 8 Bit Digital 1 0 4 bit Analog Digital Input Port 1 8 Bit Digital I O XTAL1 XTAL2 Port 2 ALE 8 Bit Digital I O PSEN Port 3 EA 8 Bit Digital I O RESET Port 4 PE SWD 8 Bit Digital I O OWE Port 5 RO 8 Bit Digital I O HWPD Port 6 8 Bit Digital l O VAREF VAGND MCL03318 Figure 1 2 Logic Symbol Semiconductor Group 1 3 1997 08 01 SIEMENS Introduction C517A 1 4 Pin Configuration This section describes the pin configuration of the C517A in the P MQFP 100 package
53. control applications ignition injection control anti lock brakes etc as well as for industrial applications DC three phase AC and stepper motor control frequency generation digital to analog conversion process control etc The detailed description in the following sections refers to the CCU s functional blocks as listed below Timer 2 with fosc 12 input clock 2 bit prescaler 16 bit reload counter gated timer mode and overflow interrupt request Compare timer with fosc 2 input clock 3 bit prescaler 16 bit reload and overflow interrupt request Compare reload capture register array consisting of four different kinds of registers one 16 bit compare reload capture register three 16 bit compare capture registers one 16 bit compare capture register with additional concurrent compare feature eight 16 bit compare registers with timer overflow controlled loading In summary the register array may control up to 21 output lines and can request up to 7 independent interrupts In the following text all double byte compare compare capture or compare reload capture registers are called CMx x 0 7 CCx x 0 4 or CRC register respectively The block diagram in figure 6 13 shows the general configuration of the CCU All CC1 to CC4 registers and the CRC register are exclusively assigned to timer 2 Each of the eight compare registers CMO through CM7 can either be assigned to timer 2 or to the faster compare
54. detected the divide by 16 counter is immediately reset and 1FFj is written into the input shift register and reception of the rest of the frame will proceed The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXDO RXD1 The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back looking for another 1 to 0 transition This is to provide rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come from the right 1 s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 B is a 9 bit register it flags the RX control block to do one last shift The signal to load SOBUF S1BUF and RB80 RB81 and to set RIO RI1 will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RIO RI1 0 and 2 either SM20 SM21 0 or the received stop bit 1 If one of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB80 RB81 the 8 data bits go into SOBUF S1BUF and RIO RI1 is activated At this time
55. function The timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction In this mode no interrupt request will be generated Figures 6 23 and 6 24 show functional diagrams of the capture function of timer 2 Figure 6 23 illustrates the operation of the CRC or CC4 register while figure 6 24 shows the operation of the compare capture registers CC1 to CC3 The two capture modes are selected individually for each capture register by bits in SFR CCEN compare capture enable register and CC4EN compare capture 4 enable register That means in contrast to the compare modes it is possible to simultaneously select capture mode 0 for one capture register and capture mode 1 for another register Semiconductor Group 6 45 1997 08 01 SIEMENS On Chip Peripheral Components C517A Timer 2 TL2 TH2 TF2 Interrupt Request Write to _ E Fed l Capture P1 0 INT 3 CCo o T2CON6 in External ae IEX3 Interrupt 3 Request MCS01855 Figure 6 23 Capture with Registers CRC CC4 Timer 2 TL2 TH2 TF2 Interrupt Request Write to B T p I Capture l P1 1 INT 4 External CC1 O _ gt PA IEX4 Interrupt 4 Request MCS01856 Figure 6 24 Capture with Registers CC1 to CC3 Semiconductor Group 6 46 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 4 3 Compare Function of Register CC4 Concurrent Compare Compare register CC4 is permanently a
56. is completed after phase III in figure 5 2 When an external clock generator is used phase ll is very short Therefore an external reset time of typically 1 ms is sufficent in most applications Generally for reset time generation at power on an external capacitor can be applied to the RESET pin Semiconductor Group 5 3 1997 08 01 C517A Reset System Clock SIEMENS cLc000N uolnoexe jeubis 10S91 xo Jo osneooQ a es9J ul SUIeUJOJ Od So o 897 Xew qM J0 eII10S0 Aq eouenbes 9SOJ EUIJ Spejs 4o0jej ioso diuo uo Srl ye xew si gi dh yog Japun UQ 13M0d SHOd Ie Jasay Jo0je iosQ oH Wo1 490 E X Ex josoH Jepun JojejiosQ Joje iosQ diu5 uo Power On Reset of the C517A Figure 5 2 1997 08 01 5 4 Semiconductor Group SIEMENS Reset System Clock C517A 5 3 Hardware Reset Timing This section describes the timing of the hardware reset signal The input pin RESET is sampled once during each machine cycle This happens in state 5 phase 2 Thus the external reset signal is synchronized to the internal CPU timing When the reset is found active low level the internal reset procedure is started It needs two complete machine cycles to put the complete device to its correct reset state i e all special function registers contain their default values the port latches contain 1 s etc Note that this re
57. line of the port latch are disconnected when compare mode 0 is enabled Compare mode 0 is ideal for generating pulse width modulated output signals which in turn can be used for digital to analog conversion via a filter network or by the controlled device itself e g the inductance of a DC or AC motor Compare mode 0 may also be used for providing output clocks with initially defined period and duty cycle This is the mode which needs the least CPU time Once set up the output goes on oscillating without any CPU intervention Figure 6 18 illustrates the function of compare mode 0 Port Circuit Compare Register Circuit Compare Reg Internal Bus LIO wi Compare Writeto Match Latch Timer Register IL Timer Circuit Timer Overflow Read Pin MCS02661 Figure 6 17 Port Latch in Compare Mode 0 Figure 6 18 shows a typical output signal waveform which is generated when compare mode 0 is selected Semiconductor Group 6 37 1997 08 01 SIEMENS On Chip Peripheral Components C517A Timer Count FFFFy Timer Count Contents Compare Value of a Timer Register Timer Count Reload Value Interrupt can be generated on overflow Compare Output P1 x CCx j MCTO1846 Interrupt can be generated on compare match Figure 6 18 Output Waveform of Compare Mode 0 Modulation Range of a PWM Signal and Differences between the Two Timer Compare Regist
58. must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain hu man life If they fail it is reasonable to assume that the health of the user may be endangered SIEMENS General Information C517A Table of Contents Page 1 INTFOGUCHON DER 1 1 1 1 Pin Configuration s seer peniana RPRSRIS RR EXGC uA beens cake eee Res 1 4 1 2 Pin Definitions and Functions 32 t ke eee ez eae Srt 1 5 2 Fundamental Structure 0 000 teas 2 1 2 1 GPU qp prc 2 3 2 2 PUP Gia neha h te a Paco Bar e Sac n welts terete Pont het Dad n acce 2 5 3 Memory Organization 0 60 ceca 3 1 3 1 Program Memory Code Space 0 200s 3 2 3 2 Data Memory Data Spa
59. normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt and the bit will have to be cleared by software Special Function Register SOCON Address 984 Reset Value 00H Special Function Register S1CON Address 9By Reset Value 0X000000p MSB LSB Bit No 9Fu 9E 9Dy 9Cy 9By 9AH 994 984 981 SMO SM10 SM20 RENO TB80 RB80 TIO RIO SOCON 7 6 5 4 3 2 1 0 9By SM SM21 REN1 TB81 RB81 TH Rl1 S1CON The shaded bits are not used for interrupt purposes Bit Function TIO Serial interface 0 transmitter interrupt flag Set by hardware at the end of a serial data transmission Must be cleared by software RIO Serial interface 0 receiver interrupt flag Set by hardware if a serial data byte has been received Must be cleared by software TI1 Serial interface 1 transmitter interrupt flag Set by hardware at the end of a serial data transmission Must be cleared by software H1 Serial interface 1 receiver interrupt flag Set by hardware if a serial data byte has been received Must be cleared by software Semiconductor Group 7 9 1997 08 01 SIEMENS Interrupt System C517A The external interrupt 2 INT2 CC4 can be either positive or negative transition activated depending on bit I2FR in register T2CON The flag that actually generates this interrupt is bit I
60. not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The polling cycle LCALL sequence is illustrated in figure 7 4 gt lt S5P2 Wo Interrupts Long Call to Interrupt Interrupt Interrupt are polled Vector Address Routine is latched MCT01859 Figure 7 4 Interrupt Response Timing Diagram Semiconductor Group 7 16 1997 08 01 SIEMENS Interrupt System C517A Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7 4 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt while in other cases it does not Then this has to be done by the user s software The hardware clears the external interrupt flags IEO and IE1 only if they were transition activated The hardware generated LCALL pushes the contents of the program counter onto the stack but it does not save the PSW and reloads the program counter with an address that depends on the source of the interrupt being vectored to as shown in table 7 2 Table 7 2 Interrupt Source and Vectors
61. of the flags was in a set condition at S5P2 of the preceeding cycle the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to registers IENO IEN1 IEN2 or IPO IP1 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to the IEN or IP registers then at least one more instruction will be executed before any interrupt is vectored to this delay guarantees that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but
62. one following the instruction that sets the bits IDLS and SD Nevertheless the slow down mode keeps enabled and if required has to be disabled by clearing the bit SD in the corresponding interrupt service routine or after the instruction that sets the bits IDLS and SD The other possibility of terminating the combined idle and slow down mode is a hardware reset Since the oscillator is still running the hardware reset has to be held active for only two machine cycles for a complete reset Semiconductor Group 9 4 1997 08 01 SIEMENS Power Saving Modes C517A 9 4 Software Power Down Mode In the software power down mode the RC osciillator and the on chip oscillator which operates with the XTAL pins is stopped Therefore all functions of the microcontroller are stopped and only the contents of the on chip RAM XRAM and the SFR s are maintained The port pins which are controlled by their port latches output the values that are held by their SFR s The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the software power down mode ALE and PSEN hold at logic low level see table 9 1 In the software power down mode of operation Vc can be reduced to minimize power consumption It must be ensured however that is Voc not reduced before the software power down mode is invoked and that Vcc is restored to its normal operating level before the softw
63. one of four priority levels by setting or clearing a bit in the IPO and IP1 priority registers Further deails abaout the interrupt priority structure are given in chapter 7 2 Special Function Register IPO Address A9 Reset Value 00H Special Function Register IP1 Address B94 Reset Value XX000000p MSB LSB Bit No 7 6 5 4 3 2 1 0 A94 OWDS WDTS IPO 5 IPO 4 IPOS3 IPO 2 IPO 1 IPO O IPO 7 6 5 4 3 2 1 0 BOY IP1 5 IP1 4 IP1 3 IP1 2 IP1 1 IP1 0 IP1 The shaded bits are not used for interrupt purposes Bit Function IP1 x Interrupt Priority level bits x 0 5 dio IPi x IPO x Function 0 0 Interrupt group x is set to priority level 0 lowest 0 1 Interrupt group x is set to priority level 1 1 0 Interrupt group x is set to priority level 2 1 1 Interrupt group x is set to priority level 3 highest Semiconductor Group 7 14 1997 08 01 Interrupt System C517A SIEMENS 7 2 The 17 interrupt sources of the C517A are combined in six groups Table 7 1 lists the structure of these interrupt groups Interrupt Priority Level Structure Table 7 1 Interrupt Source Structure Interrupt Associated Interrupts Priority Group High Priority F Low Priority 1 External interrupt 0 Serial port 1 interrupt A D converter interrupt High 2 Timer 0 overflow External interrupt 2 3 Ext
64. open drain port but uses a strong internal pullup FET 6 1 1 Port Structures The C517A generally allows digital I O on 56 lines grouped into 7 bidirectional C501 compatible 8 bit ports and one 8 bit and one 4 bit analog digital input port Each port bit except port 7 8 consists of a latch an output driver and an input buffer Read and write accesses to the I O ports PO to P6 are performed via their corresponding special function registers Depending on the specific ports multiple functions are assigned to the port pins These alternate functions of the port pins are listed in table 6 1 When port 7 or 8 is used as analog input an analog channel is switched to the A D converter through a 4 bit multiplexer which is controlled by three bits in SFR ADCON1 Port 6 lines may also be used as digital inputs In this case they are addressed as an input port via SFR P7 or P8 Since ports 7 and 8 have no internal latch the contents of SFR P7 or P8 only depends on the levels applied to the input lines It makes no sense to output a value to these input only port by writing to the SFR P7 or P8 This will have no effect Semiconductor Group 6 1 1997 08 01 SIEMENS On Chip Peripheral Components C517A Table 6 1 Alternate Functions of Port 1 3 4 5 and 6 Port Alternate Description Functions P1 0 INT3 CCO External Interrupt 3 input Capture compare 0 input output P1 1 INT4 CC1 External Interrupt 4 input Capture compar
65. overwritten before the timer had the chance to reach the previously loaded compare value Hence there must be something to synchronize the loading of the compare registers to the running timer circuitry This could either be an interrupt caused by the timer circuitry as described before or a special hardware circuitry Thus TOC loading means that there is dedicated hardware in the CCU which synchronizes the loading of the compare registers CMx in such a way that there is no loss of compare events It also relieves the CPU of interrupt load A CMx compare register in compare mode 0 consists of two latches When the CPU tries to access a CMx register it only addresses a register latch and not the actual compare latch which is connected to the comparator circuit The contents of the register latch may be changed by the CPU at any time because this change would never affect the compare event for the current timer period The compare latch the actual latch holds the compare value for the present timer period Thus the CPU only changes the compare event for the next timer period since the loading of the latch is performed by the timer overflow signal of the compare timer This means for an application which uses several PWM outputs that the CPU does not have to serve every single compare line by an individual interrupt It only has to watch the timer overflow of the compare timer and may then set up the compare events of all compares for the next
66. relevant registers MDO through MD3 is accessed before the previously commenced operation has been completed Semiconductor Group 6 67 1997 08 01 SIEMENS On Chip Peripheral Components C517A For proper operation of the error flag mechanism it is necessary to take care that the right write or read sequence to or from registers MDO to MD3 see table 6 11 is maintained Table 6 11 Programming a Shift or Normalize Operation Operation Normalize Shift Left Shift Right First write MDO least significant byte MD1 MD2 MD3 most significant byte Last write ARCON start of conversion First read MDO least significant byte MD1 MD2 Last read MD3 most significant byte 6 4 5 The Overflow Flag An overflow flag is provided for some exceptions during MDU calculations There are three cases where flag MDOV ARCON 6 is set by hardware Division by zero Multiplication with a result greater then 0000 FFFFH auxiliary carry of the lower 16bit Start of normalizing if the most significant bit of MD3 is set MD3 7 1 Any operation of the MDU which does not match the above conditions clears the overflow flag Note that the overflow flag is exclusively controlled by hardware It cannot be written to 6 4 6 The Error Flag The error flag bit MDEF in register ARCON is provided to indicate whether one of the arithmetic operations of the MDU multiplication division normalize shift left right has been restarted o
67. reset the pins will be in IL state latch is set to 1 voltage level on pin is below of the trip point of p3 Depending on the voltage level and load applied to the pin it will remain in this state or will switch to IH SOH state If itis used as output the weak pull up p2 will pull the voltage level at the pin above p3 s trip point after some time and p3 will turn on and provide a strong 1 Note however that if the load exceeds the drive capability of p2 J the pin might remain in the IL state and provide a week 1 until the first O to 1 transition on the latch occurs Until this the output level might stay below the trip point of the external circuitry The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at 0 and the load then exceeds the p2 drive capabilities If the load exceeds the pin can be forced to 1 by writing a 0 followed by a 1 to the port pin Semiconductor Group 6 10 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 1 3 Port Timing When executing an instruction that changes the value of a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction However port latches are only sampled by their output buffers during phase 1 of any clock period during phase 2 the output buffer holds the value it noticed during the previous phase 1 Consequently the new value in the po
68. resistors are required during program verification 36 Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C517A A low level for a longer period will force the part into hardware power down mode with the pins floating There is no internal pullup resistor connected to this pin P5 0 P5 7 44 37 I O Port 5 is a quasi bidirectional I O port with internal pull up resistors Port 5 pins that have 1 s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 5 pins being externally pulled low will source current J in the DC characteristics because of the internal pull up resistors This port also serves the alternate function Concurrent Compare and Set Reset Compare The secondary functions are assigned to the port 5 pins as follows CCMO to CCM7 P5 0to P57 concurrent compare or Set Reset lines Input O Output Semiconductor Group 1 7 1997 08 01 SIEMENS Introduction C517A Table 1 1 Pin Definitions and Functions contd Symbol Pin Number 1 O P MQFP 100 Function OWE 45 l Oscillator Watchdog Enable A high level on this pin enables the oscillator watchdog When left unconnected this pin is pulled high by a weak internal pull up resisitor The logic level at OWE should not be changed during normal operation Whe
69. same functionality in its asynchronous modes but the synchronous mode is missing 6 5 1 Serial Interface 0 6 5 1 1 Operating Modes of Serial Interface 0 The serial interface 0 can operate in four modes one synchronous mode three asynchronous modes The baud rate clock for this interface is derived from the oscillator frequency mode 0 2 or generated either by timer 1 or by a dedicated baud rate generator mode 1 3 A more detailed description of how to set the baud rate will follow in section 6 5 1 4 Mode 0 Shift register synchronous mode Serial data enters and exits through RxDO TxDO outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at 1 6 of the oscillator frequency See section 6 5 3 1 for more detailed information Mode 1 8 bit UART variable baud rate 10 bits are transmitted through TXDO or received through RXDO a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB80 in special function register SOCON The baud rate is variable See section 6 5 3 2 for more detailed information Mode 2 9 bit UART fixed baud rate 11 bits are transmitted through TXDO or received through RXDO a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 On transmission the 9th data bit TB80 in SOCON can be assigned to the value of 0 or 1 For example the parity bit P in the PSW could be moved into
70. specified logic levels With RESET going inactive the ROM verification mode 2 sequence is started The C517A outputs an ALE signal with a period of 12 tc cj and expects data bytes at port 0 The data bytes at port 0 are assigned to the ROM addresses in the following way 1 Data Byte content of internal ROM address 0000H 2 Data Byte content of internal ROM address 0001H 3 Data Byte content of internal ROM address 00024 16 Data Byte content of internal ROM address 000FH The C517A 4R does not output any address information during the ROM verification mode 2 The first data byte to be verified is always the byte which is assigned to the internal ROM address 00004 and must be put onto the data bus with the falling edge of RESET With each following ALE pulse the ROM address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally Between two ALE pulses the data at port 0 is latched at 3 CLP after ALE rising edge and compared internally with the ROM content of the actual address If an verify error is detected the error Semiconductor Group 4 10 1997 08 01 SIEMENS External Bus Interface C517A condition is stored internally After each 16th data byte the cumulated verify result pass or fail of the last 16 verify operations is output at P3 5 This means that P3 5 stays at static level low for fail and high for pass during the 16 bytes are checked In ROM verification
71. that the last three instructions in table 6 2 are read modify write instructions but they are The reason is that they read the port byte all 8 bits modify the addressed bit then write the complete byte back to the latch Table 6 2 Read Modify Write Instructions Instruction Function ANL Logic AND e g ANL P1 A ORL Logic OR e g ORL P2 A XRL Logic exclusive OR e g XRL P3 A JBC Jump if bit is set and clear bit e g JBC P1 1 LABEL CPL Complement bit e g CPL P3 0 INC Increment byte e g INC P4 DEC Decrement byte e g DEC P5 DJNZ Decrement and jump if not zero e g DJNZ P3 LABEL MOV Px y C Move carry bit to bit y of port x CLR Px y Clear bit y of port x SETB Px y Set bit y of port x The reason why read modify write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transitor approx 0 7 V i e a logic low level and interpret it as 0 For example when modifying a port bit by a SETB or CLR instruction another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to th latch However
72. the wave of a rectangular output signal at a port pin This may as a variation of the duty cycle of a periodic signal be used for pulse width modulation as well as for a continually controlled generation of any kind of square wave forms In the case of the C517A two compare modes are implemented to cover a wide range of possible applications In the C517A thanks to the high number of 13 compare registers and two associated timers several timer compare register combinations are selectable In some of these configurations one of the two compare modes may be freely selected Others however automatically establish a compare mode In the following the two possible modes are generally discussed This description will be referred to in later sections where the compare registers are described Semiconductor Group 6 36 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 3 1 Compare Mode 0 In mode 0 upon matching the timer and compare register contents the output signal changes from low to high It goes back to a low level on timer overflow As long as compare mode 0 is enabled the appropriate output pin is controlled by the timer circuit only and not by the user Writing to the port will have no effect Figure 6 17 shows a functional diagram of a port circuit when used in compare mode 0 The port latch is directly controlled by the timer overflow and compare match signals The input line from the internal bus and the write to latch
73. timer 1 count rolls over from all ones to the reload value When CTF is set a compare timer interrupt can be generated if enabled CTF is cleared by hardware RETI instruction when the compare timer value is no more equal to the reload value Semiconductor Group 6 33 1997 08 01 SIEMENS On Chip Peripheral Components C517A Bit Function CLK2 Compare timer input clock selection CLK1 These bits define the prescaler divider ratio of the compare timer input CLKO clock according to the following table CLK2 CLK1 CLKO Compare Timer Input Clock 0 0 0 fosc 2 0 1 0 fosc 8 0 1 1 fosc 16 1 0 0 fosc 32 1 0 1 fosc 64 1 1 0 fosc 128 1 1 1 fosc 256 Special Function Register CTRELL Address DE Reset Value 00H Special Function Register CTRELH Address DF Reset Value 00H MSB LSB Bit No 7 6 5 4 3 2 1 0 DEH vs 5 4 3 2 A 0 CTRELL DFy 4 6 5 4 3 2 A 0 CTRELH Bit Function CTRELL 7 0 Compare timer reload value low part The CTRELL register holds the lower 8 bits of the 16 bit reload value for the compare timer CTRELH 7 0 Compare timer reload value high part The CTRELH register holds the upper 8 bits of the 16 bit reload value for the compare timer Semiconductor Group 6 34 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 2 2 Operating Modes of the Compare Timers The compare timer receives its in
74. triggers the actual reload procedure mentioned above The 16 bit reload value can be overwritten at any time Semiconductor Group 6 35 1997 08 01 SIEMENS On Chip Peripheral Components C517A The compare timer has as any other timer in the C517A its own interrupt request flag CTF This flag is located in register CTCON CTF is set when the timer count rolls over from all ones to the reload value CTF is reset by hardware when the compare timer value is no more equal to the reload value The compare timer overflow interrupt eases e g software control of pulse width modulated output signals A periodic interrupt service routine caused by an overflow of the compare timer can be used to load new values in the assigned compare registers and thus change the corresponding PWM output accordingly More details about interrupt control are discussed in chapter 7 6 3 3 Compare Functions of the CCU The compare function of a timer register combination can be described as follows The 16 bit value stored in a compare or compare capture register is compared with the contents of the timer register If the count value in the timer register matches the stored value an appropriate output signal is generated at a corresponding port pin The contents of a compare register can be regarded as time stamp at which a dedicated output reacts in a predefined way either with a positive or negative transition Variation of this time stamp somehow changes
75. voltage level within the indicated time The maximum internal resistance results from the programmed conversion timing 6 Not 100 tested but guaranteed by design characterization Semiconductor Group 10 6 1997 08 01 SIEMENS Device Specifications C517A 10 4 AC Characteristics 18 MHz Voc 5 V 10 15 Vss 0 V T 0 to 70 C for the SAB C517A T 40 to 85 C for the SAF C517A T 40 to 110 C for the SAH C517A C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 18 MHz Variable Clock Clock 1 teic 3 5 MHz to 18 MHz min max min max ALE pulse width fiu 71 2 toc 40 ns Address setup to ALE AVLL 26 toric 30 ns Address hold after ALE fL LAX 26 terc 30 ns ALE low to valid instruction in fiy 122 4tfgc 100 ns ALE to PSEN fp 31 toc 25 ns PSEN pulse width fipa 132 l 3 tac 35 l ns PSEN to valid instruction in Iu 92 3 toc 75 ns Input instruction hold after PSEN fp 0 0 ns Input instruction float after PSEN tpyiz 46 toc 10 ns Address valid after PSEN fox 48 toc 8 ns Address to valid instr in taviy 180 5 fec 98 ns Address float to PSEN lazgi 0 0 ns Interfacing the C517A to devices with float times up to 45 ns is permissi
76. were not addressed leave their SM20 set and go on about their business ignoring the incoming data bytes SM20 has no effect in mode 0 In mode 1 SM20 can be used to check the validity of the stop bit If SM20 1 in mode 1 the receive interrupt will not be activated unless a valid stop bit is received 6 5 1 3 Serial Port Registers The serial port control and status register is the special function register SOCON This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB80 and RB80 and the serial port interrupt bits TIO and RIO SOBUF is the receive and transmit buffer of serial interface 0 Writing to SOBUF loads the transmit register and initiates transmission Reading out SOBUF accesses a physically separate receive register Semiconductor Group 6 71 1997 08 01 SIEMENS On Chip Peripheral Components C517A Special Function Register SOCON Address 984 Special Function Register SOBUF Address 994 Bit No MSB 9Fy 9EH 98H 99H 9DH 9CH 9BH 9AH Reset Value 00H Reset Value XX4 LSB 99H 98H SMO SM1 SM20 RENO TB80 RB80 TIO RIO SOCON 7 6 5 4 3 2 1 0 Serial Interface 0 Buffer Register SOBUF Bit Function SMO SM1 Serial port 0 mode selection bits SMO SM1 Selected operating mode Serial mode 0 Shift register fixed baud rate fosc 12 Serial mode 1 8 bit U
77. which have been made for integration of the wake up from power down mode capability RC Oscillator Frequency Comparator Internal Reset IPO A9 p Osca ows f r Internal Clock MCB03337 Figure 8 3 Functional Block Diagram of the Oscillator Watchdog The frequency coming from the RC oscillator is divided by 5 and compared to the on chip oscillator s frequency If the frequency coming from the on chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition the oscillation at the on chip oscillator could stop because of crystal damage etc In this case it switches the input of the internal clock system to the output of the RC oscillator This means that the part is being clocked even if the on chip oscillator has stopped or has not yet started At the same time the watchdog activates the internal reset in order to bring the part in its defined reset state The reset is performed because clock is available from the RC oscillator This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions The Watchdog Timer Status flag WDTS is not reset the Watchdog 99Timer however is stopped and bit OWDS is set This allows the software to examine error conditions detected by the Watchdog Timer even if meanwhile an oscillator failure occured The oscillator watchdog is able to dete
78. 0 and 1 Timer counter 0 and 1 of the C517A are fully compatible with timer counter 0 and 1 of the C501 and can be used in the same four operating modes Mode 0 8 bit timer counter with a divide by 32 prescaler Mode 1 16 bit timer counter Mode 2 8 bit timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as one 8 bit timer counter and one 8 bit timer Timer counter 1 in this mode holds its count The effect is the same as setting TR1 0 External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Each timer consists of two 8 bit registers THO and TLO for timer counter 0 TH1 and TL1 for timer counter 1 which may be combined to one timer configuration depending on the mode that is established The functions of the timers are controlled by two special function registers TCON and TMOD In the following descriptions the symbols THO and TLO are used to specify the high byte and the low byte of timer O TH1 and TL 1 for timer 1 respectively The operating modes are described and shown for timer O If not explicity noted this applies also to timer 1 Semiconductor Group 6 14 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 2 1 1 Timer Counter 0 and 1 Registers Totally six special function registers control the timer counter O and 1 operat
79. 004 7 6 5 4 3 2 1 0 F2 CML6 004 7 6 5 4 3 2 1 0 F34 CMH6 00 7 6 5 4 3 2 1 0 F44 CML7 004 7 6 5 4 3 2 1 0 F54 CMH7 004q 7 6 5 4 3 2 1 0 F64 CMEN 004 7 6 5 4 3 2 1 0 F74 CMSEL 004 7 6 5 4 3 2 1 0 F842 P5 FF CCM7 CCM6 CCM5 CCM4 CCM3 CCM2 CCM1 CCMO FAY P6 FFH 7 6 5 4 3 TxD1 RxD1 ADST 1 X means that the value is undefined and the location is reserved 2 Shaded registers are bit addressable special function registers Semiconductor Group 3 18 1997 08 01 SIEMENS External Bus Interface C517A 4 External Bus Interface The C517A allows for external memory expansion The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture 4 1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively This distinction is made by hardware accesses to external program memory use the signal PSEN program store enable as a read strobe Accesses to external data memory use RD and WR to strobe the memory alternate functions of P3 7 and P3 6 Port O and port 2 with exceptions are used to provide data and address signals In this section only the port 0 and port 2 functions relevant to external memory accesses are described Fetches from external program memory always use a 16 bit address Accesses to external data memory can use eit
80. 0H TH2 Timer 2 High Byte CDH 00H TL2 Timer 2 Low Byte CCH 00H T2CON Timer 2 Control Register C8y 00H IRCONO Interrupt Request Control Register 0 COW 00H 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved Semiconductor Group 3 13 1997 08 01 SIEMENS Memory Organization C517A Table 3 1 Special Function Registers Functional Blocks cont d Block Symbol Name Address Contents after Reset Ports PO Port 0 8041 FFH P1 Port 1 90g FFH P2 Port 2 A0y FFy P3 Port 3 Boy FFy P4 Port 4 E84 FFH P5 Port 5 F8H FFH P6 Port 6 FAH FFH P7 Port 7 Analog Digital Input DBH P8 Port 8 Analog Digital Input 4 bit DDH XRAM XPAGE Page Address Register for Extended 91H 00H On Chip RAM SYSCON System XRAM Control Register Bly XXXX XX01p 9 Serial ADCONO A D Converter Control Register D8y 00H Channels PCON Power Control Register 87H 00H SOBUF Serial Channel 0 Buffer Register 99H XXH SOCON Serial Channel 0 Control Register 98H 00H SORELL Serial Channel 0 Reload Reg Low Byte AAH D9H SORELH Serial Channel 0 Reload Reg High Byte BAH XXXX XX11p S1BUF Serial Channel 1 Buffer Register 9CH XXH S1CON Serial Channel 1 Control Register 9By 0X00 0000p S1RELL
81. 10 This mechanism also reduces execution time spent for controlling the MDU Hence a special write sequence selects an operation The MDU monitors the whole write and read out sequence to ensure that the CPU has fetched the result correctly and was not interrupted by another calculation task Thus a complete operation lasts from writing the first byte of the operand in phase 1 until reading the last byte of the result in phase 3 Semiconductor Group 6 64 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 4 3 Multiplication Division The general mechanism to start an MDU activity has been described above The following description of the write and read sequences adds to the information given in the table below where the write and read operations necessary for a multiplication or division are listed Table 6 10 Programming the MDU for Multiplication and Division Operation 32Bit 16Bit 16Bit 16Bit 16Bit x 16Bit First Write MDO D endL MDO D endL MDO M andL MD1 D end MD1 D endH MD4 M orL MD2 D end MD3 D endH MD4 D orL MD1 M andH MD4 D orL Last Write MD5 D orH MD5 D orH MD5 M orH First Read MDO QuoL MDO QuoL MDO PrL MD1 Quo MD1 QuoH MD1 MD2 Quo MD3 QuoH MD4 RemL MD2 MD4 RemL Last Read MD5 RemH MD5 RemH MD3 PrH Abrevations D end Dividend 1st operand of division D or Divisor 2nd operand of division M and Multiplicand 1st operand of multiplication M or Multiplic
82. 2 In table 3 1 they are organized in groups which refer to the functional blocks of the C517A Table 3 2 illustrates the contents of the SFRs in numeric order of their addresses Semiconductor Group 3 11 1997 08 01 SIEMENS Memory Organization C517A Table 3 1 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC Accumulator Ey 00H B B Register FOH 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82H 00H DPSEL Data Pointer Select Register 924 XXXX X000pg PSW Program Status Word Register DOW 00H SP Stack Pointer 81H 07H A D ADCONO A D Converter Control Register 0 D8y 00H Converter ADCON1 A D Converter Control Register 1 DCH OXXX 0000p ADDATH A D Converter Data Register High Byte D9H 00H ADDATL A D Converter Data Register Low Byte DAY 00XX XXXXp Interrupt IENO Interrupt Enable Register 0 A8y 00H System IEN12 Interrupt Enable Register 1 B8y 00H IEN2 Interrupt Enable Register 2 9AH XX00 00X0p IPO 9 Interrupt Priority Register 0 A9H 00H IP1 Interrupt Priority Register 1 BOY XX00 0000p IRCONO Interrupt Request Control Register 0 COW 00H IRCON1 Interrupt Request Control Register 1 Dig 00H TCON Timer 0 1 Control Register 88H 00H T2CON Timer 2 Control Register C8y 00H SOCON Serial Channel 0 Control Register 98H 00H S1CON Serial Channel Control Register 9BH 0X00 0000p CTCON Com
83. 6 31 Special Function Registers 3 11 Gated timer mode 6 31 Table address ordered 3 15 to 3 18 Registers 6 26 to 6 29 Table functional order 3 12 to 3 14 Reload mode 6 31 SWD et at alee ehe E ane 3 16 8 3 Timings SY SOON i usadas 3 3 3 14 3 16 Data memory readcycle 10 12 System clock output 5 8 to 5 9 Data memory write cycle 10 13 External clock timing 10 13 TOs tii E hee ee J ae ued 3 16 Program memory read cycle 10 11 jn E E E 3 16 ROM verification mode 1 10 14 JU ELE 3 15 ROM verification mode 2 10 15 TOG NOTER 3 16 6 42 TLO 6 ee eee eee 3 12 3 15 6 15 T2CON 3 12 3 13 3 16 6 26 6 42 7 10 Tira he orb ESOS PES 3 12 3 15 6 15 jp cali clea cama HEN 3 15 6 31 UE 3 13 3 17 6 28 Semiconductor Group 11 5 1997 08 01 SIEMENS naex C517A MOD Lessee ea ees 3 12 3 15 6 17 TP Geist diste toan anti dati 3 15 6 16 NE nu PRAEC OP ae eae T EIU 3 15 6 16 TXDO sacas Re p havens 3 16 6 70 RDN Ave erac eei oumo sd d tee ees te 3 18 U Unprotected ROM verify timing 4 9 Watchdog timer 8 1 to 8 5 Block diagram 055 8 1 Control status flags 8 3 Input clock selection 8 2 Refreshing of the WDT 8 5 Reset operation 8 5 Starting ofthe WDT 8 4 Time out periods 8 2 WDT sere Grseci add
84. 7 08 01 SIEMENS Interrupt System C517A The SFR IEN2 includes the enable bits for the compare match with compare register interrupts the compare timer overflow interrupt and the serial interface 1 interrupt Special Function Register IEN2 Address 9Ap Reset Value XX0000X0p MSB LSB Bit No 7 6 5 4 3 2 1 0 9AH ECR ECS ECT ECMP ES1 IEN2 Bit Function Reserved bits for future use ECR COMCLR register compare match interrupt enable If ECR 0 the COMCLR compare match interrupt is disabled ECS COMSET register compare match interrupt enable If ECS 0 the COMSET compare match interrupt is disabled ECT Enable compare timer interrupt enable If ECT 0 the compare timer overflow interrupt is disabled ECMP CMO 7 register compare match interrupt enable If ECMP 0 the CMO 7 compare match interrupt is disabled ES1 Serial Interface 1 interrupt enable if ES1 0 the serial interrupt 1 is disabled Semiconductor Group 7 7 1997 08 01 SIEMENS Interrupt System C517A 7 1 2 Interrupt Request Control Flags The request flags for the different interrupt sources are located in several special function registers This section describes the locations and meanings of these interrupt request flags in detail The external interrupts 0 and 1 P3 2 INTO and P3 3 INT1 can each be either level activated or negative transition activated depending on
85. 9 4 1 Invoking Software Power Down Mode selle sen 9 5 9 4 2 Exit from Software Power Down Mode ssselesleeleeleren 9 5 9 5 State of Pins in Software Initiated Power Saving Modes 9 6 9 6 Hardware Power Down Mode 0 00 ce eee eee eens 9 7 9 7 Hardware Power Down Reset Timing 0 cc eee eee eee 9 9 10 Device Specifications 00 eee 10 1 10 1 Absolute Maximum Ratings irem cT Her DEL Ohad DECRE Io 10 1 10 2 DC Characteristics ius eg es Sane gees S84 xeu Nous eon Be ee eee od 10 2 10 3 A D Converter Characteristics 0 00 0 00 cc eee 10 5 10 4 AC Characteristics 18 MZ eu ent am rent feat is sa e x Dei 10 7 10 5 AC Characteristics 24 MHz 000 cee ee rens 10 9 10 6 ROM Verification Characteristics for the C517A 4R 002000 00 ee 10 14 10 7 Package Information x cvs ua i RAS RISSEE EEXTDRE S ET eee IN RE 10 17 11 INDEX O 11 1 Semiconductor Group 4 1997 08 01 SIEMENS Introduction C517A 1 Introduction The C517A is a high end member of the Siemens C500 family of 8 bit microcontrollers It is functionally fully compatible with the SAB 80C517A 83C537A 5 microcontrollers The C517A basically operates with internal and or external program memory The C517A L is identical to the C517A 4R except that it lacks the on chip program memory Therefore in this documentation the term C517A refer
86. ART variable baud rate Serial mode 2 9 bit UART fixed baud rate fosc 32 or fosc 64 Serial mode 3 9 bit UART variable baud rate O 0 1 0 1 SM20 Enable serial port 0 multiprocessor communication in modes 2 and 3 In mode 2 or 3 if SM20 is set to 1 then RIO will not be activated if the received 9th data bit RB80 is 0 In mode 1 if SM20 1 then RIO will not be activated if a valid stop bit was not received In mode 0 SM20 should be 0 RENO Serial port 0 receiver enable Enables serial reception Set by software to enable serial reception Cleared by software to disable serial reception TB80 Serial port 0 transmitter bit 9 TB80 Is the 9th data bit that will be transmitted in modes 2 and 3 Set or cleared by software as desired RB80 Serial port 0 receiver bit 9 In modes 2 and 3 RB80 is the 9th data bit that was received In mode 1 if SM2 0 RB80 is the stop bit that was received In mode 0 RB80 is not used TIO Serial port 0 transmitter interrupt flag TIO is set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes in any serial transmission TIO must be cleared by software RIO Serial port 0 receiver interrupt flag RIO is set by hardware at the end of the 8th bit time in mode 0 or halfway through the stop bit time in the other modes in any serial reception exception see SM20 RIO must
87. CH2 Compare Capture Register 2 High Byte C5H CCH3 Compare Capture Register 3 High Byte C7H CCH4 Compare Capture Register 4 High Byte CF4 CCL1 Compare Capture Register 1 Low Byte C2y CCL2 Compare Capture Register 2 Low Byte C4y CCL3 Compare Capture Register 3 Low Byte C6H CCL4 Compare Capture Register 4 Low Byte CEH CMEN Compare Enable Register F6H CMHO Compare Register 0 High Byte D3y CMH1 Compare Register 1 High Byte D5y CMH2 Compare Register 2 High Byte D7y CMH3 Compare Register 3 High Byte E3y CMH4 Compare Register 4 High Byte E5H CMH5 Compare Register 5 High Byte E7y CMH6 Compare Register 6 High Byte F3y CMH7 Compare Register 7 High Byte F5H CMLO Compare Register 0 Low Byte D24 CML1 Compare Register 1 Low Byte D44 CML2 Compare Register 2 Low Byte D6H CML3 Compare Register 3 Low Byte E24 CML4 Compare Register 4 Low Byte E44 CML5 Compare Register 5 Low Byte E6H CML6 Compare Register 6 Low Byte F2u CML7 Compare Register 7 Low Byte F44 CMSEL Compare Input Select F7H CRCH Comp Rel Capt Reg High Byte CBy CRCL Comp Rel Capt Reg Low Byte CAH COMSETL Compare Set Register Low Byte Aly COMSETH Compare Set Register High Byte A2y COMCLRL Compare Clear Register Low Byte A3y COMCLRH Compare Clear Register High Byte A4y SETMSK Compare Set Mask Register Ady CLRMSK Compare Clear Mask Register A6y CTCON Compare Timer Control Register Ely CTRELH Compare Timer Rel Reg High Byte DFy CTRELL Compare Timer Rel Reg Low Byt
88. Clock C517A The time required for a reset operation is the oscillator start up time plus 2 machine cycles which under normal conditions must be at least 10 20 ms for a crystal oscillator This requirement is typically met using a capacitor of 4 7 to 10 uF The same considerations apply if the reset signal is generated externally figure 5 1 b In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive MCS03323 Figure 5 1 Reset Circuitries A correct reset leaves the processor in a defined state The program execution starts at location 0000 After reset is internally accomplished the port latches of ports 0 to 6 are set to FFy This leaves port 0 floating since it is an open drain port when not used as data address bus All other O port lines ports 1 3 to 6 output a one 1 Port 2 lines output a zero or one after reset if EA is held low or high Port 7 and 8 are input only ports They have no internal latch and therefore the contents of the special function registers P7 and P8 depend on the levels applied to port 7 or 8 The content of the internal RAM of the C517A is not affected by a reset After power up the content is undefined while it remains unchanged during a reset if the power supply is not turned off Semiconductor Group 5 2 1997 08 01 SIEMENS Reset System Clock C517A 5 2 Fast Internal
89. EX2 in register IRCON In addition this flag will be set if a compare event occurs at the corresponding output pin P1 4 INT2 CC4 regardless of the compare mode established and the transition at the respective pin If an interrupt 2 is generated flag IEX2 is cleared by hardware when the service routine is vectored to Like the external interrupt 2 the external interrupt 3 can be either positive or negative transition activated depending on bit I3FR in register T2CON The flag that actually generates this interrupt is bit IEX3 in register IRCONO In addition this flag will be set if a compare event occurs at pin P1 0 INT3 CCO regardless of the compare mode established and the transition at the respective pin The flag IEX3 is cleared by hardware when the service routine is vectored to The external interrupts 4 INT4 5 INT5 and 6 INT6 are positive transition activated The flags that actually generate these interrupts are bits IEX4 IEX5 and IEX6 in register IRCONO In addition these flags will be set if a compare event occurs at the corresponding output pin P1 1 INT4 CC1 P1 2 INT5 CC2 and P1 3 INT6 CC3 regardless of the compare mode established and the transition at the respective pin When an interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to The timer 2 interrupt is generated by the logical OR of bit TF2 in SFR T2CON and bit EXF2 in SFR IRCONO Neither of t
90. IEMENS General Information C517A Table of Contents Page 6 4 Atrithmetle UNI 35 2 ned mro Re ft ce sue te keeps UR EODE PR Uus 6 62 6 4 1 MDLU R6glsIlGF inse EE Abe eed RERAAEPSe QR S hrs RE bh eRe ewes 6 62 6 4 2 Operation on the MDU 24 rr ey uere yet meer dde pdt eoa oto 6 64 6 4 3 Multiplication Division iux iX E REPRE GR URERECS CERES EUR ESAE SR 6 65 6 4 4 Norrmalize srt Shift oaa Cresc oe ec eb deos bl eh Odes Be ete ta b nd 6 67 6 4 5 This OVverlow Flag 4a RE YUOEDEGUEEYGORER SE TEGQERSEESQEURSDU IO 6 68 6 4 6 The Error Flag ieu stove oo ERI ELE EE EC Der PE Vx Wa yis 6 68 6 5 Serial InterfaegS oiseau x qupEFsu Ded ege NES REIR IE pie SU ed ede 6 70 6 5 1 Serial lnterface Di spesa mtra tI e est utut uM CIE 6 70 6 5 1 1 Operating Modes of Serial Interface 0 l l 6 70 6 5 1 2 Multiprocessor Communication Feature 0 00 eee eee 6 71 6 5 1 3 Serial Port Registers cresas abotavae avawddewhs a eed e BO eas 6 71 6 5 1 4 Baud Rates of Serial Channel O 0 2000 c eee eee 6 73 6 5 1 4 1 Baud Rate in Mode 0 ues iR E RR RERUM bie tees P Y RE ERS 6 75 6 5 1 4 2 Ba d Rate mn MOE Z vinme dde due SO E end eeu ae e iul d ets 6 75 6 5 1 4 3 Baud Rate in Mode T and 3 Vues eoe eh yon Rt ae UR SR he 6 75 6 5 2 Seal dterfaeg i ess ass ueteri woe Eme due PRU git 6 79 6 5 2 1 Operating Modes of Serial Interface 1 0 cee eee 6 79 6 5 2 2 Multiprocessor Communication Feature ssaa saaara eeaeee 6
91. Interrupt Request MCS01844 Figure 6 15 Timer 2 in Reload Mode Semiconductor Group 6 32 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 2 Operation of the Compare Timer The compare timer operates as a fast 16 bit time base for the compare registers CMO to CM7 The compare timer combined with the CMx registers and can be used for high speed output puposes or as a fast 16 bit pulse width modulation unit Prior to the description of the compare timer operating modes and functions the compare timer related special function registers are described 6 3 2 1 Compare Timer Registers The compare timer has a 8 bit control control register and a 16 bit reload register These 6 special function registers are described in this section Special Function Register CTCON Address E1 Reset Value 0X000000p MSB LSB Bit No 7 6 5 4 3 2 1 0 Eip T2PSi ICR ICS CTF CLK2 CLK1 CLKO CTCON The shaded bits are not used for compare timer control Bit Function ICR Interrupt request flag for compare register COMCLR ICR is set when a compare match occured ICR is cleared ba hardware when the processor vectors to interrupt routine ICS Interrupt request flag for compare register COMSET ICS is set when a compare match occured ICS is cleared by hardware when the processor vectors to interrupt routine CTF Compare timer overflow flag CTF is set when the compare
92. LR SC 4 SC 0 Semiconductor Group 6 63 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 4 2 Operation of the MDU The MDU can be regarded as a special coprocessor for multiplication division and shift Its operations can be divided into three phases see figure 6 32 1 Loading the MDx registers 2 Executing the calculation 3 Reading the result from the MDx registers During phase two the MDU works on its own parallelly to the CPU Execution times of the above table refer to this phase Because of the fast operation and the determined execution time for C517A s instructions there is no need for a busy flag The CPU may execute a determined number of instructions before the result is fetched The result and the remainder of an operation may also be stored in the MDx registers for later use Phase one and phase three require CPU activity In these phases the CPU has to transfer the operands and fetch the results 1st Write MDO Last Write MD5 or ARCON First Read Last Read MDO MD3 or MD5 v Phase 1 p Phase 2 X Phase 3 gt Load Registers Calculate Read Registers Time MCD00787 Figure 6 32 Operating Phases of the MDU The MDU has no dedicated instruction register only for shift and normalize operations register ARCON is used in such a way The type of calculation the MDU has to perform is selected following the order in which the MDx registers are written to see table 6
93. ON 0 1 when ADCON 1 0 is written after ADCON 0 1 The analog inputs are selected according the following table MX3 MX2 MX1 MXO Selected Analog Input 0 0 0 0 P7 0 ANO 0 0 0 1 P7 1 AN1 0 0 1 0 P7 2 AN2 0 0 1 1 P7 3 AN3 0 1 0 0 P7 2 AN4 0 1 0 1 P7 3 AN5 0 1 1 0 P7 4 AN6 0 1 1 1 P7 5 AN7 1 0 0 0 P8 0 AN8 1 0 0 1 P8 1 AN9 1 0 1 0 P8 2 AN10 1 0 1 1 P8 3 AN11 Semiconductor Group 6 96 1997 08 01 SIEMENS On Chip Peripheral Components C517A Bit Function ADCL A D converter clock prescaler selection ADCL selects the prescaler ratio for the A D conversion clock fapc Depending on the clock rate fosc of the C517A fapc must be adjusted in a way that the resulting fapc clock is less or equal 2 MHz The prescaler ratio is selected according the following table ADCL Prescaler Ratio 0 divide by 4 default after reset 1 divide by 8 Note Generally before entering the power down mode an A D conversion in progress must be stopped If a single A D conversion is running it must be terminated by polling the BSY bit or waiting for the A D conversion interrupt In continuous conversion mode bit ADM must be cleared and the last A D conversion must be terminated before entering the power down mode A single A D conversion is started by writing to SFR ADDATL with dummy data A continuous conversion is started under the following conditions Bysetting bit ADM during a r
94. ONO is set Conversion Time tco During the conversion time the analog voltage is converted into a 10 bit digital value using the successive approximation technique with a binary weighted capacitor network During an A D Semiconductor Group 6 100 1997 08 01 SIEMENS On Chip Peripheral Components C517A conversion also a calibration takes place During this calibration alternating offset and linearity calibration cycles are executed see also section 6 6 5 At the end of the conversion time the BSY bit is reset and the IADC bit in SFR IRCONO is set indicating an A D converter interrupt condition Write Result Time twp At the result phase the conversion result is written into the ADDAT registers Figure 6 45 shows how an A D conversion is embedded into the microcontroller cycle scheme using the relation 12 x t jv 1 instruction cycle It also shows the behaviour of the busy flag BSY and the interrupt flag IADC during an A D conversion Prescaler MOV ADDATL Write Result Cycle Selection 0 1 Instruction Cycle MOV A ADDATL AS A pea xir ja2sjajseej rjejojnjmnjr epee ee ESSET DS TES T9 Start of A D Start of next conversion conversion Cycle in continuous mode ADCC A D Conversion Cycle Write ADDAT mm 010 ot 64 E Cont conv BSY Bit Single conv IADC Bit First Instr of an Interrupt Routine IADC Bit First Instr of an Interrupt Routine MC
95. R P4 x 8 Start the compare timer with a desired value Compare function is initialized the output write to CTREL will oscillate Semiconductor Group 6 54 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 4 4 2 CMx Registers Assigned to the Timer 2 Any CMx register assigned to timer 2 as a time base operates in compare mode 1 In this case CMx registers behave like any other compare register connected to timer 2 e g the CRC or CCx registers Since there are no dedicated interrupts for the CMx compare outputs again a buffered compare register structure is used to determine an exact 16 bit wide loading of the compare value the compare value is transferred to the actual compare latches at a write to CML x instruction low byte of CMx Thus the CMx register is to be written in a fixed order too high byte first low byte second If the high byte may remain unchanged it is sufficient to load only the low byte See figure 6 28 block diagram of a CMx register connected to timer 2 er 2 168 Port 4 fi Compare Latch 16 Bi fi Write to CMLx MCS01866 Figure 6 28 CMx Register Assigned to Timer 2 Semiconductor Group 6 55 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 4 5 Timer 2 Operating in Compare Mode 2 The compare mode 2 of the CCU can be used for the concurrent compare output function at port 5 In compare mode 2 the port 5 pins are no longer gen
96. Read next Opcode Opcode Discard Read next if Opcode again sTe sTvTs s a 1 Byte 1 Cycle Instruction e g INC A Read Read 2nd Opcode Byte Read next Opcode SISTISTSTSIST 1 Cycle Instruction e g ADD A Data Read next Opcode again Opcode Read next Opcode Discard Read Y Y Y SISTSTSTSISTSTSISTSTSTS 2 Cycle Instruction e g INC DPTR Read next Opcode again Opcode Opcode No Fetch No Fetch MOVX Discard No ALE EAM LANI STSISTSTSISTSISISIRTSIST d MOVX 1 Byte 2 Cycle ADDR DATA Read Read next Access External Memory MCD03218 Figure 2 2 Fetch Execute Sequence Semiconductor Group 2 6 1997 08 01 SIEM ENS Memory Organization C517A 3 Memory Organization The C517A CPU manipulates operands in the following four address spaces up to 64 Kbyte of internal external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory 2K bytes of internal XRAM data memory a 128 byte special function register area Figure 3 1 illustrates the memory address spaces of the C517A ext XMAPO 1 F800 Indirect Direct Address Address ae F7FF y FFH ren mena E RAN 804 Regs ext 7FH Internal RAM 0000 H 0000 H 00H Code Space Data Space Internal Data Space MCB03321 Figure 3 1 C517A Memory Map Semiconductor Group 3 1 1997 08 01 SIEM ENS Memory Orga
97. Reset after Power On The C517A uses the oscillator watchdog unit for a fast internal reset procedure after power on Figure 5 1 shows the power on sequence under control of the oscillator watchdog Normally the devices of the 8051 family do not enter their default reset states before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 10 ms During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins In the C517A the oscillator watchdog unit avoids this situation In this case after power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the defined state see figure 5 2 Under worst case conditions fast Voc rise time e g 1us m
98. SIEMENS Power Saving Modes C517A 9 Power Saving Modes The C517A provides two basic power saving modes the idle mode and the power down mode Additionally a slow down mode is available This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode 9 1 Power Saving Mode Control Registers The functions of the power saving modes are controlled by bits which are located in the special function registers PCON which is located at SFR address 87g The bits PDE PDS and IDLE IDLS located in SFR PCON select the power down mode or the idle mode respectively If the power down mode and the idle mode are set at the same time power down takes precedence Special Function Register PCON Address 871 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS SD GF1 GFO PDE IDLE PCON The function of the shaded bit is not described in this section Symbol Function PDS Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode IDLS Idle start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode SD Slow down mode bit When set the slow down mode is enabled GF1 General purpose flag GFO General purpose flag PDE Power down enable bit When set starting of the power do
99. Start RX Control Detector FF Shift Bit Detector Input Shift Register 9Bits Iv Note x means that 0 or 1 can XZ be inserted for interface SxBUF 0 or interface 1 resp NZ Read SxBUF Internal Bus MCS01834 Figure 6 40 Functional Diagram Serial Interfaces 0 and 1 Modes 2 and 3 Mode A Semiconductor Group 6 91 1997 08 01 C517A On Chip Peripheral Components SIEMENS 9E810LOW e Xl Transmit eoepneiul eues 10 x pue Q eoepelul eas 104 O X SION 1049940 Ig LASAY 94 LL s IL HUS geq IdiS epo pues Ld9S Z apoyy ll ANEXS oi aHM ll ll ll ll l ll ll ll ll ll ll 49010 XL Figure 6 41 Timing Diagram Serial Interfaces 0 and 1 Modes 2 and 3 Mode A 1997 08 01 6 92 Semiconductor Group SIEMENS On Chip Peripheral Components C517A 6 6 10 bit A D Converter The C517A includes a high performance high speed 10 bit A D Converter ADC with 12 analog input channels It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors The A D converter provides the following features 12 multiplexed input channels port 7 8 which can also be used as digital inputs 10 bit resolution Single or continuous conversion mode Internal or external start of conversion trigger capability Interrupt request generation after e
100. T03266 Figure 6 45 A D Conversion Timing in Relation to Processor Cycles Depending on the selected prescaler ratio see figure 6 43 two different relationships between machine cycles and A D conversion are possible The A D conversion is always started with the beginning of a processor cycle when it has been started by writing SFR ADDATL with dummy data or after an high to low transition has been detcted at P6 0 ADST The ADDATL write operation may take one or two machine cycles In figure 6 45 the instruction MOV ADDATL 00 starts the A D conversion machine cycle X 1 and X The total A D conversion is finished with the end of the 8th or 16th machine cycle after the A D conversion start In the next machine cycle the conversion result is written into the ADDAT registers and can be read in the same cycle by an instruction e g Semiconductor Group 6 101 1997 08 01 SIEMENS On Chip Peripheral Components C517A MOV A ADDATL If continuous conversion is selected bit ADM set the next conversion is started with the beginning of the machine cycle which follows the writre result cycle The BSY bit is set at the beginning of the first A D conversion machine cycle and reset at the beginning of the write result cycle If continuous conversion is selected BSY is again set with the beginning of the machine cycle which follows the write result cycle The interrupt flag IADC is set at the end o
101. X 2 A X000p 984 S0CON 00y SMO SM1 SM20 RENO TB80 RB80 TIO RIO 994 SOBUF XXy 7 6 5 4 3 2 1 0 9Ay IEN2 XX00 ECR ECS ECT ECMP ES1 00X0p 9B S1CON 0X00 SM SM21 REN1 TB81 RB81 TIt RI1 0000p 9Cy S1BUF XXH 7 6 5 4 3 2 1 0 9Dy STRELL 004 7 6 5 4 3 2 1 0 AOL P2 FFH 7 6 5 4 3 2 1 0 Aij COMSETL 00H a 6 5 4 3 2 1 0 A24 COMSETH 00j 7 6 5 4 3 2 1 0 A34 COMCLRL 00 7 6 5 4 3 2 1 0 1 X means that the value is undefined and the location is reserved 2 Shaded registers are bit addressable special function registers Semiconductor Group 3 15 1997 08 01 SIEMENS Memory Organization C517A Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 after Reset A44 COMCLRH 00H 1 A5y SETMSK 00H 1 A6y CLRMSK 00y 1 A814 IENO 00H EAL WDT ET2 ESO Ell EX1 ETO EXO A94 IPO 00H OWDS WDTS 5 4 3 2 1 0 AAH SORELL D9j 7 6 5 4 EC 2 1 0 BO P3 FFH RD WR T1 TO INT1 INTO TxDO RxDO Bi SYSCON XXXX XMAP1 XMAPO XX01p B8p IEN1 00H EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC B94 IP1 XX00 5 4 3 2 1 0 0000p BAH SORELH XXXX 1 0 XX11p BBY S1RELH XXXX 1 0
102. XEN2 1 If ET2 in IENO is set timer 2 interrupt enabled EXF2 1 will cause an interrupt Can be used as an additional external interrupt when the reload function is not used EXF2 must be cleared by software TF2 Timer 2 overflow flag Set by a timer 2 overflow and must be cleared by software If the timer 2 interrupt is enabled TF2 1 will cause an interrupt Semiconductor Group 6 27 1997 08 01 SIEMENS On Chip Peripheral Components C517A Special Function Registers TL2 TH2 Addresses CCH CDH Reset Value 00 4 00 4 Special Function Registers CRCL CRCH Addresses CAQ CBj Reset Value 001 001 Bit No MSB LSB 7 6 5 4 3 2 1 0 CCy ul 6 5 4 3 2 A 0 TL2 CDH T 6 5 4 3 2 A 0 TH2 CAH T 6 5 4 3 2 A 0 CRCL CBy m 6 5 4 3 2 A 0 CRCH Bit Function TL2 7 0 Timer 2 low byte TL2 contains the 8 bit low byte of the 16 bit timer 2 count value TH2 7 0 Timer 2 high byte TH2 contains the 8 bit high byte of the 16 bit timer 2 count value CRCL 7 0 Compare Reload Capture register low byte CRCL is the 8 bit low byte of the 16 bit reload register of timer 2 It is also used for compare capture functions CRCH 7 0 Compare Reload Capture register high byte CRCH is the 8 bit high byte of the 16 bit reload register of timer 2 It is also used for compare capture functions Semiconductor Group 6 28 1997 08 01 SIEMENS On Chip Peripheral Components
103. Xx registers are assigned to the compare timer and compare mode 0 is enabled The compare registers are assigned to timer 2 if CMSELx 0 In this case compare mode 1 is selected CMEN 7 0 Enable bits for compare registers CMx x 0 7 When set the compare function is enabled and led to the output lines of port 4 Semiconductor Group 6 51 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 4 4 1 CMx Registers Assigned to the Compare Timer Every CMx register assigned to the compare timer as a time base operates in compare mode 0 and uses a port 4 pin as an alternate output function The Timer Overflow Controlled TOC Loading There is one great difference between a CMx register and the other previously described compare registers compare outputs controlled by CMx registers have no dedicated interrupt function They use a timer overflow controlled loading further on called TOC loading to reach the same performance as an interrupt controlled compare To show what this TOC loading is for it will be explained more detailed in the following The main advantage of the compare function in general is that the controller s outputs are precisely timed by hardware no matter which task is running on the CPU This in turn means that the CPU normally does not know about the timer count So if the CPU writes to a compare register only in relation to the program flow then it could easily be that a compare register is
104. a timer period In a timer 2 CCx register configuration in compare mode 0 this spike is divided into two halves one at the beginning when the contents of the compare register is equal to the reload value of the timer the other half when the compare register is equal to the maximum value of the timer register here FFFFp Please refer to figure 6 30 where the maximum and minimum duty cycle of a compare output signal is illustrated Timer 2 is incremented with the processor cycle fosc 12 thus at 12 MHz operating frequency these spikes are both approx 500 ns long CCHx CCLx 0000 4 or CRCH CRCL maximum duty cycle P1 x Appr 1 2 of a Machine Cycle CCHx CCLx FFFF y minimum duty cycle Appr 1 2 of a Machine Cycle MCT01851 Figure 6 30 Modulation Range of a PMW Signal Generated with a Timer 2 CCx Register Combination in Compare Mode 0 The following example shows how to calculate the modulation range for a PWM signal For the calculation with reasonable numbers a reduction of the resolution to 8 bit is used Otherwise for the maximum resolution of 16 bit the modulation range would be so severely limited that it would be negligible Example Timer 2 in auto reload mode contents of reload register CRC FFOO 1 Restricti f modulation 0 195 estriction of modulation range 256 x2 x 100 0 195 This leads to a variation of the duty cycle from 0 195 to 99 805 for a timer 2 CCx register
105. ach conversion Using successive approximation conversion technique via a capacitor array Bullt in hidden calibration of offset and linearity errors The externally applied reference voltage range has to be held on a fixed value within the specifications The main functional blocks of the A D converter are shown in figure 6 42 6 6 1 A D Converter Operation An internal start of a single A D conversion is triggered by a write to ADDATL instruction The start procedure itself is independent of the value which is written to ADDATL When single conversion mode is selected bit ADM 0 only one A D conversion is performed In continuous mode bit ADM 1 after completion of an A D conversion a new A D conversion is triggered automatically until bit ADM is reset An externally controlled conversion can be achieved by setting the bit ADEX In this mode one single A D conversion is triggered by a 1 to 0 transition at pin P6 0 ADST when ADM is 0 P6 0 ADST is sampled during S5P2 of every machine cycle When the samples show a logic high in one cycle and a logic low in the next cycle the transition is detected and the A D conversion is started When ADM and ADEX is set a continuous conversion is started when pin P6 0 ADST sees a low level Only if no A D conversion single or continuous has occurred after the last reset operation a 1 to 0 transition is required at pin P6 0 ADST for starting the continuous conversion mode externally The continuous
106. activated in the next timer period Initializing the Compare Register Compare Latch Circuit Normally when the compare function is desired the initialization program would just write to the compare register called register latch The compare latch itself cannot be accessed directly by a move instruction it is exclusively loaded by the timer overflow signal In some very special cases however an initial loading of the compare latch could be desirable If the following sequence in table 6 7 is observed during initialization then latches the register and the compare latch can be loaded before the compare mode is enabled Table 6 7 Compare Register Latch Initializing Sequence Step Action Comment 1 Select compare mode 1 CMSEL x 0 This is also the default value after reset 2 Move the compare value for the first timer In compare mode 1 latch is loaded directly period to the compare register CMx high after a write to CMLx Thus the value slips byte first directly into the compare latch Switch on compare mode 0 CMSEL x 1 Now select the right compare mode Move the compere value for the second The register latch is loaded this value is timer period to the compare register used after the first timer overflow Enable the compare function CMEN x 1 Set up the prescaler for the compare timer Set specific compare output to low level The compare output is switched to low level CL
107. apc 26624 x tix 53248 x tosc For achieving a proper reset calibration the fApc prescaler value must satisfy the condition fADCmax 2 MHz For oscillator frequencies above 16 MHz this condition is not met with the default prescaler value 4 after reset Therefore the prescaler of the A D converter must be adjusted by software immediately after reset by setting bit ADCL in SFR ADCON1 When setting bit ADCL directly after reset as required for oscillator clocks greater or equal 16 MHz the clock prescaler ratio 8 is selected and therefore the absolute value for the reset calibration phase will be extended by factor 2 After a reset operation of the C517A this means when a reset calibration phase is started the total unadjusted error TUE of the A D converter is 6 LSB After the reset calibration phase the A D converter is calibrated according to its DC characteristics TUE 2 LSB Nevertheless during the reset calibration phase single or continuous A D can be executed In this case it must be regarded that the reset calibration is interrupted and continued after the end of the A D conversion Therefore interrupting the reset calibration phase by A D conversions extends the total reset calibration time If the specified total unadjusted error TUE has to be valid for an A D conversion itis recommended to start the first A D conversions after reset when the reset calibration phase is finished After the reset calibration a second calibr
108. are power down mode is terminated The software power down mode can be left either by an active reset signal or by a low signal at the P3 2 INTO pin Using reset to leave software power down mode puts the microcontroller with its SFRs into the reset state Using the P3 2 INTO pin for software power down mode exit starts the RC oscillator and the on chip oscillator and maintains the state of the SFRs which has been frozen when software power down mode is entered Leaving software power down mode should not be done before Vec is restored to its nominal operating level 9 4 1 Invoking Software Power Down Mode The software power down mode is entered by two consecutive instructions The first instruction has to set the flag bit PDE PCON 1 and must not set bit PDS PCON 6 the following instruction has to set the start bit PDS PCON 6 and must not set bit PDE PCON 1 The hardware ensures that a concurrent setting of both bits PDE and PDS does not initiate the software power down mode Bits PDE and PDS will automatically be cleared after having been set and the value shown by reading one of these bits is always 0 This double instruction is implemented to minimize the chance of unintentionally entering the software power down mode which could possibly freeze the chip s activity in an undesired status PCON is not a bit addressable register so the above mentioned sequence for entering the software power down mode is obtained by byte handling i
109. are reset i e especially the watchdog timer is stopped and its status flag WDTS is cleared In this phase the power consumption is not yet reduced After completion of the internal reset both oscillators of the chip are disabled the on chip oscillator as well as the oscillator watchdog s RC oscillator At the same time the port pins and several control lines enter a floating state as shown in table 9 2 In this state the power consumption is reduced to the power down current Ipp Also the supply voltage can be reduced Table 9 2 also lists the voltages which may be applied at the pins during hardware power down mode without affecting the low power consumption Table 9 2 Status of all Pins During Hardware Power Down Mode Pins Status Voltage Range at Pin During HW Power Down PO P1 P2 P3 P4 P5 Floating outputs Vas Vin lt Voc P6 Disabled input function EA Active input Vin Voc or Vin Vas PE SWD Active input Pull up resistor Vin Voc or Vin Vss Disabled during HW power down XTAL 1 Active output pin may not be driven XTAL 2 Disabled input function Vss Vin lt Voc PSEN ALE Floating outputs Vas Vin lt Voc Disabled input function for test modes only HESET Active input must be at high level if Vin Voc HWPD is used Viret ADC reference supply input Vas Vin lt Vec Semiconductor Group 9 7 1997 08 01 SIEMENS Power Saving Modes C517A The hardware pow
110. ared by hardware Figure 7 1 Interrupt Structure Overview Part 1 Semiconductor Group 7 2 1997 08 01 SIEMENS Interrupt System C517A Highest Priority Level ma oo NTI me l Lowest TCON 2 Priority Level Match in CM0 CM7 ICMP0 7 IRCON1 0 7 LECMP IEN2 2 IRCONO 2 BFR IENT2 T2CON 5 cco Timer 1 Overflow e e e D 2 c D oN D o A Compare Timer Overflow MCS03334 L Bit addressable C 1 Request Flag is cleared by hardware Figure 7 2 Interrupt Structure Overview Part 2 Semiconductor Group 7 3 1997 08 01 SIEMENS Interrupt System C517A Highest Priority Level USART 0 Match in COMSET P1 2 INT5 CC2 Timer 2 Overflow Match in COMCLR Polling Sequence IEN1 7 P1 3 INT6 CC3 MCS03335 Y Bit addressable 4 Request Flag is cleared by hardware Figure 7 3 Interrupt Structure Overview Part 3 Semiconductor Group 7 4 1997 08 01 SIEMENS Interrupt System C517A 7 1 Interrupt Registers 7 1 1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IENO IEN1 and IEN2 Register IENO also contains the global disable bit EAL which can be cleared to disable all interrupts at once Some interrupts sources have further e
111. art bit if REN1 1 The serial interfaces also provide interrupt requests when a transmission or a reception of a frame has completed The corresponding interrupt request flags for serial interface 1 are Tl1 or RI1 respectively The interrupt request flags TI1 and RI1 can also be used for polling the serial interface 1 if the serial interrupt shall not be used i e serial interrupt 1 not enabled The control and status bits of the serial channel 1 in special function register S1CON and the transmit receive data register S1BUF are shown on the next page Writing to S1BUF loads the transmit register and initiates transmission Reading out S1BUF accesses a physically separate receive register Note that these special function registers are not bit addressable Due to this fact bit instructions cannot be used for manipulating these registers This is important especially for S1CON where a polling and resetting of the RI1 or TI1 request flag cannot be performed by JNB and CLR instructions but must be done by a sequence of byte instructions e g LOOP MOV A S1CON JNB ACC 0 LOOP Testing of RI1 ANL S1CON ZOFEH Resetting of RI1 Semiconductor Group 6 79 1997 08 01 SIEMENS On Chip Peripheral Components C517A Special Function Register S1CON Address 9By Reset Value 0X000000p Special Function Register S1BUF Address 9Cj Reset Value XXH Bit No MSB LSB 7 6 5 4 3 2 1 0
112. at the double latch structure is transparent as long as the internal compare signal is active While the compare signal is active a write operation to the port will then change both latches This may become important when timer 2 is driven with a slow input clock In this case the compare signal could be active for many machine cycles in which the CPU could unintentionally change the contents of the port latch A read modify write instruction will read the user controlled shadow latch and write the modified value back to this shadow latch A standard read instruction will as usual read the pin of the corresponding compare output Semiconductor Group 6 39 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 3 3 Compare Mode 2 In the compare mode 2 in the CCU can be used for the concurrent compare outputs at port 5 In this compare mode 2 the port 5 pins are no longer general purpose I O pins or under control of compare capture register CC4 but under control of the compare registers COMSET and COMCLR These both 16 bit registers are always associated with timer 2 same as CRC CC1 to CC4 In compare mode 2 the concurrent compare output pins on port 5 are used as shown in figure 6 20 Port Circuit COMSET IL e 5 Compare SETMSK Signal Bits Internal Write to Timer 2 Latch Signal Bits IL ft 7 Compare CLRMSK COMCLR Read Pin MCS02663 Figure 6 20 Compare F
113. ated by timer 1 which is incremented by a rate of fosc 12 The dedicated baud rate generator of serial interface 1 however is clocked by a fosc 2 signal and so its maximum baud rate is fosc 32 6 5 3 4 Mode 3 Mode A 9 Bit UART Serial Interfaces 0 and 1 Eleven bits are transmitted through TXDO TXD1 or received through RXDO RXD1 a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmission the 9th data bit TB80 TB81 can be assigned the value of 0 or 1 On reception the 9th data bit goes into RB80 RB81 in SOCON S1CON Mode 3 may have a variable baud rate generated from either timer 1 or 2 depending on the state of TCLK and RCLK in SFR T2CON Figure 6 40 shows a simplified functional diagram of the both serial channels in mode 2 an 3 or mode A respectively The associated timing is illustrated in figure 6 41 The receive portion is exactly the same as in mode 1 The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register Transmission is initiated by any instruction that uses SOBUF S1BUF as a destination register The write to SOBUF S1BUF signal also loads TB80 TB81 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission commences at S1P1 of the machine cycle following the next rollover in the divide by 16 counter thus the bit times are synchronized to the divide by 16 counter and n
114. ates as a gate to the input of timer 2 If T2 is high the internal clock input is gated to the timer T2 0 stops the counting procedure This will facilitate pulse width measurements The external gate signal is sampled once every machine cycle 6 3 1 2 2 Event Counter Mode In the event counter function the timer 2 is incremented in response to a 1 to 0 transition at its corresponding external input pin P1 7 T2 In this function the external input is sampled every machine cycle When the sampled inputs show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the timer register in the cycle following the one in which the transition was detected Since it takes two machine cycles 24 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held stable for at least one full machine cycle Note The prescaler must be turned off for proper counter operation of timer 2 T2PS1 T2PS 0 In either case no matter whether timer 2 is configured as timer event counter or gated timer a rolling over of the count from all 1 s to all O s sets the timer overflow flag TF2 bit 6 in SFR IRCONO interrupt request control which can generate an interrupt If TF2 is used to generate a timer over
115. ation mechanism is initiated This calibration is coupled to each A D conversion With this second calibration mechanism alternatively offset and linearity calibration values stored in the calibration RAM are always checked when an A D conversion is executed and corrected if required Semiconductor Group 6 104 1997 08 01 SIEMENS Interrupt System C517A 7 Interrupt System The C517A provides 17 interrupt sources with four priority levels Ten interrupts can be generated by the on chip peripherals timer 0 timer 1 timer 2 compare timer compare match set clear A D converter and serial interface 0 and 1 and seven interrupts may be triggered externally P3 2 INTO P3 S INT1 P1 4 INT2 P1 0 INT3 P1 1 INT4 P1 2 INT5 P1 3 INT6 This chapter shows the interrupt structure the interrupt vectors and the interrupt related special function registers Figure 7 1 to 7 3 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections Semiconductor Group 7 1 1997 08 01 SIEMENS Interrupt System C517A Priority Level gt Highest P3 2 lt INTO TCON 1 IX ED TCON 0 UART 1 1CON 21 TH IEN2 0 1CON A D Converter IRCONO 0 IEN1 0 2 s c o 2 co o wn D o A Timer 0 Overflow P14 no Cae s IRCONO 1 Ei ENI T2CON 5 MCS03333 L Bit addressable C 1 Request Flag is cle
116. ator 2nd operand of multiplication Pr Product result of multiplication Rem Remainder Quo Quotient result of division gale means that this byte is the least significant of the 16 bit or 32 bit operand H means that this byte is the most significant of the 16 bit or 32 bit operand Semiconductor Group 6 65 1997 08 01 SIEMENS On Chip Peripheral Components C517A Write Sequence The first and the last write operation in phase one are fixed for every calculation of the MDU All write operations inbetween determine the type of MDU calculation A write to MDO is the first transfer to be done in any case This write resets the MDU and triggers the error flag mechanism see below The next two or three write operations select the calculation type 32bit 16bit 16bit 16bit 16bit x 16bit The last write to MD5 finally starts the selected MUL DIV operation Read Sequence Any read out of the MDx registers should begin with MDO The last read from MD5 division or MD3 multiplication determines the end of a whole calculation and releases the error flag mechanism There is no restriction on the time within which a calculation must be completed The CPU is allowed to continue the program simultaneously to phase 2 and to fetch the result bytes at any time If the user s program takes care that interrupting a calculation is not possible monitoring of the calculation process is probably not needed In this case
117. be cleared by software Semiconductor Group 6 72 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 5 1 4 Baud Rates of Serial Channel 0 There are several possibilities to generate the baud rate clock for the serial interface 0 depending on the mode in which it is operated For clarification some terms regarding the difference between baud rate clock and baud rate should be mentioned The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization Therefore the baud rate generators have to provide a baud rate clock to the serial interface which there divided by 16 results in the actual baud rate However all formulas given in the following section already include the factor and calculate the final baud rate Further the abrevation fosc refers to the oscillator frequency crystal or external clock operation The baud rate of the serial channel 0 is controlled by several bits which are located in the special function registers as shown below Special Function Register ADCONO Address D84 Reset Value 00H Special Function Register PCON Address 87g Reset Value 00H Bit No MSB LSB DFy DEY DD4 DC4 DB4 DAY Dx D8 H H H H H H H H D8H CLK ADEX BSY ADM MX2 MX1 MXO ADCONO 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS SD GF1 GFO PDE IDLE PCON The shaded bits are not used in controlling serial interface 0
118. bers refer to the main definition C ct elo dh i we dri arid 3 15 6 17 part of SFRs or SFR bits CG4EN uv 3 13 3 16 6 49 A CQOEN sea te dee 3 13 3 16 6 42 A D converter 6 93 to 6 104 CCH esee 9 19 91636 25 Block diagram 5 2o eei 6 94 ps EP Rd ELLE Hd E E e Calibration mechanisms 6 104 19297 ie ee 3 13 3417 6 25 Clock selection LLL 6 99 ee PE SUP RS Mer ARS i Conversion time over system clock 6 103 COLT ee esses 3 13 3 16 6 25 Conversion times 6 102 ee S719 8 16 0 25 Conversion timing 6 100 to 6 103 E d E x A 2 2 General operation 6 93 COM ee 3 18 Registers uosiic ee ni 6 95 to 6 98 COMI ee ae 3 18 System clock relationship 6 101 COME DN MEM EN M 3 18 A D converter characteristics 10 5 to 10 6 707077770 Absolute maximum ratings 10 1 E AR TIAS RO DIPENDE SES Pesci E a A srt uo ar a be kt 2 4 3 17 COMBAT 3 18 AC characteristics TOSZdOcHU ID SOSEA pe I Ne AE qua d 18 MHz timing 10 7 to 10 8 COMG eri aoctor ira dut 3 18 24 MHz timing cres o Tom 0 10 DOM nee st oe os cate pue M 3 18 Data memory read cycle 10 12 e uit lS PI AA IE NO Data memory write cycle 10 13 CU AREE 3 4 7 6 34 External clock timing 10 13 T S 317 6 34 Program memory read cycle 10 11 CLKOUT SR gr Cog S Ve EIE 3 15 5 8 ROM verification mode 1 10 14 CLRMSK 3 1 3 3 16 6 29
119. ble This limited bus contention will not cause any damage to port 0 drivers CLKOUT Characteristics Parameter Symbol Limit Values Unit 18 MHz Variable Clock Clock 1 tz c 3 5 MHz to 18 MHz min max min max ALE to CLKOUT tiisn 349 7 terc 40 ns CLKOUT high time tsHsL 71 2 fac 40 ns CLKOUT low time sLsH 516 10 top 40 ns CLKOUT low to ALE high SLLH 16 96 faic 40 faic 40 ns Semiconductor Group 10 7 1997 08 01 SIEMENS Device Specifications C517A AC Characteristics 18 MHz cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 18 MHz Variable Clock Clock 1 tere 3 5 MHz to 18 MHz min max min max RD pulse width TUR 233 6144 100 ns WR pulse width NE 233 6 tac 100 l ns Address hold after ALE fiLaX2 81 2 fcc 30 ns RD to valid data in aie 128 5 tac 150 ns Data hold after RD A 0 0 ns Data float after RD RuDZz 51 2 fcc 60 ns ALE to valid data in fiov 294 8 foc 150 ns Address to valid data in tavoy 335 9 toc 165 ns ALE to WR or RD fw 117 217 3 tac 50 3 fac 50 ns Address valid to WR or RD En 92 4 tac 130 ns WR or RD high to ALE high fwHLH 16 96 faic 40 faic 40 ns Data valid to WR tra
120. capture interrupt capture are located in the SFR IEN2 Special Function Register IEN2 Address 9Aq Reset Value XX0000X0p MSB LSB Bit No 7 6 5 4 3 2 1 0 9AH ECR ECS ECT ECMP ES1 IEN2 The shaded bits are not used for CCU interrupt control Bit Function ECR COMCLR register compare match interrupt enable If ECR 0 the COMCLR compare match interrupt is disabled ECS COMSET register compare match interrupt enable If ECS 0 the COMSET compare match interrupt is disabled ECT Enable compare timer interrupt If ECT 0 the compare timer overflow interrupt is disabled ECMP CMO 7 register compare match interrupt If ECMP 0 the CMO 7 compare match interrupt is disabled Semiconductor Group 6 60 1997 08 01 On Chip Peripheral Components C517A SIEMENS 6 3 6 3 This section handles the CCU related compare match interrupt flags The timer 2 and compare timer overflow interrupt flags TF2 and CTF are described in detail in section 6 3 1 1 and 6 3 2 1 Interrupt Flags of the Compare Capture Unit The compare timer match interrupt occurs on a compare match of the CMO to CM7 registers with the compare timer when compare mode 1 is selected for the corresponding channel There are 8 compare match interrupt flags available in SFR IRCON1 which are or ed together for a single interrupt request Thus a compare match interrupt service routine has to check which compare
121. ce ws Detention d 3 2 3 3 General Purpose Registers 0 0c c eee eee 3 2 3 4 ARAM Operations sob ERG ERR DERE ERR eel tia OS ee ee Pee eus 3 3 3 4 1 ARAN ACCESS Control a su ceases cour PRE wes eRe eos eane aaa E 3 3 3 4 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode 3 5 3 4 3 Accesses to XRAM using the Registers RO R1 00 0 eee eee eee 3 5 3 4 4 Reset Operation of the XRAM 0 00 0c eee 3 9 3 4 5 Behaviour of FPort and Port2 iuis xeREIEOSR EI 0 dee ee deta ew ee Res 3 9 3 5 Special Function REGISIONS seantero tede ae ai Rr eal es 8 eee ree oe 3 11 4 External Bus Interface 0 0 00 cee 4 1 4 1 Accessing External Memory s vro RE mne UR ca aa esa eon pd 4 1 4 1 1 Role of PO and P2 as Data Address Bus 000 cece ees 4 1 4 1 2 BAL tall gle e Superi Mos odio odit des dos Cn TOS ene aded sud Re neem 4 3 4 1 3 External Program Memory Access 0 000 eee eee teens 4 3 4 2 PSEN Program Store Enable user dut ct bi NC Soke oe b bie Be pede ee 4 3 4 3 Overlapping External Data and Program Memory Spaces 4 3 4 4 Enhanced Hooks Emulation Concept 0000 cece eee eee eee 4 4 4 5 Eight Datapointers for Faster External Bus Access 0000 eee eae 4 5 4 5 1 The Importance of Additional Datapointers llli 4 5 4 5 2 How the eight Datapointers of the C517A are realized 2 0005 4 5 4 5 3 Advantages of Multiple Da
122. ct a recovery of the on chip oscillator after a failure If the frequency derived from the on chip oscillator is again higher than the reference the watchdog starts a final reset sequence which takes typ 1 ms Within that time the clock is still supplied by the RC oscillator and the part is held in reset This allows a reliable stabilization of the on chip oscillator After that the watchdog toggles the clock supply back to the on chip oscillator and releases thereset Semiconductor Group 8 7 1997 08 01 SIEMENS Fail Safe Mechanisms C517A request If no reset is applied in this moment the part will start program execution If an external reset is active however the device will keep the reset state until also the external reset request disappears Furthermore the status flag OWDS is set if the oscillator watchdog was active The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog The flag OWDS can be set or cleared by software An external reset request however also resets OWDS and WDTS Special Function Register IPO Address A9p Reset Value 00H MSB LSB Bit No 7 6 5 4 3 2 1 0 A94 OWDS WDTS IPO 5 IPO 4 IP0 3 IPO 2 IPO 1 IPO O IPO The shaded bits are not used for fail save control Bit Function OWDS Oscillator Watchdog Timer Status Flag Set by hardware when an oscillator watchdog reset occured Can be set and cleared by s
123. cteristics a Use of PO and P2 pins during the MOVX access Bus The pins work as external address data bus If internal XRAM is accessed the data written to the XRAM can be seen on the bus in debug mode 1 0 The pins work as Input Output lines under control of their latch b Activation of the RD and WR pin during the access C Use of internal or external XDATA memory The shaded areas describe the standard operation as each 80C51 device without on chip XRAM behaves Semiconductor Group 3 9 1997 08 01 C517A Memory Organization SIEMENS sessoooy XAOIN unna YM AY PU Zd Od JO ANoIAeYyog Z 9 qer Awe L0SO LG08 01 ejqneduioo sepoui pesn si pesn si Ajoujeul1xe 9 pesn s NvuHX 9 pesn si WWHX 9 Ajoujeul1xe 9 pesn s NvuHX 9 pesn s WWHX 9 OAI OEUI OAI OEUI oDueiJ 9 9 HAVGH a e u e uw au a uw qu a SAnoe Haga e u e uw au a YM GH G ebed uppe O I lt 2d O I lt 2d O l lt 2d INVHX O I ed eiegq Hw qu O I ed erg uwaqdg eiea uwauy z sng od e sng od e Orrc ed od e sng od e sng od e sng od e 3ovdx pesn si pesn s pesn si pesn s pesn s pesn si oDuei Kyoujeul1xe o Kjoueur1xe o Kjoueul1xe o Kjoujeur1xe o Kjoueur1xe o Kjoueul1xe o oDed ippe e o YM GH e o uw au a eanoe YMY q eagoe uda e noe uwau a e noe uw au a INVHX O I 2d O I 2d O I 2d O I 2d O I 2d O I 2d gt H sng od e sng od e sng
124. d a ER he Bee AR 7 18 7 5 Interrupt Response Time s cse RR RESETLSwRReXG Y 4 9h REX ex CENE REALE 7 19 Semiconductor Group I 3 1997 08 01 SIEMENS General Information C517A Table of Contents Page 8 Fail Safe Mechanisms csse o i eee ay RR UR ER 8 1 8 1 Programmable Watchdog Timer iis sexe p Gk eee ee ees SEA EG RE EE 8 1 8 1 1 lp Clock Selection x4 a dove oit ratto HU dE ERU ERE QI Ba rad 8 2 8 1 2 Watchdog Timer Control Status Flags 0 00 ccc eee eee eee 8 3 8 1 3 Starting the Watchdog Timer io ra et e node Rr b ede Ok Pp wwe 8 4 8 1 3 1 The First Possibility of Starting the Watchdog Timer ss 8 4 8 1 3 2 The Second Possibility of Starting the Watchdog Timer lusus 8 4 8 1 4 Refreshing the Watchdog Timer 0 00 eee eee eee 8 5 8 1 5 Watchdog Reset and Watchdog Status Flag 20 0c eee eee 8 5 8 2 Oscillator Watchdog Unit ate rer tet br ete a ele D Ro eR eae 8 6 8 2 1 Description of the Oscillator Watchdog Unit 00 00 e eee 8 7 8 2 2 Fast Internal Reset after Power On 000 cc eee eee 8 8 9 Power Saving Modes 000 e eects 9 1 9 1 Power Saving Mode Control Registers 00 cece e ee eee eee 9 1 9 2 Idle ModE Te a siena pube Put peg cat ot up Eee eee same sen bate rx ets 9 2 9 3 Slow Down Mode Operation sse Ee Re eR XE E ER RR RR 9 4 9 4 Software Power Down Mode 00 cece eee eee en 9 5
125. d in controlling timer counter 0 and 1 Bit Function TRO Timer O run control bit Set cleared by software to turn timer counter 0 ON OFF TFO Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 Timer 1 run control bit Set cleared by software to turn timer counter 1 ON OFF TF1 Timer 1 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine Semiconductor Group 6 16 1997 08 01 SIEMENS On Chip Peripheral Components C517A Special Function Register TMOD Address 894 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 894 Gate C T M1 MO Gate C T M1 MO TMOD Timer 1 Control Timer 0 Control Bit Function GATE Gating control When set timer counter x is enabled only while INT x pin is high and TRx control bit is set When cleared timer x is enabled whenever TRx control bit is set C T Counter or timer select bit Set for counter operation input from Tx input pin Cleared for timer operation input from internal system clock M1 Mode select bits MO F M1 MO Function 0 0 8 bit timer counter THx operates as 8 bit timer counter TLx serves as 5 bit prescaler 0 1 16 bit timer counter THx and TLx are cascaded there is no prescaler 1 0 8 bit auto reload timer counter THx holds a value which i
126. dress is used or Port 2 serves as page register which selects pages of 256 Byte However the distinction whether Port 2 is used as general purpose 1 0 or as page address is made by the external system design From the device s point of view it cannot be decided whether the Port 2 data is used externally as address or as 1 0 data Hence a special page register is implemented into the C5174A to provide the possibility of accessing the XRAM also with the MOVX Ri instructions i e XPAGE serves the same function for the XRAM as Port 2 for external data memory Special Function Register XPAGE Address 911 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 914 7 6 5 4 3 2 n 0 XPAGE Bit Function XPAGE 7 0 XRAM high address XPAGE 7 0 is the address part A15 A8 when 8 bit MOVX instructions are used to access the internal XRAM Figures 3 2 to 3 4 show the dependencies of XPAGE and Port 2 addressing in order to explain the differences in accessing XRAM ext RAM or what is to do when Port 2 is used as an I O port Semiconductor Group 3 5 1997 08 01 SIEM ENS Memory Organization C517A gt Address Data Write to Port 2 Page Address MCB02112 Figure 3 2 Write Page Address to Port 2 MOV P2 pageaddress will write the page address to Port 2 and the XPAGE Register When external RAM is to be accessed in the XRAM address
127. e combined by the logical AND of PSEN and RD A positive result from this AND operation produces alow active read strobe that can be used for the combined physical memory Since the PSEN cycle is faster than the RD cycle the external memory needs to be fast enough to adapt to the PSEN cycle Semiconductor Group 4 3 1997 08 01 SIEMENS External Bus Interface C517A 4 4 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers Emulation of on chip ROM based programs is possible too Each C500 production chip has built in logic for the supprt of the Enhanced Hooks Emulation Concept Therefore no costly bond out chips are necessary for emulation This also ensures that emulation and production chips are identical The Enhanced Hooks Technology which requires embedded logic in the C500 allows the C500 together with an EH IC to function similar to a bond out chip This simplifies the design and reduces costs of an ICE system ICE systems using an EH IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers This includes emulation of ROM ROM with code rollover and ROMless modes of operation It is also able to operate in single step mode and to read the SFRs after a break ICE System in
128. e signals define the internal phases states and machine cycles Figure 5 4 shows the recommended oscillator circuit 3 5 24 MHz C C 20 pF 10 pF for Crystal Operation MCS03324 Figure 5 4 Recommended Oscillator Circuit In this application the on chip oscillator is used as a crystal controlled positive reactance oscillator a more detailed schematic is given in figure 5 5 It is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip The crystal specifications and capacitances are non critical In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal A ceramic resonator can be used in place of the crystal in cost critical applications If a ceramic resonator is used the two capacitors normally have different values depending on the oscillator frequency We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors Semiconductor Group 5 6 1997 08 01 SIEMENS Reset System Clock C517A To Internal Timing Circuitry Crystal or ceramic resonator MCS03325 Figure 5 5 On Chip Oscillator Circuitry To drive the C517A with an external clock source the external clock signal has to be applied to XTAL2 as shown in figure 5 6 XTAL1 has to be left unconnected A pullup resistor is suggested to inc
129. e 1 input output P1 2 INT5 CC2 External Interrupt 5 input Capture compare 2 input output P1 3 INT6 CC3 External Interrupt 6 input Capture compare 3 input output P1 4 INT2 CC4 External Interrupt 2 input Capture compare 4 input output P1 5 T2EX Timer 2 external reload trigger input P1 6 CLKOUT System clock output P1 7 T2 Timer 2 external count input P3 0 RxDO Serial port 0 receiver data input asynchronous or data input output synchronous P3 1 TxDO Serial port O transmitter data output asynchronous or data clock output synchronous P3 2 INTO External interrupt O input timer O gate control P3 3 INT1 External interrupt 1 input timer 1 gate control P3 4 TO Timer 0 external count input P3 5 T1 Timer 1 external count input P3 6 WR External data memory write strobe P3 7 RD External data memory read strobe P4 0 CMO Compare output for the CMO register P4 1 CM1 Compare output for the CM1 register P4 2 CM2 Compare output for the CM2 register P4 3 CM3 Compare output for the CM3 register P4 4 CM4 Compare output for the CM4 register P4 5 CM5 Compare output for the CM5 register P4 6 CM6 Compare output for the CM6 register P4 7 CM7 Compare output for the CM7 register P5 0 CCMO Concurrent compare 0 output P5 1 CCM1 Concurrent compare 1 output P5 2 CCM2 Concurrent compare 2 output P5 3 CCM3 Concurrent compare 3 output P5 4 CCM4 Concurrent compare 4 output P5 5 CCM5 Concurrent compare 5 output P5 6 CCM6 Concurrent compare 6 output P5 7 CCM7 C
130. e 10 9 AC Testing Input Output Waveforms Timing Reference Points VoL 40 1 V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded Vow Vo level occurs Ig Ig 2 X 20 mA Figure 10 10 AC Testing Float Waveforms Crystal Oscillator Mode Driving from External Source T XTAL1 NS XTAL1 External Oscillator Signal SON 3 5 24 MHz XTAL2 C Crystal Mode C 20 pF 10 pF incl stray capacitance MCS03339 Figure 10 11 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 10 16 1997 08 01 SIEMENS Device Specifications C517A 10 7 Package Information Plastic Package P MQFP 100 2 SMD Plastic Metric Quad Flat Package A B A B Index Marking 2 Does not Include dambar protrusion of 0 08 max per side 1 Does not include plastic or metal protrusion of 0 25 max per side Figure 10 12 P MQFP 100 2 Package Outline Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Semiconductor Group 10 17 GPM05623 Dimensions in mm 1997 08 01 SIEMENS naex C517A 11 Index C Note Bold page num
131. e DEH TH2 Timer 2 High Byte CDH TL2 Timer 2 Low Byte CCH T2CON Timer 2 Control Register C8y IRCONO Interrupt Control 0 Register COH Semiconductor Group 6 25 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 1 Timer 2 Operation Timer 2 is one of the two 16 bit timer units of the capture compare unit It can operate as timer event counter or gated timer Prior to the description of the timer 2 operating modes and functions the timer 2 related special function registers are described 6 3 1 1 Timer 2 Registers Timer 2 is controlled by bits of the 5 special function register T2CON CTCON IENO IEN1 and IRCONO The related meaning of the timer 2 control bits and flags is shown below Special Function Register T2CON Address C8j Reset Value 00H Special Function Register CTCON Address E1 Reset Value 0X000000p Special Function Register IENO Address A8 Reset Value 00H Special Function Register IEN1 Address B8jj Reset Value 00H Special Function Register IRCONO Address COj Reset Value 00H MSB LSB Bit No CFy CEy CDy CCH CBy CA4 C94 C84 C84 T2PS IBER I2FR T2R1 T2RO T2CM T2 T110 T2CON Elp T2PS1 ICR ICS CTF CLK2 CLK1 CLKO CTCON AF AEQ ADy ACy AB AAW A94 A84 A8H EAL WDT ET2 ESO ET1 EX1 ETO EXO IENO BFy BE BDy BC BBy BA B9 Bay B8y EXEN2 SWDT EX6 EX5 EX4 EX3 EX2
132. e Machine Cycle One Machine Cycle gt S1 s2 s3 s4 s5 se st s2 s3 s4 5 se A without MOVX OUT OUT OUT OUT CR Qut R HOUT AC Noo Ah oin Ah PCL OUT PCL OUT PCL OUT PCL OUT valid valid valid valid One Machine Cycle One Machine Cycle gt s4 s2 s3 s4 s5 se st s2 s3 s4 s5 se B OES DE ei ee 0 PCH DPH OUT OR OUT P2 OUT OUT DATA ro Hou JA out Sn A A A MCT03220 PCL OUT DPL or Ri PCL OUT valid valid valid Figure 4 1 External Program Memory Execution Semiconductor Group 4 2 1997 08 01 SIEMENS External Bus Interface C517A 4 1 2 Timing The timing of the external bus interface in particular the relationship between the control signals ALE PSEN RD WR and information on port 0 and port 2 is illustated in figure 4 1 a and b Data memory in a write cycle the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated In a read cycle the incoming byte is accepted at port O before the read strobe is deactivated Program memory Signal PSEN functions as a read strobe 4 1 3 External Program Memory Access The external program memory is accessed under two conditions whenever signal EA is active low or whenever the program counter PC con
133. e ROM verification mode 1 as shown in figure 4 4 is used to read out the contents of the ROM The AC timing characteristics of the ROM verification mode is shown in the AC specifications chapter 10 MALI Address 1 Address 2 Inputs Vag P2 0 P2 6 Vir Vis Vio Data 1 Out Data 2 Out MCT03255 Figure 4 4 ROM Verification Mode 1 ROM verification mode 1 is selected if the inouts PSEN ALE EA and RESET are put to the specified logic level Then the 14 bit address of the internal ROM byte to be read is applied to the port 1 and port 2 lines After a delay time port 0 outputs the content of the addressed ROM cell In ROM verification mode 1 the C517A must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines Semiconductor Group 4 9 1997 08 01 SIEMENS External Bus Interface C517A 4 6 2 Protected ROM Mode If the ROM is protected the ROM verification mode 2 as shown in figure 4 5 is used to verify the contents of the ROM The detailed timing characteristics of the ROM verification mode is shown in the AC specifications chapter 10 RESET T3 1 ALE Pulse after Reset e a ir Data for Data for Data for y Data for tC X 16 Addr 1 Addr X 16 1 Addr x 16 1 Error High OK Inputs ALE Vss PSEN EA Vy RESET MCT03222 Figure 4 5 ROM Verification Mode 2 ROM verification mode 2 is selected if the inputs PSEN EA and ALE are put to the
134. e arsit iu 3 12 3 15 6 60 7 7 Execution of instructions 2 5 2 6 X EE 3 16 7 11 EXEN2 3 2 2 6 fae Sd eed Ses 3 16 6 27 7 6 ES ius sess Pant eoe nes 3 16 7 11 EXE2 riui eae et ess 3 16 6 27 7 11 EX o esu eee a SN eed 3 16 7 11 External bus interface 4 1 to 4 3 IEXS soe be ete cere a e 3 16 7 11 Overlapping of data program memory 4 3 Nice ci oie te heat Ss cane far St Sta as 3 16 7 11 Program memory access 4 3 INTO aea a 3 16 7 18 Program data memory timing 4 2 UIT AS Bott a T e rct iss 3 16 7 18 PSEN signal zs dod dente dpi 4 3 UIST PUEROS ie at at saat EN Be 3 15 7 18 Role of PO and P2 4 1 IIT e Ee ttt 3 15 7 18 lI EET 3 15 7 18 Firea iris ratete de oai arsed 2 4 3 17 INTS esee n 3 15 7 18 ee eer ee etre i CE 2 4 3 17 INTE 6 eee eee ee eee 3 15 7 18 Fail save mechanisms 8 1 to 8 8 Interrupt system 7 1 to 7 19 Fast power on reset 5 3 8 8 Interrupts Features 1 2 Block diagram 7 2 to 7 4 Functional UNIIS 265 he o EE o EDEN 1 1 Enable registers 7 5 to 7 7 Fundamental structure 2 1 External interrupts 7 18 Handling procedure 7 16 GATE Len a eue 3 15 6 17 Priority registers 7 14 GFO MMC 3 15 9 1 Priority within level structure 7 15 cz MADERA AM 3 15 9 1 POUES NAGS osctsoieden n 51059 Response time 7 19 Sources and vec
135. e interrupt to be negative transition triggered is advisive in the above case Then the compare signal is already inactive and any write access to the port latch just changes the contents of the shadow latch Semiconductor Group 6 59 1997 08 01 SIEMENS On Chip Peripheral Components C517A Please note that for CC registers 1 to 3 an interrupt is always requested when the compare signal goes active The second configuration which should be noted is when compare functions are combined with negative transition activated interrupts If the port latch of port P1 0 or P 1 4 contains a 1 the interrupt request flags IEX3 or IEX2 will immediately be set after enabling the compare mode for the CRC or CC4 register The reason is that first the external interrupt input is controlled by the pin s level When the compare option is enabled the interrupt logic input is switched to the internal compare signal which carries a low level when no true comparison is detected So the interrupt logic sees a 1 to 0 edge and sets the interrupt request flag An unintentional generation of an interrupt during compare initialization can be prevented if the request flag is cleared by software after the compare is activated and before the external interrupt is enabled 6 3 6 2 Interrupt Enable Bits of the Compare Capture Unit This section summarizes all CCU related interrupt enable control bits The interrupt enable bits for the compar timer and the compare match and
136. ead from teh external bus To avoid this the XMAPO bit is forced to 1 only by a reset operation Additionally during reset an internal capacitor is loaded So the reset state is a disabled XRAM Because of the load time of the capacitor XMAPO bit once written to O that is discharging the capacitor cannot be set to 1 again by software On the other hand any distortion software hang up noise is not able to load this capacitor too That is the stable status is XRAM enabled The clear instruction for the XMAPO bit should be integrated in the program initialization routine before the XRAM is used In extremely noisy systems the user may have redundant clear instructions Semiconductor Group 3 4 1997 08 01 SIEM ENS Memory Organization C517A 3 4 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode The XRAM can be accessed by two read write instructions which use the 16 bit DPTR for indirect addressing These instructions are MOVX A QDPTR Read MOVX DPTR A Write For accessing the XRAM the effective address stored in DPTR must be in the range of F800 to FFFFy 3 4 3 Accesses to XRAM using the Registers RO R1 The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8 bit address indirect addressing with registers RO or R1 The instructions are MOVX A Ri Read MOVX Ri A Write In application systems either a real 8 bit bus with 8 bit ad
137. easured from Vec 4 25 V up to stable port condition the delay between power on and the correct port reset state is Typ 18ys Max 34us The RC oscillator will already run at a Voc below 4 25V lower specification limit Therefore at slower Vec rise times the delay time will be less than the two values given above After the on chip oscillator has finally started the oscillator watchdog detects the correct function then the watchdog still holds the reset active for a time period of max 768 cycles of the RC oscillator clock in order to allow the oscillation of the on chip oscillator to stabilize figure 5 2 Il Subsequently the clock is supplied by the on chip oscillator and the oscillator watchdog s reset request is released figure 5 2 IIl However an externally applied reset still remains active figure 5 2 IV and the device does not start program execution figure 5 2 V before the external reset is also released Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up The reasons are as follows Termination of software power down mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence Using a crystal or ceramic resonator for clock generation the external reset signal must be held active at least until the on chip oscillator has started and the internal watchdog reset phase
138. ectively The associated timing is illustrated in figure 6 39 Transmission is initiated by any instruction that uses SOBUF S1BUF as a destination register The write to SOBUF S1BUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control block that a transmission is requested Transmission actually commences at S1P1 of the machine cycle following the next roll over in the divide by 16 counter thus the bit times are synchronized to the divide by 16 counter not to the write to SOBUF S1BUF signal The transmission begins with activation of SEND which puts the start bit to TXDO TXD1 One bit time later DATA is activated which enables the output bit of the transmit shift register to TXDO TXD1 The first shift pulse occurs one bit time after that As data bits shift out to the right zeros are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeros This condition flags the TX control to do one last shift and then deactivate SEND and set TI0 TI1 This occurs at the 10th divide by 16 rollover after write to SOBUF S1BUF Reception is initiated by a detected 1 to 0 transition at RXDO RXD1 For this purpose RXDO RXD1 is sampled at a rate of 16 times whatever baud rate has been established When a reception is
139. ecuted just before timer overflow and the other instruction loading the high byte after the overflow If there were no rule the TOC loading would just load the new low byte into the compare latch The high byte written after timer overflow would have to wait till the next timer overflow The mentioned condition for TOC loading prevents such undesired behavior If the user writes the high byte first then no TOC loading will happen before the low byte has been written even if there is a timer overflow in between If the user just intends to change the low byte of the compare latch then the high byte may be left unaffected Semiconductor Group 6 53 1997 08 01 On Chip Peripheral Components C517A SIEMENS Summary of the TOC loading capability The CMx registers are when assigned to the compare timer protected from direct loading by the CPU A register latch couple provides a defined load time at timer overflow Thus the CPU has a full timer period to load a new compare value there is no danger of overwriting compare values which are still needed in the current timer period When writing a 16 bit compare value the high byte should be written first since the write to low byte instruction enables a 16 bit wide TOC loading at next timer overflow If there was no write access to a CMx low byte then no TOC loading will take place Because of the TOC loading all compare values written to CMx registers are only
140. eeeaeeeeeeeeaeeeeeeeeaeeeeeeenaeeeseeeeeeesenneees 65 C to 150 C Voltage on Vec pins with respect to ground Vss esee 0 5Vto 6 5 V Voltage on any pin with respect to ground Vas eeeeeeeeessse 0 5V to Voc 0 5 V Input current on any pin during overload condition esseesssssss 10 mA to 10 mA Absolute sum of all input currents during overload condition 100 mA Power dISsIBallOliss scene eth nd t anaataatu D home doe iD dm TBD Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions Vn gt Voc or Vn lt Vss the Voltage on Vcc pins with respect to ground Vss must not exceed the values defined by the absolute maximum ratings Semiconductor Group 10 1 1997 08 01 SIEMENS Device Specifications C517A 10 2 DC Characteristics Voc 5V 10 1596 Vas 20V T 0 to 70 C T 40 to 85 C T 40 to 110 C for the SAB C517A for the SAF C517A for the SAH C517A Parameter Symbol Limit Va
141. efore completely independent from any service delay which in real time applications could be disastrous The compare interrupt in turn is not sensitive to such delays since it loads the parameters for the next event This in turn is supposed to happen after a sufficient space of time Please note two special cases where a program using compare interrupts could show a surprising behavior The first configuration has already been mentioned in the description of compare mode 1 The fact that the compare interrupts are transition activated becomes important when driving timer 2 with a slow external clock In this case it should be carefully considered that the compare signal is active as long as the timer 2 count is equal to the contents of the corresponding compare register and that the compare signal has a rising and a falling edge Furthermore the shadow latches used in compare mode 1 are transparent while the compare signal is active Thus with a slow input clock for timer 2 the comparator signal is active for a long time 2 high number of machine cycles and therefore a fast interrupt controlled reload of the compare register could not only change the shadow latch as probably intended but also the output buffer When using the CRC or CCA register you can select whether an interrupt should be generated when the compare signal goes active or inactive depending on the status of bits IBFR or I2FR in T2CON respectively Initializing th
142. em thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged 7 4 External Interrupts The external interrupts 0 and 1 can be programmed to be level activated or negative transition activated by setting or clearing bit ITO or IT1 respectively in register TCON If ITx 0 x 0 or 1 external interrupt x is triggered by a detected low level at the INTx pin If ITx 1 external interrupt x is negative edge triggered In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle interrupt request flag IEx in TCON is set Flag bit IEx then requests the interrupt If the external interrupt O or 1 is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated The external interrupts 2 and 3 can be programmed to be negative or positive transition activated by setting or clearing bit I2FR or I3FR in register T2CON If IXFR 0 x 2 or 3 external interrupt x is negative transition activated If IXFR 1 external interrupt is triggered by a positive transition The external interrupts 4 5 and 6 are activated by a positive transition The external timer 2 reload trigger interrupt request flag EXF2 will be activated by a negative transition at pin
143. eneral purpose registers 3 2 Memory map dos doped reto nse 3 1 Semiconductor Group 11 3 1997 08 01 SIEMENS Semiconductor Group C517A Program memory 3 2 Port O circuitry as sarete iaa 6 5 Multiplication division unit 6 62 to 6 69 Port 1 3 to 6 circuitry 6 6 Error IB eee cre RE donee ened 6 68 Port 2 circuitry eoe 6m er dee fs 6 7 Multiplication and division 6 65 Standard I O port circuitry 6 3 to 6 4 Normalize and shift 6 67 to 6 68 Power down mode Operation 2 ec EP beter oes s 6 64 by hardware 9 7 to 9 12 Overflow flag lesus 6 68 Dy SOUWALC He ila oe ROSE 9 5 Registers 6 62 to 6 63 Power saving modes 9 1 to 9 12 MX sober rate dias teats die 3 17 6 96 Control register 9 1 MXT mit rcs 3 17 6 96 Hardware power down mode 9 7 to 9 12 MXZ urswRRESR eR E edhe 2d 3 17 6 96 Reset timing nx 9 9 WAS hired wheet ee 4 3 17 6 96 Status of external pins 9 7 Idle mode 9 2 to 9 3 Oscillator operation 5 6 to 5 7 Slow down mode 9 4 External clock source 5 7 Software power down mode 9 5 On chip oscillator circuitry 5 7 Entry procedure 9 5 Recommended oscillator circuit 5 6 Exit procedure 4 9 5 Oscillator watchdog 8 6 to 8 8 State of PINS 1 5 eese 9 6 Behaviour at reset
144. er Configurations in the CCU There are two timer compare register configurations in the CCU which can operate in compare mode 0 either timer 2 with a CCx CRC and CC1 to CC4 register or the compare timer with a CMx register They basically operate in the same way but show some differences concerning their modulation range when used for PWM Generally it can be said that for every PWM generation with n bit wide compare registers there are 2 different settings for the duty cycle Starting with a constant low level 0 duty cycle as the first setting the maximum possible duty cycle then would be 1 1 2 x 100 96 This means that a variation of the duty cycle from 096 to real 10096 can never be reached if the compare register and timer register have the same length There is always a spike which is as long as the timer clock period In the C517A there are two different modulation ranges for the above mentioned two timer compare register combinations The difference is the location of the above spike within the timer period at the end of a timer period or at the beginning plus the end of a timer period Please refer to the description of the CCU relevant timer register combinations in section 6 3 4 for details Semiconductor Group 6 38 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 3 2 Compare Mode 1 In compare mode 1 the software adaptively determines the transition of the output signal This mode can only be selec
145. er address byte for accesses to XRAM with MOVX Ri instructions If the address formed by XPAGE and Ri points outside the XRAM address range an external access is performed For the C517A the content of XPAGE must be F84 FFy in order to use the XRAM The software has to distinguish two cases if the MOVX Ri instructions with paging shall be used a Access to XRAM The upper address byte must be written to XPAGE or P2 both writes select the XRAM address range b Access to external memory The upper address byte must be written to P2 XPAGE will be loaded with the same address in order to deselect the XRAM 3 4 4 Reset Operation of the XRAM The contents of the XRAM are not affected by a reset After power up the contents are undefined while they remain unchanged during and after a reset as long as the power supply is not turned off If a reset occurs during a write operation to XRAM the content of a XRAM memory location depends on the cycle in which the active reset signal is detected MOVX is a 2 cycle instruction Reset during 1st cycle The new value will not be written to XRAM The old value is not affected Reset during 2nd cycle The old value in XRAM is overwritten by the new value 3 4 5 Behaviour of PortO and Port2 The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA The table 3 7 lists the various operating conditions It shows the following chara
146. er down mode is maintained while pin HWPD is held active If HWPD goes to high level inactive state an automatic start up procedure is performed First the pins leave their floating condition and enter their default reset state as they had immediately before going to float state Both oscillators are enabled While the on chip oscillator with pins XTAL1 and XTAL2 usually needs a longer time for start up if not externally driven with crystal approx 1 ms the oscillator watchdog s RC oscillator has a very short start up time typ less than 2 us Because the oscillator watchdog is active it detects a failure condition if the on chip oscillator hasn t yet started Hence the watchdog keeps the part in reset and supplies the internal clock from the RC oscillator Finally when the on chip oscillator has started the oscillator watchdog releases the part from reset after it performed a final internal reset sequence and switches the clock supply to the on chip oscillator This is exactly the same procedure as when the oscillator watchdog detects first a failure and then a recovering of the oscillator during normal operation Therefore also the oscillator watchdog status flag is set after restart from hardware power down mode When automatic start of the watchdog was enabled PE SWD connected to Vec the watchdog timer will start too with its default reload value for time out period The SWD Function of the PE SWD Pin is sampled only by a hardwa
147. eral purpose l O pins or under control of the compare capture register CC4 but under control of the compare registers COMSET and COMCLR The details of compare mode 2 are already described in section 6 3 3 3 Figure 6 29 shows the complete compare mode 2 configuration of the CCU and the port 5 pins Comparator Number of Pins for this function is selectable from ICS ICR i 1108 by Bit COCOENO 2 ECS ra ECS J in CC4EN 7 4 IEN2 4 4 IEN2 5 Y Y Int Int Request Request Vector Vector 00A3 00AB MCB02249 Figure 6 29 Compare Mode 2 Port 5 only The compare registers COMSET and COMCLR have their dedicated interrupt vectors The corresponding request flags are ICS for register COMSET and ICR for register COMCLR The flags are set by a match in registers COMSET and COMCLR when enabled As long as the match condition is valid the request flags can t be reset neither by hardware nor software The request flags are located in SFR CTCON Semiconductor Group 6 56 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 5 Modulation Range in Compare Mode 0 In compare mode 0 a 100 variation of the duty cycle of a PWM signal cannot be reached A time portion of 1 2 of an n bit timer period is always left over This spike may either appear when the compare register is set to the reload value limiting the lower end of the modulation range or it may occur at the end of
148. erial interface 0 are TIO or RIO resp See chapter 7 of this user manual for more details about the interrupt structure The interrupt request flags TIO and RIO can also be used for polling the serial interface O if the serial interrupt is not to be used i e serial interrupt O not enabled 6 5 1 2 Multiprocessor Communication Feature Modes 2 and 3 of the serial interface 0 have a special provision for multi processor communication In these modes 9 data bits are received The 9th bit goes into RB80 Then a stop bit follows The port can be programmed such that when the stop bit is received the serial port 0 interrupt will be activated i e the request flag RIO is set only if RB80 1 This feature is enabled by setting bit SM20 in SOCON A way to use this feature in multiprocessor communications is as follows If the master processor wants to transmit a block of data to one of the several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM20 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM20 bit and prepare to receive the data bytes that will be coming After having received a complete message the slave sets SM20 again The slaves that
149. eripheral Components C517A 6 6 4 A D Conversion Timing An A D conversion is internally started by writing into the SFR ADDATL with dummy data A write to SFR ADDATL will start a new conversion even if a conversion is currently in progress The conversion begins with the next machine cycle and the BSY flag in SFR ADCONO will be set The A D conversion procedure is divided into three parts Sample phase ts used for sampling the analog input voltage Conversion phase tco used for the A D conversion includes calibration Write result phase twp used for writing the conversion result into the ADDAT registers The total A D conversion time is defined by tapcc which is the sum of the two phase times ts and tco The duration of the three phases of an A D conversion is specified by its specific timing parameter as shown in figure 6 44 Internal start of Result is written AD conversion into ADDAT BSY Bit Conversion Phase t Write ue Result t ADCC Phase tco A D Conversion Cycle Time twr tin tance ts fco MCT03265 Selected ts tco Divider Ratio 4 8 Figure 6 44 A D Conversion Timing Sample Time ts During this time the internal capacitor array is connected to the selected analog input channel and is loaded with the analog voltage to be converted The analog voltage is internally fed to a voltage comparator With beginning of the sample phase the BSY bit in SFR ADC
150. ernal interrupt 1 CMO 7 match interrupt External interrupt 3 4 Timer 1 overflow Compare timer interrupt External interrupt 4 5 Serial port 0 interrupt Match in COMSET External interrupt 5 6 Timer 2 interrupt Match in COMCLR External interrupt 6 Low Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IPO and one in IP1 A low priority interrupt can itself be interrupted by a high priority interrupt but not by another interrupt of the same or a lower priority An interrupt of the highest priority level cannot be interrupted by another interrupt source If two or more requests of different priority leveis are received simultaneously the request of the highest priority is serviced first If requests of the same priority level are received simultaneously an internal polling sequence determines which request is to be serviced first Thus within each priority level there is a second priority structure determined by the polling sequence as follows Within one interrupt group the left interrupt is serviced first The interrupt groups are serviced from top to bottom of the table Semiconductor Group 7 15 1997 08 01 SIEMENS Interrupt System C517A 7 3 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle The sampled flags are polled during the following machine cycle If one
151. es see figure 6 35 This baud rate generator consists of a free running 10 bit timer with fosc 2 input frequency On overflow of this timer next count step after counter value 3FFp there is an automatic 10 bit reload from the registers 1RELL and S1RELH The lower 8 bits of the timer are reloaded from S1RELL while the upper two bits are reloaded from bit O and 1 of register S1RELH The baud rate timer is reloaded by writing to S1RELL Baud Rate Generator S1RELH afol S1RELL fl Input loek 10 Bit Timer Owerflow MCS03331 Figure 6 35 Baud Rate Generator for Serial Interface 1 Semiconductor Group 6 81 1997 08 01 SIEMENS On Chip Peripheral Components C517A Special Function Register S1RELH Address BBy Reset Value XXXXXX11p Special Function Register S1RELL Address 9D Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 BBH MSB 0 S1RELH 7 6 5 4 3 2 1 0 9D ah 6 5 4 3 2 1 LSB S1RELL Bit Function S1RELH 0 1 Baudrate generator for serial interface 1 reload high value Upper two bits of the baudrate timer reload value S1RELL 0 7 Baudrate generator for serial interface 1 reload low value Lower 8 bits of the baudrate timer reload value The baud rate in operating modes A and B can be determined by following formula Mode A B baud rate oscillator frequency 32 x baud rate generator overflow rate Baud rate ge
152. et Semiconductor Group 6 83 1997 08 01 SIEMENS On Chip Peripheral Components C517A Internal Bus RXDO P3 0 Alt Output Function Shift Shift TX Control Send 2 TXDO TIO P3 1 Alt Output m Function Interrupt Start RIO Receive RX Control RXDO P8 0AIt Input Function Internal Bus 2 MCS01831 Figure 6 36 Functional Diagram Serial Interface 0 Mode 0 Semiconductor Group 6 84 1997 08 01 SIEMENS On Chip Peripheral Components C517A Transmit MCT01832 ra G e 2 z Q c ce oN 2 g Write to SOBUF Shift Clock Shift Clock TXDO TXDO Figure 6 37 Timing Diagram Serial Interface 0 Mode 0 Semiconductor Group 6 85 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 5 3 2 Mode 1 Mode B 8 Bit UART Serial Interfaces 0 and 1 Ten bits are transmitted through TXDO or TXD1 or received through RXDO or RXD1 a start bit 0 8 data bits LSB first and a stop bit 1 On reception through RXDO the stop bit goes into RB80 SOCON on reception through RXD1 RB81 S1CON stores the stop bit The baud rate for serial interface 0 is determined by the timer 1 overflow rate or by the internal baud rate generator of serial interface 0 Serial interface 1 receives the baud rate clock from its own baud rate generator Figure 6 38 shows a simplified functional diagram of the both serial channels in mode 1 or mode B resp
153. evided into a phase 1 half and a phase 2 half Thus a machine cycle consists of 12 oscillator periods numbererd S1P1 state 1 phase 1 through S6P2 state 6 phase 2 Each state lasts one oscillator period Typically arithmetic and logic operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in figure 2 2 show the fetch execute timing related to the internal states and phases Since these internal clock signals are not user accessible the XTAL1 oscillator signals and the ALE address latch enable signal are shown for external reference ALE is normally activated twice during each machine cycle once during S1P2 and S2P1 and again during S4P2 and S5P1 Executing of a one cycle instruction begins at S1P2 when the op code is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If itis a one byte instruction there is still a fetch at S4 butthe byte read which would be the next op code is ignored discarded fetch and the program counter is not incremented In any case execution is completed at the end of S6P2 Figures 2 2 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Semiconductor Group 2 5 1997 08 01 SIEMENS Fundamental Structure C517A ee ee ee P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 PI P2 P1 P2 P1 P2 P1 P2 Read
154. f ports 1 3 4 5 and 6 are multifunctional They are port pins and also serve to implement special features as listed in table 6 1 Figure 6 4 shows a functional diagram of a port latch with alternate function To pass the alternate function to the output pin and vice versa however the gate between the latch and driver circuit must be open Thus to use the alternate input or output functions the corresponding bit latch in the port SFR has to contain a one 1 otherwise the pulldown FET is on and the port pin is stuck at 0 After reset all port latches contain ones 1 Alternate V Output Function Internal Pull Up Arrangement e o Pin Int Bus Write to Latch MCS01827 Alternate Input Function Figure 6 4 Ports 1 3 4 5 and 6 Semiconductor Group 6 6 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 1 2 3 Port 2 Circuitry As shown in figure 6 3 and below in figure 6 5 the output drivers of ports 0 and 2 can be switched to an internal address or address data bus for use in external memory accesses In this application they cannot be used as general purpose I O even if not all address lines are used externally The switching is done by an internal control signal dependent on the input level at the EA pin and or the contents of the program counter If the ports are configured as an address data bus the port latches are disconnected from the driver circuit During thi
155. f the A D conversion If the A D converter interrupt is enabled and the A D converter interrupt is priorized to be serviced immediately the first instruction of the interrupt service routine will be executed in the third machine cycle which follows the write result cycle IADC must be reset by software Depending on the application typically there are three methods to handle the A D conversion in the C517A Software delay The machine cycles of the A D conversion are counted and the program executes a software delay e g NOPs before reading the A D conversion result in the write result cycle This is the fastest method to get the result of an A D conversion Polling BSY bit The BSY bit is polled and the program waits until BSY 0 Attention a polling JB instruction which is two machine cycles long possibly may not recognize the BSY 0 condition during the write result cycle in the continuous conversion mode A D conversion interrupt After the start of an A D conversion the A D converter interrupt is enabled The result of the A D conversion is read in the interrupt service routine If other C517A interrupts are enabled the interrupt latency must be regarded Therefore this software method is the slowest method to get the result of an A D conversion Depending on the oscillator frequency of the C517A and the selected divider ratio of the A D converter prescaler the total time of an A D conversion is calculated according fi
156. fferent location of the RAM which is not used for data storage Semiconductor Group 3 2 1997 08 01 SIEM ENS Memory Organization C517A 3 4 XRAM Operation The XRAM in the C517A is a memory area that is logically located at the upper end of the external memory space but is integrated on the chip Because the XRAM is used in the same way as external data memory the same instruction types MOVX must be used for accessing the XRAM 3 4 1 XRAM Access Control Two bits in SFR SYSCON XMAPO and XMAP1 control the accesses to the XRAM XMAPO is a general access enable disable control bit and XMAP1 controls the external signal generation during XRAM accesses Special Function Register SYSCON Address B14 Reset Value XXXXXX01p Bit No MSB LSB 7 6 5 4 3 2 1 0 BiH XMAP1XMAPO SYSCON The functions of the shaded bits are not described in this section Bit Function Reserved bits for future use XMAP1 XRAM visible access control Control bit for RD WR signals during XRAMaccesses If addresses are outside the XRAM address range or if XRAM is disabled this bit has no effect XMAP1 0 The signals RD and WR are not activated during accesses to the XRAM XMAP1 1 Ports 0 2 and the signals RD and WR are activated during accesses to XRAM In this mode address and data information during XRAM accesses are visible externally XMAPO Global XRAM access enable disable cont
157. flow interrupt the request flag must be cleared by the interrupt service routine as it could be necessary to check whether it was the TF2 flag or the external reload request flag EXF2 which requested the interrupt for EXF2 see below Both request flags cause the program to branch to the same vector address 6 3 1 2 3 Reload of Timer 2 The reload mode for timer 2 see figure 6 15 is selected by bits T2RO and T2R1 in SFR T2CON Two reload modes are selectable In mode 0 when timer 2 rolls over from all 1 s to all O s it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16 bit value in the CRC register which is preset by software The reload will happen in the same machine cycle in which TF2 is set thus overwriting the count value 0000 In mode 1 a 16 bit reload from the CRC register is caused by a negative transition at the corresponding input pin P 1 5 T2EX In addition this transition will set flag EXF2 if bit EXEN2 in SFR IEN1 is set If the timer 2 interrupt is enabled setting EXF2 will generate an interrupt The external input pin T2EX is sampled in every machine cycle When the sampling shows a high in one cycle and a low in the next cycle a transition will be recognized The reload of timer 2 registers will then take place in the cycle following the one in which the transition was detected Semiconductor Group 6 31 1997 08 01 SIEMENS On Chip Peripheral Components C517A Timer 2
158. functions depends on the status of the controller when entering idle mode Normally the port pins hold the logical state they had at the time when the idle mode was activated If some pins are programmed to serve as alternate functions they still continue to output during idle mode if the assigned function is on This especially applies to the system clock output signal at pin P1 6 CLKOUT and to the serial interfaces in case it cannot finish reception or transmission during normal operation The control signals ALE and PSEN are hold at logic high levels As in normal operation mode the ports can be used as inputs during idle mode Thus a capture or reload operation can be triggered the timers can be used to count external events and external interrupts will be detected The idle mode is a useful feature which makes it possible to freeze the processor s status either for a predefined time or until an external event reverts the controller to normal operation as discussed below The watchdog timer is the only peripheral which is automatically stopped during idle mode Semiconductor Group 9 2 1997 08 01 SIEMENS Power Saving Modes C517A The idle mode is entered by two consecutive instructions The first instruction sets the flag bit IDLE PCON O and must not set bit IDLS PCON 5 the following instruction sets the start bit IDLS PCON 5 and must not set bit IDLE PCON 0 The hardware ensures that a concurrent setting of both b
159. gister If a bit in SETMSK is set the corresponding port 5 pin is set in concurrent compare mode if a match of timer 2 and the COMSET registers occurs CLRMSK 7 0 Concurrent compare output clear mask register If a bit in CLRMSK is set the corresponding port 5 pin is reset in concurrent compare mode if a match of timer 2 and the COMCLR registers occurs Semiconductor Group 6 29 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 1 2 Timer 2 Operating Modes Figure 6 14 shows a functional block diagram of the timer 2 unit Programmable Prescaler T210 SFR T2CON No input selected Timer stop EDEN N Counter function P1 7 T2 EIS via ext input P1 7 T2 r Timer 2 be A Gated timer function by ext input P1 7 T2 Input Glogk TL2 TH2 8 Bits 8 Bits 1 Interrupt PLST2EX EXEN2 Reload MCB03328 Figure 6 14 Block Diagram of Timer 2 Timer mode In timer function the count rate is derived from the oscillator frequency A prescaler offers the possibility of selecting a count rate of 1 12 to 1 96 of the oscillator frequency Thus the 16 bit timer register consisting of TH2 and TL2 is incremented at maximum in every machine cycle The prescaler is selected by the bits T2PS1and T2PS Semiconductor Group 6 30 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 1 2 1 Gated Timer Mode In gated timer function the external input pin P1 7 T2 oper
160. gure 6 44 and table 6 14 Figure 6 46 on the next page shows the minimum A D conversion time in relation to the oscillator frequency fosc The minimum conversion time is 6 us which can be achieved at fosc of 16 or 32 MHz Table 6 14 A D Conversion Time for Dedicated System Clock Rates fosc Prescaler fApc MHz Sample Time Total Conversion MHz Ratio ts us Time tApcc us 3 5 4 438 4 57 27 43 12 4 1 5 1 33 8 16 4 2 1 6 18 8 1 125 1 78 10 67 24 8 1 5 1 33 8 Semiconductor Group 6 102 1997 08 01 SIEMENS On Chip Peripheral Components C517A Note The prescaler ratios in table 6 14 are mimimum values At system clock rates fosc up to 16 MHz the divider ratio 4 and 8 can be used At system clock rates greater than 16 MHz only the divider ratio 8 can be used Using higher divider ratios than required increases the total conversion time but can be useful in applications which have voltage sources with higher input resistances for the analog inputs increased sample phase MCD03316 tance min 6 HS Prescaler 4 Prescaler 8 18 20 MHz fosc Figure 6 46 Minimum A D Conversion Time in Relation to System Clock Semiconductor Group 6 103 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 6 5 A D Converter Calibration The C517A A D converter includes hidden internal calibration mechanisms which assure a save functionality of the A D converter accordi
161. her a 16 bit address MOVX DPTR or an 8 bit address MOVX Ri 4 1 1 Role of PO and P2 as Data Address Bus When used for accessing external memory port 0 provides the data byte time multiplexed with the low byte of the address In this state port 0 is disconnected from its own port latch and the address data signal drives both FETs in the port 0 output buffers Thus in this application the port 0 pins are not open drain outputs and do not require external pullup resistors During any access to external memory the CPU writes FFy to the port 0 latch the special function register thus obliterating whatever information the port 0 SFR may have been holding Whenever a 16 bit address is used the high byte of the address comes out on port 2 where it is held for the duration of the read or write cycle During this time the port 2 lines are disconnected from the port 2 latch the special function register Thus the port 2 latch does not have to contain 1s and the contents of the port 2 SFR are not modified If an 8 bit address is used MOVX Ri the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle This will facilitate paging It should be noted that if a port 2 pin outputs an address bit that is a 1 strong pullups will be used for the entire read write cycle and not only for two oscillator periods Semiconductor Group 4 1 1997 08 01 External Bus Interface SIEMENS pale lt On
162. hese flags is cleared by hardware when the service routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and the bit will have to be cleared by software The A D converter interrupt is generated by IADC in register IRCONO It is set some cycles before the result is available That is if an interrupt is generated in any case the converted result in ADDATH ADDADL is valid on the first instruction of the interrupt service routine with respect to the minimal interrupt response time If continuous conversions are established IADC is set once during each conversion If an A D converter interrupt is generated flag IADC must be cleared by software Special Function Register T2CON Address C8j Reset Value 00H MSB LSB Bit No CFy CEy CDy CCy CBu CAH C94 C8y C84 T2PS I3FR I2ZFR T2R1 T2RO T2CM T2H T110 T2CON The shaded bits are not used for interrupt purposes Bit Function ISFR External interrupt 3 rising falling edge control flag If IBFR 0 the external interrupt 3 is activated by a negative transition at INT3 If IBFR 1 the external interrupt 3 is activated by a positive transition at INT3 I2FR External interrupt 2 rising falling edge control flag If IBFR 0 the external interrupt 3 is activated by a negative transition at INT2 If IBFR 1 the external interrupt 3 is activated by a positive transi
163. ied to pin PE SWD This pin serves two functions because it is also used for blocking the power saving modes see also chapter 9 8 1 3 1 The First Possibility of Starting the Watchdog Timer The automatic start of the watchdog timer directly while an external HW reset is a hardware start initialized by strapping pin PE SWD to Vee In this case the power saving modes power down mode idle mode and slow down mode are also disabled and cannot be started by software If pin PE SWD is left unconnected a weak pull up transistor ensures the automatic start of the watchdog timer The self start of the watchdog timer by a pin option has been implemented to provide high system security in electrically very noisy environments Note The automatic start of the watchdog timer is only performed if PE SWD power save enable start watchdog timer is held at high level while RESET or HWPD is active A positive transition at these pins during normal program execution will not start the watchdog timer Furthermore when using the hardware start the watchdog timer starts running with its default time out period The value in the reload register WDTREL however can be overwritten at any time to set any time out period desired 8 1 3 2 The Second Possibility of Starting the Watchdog Timer The watchdog timer can also be started by software Setting of bit SWDT in SFR IEN1 starts the watchdog timer Using the software start the timeout period can be progra
164. ight run for a certain time at reduced speed e g if the controller is waiting for an input signal Since in CMOS devices there is an almost linear dependence of the operating frequency and the power supply current a reduction of the operating frequency results in reduced power consumption In the slow down mode all signal frequencies that are derived from the oscillator clock are divided by 8 This also includes the clock output signal at pin P1 6 CLKOUT Further if the slow down mode is used pin PE SWD must be held low The slow down mode is activated by setting the bit SD in SFR PCON If the slow down mode is enabled the clock signals for the CPU and the peripheral units are reduced to 1 8 of the nominal system clock rate The controller actually enters the slow down mode after a short synchronization period max two machine cycles The slow down mode is disabled by clearing bit SD The slow down mode can be combined with the idle mode by performing the following double instruction sequence ORL PCON 00000001B preparing idle mode set bit IDLE IDLS not set ORL PCON 00110000B entering idle mode combined with the slow down mode IDLS and SD set There are two ways to terminate the combined Idle and Slow Down Mode The idle mode can be terminated by activation of any enabled interrupt The CPU operation is resumed the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the
165. ignal that enables the external program memory to the bus during external fetch operations It is activated every six oscillator periods except during external data memory accesses The signal remains high during internal program execution ALE 23 O The Address Latch enable output is used for latching the address into external memory during normal operation It is activated every six oscillator periods except during an external data memory access Input O Output Semiconductor Group 1 6 1997 08 01 SIEMENS Introduction C517A Table 1 1 Pin Definitions and Functions cont d Symbol Pin Number P MQFP 100 1 O Function EA 24 External Access Enable When held high the C517A executes instructions from the internal ROM as long as the PC is less than 80004 When held low the C517A fetches all instructions from external program memory For the C517A L this pin must be tied low P0 0 P0 7 26 27 30 35 I O Port 0 is an 8 bit open drain bidirectional I O port Port 0 pins that have 1 s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pullup resistors when issuing 1 s Port 0 also outputs the code bytes during program verification in the C517A 4R External pullup
166. imer immediately after reset When left unconnected this pin is pulled high by a weak internal pull up resistor During hardware power down the pullup resisitor is switched off RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C517A A small internal pullup resistor permits power on reset using only a capacitor connected to Vss VAREF 78 T Reference voltage for the A D converter VAGND 79 Reference ground for the A D converter P7 0 P7 7 87 80 Port 7 is an 8 bit unidirectional input port Port pins can be used for digital input if voltage levels meet the specified input high low voltages and for the lower 8 bit of the multiplexed analog inputs of the A D converter simultaneously P7 0 P7 7 AINO AIN7 analog input 8 14 Input O Output Semiconductor Group 1 9 1997 08 01 SIEMENS Introduction C517A Table 1 1 Pin Definitions and Functions contd Symbol Pin Number 1 O Function P MQFP 100 P3 0 P3 7 90 97 O Port3 is an 8 bit quasi bidirectional I O port with internal pullup resistors Port 3 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 3 pins being externally pulled low will source current J i in the DC characteristics because of the internal pullup resistors Port 3 also co
167. ines as compare outputs then the input line from the port pin to the interrupt system is disconnected but the pin s level can still be read under software control Thus a change of the pin s level will not cause a setting of the corresponding interrupt flag In this case the interrupt input is directly connected to the internal compare signal thus providing a compare interrupt The compare interrupt can be used very effectively to change the contents of the compare registers or to determine the level of the port outputs for the next compare match The principle is that the internal compare signal generated at a match between timer count and register contents not only manipulates the compare output but also sets the corresponding interrupt request flag Thus the current task of the CPU is interrupted of course provided the priority of the compare interrupt is higher than the present task priority and the corresponding interrupt service routine is called This service routine then sets up all the necessary parameters for the next compare event 6 3 6 1 Advantages in Using Compare Interrupts Firstly there is no danger of unintentional overwriting a compare register before a match has been reached This could happen when the CPU writes to the compare register without knowing about the actual timer 2 count Secondly and this is the most interesting advantage of the compare feature the output pin is exclusively controlled by hardware ther
168. ion TLO THO and TL1 TH1 counter registers low and high part TCON and TMOD control and mode select registers Special Function Register TLO Address 8A Reset Value 00H Special Function Register THO Address 8C Reset Value 00H Special Function Register TL1 Address 8B Reset Value 00H Special Function Register TH1 Address 8D Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 8AH af 6 5 4 3 2 1 0 TLO 8CH 7 6 5 4 3 2 A 0 THO 8By 7 6 5 4 ko 2 A 0 TL1 8DH 7 6 5 4 i3 2 n 0 TH1 Bit Function TLx 7 0 Timer counter 0 1 low register 20 1 ass Operating Mode Description 0 TLx holds the 5 bit prescaler value 1 TLx holds the lower 8 bit part of the 16 bit timer counter value 2 TLx holds the 8 bit timer counter value 3 TLO holds the 8 bit timer counter value TL1 is not used THx 7 0 Timer counter 0 1 high register aed Operating Mode Description 0 THx holds the 8 bit timer counter value 1 THx holds the higher 8 bit part of the 16 bit timer counter value 2 THx holds the 8 bit reload value 3 THO holds the 8 bit timer value TH1 is not used Semiconductor Group 6 15 1997 08 01 SIEMENS On Chip Peripheral Components C517A Special Function Register TCON Address 881 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 8Fy 8Ey 8Dy 8Cy 8By 8AH 89H 88H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO TCON The shaded bits are not use
169. ion If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed Semiconductor Group 6 89 1997 08 01 SIEMENS On Chip Peripheral Components C517A As data bits come from the right 1 s shift out to the left When the start bit arrives at the leftmost position in the shift register which is a 9 bit register it flags the RX control block to do one last shift load SOBUF S1BUF and RB80 RB81 and set RIO RI1 The signal to load SOBUF S1BUF and RB80 RB81 and to set RIO RI1 will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RIO RI1 0 and 2 either SM20 SM21 0 or the received 9th data bit 1 If either one of these two conditions is not met the received frame is irretrievably lost and RIO RI1 is not set If both conditions are met the received 9th data bit goes into RB80 RB81 the first 8 data bits go into SOBUF S1BUF One bit time later no matter whether the above conditions are met or not the unit goes back to look for a 1 to 0 transition at the RXDO RXD1 input Note that the value of the received stop bit is irrelevant to SOBUF S1BUF RB80 RB81 or RIO RI1 Semiconductor Group 6 90 1997 08 01 SIEMENS On Chip Peripheral Components C517A Internal Bus Shift Data TX Control Send 16 RX Clock Rix Load 1 to 0 SxBUF r Transition
170. its IDLE and IDLS does not initiate the idle mode Bits IDLE and IDLS will automatically be cleared after being set If one of these register bits is read the value that appears is 0 This double instruction is implemented to minimize the chance of an unintentional entering of the idle mode which would leave the watchdog timer s task of system protection without effect Note PCON is not a bit addressable register so the above mentioned sequence for entering the idle mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000001B Set bit IDLE bit IDLS must not be set ORL PCON 00100000B Set bit IDLS bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt This interrupt will be serviced and normally the instruction to be executed following the RETI instruction will be the one following the instruction that sets the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset Semiconductor Group 9 3 1997 08 01 SIEMENS Power Saving Modes C517A 9 3 Slow Down Mode Operation In some applications where power consumption and dissipation is critical the controller m
171. k rate of the watchdog timer is derived from the system clock of the C517A There is a prescaler available which is software selectable and defines the input clock rate This prescaler is controlled by bit WDTPSEL in the SFR WDTREL Tabel 8 1 shows resulting timeout periods at fosc 12 and 24 MHz Special Function Register WDTREL Address 86H Reset Value 00H MSB LSB BitNo 7 6 5 4 3 2 1 0 seH ERT Reload Value WDTREL Bit Function WDTPSEL Watchdog timer prescaler select bit When set the watchdog timer is clocked through an additional divide by 16 prescaler WDTREL 6 0 Seven bit reload value for the high byte of the watchdog timer This value is loaded to WDTH when a refresh is triggered by a consecutive setting of bits WDT and SWDT Table 8 1 Watchdog Timer Time Out Periods WDTPSEL 0 WDTREL Time Out Period Comments fose 12 MHz fosc 24 MHz 00H 65 535 ms 32 768 ms This is the default value 80H 1 18 0 55 s Maximum time period 7FH 512 us 256 us Minimum time period Semiconductor Group 8 2 1997 08 01 SIEMENS Fail Safe Mechanisms C517A 8 1 2 Watchdog Timer Control Status Flags The watchdog timer is controlled by two control flags located in SFR IENO and IEN1 and one status flags located in SFR IPO Special Function Register IENO Address A814 Reset Value 00H Special Function Register IEN1 Address B81 Reset Val
172. l as some enhancements in the Fail Save Mechanism Unit Figure 2 1 shows a block diagram of the C517A Semiconductor Group 2 1 1997 08 01 SIEMENS Fundamental Structure C517A Oscillator Watchdog XRAM ROM 2k x8 32k x 8 OSC amp Timing ER 8 Datapointer Emulation Support Programmable Logic Watchdog Timer Port 0 8 Bit Digital I O Timer 0 Timer 1 Port 1 8 Bit Digital l O Timer 2 Port 2 8 Bit Digital I O Capture Compare Unit Compare Timer Port 3 8 Bit Digital I O Serial Channel 0 Programmable Baud Rate Generator Port 4 8 Bit Digital I O Serial Channel 1 Programmable Baud Rate Generator Interrupt Unit 1 A D Converter 10 Bit Port 5 Port 6 8 Bit Digital I O 8 Bit Digital I O Port 7 8 Bit Analog Digital Input Port 8 4 Bit Analog Digital Input EECA MCB03320 Figure 2 1 Block Diagram of the C517A Semiconductor Group 2 2 1997 08 01 SIEMENS Fundamental Structure C517A 2 1 CPU The CPU is designed to operate on bits and bytes The instructions which consist of up to 3 bytes are performed in one two or four machine cycles One machine cycle requires six oscillator cycles this number of oscillator cycles differs from other members of the C500 microcontr
173. l demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory Start address of ROM source table 1FFFH Start address of table in external RAM 2FA0H Semiconductor Group 4 6 1997 08 01 External Bus Interface C517A SIEMENS Example 1 Using only One Datapointer Code for a C501 Initialization Routine MOV LOW SRC PTR 0FFH MOV HIGH SRC_PTR 1FH MOV LOW DES_PTR 0A0H MOV HIGH DES_PTR 2FH Initialize shadow variables with source pointer Initialize shadow variables with destination pointer Table Look up Routine under Real Time Conditions Number of cycles PUSH DPL Save old datapointer 2 PUSH DPH 2 MOV DPL LOW SRC PTR Load Source Pointer 2 MOV DPH HIGH SRC_PTR 2 INC DPTR Increment and check for end of table execution time CUNE 00 not relevant for this consideration MOVC A DPTR Fetch source data byte from ROM table 2 MOV LOW SRC PTR DPL Save source pointer and 2 MOV HIGH SRC_PTR DPH load destination pointer 2 MOV DPL LOW DES PTR 2 MOV DPH HIGH DES PTR 2 INC DPTR Increment destination pointer ex time not relevant MOVX DPTR A Transfer byte to destination address 2 MOV LOW DES_PTR DPL Save destination pointer 2 MOV HIGH DES PTR DPH 2 POP DPH Restore old datapointer 2 POP DPL 2 Total execution time machine cycles 28 Semiconductor Group 4 7 1997 08 01 SIEMENS External Bus Interface C517A
174. lues Unit Test Condition min max Input low voltage Pins except EA RESET HWPD V 0 5 0 2 Voc 0 1 V EA pin Via 0 5 0 2 Voc 0 3 V HWPD and RESET pins Vio 0 5 0 2 Vog 0 1 V Input high voltage pins except RESET XTAL2 and HWPD Vu 0 2 Voc 0 9 Voc 0 5 V XTAL2 pin Vie 0 7 Voc Voc 0 5 V RESET and HWPD pin Vine 0 6 Voc Voc 0 5 V Output low voltage Ports 1 2 3 4 5 6 Vo 0 45 V lo 2 1 6 mA Port 0 ALE PSEN RO Vou 0 45 V lo 232 mA Output high voltage Ports 1 2 3 4 5 6 Vou 2 4 V lop 80 pA Port 0 in external bus mode Vout 2 4 V lop 800 HA ALE PSEN RO 0 9 Voc V lon 80 pA Logic 0 input current Ports 1 2 3 4 5 6 Ty 10 70 uA Vin 0 45 V Logical 0 to 1 transition current Ports 1 2 3 4 5 6 In 65 650 uA Viu 22V Input leakage current Port 0 7 and 8 EA HWPD L E 4 uA 0 45 lt Vin lt Voc Input low current to RESET for reset Ij 10 100 uA Viy 0 45 V PE SWD OWE lia 20 uA Vin 0 45 V Pin capacitance Cio 10 pF fc21MHz TOA 25 C Overload current Toy t5 mA 78 Notes see next page Semiconductor Group 10 2 1997 08 01 SIEMENS Device Specifications C517A Power Supply Current Parameter Symbol Limit Values Unit Test Condition typ max 1 Active mode 18 MHz Io 21 3 29 2 mA 24 MHz Tec 27 3 37 6 mA Idle mode 18MHz
175. mmed before the watchdog timer starts running Note that once the watchdog timer has been started it can only be stopped if one of the following conditions are met active external hardware reset through pin RESET with a low level at pin PE SWD active hardware power down signal HWPD independently of the level at PE SWD entering idle mode or power down mode by software See chapter 9 for entering the power saving modes by software Semiconductor Group 8 4 1997 08 01 SIEMENS Fail Safe Mechanisms C517A 8 1 4 Refreshing the Watchdog Timer At the same time the watchdog timer is started the 7 bit register WDTH is preset by the contents of WDTREL O to WDTREL 6 Once started the watchdog cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT IENO 6 and by the next instruction setting SWDT IEN1 6 Bit WDT will automatically be cleared during the second machine cycle after having been set For this reason setting SWDT bit has to be a one cycle instruction e g SETB SWDT This double instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog The reload register WDTREL can be written to at any time as already mentioned Therefore a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer Thus a wrong reload value caused by a possible distortion during the write o
176. mode 2 the C517A must be provided with a system clock at the XTAL pins Figure 4 6 shows an application example of an external circuitry which allows to verify a protected ROM inside the C517A 4R in ROM verification mode 2 With RESET going inactive the C517A 4R starts the ROM verify sequence Its ALE is clocking a 16 bit address counter This counter generates the addresses for an external EPROM which is programmed with the contents of the internal protected ROM The verify detect logic typically displays the pass fail information of the verify operation P3 5 can be latched with the falling edge of ALE When the last byte of the internal ROM has been handled the C517A 4R starts generating a PSEN signal This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal ROM verification Carry CLK 15 Bit Address Counter C517A 4R RESET Compare Code ROM MCS03322 Figure 4 6 ROM Verification Mode 2 External Circuitry Example Semiconductor Group 4 11 1997 08 01 SIEMENS Reset System Clock C517A 5 Reset and System Clock Operation 5 1 Hardware Reset Operation The hardware reset function incorporated in the C517A allows for an easy automatic start up at a minimum of additional hardware and forces the controller to a predefined default state The hardware reset function can also be used during normal operation in order to restart
177. mple for a Concurrent Compare Waveform at Port 5 Semiconductor Group 6 48 1997 08 01 SIEMENS On Chip Peripheral Components C517A Special Function Register CC4EN Address C94 Reset Value 00H MSB LSB Bit No 7 6 b 4 3 2 1 0 CoH Sar tg n icd poet COCAH4 COCAL4 COMO CC4EN Bit Function COCOEN 1 Selection of compare modes 1 and 2 at port 5 COCOENO For details on mode selection with COCOEN1 COCOENO see table 6 6 COCON2 Port 5 compare outputs selection COCON 1 These bits select the number of compare outputs at port 5 according the COCONO following table COCON COCON1 COCONO Function 0 0 0 One additional output of CC4 at P5 0 0 0 1 Additional outputs of CC4 at P5 0 to P5 1 0 1 0 Additional outputs of CC4 at P5 0 to P5 2 0 1 1 Additional outputs of CC4 at P5 0 to P5 3 1 0 0 Additional outputs of CC4 at P5 0 to P5 4 1 0 1 Additional outputs of CC4 at P5 0 to P5 5 1 1 0 Additional outputs of CC4 at P5 0 to P5 6 1 1 1 Additional outputs of CC4 at P5 0 to P5 7 COCAH4 Compare capture mode selection for the CC register 4 COCAL4 For details on mode selection with COCAH4 COCAL4 see table 6 6 COMO CC4 compare mode select bit When set compare mode 1 is selected for CC4 COMO 0 selects compare mode 0 for CC4 Setting of bit COCOENO automatically sets COMO Semiconductor Group 6 49 1997 08 01 SIEMENS On Chip Peripheral Component
178. n held at low level the oscillator watchdog function is turned off During hardware power down the pullup resistor is switched off P6 0 P6 7 46 50 I O 54 56 46 47 48 Port 6 is a quasi bidirectional I O port with internal pull up resistors Port 6 pins that have 1 s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 6 pins being externally pulled low will source current Z i in the DC characteristics because of the internal pull up resistors Port 6 also contains the external A D converter start control pin and the transmit and receive pins for the serial interface 1 The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 6 as follows P6 0 ADST external A D converter start pin P6 1 RxD1 receiver data input of serial interface 1 P6 2 TxD1 transmitter data input of serial interface 1 P8 0 P8 3 57 60 Port 8 is a 4 bit unidirectional input port Port pins can be used for digital input if voltage levels meet the specified input high low voltages and for the higher 4 bit of the multiplexed analog inputs of the A D converter simultaneously P8 0 P8 3 AIN8 AIN11 analog input 8 14 Reset Output This pin outputs the internally synchronized reset request signal This signal may be generated by an exte
179. n to the right As data bits shift out to the right zeros come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just left of the MSB and all positions to the left of that contain zeros This condition flags the TX control block to do one last shift and then deactivates SEND and sets TIO Both of these actions occur at S1P1 in the 10th machine cycle after Write to SOBUF Reception is initiated by the condition RENO 1 and RIO 0 At S6P2 in the next machine cycle the RX control unit writes the bits 1111 1110 to the receive shift register and in the next clock phase activates RECEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 in every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shifted one position to the left The value that comes in from the right is the value that was sampled at the P3 0 pin at S5P2 in the same machine cycle As data bits come in from the right 1 s shift out to the left When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register it flags the RX control block to do one last shift and load SOBUF At S1P1 in the 10th machine cycle after the write to SOCON that cleared RIO RECEIVE is cleared and RIO is s
180. nable bits e g EXEN2 Such interrupt enable bits are controlled by specific bits in the SFRs of the corresponding peripheral units This section describes the locations and meanings of the interrupt enable bits in detail After reset the enable bits of the interrupt enable registers IENO to IEN2 are set to 0 That means that the corresponding interrupts are disabled The SFR IENO includes the enable bits for the external interrupts O and 1 the timer 0 1 and 2 interrupts the serial interface O interrupt and the general interrupt enable control bit EAL Special Function Register IENO Address A8 Reset Value 00H MSB LSB BitNo AFy AEQ ADy ACY ABu AAY A94 AH A8H EAL WDT ET2 ESO ET1 EX1 ETO EXO IENO The shaded bit is not used for interrupt control Bit Function EAL Enable disable all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit ET2 Timer 2 interrupt enable If ET2 0 the timer 2 interrupt is disabled ESO Serial channel 0 interrupt enable If ESO 0 the serial channel interrupt 0 is disabled ET1 Timer 1 overflow interrupt enable If ET1 0 the timer 1 interrupt is disabled EX1 External interrupt 1 enable If EX1 0 the external interrupt 1 is disabled ETO Timer 0 overflow interrupt enable If ETO 0 the timer O interrupt is disabled
181. neration SMOD controls a divide by 2 option BD 1 Baud rate generator is used for baud rate generation SMOD controls a divide by 2 option Mode 2 9 bit UART X Fixed baud rate clock fosc 32 SMOD 1 or fosc 64 SMOD 0 Semiconductor Group 6 74 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 5 1 4 1 Baud Rate in Mode 0 The baud rate in mode 0 is fixed to oscillator frequency 12 Mode 0 baud rate 6 5 1 4 2 Baud Rate in Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON If SMOD 0 which is the value after reset the baud rate is 1 64 of the oscillator frequency If SMOD 1 the baud rate is 1 32 of the oscillator frequency 2 SMOD Mode 2 baud rate x oscillator frequency 6 5 1 4 3 Baud Rate in Mode 1 and 3 In these modes the baud rate is variable and can be generated alternatively by the programmable baud rate generator or by timer 1 Using the Programmable Baud Rate Generator In modes 1 and 3 the C517A can use an internal baud rate generator for serial interface 0 To enable this feature bit BD bit 7 of special function register ADCONO must be set Bit SMOD PCON 7 controls a divide by 2 circuit which affects the input and output clock signal of the baud rate generator After reset the divide by 2 circuit is active and the resulting overflow output clock will be divided by 2 The input clock of the baud rate genera
182. nerator overflow rate 21 STREL Semiconductor Group with S1REL S1RELH 1 0 S1RELL 7 0 6 82 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 5 3 Detailed Description of the Operating Modes The following sections give a more detailed description of the several operating modes of the two serial interfaces 6 5 3 1 Mode 0 Synchronous Mode Serial Interface 0 Serial data enters and exits through RXDO TXDO outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at 1 12 of the oscillator frequency Figure 6 36 shows a simplified functional diagram of the serial port in mode 0 The associated timing is illustrated in figure 6 37 Transmission is initiated by any instruction that uses SOBUF as a destination register The Write to SOBUF signal at S6P2 also loads a 1 into the 9th bit position of the transmit shift register and tells the TX control block to commence a transmission The internal timing is such that one full machine cycle will elapse between Write to SOBUF and activation of SEND SEND enables the output of the shift register to the alternate output function line P3 0 and also enables SHIFT CLOCK to the alternate output function line P3 1 SHIFT CLOCK is low during S3 S4 and S5 of every machine cycle and high during S6 S1 and S2 At S6P2 of every machine cycle in which SEND is active the contents of the transmit shift register is shifted one positio
183. ng a capture is for CC1 to CC3 registers A positive transition at pins CC1 to CC3 of port 1 forthe CRC and CC4 register A positive or negative transition at the corresponding pins depending on the status of the bits IBFR and I2FR in SFR T2CON If the edge flags are cleared a capture occurs in response to a negative transition if the edge flags are set a capture occurs in response to a positive transition at pins P1 0 INT3 CCO and P1 4 INT2 CC4 In both cases the appropriate port 1 pin is used as input and the port latch must be programmed to contain a one 1 The external input is sampled in every machine cycle When the sampled input shows a low high level in one cycle and a high low in the next cycle a transition is recognized The timer 2 content is latched to the appropriate capture register in the cycle following the one in which the transition was identified In capture mode 0 a transition at the external capture inputs of registers CCO to CC4 will also set the corresponding external interrupt request flags IEX2 to IEX6 If the interrupts are enabled an external capture signal will cause the CPU to vector to the appropriate interrupt service routine In capture mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register The write to register signal e g write to CRCL is used to initiate a capture The value written to the dedicated capture register is irrelevant for this
184. ng to the DC characteristics The A D converter calibration is implemented in a way that a user program which executes A D conversions is not affected by its operation Further the user program has no control on the calibration mechanism The calibration itself executes two basic functions Offset calibration compensation of the offset error of the internal comparator Linearity calibration correction of the binary weighted capacitor network The A D converter calibration operates in two phases calibration after a reset operation and calibration at each A D conversion The calibration phases are controlled by a state machine in the A D converter This state machine once executes a reset calibration phase after each reset operation of the C517A and stores the result values of the reset calibration phase after its end in an internal RAM Further these values are updated after each A D conversion After a reset operation the A D calibration is automatically started This reset calibration phase which takes 3328 fapc clocks alternating offset and linearity calibration is executed Therefore at 12 MHz oscillator frequency and with the default prescaler value of 4 a reset calibration time of approx 2 2 ms is reached The reset calibration phase is defined as follows tosc 1 fosco Prescaler 4 selected Reset calibration phase 3328 x fapc 13312 x tiy 26624 x tosc Prescaler 8 selected Reset calibration phase 3328 x f
185. nization C517A 3 1 Program Memory Code Space The C517A 4R has 32 Kbytes of read only program memory which can be externally expanded up to 64 Kbytes If the EA pin is held high the C517A 4R executes program code out of the internal ROM unless the program counter address exceeds 7FFF Address locations 80004 through FFFFy are then fetched from the external program memory If the EA pin is held low the C517A fetches all instructions from the external 64K byte program memory 3 2 Data Memory Data Space The data memory address space consists of an internal and an external memory space The internal data memory is divided into three physically separate and distinct blocks the lower 128 bytes of RAM the upper 128 bytes of RAM and the 128 byte special function register SFR area While the upper 128 bytes of data memory and the SFR area share the same address locations they are accessed through different addressing modes The lower 128 bytes of data memory can be accessed through direct or register indirect addressing the upper 128 bytes of RAM can be accessed through register indirect addressing the special function registers are accessible through direct addressing Four 8 register banks each bank consisting of eight 8 bit multi purpose registers occupy locations 0 through 1Fp in the lower RAM area The next 16 bytes locations 204 through 2Fy contain 128 directly addressable bit locations The stack can be located anywhere in the
186. nsition Iovi 11 tere 45 ns Data setup before WR avw 239 7 tac 150 ns Data hold after WR tnia 16 _ feci 40 _ ns Address float after RD f 0 0 ns External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 18 MHz min max Oscillator period toc 55 6 285 7 ns High time cucx 15 terel feicx ns Low time cicx 15 toro fcucx ns Rise time ToLcH s 15 ns Fall time ToHCL 15 ns Semiconductor Group 10 8 1997 08 01 SIEMENS Device Specifications C517A 10 5 AC Characteristics 24 MHz Vac 5 V 10 1595 Vss 0 V T 0 to 70 C for the SAB C517A T 40 to 85 C for the SAF C517A C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 24 MHz Variable Clock Clock l c c 3 5 MHz to 24 MHz min max min max ALE pulse width TR 43 l Bod l ns Address setup to ALE AVLL 17 toro 25 ns Address hold after ALE tax 17 toro 25 ns ALE low to valid instruction in fy 80 4 tore 87 ns ALE to PSEN fiip 22 terc 20 ns PSEN pulse width leip 95 3teic 30 ns PSEN to valid instruction in fot 60 3 tore 65 ns Input instruction hold after PSEN tpx x 0 0 ns Input instruction float after PSEN tpxiz 32 toc 10 ns Address valid af
187. nstructions as shown in the following example ORL PCON 00000010B set bit PDE bit PDS must not be set ORL PCON 01000000B set bit PDS bit PDE must not be set enter power down The instruction that sets bit PDS is the last instruction executed before going into software power down mode 9 4 2 Exit from Software Power Down Mode If software power down mode is exit via a hardware reset the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed The reset signal that terminates the software power down mode also restarts the RC oscillator and the on chip oscillatror The reset operation should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset Semiconductor Group 9 5 1997 08 01 SIEMENS Power Saving Modes C517A 9 5 State of Pins in Software Initiated Power Saving Modes In the idle mode and in the software power down mode the port pins of the C517A have a well defined status which is listed in the following table 9 1 This state of some pins also depends on the location of the code memory internal or external Table 9 1 Status of External Pins During Idle and Software Power Down Mode Outputs Last Instruction Executed from Last Instruction Executed from Internal Code Memory External Code Memory Idle Power Down
188. ntains the interrupt timer serial port and external memory strobe pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 3 as follows 90 P3 0 RxDO Receiver data input asynch or data input output synch of serial interface 0 91 P3 1 TxDO Transmitter data output asynch or clock output synch of serial interface 0 92 P3 2 INTO External interrupt O input timer O gate control input 93 P3 3 INT1 External interrupt 1 input timer 1 gate control input 94 P3 4 TO Timer 0 counter input 95 P3 5 T1 Timer 1 counter input 96 P3 6 WR WR control output latches the data byte from port 0 into the external data memory 97 P3 7 RD RD control output enables the external data memory N C 2 5 25 Not connected 28 29 32 These pins of the P MQFP 100 package need not be 43 44 connected 51 53 74 T7 88 89 Input O Output Semiconductor Group 1 10 1997 08 01 SIEMENS Fundamental Structure C517A 2 Fundamental Structure The C517A is fully compatible to the architecture of the standard 8051 C501 microcontroller family While maintaining all architectural and operational characteristics of the C501 the C517A incorporates a CPU with 8 datapointers a genuine 10 bit A D converter a capture compare unit two USART serial interfaces a XRAM data memory as wel
189. oberen 3 12 3 15 6 15 6 92 WE ots kee on ore Y 3 13 3 17 6 28 Serial interface 0 6 70 to 6 78 Bt EDEN 3 15 6 71 6 72 7 9 Baudrate generation 6 73 to 6 78 TET a iei tei RS 3 15 6 80 7 9 Multiprocessor communication 6 71 Timer GOUlter css x Rua Rx AR 6 14 Operating modes 6 70 to 6 71 Compare timer 6 33 to 6 36 Registers 0 6 72 Block diagram 6 35 Serial interface 1 6 79 to 6 82 Operating modes 6 35 to 6 36 Baud rate generation 6 81 to 6 82 Registers 6 33 to 6 34 Multiprocessor communication 6 81 Timer counter O0 and 1 6 14 to 6 21 Operating modes 6 79 Mode 0 13 bit timer counter 6 18 RegisterS 000 eee eee 6 80 Mode 1 16 bit timer counter 6 19 SETMSK wns ae deg te 3 13 3 16 6 29 Mode 2 8 bit rel timer counter 6 20 BUR 5 wEERW oats eS 3 18 6 63 Mode 3 two 8 bit timer counter 6 21 SM ossa Piva aed wees wt 3 15 6 80 Registers es een 6 15 to 6 17 SMO 5e 9ukeR RR et ae Ge IS 3 15 6 72 Timer counter 2 6 26 to 6 32 SMA cr EE ERE RES 3 15 6 72 Block diagram 6 30 SM20 niece be hed obra ES 3 15 6 72 Capture mode 6 45 to 6 46 IMO aca aca us ore rd 3 15 6 80 Compare mode 6 42 to 6 44 SMOD out tent atr tenait 3 15 6 73 Concurrent compare mode 6 47 to 6 48 SPetr x Mere Bra 2 4 3 12 3 15 Event counter mode
190. ode 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P1 3 INT6 CC3 1 0 Compare enabled 1 1 Capture on write operation into register CCL3 Semiconductor Group 6 42 1997 08 01 SIEMENS On Chip Peripheral Components C517A Bit Function COCAH2 Compare capture mode for the CC register 2 RE COCAH2 COCAL2 Mode 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P1 2 INT5 CC2 1 0 Compare enabled 1 1 Capture on write operation into register CCL2 COCAH1 Compare capture mode for the CC register 2 SORA COCAH1 COCAL1 Mode 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P1 1 INT4 CC1 1 0 Compare enabled 1 1 Capture on write operation into register CCL1 COCAHO Compare capture mode for the CC register 2 ene COCAHO COCALO Mode 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P1 0 INT3 CCO 1 0 Compare enabled 1 1 Capture on write operation into register CRCL Figure 6 21 and 6 22 show the general timer compare register port latch configuration for registers CRC and CC1 to CC4 in compare mode 0 and compare mode 1 It also shows the interrupt capabilities The compare interrupts of registers CRC and CC4 can be programmed to be either negative or positive transition activated Compare interrupts for the CC1 to CC3 registers are always positive transition activated The compare function
191. of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is brought into reset if the failure condition disappears i e the on chip oscillator has a higher frequency than the RC oscillator the part executes a final reset phase of typ 1 ms in order to allow the oscillator to stabilize then the oscillator watchdog reset is released and the part starts program execution again Fast internal reset after power on The oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator has started The oscillator watchdog unit also works identically to the monitoring function Restart from the hardware power down mode If the hardware power down mode is terminated the oscillator watchdog has to control the correct start up of the on chip oscillator and to restart the program The oscillator watchdog function is only part of the complete hardware power down sequence however the watchdog works identically to the monitoring function Note The oscillator watchdog unit is always enabled Semiconductor Group 8 6 1997 08 01 SIEMENS Fail Safe Mechanisms C517A 8 2 1 Description of the Oscillator Watchdog Unit Figure 8 3 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the on chip oscillator It also shows the modifications
192. of CC4 is described in section 6 3 4 3 Semiconductor Group 6 43 1997 08 01 SIEMENS On Chip Peripheral Components C517A Compare Register Shaded Functions for CRC CCx CRC and CC4 only l fi TL Set Latch e Compare Signal Reset Latch Port Latch JTL Overflow Timer 2 Interrupt MCS02664 Figure 6 21 Timer 2 with Registers CRC and CC1 to CC4 in Compare Mode 0 Interrupt Compare Register Shaded Functions for CRC CCx CRC and CC4 only IL Port C t Compare Signal Om Shadow Latch Overflow gt Interrupt 1 Ord OutputLatch P1 0 INT3 cco MCS02665 Figure 6 22 Timer 2 with Registers CRC and CC1 to CC3 in Compare Mode 1 Semiconductor Group 6 44 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 4 2 Timer 2 Capture Function with Registers CRC CC1 to CC4 Each of the four compare capture registers CC1 to CC4 and the CRC register can be used to latch the current 16 bit value of the timer 2 registers TL2 and TH2 Two different modes are provided for the capture function In capture mode 0 an external event latches the timer 2 contents to a dedicated capture register In capture mode 1 a capture event will occur when the low order byte of the dedicated 16 bit capture register is written to This capture mode is provided to allow the software to read the timer 2 contents on the fly In capture mode O0 the external event causi
193. oftware 8 2 2 Fast Internal Reset after Power On The C517A can use the oscillator watchdog unit for a fast internal reset procedure after power on Normally the members of the 8051 family e g SAB 80C52 enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 1 ms During this time period the pins have an undefined state which could have severe effects e g to actuators connected to port pins In the C517A the oscillator watchdog unit avoids this situation After power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip This allows correct resetting of the part and brings all ports to the defined state see also chapter 5 of this manual The delay time between power on and correct reset state is max 34 us more details see chapter 5 2 Semiconductor Group 8 8 1997 08 01
194. oller family The instruction set has extensive facilities for data transfer logic and arithmetic instructions The Boolean processor has its own full featured and bit based instructions within the instruction set The C517A uses five addressing modes direct access immediate register register indirect access and for accessing the external data or program memory portions a base register plus index register indirect addressing Efficient use of program memory results from an instruction set consisting of 44 one byte 41 two byte and 15 three byte instructions With a 24 MHz clock 58 of the instructions execute in 500 ns The CPU Central Processing Unit of the C517A consists of the instruction decoder the arithmetic section and the program control section Each program instruction is decoded by the instruction decoder This unit generates the internal signals controlling the functions of the individual units within the CPU They have an effect on the source and destination of data transfers and control the ALU processing The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic logic unit ALU an A register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs the arithmetic operations add substract multiply divide increment decrement BDC decimal add adju
195. on cannot be interrupted by other calculations then there is no need to pay attention to the error flag In this case it is also possible to change the order in which the MDx registers are read or even to skip some register read instructions Concerning the shift or normalize instructions it is possible to read the result before the complete execution time of six machine cycles has passed e g when a small number of shifts has been programmed All of the above illegal actions would set the error flag but on the other hand do not affect a correct MDU operation The user has just to make sure that everything goes right The error flag MDEF is located in ARCON and can be read only It is automatically cleared after being read Semiconductor Group 6 69 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 5 Serial Interfaces The C517A has two serial interfaces which are functionally nearly identical concerning the asynchronous modes of operation The two channels are full duplex meaning they can transmit and receive simultaneously They are also receive buffered meaning they can commence reception of a second byte before a previously received byte has been read from the receive register however if the first byte still has not been read by the time reception of the second byte is complete the last received byte will be lost The serial channel 0 is completely compatible with the serial channel of the C501 Serial channel 1 has the
196. on ett 3 16 8 3 WDTPSEL 545342 je bel 3 15 8 2 WDTHEU s cies WEIT 3 14 3 15 8 2 WD TS vest Rab xu Ee ES 3 16 8 3 lg TI iuni gitan a Koe as 3 16 X XMAP O admen ta en Redd E En 3 3 XMAP To od teks aiia res Eos Eos 3 3 APAGE ie are Boe es 3 5 3 14 3 15 XRAM operation 3 3 to 3 10 Access control by SYSCON 3 3 Access with DPTR 16 bit 3 5 Access with RO R1 8 bit 3 5 Programming example 3 8 Usage of port 2 as l Oport 3 8 Write page address to port 2 3 6 Write page address to XPAGE 3 7 XPAGE register 3 5 Behaviour of port 0 and 2 with MOVX 3 9 Reset operation 3 9 Table PO P2 during MOVX instr 3 10 Semiconductor Group 11 6 1997 08 01
197. oncurrent compare 7 output P6 0 ADST External A D converter start P6 1 RxD1 Serial port 1 receiver data input P6 2 TxD1 Serial port 1 transmitter data output Semiconductor Group 6 2 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 1 2 Standard I O Port Circuitry Figure 6 1 shows a functional diagram of a typical bit latch and I O buffer which is the core of each of the seven l O ports The bit latch one bit in the port s SFR is represented as a type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read from a port i e from the corresponding port SFR PO to P6 activate the read latch signal while others activate the read pin signal Port Driver Circuit MCS01822 Figure 6 1 Basic Structure of a Port Circuitry Semiconductor Group 6 3 1997 08 01 SIEMENS On Chip Peripheral Components C517A The output drivers of port 1 to 6 have internal pullup FET s see figure 6 2 Each I O line can be used independently as an input or output To be used as an input the port bit stored in the bit latch must contain a one 1 that means for figure 6 2 Q 0 which turns off the output driver FET n1
198. only the write sequence must be observed Any new write access to MDO starts a new calculation no matter whether the read out of the former result has been completed or not Semiconductor Group 6 66 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 4 4 Normalize and Shift Register ARCON controls an up to 32 bit wide normalize and shift operation in registers MDO to MD3 It also contains the overflow flag and the error flag which are described in the next two sections Write Sequence A write to MDO is also the first transfer to be done for normalize and shift This write resets the MDU and triggers the error flag mechanism see below To start a shift or normalize operation the last write must access register ARCON Read Sequence The order in which the first three registers MDO to MD2 are read is not critical The last read from MD3 determines the end of a whole shift or normalize procedure and releases the error flag mechanism Note Any write access to ARCON triggers a shift or normalize operation and therefore changes the contents of registers MDO to MD3 Normalizing Normalizing is done on an integer variable stored in MDO least significant byte to MD3 most significant byte This feature is mainly meant to support applications where floating point arithmetic is used To normalize means that all reading zeroes of an integer variable in registers MDO to MD3 are removed by shift left operations
199. ot to the write to SOBUF S1 BUF signal The transmission begins with the activation of SEND which puts the start bit to TXDO TXD1 One bit time later DATA is activated which enables the output bit of transmit shift register to TXDO TXD1 The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift register Thereafter only zeros are clocked in Thus as data shift out to the right zeros are clocked in from the left When TB80 TB81 is at the output position of the shift register then the stop bit is just left of the TB80 TB81 and all positions to the left of that contain zeros This condition flags the TX control unit to do one last shift and then deactivate SEND and set TIO TI1 This occurs at the 11th divide by 16 rollover after write to SOBUF S1BUF Reception is initiated by a detected 1 to 0 transition at RXDO RXD1 For this purpose RXDO RXD1 is sampled of a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written to the input shift register At the 7th 8th and 9th counter state of each bit time the bit detector samples the value of RxDO RxD1 The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to O transit
200. ovides an additional pullup current if a logic high level shall be output at the pin and the voltage is not forced lower than approximately 1 0 to Semiconductor Group 6 9 1997 08 01 SIEMENS On Chip Peripheral Components C517A 1 5 V However this transistor is turned off if the pin is driven to a logic low level e g when used as input In this configuration only the weak pullup FET p2 is active which sources the current J If in addition the pullup FET p3 is activated a higher current can be sourced Thus an additional power consumption can be avoided if port pins are used as inputs with a low level applied However the driving capability is stronger if a logic high level is output The described activating and deactivating of the four different transistors translates into four states the pins can be inputlow state IL p2 active only input high state IH steady output high state SOH p2 and p3 active forced output high state FOH p1 p2 and p3 active output low state OL n1 active If a pin is used as input and a low level is applied it will be in IL state if a high level is applied it will switch to IH state If the latch is loaded with O the pin will be in OL state If the latch holds a 0 and is loaded with 1 the pin will enter FOH state for two cycles and then switch to SOH state If the latch holds a 1 and is reloaded with a 1 no state change will occur At the beginning of power on
201. oy 220 9 toc 155 ns ALE to WR or RD fw 75 175 3 tag 50 3 foc 50 ns Address valid to WR or RD En 67 4 tac 97 ns WR or RD high to ALE high fwHLH 17 67 faic 25 faic 25 ns Data valid to WR transition TONNY 5 tere 37 ns Data setup before WR avw 170 7 tac 122 ns Data hold after WR udo 15 _ terc 27 _ ns Address float after RD f 0 0 ns External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 24 MHz min max Oscillator period teLcL 41 7 285 7 ns High time cucx 12 terel feicx ns Low time cicx 12 cici fcucx ns Rise time cicH 12 ns Fall time feHcL 12 ns Semiconductor Group 10 10 1997 08 01 Device Specifications SIEMENS on th gt ALE F zn zi MCT00096 Figure 10 2 Program Memory Read Cycle Semiconductor Group 10 11 1997 08 01 Device Specifications SIEMENS on t AVWL DV P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00097 Figure 10 3 Data Memory Read Cycle CLK OUT Program Memory Access Data Memory Access MCTO0083 Figure 10 4 CLKOUT Timing Semiconductor Group 10 12 1997 08 01 Device Specifications SIEMENS on ag A0 A7 from Y A0 A7 Ri or DPL Data OUT MA _ from PCL SUN E Cave i P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00098
202. pare register CC4 To Interrupt Logic P14 Compare Register CC4 poe nee tlt y fi COCON 1 TH2 TL2 COCON Timer 2 COCONS Output Buffer Oo O P57 P14 CCM7_INT2 CC4 MCS02666 Figure 6 25 Concurrent Compare Function of Register CC4 Semiconductor Group 6 47 1997 08 01 SIEMENS On Chip Peripheral Components C517A Figure 6 26 gives an example of how to generate eight different rectangular wave forms at port 5 using a pattern table and a time schedule for these patterns The patterns are moved into port 5 before the corresponding timer count is reached The future timer count at which the pattern shall appear at the port must be loaded to register CC4 Thus the user can mask each port bit differently depending on whether he wants the output to be changed or not Concurrent compare is enabled by setting bit COCOEN in special function register CCAEN A 1 in this bit automatically sets compare mode 1 for register CC4 too A 3 bit field in special function register CCAEN determines the additional number of output pins at port 5 Port P1 4 INT2 CC4 is used as a standard output pin in any compare mode for register CC4 Pattern Table 8 Bit Schedule Table 16 Bit Compare Register CC4H CC4L A Port 5 Latch 00H Timer Count 1000H 2000H 30004 40004 P5 7 P5 6 P5 5 Port Pattern P5 4 P5 3 P5 2 P5 1 P5 0 MCT01853 Figure 6 26 Exa
203. pare Timer Control Register Ely 0X00 0000p MUL DIV ARCON _ Arithmetic Control Register EFy OXXXXXXXp 9 Unit MDO Multiplication Division Register 0 E9H XXH MD1 Multiplication Division Register 1 EAH XXH MD2 Multiplication Division Register 2 EBH XXH MD3 Multiplication Division Register 3 ECH XXH MD4 Multiplication Division Register 4 EDH XXH MD5 Multiplication Division Register 5 EEH XXH Timer0 TCON Timer 0 1 Control Register 884 00H Timer 1 THO Timer 0 High Byte 8Cy 00H TH1 Timer 1 High Byte 8DH 00H TLO Timer 0 Low Byte 8AH 00H TL1 Timer 1 Low Byte 8BH 00H TMOD Timer Mode Register 89H 00H 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved Semiconductor Group 1997 08 01 SIEMENS Memory Organization C517A Table 3 1 Special Function Registers Functional Blocks cont d Block Symbol Name Address Contents after Reset Compare CCEN Compare Capture Enable Register Ciy 00H Capture CCA4EN Compare Capture 4 Enable Register C9H 00H Unit CCH1 Compare Capture Register 1 High Byte C3y 00H CCU CCH2 Compare Capture Register 2 High Byte C5H 00H Timer 2 CCH3 Compare Capture Register 3 High Byte C7H 00H CCH4 Compare Capture Register 4 High Byte CFH 00H CCL1 Compare Capture Register 1 Low
204. peration to the WDTREL can be corrected by software 8 1 5 Watchdog Reset and Watchdog Status Flag If the software fails to clear the watchdog in time an internally generated watchdog reset is entered at the counter state 7FFCH The duration of the reset signal then depends on the prescaler selection either 8 cycles or 128 cycles This internal reset differs from an external one only in so far as the watchdog timer is not disabled and bit WDTS watchdog timer status bit 6 in SFR IPO is set Figure 8 2 shows a block diagram of all reset requests in the C517A and the function of the watchdog status flags The WDTS flag is a flip flop which is set by a watchdog timer reset and cleared by an external HW reset Bit WDTS allows the software to examine from which source the reset was activated The watchdog timer status flag can also be cleared by software OWD Reset Request WDT Reset Request OWDS WDTS Synchronization nee Clear External HW Reset Request External HW Power Down Request RESETo HWPD o lt v v gt Internal Bus MCS02756 Figure 8 2 Watchdog Timer Status Flags and Reset Requests Semiconductor Group 8 5 1997 08 01 SIEMENS Fail Safe Mechanisms C517A 8 2 Oscillator Watchdog Unit The oscillator watchdog unit serves for four functions Monitoring of the on chip oscillator s function The watchdog supervises the on chip oscillator s frequency if it is lower than the frequency
205. pt request flag for compare register COMSET ICS is set when a compare match occured ICS is cleared by hardware when the processor vectors to interrupt routine CTF Compare timer overflow flag CTF is set when the compare timer 1 count rolls over from all ones to the reload value When CTF is set a compare timer interrupt can be generated if enabled CTF is cleared by hardware when the compare timer value is no more equal to the reload value All of these interrupt request bits that generate interrupts can be set or cleared by software with the same result as if they had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be cancelled by software The only exceptions are the request flags IEO and IE1 If the external interrupts O and 1 are programmed to be level activated IEO and IE1 are controlled by the external source via pin INTO and INT1 respectively Thus writing a one to these bits will not set the request flag IEO and or IE1 In this mode interrupts O and 1 can only be generated by software and by writing a 0 to the corresponding pins INTO P3 2 and INT1 P3 3 provided that this will not affect any peripheral circuit connected to the pins Semiconductor Group 7 13 1997 08 01 IE Interrupt System SIEMENS C517A 7 1 3 Interrupt Priority Registers The 17 interrupt sources of the C517A are combined to six interrupt groups Each of the six interrupt groups can be programmed to
206. put clock from a programmable prescaler which provides eight input frequencies ranging from fosc 2 up to fos 256 This configuration allows a very high flexibility concerning timer period length and input clock frequency The prescaler ratio is selected by four bits in the special function registers CTCON Figure 6 16 shows the block diagram of the compare timer 3 Bit Prescaler Compare Timer 2 4 i8 A6 32 64 Control CTCON To Compare Circuitry To Interrupt Circuitry 16 Bit Compare Timer Overflow 16 Bit Reload CTREL MCB00783 Figure 6 16 Compare Timer Block Diagram The compare timer is once started a free running 16 bit timer which upon overflow is automatically reloaded by the content of the 16 bit reload register This reload register is CTRELL compare timer reload register low byte and CTRELH compare timer reload register high byte An initial writing to the reload register CTRELL starts the corresponding compare timer If a compare timer is already running a write to CTRELL again triggers an instantly reload of the timer in other words loads the timer in the cycle following the write instruction with the new count stored in the reload registers CTRELH CTRELL When the reload register is to be loaded with a 16 bit value the high byte of the reload register CTRELH must be written first to ensure a determined start or restart position Writing to the low byte CTRELL then
207. r frequency the commonly used baud rates 4800 baud SMOD 0 and 9600 baud SMOD 1 are available with 0 16 96 deviation With the baud rate generator as clock source for the serial port 0 in mode 1 and 3 the baud rate of can be determined as follows 23VOP x oscillator frequency Mode 1 3 baud rate 64 x baud rate generator overflow rate Baud rate generator overflow rate 21 SOREL with SOREL SORELH 1 0 SORELL 7 0 Semiconductor Group 6 76 1997 08 01 SIEMENS On Chip Peripheral Components C517A Using Timer 1 for Baud Rate Generation In mode 1 and 3 of serial interfacel O timer 1 can be used for generating baud rates Then the baud rate is determined by the timer 1 overflow rate and the value of SMOD as follows SMOD 32 Mode 1 3 baud rate x timer 1 overflow rate The timer 1 interrupt is usually disabled in this application Timer 1 itself can be configured for either timer or counter operation and in any of its operating modes In most typical applications it is configured for timer operation in the auto reload mode high nibble of TMOD 0010p In this case the baud rate is given by the formula 25VOD x oscillator frequency Mode 1 3 baud rate 32 x 12 x 256 TH1 Very low baud rates can be achieved with timer 1 if leaving the timer 1 interrupt enabled configuring the timer to run as 16 bit timer high nibble of TMOD 0001 p and using the timer 1 interrupt fo
208. r interrupted by a new operation This can possibly happen e g when an interrupt service routine interrupts the writing or reading sequence of the arithmetic operation in the main program and starts a new operation Then the contents of the corresponding registers are indeterminate they would normally show the result of the last operation executed In this case the error flag can be used to indicate whether the values in the registers MDO to MD5 are the expected ones or whether the operation must be repeated For a multiplication division the error flag mechanism is automatically enabled with the first write instruction to MDO phase 1 According to the above described programming sequences this is the first action for every type of calculation The mechanism is disabled with the final read instruction from MD3 or MD5 phase 3 Every instruction which rewrites MDO and therefore tries to start a new calculation in phases 1 through 3 of the same process sets the error flag Semiconductor Group 6 68 1997 08 01 SIEMENS On Chip Peripheral Components C517A The same applies for any shift operation normalize shift left right The error flag is set if the user s program reads one of the relevant registers MDO to MD3 or if it writes to MDO again before the shift operation has been completed Please note that the error flag mechanism is just an option to monitor the MDU operation If the user s program is designed such that an MDU operati
209. r a 16 bit software reload Table 6 13 lists various commonly used baud rates and shows how these baud rates can be obtained from timer 1 or from the baud rate generator Semiconductor Group 6 77 1997 08 01 SIEMENS On Chip Peripheral Components C517A Table 6 13 Commonly used Baud Rates Baud Rate fosc MHz SMOD BD Timer 1 Mode Reload Value Mode 1 3 62 5 Kbaud 12 0 1 0 2 FFH 125 Kbaud 24 0 1 0 2 FFH 19 5 Kbaud 11 059 1 0 2 FDH 9 6 Kbaud 11 059 0 0 2 FDH 4 8 Kbaud 11 059 0 0 2 FAH 2 4 Koaud 11 059 0 0 2 Fay 1 2 Kbaud 11 059 0 0 2 E8y 110 Baud 6 0 0 0 2 72H 110 Baud 12 0 0 0 1 FEEBy Baud Rate Generator Reload value 375 Kbaud 12 0 1 1 3FFH 562 5 Kbaud 18 0 1 1 3FFH 750 Kbaud 24 0 1 1 3FFH 9 6 Kbaud 12 0 1 1 3D9H 9 6 Kbaud 18 0 1 1 3C5H 9 6 Kbaud 24 0 1 1 3B2y Mode 0 1 Mbaud 12 0 z 1 5 Mbaud 18 0 2Mbaud 24 0 E Mode 2 187 5 Kbaud 12 0 375 Kbaud 12 0 281 Kbaud 18 0 562 5 Kbaud 18 0 375 Kbaud 24 0 750 Kbaud 24 0 OoO O oO 1 1 1 Semiconductor Group 6 78 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 5 2 Serial Interface 1 6 5 2 1 Operating Modes of Serial Interface 1 The serial interface 1 is an asynchronous unit only and is able to operate in two modes as an 8 bit or 9 bit UART These modes however correspond to the above mentioned modes 1 2 and 3 of serial interface 0 The m
210. range F800y FFFFy XRAM has to be disabled When additional external RAM is to be addressed in an address range lt F800y XRAM may remain enabled and there is no need to overwrite XPAGE by a second move Semiconductor Group 3 6 1997 08 01 SIEM ENS Memory Organization C517A Address Data Write to XPAGE Address l O Data MCB02113 Figure 3 3 Write Page Address to XPAGE MOV XPAGE pageaddress will write the page address only to the XPAGE register Port 2 is available for addresses or I O data Semiconductor Group 3 7 1997 08 01 SIEM ENS Memory Organization C517A Address Data Write I O Data to Port 2 gt l O Data MCB02114 Figure 3 4 Usage of Port 2 as I O Port At a write to port 2 the XRAM address in the XPAGE register will be overwritten because of the concurrent write to port 2 and XPAGE register So whenever XRAM is used and the XRAM address differs from the byte written to port 2 latch it is absolutely necessary to rewrite XPAGE with the page address Example I O data at port 2 shall be AAy A byte shall be fetched from XRAM at address F830y MOV RO 30H MOV P2 0AAH P2 shows AAH MOV XPAGE 0F8H P2 still shows AAH but XRAM is addressed MOVX A RO the contents of XRAM at F830H is moved to accumulator Semiconductor Group 3 8 1997 08 01 SIEM ENS Memory Organization C517A The register XPAGE provides the upp
211. re reset Therefore at least one power on reset has to be performed Semiconductor Group 9 8 1997 08 01 SIEMENS Power Saving Modes C517A 9 7 Hardware Power Down Reset Timing The following figures show the timing diagrams for entering figure 9 1 and leaving figure 9 2 the hardware power down mode If there is only a short signal at pin HWPD i e HWPD is sampled active only once then a complete internal reset is executed Afterwards the normal program execution starts again figure 9 3 Note Delay time caused by internal logic is not included The RESET pin overrides the hardware power down function i e if reset gets active during hardware power down it is terminated and the device performs the normal reset function Thus pin RESET has to be inactive during hardware power down mode Semiconductor Group 9 9 1997 08 01 C517A Power Saving Modes SIEMENS 1SLZ0L9N uondunsuo jewog paonpay eouenbes 1esey jeuiguu a 9jelS 160 QdMH gidwes d Id Ed dde ee e se Jede ME Me ds ds i Wood eap E GS 7S tS ZS IS 9S SS PS ES ZS IS 9S SS HS ES ZS IS 9S GS vS ES ZS IS 9S SS uoneiedo amp UJON 13S3d 294 Jojejioso Ou A0 E 9SQ SuOd jesou jeuieju QdMH Figure 9 1 Timing Diagram of Entering Hardware Power Down Mode 1997 08 01 9 10 Semiconductor Group C517A Power Saving Modes SIEMENS 8SLZOLIN euin s sil pg xew
212. reading the latch rater than the pin will return the correct value of 1 Semiconductor Group 6 13 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 2 Timers Counters The C517A contains three general purpose 16 bit timers counters timer 0 1 and 2 and the compare timer which are useful in many applications for timing and counting In timer function the timer register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 12 oscillator periods the counter rate is 1 12 of the oscillator frequency In counter function the register is incremented in response to a 1 to 0 transition falling edge at its corresponding external input pin TO or T1 alternate functions of P3 4 and P3 5 resp In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles 24 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for at least one full machine cycle 6 2 1 Timer Counter
213. rease the noise margin but is optional if Voy of the driving gate corresponds to the Vi specification of XTAL2 C517A XTAL1 External Clock EI XTAL2 Signal MCS03326 Figure 5 6 External Clock Source Semiconductor Group 5 7 1997 08 01 SIEMENS Reset System Clock C517A 5 5 System Clock Output For peripheral devices requiring a system clock the C517A provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1 6 CLKOUT If bit CLK is set bit 6 of special function register ADCONO a clock signal with 1 12 of the oscillator frequency is gated to pin P1 6 CLKOUT To use this function the port pin must be programmed to a one 1 which is also the default after reset Special Function Register ADCONO Address D8 Reset Value 00H MSB LSB Bit No DFy DEH DDy DCH DBH DAH D9H D8H D8H BD CLK ADEX BSY ADM MX2 MX1 MXO ADCONO The shaded bits are not used for clock output control Bit Function CLK Clock output enable bit When set pin P1 6 CLKOUT outputs the system clock which is 1 12 of the oscillator frequency The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states Thus the duty cycle of the clock signal is 1 6 Associated with a MOVX instruction the system clock coincides with the last state S3 in which a RD or WR signal is active A timing diagram of
214. rent Calculation Formulas Parameter Symbol Formula Active mode Toc typ 1 fosc T 3 3 Toc max 1 4 fosc 4 0 Idle mode Toc typ 0 5 fosc T 2 6 Toc max 0 7 fosc 3 6 Active mode with Icc typ 0 25 fosc T 4 95 slow down enabled Toc max 0 3 fosc 7 7 Note fosc is the oscillator frequency in MHz cc values are given in mA Semiconductor Group 10 4 1997 08 01 SIEMENS Device Specifications C517A 10 3 A D Converter Characteristics Voc 5V 10 1596 Vas 20V T 0 to 70 C T 40 to 85 C T 40to 110 C 4V lt Varer lt Voct0 1 V Vss 0 1 Vx VacND lt Vsg 0 2 V for the SAB C517A for the SAF C517A for the SAH C517A Parameter Symbol Limit Values Unit Test Condition min max Analog input voltage V Vise Vier V 1 Sample time ts 16 x fn ns Prescaler 8 8 X f Prescaler 4 2 Conversion cycle time ADCC 96 X fn ns Prescaler 8 48 X n Prescaler 4 3 Total unadjusted error Tue t2 LSB Vss 0 5V lt Vin Vcc 0 5V Internal resistance of Rig faoc 250 kQ fanc in ns 99 reference voltage source 0 25 Internal resistance of Bis ts 500 kQ fsin ns 99 analog source 0 25 ADC input capacitance Can 50 pF 9 Notes see next page Clock calculation table Clock Prescaler ADCL tADC ts tADCC Ratio 8 1 8 X tin 16 x tin 96 x tin 4 0 4xtin 8 X tin 48 x tin Further
215. rmanently connected to timer 2 All four registers are multifunctional as they additionally provide a capture or a reload capability CRC register only A general selection of the compare capture function is done in register CCEN For compare function they can be used in compare mode 0 or 1 respectively The compare mode is selected by setting or clearing bit T2CM in special function register T2CON Always two bits in register CCEN select the CRC and CC1 to CC3 register functionality which are Disable compare capture mode normal I O at the pin Capture enabled on rising edge at a pin Compare enabled pin becomes a compare output Capture enabled on a write operation into the low part register of CRC or CC1 to CC3 Special Function Register T2CON Address C81 Reset Value 00H Special Function Register CCEN Address C144 Reset Value 00H MSB LSB Bit No CFy CEy CDy CCH CBy CA4 C94 C84 C84 T2PS ISFR I2FR T2R1 T2RO T2CM T2H T110 T2CON 7 6 5 4 3 2 1 0 Cip COCAH3 COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAHO COCALO CCEN The shaded bits are not used for compare capture control Bit Function T2CM Compare mode control for CCR and CC1 to CC3 registers When T2CM is cleared compare mode 0 is selected When T2CM is set compare mode 1 is selected COCAH3S Compare capture mode for the CC register 3 Scents COCAH3 COCAL3 M
216. rnal hardware reset a watchdog timer reset or an oscillator watchdog reset The RO output signal is active low Input O Output Semiconductor Group 1 8 1997 08 01 SIEMENS Introduction C517A Table 1 1 Pin Definitions and Functions contd Symbol Pin Number 1 O Function P MQFP 100 P4 0 P4 7 64 66 O Port4 68 72 is an 8 bit quasi bidirectional I O port with internal pull up resistors Port 4 pins that have 1 s written to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 4 pins being externally pulled low will source current I i in the DC characteristics because of the internal pull up resistors Port 4 also erves as alternate compare functions The output latch corresponding to a secondary functionmust be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 4 as follows P4 0 P4 7 CMO CM7 Compare channel 0 7 PE SWD 67 Power saving mode enable Start watchdog timer A low level at this pin allows the software to enter the power saving modes idle mode slow down mode and power down mode In case the low level is also seen during reset the watchdog timer function is off on default Usage of the software controlled power saving modes is blocked when this pin is held at high level A high level during reset performs an automatic start of the watchdog t
217. rnate Function P MQFP 100 P1 0 INT3 CCO 9 Compare output capture input for CRC register P1 1 INT4 CC1 8 Compare output capture input for CC1 register P1 2 INT5 CC2 7 Compare output capture input for CC2 register P1 3 INT6 CC3 6 Compare output capture input for CC3 register P1 4 INT2 CC4 1 Compare output capture input for CC4 register P1 5 T2EX 100 Timer 2 external reload trigger input P1 7 T2 98 Timer 2 external count gate input P4 0 CMO 64 Compare output for the CMO register P4 1 CM1 65 Compare output for the CM1 register P4 2 CM2 66 Compare output for the CM2 register P4 3 CM3 68 Compare output for the CM3 register P4 4 CM4 69 Compare output for the CM4 register P4 5 CM5 70 Compare output for the CM5 register P4 6 CM6 71 Compare output for the CM6 register P4 7 CM7 72 Compare output for the CM7 register P5 0 CCMO 44 Concurrent compare 0 output P5 1 CCM1 43 Concurrent compare 1 output P5 2 CCM2 42 Concurrent compare 2 output P5 3 CCM3 41 Concurrent compare 3 output P5 4 CCM4 40 Concurrent compare 4 output P5 5 CCM5 39 Concurrent compare 5 output P5 6 CCM6 38 Concurrent compare 6 output P5 7 CCM7 37 Concurrent compare 7 output Semiconductor Group 6 24 1997 08 01 SIEMENS On Chip Peripheral Components C517A Table 6 4 Special Function Register of the CCU Symbol Description Address CCEN Compare Capture Enable Register Ciy CC4EN Compare Capture 4 Enable Register C9H CCH1 Compare Capture Register 1 High Byte C3H C
218. rol XMAPO 0 The access to XRAM is enabled XMAPO 1 The access to XRAM is disabled default after reset All MOVX accesses are performed via the external bus Further this bit is hardware protected When bit XMAP1 in SFR SYSCON is set during all accesses to XRAM RD and WR become active and port 0 and 2 drive the actual address data information which is read written from to XRAM This feature allows to check externally the internal data transfers to the XRAM When port 0 and 2 are used for I O purposes the XMAP1 bit should not be set Otherwise the I O function of the port 0 and port 2 lines is interrupted Semiconductor Group 3 3 1997 08 01 SIEM ENS Memory Organization C517A After a reset operation bit XMAPO is reset This means that the accesses to the XRAM are generally disabled In this case all accesses using MOVX instructions within the address range of F800j to FFFF generate external data memory bus cycles When XMAPO is set the access to the XRAM is enabled and all accesses using MOVX instructions with an address in the range of F8004H to FFFFy will access internally the XRAM Bit XMAPO is hardware protected If it is reset once XRAM access enabled it cannot be set by software Only a reset operation will set the XMAPO bit again This hardware protection mechanism is done by an unsymmetric latch at the XMAPO bit A unintentional disabling of XRAM could be dangerous since indeterminate values could be r
219. rt latch will not appear at the output pin until the next phase 1 which will be at S1P1 of the next machine cycle When an instruction reads a value from a port pin e g MOV A P1 the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions Figure 6 8 illustrates this port timing It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an edge e g when used as counter input In this case an edge is detected when the sampled value differs from the value that was sampled the cycle before Therefore there must be met certain reqirements on the pulse length of signals in order to avoid signal edges not being detected The minimum time period of high and low level is one machine cycle which guarantees that this logic level is noticed by the port at least once S3 P2 P2 P1 led l Asan P1 active for 1 State driver transistor m Port Old Data X New Data MCT03327 Figure 6 8 Port Timing Semiconductor Group 6 11 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 1 4 Port Loading and Interfacing The output buffers of ports 1 to 5 can drive TTL inputs directly The maximum port load which still guarantees correct logic output levels can be be looked up in the DC characteristics in the Data Sheet of the C517A or in chapter 10 of this User s Manual The corresponding parameters are Vo and Von
220. s C517A Table 6 6 Configurations for Concurrent Compare Mode and Compare Mode 2 at Port 5 COCAH4 COCAL4 COCOEN1 COCOENDO Function of CC4 Function of Compare Modes at P5 0 0 0 0 Compare Capture Disabled 1 disabled Compare mode 2 selected but only interrupt generation ICR ICS no output signals at P5 1 1 Compare Mode 2 selected at P5 0 1 0 0 Capture on falling Disabled 1 rising edge at pin Compare mode 2 P1 4 INT2 CC4 selected but only interrupt generation ICR ICS no output signals at P5 1 0 0 0 Compare enable at Disabled 1 CC4 mode 0 1 is Compare mode 2 selected by COMO selected but only interrupt generation ICR ICS no output signals at P5 0 1 Compare mode 1 en Concurrent compare abled at CC4 COMO mode 1 selected at is automatically set P5 1 Compare mode 2 selected at P5 1 1 0 0 Capture on write Disabled operation into register CCL4 Compare mode 2 selected but only interrupt generation ICR ICS no output signals at P5 Note All other combinations of the 4 mode select bits are reserved and must not be used Semiconductor Group 6 50 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 4 4 Compare Function of Registers CMO to CM7 The CCU of the C517A contains another set of eight compare registers and an additional timer the compare timer and some control SFRs These compare registers
221. s 6 9 6 1 3 POM MIG Ls did eise diede AL eed Gk MALI te Se Tote Pant ces eA he ale 6 11 6 1 4 Port Loading and Interfacing asses o et e cina e RE oc e ele Se RN eet d 6 12 6 1 5 Read Modify Write Feature of Ports Oto 6 0 cee ee 6 13 6 2 Titmers COUllBIS sues oycra vh RE EERSAEERUES RA CU CE RA Sd ee AC ae dt 6 14 6 2 1 Timer Counter oand T eus it oom re o a e xU a d EC ER act Dae tas 6 14 6 2 1 1 Timer Counter 0 and 1 Registers 00 0c eects 6 15 6 2 1 2 WIG D Cice re pected ante i Du udo ops vao Dar Sod avo ote a iU ut eia e enr 6 18 6 2 1 3 MIOUB T ome n sd isnt Eae tl srt iih ce End cian oM 6 19 6 2 1 4 WAS dd gets he ado vetita Sr o watdrdpa Ee iuit Dre Dude dde nk ton eot 6 20 6 2 1 5 Mode TT TT TT IE 6 21 6 3 The Compare Capture Unit CCU 0 0 ccc ee 6 22 6 3 1 Timer2 Operation vias oi va erase eee oe OES eee e ee Sees DN SS 6 26 6 3 1 1 Timer 2 Registers 253 ontanre cet escuie OU DUE yearn te mere algae i ae 6 26 6 3 1 2 Timer 2 Operating Modes sirra neia eeu ERES Reb peg RE ERR Tee 6 30 6 3 1 2 1 Gated Timer Mode 21 2 B ure Bii Ca tt sov M E du ME 6 31 6 3 2 2 Event Counter Mode os RR XR ERE CK uu oe vd ee pt v o eR ees 6 31 6 3 1 2 3 HSloa3d or TIMCh2 vies esa tepate sr epPQessq ug he EPES UI e M Had ete 6 31 6 3 2 Operation of the Compare Timer 00000 eee 6 33 6 3 2 1 Compare Timer Registers 0 00 c cece eee 6 33 6 3 2 2 Operating Modes of the Compare Timers
222. s shown in figure 6 12 TLO uses the timer 0 control bits C T Gate TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When timer 0 is in mode 3 timer 1 can be turned on and off by switching it out of and into its own mode 3 or can still be used by the serial channel as a baud rate generator or in fact in any application not requiring an interrupt from timer 1 itself fos o Y Grag TL0 Interrupt c ro TFO A 8 Bits C T 1 P3 4 TO Control P3 2 INTO MCS02096 Interrupt 8 Bits Control Figure 6 12 Timer Counter 0 Mode 3 Two 8 Bit Timers Counters Semiconductor Group 6 21 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 3 The Compare Capture Unit CCU The compare capture unit is one of the C517A s most powerful peripheral units for use in all kinds of digital signal generation and event capturing like pulse generation pulse width modulation pulse width measuring etc The CCU consists of two 16 bit timer counters with automatic reload feature and an array of 13 compare or compare capture registers A set of six control registers is used for flexible adapting of the CCU to a wide variety of user s applications The CCU is the ideal peripheral unit for various automotive
223. s time the P2 SFR remains unchanged while the PO SFR has 1 s written to it Being an address data bus port 0 uses a pullup FET as shown in figure 6 3 When a 16 bit address is used port 2 uses the additional strong pullups p1 figure 6 6 to emit 1 s for the entire external memory cycle instead of the weak ones p2 and p3 used during normal port activity Addr Control Internal Pull Up Arrangement Int Bus Write to Latch MCS03228 Figure 6 5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses port 0 can be used for I O functions Semiconductor Group 6 7 1997 08 01 SIEMENS On Chip Peripheral Components C517A Control e 1 MUX 1 State Input Data Read Pin MCS03229 Figure 6 6 Port 2 Pull up Arrangement Port 2 in I O function works similar to the standard port driver circuitry next section whereas in address output function it works similar to Port O circuitry Semiconductor Group 6 8 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 1 2 4 Detailed Output Driver Circuitry In fact the pullups mentioned before and included in figure 6 2 6 4 and 6 5 are pullup arrangements Figure 6 7 shows the detailed output driver pullup arrangement circuit of the the port 1 and 3 to 6 port lines The basic circuitry of these por
224. s to all versions within this specification unless otherwise noted Figure 1 1 shows the different functional units of the C517A and figure 1 2 shows the simplified logic symbol of the C517A Oscillator Watchdog XRAM RAM Port 0 Watchdog Timer 2K x8 256 x 8 C E CPU ompare Timer T2 mI Datapointer MDU e 2 10 ras ROM ras Converter 32k x 8 8 Bit 8 Bit USABT UART Port8 Port7 Porte Port5 Port4 Analog Analog I O VO Digital Digital Input Input MCA03317 o 5 Ke e ae e e 2 5 92 c L Es 5 Lu 2 lt e c O Figure 1 1 C517A Functional Units Semiconductor Group 1 1 1997 08 01 SIEMENS Introduction C517A Listed below is a summary of the main features of the C517A e Full upward compatibility with SAB 80C517A 83C517A 5 Upto 24 MHz external operating frequency 500 ns instruction cycle at 24 MHz operation e Superset of the 8051 archoitecture with 8 datapointers e 32K byte on chip ROM with optional ROM protection alternatively up to 64K byte external program memory Upto 64K byte external data memory e 256 byte on chip RAM e 2K byte on chip RAM XRAM e Seven 8 bit parallel I O ports Two input ports for analog digital input Two full duplex serial interfaces USART 4 operating modes fixed or variabie baud rates programmable baud rate generators Four 16 bit timer counters Timer 0 1 C501 compatible Timer 2 for 16 bit reload
225. s to be reloaded into TLx each time it overflows 1 1 Timer O TLO is an 8 bit timer counter controlled by the standard timer 0 control bits THO is an 8 bit timer only controlled by timer 1 control bits Timer 1 Timer counter 1 stops Semiconductor Group 6 17 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 2 1 2 Mode 0 Putting either timer counter 0 1 into mode 0 configures it as an 8 bit timer counter with a divide by 32 prescaler Figure 6 9 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1 s to all O s it sets the timer overflow flag TFO The overflow flag TFO then can be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 setting Gate 1 allows the timer to be controlled by external input INTO to facilitate pulse width measurements TRO is a control bit in the special function register TCON Gate is in TMOD The 13 bit register consists of all 8 bits of THO and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 0 operation is the same for timer 0 as for timer 1 Substitute TRO TFO THO TLO and INTO for the corresponding timer 1 signals in figure 6 9 There are two different gate bits one for timer 1 TMOD 7 and one for timer 0 TMOD 3 C
226. set procedure is also performed if there is no clock available at the device This is done by the oscillator watchdog which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins The RESET signal must be active for at least two machine cycles after this time the C517A remains in its reset state as long as the signal is active When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle Then the processor starts its address output when configured for external ROM in the following state 5 phase 1 One phase later state 5 phase 2 the first falling edge at pin ALE occurs Figure 5 3 shows this timing for a configuration with EA 0 external program memory Thus between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles One Machine Cycle gt dL S3 S4 dedesbdhsba bald P1 P2 MCT01879 Figure 5 3 CPU Timing after Reset Semiconductor Group 5 5 1997 08 01 SIEMENS Reset System Clock C517A 5 4 Oscillator and Clock Circuit XTAL1 and XTAL2 are the output and input of a single stage on chip inverter which can be configured with off chip components as a Pierce oscillator The oscillator in any case drives the internal clock generator The clock generator provides the internal clock signals to the chip Thes
227. ssigned to timer 2 It has its own compare capture enable register CCAEN Register CC4 can be set to operate as any of the other CC registers see also figures 6 25 and 6 26 Its output pin is P1 4 INT2 CC4 and it has a dedicated compare mode select bit COMO located in register CCAEN In addition to the standard operation in compare mode 0 or 1 there is another feature called concurrent compare which is just an application of compare mode 1 to more than one output pin Concurrent compare means that the comparison of CC4 and timer 2 can manipulate up to nine port pins concurrently A standard compare register in compare mode 1 normally transfers a preprogrammed signal level which is stored in the shadow latch to a single output line Register CC4 however is able to put a 9 bit pattern to nine output lines The nine output lines consist of one line at port 1 P1 4 which is the standard output for register CC4 and additional eight lines at port 5 see figure 6 25 Concurrent compare is an ideal and effective option where more than one synchronous output signal is to be generated Applications including this requirement could among others be a complex multiple phase stepper motor control as well as the control of ignition coils of a car engine All these applications have in common that predefined bit patterns must be put to an output port at a precisely predefined moment This moment refers to a special count of timer 2 which was loaded to com
228. st and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations as set clear complement jump if not set jump if set and clear and move to from carry Between any addressable bit or its complement and the carry flag it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence Accumulator ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU Semiconductor Group 2 3 1997 08 01 SIEMENS Fundamental Structure C517A Special Function Register PSW Address DO Reset Value 00H Bit No MSB LSB D7y D6y D5y D44 D3y D24 Diy DOW DOH CY AC FO RS1 RSO OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic instruction AC Auxiliary Carr
229. tapointers liliis 4 6 4 5 4 Application Example and Performance Analysis 0000e eee eee 4 6 4 6 ROM Protection for the C51 7A oo eras eet RARE P bre ex REA 4 9 4 6 1 Unprotected ROM Mode itk ut een REREXELPRREODEex hp boot PUER RR X eed 4 9 4 6 2 Protected ROM Mod n sraa canoe Oe CU oben Re C ero e DRE ROC Pob de UE 4 10 5 Reset and System Clock Operation aana aana 5 1 5 1 Hardware Reset Operation 0 0 000 eet res 5 1 5 2 Fast Internal Reset after Power On 00000 cece eee eee 5 3 5 3 Hardware Reset Timing sca ua Gad had tto e OR o SO ee PES eos Vea deeds 5 5 5 4 Oscillator and Clock Circuit niue tee neus Cowes Oa de Bae oa eras 5 6 5 5 System Clock OUIDUL vx exert ERE Er tree Oh at ae 5 8 Semiconductor Group l 1 1997 08 01 SIEMENS General Information C517A Table of Contents Page 6 On Chip Peripheral Components 00000 ce eee 6 1 6 1 Parallel WO sen esa tod cR Be eee eee eee Be hha eS ee IAS Yc ees 6 1 6 1 1 POL a UIUC TSS coin leah a el aa Ghee et trae te dn Un asthe eal amet AO ied we 6 1 6 1 2 Standard O Port Circuitry ae sce bas qu tarts RE CEU EB Sea E Sak 6 3 6 1 2 1 Port OGirc itry oido coeur tate ia tecto Ds bd ebd ien ted d hid 6 5 6 1 2 2 Port T3POFU319 Port 6 GIEGUIEV a4 o ribeu weet ETSOLERSSSSSDESUSCNTIUNEIO oe 6 6 6 1 2 3 Port 2 GIFOUITEC ue atr neret ce cule pc Pc Rea tw Coe il e ate eet 6 7 6 1 2 4 Detailed Output Driver Circuitry lilii
230. ted for compare registers assigned to timer 2 It is commonly used when output signals are not related to a constant signal period as in a standard PWM generation but must be controlled very precisely with high resolution and without jitter In compare mode 1 both transitions of a signal can be controlled Compare outputs in this mode can be regarded as high speed outputs which are independent of the CPU activity If compare mode 1 is enabled and the software writes to the appropriate output latch at the port the new value will not appear at the output pin until the next compare match occurs Thus it can be choosen whether the output signal has to make a new transition 1 to 0 or 0 to 1 depending on the actual pin level or should keep its old value at the time when the timer value matches the stored compare value Figure 6 19 shows a functional diagram of a port cicuit configuration in compare mode 1 In this mode the port circuit consists of two separate latches One latch which acts as a shadow latch can be written under software control but its value will only be transferred to the port latch and thus to the port pin when a compare match occurs Port Circuit Read Latch Compare Register Circuit Compare Reg Internal Bus T L Compare i 16 Bit Match Lath Write to Timer Register Timer Circuit Read Pin MCS02662 Figure 6 19 Compare Function of Compare Mode 1 Note th
231. tent is greater than 7FFFy When the CPU is executing out of external program memory all 8 bits of port 2 are dedicated to an output function and must not be used for general purpose I O The content of the port 2 SFR however is not affected During external program memory fetches port 2 lines output the high byte of the PC and during accesses to external data memory they output either DPH or the port 2 SFR depending on whether the external data memory access is a MOVX DPTR or a MOVX Ri 4 2 PSEN Program Store Enable The read strobe for external program memory fetches is PSEN It is not activated for internal program memory fetches When the CPU is accessing external program memory PSEN is activated twice every instruction cycle except during a MOVX instruction no matter whether or not the byte fetched is actually needed for the current instruction When PSEN is activated its timing is not the same as for RD A complete RD cycle including activation and deactivation of ALE and RD takes 6 oscillator periods A complete PSEN cycle including activation and deactivation of ALE and PSEN takes 3 oscillator periods The execution sequence for these two types of read cycles is shown in figure 4 1 a and b 4 3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data In the C517A the external program and data memory spaces can b
232. ter PSEN foxav 37 toc 5 ns Address to valid instr in tayiy 148 5 ferc 60 ns Address float to PSEN bagi 0 0 ns Interfacing the C517A to devices with float times up to 37 ns is permissible This limited bus contention will not cause any damage to port 0 drivers CLKOUT Characteristics Parameter Symbol Limit Values Unit 24 MHz Variable Clock Clock 1 to c 3 5 MHz to 24 MHz min max min max ALE to CLKOUT tiisn 252 7 torc 40 ns CLKOUT high time tous 43 2 torc 40 ns CLKOUT low time tsisy 377 10 tog 40 ns CLKOUT low to ALE high SLLH 2 82 faic 40 faic 40 ns Semiconductor Group 10 9 1997 08 01 SIEMENS Device Specifications C517A AC Characteristics 24 MHz cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 24 MHz Variable Clock Clock 1 tere 3 5 MHz to 24 MHz min max min max RD pulse width TUR 180 l 6144 70 l ns WR pulse width NE 180 6 fcc 70 ns Address hold after ALE fiLaX2 53 2 toc 30 ns RD to valid data in aie 118 5 facic 90 ns Data hold after RD fes 0 0 ns Data float after RD RuDZz 63 2 fcc 20 ns ALE to valid data in tiipy 200 8 toc 133 Ins Address to valid data in tav
233. terface to emulation hardware SYSCON RSYSCON SYSCON RSYSCON TCON RTCON TCON RTCON Enhanced Hooks Interface Circuit opt RPORT RPORT I O Ports 2 0 TEA TALE TPSEN y Target System Interface MCS03254 Figure 4 2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0 port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware ICE system and the C500 MCU 1 Enhanced Hooks Technology is a trademark and patent of Metalink Corporation licensed to Siemens Semiconductor Group 4 4 1997 08 01 SIEMENS External Bus Interface C517A 4 5 Eight Datapointers for Faster External Bus Access 4 5 1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16 bit pointer for indirect addressing of external devices memories peripherals latches etc Except for a 16 bit move immediate to this datapointer and an increment instruction any other pointer handling is to be handled bytewise For complex applications with peripherals located in the external data memory space e g CAN controller or extended data storage capacity this turned out to be a bottle neck for the 8051 s comm
234. ternal pullup resistors Port 1 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 1 pins being externally pulled low will source current J i in the DC characteristics because of the internal pullup resistors The port is used for the low order address byte during program verification Port 1 also contains the interrupt timer clock capture and compare pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate except when used for the compare functions The secondary functions are assigned to the port 1 pins as follows P1 0 INT3 CCO Interrupt 3 input compare 0 output capture 0 input P1 1 INT4 CC1 Interrupt 4 input compare 1 output capture 1 input P1 2 INT5 CC2 Interrupt 5 input compare 2 output capture 2 input P1 3 INT6 CC3 Interrupt 6 input compare 3 output capture 3 input P1 4 INT2 CCA Interrupt 2 input compare 4 output capture 4 input P1 5 T2EX Timer 2 external reload trigger input P1 6 CLKOUT System clock output P1 7 T2 Counter 2 input Vee 10 62 Ground 0V during normal idle and power down operation Vee 11 63 Supply voltage during normal idle and power down mode Input O Output Semiconductor Group 1 5 1997 08 01 SIEMENS Introduction
235. the device This is particularly done when the power down mode is to be terminated Additional to the hardware reset which is applied externally to the C517A there are two internal reset sources the watchdog timer and the oscillator watchdog This chapter deals only with the external hardware reset The reset input is an active low input An internal Schmitt trigger is used at the input for noise rejection Since the reset is synchronized internally the RESET pin must be held low for at least two machine cycles 24 oscillator periods while the oscillator is running With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes high again During reset pins ALE and PSEN are configured as inputs and should not be stimulated or driven externally An external stimulation at these lines during reset activates several test modes which are reserved for test purposes This in turn may cause unpredictable output operations at several port pins At the RESET pin a pullup resistor is internally connected to Vec to allow a power up reset with an external capacitor only An automatic power up reset can be obtained when Vec is applied by connecting the reset pin to Vas via a capacitor After Voc has been turned on the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset Semiconductor Group 5 1 1997 08 01 SIEMENS Reset System
236. the requested service routine will be next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions If an interrupt of equal or higer priority is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to registers IE or IP the additional wait time cannot be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles Semiconductor Group 7 19 1997 08 01 SIEMENS Fail Safe Mechanisms C517A 8 Fail Safe Mechanisms The C517A offers enhanced fail safe mechanisms which allow an automatic recovery from software upset or hardware failure a programmable watchdog timer WDT with variable time out period from 512 us up to
237. the system clock output is shown in figure 5 7 Note During slow down operation the frequency of the CLKOUT signal is divided by 8 Semiconductor Group 5 8 1997 08 01 SIEMENS Reset System Clock C517A mU NNUS CLKOUT o MCT01858 Figure 5 7 Timing Diagram System Clock Output Semiconductor Group 5 9 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 On Chip Peripheral Components This chapter gives detailed information about all on chip peripherals of the C517A except for the integrated interrupt controller which is described separately in chapter 7 6 1 Parallel I O The C517A has seven 8 bit digital I O ports and one 8 bit and one 4 bit input port for analog digital input Port 0 is an open drain bidirectional I O port while ports 1 to 6 are quasi bidirectional I O ports with internal pullup resistors That means when configured as inputs ports 1 to 6 will be pulled high and will source current when externally pulled low Port 0 will float when configured as input The output drivers of port O and 2 and the input buffers of port O are also used for accessing external memory In this application port O outputs the low byte of the external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the port 2 pins continue emitting the P2 SFR contents In this function port 0 is not an
238. timer e g to provide up to 8 PWM output channels The assignment of the CMx registers which can be done individually for every single register is combined with an automatic selection of one of the two possible compare modes Port 5 port 4 and five lines of port 1 have alternate functions dedicated to the CCU These functions are listed in table 6 3 Normally each register controls one dedicated output line at the ports Register CC4 is an exception as it can manipulate up to nine output lines one at port 1 4 and the other eight at port 5 concurrently This function is referenced as concurrent compare Note that for an alternate input function the port latch has to be programmed with a 1 For bit latches of port pins that are used as compare outputs the value to be written to the bit latches depends on the compare mode established A list of all special function registers concerned with the CCU is given in table 6 4 Semiconductor Group 6 22 1997 08 01 SIEMENS On Chip Peripheral Components C517A hi Internal Bus 16 bit Reload ve Compare Timer Prescaler Max Clock fogc 2 Compare Max Clock fog 12 16 bit Rel Capt CRC Comp Timer 2 Prescaler MCB01577 Figure 6 13 Block Diagram of the CCU Semiconductor Group 6 23 1997 08 01 SIEMENS On Chip Peripheral Components C517A Table 6 3 Alternate Port Functions of the CCU Pin Symbol Pin No Alte
239. timer period This job may take the whole current timer period since the TOC loading prevents unintentional overwriting of the actual and prepared value in the compare latch Semiconductor Group 6 52 1997 08 01 SIEMENS On Chip Peripheral Components C517A Output Compare Latch TOC Loading Control Write to CMLx Compare Register CMx MCS01865 Figure 6 27 Compare Function of a CMx Register Assigned to the Compare Timer Figure 6 27 shows a more detailed block diagram of a CMx register connected to the compare timer It illustrates that the CPU can only access the special function register CMx the actual compare latch is however loaded at timer overflow The timer overflow signal also sets an interrupt request flag CTF in register CTCON which may be used to inform the CPU by an interrupt that a new timer cycle has started and that the compare values for the next cycle may be programmed from now on The activation of the TOC loading depends on a few conditions described in the following A TOC loading is performed only if the CMLx register has been changed by the CPU A write instruction to the low byte of the CMx register is used to enable the loading The 8 bit architecture of the C517A requires such a defined enable mechanism because 16 bit values are to be transferred in two portions two instructions Imagine the following situation one instruction e g loading the low byte of the compare register is ex
240. timing conditions Semiconductor Group tADC min 500 ns tin 2 fosc 2tci cL 10 5 1997 08 01 SIEMENS Device Specifications C517A Notes 1 Vain may exeed Vacnp Or VAngr up to the absolute maximum ratings However the conversion result in these cases will be X000 or X3FFy respectively 2 During the sample time the input capacitance Cay can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach their final voltage level within ts After the end of the sample time tg changes of the analog input voltage have no effect on the conversion result g This parameter includes the sample time tg the time for determining the digital result and the time for the calibration Values for the conversion clock tapc depend on programming and can be taken from the table on the previous page 2 Tye is tested at Varner 5 0 V Vacnp 0 V Voc 4 9 V It is guaranteed by design characterization for all other voltages within the defined voltage range If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA an additional conversion error of 1 2 LSB is permissible S During the conversion the ADC s capacitance must be repeatedly charged or discharged The internal resistance of the reference source must allow the capacitance to reach their final
241. tion protected or unprotected is fixed with the ROM mask Therefore the customer of a C517A 4R version has to define whether ROM protection has to be selected or not The C517A 4R devices which operate from internal ROM are always checked for correct ROM contents during production test Therefore unprotected as well as protected ROMs must provide a procedure to verify the ROM contents In ROM verification mode 1 which is used to verify unprotected ROMs a ROM address is applied externally to the C517A 4R and the ROM data byte is output at port 0 ROM verification mode 2 which is used to verify ROM protected devices operates different ROM addresses are generated internally and the expected data bytes must be applied externally to the device by the manufacturer or by the customer and are compared internally with the data bytes from the ROM After 16 byte verify operations the state of the P3 5 pin shows whether the last 16 bytes have been verified correctly This mechanism provides a very high security of ROM protection Only the owner of the ROM code and the manufacturer who know the contents of the ROM can read out and verify it with less effort The behaviour of the move code instruction when the code is executed from the external ROM is in such a way that accessing a code byte from a protected on chip ROM address is not possible In this case the byte accessed will be invalid 4 6 1 Unprotected ROM Mode If the ROM is unprotected th
242. tion at INT2 Semiconductor Group 7 10 1997 08 01 SIEMENS Interrupt System C517A Special Function Register IRCONO Address CO Reset Value 00H MSB LSB Bit No C74 C64 C5y C4y C3y C24 C1y C04 COH EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC IRCONO Bit Function EXF2 Timer 2 external reload flag Set when a reload is caused by a negative transition on pin T2EX while EXEN2 1 If ET2 in IENO is set timer 2 interrupt enabled EXF2 1 will cause an interrupt Can be used as an additional external interrupt when the reload function is not used EXF2 must be cleared by software TF2 Timer 2 overflow flag Set by a timer 2 overflow and must be cleared by software If the timer 2 interrupt is enabled TF2 1 will cause an interrupt IEX6 External interrupt 6 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 3 INT6 CC3 Cleared by hardware when processor vectors to interrupt routine IEX5 External interrupt 5 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 2 INT5 CC2 Cleared by hardware when processor vectors to interrupt routine IEX4 External interrupt 4 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 1 INT4 CC1 Cleared by hardware when processor vectors to interrupt routine
243. tor addresses 7 17 Hardware reset 005 5 1 IPO 3 12 3 14 3 16 7 14 8 3 8 8 TESTE Pagus Bra 8 SR aie setae a 3 12 3 16 7 14 VO DONS saco deed asl eS te 6 1 to 6 13 IRCONO 3 12 3 13 3 16 6 26 6 98 7 11 l2EB re ERE REF ee 3 16 7 10 IRGONT a4 zeiten 3 12 3 17 6 61 7 12 SF Resid a etd heats eine ote er 3 16 7 10 el tence toe at Ah cela hee 3 15 7 8 IADG eee 3 16 6 98 7 11 EF etse rtr eaten Gace seid 3 15 7 8 ICMP Ds est tin ea eae doe 3 17 6 61 7 12 IGMIPN a 2a dos udi bus 3 17 6 61 7 12 ICMP2 ss 3 17 6 61 7 12 Logic symbol s vore BS Rn 1 3 ICMP3 E EO 3 17 6 61 7 12 ICMP4 3 17 6 61 7 12 MD dacteas cee ee canes Lern dent E 3 15 6 17 ICMP5 3 17 6 61 7 12 Miaa civ Re eh nebbia eds 3 15 6 17 ICMP6 3 17 6 61 7 12 MOM dae se dee obese 3 12 3 18 6 62 ICMP7 3 17 6 61 7 12 MDT cose o nK N 3 12 3 18 6 62 To MEAM 347 699 7 13 MDA risen detis dale 71 o oe 1o MEHR 347 842 743 MUSsser tes dere 3 15 9 19 6 52 eee PORNO te 3 15 9 1 ETE Oe 3 12 3 18 6 62 Idle mode 2o ob sets dE 9 2 to 9 3 MDS 1 eee n eee 3 12 3 18 6 62 n MOORE 3 15 9 1 M E 3 18 6 63 JO a oe eich cece 3 15 7 8 MDOV Ee 3 18 6 63 ERROR soa tin aaa ranle aes 3 15 7 8 Memory organization 3 1 IENO 3 12 3 14 3 16 6 26 7 5 8 3 Datamemory ette es 3 2 IEN1 3 12 3 14 3 16 6 26 6 98 7 6 8 3 G
244. tor is fosc 2 Baud Rate Generator SORELL lock Baud pet Gib 10 Bit Timer Rate Clock MCS03330 Figure 6 34 Serial Interface 0 Input Clock using the Baud Rate Generator Semiconductor Group 6 75 1997 08 01 SIEMENS On Chip Peripheral Components C517A The baud rate generator consists of a free running upward counting 10 bit timer On overflow of this timer next count step after counter value 3FF there is an automatic 10 bit reload from the registers SORELL and SORELH The lower 8 bits of the timer are reloaded from SORELL while the upper two bits are reloaded from bit 0 and 1 of register SORELH The baud rate timer is reloaded by writing to SORELL Special Function Register SORELH Address BA Reset Value XXXXXX11p Special Function Register SORELL Address AA Reset Value D9H Bit No MSB LSB 7 6 5 4 3 2 1 0 BAH _ MSB 0 SORELH 7 6 5 4 3 2 1 0 AAH 7 6 5 A id 2 A LSB SORELL Bit Function SORELH 0 1 Baudrate generator for serial interface 0 reload high value Upper two bits of the baudrate timer reload value SORELL 0 7 Baudrate generator for serial interface 0 reload low value Lower 8 bits of the baudrate timer reload value After reset SORELH and SORELL have a reload value of 3D9j4 With this reload value the baud rate generator has an overflow rate of input clock 39 With this reset value and a 12 MHz oscillato
245. ts is shown in figure 6 4 The pullup arrangement of these port lines has one n channel pulldown FET and three pullup FETs Delay 1 State Input Data Read Pin MCS03230 Figure 6 7 Driver Circuit of Ports 1 3 to 6 The pulldown FET n1 is of n channel type Itis a very strong driver transistor which is capable of sinking high currents o1 it is only activated if a 0 is programmed to the port pin A short circuit to Vc must be avoided if the transistor is turned on since the high current might destroy the FET This also means that no 0 must be programmed into the latch of a pin that is used as input The pullup FET p1 is of p channel type It is activated for one state S1 if a 0 to 1 transition is programmed to the port pin i e a 1 is programmed to the port latch which contained a O The extra pullup can drive a similar current as the pulldown FET n1 This provides a fast transition of the logic levels at the pin The pullup FET p2 is of p channel type It is always activated when a 1 is in the port latch thus providing the logic high output level This pullup FET sources a much lower current than p1 therefore the pin may also be tied to ground e g when used as input with logic low input level The pullup FET p3 is of p channel type It is only activated if the voltage at the port pin is higher than approximately 1 0 to 1 5 V This pr
246. ue 00H Special Function Register IPO Address A9j Reset Value 00H MSB LSB AFH AEQ ADy ACy AB AAY A94 ABY A84 EAL WDT Ef2 ES ET1 EX1 ETO EXO IENO BF BE BD BCy BB BAY B9y B8g B8y EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC IEN1 Bit No 7 6 5 4 3 2 1 0 A94 OWDS WDTS IPO 5 IPO 4 IPO 3 IPO 2 IPO 1 IPO O IPO The shaded bits are not used for fail save control Bit Function WDT Watchdog timer refresh flag Set to initiate a refresh of the watchdog timer Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer SWDT Watchdog timer start flag Set to activate the Watchdog Timer When directly set after setting WDT a watchdog timer refresh is performed WDTS Watchdog timer status flag Set by hardware when a watchdog Timer reset occured Can be cleared and set by software Semiconductor Group 8 3 1997 08 01 SIEMENS Fail Safe Mechanisms C517A 8 1 3 Starting the Watchdog Timer Immediately after start see next section for the start procedure the watchdog timer is initialized to the reload value programmed to WDTREL O WDTREL 6 After an external HW or HWPD reset an oscillator power on reset or a watchdog timer reset register WDTREL is cleared to 0014 WDTREL can be loaded by software at any time There are two ways to start the watchdog timer depending on the level appl
247. ultiprocessor communication feature is identical with this feature in serial interface 0 The serial interface 1 has its own interrupt request flags RI1 and Tl1 which have a dedicated interrupt vector location The baud rate clock for this interface is generated by a dedicated baud rate generator Mode A 9 bit UART variable baud rate 11 bits are transmitted through TXD1 or received through RXD1 a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 On transmission the 9th data bit TB81 in S1CON can be assigned to the value of 0 or 1 For example the parity bit P in the PSW could be moved into TB81 or a second stop bit by setting TB81 to 1 On reception the 9th data bit goes into RB81 in special function register S1CON while the stop bit is ignored In fact mode A of serial interface 1 is identical with mode 2 or 3 of serial interface 0 in all respects except the baud rate generation Mode B 8 bit UART variable baud rate 10 bits are transmitted through TXD1 or received through RXD1 a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB81 in special function register S1CON In fact mode B of serial interface 1 is identical with mode 1 of serial interface O in all respects except for the baud rate generation In both modes transmission is initiated by any instruction that uses S1BUF as a destination register Reception is initiated by the incoming st
248. unction of Compare Mode 2 When a compare match occurs with register COMSET a high level appears at the pins of port 5 when the corresponding bits in the mask register SETMSK are set When a compare match occurs with register COMCLR a low level appears at the pins of port 5 when the corresponding bits in the mask register CLRMSK are set Additionally the port 5 pins which are used for compare mode 2 can also be directly written using write instructions to SFR P5 Further the pins can also be read under program control If compare mode 2 shall be selected register CC4 must operate in compare mode 1 with the corresponding output pin P1 4 Therefore compare mode 2 is selected by enabling the compare function for register CC4 COCAH4 1 COCAL4 0 in SFR CC4EN and by programming bits COCOENO and COCOEN in SFR CC4EN Like in concurrent compare mode associated with CCA the number of port pins at P5 which serve the compare output function can be selected by bits COCONO COCONe in SFR CCAEN If a set and reset request occurs at the same time identical values in COMSET and COMCLR the set operation takes precedence It is also possible to use only the interrupts which are generated by matches in COMSET and COMCLR without affecting port 5 software compare For this interrupt only mode it is not necessary that the compare function at CC4 is selected Semiconductor Group 6 40 1997 08 01 SIEMENS On Chip Peripheral Components C517A
249. unication to the external world Especially programming in high level languages PLM51 C51 PASCAL51 requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages 4 5 2 How the eight Datapointers of the C517A are realized Simply adding more datapointers is not suitable because of the need to keep up 100 compatibility to the 8051 C501 instruction set This instruction set however allows the handling of only one single 16 bit datapointer DPTR consisting of the two 8 bit SFRs DPH and DPL To meet both of the above requirements speed up external accesses 10096 compatibility to 8051 architecture the C517A contains a set of eight 16 bit registers from which the actual datapointer can be selected This means that the user s program may keep up to eight 16 bit addresses resident in these registers but only one register at a time is selected to be the datapointer Thus the datapointer in turn is accessed or selected via indirect addressing This indirect addressing is done through a special function register called DPSEL data pointer select register All instructions of the C517A which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment Figure 4 3 illustrates the addressing mechanism a 3 bit field in register DPSEL points to the currently used DPTRx Any standard 8051 instruction e g MOVX
250. unning single A D conversion By setting bit ADM when at least one A D conversion has occured after the last reset operation By writing ADDATL with dummy data after bit ADM has been set before if no A D conversion has occured after the last reset operation When bit ADM is reset by software in continuous conversion mode the just running A D conversion is stopped after its end Semiconductor Group 6 97 1997 08 01 SIEMENS On Chip Peripheral Components C517A The A D converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCONO Special Function Register IEN1 Address B81 Special Function Register IRCONO Address COj Reset Value 00H Reset Value 00H MSB LSB Bit No BFy BE BDy BCy BB BAy B94 B8y B8 EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC IEN1 C74 C6p Coy C44 C34 C24 Cip COH COH EXF2 TF2 IEX6 IEX5 IEX4 IEX3 1EX2 IADC IRCONO The shaded bits are not used for A D converter control Bit Function EADC Enable A D converter interrupt If EADC 0 the A D converter interrupt is disabled IADC A D converter interrupt request flag Set by hardware at the end of an A D conversion Must be cleared by software Semiconductor Group 6 98 1997 08 01 SIEMENS On Chip Peripheral Components C517A 6 6 3 A D Converter Clock Selection The ADC uses two clock signals for operation the conversion
251. wn is enabled IDLE Idle mode enable bit When set starting of the idle mode is enabled Note The PDS bit which controls the software power down mode is forced to logic low whenever the external PE SWD pin is held at logic high level Changing the logic level of the PE SWD pin from high to low will irregularly terminate the software power down mode an is not permitted Semiconductor Group 9 1 1997 08 01 SIEMENS Power Saving Modes C517A 9 2 Idle Mode In the idle mode the oscillator of the C517A continues to run but the CPU is gated off from the clock signal However the interrupt system the serial port the A D converter and all timers with the exception of the watchdog timer are further provided with the clock The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The reduction of power consumption which can be achieved by this feature depends on the number of peripherals running If all timers are stopped and the A D converter and the serial interfaces are not running the maximum power reduction can be achieved This state is also the test condition for the idle mode Icc Thus the user has to take care which peripheral should continue to run and which has to be stopped during idle mode Also the state of all port pins either the pins controlled by their latches or controlled by their secondary
252. y Flag Used by instructions which execute BCD operations FO General Purpose Flag RS1 Register Bank select control bits RSO These bits are used to select one of the four register banks RS1 RSO Function 0 0 Bank 0 selected data address 001 07 0 1 Bank 1 selected data address 08 OFY 1 0 Bank 2 selected data address 101 174 1 1 Bank 3 selected data address 184 1FH OV Overflow Flag Used by arithmetic instruction F1 General Purpose Flag P Parity Flag Set cleared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity B Register The B register is used during multiply and divide and serves as both source and destination For other instructions it can be treated as another scratch pad register Stack Pointer The stack pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in the on chip RAM the stack pointer is initialized to 074 after a reset This causes the stack to begin a location 084 above register bank zero The SP can be read or written under software control Semiconductor Group 2 4 1997 08 01 SIEMENS Fundamental Structure C517A 2 2 CPU Timing A machine cycle of the C517A consists of 6 states 12 oscillator periods Each state is d
253. y hardware if IT1 0 IT1 External interrupt 1 level edge trigger control flag If IT1 2 O level triggered external interrupt 1 is selected If IT1 1 negative edge triggered external interrupt 1 is selected IEO External interrupt O request flag Set by hardware Cleared by hardware when processor vectors to interrupt routine if ITO 1 or by hardware if ITO O ITO External interrupt O level edge trigger control flag If ITO O level triggered external interrupt O is selected If ITO 1 negative edge triggered external interrupt 0 is selected Semiconductor Group 7 8 1997 08 01 SIEMENS Interrupt System C517A The interrupt of the serial interface 0 is generated by the request flags RIO and TIO in SFR SOCON The two request flags of the serial interface are logically OR ed together Neither of these flags is cleared by hardware when the service routine is vectored too In fact the service routine of each interface will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt and the bit will have to be cleared by software The interrupt of the serial interface 1 is generated by the request flags RI1 and TI1 in SFR S1CON The two request flags of the serial interface are logically OR ed together Neither of these flags is cleared by hardware when the service routine is vectored too In fact the service routine of each interface will

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