Hardware Manual - RTD Embedded Technologies, Inc.
Contents
1. Table 14 P4 Pin Assignments 1 Port2 al 1 22 Port2_n 0 2 43 Port2 p 13 2 Bo il 4 23 Port2_p 2 _ 5 44 Bo il 6 3 Port2_p 3 _ 7 24 Port2_n 3 _ 8 45 GND 9 4 GND 10 25 Port2_pi4 _ 11 46 Port2_n 4 _ 12 5 Port2_p 5 _ 13 26 Port2_n 5 14 47 Port2_p 6 15 6 Port2_n 6 16 27 Bom a 17 48 Port2_n 7 _ 18 7 GND 19 28 GND 20 49 Port2_p 8 _ 21 8 Port2_n 8 _ 22 29 Port2_p 9 _ 23 50 Port2_n 9 _ 24 19 FPGA35S6 User s Manual Table 14 P4 Pin Assignments Bo ef 0 30 Port2_n 10 26 51 Port2_p 11 27 10 Port2_n 11 28 31 GND 29 52 GND 30 11 Port2_p 12 31 32 Port2_n 12 32 53 Port2_p 13 33 12 Port2_n 13 34 33 Port2_p 14 35 54 Port2_n 14 36 13 Port2_p 15 37 34 Port2_n 15 38 55 GND 39 14 GND 40 35 Port2_p 16 41 56 Port2_n 16 42 15 Port2_p 17 43 36 Port2_n 17 44 57 Port2_p 18 45 16 Port2_n 18 46 37 Port2_p 19 47 58 Port2_n 19 48 17 5V 49 38 GND 50 59 Reserved 18 Reserved 39 Reserved 60 Reserved 19 Reserved 40 Reserved 61 Reserved 20 Reserved 41 Reserved 62 Reserved 21 Reserved 42 Reserved RTD Embedded Technologies Inc www rtd com 20 Accessing the Analog World FPGA35S6 User s Manual A2. Dimensions 152mm L x 130mm W x 34mm H 5 983 L x 5 117 W x 1 339 H 5 983 152mm Figure 5 IDAN Dimensions RTD Embedded Technologies Inc www rtd com 17 FPGA35S6 User s Manual 4 3 Connectors and Jumpers P2 amp P3 Digital I O Connector Connector Part VALCONN HDB 62S Mating Connector VALCONN HDB 62P Accessing the Analog World Connectors P2 and P3 each provide 24 digital I O lines along with a 5V pin and ground pins All I O have pull up pull down resistors that are controlled by jumper options also shown in the table These signals are 5V tolerant The signal names reflect the signal names n the Xilinx UCF file with the device pin out P2 and P3 are attached to Bank 2 and 0 respectively and support any of the Spartan 6 I O Standards that use a 3 3V Vcco and no reference voltage This includes LVTTL LVCMOS33 and LVDS_33 input and output Connector P2 also provides a connection to the Xilinx JTAG programming header This connector header mates with the Xilinx OEM programming cable through an adapter cable The adapter cable is provided when purchasing the Starter Kit 1 port0_p 0 1 22 GND 2 43 portO_n 0 3 2 GND 4 23 po
3. This is the input register for the port high port2_ 16 port2_ 19 This reads the current value the WO RTD Embedded Technologies Inc www rtd com 27 FPGA35S6 User s Manual Accessing the Analog World 6 2 15 R_PORT2H_OUT Write This is the output register for the port high port2_ 16 port2_ 19 The value to be output direction must be set to output 6 2 16 R_PORT2H_DIR READ WRITE This is the direction register for port high port2_ 16 port2_ 19 Indicates the direction of each pin 0 input 1 output 6 2 17 R_DDR_RD_DATA READ Reads the data of the DDR2 SRAM at R_LDDR_ADDR location A read is performed by writing address to RIDDDR_ADDR 6 2 18 R_DDR_WR_DATA READ WRITE Writes data in registry to location RLDDR_ADDR of the DDR2 SRAM 6 2 19 R_DDR_ADDR READ WRITE Address pointer of the DDR2 SRAM RTD Embedded Technologies Inc www rtd com 28 FPGA35S6 User s Manual 6 2 20 R_DDR_STATUS READ This is a status register for the DDR2 memory interface BO Read error B1 Read overflow B2 Read empty B3 Read full B4 Write error B5 Write underrun B6 Write empty B7 Write full B 14 8 Read count B 22 16 Write count B 24 Command full B 25 Command empty B 31 Calibration done RTD Embedded Technologies Inc www rtd com 29 flit Accessing the Analog World FPGA35S6 User s Manual flit Accessing the Analog World 7 Troubleshooti
4. Handling Precautions c cccceccesesecseseesecsesesecseseeeeaesneeceansneensansaeensanseeeesensetensentees 3 2 Physical Charachertetices A 3 3 Connectors and Jumpers ENEE 3 3 1 External I O Connectors CN3 Xilinx JTAG Programming Header CNS High Speed Digital UO Connector CNA amp CN9 Digital I O Connector 3 3 2 Bus Connectors CN1 Top amp CN2 Bottom PCle Connector 3 3 3 Jumpers JP1 JP2 JP3 JP4 JP5 amp JP6 Pull up Pull down Jumper JP7 Embedded Programmer Enable JP8 User ID Jumper 3 3 1 Solder Jumpers B1 Pull up Voltage B2 Pull up Voltage 3 4 Steps for Installing AEN 4 IDAN Connections 4 1 Module Handling Precautions A 4 2 Physical Charzachertetice A 43 Connectors and Jumpers P2 amp P3 Digital I O Connector P4 High Speed Digital WO Connector 43 1 Bus Connectors CN1 Top amp CN2 Bottom PCle Connector 43 2 Jumpers JP1 JP2 JP3 JP4 JP5 amp JP6 Pull up Pull down Jumper JP7 Embedded Programmer Enable JP8 User ID Jumper 43 3 Solder Jumpers B1 Pull up Voltage B2 Pull up Voltage 44 Steps for lmstalling sic csscsesectethioasidicsdds tardies e a a a i 5 Functional Description 5 2 Configuration SEN 5 3 ET 5 4 EERRON asstesaastieecscticentieineniihiscaienediimudh ial a a ia RTD Embedded Technologies Inc www rtd com iv flit Accessing the Analog World a ee or er x a it zit et a a CO Om Om Om Om PPP RONN FPGA35S6 User s Manual 5 5 DDR2
5. SRAM 5 6 Digital I O 5 7 Embedded Digilent USB JTAG Programmer 6 Register Address Space 6 1 Identifying the Board 6 2 BARO FPGA Example Register Map 6 2 1 R_ID Read 6 2 2 R_STATUS Read 6 2 3 R_EEPROM Read Write 6 2 4 R_USER_ID Read 6 2 5 RH PORTO IN Read 6 2 6 RH PORTO OUT Write 6 2 7 H PORTO DIR Write 6 2 8 R_PORT1_IN Read 6 2 9 R_PORT1_OUT Write 6 2 10 R_PORT1_DIR Read Write 6 2 11 R_PORT2L_IN Read 6 2 12 R_PORT2L_OUT Write 6 2 13 R_PORT2L_DIR Read Write 6 2 14 R_PORT2H_IN Read 6 2 15 R_PORT2H_OUT Write 6 2 16 R_PORT2H_DIR Read Write 6 2 17 R_DDR_RD_DATA Read 6 2 18 R_DDR_WR_DATA Read Write 6 2 19 R_DDR_ADDR Read Write 6 2 20 R_DDR_STATUS Read 7 Troubleshooting 8 Additional Information 8 1 PC 104 Specifications 8 2 PCI and PCI Express Specification 9 Limited Warranty RTD Embedded Technologies Inc www rtd com lita Accessing the Analog World FPGA35S6 User s Manual Table of Figures Figute 1 Board TEE 10 Figitre 2 lee E EE 11 Figure 3 Bottom Solder Jumper Locations cesecceccessesessessesessnssesecsnsseeeesusseeessuseeeessuseseassneeseessuseneaesueeseansueeseansaeensansaseasansasentansaeessanseeensenseeeasens 12 Figure 4 Example t04 Stack EE 16 Fig re 5 IDAN D ue NEE 17 Figure 6 Example IDAN SyStemiics ccccaisaskecibistecdbastacarsdarasateactalscedsrasdiegeraasdesersaadeuctadadedersabdeactaaadedchueaieachadaded chucddaashanede
6. ol 5 44 GND 6 3 po nl 7 24 GND 8 45 po o e H 4 GND 10 25 port0_n 2 11 46 GND 12 5 port0_p 3 13 26 GND 14 47 port0_n 3 15 6 GND 16 27 port0_p 4 17 48 GND 18 7 port0_n 4 19 28 GND 20 49 port0_p 5 21 8 GND 22 29 port0_n 5 23 50 GND 24 9 oo d i 2 25 20 GND 26 51 port0_n 6 27 10 GND 28 31 port0_p 7 29 52 GND 30 11 port0_n 7 31 32 GND 32 53 port0_p 8 33 12 GND 34 33 port0_n 8 35 54 GND 36 13 port0_p 9 37 34 GND JP3 38 55 port0_n 9 39 14 GND 40 35 port0_p 10 41 56 GND 42 15 port0_n 10 43 RTD Embedded Technologies Inc www rtd com Table 13 P2 and P3 Pin Assignments 1 22 GND 2 43 port1_n 0 3 2 GND 4 23 port1_p 1 5 44 GND 6 3 por nl 7 24 GND 8 45 port1_p 2 JP4 9 4 GND 10 25 port1_n 2 11 46 GND 12 5 port1_p 3 13 26 GND 14 47 port1_n 3 15 6 GND 16 27 port1_p 4 17 48 GND 18 7 port1_n 4 19 28 GND 20 49 port1_p 5 21 8 GND 22 29 port1_n 5 23 50 GND 24 9 port1_p 6 JP5 25 30 GND 26 51 port1_n 6 27 10 GND 28 31 port1_p 7 29 52 GND 30 11 port1_n 7 31 32 GND 32 53 port1_p 8 33 12 GND 34 33 port1_n 8 35 54 GND 36 13 port1_p 9 37 34 GND JP6 38 55 port1_n 9 39 14 GND 40 35 port1_p 10 41 56 GND 42 1
7. this core in a FPGA design RTD Embedded Technologies Inc www rtd com 24 FPGA35S6 User s Manual Accessing the Analog World 5 6 Digital I O The FPGA35S6 digital I O on connectors CNA and CN9 use the circuitry shown below to level shift the input voltage from 5V to 3 3V allowing the HO on these connectors to be 5V tolerant CN4 CN9 Digital 0 5VB 3V oG Figure 8 CN4 CN9 Digital I O Circuitry 5 7 Embedded Digilent USB JTAG Programmer This FPGA board includes an embedded Digilent JTAG programming module It connects to the host through the USB connections on the PCle Bus connectors A USB hub is also provided for lane repopulation The programming module is compatible with all Xilinx tools including iMpact and ChipScope www xilinx com Itis also supported by Digilent s Adept software package www digilentinc com In order to use the embedded programmer JP7 must be installed in the 1 2 position This attaches the programmer to the JTAG chain CN3 can always be used regardless of whether or not JP1 is installed The embedded programmer has a user string of RTD followed by the serial number of the board This can be used to differentiate the programmers if there are multiple boards in the system RTD Embedded Technologies Inc www rtd com 25 FPGA35S6 User s Manual Accessing the Analog World 6 Register Address Space This is the register address space for the example FPGA t
8. tolerant high speed I O with ESD protection e Embedded Digilent USB JTAG Programmer o Allows programming from the host computer o Compatible with Xilinx tools including iMpact and ChipScope e PCI Express Bus o PCle 104 Universal Board Interfaces with Type 1 or Type 2 bus Nore population o Provides 2 5 Gbps in each direction o in band interrupts and messages o Message Signaled Interrupt MSI support RTD Embedded Technologies Inc www rtd com 7 FPGA35S6 User s Manual lea Accessing the Analog World 1 3 Ordering Information The FPGA35S6 series of FPGA boards is available in the following options Table 1 Ordering Options FPGA35S6045HR PCle 104 Spartan 6 XC6SLX45T User Programmable FPGA Module FPGA35S6100HR PCle 104 Spartan 6 XC6SLX100T User Programmable FPGA Module IDAN FPGA35S6045HR_ PCle 104 Spartan 6 XC6SLX45T User Programmable FPGA Module in IDAN enclosure IDAN FPGA35S6100HR_ PCle 104 Spartan 6 XC6SLX100T User Programmable FPGA Module in IDAN enclosure A Starter Kit is available for any of the options which includes the appropriate programming cable Contact RTD Sales for more information The FPGA35S6 is a general use FPGA module allowing you to design your own FPGA It has support for custom oscillator and larger Xilinx Spartan 6 FPGAs Please contact RTD Embedded Technologies for more information on custom FPGA35S6 products and custom FPGA designs The Intelligent Data Acquisition No
9. 5 port1_n 10 43 FPGA35S6 User s Manual 36 GND Table 13 P2 and P3 Pin Assignments 57 port0_p 11 GND 37 port0_n 11 58 GND 5V 38 GND 59 Reserved Reserved 39 Reserved 60 Reserved Reserved 40 Reserved 61 Reserved 20 Reserved 41 Reserved 62 Reserved 21 Reserved 42 Reserved P4 High Speed Digital I O Connector RTD Embedded Technologies Inc www rtd com Connector Part VALCONN HDB 62S Accessing the Analog World 36 GND 44 57 port of 45 16 GND 46 37 port ai 47 58 GND 48 17 5V 49 38 GND 50 59 Reserved 18 jtag_vref CN3 2 39 GND CN3 3 60 jtag_tms CN3 4 19 GND_TCK CN3 5 40 jtag_tck CN3 6 61 GND CN3 7 20 jtag_tdo CN3 8 41 GND CN3 9 62 jtag_tdi CN3 10 21 Reserved 42 Reserved Mating Connector VALCONN HDB 62P Connector P4 provides 40 digital I O lines along with a 5V pin and ground pins These signals are 3 3V tolerant The signal names reflect the signal names n the Xilinx UCF file with the device pin out P4 is attached to Bank 1 and supports any of the Spartan 6 I O Standards that use a 3 3V Vcco and no reference voltage This includes LVTTL LVCMOS33 input and output and LVDS_33 input LVDS output is not supported in Bank 1
10. ET TT FPGA35S6045HR FPGA35S6100HR FPGA Module e ihe User s Manual BDM 610010045 Rev D Tdr Zan ER EH ER EN EEN EH E t RTD Embedded Technologies Inc AS9100 and ISO 9001 Certified RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com wv AS9100 wv 1s0 9001 flit Accessing the Analog World Revision History RevA Initial Release Rev B Corrected pin names in Table 5 on page 13 Corrected FPGA Bank designations in CN4 amp CN9 Digital I O Connector on page 14 Added IDAN connector section Rev C Change IDAN JTAG signals from P2 to P3 in Table 13 on page 18 Rev D Updated pictures Changed JP7 to three pin Added User ID jumpers Added embedded programmer configuration flash PCI vendor and device ID Advanced Analog I O Advanced Digital I O aAlO aDIO a2DI0 Autonomous SmartCal Catch the Express cpuModule dspFramework dspModule expressMate ExpressPlatform HiDANplus MIL Value for COTS prices multiPort PlatformBus and PC 104EZ are trademarks and Accessing the Analog World dataModule IDAN HiDAN RTD and the RTD logo are registered trademarks of RTD Embedded Technologies Inc formerly Real Time Devices Inc PS 2 is a trademark of International Business M
11. Y AS9100 wv so 9001 Copyright 2015 by RTD Embedded Technologies Inc All rights reserved
12. achines Inc PCI PCI Express and PCle are trademarks of PCI SIG PC 104 PC 104 Plus PCI 104 PCle 104 PCI 104 Express and 104 are trademarks of the PC 104 Embedded Consortium All other trademarks appearing in this document are the property of their respective owners Failure to follow the instructions found in this manual may result in damage to the product described in this manual or other components of the system The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment Contents and specifications within this manual are given without warranty and are subject to change without notice RTD Embedded Technologies Inc shall not be liable for errors or omissions in this manual or for any loss damage or injury in connection with the use of this manual Copyright 2015 by RTD Embedded Technologies Inc All rights reserved RTD Embedded Technologies Inc www rtd com il FPGA35S6 User s Manual Table of Contents 1 Introduction 1 1 Product EE 1 2 Gieres EE 13 Ordering Informatio EE 1 4 Contact Informati n ee eeue Ae Lee EUREN 1 4 1 Sales Support 1 4 2 Technical Support 2 Specifications 2 1 Operating Conditions ceceescecceseeseseseeseceseeeceesneecesesaeeteansaeeneansneessansaeensansneentensetententees 2 2 Electrical Characteristics cccccccssscscssssssssssscssscscscecscseeeesessesssesssssscssscscsescsvsesesnsaaeseaees 3 Board Connection 3 1 Board
13. ccessing the Analog World 4 3 1 BUS CONNECTORS ONT Top amp CN2 Bottom PCle Connector The PCle connector is the connection to the system CPU The position and pin assignments are compliant with the PC 104 Express Specification See PC 104 Specifications on page 31 The FPGA35S6 is a Universal board and can connect to either a Type 1 or Type 2 PCle 104 connector 4 3 2 JUMPERS JP1 JP2 JP3 JP4 JP5 amp JP6 Pull up Pull down Jumper JP1 JP2 JP3 JP4 JP5 and JP6 are 3 pin two position jumpers that are used to set pull up or pull downs options on the I O signal lines of CN4 and C5 Refer to Table 13 and Table 14 to determine which I O pins are effected by each jumper Table 15 Pull up Pull down Jumper options 1 2 UO is pulled up to 3 3V or 5V Set by B1 and B2 2 3 UO is pulled down to GND No Jumper VO has no pull up pull down JP7 Embedded Programmer Enable This jumper is used to enable the embedded programmer to the JTAG chain See Section 5 7 on page 25 for more details The board can be programmed from and external programmer with this jumper in either position Table 16 B1 Pull up Voltage 1 2 Enabled embedded programmer 2 30r Disables embedded programmer open JP8 User ID Jumper The User ID Jumper is a four position user defined jumper block The jumpers can be read by the FPGA An installed jumper results in a logic low and an open jumper results in a logic h
14. de IDAN building block can be used in just about any combination with other IDAN building blocks to create a simple but rugged 104 stack This module can also be incorporated in a custom built RTD HIDAN or HiDANplus High Reliability Intelligent Data Acquisition Node Contact RTD sales for more information on our high reliability systems 1 4 Contact Information 1 4 1 SALES SUPPORT For sales inquiries you can contact RTD Embedded Technologies sales via the following methods Phone 1 814 234 8087 Monday through Friday 8 00am to 5 00pm EST E Mail sales rtd com 1 4 2 TECHNICAL SUPPORT If you are having problems with you system please try the steps in the Troubleshooting section of this manual For help with this product or any other product made by RTD you can contact RTD Embedded Technologies technical support via the following methods Phone 1 814 234 8087 Monday through Friday 8 00am to 5 00pm EST E Mail techsupport rtd com RTD Embedded Technologies Inc www rtd com 8 FPGA35S6 User s Manual Accessing the Analog World 2 Specifications 2 1 Operating Conditions Table 2 Operating Conditions Vco5 5V Supply Voltage 4 75 5 25 V Moo 3 3V Supply Voltage n a n a V Vect2 12V Supply Voltage n a n a V Ta Operating Temperature 40 85 C Ts Storage Temperature 40 85 C RH Relative Humidity Non Condensing 0 90 Telcordia Issue 2 MTBF Mea
15. detunddeashadedeiahectteasnacededdeasbad 23 Figure 7 FPGA35S6 ET dl EI 24 Fig re 82 CN4 CN9 Digital EEGEN eegenen e eegene Eeer aaas CES AA aasa Aadi dee ees 25 Table of Tables Table 1 Eelere AER 8 Table 2 Operating ere e EE 9 Table 3 Electricall Characteristics x cciscescssctzacsccaesscsactentesscaecnsesccdesshacesoueesntasiasdincnsenttdesuvssaduschatasedst sshd seraceuseastastdercuseudagunssieershacefases EEE 9 Table 4 CN3 Programming Header 12 Table 5 CN8 I O Pin Aesionments A 13 Table 6 CN4 ME TEE 14 Table ee Ee NC 14 Table 8 Pull up Pull down Jumper Options cccececcecsessesecsescseesesseseesesseeceansaeeccensseessnseeecsnsseeassnseeeassnseseaseneeseasenseeeassnseseansnseeeansaseneansasensaneaeeets 14 Table 9 JP7 Embedded Programmer Enable ENEE 15 El ET RTR EE Table BI Pulllup Voltages tege eet Table 12 B2 GET el Table 13 P2 and P3 Pin Assignments Table 14 PA E e ELE Table 15 Pull up Pull down Jumper Options ENEE 21 Table 16 B1 Pull up Voltage ANEN 21 Tabled Ee ID lu EE 21 HEI EA AR Pulliup el 21 Fable 19 B2 Pullll up OltAG EE 22 Table 20 Identifying the FPGA35S6 AA 26 Table 21 FPGA Example Register Map NENNEN 26 flit Accessing the Analog World RTD Embedded Technologies Inc www rtd com vi FPGA35S6 User s Manual flit Accessing the Analog World 1 Introduction 1 1 Product Overview The FPGA35S6 series of FPGA boards are designed to provide platfo
16. do not touch the components or connectors Handle the board in an antistatic environment and use a grounded workbench for testing and handling of your hardware 3 2 Physical Characteristics e Weight Approximately 63 5 g 0 14 Ibs e Dimensions 90 17 mm L x 95 89 mm W 3 550 in L x 3 775 in W LL LOL GU ULT iriririr FPGA35800 Mn RTD Embedded Technologies Inc EH II J joa A HIN zs DHIUDNL zs DI HIN D Figure 1 Board Dimensions RTD Embedded Technologies Inc www rtd com 10 FPGA35S6 User s Manual 3 3 Connectors and Jumpers JP7 Embedded Programmer Enable ba CN9 Digital VO Ha 2 JP4 JP5 amp JP6 Pull up Pull down e beet mg _ _ a SE emm La f A RTD Embedded Technologies Inc www rtd com Accessing the Analog World CN High Speed Digital I O CNA Digital I O RTD Embedded Technologies Inc D JP1 JP2 amp JP3 Pull up Pull down UNO CN3 eo Programming Header JP8 User ID CN1 A CN2 PCle Connector Jumper Figure 2 Board Connections 11 FPGA35S6 User s Manual Accessing the Analog World TIM SA M39A 0 B2 B1 Figure 3 Bottom Solder Jumper Locations 3 3 1 EXTERNAL I O CONNECTORS CN3 Xilinx JTAG Programming Header Connector CN3 provides a connection to the Xilinx JTAG programming header The pin assignment for CN3 is shown below This connector header mates
17. gister shows the status of the User ID Jumpers BO User ID 0 Jumper 0 Open 1 Closed B1 User ID 1 Jumper 0 Open 1 Closed B2 User ID 2 Jumper 0 Open 1 Closed B3 User ID 3 Jumper 0 Open 1 Closed 6 2 5 R_PORTO_IN READ This is the input register for the pont This reads the current value the 1 0 6 2 6 R_PORTO_OUT WRITE This is the output register for the port The value to be output direction must be set to output 6 2 7 R_PORTO_DIR WRITE This is the direction register for port Indicates the direction of each pin 0 input 1 output 6 2 8 R_PORT1_IN READ This is the input register for the port1 This reads the current value the I O 6 2 9 R_PORT1_OUT WRITE This is the output register for the port1 The value to be output direction must be set to output 6 2 10 R_PORT1_DIR READ WRITE This is the direction register for port1 Indicates the direction of each pin 0 input 1 output 6 2 11 R_PORT2L_IN READ This is the input register for the port low port2_ 0 port2_ 15 This reads the current value the I O 6 2 12 R_PORT2L_OUT WRITE This is the output register for the port low port2_ 0 port2_ 15 The value to be output direction must be set to output 6 2 13 R_PORT2L_DIR READ WRITE This is the direction register for port2 low port2_ 0 port2_ 15 Indicates the direction of each pin 0 input 1 output 6 2 14 R_PORT2H_IN READ
18. hat is given with the FPGA35S6 6 1 Identifying the Board The FPGA35S6 Example shows up in standard PCI Configuration space as a PCI device It can be positively identified as shown in the Table below Table 20 Identifying the FPGA35S6 0x00 Vendor ID 0x1435 0x02 Device ID 0x5800 6 2 BARO FPGA Example Register Map Table 21 FPGA Example Register Map 0x00 R_ID 0x04 R_STATUS 0x08 R_EEPROM 0x0C R_USER_ID 0x10 R_PORTO_IN 0x14 R_PORTO_OUT 0x18 R_PORTO_DIR 0x20 R_PORT1_IN 0x24 R_PORT1_OUT 0x28 R_PORT1_DIR 0x30 R_PORT2L_IN 0x34 R_PORT2L_OUT 0x38 R_PORT2L_DIR 0x40 R_PORT2H_IN 0x44 R_PORT2H_OUT 0x48 R_PORT2H_DIR 0x50 R_DDR_RD_DATA 0x54 R_DDR_WR_DATA 0x58 R_DDR_ADDR 0x5C R_DDR_STATUS 0x60 R_CLK_27_1 0x64 R_CLK_27_2 6 2 1 R_ID READ This is a register that identifies the board 0x12345678 is the identification of the example code 6 2 2 R_STATUS READ This is a status register for power good pgood for the power supplies and serial out from the EEPROM B0 EEPROM Serial out B4 1 2V pgood RTD Embedded Technologies Inc www rtd com 26 FPGA35S6 User s Manual Accessing the Analog World B5 1 8V pgood B6 3 3V pgood 6 2 3 R_EEPROM READ WRITE This register has the outputs to the EEPROM BO EEPROM Serial Clock B1 EEPROM Serial Input B2 EEPROM Chip Select 6 2 4 R_USER_ID READ This re
19. igh Table 17 JP8 User ID Jumper 1 2 User ID bit 0 3 4 User ID bit 1 5 6 User ID bit 2 7 8 User ID bit 3 4 3 3 SOLDER JUMPERS B1 Pull up Voltage Solder jumper B1 are used to set the pull up voltage for JP1 JP2 and JP3 Table 18 B1 Pull up Voltage 1 2 Sets Pull up voltage to 3 3V 2 3 Sets Pull up voltage to 5V RTD Embedded Technologies Inc www rtd com 21 FPGA35S6 User s Manual B2 Pull up Voltage Solder jumper B1 are used to set the pull up voltage for JP4 JP5 and JP6 1 2 Table 19 B2 Pull up Voltage Sets Pull up voltage to 3 3V 2 3 Sets Pull up voltage to 5V RTD Embedded Technologies Inc www rtd com 22 Accessing the Analog World FPGA35S6 User s Manual Accessing the Analog World 44 Steps for Installing Always work at an ESD protected workstation and wear a grounded wrist strap Turn off power to the IDAN system Remove the module from its anti static bag Check that pins of the bus connector are properly positioned Check the stacking order make sure all of the busses used by the peripheral cards are connected to the cpuModule Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack Gently and evenly press the module onto the IDAN system If any boards are to be stacked above this module install them Finish assembling the IDAN stack by install
20. ing screws of an appropriate length Attach any necessary cables to the IDAN system Re connect the power cord and apply power to the stack Boot the system and verify that all of the hardware is working properly SO S 4 a En o Ne a a 3 i ba cz Figure 6 Example IDAN System RTD Embedded Technologies Inc www rtd com 23 FPGA35S6 User s Manual Accessing the Analog World 5 Functional Description 5 1 Block Diagram The Figure below shows the functional block diagram of the FPGA35S6 The various parts of the block diagram are discussed in the following sections al UO CNA and CN9 PCle x1 Figure 7 FPGA35S6 Block Diagram 5 2 Configuration Flash The FPGA35S6 includes a Configuration Flash that is sized for the FPGA At power up the FPGA design is loaded from the Configuration Flash The Configuration Flash can be programmed through either the Embedded Digilent USB JTAG Programmer or CN3 Xilinx JTAG Programming Header 5 3 Oscillator The FPGA35S6 features a 27 MHz oscillator for clock based operations in the FPGA 5 4 EEPROM The FPGA35S6 features a 256 x 16 SPI EEPROM ATMEL AT93C66A For information on the AT93C66A refer to http www atmel com 5 5 DDR2 SRAM The FPGA35S6 features a 1Gb DDR2 SRAM MT47H64M16HR 25E This is interface to the Spartan 6 FPGA using Xilinx Memory Interface Generators MIG core The example FPGA code has demonstrated how to use
21. ll implied warranties including implied warranties for merchantability and fitness for a particular purpose are limited to the duration of this warranty In the event the product is not free from defects as warranted above the purchaser s sole remedy shall be repair or replacement as provided above Under no circumstances will RTD Embedded Technologies be liable to the purchaser or any user for any damages including any incidental or consequential damages expenses lost profits lost savings or other damages arising out of the use or inability to use the product Some states do not allow the exclusion or limitation of incidental or consequential damages for consumer products and some states do not allow limitations on how long an implied warranty lasts so the above limitations or exclusions may not apply to you This warranty gives you specific legal rights and you may also have other rights which vary from state to state RTD Embedded Technologies Inc www rtd com 32 FPGA35S6 User s Manual RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Represents all cpu s P In systems capable of berg as new cpu s are detected method such as ACPI for cpumask_t cpu_present_map _ EXPORT_SYMBOL cpu_present_may ifndef CONFIG SMP Ze Represents all cpu s that cpumask_t cpu online map _ V
22. n Time Before Failure 30 C Ground benign controlled FPGA35S6045HR 2 471 464 Hours 2 2 Electrical Characteristics Table 3 Electrical Characteristics P Power Consumption Vecs 5 0V 2 5 W loo 5V Input Supply Current Active 500 mA PCle 104 Bus Differential Output Voltage 0 8 12 V DC Differential TX Impedance 80 120 Q Differential Input Voltage 0 175 12 V DC Differential RX Impedance 80 120 Q Electrical Idle Detect Threshold 65 175 mV Digital I O Vin Input High Voltage CN4 CN9 2 0 5 5 V Vin Input High Voltage CN8 2 0 3 6 V Vi Input Low Voltage CN4 CN8 CN9 0 5 0 8 V VoH Output High Voltage lo 12mA CN4 CN8 CN9 2 6 3 3 V VoL Output Low Voltage lo 12mA CN4 CN8 CN9 0 04 V 5V Output CN4 CN8 CN9 200 mA DDR2 Interface Access Rate 250 800 Mb s Note 1 Typical power consumption based on RTD s FPGA example 2 Proving by design not production tested For additionally electrical characteristic of the Spartan 6 I O refer to http www xilinx com RTD Embedded Technologies Inc www rtd com 9 FPGA35S6 User s Manual Accessing the Analog World 3 Board Connection 3 1 Board Handling Precautions To prevent damage due to Electrostatic Discharge ESD keep your board in its antistatic bag until you are ready to install it into your system When removing it from the bag hold the board at the edges and
23. ng If you are having problems with your system please try the following initial steps e Simplify the System Remove modules one at a time from your system to see if there is a specific module that is causing a problem Perform you troubleshooting with the least number of modules in the system possible e Swap Components Try replacing parts in the system one at a time with similar parts to determine if a part is faulty or if a type of part is configured incorrectly If problems persist or you have questions about configuring this product contact RTD Embedded Technologies via the following methods Phone _ 1 814 234 8087 E Mail techsupport rtd com Be sure to check the RTD web site http www rtd com frequently for product updates including newer versions of the board manual and application software RTD Embedded Technologies Inc www rtd com 30 FPGA35S6 User s Manual Accessing the Analog World 8 Additional Information 8 1 PC 104 Specifications A copy of the latest PC 104 specifications can be found on the webpage for the PC 104 Embedded Consortium www pc104 org 8 2 PCI and PCI Express Specification A copy of the latest PCI and PCI Express specifications can be found on the webpage for the PCI Special Interest Group www pcisig com RTD Embedded Technologies Inc www rtd com 31 FPGA35S6 User s Manual flit 9 Limited Warranty RTD Embedded Technologies Inc warrants the hardware and
24. om 14 FPGA35S6 User s Manual Accessing the Analog World JP7 Embedded Programmer Enable This jumper is used to enable the embedded programmer to the JTAG chain See Section 5 7 on page 25 for more details The board can be programmed from and external programmer with this jumper in either position Table 9 JP7 Embedded Programmer Enable 1 2 Enabled embedded programmer 2 3 or Disables embedded programmer open JP8 User ID Jumper The User ID Jumper is a four position user defined jumper block The jumpers can be read by the FPGA An installed jumper results in a logic low and an open jumper results in a logic high Table 10 JP8 User ID Jumper 1 2 User ID bit 0 3 4 User ID bit 1 5 6 User ID bit 2 7 8 User ID bit 3 3 3 1 SOLDER JUMPERS B1 Pull up Voltage Solder jumper B1 are used to set the pull up voltage for JP1 JP2 and JP3 Table 11 B1 Pull up Voltage 1 2 Sets Pull up voltage to 3 3V 2 3 Sets Pull up voltage to 5V B2 Pull up Voltage Solder jumper B1 are used to set the pull up voltage for JP4 JP5 and JP6 Table 12 B2 Pull up Voltage 1 2 Sets Pull up voltage to 3 3V 2 3 Sets Pull up voltage to 5V RTD Embedded Technologies Inc www rtd com 15 FPGA35S6 User s Manual Accessing the Analog World 3 4 Steps for Installing Always work at an ESD protected workstation and wear a grounded wrist strap Turn off p
25. ower to the PC 104 system or stack Select and install stand offs to properly position the module on the stack Remove the module from its anti static bag Check that pins of the bus connector are properly positioned Check the stacking order make sure all of the busses used by the peripheral cards are connected to the cpuModule Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack Gently and evenly press the module onto the PC 104 stack If any boards are to be stacked above this module install them Attach any necessary cables to the PC 104 stack Re connect the power cord and apply power to the stack Boot the system and verify that all of the hardware is working properly SO OO SE OP OT RE a oe Baek SE Figure 4 Example 104 Stack RTD Embedded Technologies Inc www rtd com 16 FPGA35S6 User s Manual Accessing the Analog World 4 IDAN Connections 4 1 Module Handling Precautions To prevent damage due to Electrostatic Discharge ESD keep your module in its antistatic bag until you are ready to install it into your system When removing it from the bag hold the module by the aluminum enclosure and do not touch the components or connectors Handle the module in an antistatic environment and use a grounded workbench for testing and handling of your hardware 4 2 Physical Characteristics e Weight Approximately 0 42 Kg 0 92 bel e
26. ptions also shown in the table These signals are 5V tolerant The signal names reflect the signal names n the Xilinx UCF file with the device pin out CNA and CN9 are attached to Bank 2 and 0 respectively and support any of the Spartan 6 I O Standards that use a 3 3V Vcco and no reference voltage This includes LVTTL LVCMOS33 and LVDS_33 input and output Table 6 CN4 I O Pin Assignments N E N p N N N p 1 D D D e N GND a d porto ni9 Te 3 3 2 Bus CONNECTORS CN1 Top amp CN2 Bottom PCle Connector Table 7 CN9 I O Pin Assignments port1_p 0 GND 5V The PCle connector is the connection to the system CPU The position and pin assignments are compliant with the PCI 104 Express Specification See PC 104 Specifications on page 31 The FPGA35S6 is a Universal board and can connect to either a Type 1 or Type 2 PCle 104 connector 3 3 3 JUMPERS JP1 JP2 JP3 JP4 JP5 amp JP6 Pull up Pull down Jumper JP1 JP2 JP3 JP4 JP5 and JP6 are 3 pin two position jumpers that are used to set pull up or pull downs options on the I O signal lines of CNA and C5 Refer to Table 6 and Table 7 to determine which I O pins are effected by each jumper Table 8 Pull up Pull down Jumper options 1 2 1 0 is pulled up to 3 3V or 5V Set by B1 and B2 2 3 1 0 is pulled down to GND No Jumper UO has no pull up pull down RTD Embedded Technologies Inc www rtd c
27. rm to create any digital I O that is required for your application It interfaces with the PCle bus and features a Xilinx Spartan 6 FPGA with a 27 MHz oscillator and 1Gb of DDR2 SDRAM There 48 5V tolerant I O and 40 3 3V tolerant high speed I O 1 2 Board Features e Xilinx Spartan 6 System level features o XC6SLX45T 2FGG484l 43 661 Logic Cells 2 489 kb of internal RAM e 116 18Kb 2088 Kb Max Block RAM e 401 kB Distributed RAM XCF16PFSG48C Configuration Flash o XC6SLX100T 2FGG4841 101 261 Logic Cells 5 800 kb of internal RAM e 268 18Kb 4 824 Kb Max Block RAM e 976 kB Distributed RAM XCF32PFSG48C Configuration Flash o RAM hierarchical memory Each block RAM has two independent ports Programmable Data Width o Integrated Endpoint block for PCI Express o Integrated Memory Controller 1 Gb of DDR2 SDRAM Supports access rates of up to 800Mb s o Dedicated carry logic for high speed arithmetic o Abundant logic resources with increased logic capacity Optional shift register or distributed RAM support Efficient 6 input LUTs LUT with dual flip flops o Four dedicated DLLs for advanced clock control Phase shift input clock by 0 90 180 270 Multiply input clock by 2 to 32 Divide input clock by 1 to 32 e Fully supported by Xilinx development system o ISE WebPACK free download from http www xilinx com o SE Design Suite e Digital I O Connectors o 485 volt tolerant I O with ESD protection o 403 3 volt
28. software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies Inc This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period RTD Embedded Technologies will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD Embedded Technologies All replaced parts and products become the property of RTD Embedded Technologies Before returning any product for repair customers are required to contact the factory for a Return Material Authorization RMA number This limited warranty does not extend to any products which have been damaged as a result of accident misuse abuse such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by RTD Embedded Technologies acts of God or other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no other warranties are expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose and RTD Embedded Technologies expressly disclaims all warranties not stated herein A
29. with the Xilinx OEM programming cable Table 4 CN3 Programming Header 3 3V VRef 2 MS CK mo MG ts RTD Embedded Technologies Inc www rtd com 12 FPGA35S6 User s Manual Accessing the Analog World CNS High Speed Digital I O Connector Connector CNS provides 40 digital I O lines along with a 5V pin and ground pins These signals are 3 3V tolerant The signal names reflect the signal names n the Xilinx UCF file with the device pin out CN8 is attached to Bank 1 and supports any of the Spartan 6 I O Standards that use a 3 3V Vcco and no reference voltage This includes LVTTL LVCMOS33 input and output and LVDS_33 input LVDS output is not supported in Bank 1 Table 5 CN8 I O Pin Assignments Port2 et Port2_p 3 OD 10 9 GND Port2_p 5 Port2 pje Port2 ei GND 20 79 cnND __ Port2_p 8 Port2_p 9 Port2_p 10 Port2_p 11 Port2_p 12 Port2_p 13 Port2_p 14 Port2_p 15 Port2_p 16 Port2_n 17 Port2_p 17 Port2_n 8 Port2_p 8 Port2_n 19 Port2_p 19 GND som v Port2_n 12 Port2_n 13 RTD Embedded Technologies Inc www rtd com 13 FPGA35S6 User s Manual CNA amp CNO Digital WO Connector Accessing the Analog World Connectors CNA and CN9 each provide 24 digital I O lines along with a 5V pin and ground pins All I O have pull up pull down resistors that are controlled by jumper o
Download Pdf Manuals
Related Search