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MPC860DB & User`s Manual - Freescale Semiconductor

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3. Mother M S60SAR Mother 007 800 Daughter Daughter Daughter amp S60SAR Daughter Pin Board Daughter Pin Board i Board Board S Board Signal Board Signal z Signal Signal N Signal N Signal N Signal Name Signal uud Name SE Name nu Name Name 9 FETHFDE FETHFDE 10 DSCK DSCK DSCK DSCK DB ONLY 11 FETHCFGI FETHCFGI 12 DSDO DSDO DSDO DSDO DB ONLY 13 FETHCFGO FETHCFGO 14 TMS TMS TMS TMS DB ONLY 15 FETHRST FETHRST 16 TRST TRST TRST TRST DB ONLY 17 BVSI BVSI BVSI BVSI 18 NMI NMI NMI NMI 19 BVS2 BVS2 BVS2 BVS2 20 IRQI IRQI IRQI IRQI 21 BBVDI BBVDI BBVDI BBVDI 22 IRQ2 IRQ2 IRQ2 IRQ2 23 BBVD2 BBVD2 BBVD2 BBVD2 24 IRQ3 IRQ3 IRQ3 IRQ3 25 RSTCNF RSTCNF RSTCNF RSTCNF 26 FRZ FRZ FRZ FRZ 2 TEXP TEXP TEXP TEXP 28 BINPAK BINPAK RxCav BINPAK 29 HRESET HRESET HRESET HRESET 30 DPO DPO DPO DPO 31 SRESET SRESET SRESET SRESET 32 DPI DPI DPI DP1 33 PORST PORST PORST PORST 34 52 DP2 DP2 DP2 35 R_PORI R_PORI R_PORI R_PORI 36 DP3 DP3 DP3 DP3 37 IRQ7 MIITCLK IRQ7 IRQ7 38 V3 3 V3 3 V3 3 TABLE 5 6 P6 Interconnect Signals MPCS860T S60SAR MPC860 S60T S60SAR 660 Mother Mother Daughter Daughter Daughter d Daughter Daughter Daughter Pin Board Pin Board Board Board Board Board Board Board Signal E e Signal A ARE Signal Signal Signal Name Signal Signal Signal Name Name Name Name Name Name
4. 13 TUE 204 INSTALLATION INSTRUCTIONS 13 CHAPTER 3 OPERATING INSTRUCTIONS 14 Tm 31 cea INTRODUCTION ES TE 3 2 CONTROLS AND INDICATORS 14 17 7777 3920 s GND e 14 RE QUAS 3 3 Indicator LD EEN 4 tin 47 36283 12 Receive Led EE RN EE 95264 1131081011 Eed LDS EG Pea a w Bayas 3 263 sqa Link Led LD4 c 14 ba ad aaa 3 26 Collision Led LD5 E 38287 010010001 0 14 EE 3 2 8 Fast Ethernet On Indicator LD An 14 Nee pusu mau 33 e MEMORY MAB aies ins E GH V eie doe d 304 MPC Registers Programming 15 CHAPTER 4 Functional Description on Eon de pea taut et ao 16 M 4e Reset amp Reset Configuration 16 Liepiai ae 411 Power On Reset qe 16 EET 4812 oe Hard RESCUE nn Gea a LO ESE 45183 pois DO RESO eT 1 02 w4 EE e 777 Ae vxo Clock EEN e Es 44 Fast Ethernet Support 7 This section is relevant for 860T only L7 TIENS 4 5
5. LD4 LDS LD6 BRIDGE JS C2 3 MOTOROLA INC U3 R2 Y1 P9 2030 MPCs Replacing U2 Before replacing the MPC the user should turn off the power When replacing U2 with another MPC it should be noticed where is the MPCs A1 pin Put the new MPC in the same direction as the old one 2e3e e MPC TOP VIEW Al MPC 10 Release 1 0 MPCS860DB User s Manual Hardware Preparation and Installation 20302 Clock Generator Replacement 41 When replacing U1 with another clock generator it should be noticed that there are 2 supply level available at U1 1 5V supply at pin 14 2 3 3V supply available at pin 11 FIGURE 2 2 U1 Power Sources 5V 3 3V From looking at FIGURE 2 2 U1 Power Sources above we see that 5V with 3 3V output only oscillator may be used with 14 pins only form factor while 3 3V oscillators may be used with 8 pins only form factor WARNING IF A 14 Pin Form Factor 3 3V Clock Generator is inserted to U1 PERMANENT DAMAGE Might Be Inflicted To The De vice WARNING Since the MPC clock input is NOT 5V TOLERANT any clock generator inserted to U1 MUST HAVE 3 3V compatible out put If a 5V output clock generator is inserted to U1
6. 111004 Hn A1SuHldi O mq HW AOXUIIIA ES 601 si 601 E LOT EOX LIIIA LOT SNH ZOX LIA Sot Sot ETHEHS38 Es EOT STH eZ TOXLIIIA EOT 50190 TOT 101 Eaiga 66 SM OUEYSIE 66 Targa E L6 18d TA3H80 E L6 THEuS 8 510 56 26 918d 1110143 Eb 6 12857 16 2163 Dud 68 or101X3 18 ee LH 101113 a Wd 58 5 ga EH 8 N35324 E 8 18 M HAHO 6L Eu wars LE VN31 3 ae m m AH N EL N zo E IL EVd j mol 8 19 XTDSAS 59 9 OIONIIA 19 NSD 3 67 L7 ee Bn GE TOXUSU Bo s T gd 62 Lt 21H13 SZ m m d Ba Bal lt LT olvd EL TiVd Ox1aur WA L gt E X1H13 T XuH13 T 77 MPCS860DB User s Manual Support Information t un o m N Ne e S 2 8 3 g GIS Z
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9. 61 TABLE 5 15 PX3 PNG Interconnect Signals Differences 61 TABLE 5 16 PX4 PM4 Interconnect Signals Differences 62 TABLE 5 17 P8 Interconnect Signals 04 TABLE 5 18 PILOT Part LISE Rane Boe ive dea E oe 70 4 Release 1 0 MPCS860DB User s Manual l1 General Information 1 1 Introduction This document is the operation guide for the MPC8XXFADS Daughter Board which can be for MPC860T MPC860SAR or MPC860 named the MPC860DB The daughter board holds The device MPC860T or MPC860SAR or the MPC860 along with some necessary logic which is required to be in the nearest vicinity of The device as well as peripherals that are dedicated to the MPC860T and are not required for any other member of the MPC8XX family The daughter board has 2 sets of matching connectors on the print side and on the component side Those on the print side connect to a matching set found on the MPC8XXFADS while those on the component side are to serve hardware expansion via a dedicated adaptor In addition a set of logic analyzer connectors is featured matching the new high density HP16500 logic analyzer adaptors this to provide fast connection to logic analyzer while saving on board s space and reducing EMI 1 2 Abbreviations List FADSC the MPC8XXFADS to which this board conn
10. SRR s 5 2 2 Lep aln I le Ix E E eee xs xx c e e bed I O CIEININININ eye ola l s IE E ta zn en A o emm eme ISIE EEE ajajaja ja fur ri FF j ja jaa Jo gt gt gt gt gt gt gt lalala IS lala Sg EISE Gs S ele E gt gt E 2 5 Gi S e ge E 6 5 g 2 KI ERE ro fe ERE ls ERGE E BE EE BEE E aae kek RERE Im flee ls llo E E E 55 5 2 ele e Inns o o SNS 3 8 SIR 8 T W U 11 11 O U QEBOLIIWN Le D D 11 EE O 1 e mun m Jos im fin o m un fre e m un Je SRR EmeEERRRIRIEREIS 8 2 S tlh INI a tz Ilo S lt BRE S BEB 222227 SE m mm Clees Sos kl WEIS BL BBS E SIS x ap m z gt gt gt lo Et fta fia HS ajala ZJB a je je E Lu ca lt x s e ee e nim zs en se Ir eo e s E ki Zle 25s d sie ISS S SSS IS RIm IR 2 2 2 2 2 2 2 2 2 lt a unugrEBIEEUvEmBLSSE B BHIBEB SISSSISSISS Sm mp QE III gt gt gt z alege x eel kd a elalelslelelalylelalelale ele SISISISISISISISWK f o8 TTL 1 1
11. 4 RES HEEE EE EEE Se SSS SSS 285 28 2 6 625 8 2 552 EEG ER 5 8 cr EA LW lt Es CO N m t un Release 1 0 Release 1 0 Support Information MPCS860DB User s Manual r I H D J J 0 2 8 0 00123002 08908 NOISNVdX3 8 Div WYH 3 7 s 8 ims OTA 8050 21090208 1330802 CR 1 1 071 EC ma E i JNI V 108010N BET E 32 SET Ee IET SET pir EL sc e EL 2 TE m m DL ET 621 EL 3 NNO3 023 0 eZ 121 on Wo GL 138521 szi 521 kam 971 Ez Ei 9 lel 2002 1 m CT x gU 7 a EOXUIIN Die m ME Z XuliW 7 6T1 TOXIN 02 Di Ld 0 1 811 e EL 11 ar E II 519 O E DOXMIH 911 e en EL 00X 11IN Due 1 a IQ OE xoxan TU eg EU BIXIN e e E Oe DH Ep ser T1 EH 4 SE Oo a xain Le 601 on E z 12 QT 80 eg EU SNIHD wx TO Ote ENN 801 201 901 e HL ETUENSIE a Q Qi im To ER susa O O 901 22 SY 01 Tor EO 97 SZ 1 199 SOAN s01 94 001 e Tago z Q 9 Bx 01 T Se E THEUSI8 OO m 1212 Su 96 S6 ZA3U80 07 6T 1 O 0 zm Isal v6 en ER OA3HEU 81 LI OQXIUW O
12. U8 LM317MDT Variable Output Voltage regulator SMD 051 LM317MD Y1 CTX093 25Mhz CRYSTAL TH 048 00099 Y2 Crystal resonator 32 768 KHz Frequency tolerance 30 ppm Drive level 10uW Max Shunt capacitance 2pF Max Load capacitance 12 5pF Max Equivalent Series Resistance 35 KQ Max SMD 048 00034 71 Release 1 0 MPCS860DB User s Manual Support Information r I H D J dom Mul see d DEE 818 WIVH SNA 6 mp 71 195 LOTTA 50 410962 0 1230082 EEN meme aH aa x axe BEB SE eager pe ale ago BE E IRIS NIP SISHI S gt Alli e gt gt gt gt gt gt gt gt gt gt gt EEE EE o gt gt EE gt a o gt EEA OF 01 0 5 RS s S RS s ISIN elle es sss le QIN SE SSIS E Ee Es les S in tn ex f o gt gt p so ez ose p s gt eo gt z s gt lf gt lanl gt zn RIZE wz We sS Fi s agama Ge a J Jos Sese Xm mum kin a Res dall Ll 8 2 f a gt lt lt lt NN ze 3 as
13. User s Manual Support Information Se e2 P9 amp U3 Fast Ethernet Connectors Relevant only for MPC860T The 860DB supports both types of connectors for fast ethernet RJ45 P9 and fiber optic tranceiver it is not mounted on the board U3 The signals of P9 are described in TABLE 5 8 P9 Interconnect Signal below TABLE 5 8 P9 Interconnect Signal Pin No Signal Name 1 TPO 2 TPO 3 TPI 4 COMMON_O 5 COMMON_O 6 TPI 7 COMMON I 8 COMMON I PMI PM4 Mother Board Connectors 3 These connectors which connect to their mates on the motherboard hence their name are 140 pin inter board mail connectors made by Molex These connectors are arranged in a quadratic shape this to provide the shortest PCB routes as possible As can be seen from their mechanical assembly shown in FIGURE 5 1 Motherboard Connectors Mechanical Assembly below the connectors are not set in a perfect symmetric shape this to prevent the possibility of daughter board s miss insertion 513 1 PMI PM4 Signal Names The Mother Board connectors signal names table compose of the motherboard signal name and the MPC relevant special name if there is a special function to this pin The special name mentioned in the same MPC column in the table For example for the MPC860SAR PB16 this pin name is also a PHREQ 0 For MPC860T SPAREA is now MIICOL One column is for the Mother board signal name to make is easy to the user t
14. V3 3 V3 3 V3 3 V3 3 138 N C N C N C N C 139 V3 3 V3 3 V3 3 V3 3 140 N C N C N C N C a Be aware that TRST is connected to GND with a zero ohm resistor 43 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 11 PM3 Interconnect Signals Daughter Pin Board Signal 860 Daughter pour OR Attri m j Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 1 ETHRX ETHRX ETHRX ETHRX 0 X Ethernet port Receive Data When the ethernet port is disabled via BCSR1 tri stated Appears also at P8 2 GND GND GND GND 3 When this signal is active LOW it enable the LXT970 device This signal connected to the TRSTE signal of the LXT970 In DTE mode when this pin is high the LXT970 isolate it self from the MII data interface In repeater mode when it is high the LXT970 tree state the MII output pins 5 ETHTX ETHTX ETHTX ETHTX LX Ethernet Port Transmit Data Appears also at P8 6 GND GND GND GND 7 8 PC9 PC9 PC9 PC9 X X MPC s 21 0 C 9 pin Appears also at P8 but otherwise unused on the FADS 9 IRDRXD IRDRXD IRDRXD IRDRXD O X InfraRed Port Receive Data When the I R port is disabled via BCSR1 tri stated Appears also at P8 10 GND GND GND GND 11 IRDTXD IRDTXD IRDTXD IRDTXD LX InfraRed Port Transmit Data Appears also at P8 12 GND GND GND
15. 0 MPCS 60DB User s Manual TABLE 1 1 860DB Specifications 7 TABLE 4 1 MFO MF4 Function Description Pins 17 TABLE 4 2 BCSR4 The control pins for the LXT970 relevant for MPC860T only 18 TABLE 5 1 ER Interconneet Signals s s nan gs ose RIA RE ER xd 20 TABLE 5 2 P2 Interconnect Signals 4 REV AS quA EE eS 20 TABLE 5 3 3 Interconnect Signals EEN 21 TABLE 5 4 P4 Interconnect Signals eR eR AA dees vase 23 TABLE 5 5 P5 Interconnect Signals 2 2 42 044 es eee x phe 23 TABLE 5 6 P6 Interconnect Signals 2 294484 c40409 24 TABLE 5 7 18 Interconnect Signals eee ee eee ee nee 25 TABLE 5 8 e P9 Interconnect Signal 12222 e cde enue tent RETE EIE 27 TABLE 5 9 PMI Interconnect Signals ge C TABLE 5 10 PM2 Interconnect Signals sees 36 TABLE 5 11 PM3 Interconnect Signals ACEN 45 TABLE 5 12 PM4 Interconnect Signals 54 TABLE 5 13 PXI PMI Interconnect Signals Differences 61 TABLE 5 14 PX2 PM2 Interconnect Signals Differences
16. 1 0 X Reserved signal 13 in BCSR3 See TABLE 4 19 BCSR3 Description on page 55 In the motherboard documentations 57 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 12 PM4 Interconnect Signals Daughter Pin Board Signal 860 Daughter M 60548 is I Daughter Daughter Attribute Description No Name Signal Name Sienal N Sienal N General ignal Name ignal Name 106 DBID4 DBID4 DBID4 DBID4 IO X Daughter Board ID Code 4 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 55 In the motherboard documentations 107 CHINS CHINS CHINS CHINS T O L Chip In Socket When this signal is active low FADS logic is noticed that the evaluated MPC8XX resides in its socket If inactive either the MPC is out of socket or a daughter board is not connected in which case the FADS becomes a debug station 108 GND GND GND GND 109 110 N C N C N C N C 111 112 GND GND GND GND 113 114 NC N C N C N C 115 116 GND GND GND GND 117 118 N C N C N C N C 119 120 GND GND GND GND 121 122 N C N C N C N C 123 124 GND GND GND GND 125 126 N C N C N C N C 127 128 GND GND GND GND 129 130 N C N C N C N C 131 58 Release 1 0 MPCS860DB User s Manual TABLE 5 12 PM
17. 1 O 11 11 11 oO in in j le m un r lala nj o un Jos un Je ft un os un r r OS iz ke in D aye B RR o o s lt lt pal E NINN m m m eo Es X8 S o N Ri m m m m m dee tn tn En S88 bal a 38888 o9 Li G i E Ok cE BEBE CERES dall 825 2525555355558 2 2 55 BBB 33 EE X Ca O lt MO co Release 1 0 Support Information MPCS860DB User s Manual Release 1 0 diu2530 HO1233NND3 08908 90 M3018 BIN WIVH DN3 el 30 5 133HS O Td Aad 5019110982 12311082 DA 1 1 1 SEL 071 SEL INI v 108010N Si cet SET ey BET gt EET TEV en EET TET TET ES SL 061 e SL NaWAQOW m UL DIS H 827 en m 12 051 SC 10 91 cag EL dO00 HU E EZI yarm E EZT gt Yem T EOXHIIW m T Z xull 071 e 611 TOXHIIW 617 JOWIIW 6 Lu W3X LITA 87 E OOXHIIW Sit Tzu Zi DS LIA 9 Sit 13XBIW Er ETIT 0268 0 GE TU
18. 16 bit data bus width See TABLE 4 10 BCSR1 Description on page 49 In the motherboard documentations 82 DRAMEN DRAMEN DRAMEN DRAMEN 0 1 Dram Enable Enables Dram to the FADS memory map See TABLE 4 10 BCSRI Description on page 49 In the motherboard documentations 83 FCFGEN FCFGEN FCFGEN FCFGEN 0 17 Flash Configuration Enable Allows for Hard Reset Configuration to be obtained from the Flash memory provided that this option is supported by the MPC See TABLE 4 10 BCSRI Description on page 49 In the motherboard documentations 55 Release 1 0 MPCS 60DB User s Manual Support Information TABLE 5 12 PM4 Interconnect Signals Pin No Daughter Board Signal Name General 660 Daughter Signal Name 860T Daughter Signal Name S60SAR Daughter Signal Name Attribute Description 84 F_EN F_EN F_EN F_EN Flash Enable Enables the Flash memory to the FADS memory map See TABLE 4 10 BCSRI Description on page 49 In the motherboard documentations 85 SDRAMEN SDRAMEN SDRAMEN SDRAMEN O H Sdram Enable Enables the Synchronous Dram to the FADS memory map See TABLE 4 10 BCSR1 Description on page 49 In the motherboard documentations 86 BCSREN BCSREN BCSREN BCSREN BCSR Enable Enables the BCSR to the FADS memory map See TABLE 4 10 BCSRI Description on page 49 In the motherboard documentations 87 FETHFDE FE
19. 5 x EU EN ne B fea y iMm zoxy 7 SR ACESS 2 z 5 wen GR AES n d DK 8 D F mud Du H SS noo 120 HCH Ze ae si isl ang Di i 4 i 1 Di bs 4T SS W 44 T Dm AMZ 0 E yn xd 30A DN cn z d Od xd 3 ME 0 xu Ae Ts ET Y S5 B Goar Ayu 4 gt 22 Kd O o a Mes N OHB T ay x 7 B3 X1 5 01134 Z pr froe LAA Fe Is 8 NID 03 7 O1VH 9 EI Mia coo Vi XV S 29 didi 2041 22111 2 ix P mg L Eu 5 aen 9 a gue xu Gt Se i us up 1 xt pag ai Mai N3 XL F K d lt 9056 1 1 oe 5 x D DECH wei E ie DND LZu EI 23 4 va 8 vd d a adgy Ae 2 ENd 90 Release 1 0 73 MPCS860DB User s Manual Support Information MI 1 H t 3 3 H DEN 0077 1300 1403 8 Hild WIVH 9N3 we 6 3 56 LOTId 9050 2109620 4 1230082 V TH SEJ ETU 135328 NOd u3M0d HP aa v wot a 4110 OND mi ESH y 8n oz US rav Int S nor tr Im N 4 7 ZA 7 JL 1 1 CEA Hu den ZE Nagy 031 KY T01 ay H I
20. 8 MPC s Address line 1 Not used on the FADS T S 138 GND GND GND GND 139 AO AO AO AO 8 MPC s Address line 0 Not used on the FADS T S 140 GND GND GND GND TABLE 5 10 PM2 Interconnect Signals Daughter Pin Board Signal S60 Daughter OIE Attri E Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute Generali ignal Name ignal Name 1 V12 V12 V12 V12 0 1017 output from voltage doubler Used to switch 5 gates on both mother and daughter boards Should not be 2 used for any other purpose 3 4 5 N C N C N C N C 6 35 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 10 PM2 Interconnect Signals Daughter Pin Board Signal 860 Daughter ned S0054R Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 7 DSDI DSDI DSDI DSDI IO DSDI TDI Debug Port Serial Data Input or JTAG port serial Data Input Used on the FADS as debug port serial data driven by the debug port controller If the ADI bundle is not connected to the FADS may be driven by external debug JTAG port controller 8 GND GND GND GND 9 10 DSCK DSCK DSCK DSCK IO DSCK TCK Debug Port Serial Clock input or JTAG port serial clock input Used on the FADS as debug port serial clock driven by the debug port controller If the ADI bundle is not connected to the FADS
21. Board Control amp Status Register BCSR 18 CHAPTER 5 Support InfOormatI n Dp 19 ee eee eer 5 1 Interconnect Signals issu t an tein 19 o 511 P1 P2 P3 P4 P5 P6 and P8 Logic Analyzer Connectors 19 CO E Selelel P1 P2 P3 P4 P5 P6 and P8 Signal Names 19 eS 512 P9 amp U3 Fast Ethernet Connectors Relevant only for MPC860T 27 Release 1 0 MPCS 60DB User s Manual chen 0 5 13 PMI PM4 Mother Board Connectors 27 Lee sou 5 103 1 PM1 PM4 Signal Names 5 104 PXI PX4 Hardware Expansion Connectors 60 Serre eT 5 15 MPC8XXFADS s 28 Serial Ports Expansion Connector 63 m 52 MPC860TFADSDB Part List 70 Release 1 0 MPCS 60DB User s Manual FIGURE 1 1 MPC860DB Block Diagram 8 FIGURE 2 1 MPC860DB Top Side Part Location diagram 10 FIGURE 2 2 U1 Power Sources toes eens eysnedcdeeh RARE EE EE 11 FIGURE 2 3 Power On Reset Source Selection 12 FIGURE 2 4 VDDL Source Selection 12 FIGURE 2 5 Keep Alive Power Source Selection 13 FIGURE 5 2 Expansion Connectors Mechanical Assembly 61 5 Release 1
22. DCH 1 0 See PM3 99 B31 LIRSYNCA PC4 PC4 PC4 1 0 See PM3 98 B32 GND GND GND GND CI VCC VCC VCC VCC C2 C3 C4 C5 C6 RS_EN2 RS_EN2 RS_EN2 RS_EN2 O L j See PM3 102 C7 GND GND GND GND C8 C9 C10 C11 C12 C13 C14 66 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 17 P8 Interconnect Signals Daughter 860 860T 860Sar Pin BoardSignal Daughter Daughter Daughter Attrib D is No Name BoardSignal BoardSignal BoardSignal ute Senn General Name Name Name 015 VD7 PD15 MIIRXD3 PD15 IO See PM3 121 UTPB 0 If the 860Sar is used with the 860Sar phy board this signal can be use for UTPB 0 in the 860Sar Phy Board C16 PD14 MIIRXD2 PD14 1 0 See PM3 120 UTPB 1 If the 860Sar is used with the 860Sar phy board this signal can be use for UTPB 1 in the 860Sar Phy Board C17 VD5 PD13 MIIRXDI PD13 I O See PM3 119 UTPB 2 If the 860Sar is used with the 860Sar phy board this signal can be use for UTPB 2 in the 860Sar Phy Board CI8 VD4 PD12 MIIMDC PD12 1 0 See PM3 118 UTPB 3 If the 860Sar is used with the 860Sar phy board this signal can be use for UTPB 3 in the 860Sar Phy Board C19 FIELD PD7 MIIRXER PD7 IO See PM3 113 UTPB 4 If the 860Sar is used with the 860Sar phy board this signal can be use for UTPB 4 in the 860Sar Phy Board C20 BLANK PD6 MIIRXDV PD6 1 0 See PM3 110 UTPB 5 If the 86
23. MPC Registers Programming on page 10 of the MPC8XXFADS User s Manual Release 1 0 MPCS860DB User s Manual Functional Description 4 Functional Description In this chapter the various modules combining the MPC860DB are described in details 4e Reset amp Reset Configuration There are 3 reset sources for the MPC 1 Power On Reset 2 Hard Reset 3 Soft Reset 4e e Power On Reset The Power On Reset on the MPC860DB is generated out of 2 alternative power buses 1 The keep alive power bus 2 The MAIN power bus Selection between the 2 options is done by means of jumper When option 1 above is selected the power on reset is generated by a dedicated voltage detector made by Seiko the S 8051HN CD X with detection voltage range of 1 795 to 2 005V During keep alive power on or when there is a voltage drop of that input into the above range Power On Reset is generated i e PORESET input of the MPC is asserted for a period of approximately 4 sec When option 2 above is selected the power on reset is generated by a dedicated voltage detector made by Seiko the S 8052ANY NH X with detection voltage range of 2 595V to 2 805V During MAIN 3 3V bus power on or when there is a voltage drop of that input into the above range Power On Reset is generated i e PORESET input of the MPC is asserted for a period of approximately 4 sec The MAIN power on reset also generates power on reset to all logic located on the motherboa
24. O MPC s Read Write indication Pulled up on the L FADS and used by FADS logic 24 VCC VCC VCC VCC 25 BCSRCS BCSRCS BCSRCS BCSRCS I O In fact CS1 of the MPC Used as chip select for the L BCSRs Pulled up When BCSR is removed from the local map may be used off board via the daughter board s expansion connectors 26 VCC VCC VCC VCC 0 SV Bus 27 GPLSA GPLSA GPLSA GPLSA X L UPMA general purpose line 5 Not used on the FADS 28 VCC VCC VCC VCC 0 SV Bus 29 BI BI BI BI I MPC s Burst Inhibit input Pulled up but otherwise 0 17 unused on the FADS 30 N C N C N C N C Not Connected Reserved 31 CS7 CS7 CS7 CS7 32 GND GND GND GND FADS Ground plane 33 CS5 CS5 CS5 CS5 MPC s Chip Select line 5 Unused on the FADS 34 GND GND GND GND 35 CEIA CEIA CEIA CEIA LL PC Card Enable 1 for PCMCIA slot A Enables the EVEN address bytes Used by on board PCMCIA port 36 GND GND GND GND 37 F CS F CS P CS F CS T O In fact MPC s chip select line 0 Used as chip select for L the Flash Simm Pulled up When the Flash is disabled via BCSR may be used off board via the daughter board s expansion connectors 38 GND GND GND GND 39 CS6 CS6 CS6 CS6 MPC s Chip Select line 6 Unused on the FADS 40 GND GND GND GND 41 CE2A CE2A CE2A CE2A LL PC Card Enable 2 for PCMCIA slot A Enables the ODD address bytes Used by on board PCMCIA port 42 GND GND GND GND 43 DRMCS2 DRMCS2 DRMCS2 DRMCS2 I O In
25. P8 Interconnect Signals Daughter 860 860T 860Sar Pin Board Signal Daughter Daughter Daughter Attrib D ge No Name BoardSignal BoardSignal BoardSignal ute SEH General Name Name Name Al ETHRX ETHRX ETHRX ETHRX 1 0 Ethernet port receive data See PM3 1 A2 ETHTX ETHTX ETHTX ETHTX 1 0 Ethernet Port transmit data See PM3 5 11 42 A3 IRDRXD IRDRXD IRDRXD IRDRXD 1 0 IrDA port receive data See PM3 9 A4 IRDTXD IRDTXD IRDTXD IRDTXD IO IrDA port transmit data See PM3 5 11 42 AS LD4 PD11 MIITXER RXENB 1 0 Also VD3 See PM3 117 A6 LD3 PD10 MIIRXDO TXENB 1 0 Also VD2 See PM3 116 A7 LD2 PD9 MIITXDO UTPCLK IO Also VD1 See PM3 115 A8 LD1 PD8 MIIRXCLK UTPB 4 1 0 Also VDO See PM3 114 A9 ETHTCK ETHTCK ETHTCK ETHTCK 1 0 Ethernet port transmit clock See PM3 27 A10 ETHRCK ETHRCK ETHRCK ETHRCK 1 0 Ethernet port receive clock See PM3 29 All PAS PAS PAS LITSYNCB 1 0 If the 860Sar is used with the 860Sar phy board this TIN2 signal can be use for LITSYNCB A12 PA4 PA4 PA4 LITCLKB 1 0 BRGCLK2 TOUT2 CLK4 PA 4 See PM3 60 TOUT2 If the 860Sar is used with the 860Sar phy board this signal can be use for LITCLKB A13 PA3 PA3 PA3 PA3 1 0 If the 860Sar is used with the 860Sar phy board this AD3 signal can be use for AD3 in the 860Sar Phy Board Al4 LIRCLKB LIRCLKB LIRCLKB LIRCLKB 1 0 See PM3 74 If the 860Sar is used with the 860Sar phy board this si
26. PAO PAO 8 LD8 MIIRXD3 UTPBO PD15 9 PAI PAI PAI PAI 10 LD7 MIIRXD2 UTPB1 PD14 11 PA2 PA2 PA2 PA2 12 LD6 MIIRXDI UTPB2 PD13 13 PA3 PA3 PA3 PA3 14 LD5 MIIMDC UTPB3 PD12 15 PA4 PA4 PA4 PA4 16 LD4 MIITXER RxEnb PD11 17 PAS PAS PAS PAS 18 LD3 MIIRXDO TxEnb PD10 19 PA6 PA6 PA6 PA6 20 LD2 MIITXDO UTPclk PD9 21 PA7 PA7 PA7 PA7 22 LD1 MIIRXCLK PD8 PD8 23 PA8 PA8 PA8 PA8 24 LDO MIIRXER UTPB4 PD7 25 PA9 PA9 PA9 PA9 26 LOE MIIRXDV UTPB5 PD6 27 PA10 PA10 PA10 PA10 28 VSYNC MIITXD3 UTPB6 PD5 29 PALL PAI PAI 1 30 HSYNC MIITXD2 UTPB7 PD4 31 IRDTXD IRDTXD IRDTXD IRDTXD 32 SHIFT_C MIITXDI SOC PD3 33 IRDRXD IRDRXD IRDRXD IRDRXD 34 SPAREI MIICRS SPAREI SPAREI 35 ETHTX ETHTX ETHTX ETHTX 36 SPARE2 MIIMDIO SPARE2 SPARE2 37 ETHRXS ETHRXS ETHRXS ETHRXS 38 SPARE3 MIITXEN SPARE3 SPARE3 TABLE 5 5 P5 Interconnect Signals Mother be dud S60SAR So Mother 1 20 A Daughter Daughter Daughter amp S60SAR Daughter Pin Board Daughter Pin Board Board Board Board Signal Board Signal 4 Signal Signal N Signal N Signal N Signal Name Signal SE Name we Name Name Name 1 N C N C N C N C 2 N C N C N C N C 3 GND GND GND GND 4 5 IRQ7 MIITCLK IRQ7 IRQ7 6 7 UUFEN UUFEN 8 DSDI DSDI DSDI DSDI DB ONLY 23 Release 1 0 Support Information MPCS 60DB User s Manual TABLE 5 5 P5 Interconnect Signals
27. PERMA NENT DAMAGE might be inflicted to the MPC 20303 Power On Reset Source Selection As there are differences between MPC revisions regarding the functionality of the Power On Reset logic it is there fore necessary to select different sources for Power ON reset generation J1 on the MPC860DB is used to select Power On Reset source when a jumper is placed between positions 1 2 of J1 Power On reset to the MPC is generated by the Keep Alive power rail I e When KAPWR goes below 2 005V Power On reset is generated When a jumper is place between position 2 3 of J1 Power On reset to the MPC is generated from the MAIN 3 3V power rail I e when the MAIN 3 3V power rail goes below 2 805V Power On reset is generated Release 1 0 MPCS860DB User s Manual Hardware Preparation and Installation FIGURE 2 3 Power On Reset Source Selection JI d d KA Power Rail MAIN Power Rail 2e3e4 VDDL Source Selection J3 serves as a selector for VDDL MPC internal logic supply When a jumper is placed between positions 1 2 of J3 VDDL is supplied with 3 3V When a jumper is placed between positions 2 3 of J3 VDDL is supplied by 2V power source The jumper on J3 is factory set between positions 1 2 to supply 3 3 to VDDL FIGURE 2 4 VDDL Source Selection J3 ab VDDL 3 3V VDDL 2V x pd 20305 Keep Alive Power Source Selection J2 selects the Keep Alive power source of the MPC When a jumpe
28. by the debug port controller as debug state indication May be configured to alternate function provided that VFLS 0 1 function as VFLS and 11 is moved to position 1 2 25 GND GND GND GND 26 RSV IRQ2 Reservation or Interrupt Request 2 Pulled up but otherwise unused on the FADS This signal used as an input pin for getting the interrupt from the PHY board when using 860SAR device and connecting the mother board to 860SAR PHY board 27 GND GND GND GND 28 29 30 AT3 AT3 AT3 AT3 IO IP_B7 PTR AT3 PCMCIA slot B Input Port 7 or Program Trace instruction fetch indication or Address Type 3 31 GND GND GND GND 32 SPARE4 SPARE4 MIICALL MPC s spare line 4 Pulled up but otherwise unused on the FADS This Signal is used in 860T only as a MIICALL signal for the Fast Ethernet 33 GND GND GND GND 34 VFLSO VFLSO VFLSO VFLSO IO IP BO TWPO VFLSO PCMCIA slot B Input Port 0 or Instruction Watchpoint 0 or Visible history Flushes Status 0 Configured as VFLSO May be configured to any alternate function Indicates in conjunction with VFLS1 the number of instructions flushed from the core s history buffer Indicates also whether the MPC is in debug mode If not using the debug port may be configured for alternate function 35 GND GND GND GND 36 SPKROUT SPKROUT SPKROUT SPKROUT I X KR IRQ4 SPKROUT Kill Reservation input or Interrupt Request 4 input or PCMCIA Speaker Output Configured on the FADS as SPKROUT May be configured to alte
29. was negligent regarding the design or manufacture of the part MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office All other prodi uct or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2000 M PC860FADSDBUM D Rev 1 1 2000
30. when the FADS is disconnected from any power supply The 860DB should be placed over the mother board connectors in a way that the mother board connectors of the 860DB PM1 PM4 match the daughter connectors of the FADS and than pressed gently into position The connectors are arranged in a non symmetrical form so miss insertion is inhibited 13 Release 1 0 MPCS860DB User s Manual OPERATING INSTRUCTIONS OPERATING INSTRUCTIONS Zei INTRODUCTION This chapter provides necessary information to use the MPC860DB 32 CONTROLS AND INDICATORS The MPC860DB has in addition to the switches a few indicators described below 3e2e GND Bridges There are 4 GND bridges on the MPC860DB They are meant to assist general measurements and logic analyzer con nection Warning The GND bridges on board physically resemble J4 Do not mistake J4 to be a GND jumper otherwise permanent damage might be inflicted to the MPC860DB and or to the MPCS8XXFADS Warning When connecting to a GND bridge use only INSULATED GND clips Failure in doing so might result in permanent damage to the MPC860DB 3e2e2 3 3V Indicator LD1 The yellow 3 317 LED LD1 indicates that the 3 3V power bus is powered from the MPC8XXFADS 3e2e3 Receive Led LD2 When the yellow LED LD2 is ON the fast ethernet receive is in process for 10M or for 100M 3e2e4 Transmit Led LD3 When the yellow LED LD3 is ON the fast ethernet transmit is in process for 1
31. 0 0S GE General 1 GND GND GND GND 2 D31 D31 D31 D31 1 0 X MPC s Data line 31 3 GND GND GND GND 4 D30 D30 D30 D30 1 0 X MPC s Data line 30 5 GND GND GND GND 6 D29 D29 D29 D29 1 0 X MPC s Data line 29 7 GND GND GND GND 8 D28 D28 D28 D28 1 0 X MPC s Data line28 9 GND GND GND GND 10 11 12 D27 D27 D27 D27 1 0 X MPC s Data line 27 13 GND GND GND GND 14 D26 D26 D26 D26 1 0 X MPC s Data line 26 15 GND GND GND GND 16 D25 D25 D25 D25 1 0 X MPC s Data line 25 17 GND GND GND GND 18 D24 D24 D24 D24 I O X MPC s Data line 24 19 GND GND GND GND 20 21 22 D23 D23 D23 D23 I O X MPC s Data line 23 23 GND GND GND GND 24 D22 D22 D22 D22 I O X MPC s Data line 22 25 GND GND GND GND 26 D21 D21 D21 D21 I O X MPC s Data line 21 27 GND GND GND GND 28 D20 D20 D20 D20 I O X MPC s Data line 20 53 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 12 PM4 Interconnect Signals Pin Poo n 860 Daughter 07 SU General 29 GND GND GND GND 30 31 32 D19 D19 D19 D19 IO X MPC s Data line 191 33 GND GND GND GND 34 D18 D18 D18 D18 IO X MPC s Data line 18 35 GND GND GND GND 36 D17 D17 D17 D17 IO X MPC s Data line 17 37 GND GND GND GND 38 D16 D16 D16 D16 IO X MPC s Data line 16 39 GND GND GND GND 40 41 42 D15 D15 D15 D15 T O X MPC s Data line 15 43 GND GND GND GND 44 D14 D14
32. 0M or for 100M 3e2e5 Link Led LD4 When the yellow LED LD4 is ON during the 100Mbps operation indicates scrambler lock and receipt of valid idle codes During 10Mbps operation indicates link valid status 3e2e6 Collision Led LD5 When the yellow LED LDS is ON in the default mode it indicates a collision However this LED is a programmable led and it can indicate other definitions For a programing options see configuration register register 19 in the LXT970 user guide 30207 Speed Led LD6 When the Speed LED LD6 is ON it indicates that the LXT970 operate in 100Mbps When this LED is off it indicates that the ethernet speed is 10M Note the 10M ethernet means 10M operating through the MII bus 30208 Fast Ethernet On Indicator LD7 When the yellow Fast Ethernet ON indicator LED LD7 is ON it designates that the LXT970 transceiver is enabled for the Fast Ethernet operation When it is off the LXT970 is tri stated and the MII pins output from the LXT970 are in three state these pins with the input to the LXT970 pins may be used for any alternate function See also TABLE 4 23 BCSR4 Description on page 57 of the MPC8XXFADS User s Manual 14 Release 1 0 15 MPCS860DB User s Manual OPERATING INSTRUCTIONS 3e3 MEMORY MAP The memory map is identical to all daughter boards therefore described in the MPC8XXFADS User s Manual section 353 MEMORY MAP on page 16 3ed MPC Registers Programming See 3 4
33. 0Sar is used with the 860Sar phy board this signal can be use for UTPB 5 in the 860Sar Phy Board C21 VCC VCC VCC VCC C22 HRESET HRESET HRESET HRESET I O L See PM2 84 C23 SRESET SRESET SRESET SRESET I O L See PM2 80 C24 N C N C N C N C Not Connected C25 VCC VCC VCC VCC C26 VDOCLK PD3 MIITXDI PD3 IO See PM3 103 SOC If the 860Sar is used with the 860Sar phy board this signal can be use for SOC in the 860Sar Phy Board C27 VPPIN VPPIN VPPIN VPPIN 1 0 12V input for PCMCIA flash programming Parallel to P7 of the MPC8XXFADS C28 C29 GND GND GND GND C30 HSYNC PD4 MIITXD2 PD4 1 0 See PM3 106 UTPB 7 If the 860Sar is used with the 860Sar phy board this signal can be use for UTPB 7 in the 860Sar Phy Board 67 Release 1 0 MPCS 60DB User s Manual Support Information TABLE 5 17 P8 Interconnect Signals Daughter 860 860T 860Sar Pin BoardSignal Daughter Daughter Daughter Attrib D is No Name BoardSignal BoardSignal BoardSignal ute SQUE General Name Name Name C31 GND GND GND GND C32 VSYNC PD5 MIITXD3 PD5 1 0 See PM3 107 UTPB 6 If the 860Sar is used with the 860Sar phy board this signal can be use for UTPB 6 in the 860Sar Phy Board 68 Release 1 0 52 MPCS860DB User s Manual Support Information MPC860TFADSDB Part List In this section the MPC860TFADSDB bill of material is listed according to th
34. 1 N C N C N C N C 2 N C N C N C N C 3 GND GND GND GND 4 N C N C N C N C 5 N C N C N C N C 6 SYSCLK SYSCLK SYSCLK SYSCLK 7 PB14 PB14 PB14 PB14 8 SYSCLK SYSCLK SYSCLK SYSCLK 9 PB15 PB15 TxCav PB15 10 PB30 PB30 PB30 PB30 11 PB16 PB16 PHREQ 0 PB16 12 PB31 PB31 PB31 PB31 13 PB17 PB17 PHREQ 1 PB17 14 PC4 PC4 PC4 PC4 15 PB18 PB18 PB18 PB18 16 PC5 PC5 PC5 PC5 24 Release 1 0 Support Information MPCS860DB User s Manual TABLE 5 6 P6 Interconnect Signals MPC860T S60SAR MPC860 860T S60SAR 860 Mother Mother Daughter Daughter Daughter Daughter Daughter Daughter Pin Board Pin Board Board Board Board Board Board Board Signal z Signal N Signal Signal Signal N Signal Signal Signal Se Name Name Name eg Name Name Name 17 E TENA E TENA E TENA E TENA 18 PC6 PC6 PC6 PC6 19 RSRXD2 RSRXD2 RSRXD2 RSRXD2 20 PC7 PC7 PC7 PC7 PHSEL 0 21 RSTXD2 RSTXD2 RSTXD2 RSTXD2 22 PC8 DCH PC8 PC8 PHSEL 1 25 RSDTR2 RSDTR2 RSDTR2 RSDTR2 24 PC9 PC9 PC9 PC9 25 RSDTRI RSDTRI RSDTRI RSDTRI 26 E RENA E RENA E RENA E RENA 2 RSRXDI RSRXDI RSRXDI RSRXDI 28 E CLSN E CLSN E CLSN E CLSN 29 RSTXDI RSTXDI RSTXD1 RSTXD1 30 PC12 PC12 PC12 PC12 31 PB26 PB26 PB26 PB26 32 BCI PC13
35. 1 O 01 A PU R BEYOLIIN 5 E N m d 2 Fe A A e A gt 1 1 11 11 11 11 11 81 181 11 11 8 9 81 8 8888 m mune je fun re e froin 35 Aaa SS RRR RRR B E Ke 2 5 5 8 UN Lees elek elei zm ale P BB ic ba Re E m hs BERE W 41219 ela m d G 8 Cieli 80 Release 1 0 HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED M otorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 480 768 2130 J APAN M otorola J apan Ltd SPS Technical Information Center 3 20 1 M inami Azabu M inato ku Tokyo 106 8573 J apan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 HOME PAGE http motorola com semiconductors MOTOROLA Information in this document is provided solely to enable system and software implementers to use Motoro There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated integrated circuits based on the information in this document a products circuits or Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its pr
36. 4 Interconnect Signals Support Information Pin me h 860 Daughter Soor NC Es Name Signal Name S Wer SC S en s RES General 132 GND GND GND GND 133 134 N C N C N C N C 135 136 GND GND GND GND 137 138 N C N C N C N C 139 140 GND GND GND GND Se ed PXI PX4 Hardware Expansion Connectors These connectors are receptacle inter board connectors made by Molex They are identical to those exist on the MPC8XXFADS mother board Their mechanical assembly is similar as well and is shown in FIGURE 5 2 Expan sion Connectors Mechanical Assembly below 59 Release 1 0 MPCS860DB User s Manual Support Information FIGURE 5 2 Expansion Connectors Mechanical Assembly PX1 E oo N en 17 1p 7 P 47 1 PX2 4 PX3 S l 4 S i c m i 1 17 09 29 79 p 93 98 In principle the expansion connectors are identical in signals assignment to the mother boards connectors However there is a difference mainly between PM3 and PX3 resulting from the difference between the various members of the 8XX family Therefore in the following tables only the differences are documented per each connector pair PM1 PXI TABLE 5 13 PX1 PM1 Interconnect Signals Differences
37. 9 00393 T MICTOR 69 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 18 PILOT Part List Reference Designation Part Description Type Part Number total P9 RJ 45 8PIN CONNECTOR TH 009 00236 1 P7 Connector Header 40 pin Dual In SMD 028 00165 1 line TSM 115 04 S DV PM1 PM2 PM3 PM4 Connector Inter board 7mm Height SMD 028 00392 4 140 pin Plug PX1 PX2 PX3 4 Connector Inter board 140 pin SMD 009 00172 4 Receptacle R15 R17 R18 R21 220 SMD 006 00301 4 R25 Faire Rite s n 274309447 SMD 024 1 R1 R2 R3 R4 R22 R23 R24 559 1 151 10 if ther is 20 9 SMD 006 00 10 R26 R42 R43 R45 Resistor 100 Q 1 1206 1 8W SMD 006 00240 1 R5 R6 R51 R52 Resistor 191 Q 1 1206 1 8W SMD 006 00344 4 R46 R55 R56 R57 R58 R63 Resistor 51 12 1 1206 1 S8W SMD 006 00221 8 R64 R65 R8 R9 R10 R59 R60 SH 75 Q 5 1206 1 SMD 006 00260 5 R27 Resistor 4 7 KQ 5 1206 1 8W SMD 006 00254 1 R7 R37 R38 R39 RAO R41 Resistor 330 Q 5 1206 1 8W SMD 006 00237 6 R11 Resistor 47 KQ 1 1206 1 8W SMD 006 00261 1 R12 Resistor 200 KO 5 1206 1 8177 SMD 006 00298 1 R13 Resistor 20 MQ 5 1206 1 8W SMD 006 00314 1 R14 R16 R19 R20 R29 Resistor 0 Q 1206 1 8W SMD 006 00252 12 R31 R32 R33 R34 R35 R48 R49 R28 R30 0 not use SMD 006 00252 2 R36 reum 124 KQ 5 SMD 1206 1 SMD 006 00299 1 R47 R50 R61 R62 Resistor 6
38. 9 8 Q 1 1206 1 8W SMD 006 00345 4 R44 Resistor 22 1KQ 1 1206 1 8W SMD 006 006 00236 1 R53 Resistor 243 Q 1 1206 1 8W SMD 006 006 00215 1 R54 Resistor 143 Q 5 1206 1 8W SMD_ 006 00300 1 70 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 18 PILOT Part List Reference Designation Part Description Type Part Number total RN1 RN2 RN3 Resistor Network 75 Q 5 8 resistors 16 pin SMD 051 00060 RN5 RN6 Resistor Network 1KQ 5 8 resistors 16 pin SMD 051 00066 RN4 Resistor Network 4 7K 5 8 resistors 14 pin SMD 051 00036 TIS MMDF3N03HD Transistor TMOS Dual 3A SMD 051 MMDF3NO3HD U1 4 MHz Clock generator 3 3V CMOS levels TH 048 00072 U1 Socket 14 pin PC Socket TH 009 00135 U2 MPC860T 19 X 19 357 pin BGA MPC860 or MPC860SAR or MPC860T TH 009 00284 U2 Socket 361 pin 19 X 19 BGA ZIF Socket TH 009 00284 U3 OPTICAL TRANCEIVER This device is not mounted on the board if the user wants to use fiber optic he should populate it TH U4 LXT970 F ETHERNET TRANCEIVER TH 051 LXT970QC US TG 223506 LAN Magnetics TH 091 TG 223506ND U6 7ALCX08D Quad Low 6 CMOS AND Gate SMD 051 74LCX08D U7 S 8051HN CD X Voltage level detector Range 1 795V to 2 005V O D output SMD 051 S 8051
39. AA MOTOROLA Motorola Semiconductor Israel Ltd ETWORKING amp COMMUNICATION SYSTEMS GROUP MPCS860DB amp MPCS860SARDB A Revision PILOT User s Manual SIX SIGMA AUTHOR HAIM AMIR MSIL 4 AD MPCS860DB User s Manual CHAPTER 1 General Information p aH MER EK 6 T RES lel 100001060101 uu Xv E 12 S Abbreviations List TRETEN 6 MER 13 Related Documentation 6 I 14 peso SPECIFICATIONS pe daa Sereda 15 IMPCS60DB site Saan E d CHAPTER 2 Hardware Preparation and Installation eere 9 7 7 2 1 s INTRODUCTION q 2 2 i24 UNPACKING INSTRUCTIONS acess aR 293 HARDWARE PREPARATION 9 eS 283281 ye MPCS Replacing UZ Gegen T E 21 MPC TOP VIEW ew 1Q TE 2 32 Clock Generator Replacement Ul 11 PECES 20303 Power On Reset Source Selection 11 T 234 VDDL Source Selection 5 ertet 0 12 Med athe aco 203 5 Keep Alive Power Source Selection 12 Tm 2 36 222 LXT970 Power Up HW Configuration
40. C007 MPCS60Sar Daughter Daughter Daughter Daughter Board Daughter Board Daughter Pin Board Board Pin Board Board Signal Board Signal Signal Board Signal R N Signal N Signal N Signal N Signal di Name SC Name Se Name Q Name 7 ALE_A ALE_A ALE_A ALE_A 8 BSOA BSOA BSOA BSOA 9 CE1A CEIA CEIA CE1A 10 BS1A BS1A BS1A BS1A 11 CE2A CE2A CE2A CE2A 12 BS2A BS2A BS2A BS2A 13 BWAITA BWAITA BWAITA BWAITA 14 BS3A BS3A BS3A BS3A 15 BB BB BB BB 16 WEO0 WEO0 WEO0 WEO0 17 BR BR BR BR 18 WEI WEI WEI WEI 19 BWP BWP BWP BWP 20 WE2 WE2 WE2 WE2 21 BCD2 BCD2 BCD2 BCD2 22 WE3 WE3 WE3 WE3 23 BCD1 BCD1 BCD1 BCD1 24 DRM_W DRM_W DRM_W DRM_W 25 BG BG BG BG 26 EDOOE EDOOE EDOOE EDOOE 27 BI BI BI BI 28 GPL2 GPL2 GPL2 GPL2 29 BRDY BRDY BRDY BRDY 30 GPL3 GPL3 GPL3 GPL3 31 BADDR28 BADDR28 BADDR28 BADDR28 32 GPL4A GPL4A GPL4A GPL4A 33 BADDR29 BADDR29 BADDR29 BADDR29 34 GPL4B GPL4B GPL4B GPL4B 35 BADDR30 BADDR30 BADDR30 BADDR30 36 GPL5A GPLSA GPLSA GPLSA 37 AS AS AS AS 38 GPLSB GPLSB GPLSB GPLSB TABLE 5 3 P3 Interconnect Signals Mother EF MPC860Sar Mother ss MPCS660Sar ARI Daughter Daughter Daughter Daughter Pin Board Daughter Board Daughter i Board Board Pin Board Board Signal Board Signal 5 Signal Board Signal N Signal N Signal N Signal N Signal Name oe Name ee Name HS Name 1 N C N C N C N C 2 N C N C N C
41. C860SAR is the TXENB pin one of the Utopia Bus Appears also at P8 117 LD4 PD11 MIITXER RXENB I O MPC860 PD11 RXD3 X MPCS860T MIITXER is one of the Fast Ethernet MII Bus Pins MPC860SAR is the RXENB pin one of the Utopia Bus Appears also at P8 118 LD5 PD12 MIIMDC UTPB3 I O MPC860 PDIZ LIRSYNCB MPC860T MIIMDC is one of the Fast Ethernet MII Bus Pins MPC860SAR is the UTPB3 pin one of the Utopia Bus Appears also at P8 Appears also at P8 50 Release 1 0 MPCS 60DB User s Manual Support Information TABLE 5 11 PM3 Interconnect Signals Daughter Pin Board Signal 860 Daughter Soor SUSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal Ni Sienal Ni bute General ignal Name ignal Name 119 LD6 PD13 MIIRXDI UTPB2 I O MPC860s PDI3 LITSYNCB X MPC860T MIIRXDI is one of the Fast Ethernet MII Bus Pins MPC860SAR is the UTPB2 pin one of the Utopia Bus Appears also at P8 120 LD7 PD14 MIIRXD2 UTPB1 I O MPC860 PD14 LIRSYNCA X MPCS860T MIIRXD2 is one of the Fast Ethernet MII Bus Pins MPC860SAR is the UTPBI pin one of the Utopia Bus Appears also at P8 121 LD8 PD15 MIIRXD3S UTPBO I O MPC860 PDIS LITSYNCA X MPCS860T MIIRXD3 is one of the Fast Ethernet MII Bus Pins MPC860SAR is the UTPBO pin one of the Utopia Bus Appears also at P8 122 GND GND GND GND 123 124 ETHLOOP ETHLOOP
42. D 111 A8 A8 A8 A8 I MPC s Address line 8 T S 112 GND GND GND GND 113 A29 A29 A29 A29 I MPC s Address line 29 T S 114 GND GND GND GND 115 A27 A27 A27 A27 I MPC s Address line 27 T S 116 GND GND GND GND 117 A28 A28 A28 A28 I MPC s Address line 28 T S 118 GND GND GND GND 119 A26 A26 A26 A26 I MPC s Address line 26 T S 120 GND GND GND GND 121 A25 A25 A25 A25 I MPC s Address line 25 T S 122 GND GND GND GND 123 A24 A24 A24 A24 I MPC s Address line 24 T S 124 GND GND GND GND 125 2 A22 A22 A22 I MPC s Address line 22 T S 126 GND GND GND GND 127 A3 A3 A3 A3 L MPC s Address line 3 Not used on the FADS T S 128 GND GND GND GND 34 Release 1 0 MPCS 60DB User s Manual Support Information TABLE 5 9 PM1 Interconnect Signals Daughter Pin Board Signal 860 Daughter 8001 O Attri x Daughter Daughter Description No Name Signal Name Sienal N Siendi Name bute General ignal Name 8 129 3 A23 A23 A23 I MPC s Address line 23 T S 130 GND GND GND GND 131 A4 A4 A4 A4 8 MPC s Address line 4 Not used on the FADS T S 132 GND GND GND GND 133 A2 A2 A2 A2 L MPC s Address line 2 Not used on the FADS T S 134 GND GND GND GND 135 A3 A3 AS AS I MPC s Address line 5 Not used on the FADS T S 136 GND GND GND GND 137 Al Al Al Al
43. D GND 78 79 80 SRESET SRESET SRESET SRESET I O MPC Soft Reset Driven by on board logic and may be L driven by O D off board logic with Open Drain gate only 81 GND GND GND GND 82 PORST PORST PORST PORST X L Power On reset for the MPC Not used on the FADS generated on the daughter boards 83 GND GND GND GND 84 HRESET HRESET HRESET HRESET I O MPC Hard Reset Driven by on board logic and may be L driven by off board logic with Open Drain gate only O D 85 GND GND GND GND 86 RSTCNF RSTCNF RSTCNF RSTCNF O L Hard Reset Configuration output Driven during Hard Reset to the daughter board to signal the MPC that it should sample Hard Reset configuration from the data bus 87 GND GND GND GND 88 R PORI R_PORI R_PORI R_PORI O L Main battery power on reset Generated as a result of main 3 3V bus going through power up or power down Drives on board logic as well either HARD RESET or Power On reset to the MPC 89 GND GND GND GND 90 91 40 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 10 PM2 Interconnect Signals Daughter Pin Board Signal 860 Daughter Soor S UBAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 92 BWAITA BWAITA BWAITA BWAITA O L Buffered PCMCIA slot A WAIT signal Used to prolong cycles to slow PC C
44. D GND GND GND 60 MODCKI MODCKI MODCKI MODCKI IO OPZ MODCKI STS PCMCIA Output Port 2 or Mode Clock 1 input or Special Transfer Start output Used at Power On reset as MODCKI Configured afterwards as STS 61 GND GND GND GND 62 RESETA RESETA RESETA RESETA LH PC Card reset signal 63 GND GND GND GND 64 65 66 BADDR28 BADDR28 BADDR28 BADDR28 I Burst Address Line 28 Dedicated for external master O X support Used to generate Burst address during external master burst cycles Pulled up but otherwise unused on the FADS 67 GND GND GND GND 68 TEXP TEXP TEXP TEXP X X MPC Timer Expired Not used on the FADS 69 GND GND GND GND 70 WAIT_B WAIT_B WAIT_B WAIT_B I O This signal is PCMCIA slot B wait signal Pulled up but L otherwise not used on the FADS 71 GND GND GND GND 39 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 10 PM2 Interconnect Signals Daughter Pin Board Signal 860 Daughter S007 SOOSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 72 MODCK2 MODCK2 MODCK2 MODCK2 IO OP3 MODCK2 DSDO PCMCIA Output Port 3 or Mode Clock 2 input or Special Transfer Start output Used at Power On reset as MODCK2 and configured afterwards as a OP3 May be used with alternate function 73 GND GND GND GND 74 75 76 N C N C N C N C TI GND GND GN
45. D14 D14 IO X MPC s Data line 14 45 GND GND GND GND 46 D13 D13 D13 D13 IO X MPC s Data line 13 47 GND GND GND GND 48 D12 D12 D12 D12 IO X MPC s Data line 12 49 GND GND GND GND 50 51 52 D11 D11 D11 D11 T O X MPC s Data line 11 53 GND GND GND GND 54 D10 D10 D10 D10 IO X MPC s Data line 10 55 GND GND GND GND 56 D9 D9 D9 D9 IO X MPC s Data line 9 57 GND GND GND GND 58 D8 D8 D8 D8 IO X MPC s Data line 8 54 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 12 PM4 Interconnect Signals Daughter Pin Board Signal 860 Daughter M 60548 is I Daughter Daughter Attribute Description No Name Signal Name Sienal N Sienal N General ignal Name ignal Name 59 GND GND GND GND 60 61 62 D7 D7 D7 D7 IO X MPC s Data line 7 63 GND GND GND GND 64 D6 D6 D6 D6 IO X MPC s Data line 6 65 GND GND GND GND 66 D5 D5 D5 D5 IO X MPC s Data line 5 67 GND GND GND GND 68 D4 D4 D4 D4 IO X MPC s Data line 4 69 GND GND GND GND 70 71 72 D3 D3 D3 D3 IO X MPC s Data line 3 73 GND GND GND GND 74 D2 D2 D2 D2 IO X MPC s Data line 2 75 GND GND GND GND 76 D1 D1 D1 D1 IO X MPC s Data line 1 77 GND GND GND GND 78 DO DO DO DO IO X MPC s Data line 0 79 GND GND GND GND 80 81 DRMH W DRMH W DRMH W DRMH_W O L Dram Half Word Sets the Dram to
46. ETHLOOP ETHLOOP O H Ethernet Transceiver Diagnostic Loop Back Control Generated by BCSR4 See TABLE 4 23 BCSR4 Description on page 57 In the motherboard documentations 125 TPFLDL TPFLDL TPFLDL TPFLDL O L Twisted Pair Full Duplex Allows for full duplex operation over the Ethernet Twisted Pair channel See TABLE 4 23 BCSR4 Description on page 57 In the motherboard documentations 126 TPSQEL TPSQEL TPSQEL TPSQEL O L Twisted Pair Signal Quality Error Test Enable See TABLE 4 23 BCSR4 Description on page 57 In the motherboard documentations 127 MDM AUD MDM AUD MDM AUD MDM AUD O L Not used 128 MODEMEN MODEMEN MODEMEN MODEMEN O L Not used 129 NC N C N C N C 130 GND GND GND GND 131 N C N C N C N C 132 5 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 11 PM3 Interconnect Signals Pin Daughter Board Signal Name General 660 Daughter Signal Name 860T Daughter Signal Name S60SAR Daughter Signal Name Attri bute Description 133 134 135 136 137 138 139 140 VCC VCC VCC VCC 52 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 12 PM4 Interconnect Signals Pin Renna 860 Daughter 0
47. GND 13 14 DCH DCH DCH PC8 VO MPC PI O port C 8 Appears also at P8 but otherwise X unused 15 PATI 1 PAI 1 I O MPC PI O port A 11 Appears also at P8 but otherwise X unused 16 GND GND GND GND 17 PA10 PA10 PA10 PA10 I O MPC PI O port A 10 Appears also at P8 but otherwise X unused 18 GND GND GND GND 19 20 PC7 PC7 PC7 PC7 I O MPC PI O port C 7 Appears also at P8 but otherwise X unused 44 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 11 PM3 Interconnect Signals Daughter Pin Board Signal 860 Daughter 8001 SOOSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 21 PA9 PA9 PA9 PA9 I O MPC PI O port A 9 Appears also at P8 but otherwise X unused 22 GND GND GND GND 23 PA8 PA8 PA8 PA8 I O MPC PI O port A 9 Appears also at P8 but otherwise X unused 24 GND GND GND GND 25 26 PC13 PC13 PC13 PC13 I O MPC PI O port C 13 Appears also at P8 but otherwise X unused 27 ETHTCK ETHTCK ETHTCK ETHTCK O X Ethernet port Transmit Clock When the ethernet port is disabled via 505151 tri stated Appears also at P8 28 GND GND GND GND 29 ETHRCK ETHRCK ETHRCK ETHRCK O X Ethernet port Receive Clock When the ethernet port is disabled via 505151 tri stated Appears also at P8 30 GND GND GND GND 31 32 FETHCFGO FETHCFGO Fast Ethernet CFGO signal When t
48. HOd H dEA U3MOd AEE yr EEA an aNd ONS 0 n 4m 82 c 02 e 3100 5002 o se Jnrer M lt ID y 13838 Du 0 X 2 NHI508 S e m6 le et M open DEED HMVY H r we 5 9 K 24x OND mE SC CHE ONE 40IN E BIz MoT LZ H 1 u yoy von s o 5 i ES 000 92 x sni wi ano u 3 8 DL L 30896 7 Y A F AW HOIH e 5 K EL 7 HA Nasau Te Us E Y 910 m 1 SL 4 ram 7 m 9 j 11 EN ITNA mam 8 yn Wa 5 2 5 8 4 DL L u E 2 5 v z 5 ano OND Le ET 9 T Lo w 813 Sg a i Ado do al 2 Cas TA INU BEES VIX ion ZH891Zi ZJA1X1 EES 0y 03N1X1 CI 1x3 Release 1 0 74 MPCS860DB User s Manual Support Information Sanna 8 Sdv2 6 aen YH x yao WV Wan 6 ew 6 0 7 im LOTId 905109110981 IER T 1 1 INI V 108010 d E Li A 300188 OND 390188 OND 300188 OND 300188 OND 3 A Ed T ANM 623 53 13 Jn anto ant a EEA A oND e 9 9 K 9 9 9 9 oND 83 6 cm SU 5 ea SU 013 Kal anv Ant m 522
49. I E SDRMCS SDRMCS SDRMCS SDRMCS 18 AT2 AT2 AT2 AT2 19 CS5 CS5 CS5 CS5 20 AT3 AT3 AT3 AT3 21 CS6 CS6 CS6 CS6 22 VFO VFO VFO VFO 23 CS7 CS7 CS7 CS7 24 VFI VFI VFI VFI 25 N C N C N C N C 26 VF2 VF2 VF2 VF2 27 R_W R_W R_W R_W 28 WAIT_B WAIT_B WAIT_B WAIT_B DO REG A REG A REG A REG A 30 RESETA RESETA RESETA RESETA 31 TSIZE1 TSIZE1 TSIZE1 TSIZE1 32 POE_A POE_A POE_A POE_A 33 BURST BURST BURST BURST 34 MODCK1 MODCK1 MODCK1 MODCK1 35 TEA TEA TEA TEA 36 MODCK2 MODCK2 MODCK2 MODCK2 37 SPKROUT SPKROUT SPKROUT SPKROUT 38 EXTCLK EXTCLK EXTCLK EXTCLK KR KR IRQ4 KR IRQ4 IRQ4 TABLE 5 2 P2 Interconnect Signals Mother dia MPC860Sar a Mother ECO MPCS60Sar M900 Daughter Daughter Daughter Daughter Board Daughter Board Daughter Pin E Board f Board Pinf d Board Board Signal Board Signal Signal Board Signal Name Signal Name Signal Name Signal Nam Signal Name Name Name Name 1 N C N C N C N C 2 N C N C N C N C 3 GND GND GND GND 4 N C N C N C N C 5 NC NC NC NC 6 BSOA BSOA BSOA BSOA 20 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 2 P2 Interconnect Signals Mother 01 MPC860Sar MEA Mother
50. I Description on page 49 In the motherboard documentations 97 PB14 PB14 PB14 PB14 I O MPC PI O port B 14 Appears also at P8 but otherwise X unused 98 PC4 PC4 PC4 PC4 1 0 MPC PI O port C 4 Appears also at P8 but otherwise X unused 99 PC5 PC5 PC5 PC5 I O MPC PI O port C 5 Appears also at P8 but otherwise X unused 100 PC6 PC6 PC6 PC6 I O MPC PI O port C 6 Appears also at P8 but otherwise X unused 101 GND GND GND GND 102 RS EN2 RS EN2 RS EN2 RS EN2 O L RS232 port 1 Enable Connected to BCSRI See TABLE 4 10 BCSR1 Description on page 49 In the motherboard documentation 103 SHIFT C PD3 MIITXDI SOC I O MPC860 PD3 RRJECT4 X MPCS860T MIITXDI is one of the Fast Ethernet MII Bus Pins MPC860SAR is the SOC pin one of the Utopia Bus 104 GND GND GND GND 105 106 HSYNC PD4 MIITXD2 UTPB7 I O MPC860 PD4 RRJECT3 X MPCS860T MIITXD2 is one of the Fast Ethernet MII Bus Pins MPC860SAR is the UTPB7 pin one of the Utopia Bus Appears also at P8 107 VSYNC PD5 MIITXD3 UTPB6 I O MPC860 PDS RRJECT2 X MPCS860T MIITXD3 is one of the Fast Ethernet MII Bus Pins MPC860SAR is the UTPB6 pin one of the Utopia Bus Appears also at P8 108 GND GND GND GND 109 110 LOE PD6 MIIRXDV UTPBS I O MPC860 PD6 RRJECT3 X MPC860T MIITXRXDV is one of the Fast Ethernet MII Bus Pins MPC860SAR is the UTPBS pin one of the Utopia Bus Appears also at P8 49 Release 1 0 MPC
51. I O MPC PI O port C 12 Appears also at P8 but otherwise X unused 54 PB26 PB26 PB26 PB26 I O MPC PI O port C 26 Appears also at P8 but otherwise X unused 55 GND GND GND GND 56 46 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 11 PM3 Interconnect Signals Daughter Pin Board Signal 860 Daughter Soor SOOSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 57 PA5 PA5 PA5 PAS I O MPC PI O port A 5 Appears also at P8 but otherwise X unused 58 GND GND GND GND 59 60 PA4 PA4 PA4 PA4 I O MPC PI O port A A Appears also at P8 but otherwise X unused 61 E CLSN E CLSN E CLSN E CLSN I O Ethernet Port Collision indication signal Connected to H the SCC s CTS signal When the ethernet port is disabled via BCSR1 may be used off board for any alternate function 62 E RENA E RENA E RENA E RENA I O Ethernet Receive Enable Connected to the SCC s CD H signal Active when there is network activity When the ethernet port is disabled via BCSR1 may be used off board for any alternate function 63 SPARE2 SPARE2 MIIDIO SPARE2 I O MPC spare line 2 Pulled up but otherwise unused on X the FADS 860T Transfer control information between the phy and mac 64 Applies only for MPC823 daughter board Video Encoder Enable Indication G
52. I RSRXDI RSRXDI O X RS232 Port 1 Receive Data When RS232 port 1 is disabled via BCSRI tri stated and may be used for any alternate function Appears also at P8 40 RSDTRI RSDTRI RSDTRI RSDTRI O L RS232 port 1 DTR signal When RS232 port 1 is disabled via BCSR1 tri stated and may be used for any alternate function Appears also at P8 41 GND GND GND GND 42 RSTXD2 RSTXD2 RSTXD2 PHSEL 1 LX RS232 Port 2 Transmit Data When RS232 port 2 is disabled via BCSR1 may be used for any alternate function Appears also at P8 860SAR PHSEL 1 Least significant bit of phy select bus used for MPHY mod only 43 RSRXD2 RSRXD2 RSRXD2 PHSEL 0 0 X RS232 Port 2 Receive Data When RS232 port 2 is disabled via BCSRI tri stated and may be used for any alternate function Appears also at P8 860SAR PHSEL 0 Least significant bit of phy select bus used for MPHY mod only 44 RSDTR2 RSDTR2 RSDTR2 RSDTR2 O L RS232 port 2 DTR signal When RS232 port 2 is disabled via BCSR1 tri stated and may be used for any alternate function Appears also at P8 45 PC14 PC14 PC14 PC14 I O MPC PI O port C 14 Appears also at P8 but otherwise X unused 46 GND GND GND GND 47 N C N C N C N C 48 GND GND GND GND 49 50 PB27 PB27 PB27 PB27 I O MPC PI O port B 27 Appears also at P8 but otherwise X unused 51 PB28 PB28 PB28 PB28 I O MPC PI O port B 28 Appears also at P8 but otherwise X unused 52 GND GND GND GND 53 PC12 PC12 PC12 PC12
53. IRD EN IRD EN IRD EN IRD EN O L Infra Red Enable Connected to BCSRI See TABLE 4 10 BCSR1 Description on page 49 In the motherboard documentations 85 PAI PAI PAI PAI I O MPC PI O port A 1 Appears also at P8 but otherwise X unused 86 GND GND GND GND 87 88 N C N C N C N C 89 PAO PAO PAO PAO I O MPC PI O port A 0 Appears also at P8 but otherwise X unused 90 GND GND GND GND 91 92 TMS TMS TMS TMS I O JTAG port Test Mode Select input Used to select test X through the JTAG port Pulled up but otherwise not used on the FADS 93 PB16 PB16 PB16 PHREQ 0 IO MPC PI O port B 16 Appears also at P8 but otherwise X unused 860T PHREQ O least significant bit of phy request bus used in PHY only 94 TRST TRST TRST TRST O L JTAG port Reset Pulled down with a zero ohm resistor so that the JTAG logic is constantly reset Otherwise unused on the FADS 48 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 11 PM3 Interconnect Signals Daughter Pin Board Signal 860 Daughter Soor SUSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal Ni Sienal Ni bute General ignal Name ignal Name 95 PB15 PB15 PB15 PB15 I O MPC PI O port B 15 Appears also at P8 but otherwise X unused 96 RS ENI RS ENI RS ENI RS ENI O L RS232 port 1 Enable Connected to BCSRI See TABLE 4 10 BCSR
54. N ETHEN ETHEN ETHEN 0 See PM3 82 A27 IRQ3 IRQ3 IRQ3 IRQ3 UL A28 IRQ2 IRQ2 IRQ2 IRQ2 LL RSV IRQ2 See PM2 26 Used as an IRQ in the 860T Daughter Board and in the 860Sar PHY Board A29 IRQI IRQI IRQI IRQI LL See PM2 126 A30 NMI NMI NMI NMI LL See PM2 134 A3 RS ENI RS ENI RS ENI RS ENI O L See PM3 96 A32 GND GND GND GND Bl LCD_A PB31 PB31 PB31 1 0 LCD_A PB31 See PM3 33 B2 PB30 PB30 PB30 PB30 1 0 See PM3 35 SPI_CLK If the 860Sar is used with the 860Sar phy board this signal can be use for SPI_CLK in the 860Sar Phy Board B3 PB29 PB29 PB29 PB29 1 0 See PM3 37 SPI IN If the 860Sar is used with the 860Sar phy board this signal can be use for SPI IN in the 860Sar Phy Board B4 PB28 PB28 PB28 PB28 1 0 See PM3 51 SPI_OUT If the 860Sar is used with the 860Sar phy board this signal can be use for SPI IN in the 860Sar Phy Board B5 I2CDAT PB27 PB27 PB27 I O PB27 I2CDAT See PM3 50 PC PHY If the 860Sar is used with the 860Sar phy board this signal can be use for CS PHY in the 860Sar Phy Board 64 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 17 P8 Interconnect Signals Daughter 860 860T 860Sar Pin BoardSignal Daughter Daughter Daughter Attrib D is No Name BoardSignal BoardSignal BoardSignal ute SEDET General Name Name Name B6 PB26 PB26 PB26 PB26 1 0 PB26 I2CCLK S
55. N C 3 GND GND GND GND 4 5 TEA TEA TEA TEA 6 7 AO AO AO AO 8 A16 A16 A16 A16 9 Al Al Al Al 10 A17 A17 A17 A17 11 A2 A2 A2 A2 12 A18 A18 A18 A18 13 A3 A3 A3 A3 14 A19 A19 A19 A19 15 A4 A4 A4 A4 16 A20 A20 A20 A20 21 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 3 P3 Interconnect Signals 22 Mother MEG SUD MPC860Sar M Daughter Daughter 2 Board Daughter Pin i Board Board Signal Board Signal gt Signal Signal Name Name Name Name 18 A21 A21 A21 A21 20 A22 A22 A22 A22 22 A23 A23 A23 A23 24 A24 A24 A24 A24 26 A25 A25 A25 A25 28 A26 A26 A26 A26 30 A27 A27 A27 A27 32 A28 A28 A28 A28 34 A29 A29 A29 A29 36 A30 A30 A30 A30 38 A31 A31 A31 A31 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 4 P4 Interconnect Signals Mother Daughter Daughter Daughter Mother Eun 860SAR MPC860 Pin Board Board Board Board Pin Board ES i Daughter Daughter Signal Signal Signal Signal Signal Fade Signal Board Signal Name Name Name Name Name Ce Name Name Name 1 N C N C N C N C 2 N C N C 3 GND GND GND GND 4 5 N C N C N C N C 6 LD1 MIIRXCLK PD8 1 PAO PAO
56. O im SWL Z6 16 211 91 SL YOXAN s Es OO om 06 een 68 0111 zt ET H3XHIN TEM E zn 12 QT 1 88 a 303134 OO INASA 98 5B DESEN 07 6 EOIN 7 TO Q E OKI NASH WI 78 EL NSD O 0 301 N3H13 za 18 M HAHO loo S Aan a 7 E 700 T mem SKS E Se CZ c a L dE oc wd BE al a 8 B 75E 2 GER EVd gma 3 m yg 5 T 1 SAS n e 59 sa o DS EG DOHIN a 79 EES Erg NSD 3 io oS IE Wd 65 09 Bric 52 al Era al C 2 9Zgd Bris Za oro 75 Erg Es mol z ai 9 6 67 05 za 97 EG 7a t Zul SH na EG 2005 mo a7 20 58 z Er al 7 TaS 07 6E joxusu QI 10X154 BE LE oa gc En E 2101 9t E amp au aro w 0008134 a m H zm 1 OE m 82 17 DE wl oS lt gt CO 52 57 170 sz 7t EE 8Yd zo z2 ZC ol ZE 13d OC py m 5 07 a Old c 8 ST Ren sza 9 31 seo m m OXON uo zB e m CHEN 01 63d 8 L 870 Des 9 2 E 5 XIH13 lt 2 670 E um E ocd 2 1 XuH13 Ted 7 ND i Em T71 79 MPCS860DB User s Manual Support Information
57. PC13 PC13 33 PB27 PB27 PB27 PB27 34 PC14 PC14 PC14 PC14 35 PB28 PB28 PB28 PB28 36 SPARE4 MIICOL SPARE4 SPARE4 37 PB29 PB29 PB29 PB29 38 N C N C N C N C TABLE 5 7 P8 Interconnect Signals MPC860T 680SAR MPC860 MPC860TD S60SAR MPC860 Mother Mother Daughter Daughter Daughter aughter Daughter Daughter Pin Board Pin Board gt Board Board Board Board Board Board Signal Signal Name Signal Signal Signal Nome Signal Signal Signal Name Name Name Name Name Name 1 N C N C N C N C 2 N C N C N C N C 3 GND GND GND GND 4 N C N C N C N C 5 N C N C N C N C 6 N C N C N C N C 1 DO DO DO DO 8 D16 D16 D16 D16 9 DI DI D1 D1 10 D17 D17 D17 D17 11 D2 D2 D2 D2 12 D18 D18 D18 D18 13 D3 D3 D3 D3 14 D19 D19 D19 D19 15 D4 D4 D4 D4 16 D20 D20 D20 D20 17 D5 D5 D5 D5 18 D21 D21 D21 D21 19 D6 D6 D6 D6 20 D22 D22 D22 D22 21 D7 D7 D7 D7 22 B23 D23 D23 D23 23 D8 D8 D8 D8 24 D24 D24 D24 D24 25 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 7 P8 Interconnect Signals MPC860TD S60SAR MPC860 Mother aughter Daughter Daughter Pin Board S Board Board Board Signal 3 N Signal Signal Signal Ed Name Name Name 26 D25 D25 D25 D25 28 D26 D26 D26 D26 30 D27 D27 D27 D27 32 D28 D28 D28 D28 34 D29 D29 D29 D29 36 D30 D30 D30 D30 38 D31 D31 D31 D31 Release 1 0 MPCS860DB
58. PC14 1 0 See PM3 45 LF If the 860Sar is used with the 860Sar phy board this signal can be use for LF in the 860Sar Phy Board B22 PC13 PC13 PC13 PC13 10 See PM3 26 CS_T1 If the 860Sar is used with the 860Sar phy board this signal can be use for CS_T1 S in the 860Sar Phy Board B23 PC12 PC12 PC12 PC12 1 0 See PM3 53 65 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 17 P8 Interconnect Signals Daughter 860 860T 860Sar Pin BoardSignal Daughter Daughter Daughter Attrib D is No Name BoardSignal BoardSignal BoardSignal ute Senn General Name Name Name B24 E_CLSN E_CLSN E_CLSN E_CLSNS 1 0 See PM3 61 B25 E RENA E RENA E RENA E RENA 1 0 See PM3 62 B26 USBRXP PC9 PC9 PC9 1 0 See PM3 8 AD1 If the 860Sar is used with the 860Sar phy board this signal can be use for ADI in the 860Sar Phy Board B27 USBRXN PC8 PC8 PC8 1 0 See PM3 14 ADO If the 860Sar is used with the 860Sar phy board this signal can be use for ADO in the 860Sar Phy Board B28 USBTXP PC7 PC7 PC7 1 0 See PM3 20 LIRSYNC If the 860Sar is used with the 860Sar phy board this B signal can be use for LITSYNCB in the 860Sar Phy Board B29 LIRSYNCB PC6 PC6 PC6 1 0 See PM3 100 LIRSYNC If the 860Sar is used with the 860Sar phy board this B signal can be use for LIRSYNCB in the 860Sar Phy Board B30 PCS DCH PC5
59. PC860T device If using a MPC860SAR and also using the MPC860SAR PHY board the IRQ2 signal is coming from this board More details are in the MPC860SAR PHY board user manual Clock Generator 3 4 Although most of clock generator logic is found on this board it is documented within the motherboard User s Manual since it is common to all daughter boards See 4 3 Clock Generator on page 30 of the MPC8XXFADS User s Manual 4e4 Fast Ethernet Support This section is relevant for 860T only The MPC860DB has on board full support for 802 3 Media Independent Interface MII made by the Level One LXT970 device the connection between the LXT970 and the line can be made by twisted pair RJ45 connector or by fiber optic connector which is optional The LXT970 used in the MPC860DB has the following features it is a IEEE 802 3 Compatible which is a TOBASE T and 100BASE TX using a single RJ45 connector It support an auto negotiation via Fast Link Pulse FLP exchange and parallel detection for legacy 108 81 1 and 100BASE TX systems MII interface 1 OOBASE FX fiber optic capable configurable through the MII serial port it can be DTE repeater or switch application The LXT970 has several control pins that can configure the mode of operation These pins are separated to two pins groups the WH control pins and the SW control pins The HW control pins are the MF 0 4 connected to the DS1 the SW control pins are the TRSTE FDE and CFG 0 1 whic
60. Pin No Signal Name Attribute Description No Difference TABLE 5 14 PX2 PM2 Interconnect Signals Differences Pin No Signal Name Attribute Description 76 EXTCLK O X External Clock 4MHz clock generator output the input clock to the MPC TABLE 5 15 PX3 PM3 Interconnect Signals Differences Pin No Signal Name Attribute Description No Difference 60 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 16 PX4 PM4 Interconnect Signals Differences Pin No Signal Name Attribute Description No Difference 61 Release 1 0 62 MPCS 60DB User s Manual Support Information Seles MPC8XXFADS s P6 Serial Ports Expansion Connector P8 is a 96 pin 90 DIN 41612 connector which allows for convenient expansion of the MPC s serial ports Although this connector resides on the mother board it is documented here this since it s signal assignment is unique per each MPCS8XX For the 860SAR this connector is the connector which through it the user will operate the 8608AR PHY board In the 860SAR PHY board this connector called P13 Note The contents of TABLE 5 17 P8 Interconnect Signals below might conflict with MPC8XXFADS s schematic page 14 This since that the schematic page is named in MPC821 860 terms In such case this table overrides Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 17
61. S860DB User s Manual Support Information TABLE 5 11 PM3 Interconnect Signals Daughter Pin Board Signal 860 Daughter Soor SUSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal Name Sienal Name bute General 8 8 111 FETHRST FETHRST O L Fast Ethernet Reset When this pin active LOW signal is being asserted the Fast ethernet tranceiver is being reset 112 FETHCFGI FETHCFG1 O H Fast Ethernet CFG1 signal When the LXT970 is in auto negotiation this pin determines operating speed advertisement capability in combination with MF4 see See the LXT970 documentation When auto negotiation is disabled this input enables 10Mbps link test function and directly affects bit 19 8 When this pin is high 10Mbps link test is disabled 19 8 af When this pin is low 10Mbps link test is enabled 19 8 0 113 LDO PD7 MIIRXER UTPB4 I O MPC860s PD7 RTS3 X MPC860T MIIRXER is one of the Fast Ethernet MII Bus Pins MPC860SAR is the UTPB4 pin one of the Utopia Bus Appears also at P8 114 LD1 PD8 MIIRXCLK MPC860s PD8 TXD4 MPC860T MIIRXCLK is one of the Fast Ethernet MII Bus Pins Bus 115 LD2 PD9 MIITXDO UTPCLK I O MPC860s PD9 RXD4 X MPCS860T MIITXDO is one of the Fast Ethernet MII Bus Pins MPC860SAR is the UTPB7 pin one of the Utopia Bus 116 LD3 PD10 MIIRXDO TXENB I O MPC860s PD10 TXD3 X MPC860T MIIRXDO is one of the Fast Ethernet MII Bus Pins MP
62. TABLE 5 10 PM2 Interconnect Signals Daughter Pin Board Signal 860 Daughter Soor SUSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal Ni Sienal N bute General ignal Name ignal Name 108 MODIN MODIN MODIN MODIN O X This signal selects between clock generator and the 32768 Hz crystal as clock sources for the MPC Its is driven by DS2 4 See 2 3 2 Clock Source Selection on page 7 In the motherboard documentations 109 GND GND GND GND 110 571 BBVDI BBVDI BBVDI O X Buffered PCMCIA slot A Battery Voltage Detect 1 In fact IP A6 Used in conjunction with BBVD2 to determine the battery status of a PC Card 111 GND GND GND GND 112 BCD2 BCD2 BCD2 BCD2 O L Buffered PCMCIA slot A Card Detect 2 In fact IP A3 Input Port 3 of PCMCIA slot A Used as Card Detect indication in conjunction with BCD1 113 GND GND GND GND 114 BBVD2 BBVD2 BBVD2 BBVD2 O X Buffered PCMCIA slot A Battery Voltage Detect 2 In fact IP AS Used in conjunction with BBVD1 to determine the battery status of a PC Card 115 GND GND GND GND 116 117 NC N C N C N C 118 DPO DPO DPO DPO I O DPO IRQ3 Data Parity line O or Interrupt Request 3 May generate and receive parity data for D 0 7 bits connected to the DRAM SIMM May not be configured as IRQ3 119 V3 3 V3 3 V3 3 V3 3 120 DP2 DP2 DP2 DP2 1 0 DP2 IRQS Data Pari
63. TEA TEA TEA TEA I O Transfer Error Acknowledge Pulled up not driven on L board O D 6 VCC VCC VCC VCC 7 BR BR BR BR I MPC s Bus Request signal Pulled up on the FADS 0 17 but otherwise unused 8 VCC VCC VCC VCC 9 BURST BURST BURST BURST I O MPC s Burst indication Pulled up on the FADS but L otherwise unused 10 VCC VCC VCC VCC 11 GPL4A GPL4A GPL4A GPL4A X L UPMA general purpose line 4 Not used on the FADS 12 VCC VCC VCC VCC 13 TA TA TA TA I O MPC s transfer Acknowledge signal Indicates end of L bus cycle used with FADS logic 14 VCC VCC VCC VCC 15 TS TS TS TS I O MPC s Transfer Start indication Pulled up but L otherwise unused on the FADS 16 VCC VCC VCC VCC 17 GPL5B GPL5B GPL5B GPL5B O L General Purpose Line 5 of UPMB Not used on the FADS 18 VCC VCC VCC VCC 19 BG BG BG BG VO MPC s Bus grant signal Pulled up on the FADS but L otherwise unused 20 VCC VCC VCC VCC 21 GPL4B GPL4B GPL4B GPL4B O L General Purpose Line 4 of UPMB Not used on the FADS 22 VCC VCC VCC VCC 29 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 9 PM1 Interconnect Signals Daughter Pin Board Signal 860 Daughter 8001 SOAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 23 R_W R_W R_W R_W I
64. THFDE FETHFDE FETHFDE Full Duplex Enable when auto negotiation is enable the FDE pin of the LXT970 determine full duplex advertisement capability in combination with MF4 and CFG1 See than LXT970 documentation When auto negotiation is disable the FDE pin of the LXT970 effects full duplex and determines the value of bit 0 8 Duplex Mode When this pin is high Full Duplex in Enable 0 8 1 When this pin is low Full Duplex is Disable 0 8 0 88 PCCEN PCCEN PCCEN PCCEN PC Card Enable Enables the PC Card to be accessed by the FADS 89 EXTOLIO EXTOLIO EXTOLIO EXTOLIO External Tool Identification 0 Connected to BCSR2 See 4 11 04 BCSR2 Board Control Status Register 2 on page 51 In the motherboard documentations 90 SGLAMP SGLAMP SGLAMP SGLAMP Signaling Lamp Used for misc s w signaling purpose See TABLE 4 23 BCSR4 Description on page 57 In the motherboard documentations 91 EXTOLI2 EXTOLI2 EXTOLI2 EXTOLI2 T O X External Tool Identification 2 Connected to BCSR2 See 4 11 04 BCSR2 Board Control Status Register 2 on page 51 In the motherboard documentations 92 USBVCCI USBVCCI USBVCCI USBVCCI Applies only for MPC823DB Reserved Signal for USB Power See TABLE 4 23 BCSR4 Description on page 57 In the motherboard documentations 93 DBREVO DBREVO DBREVO DBREVO LX Daughter Bo
65. ard Revision Code Signal 0 The MSB of the D B revision Code See TABLE 4 13 BCSR2 Description on page 52 In the motherboard documentations 94 EXTOLII EXTOLII EXTOLII EXTOLII I O X External Tool Identification 1 Connected to BCSR2 See 4 11 4 BCSR2 Board Control Status Register 2 on page 51 In the motherboard documentations 56 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 12 PM4 Interconnect Signals Pin Daughter Board Signal Name General 660 Daughter Signal Name 860T Daughter Signal Name S60SAR Daughter Signal Name Attribute Description 95 DBREV2 DBREV2 DBREV2 DBREV2 LX Daughter Board Revision Code Signal 2 The LMSB of the D B revision Code See TABLE 4 13 BCSR2 Description on page 52 In the motherboard documentations 96 EXTOLI3 EXTOLI3 EXTOLI3 EXTOLI3 I O X External Tool Identification 3 Connected to BCSR2 See 4 11 4 BCSR2 Board Control Status Register 2 on page 51 In the motherboard documentations 97 BCSR3R1 BCSR3R1 BCSR3R1 BCSR3RI I O X Reserved signal 1 in BCSR3 See TABLE 4 19 BCSR3 Description on page 55 In the motherboard documentations 98 DBREVI DBREVI DBREVI DBREVI I O X Daughter Board Revision Code Signal 1 See TABLE 4 13 BCSR2 Description on page 52 In the motherboard docum
66. ards In case of MPC823 or MPC850 daughter boards connected to WAIT B signal of the MPC 93 GND GND GND GND 94 BWP BWP BWP BWP 0 1 Buffered PCMCIA slot A Write Protect In fact IP A2 IOIS16A Used as PC card write protect indication or as 16 bit I O capability indication for PCMCIA slot A In case of MPC823 or MPC850 daughter boards connected to IP B2 signal of the MPC 95 GND GND GND GND 96 BVSI BVSI BVSI BVSI O X Buffered PCMCIA slot A Voltage Sense 1 In fact IP AO Used in conjunction with BVS2 to determine the operation voltage of a PCMCIA card 97 GND GND GND GND 98 BRDY BRDY BRDY BRDY O H Buffered PCMCIA slot A Ready signal In fact IP A7 Used as PCMCIA port A Card Ready indication 99 GND GND GND GND 100 101 102 DP3 DP3 DP3 DP3 I O DP3 IRQ6 Data Parity line 3 or Interrupt Request 6 X May generate and receive parity data for D 24 31 bits connected to the DRAM SIMM May also be configured as IRQ6 input for the MPC 103 GND GND GND GND 104 BVS2 BVS2 BVS2 BVS2 0 X Buffered PCMCIA slot A Voltage Sense 2 In fact IP Al Used in conjunction with 8 81 to determine the operation voltage of a PCMCIA card 105 GND GND GND GND 106 BCDI BCDI BCDI BCDI O L Buffered PCMCIA slot A Card Detect 1 In fact IP A4 Input Port 4 of PCMCIA slot A Used as Card Detect indication in conjunction with BCD2 107 GND GND GND GND 4 Release 1 0 MPCS860DB User s Manual Support Information
67. auto negotiation is enable the FDE pin of the LXT970 1 R W determine full duplex advertisement capability in combination with MF4 and CFG1 See the LXT970 documentation When auto negotiation is disable the FDE pin of the LXT970 effects full duplex and determines the value of bit 0 8 Duplex Mode When this pin is high Full Duplex is Enable 0 8 1 When this pin is low Full Duplex is Disable 0 8 0 9 FETHCFG1 Fast Ethernet CFG1 signal When the LXT970 is in auto negotiation this pin 1 R W determines operating speed advertisement capability in combination with MF4 see See the LXT970 documentation When auto negotiation is disabled this input enables 10Mbps link test function and directly affects bit 19 8 When this pin is high 10Mbps link test is disabled 19 8 1 When this pin is low 10Mbps link test is enabled 19 8 0 10 FETHRST Fast Ethernet Reset When this pin active LOW signal is being asserted the Fast 1 R W ethernet tranceiver is being reset The Fast Ethernet transceiver support two physical interfaces o 1145 8pin connector for the twisted pair use This connector is mounted on the board o Fiber Optic multi mode tranceiver not mounted on the board it is an optional The board is designed for the HP HFBR 5103 or HFBR 5105 45 Board Control amp Status Register BCSR Most BCSR control signals and some of BCSR s status signals are available on the motherboard connectors and on the expansi
68. e 0 Configured as a ATO May be used for alternate function 47 GND GND GND GND 48 POE_A POE_A POE_A POE_A LL In fact OP1 of the PCMCIA I F Enables address buffers towards the PC Card 49 GND GND GND GND 50 51 52 BADDR30 BADDR30 BADDR30 BADDR30 I Burst Address Line 30 Dedicated for external master O X support Used to generate Burst address during external master burst cycles Pulled up but otherwise unused on the FADS 53 GND GND GND GND 38 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 10 PM2 Interconnect Signals Daughter Pin Board Signal 860 Daughter 8001 BOUM Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 54 ALE_A ALE_A ALE_A ALE_A LH Address Latch Enable for PCMCIA slot A Latches address in external latches at the beginning of access to a PC Card 55 GND GND GND GND 56 BADDR29 BADDR29 BADDR29 BADDR29 I Burst Address Line 29 Dedicated for external master O X support Used to generate Burst address during external master burst cycles Pulled up but otherwise unused on the FADS 57 GND GND GND GND 58 AS AS AS AS I O Asynchronous external master Address Strobe signal L When asserted L by the external master the MPC recognizes an asynchronous cycle in progress Pulled up but otherwise unused on the FADS 59 GN
69. ects e UPM User Programmable Machine 2 GPCM General Purpose Chip select Machine GPL General Purpose Line associated with the UPM DB Daughter Board the MPC860DB the subject of this document e BSCR Board Control amp Status Register ZIF Zero Input Force BGA Ball Grid Array Spec engineering Specification Document e MPC In this document it can be one of the MPC860T or MPC860SAR or MPC860 3 Related Documentation MPC User s Manual e ADI Board Specification MPC8XXFADS Engineering Specification Level One s LXT970 Data Sheet May be obtained from http www levell ds 970 html Relevant only for MPC860T e MPC860SAR PHY Board User Manual Relevant only for MPC860SAR A Board s bottom B Board s top C Not to be mistaken for the M683XX Family Ads Release 1 0 MPCS860DB User s Manual 1 SPECIFICATIONS The MPC860DB specifications are given in TABLE 1 1 TABLE 1 1 860DB Specifications CHARACTERISTICS SPECIFICATIONS Microprocessor MPC860T or MPC860SAR or the MPC860 50 MHz Operating temperature 0 C 30 C Storage temperature 25 C to 85 C Relative humidity 5 to 90 non condensing Dimensions Length Width Thickness 145mm 125 mm 0 063 1 6 mm 15 MPCS860DB Features o MPC running upto 50 MHz o On Board Fast Ethernet Level One LXT970 with shutdown option over Twisted pair Ethernet 100Base TX this d
70. ee PM3 54 RST_BR If the 860Sar is used with the 860Sar phy board this signal can be use for RST_BRD in the 860Sar Phy Board B7 RSTXD1 RSTXDI RSTXDI RSTXDI 1 0 See PM3 38 B8 RSRXDI RSRXDI RSRXDI RSRXDI 1 0 See PM3 39 B9 RSDTRI RSDTRI RSDTRI RSDTRI 1 0 See PM3 40 B10 RSDTR2 RSDTR2 RSDTR2 RSDTR2 1 0 See PM3 44 B11 RSTXD2 RSTXD2 RSTXD2 RSTXD2 1 0 See PM3 5 11 42 B12 RSRXD2 RSRXD2 RSRXD2 RSRXD2 1 0 See PM3 43 B13 E TENA E TENA E TENA E TENA 1 0 See PM3 77 B14 LCD B PB18 PB18 PB18 1 0 PB18 LCD_B See PM3 76 READ If the 860Sar is used with the 860Sar phy board this signal can be use for READ in the 860Sar Phy Board B15 LCD C PB17 PB17 PB17 1 0 PB17 LCD_C See PM3 75 AD5 If the 860Sar is used with the 860Sar phy board this signal can be use for ADS in the 860Sar Phy Board B16 PB16 PB16 PB16 PB16 1 0 See PM3 93 AD4 S If the 860Sar is used with the 860Sar phy board this signal can be use for AD4 in the 860Sar Phy Board B17 5 PB15 PB15 PB15 If the 860Sar is used with the 860Sar phy board this TCAV signal can be use for TCAV in the 860Sar Phy Board B18 PB14 PB14 PB14 PB14 If the 860Sar is used with the 860Sar phy board this ALE signal can be use for ALE in the 860Sar Phy Board B19 GND GND GND GND B20 BINPAK BINPAK BINPAK BINPAK 1 0 See PM3 34 RCAV If the 860Sar is used with the 860Sar phy board this signal can be use for RCAV in the 860Sar Phy Board B21 PC14 PC14 PC14
71. eir reference designation TABLE 5 18 PILOT Part List Reference Designation Part Description Type Part Number total BOARD 084 00114 1 C5 C6 C7 C8 C9 CIO C11 C12 Capacitor O 1uF 16V 10 0603 SMD 021 00118 31 C14 C15 C16 C17 C19 C20 C22 Ceramic C23 C24 C25 C28 C29 C32 C37 C38 C39 C40 C43 C47 C48 C49 C52 C53 C2 C3 C4 C31 C33 C34 C36 C51 Capacitor 10uF 20V 10 SMD 023 00027 8 Size C Tantalum C13 Capacitor 100uF 10V 10 SMD 023 00038 1 Size D Tantalum C30 C35 Capacitor 1uF 25V 10 SMD 023 00028 2 Size A Tantalum C18 C21 Capacitor 10pF 50V 10 COG SMD 021 00097 2 1206 Ceramic C26 Capacitor 5000pF SOV 10 1206 SMD 021 00080 1 Ceramic C27 Capacitor 0 68uF 20V 10 SMD 023 00041 1 Size A Tantalum C1 C44 C45 C46 Cap 0 01uF 50V 10 NPO 1206 SMD 021 00070 4 C41 C42 Cap 18pF 50V COG 1206 CER T R SMD 021 00128 2 C50 Cap InF2KV X7R 1210 CER CAP SMD 021 00126 1 T R D1 Diode SMD LL4004G SMD 048 LL4004G 1 DS1 Dip Switch 90HBW08S SMD 040 00027 1 H1 H2 H3 Gnd Bridge Gold Plated TH 022 00011 3 J1 J2 J3 Jumper Header 3 Pole with TH 028 00162 3 Fabricated Jumper J1 J2 J3 TH 009 00124 3 J4 J5 Jumper Soldered TH 022 00011 2 L1 Inductor 8 2 mHy TH 024 00020 1 L2 L3 L4 L5 L6 L7 Ferrite bid SMD 024 00013 6 LD1 LD2 LD3 LD4 LD5 LD6 LD7 Led Green SMD 048 01005 7 P1 P2 P3 P4 P5 P6 P8 Connector 38 pin Receptacle SMD 00
72. enerated by BCSR4 65 GND GND GND GND 66 67 SYSCLK SYSCLK SYSCLK SYSCLK LX System Clock In fact the CLKOUT of the MPC 68 GND GND GND GND 69 70 71 PA3 PA3 PA3 PA3 I O MPC PI O port A 3 Appears also at P8 but otherwise X unused 72 GND GND GND GND 73 74 PA2 PA2 PA2 PA2 I O MPC PI O port A 2 Appears also at P8 but otherwise X unused 75 PB17 PB17 PB17 PHREQ 1 I O MPC PI O port B 17 Appears also at P8 but otherwise X unused 860T PHREQ 1 least significant bit of phy request bus used in PHY only 47 Release 1 0 MPCS 60DB User s Manual Support Information TABLE 5 11 PM3 Interconnect Signals Daughter Pin Board Signal 860 Daughter Soor S0054R Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 76 PB18 PB18 PB18 PB18 I O MPC PI O port B 18 Appears also at P8 but otherwise X unused TI E TENA E TENA E TENA E TENA I O Ethernet port Transmit Enable Connected to the SCC s H RTS signal When active transmit is enabled via the MC68160 EEST When the ethernet port is disabled via 8205151 may be used off board for any alternate function 78 GND GND GND GND 79 N C N C N C N C 80 81 82 ETHEN ETHEN ETHEN ETHEN O L Ethernet Port Enable Connected to BCSRI See TABLE 4 10 BCSRI Description on page 49 In the motherboard documentations 83 N C N C N C N C 84
73. entations 99 DBID1 DBID1 DBID1 DBID1 1 0 X Daughter Board ID Code 1 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 55 In the motherboard documentations 100 BCSR3RO BCSR3RO BCSR3RO BCSR3RO I O X Reserved signal 0 in BCSR3 See TABLE 4 19 BCSR3 Description on page 55 In the motherboard documentations 101 DBID3 DBID3 DBID3 DBID3 I O X Daughter Board ID Code 3 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 55 In the motherboard documentations 102 DBIDO DBIDO DBIDO DBIDO I O X Daughter Board ID Code 0 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 55 In the motherboard documentations 103 DBID5 DBID5 DBID5 DBID5 I O X Daughter Board ID Code 5 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 55 In the motherboard documentations 104 DBID2 DBID2 DBID2 DBID2 I O X Daughter Board ID Code 2 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 55 In the motherboard documentations 105 BCSR3R13 BCSR3R13 BCSR3R13 BCSR3R13
74. er Description No Name Signal Name Sienal Name Sienal Name bute General er4 8 83 A20 A20 A20 A20 I MPC s Address line 20 T S 84 GND GND GND GND 85 AT AT AT AT I MPC s Address line 7 T S 86 GND GND GND GND 87 A15 A15 A15 A15 I MPC s Address line 15 T S 88 GND GND GND GND 89 A14 A14 A14 A14 I MPC s Address line 14 T S 90 GND GND GND GND 91 A13 A13 A13 A13 I MPC s Address line 13 T S 92 GND GND GND GND 93 A6 A6 A6 A6 I MPC s Address line 6 T S 94 GND GND GND GND 95 A12 A12 A12 A12 I MPC s Address line 12 T S 96 GND GND GND GND 97 A11 A11 A11 A11 I MPC s Address line 11 T S 98 GND GND GND GND 99 A19 A19 A19 A19 I MPC s Address line 19 T S 100 GND GND GND GND 101 A9 A9 A9 A9 I MPC s Address line 9 T S 102 GND GND GND GND 103 A18 A18 A18 A18 I MPC s Address line 18 T S 104 GND GND GND GND 105 A10 A10 A10 A10 I MPC s Address line 10 T S 33 Release 1 0 MPCS 60DB User s Manual Support Information TABLE 5 9 PM1 Interconnect Signals Daughter Pin Board Signal 860 Daughter SOAR Attri SH Daughter Daughter Description No Name Signal Name Sienal Name Sienal Name bute General ena 8 106 GND GND GND GND 107 A17 A17 A17 A17 I MPC s Address line 17 T S 108 GND GND GND GND 109 A16 A16 A16 A16 I MPC s Address line 16 T S 110 GND GND GND GN
75. evice is only for MPC860T and it can be disabled o 5 Dip Switches for the LXT970 power up configuration o Option for Fast Ethernet over Fiber Optics Ethernet 100Base FX with MPC860T only o Selectable KAPWR source 3 3V or externally supplied o Selectable VDDL source 3 3V or 2V o Selectable clock source 32768Hz crystal resonator or 4 MHz Clock generator o On Board Expansion connectors including all MPC pins and MPC8XXFADS control status sig nals o On Board High Density Logic Analyzer connectors supporting fast connection to HP 16500 logic analyzer AMP Mictor A May be easily changed to any 3 3V powered oscillator oscillating in 3 5 MHz frequency range Release 1 0 MPCS860DB User s Manual FIGURE 1 1 MPC860DB Block Diagram Logic Analyzer Conn MOTHER BOARD amp EXPANSION CONN p MPC860 LXT970 RJ45 Connector Fast Ethernet Transceiver Tranceiver CLOCKS fa MPC860T or oo MPCS860SAR or MPC860 Release 1 0 MPCS860DB User s Manual Hardware Preparation and Installation 2 Hardware Preparation and Installation 2e INTRODUCTION This chapter provides unpacking instructions hardware preparation and installation instructions for the MPC860DB Zei UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt request carri er s agent to be present during
76. f them don t Used also as RAS signal for the SDRAM 66 GND GND GND GND 67 BSOA BSOA BSOA BSOA LL Byte Select 0 from UPMA Selects offset 0 Bytes within a word Used as one of the CAS lines for Dram access 68 GND GND GND GND 69 BS3A BS3A BS3A BS3A LL Byte Select 3 from UPMA Selects offset 3 Bytes within a word Used as one of the CAS lines for Dram access 70 GND GND GND GND 71 A31 A31 A31 A31 I MPC s Address line 31 T S 72 GND GND GND GND 73 BS1A BS1A BS1A BS1A I L Byte Select 1 from UPMA Selects offset 1 Bytes within a word Used as one of the CAS lines for Dram access 74 GND GND GND GND 75 TSIZI TSIZI TSIZI TSIZ1 X Transfer Size 1 Used in conjunction with TSIZO to T S indicate the number of bytes remaining in an operand transfer Not used on the FADS 76 GND GND GND GND TI REG A REG A REG A REG A I In fact TSIZO REG Transfer Size 0 or PCMCIA slot A T S REG Used with the PCMCIA port as Attribute L memory select or I O space select 78 GND GND GND GND 79 A30 A30 A30 A30 I MPC s Address line 30 T S 80 GND GND GND GND 81 A21 A21 A21 A21 I MPC s Address line 21 T S 82 GND GND GND GND 32 Release 1 0 MPCS 60DB User s Manual Support Information TABLE 5 9 PM1 Interconnect Signals Daughter Pin Board Signal 860 Daughter 8001 BOUE Attri Daughter Daught
77. fact MPC s chip select line 3 Used as chip select line L for the 2 nd bank of the Dram Simm Pulled up When the Dram is disabled via BCSR or when a single bank Dram Simm is being used may be used off board via the daughter board s expansion connectors 44 GND GND GND GND 30 Release 1 0 MPCS 60DB User s Manual Support Information TABLE 5 9 PM1 Interconnect Signals Daughter Pin Board Signal 860 Daughter SOOSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 45 DRMCS1 DRMCS1 DRMCS1 DRMCS1 I O In fact MPC s chip select line 2 Used as chip select line L for the 1 st bank of the Dram Simm Pulled up When the Dram is disabled via BCSR may be used off board via the daughter board s expansion connectors 46 GND GND GND GND 47 SDRMCS SDRMCS SDRMCS SDRMCS I O In fact MPC s chip select line 4 Used as chip select for L the Synchronous Dram Pulled up When the SDRAM is disabled via BCSR may be used off board via the daughter board 48 GND GND GND GND 49 GPL3 GPL3 GPL3 GPL3 I O UPMA or UPMB general purpose line 3 Used as WR L signal for the SDRAM 50 GND GND GND GND 51 GPL2 GPL2 GPL2 GPL2 LL General Purpose Line 2 for UPMA or UPMB Used with the SDRAM as a CAS signal 52 GND GND GND GND 53 WE3 WE3 WE3 WE3 LL GPCM Write Enable 3 o
78. g3 _LDUI lt ST 170 gu A489 5 58 EM e go al 8 3uvds a auydS OXu STVd vo D 7 BOES be Y0x1 71vd XIHI3 6 3vds Z Xu E1Vd 068081 3 Eld ZITA 01081 LI dd EUXH TIVd Ir nva 91 S d EOXI 0TVd 01 0 LIF 90d D EN Ed 8 L d Bvd 11 0 80d SST VY DUTVTNLL T0988 DI D LVd 60d zou rtl D DERECHITDLAEN Tee 0104 VY DLT1 ZNI1 ZODHS EYN 2 SVd BIN 11d SV wu bia 46 Zita ey eva a FIER Cut BA S orl Sy DSEZWDDSS ELD01 9y3 Zvd jit twr et MIZYODHS LY D 1 tie Ow 96 TIT TSlaS TESd E DOS DOE JDldS 0E8d d DOO D 613 08d A S1S Z4I00N EECH 70004 W N 913 amp 8d Y 0 ERD 7O9UG OSIN 87ZEd m v 30d 71 610 8754 ES Le et 080 VODER VOSIZI LZ8d 17 izga N iv ZODUG TIS IZI 9Z8d lt 911 vu 6171 6 57 qp SEZA MEIER cg Z Bee A zo 9 DOVOS INASIS EZ amp d 77 gt Z gv in BEN DOVOS NASWS ZZ d e EE v zl Save 1311 20 1 15 128 80 v r HIN Kee aloy ty aol LLSTVISLU 618d HIN WNAI 3 SUdISTHA ZISTVZS18 818d 3d 1512 E LIN 6 ddl OSTIA OCH OSTJA ZH Bid 6 5 91 Stad ld EOIHS STId 1150 71 6 0 6 glad 18 x 2 Bin 6 H mn vr n 3 8 F 9 E Son 1581 Eog sJ ud d 5 619 1Sul 08S3 Z14D ae a wo SWL 21298 sg Hr ZS 81D SW Bs Tid9 30 n S4838 0050 001 200029 93 Con ER 2 Abg D 868 wane 10 BS a
79. gnal can be use for LIRCLKB in the 860Sar Phy Board A15 PAIL PAI PAI PAI 1 0 If the 860Sar is used with the 860Sar phy board this signal can be use for AD2 in the 860Sar Phy Board AD2 A16 PAO PAO PAO PAO 1 0 If the 860Sar is used with the 860Sar phy board this LITCLKB signal can be use for LITCLKB in the 860Sar Phy Board A17 VCC VCC VCC VCC 18 PA9 PA9 PA9 PA9 1 0 5 211 LITXDB If the 860Sar is used with the 860Sar phy board this signal can be use for LITXDB in the 860Sar Phy Board 19 LIRXDB LIRXDB LIRXDB LIRXDB I O See PM3 17 If the 860Sar is used with the 860Sar phy board this signal can be use for LIRXDB in the 860Sar Phy Board 63 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 17 P8 Interconnect Signals Daughter 860 860T 860Sar Pin BoardSignal Daughter Daughter Daughter Attrib D No Name BoardSignal BoardSignal BoardSignal ute MEUM General Name Name Name A20 PA9 PA9 PA9 PA9 10 See PM3 21 AD7 If the 860Sar is used with the 860Sar phy board this signal can be use for AD7 in the 860Sar Phy Board A21 LIRXDA LIRXDA LIRXDA LIRXDA 1 0 See PM3 23 AD6 If the 860Sar is used with the 860Sar phy board this signal can be use for AD6 in the 860Sar Phy Board A22 GND GND GND GND A23 GND GND GND GND A24 IRQ7 IRQ7 IRQ7 IRQ7 LL See PM2 130 A25 FRZ FRZ FRZ FRZ I O See PM2 24 A26 ETHE
80. h are controlled via the BCSR4 register The following tables illustrate the LXT970 configuration options TABLE 4 1 MFO MF4 Function Description Pins The following table describe the SW control pins controlled via the BCSR4 register which is on the mother board 17 PIN NAME FUNCTION C A SE A Default MFO Auto negotiation Disable Enable Enable MEI Repiter DTE mode DTE Repeater DTE MF2 Nibble 4B Symbol 5B Nibble 4B Symbol 5B Nibble 4B MF3 Scrambler Operation Enable Disable Enable MF4 Select TX or FX 100TX 100FX 100TX Release 1 0 MPCS 60DB User s Manual Functional Description TABLE 4 2 BCSR4 The control pins for the LXT970 relevant for MPC860T only BIT MNEMONIC FUNCTION FON ATT DEF 4 UUFEN When this signal is active LOW it enable the LXT970 device This signal 1 R W connected to the TRSTE signal of the LXT970 In DTE mode when this pin is high the LXT970 isolate itself from the MII data interface In repeater mode when it is high the LXT970 tri state the MII output pins 5 FETHCFGO Fast Ethernet CFGO signal When the LXT970 is in auto negotiation a low to high 1 R W transition in this pin cause an auto negotiate to re start When the auto negotiation is disabled this input selects operating speed bit 0 13 When this pin is high the 100Mbps is selected 0 13 1 When this pin is low the 10Mbps is selected 0 13 0 6 FETHFDE Full Duplex Enable when
81. he LXT970 is in auto negotiation a low to high transition in this pin cause an auto negotiate to re start When auto negotiation is disabled this input selects operating speed bit 0 13 When this pin is high the 100Mbps is selected 0 13 1 When this pin is low the 10Mbps is selected 0 13 0 33 PB31 PB31 PB31 PB31 I O MPC PI O port B 31 Appears also at P8 but otherwise X unused 34 BINPAK BINPAK BINPAK RxCav IO PCMCIA port Input Port Acknowledge In fact PC15 DREQ1 RTS1 LIST1 When the PCMCIA port is disabled via BCSR1 may be used off board for any alternate function This Signal is used in the 860SAR as a RxCav signal this signal is one of the utopia bus signal 35 PB30 PB30 PB30 PB30 I O MPC PI O port B30 Appears also at P8 but otherwise X unused 36 GND GND GND GND 37 PB29 PB29 PB29 PB29 I O MPC PI O port B 29 Appears also at P8 but otherwise X unused 38 RSTXDI RSTXDI RSTXDI RSTXDI LX RS232 Port 1 Transmit Data When RS232 port 1 is disabled via BCSR1 may be used for any alternate function Appears also at P8 45 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 11 PM3 Interconnect Signals Daughter Pin Board Signal 860 Daughter S007 SOOSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 39 RSRXDI RSRXD
82. m 2 1 E 1 D my ano anro Ano dim ipd ant anrd amu anv Qnid e 0 0 0 9 9 9 9 9 RK CEA 0 A A RO Bl ale ai EM 6 8 E348 anog wc amn o L e mm 7 9 12M9 om a 5 03mg A 8058 EF 7 BEER 1 88 7 VISUS HH 5 z MISE weg a 17 1 2718 ano Ir nf AjquassD jou op suoysisau Bon GD 6 S0180 B gzu H S310H gpg y y 0 70180 m ye eun INN 65 678 NID SE 211088 T 0 emaa gt MTISAS 20 VIELE SCH enwn lt DY 8 y 9 zoen 30003 o L 300038 ZO D 9 0 0 10180 DI 5 5 CR ocd Mu 8 7 EENG Se LS 7 E eoo Hu 952 5 2 989 3 saunas 911 7 SCHUDER 7 z T o zA3H80 CO 5 1 TEU oo gt ISIN 8 SE i or HE ZSI or ZS on stu 508508 D 9 52018 S34 ZL 5 S 48 2 sl S LEE My Er 7 DR 80XITL 7 E 5508 vl 5 z x18 SL a 7 Sig 9TNu Release 1 0 75 MPCS860DB User s Manual Support Information N a Ka SEH E el 5 2 5 ei la s holy amp AB SS gx z zl s dag EXB El SEIS BRIE BE Is EISE 508 3B SEE Eme als ESSE a a Lie zia Ee o e Ko Slr a gt e s la o lt gt gt gt gt lt X gt r A n CC eam ja gt e n en e sss s sh es s 5 alala ale ale elg uas E 2 21255152 1 11 DDR o MR 0501 DSDO
83. may be driven by an external debug JTAG port controller 11 DSDO DSDO DSDO DSDO I DSDO TDO Debug Port Serial Data Output or JTAG port Data Output Used on the FADS as debug port serial data If the ADI bundle is not connected to the FADS may be used by an external debug JTAG port controllers 12 GND GND GND GND 13 14 AT2 AT2 AT2 AT2 IO IP B2 IOISI6 AT2 PCMCIA slot B Input Port 2 or PCMCIA 16 bit I O capability indication or Address Type 2 15 GND GND GND GND 16 VF2 VF2 VF2 VF2 IO IP B3 IWP2 VF2 PCMCIA slot B Input Port 3 or Instruction Watch Point 2 or Visible Instruction Queue Flushes Status 2 17 GND GND GND GND 18 VFO VFO VFO VFO IO IP BA LWPO VFO PCMCIA slot B Input Port 4 or Data Watch Point O or Visible Instruction Queue Flushes Status 0 19 GND GND GND GND 20 21 22 IRQ3 IRQ3 IRQ3 IRQ3 I O IRQ3 CR MPC s interrupt request 3 or Cancel L Reservation Pulled up but otherwise not used on the FADS 23 GND GND GND GND 36 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 10 PM2 Interconnect Signals Daughter Pin Board Signal 860 Daughter ned S0054R Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 24 FRZ FRZ FRZ FRZ LX Freeze IRQ6 MPC debug state indication or Interrupt request line 6 Used
84. mp DSRS 91H 6 e S 10S0 101 Cou een 4 cog LP ya ase E3M8 SY Ses 5 5 8 PEP Sa 30M S658 as 490082 HB aie 228 6 gus Z448 2NURERAS AG zl Xx Hao o 4 ERA 4 x NASQ ts 9V e ae anga 2 5 5 5 29522 222 02 8 13 SAD e ears lt 6 8 FERS TH Duden EF ERE FEF EEEBEEEEEREE F BESS EREP PEE SR EEE EEF E S BERE b e e 7 gem ws rni n E p p min s e a s s s s jo s mam BES am mas FER RRR 2 22 19 9 9 2 9 9 2 2 2 2 2235218 9 35912 393 sl uude Je Sle ur EE SIR SRR SSIS 2 sa fe fe GIS DIS BIS 22 S aed AFP N ke lk ES uz lt slaja X ze E S e rhage HE d ud Release 1 0 72 MPCS860DB User s Manual Support Information
85. o follow the signals from the mother board to the daughter board 27 Release 1 0 MPCS860DB User s Manual Support Information FIGURE 5 1 Motherboard Connectors Mechanical Assembly B PMI e x oo hel eo 17 17 dar 7 as 5 2 46 3 a PM2 4 5 PM3 d EE X 4 5 E 5 5 5 0 75 E d 5 E _v 17 49 5 30 19 lt 4 Y 93 98 The motherboard connectors s signals are described in TABLE 5 9 PMI Interconnect Signals on page 29 TABLE 5 10 PM2 Interconnect Signals on page 28 TABLE 5 11 PM3 Interconnect Signals on page 45 and TABLE 5 A Top View from Component side B All measures are in mm 28 Release 1 0 MPCS860DB User s Manual Support Information 12 PM4 Interconnect Signals on page 54 TABLE 5 13 PX1 PMI Interconnect Signals Differences on page 61 TABLE 5 9 PM1 Interconnect Signals Daughter Pin Board Signal 860 Daughter 8001 60548 Attri Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 1 BB BB BB BB I O MPC s Bus Busy signal Pulled up on the FADS L 2 VCC VCC VCC VCC 3 DRM_W DRM_W DRM_W DRM_W LL MPC s GPLO lines used as R W signal for the DRAM simm or as A10 line for the SDRAM 4 VCC VCC VCC VCC SV Bus 5
86. oducts for any particular purpose nor does Mo any liability arising out of the application or use of any product or circuit and specifically disclaims any and orola assume all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s echnical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola produc s for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorn ey fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola
87. on connectors The BCSR control most of the functions available on the MPC860DB and on the MPC8XXFADS See 4 11 Board Control amp Status Register BCSR on page 45 of MPC8XXFADS User s Manual 18 Release 1 0 MPCS860DB User s Manual Support Information 5 Support Information In this chapter all information needed for support maintenance and connectivity to the MPC860DB is provided Se Interconnect Signals The MPC860DB interconnects with external devices via the following set of connectors 1 Pl P2 P3 PA P5 P6 and P8 Logic Analyzer connectors 2 P9 RJ45 connector for the Fast Ethernet 3 U3 Fiber Optic Tranceiver Connector not mounted on the board 4 PMI PM PM3 and PM4 Mother Board Connectors 5 PX1 PX2 PX3 amp PX4 Expansion Connectors 6 MPCS8XXFADS s P8 Serial Ports Expansion Connector Sele P1 P2 P3 P4 P5 P6 and P8 Logic Analyzer Connectors These connectors are 38 pin receptacle MICTOR connectors made by AMP Each connector connects to a dedicated adaptor for HP 16500 series of logic analyzer which interconnects to two 16 bit pods Since all the signals that appear on these connectors appear also on the mother board connectors and on the expansion connectors they are described there Selelel PI P2 P3 P4 P5 P6 and P8 Signal Names The Logic Analyzer connectors signal names table compose of the motherboard signal name and the MPC relevant special name if there is a special functi
88. on to this pin the special name mentioned in the same MPC column in the table For example for the MPC860SAR PB 16 this pin name is also a PHREQ 0 For MPC860T SPAREA is now MIICOL One column is for the Mother board signal name to make is easy to the user to follow the signals from the mother board to the daughter board A This connector is located on the Mother Board It is documented here since its contents depends on the Daughter Board 19 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 1 P1 Interconnect Signals Mother e MPC860Sar idea Mother MCT MPCS60Sar CS0 Daughter Daughter Daughter Daughter 1 Board Daughter Board Daughter Pin h Board Board Pin j Board f Board Signal 5 Board Signal Signal Board Signal Ame Signal Name Signal Mame Signal None Signal Name Name Name Name 1 N C N C N C N C 2 N C N C N C N C 3 GND GND GND GND 4 N C N C N C N C 5 TS TS TS TS 6 TA TA TA TA 1 TS TS TS TS 8 TA TA TA TA 9 F_CS F_CS F_CS F_CS 10 VFLSO VFLSO VFLSO VFLSO 11 BCSRCS BCSRCS BCSRCS BCSRCS 12 VFLS1 VFLS1 VFLS1 VFLS1 13 DRMCSI DRMCSI DRMCSI DRMCSI 14 ATO ATO ATO ATO 15 DRMCS2 DRMCS2 DRMCS2 DRMCS2 16 ATI ATI ATI AT
89. r PCMCIA WE Selects the LSB within a word for the Flash Simm or qualifies Writes for the PC Card 54 GND GND GND GND 55 WE2 WE2 WE2 WE2 LL GPCM Write Enable 2 or PCMCIA OE Selects the offset 2 Byte within a word for the Flash Simm or open data buffers for read from PC Card 56 GND GND GND GND 57 WEI WEI WEI WEI LL GPCM Write Enablel or PCMCIA I O Write Used to qualify write cycles to the Flash memory and as I O Write for the PCMCIA channel 58 GND GND GND GND 59 BS2A BS2A BS2A BS2A LL Byte Select 2 for UPMA Selects offset 2 bytes within Word Used for Dram access 60 GND GND GND GND 61 WEO0 WEO WEO WEO LL GPCM Write Enable 0 or PCMCIA I O Read Used to qualify write cycles to the Flash memory and as I O Reads from PC Card 62 GND GND GND GND 31 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 9 PM1 Interconnect Signals Daughter Pin Board Signal 860 Daughter S007 SOOSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 63 SPAREI SPAREI MPC spare line 1 Pulled up but otherwise unused on the FADS This signal is used only in MPC860T as a MIICRS signal 64 GND GND GND GND 65 EDOOE EDOOE EDOOE EDOOE LL In fact UPMA or UPMB General Purpose Line 1 Used for Output Enable with EDO Dram simms which have this input most o
90. r is placed between positions 1 2 of J2 the Keep Alive power is fed from the main 3 3V bus When an external power source is to be connected to the Keep Alive power rail it should be connected between positions 2 the positive pole and position 3 GND of J2 A E g a battery 12 Release 1 0 MPCS860DB User s Manual Hardware Preparation and Installation FIGURE 2 5 Keep Alive Power Source Selection J2 J2 33V I x 3 37 7 KAPWR Es KAPWR KAPWR From 3 3V KAPWR From Ext Ext Power Supply Power Supply 2e3e6 LXT970 Power Up HW Configuration The LXT970 can be configure for power up by 9 pins 5 of them are connected to the LXT970 through DS1 DS1 is a 16 pin contain 8 dip switches they are the HW configuration pins The pins MFO MF4 can configure the following options MFO enables the autonegotiation if DS1 1 is OFF it enable the autonegotiation MFI selects DTE or Repeater if DS1 2 is ON it enable the DTE mode MF2 selects symbol 5B or Nibble 4B if DS1 3 is ON Nibble 4B is selected MF3 enables scrambler operation if DS1 4 is ON the scrambler operation is enabled MF4 select the output possibility options twisted pair or the fiber optic MFO MFI MF 3 MF4 DS1 Default Configuration 24 INSTALLATION INSTRUCTIONS The MPC860DB should be plugged into the MPC8XXFADS Mother Board This should be done
91. rd When PORESET is asserted to the MPC the Power On reset configuration is made available to MPC See 4 1 6 1 Power On Reset Configuration on page 29 of MPC8XXFADS User s Manual 4e e2 Hard Reset Hard Reset is generated to the MPC by the following sources 1 TheMAIN power on reset 2 Manual Hard Reset generated on the mother board 3 The debug port Hard reset 4 and by MPC860 s internal sources When the open drain signal Hard Reset is asserted Hard reset configuration is driven on the data bus by logic on the motherboard See 4 1 6 2 Hard Reset Configuration on page 29 on MPC8XXFADS User s Manual 4e e3 Soft Reset Soft Reset is generated to the MPC by the following sources 1 The debug port controller located on the motherboard 2 Manual Soft Reset generated on the motherboard 3 andby MPC internal sources When Soft reset is generated to the MPC Soft Reset configuration is made available to the MPC by logic residing A In fact generated on the daughter board 16 Release 1 0 MPCS860DB User s Manual Functional Description over the motherboard See 4 1 6 3 Soft Reset Configuration on page 29 on MPC8XXFADS User s Manual 4e2 Interrupts Two external interrupts are applied to the MPC via its interrupt controller the ABORT NMI which is generated by a push button amp logic residing over the motherboard and the other is on the IRQ2 which is the interrupt of the LXT970 Fast Ethernet Tranceiver if using a M
92. rnate function 37 GND GND GND GND 37 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 10 PM2 Interconnect Signals Daughter Pin Board Signal 860 Daughter S007 SOOSAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 38 VFLS1 VFLS1 VFLS1 VFLS1 IO IP_BI IWP1 VFLS1 PCMCIA slot B Input Port 1 or Instruction Watchpoint 1 or Visible history Flushes Status 1 Configured as VFLSO May be configured Indicates in conjunction with VFLS1 the number of instructions flushed from the core s history buffer Indicates also whether the MPC is in debug mode If not using the debug port may be configured for alternate function 39 GND GND GND GND 40 41 42 VFI VFI VFI VFI IP_B5 LWP1 VF1 PCMCIA slot B Input Port 5 or Load Store Watch Point 1 or Visible Instruction Queue Flushes Status 1 Configured as VF1 May be configured to any alternate function as no use is done with it on the FADS 43 GND GND GND GND 44 ATI ATI ATI ATI ALE_B DSCK AT1 Address Latch Enable for PCMCIA slot B or Debug Serial Clock or Address Type 1 Configured as ALE_B for all other daughter boards configured as ATI Not used on the FADS May be configured to any alternate function 45 GND GND GND GND 46 ATO ATO ATO ATO I IP_B6 DSDI ATO Input Port B 6 or Debug Serial Data Input or Address Typ
93. ty line 2 or Interrupt Request 5 May generate and receive parity data for D 16 23 bits connected to the DRAM SIMM May not be configured as IRQ5 121 V3 3 V3 3 V3 3 V3 3 122 DPI DPI DPI DPI 1 0 DP1 IRQ4 Data Parity linel or Interrupt Request 4 May generate and receive parity data for D 8 15 bits connected to the DRAM SIMM May not be configured as IRQ4 123 3 V3 3 V3 3 V3 3 124 N C N C N C N C 125 V3 3 V3 3 V3 3 V3 3 42 Release 1 0 MPCS860DB User s Manual Support Information TABLE 5 10 PM2 Interconnect Signals Daughter Pin Board Signal 860 Daughter 001 SOOSAAR Attri uu Daughter Daughter Description No Name Signal Name Sienal N Sienal N bute General ignal Name ignal Name 126 IRQI IRQI IRQI IRQI I O Interrupt Request 1 Pulled up but otherwise not used on L the FADS 127 V33 V3 3 V3 3 V3 3 128 SPARE3 SPARE3 MIITXEN MPC s spare line 3 Pulled up but otherwise unused on the FADS This pin is used in MPC860T only as a MIITXEN signal for the Fast Ethernet 129 V3 3 V3 3 V3 3 V3 3 130 NC NC NC NC 131 V3 3 V3 3 V3 3 V3 3 132 N C N C N C N C 133 V3 3 V3 3 V3 3 V3 3 134 NMI NMI NMI NMI I O Non Makable Interrupt In fact IRQO of the MPC L Driven by on board logic by O D gate Pulled up May be driven off board by O D gate only 135 V3 3 V3 3 V3 3 V3 3 136 N C N C N C N C 137
94. unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are present Save packing material for storing and reshipping of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUIT RY STATIC DISCHARGE CAN DAMAGE CIRCUITS 23 HARDWARE PREPARATION To select the desired configuration and ensure proper operation of the MPC860DB board changes of the jumpers settings may be required before installation The location of the switches LEDs and connectors is illustrated in FIGURE 2 1 MPC860DB Top Side Part Location diagram on page 10 The board has been factory tested and is shipped with Dip Switch settings as described in the following paragraphs Parameters can be changed for the following conditions e Clock generator Power On Reset Source e MPC Keep Alive Power Source e MPC Internal Logic Supply Source LXT970 power up configuration Release 1 0 MPCS860DB User s Manual Hardware Preparation and Installation FIGURE 2 1 MPC860DB Top Side Part Location diagram le GND 3 3V AI P3 ooooooo PX m 6 6 TOO ADDRESS amp STROBES U1 PX3 COMM PORTS DATA amp CONT

MPC860DB & User`s Manual - Freescale Semiconductor

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MPC860DB & User`s Manual - Freescale Semiconductor