Home

Datasheet - Mouser Electronics

1. LVDS panel and backlight inverter LVSAO N LVSAO P LVSBO N 43 3 V 3V3 IO 1V8 REG zjafzjo zo E A z a LVBSO_P rA AA Pann 99lgg 8 8 5 s 8 8 LVSCO_N 3V3 IO o GlGlolm o o o o Dla kB 2 hl aaaa AIAZ 22 EVE y LVSCKO_N c1 I LVSCKO P 2 2 uF T i N N C3 N c4 1V8 REG MAE U1 GO 9 oo oSsss y 3 F pOo w TO w jyspoN 1 En j L LVSDO_P 105 vm I I DP_AUXn 1 LVSAE_N gi Le 4o DP AUXp 5 LVSAE N LVSAE P 22u ap OTHE AT 001 BF 3 LVSAE P LVSBE N LVSBE P DP LOn 5 LVSCE_N LVSCE P 6 a DP Lip LVSCE_N LVSCKE_N LVSCE_P LVSCKE_P DP_Lin 8 BVOCEN 9 PTN3460 LVSCKE_N UON ron 78 NEP el DP HPD 11 DDC SDA 3V3 DEV_CFG 12 EDEN DDC SCL L3 2 3V3_REG 13 tran 2 BKLTEN tB T i DDC_SDA cs c10 w DDC_SCL PWMO T L cn zL Q oy 047 pF Tue 0 01 pF Qotup L mc o Qs5v a T aL TR Een 25V o Q optional EO O option d HPD pull down 2S 8 E 92 amp xS QIS IAS SISIN N 8 DEV CFG 4 R2 5 eDP port or is integrated into 5 TOO PCH port D optional Us ki silicon 400 kQ A 5 open I2C bus slave DP HPD o DP_HPD Q Sof o high address 0COh PON DP LANE1N C15 1j2 04uF DP Lin Blo 98 od L LOW 1 C bus slave 040h E DP LANE1P C16 4442 O1ur DP Ltp O o o 2 2 m O amp l ae zii DP LANEON C17 1412 0 1uF DP LOn AREG Riu o DP LANEOP C1
2. 30 19 2 Definitions is iol DRbreeR eI ere 30 19 3 Disclaimers llle 30 19 4 Trademarks ec RR Rey 31 20 Contact information 31 21 Gorlenls 24 l4 ob e RR eR REESE 32 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP Semiconductors N V 2014 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 12 March 2014 Document identifier PTN3460 Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information NXP PTN3460BS 518 PTN3460BS F1 518 PTN3460BS F2 518 PTN3460BS F3Y PTN3460BS F4Y PTN3460BS F6Y
3. 4 Vaux_pirFp p 2 x lVaux P Vaux nl 5 Common mode voltage is equal to Vpias Tx Or Vpias nx voltage 6 Steady state common mode voltage shift between transmit and receive modes of operation 7 Total drive current of the transmitter when it is shorted to its ground 8 The AUX channel AC coupling capacitor placed both on the DisplayPort source and sink devices PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 22 of 32 NXP Semiconductors PTN3460 12 5 LVDS interface characteristics eDP to LVDS bridge IC Table 20 LVDS interface characteristics Symbol Parameter Conditions Min Typ Max Unit Vo di p peak to peak differential R 100 Q 250 300 350 mV output voltage CFG4 pin is open and LVDS interface control 2 register in default value AV o dit differential output voltage R 100 Q 50 mV variation change in differential output voltage between complementary output states Vom common mode voltage R_ 21000 1 125 1 2 1 375 V los output short circuit current R 1000 24 mA loz OFF state output current output 3 state circuit current 20 uA R 100 9 LVDS outputs are 3 stated receiver biasing at 1 2 V tr rise time Ri 100 Q from 20 96 to 80 96
4. PTN3460 can be powered by either 3 3 V supply only or dual supplies 3 3 V 1 8 V and is available in the HVQFN56 7 mm x 7 mm package with 0 4 mm pitch 2 Features and benefits 2 1 Device features Embedded microcontroller and on chip Non Volatile Memory NVM allow for flexibility in firmware updates LVDS panel power up down sequencing control Firmware controlled panel power up down sequence timing parameters No external timing reference needed EDID ROM emulation to support panels with no EDID ROM Supports EDID structure v1 3 On chip EDID emulation up to seven different EDID data structures B eDP complying PWM signal generation or PWM signal pass through from eDP source NXP Semiconductors PTN3460 eDP to LVDS bridge IC 2 2 DisplayPort receiver features Compliant to DP v1 2 and v1 1a Compliant to eDP v1 2 and v1 1 Supports Main Link operation with 1 or 2 lanes default mode is 2 lane operation Supports Main Link rate Reduced Bit Rate 1 62 Gbit s and High Bit Rate 2 7 Gbit s Supports 1 Mbit s AUX channel Supports Native AUX and I C over AUX transactions Supports down spreading to minimize EMI Integrated 50 termination resistors provide impedance matching on both Main Link lanes and AUX channel High performance Auto Receive Equalization enabling optimal channel compensation device placement flexibility and power saving at CPU GPU Supports eDP authentication options Alternate Scramble
5. eDP to LVDS bridge IC 7 1 PTN3460 Pinning Fig 3 terminal 1 index area LVSCKO P LVSAO N LVSCKO N 44 LVSDO N LVSDO P LVSAE N LVSAE P PTN3460BS LVSBE N LVSBE P Vpp 3V3 LVSCE N LVSCE P LVSCKE N LVSCKE P PVCCEN LVSDE N LVSDE P Transparent top view PWMO 28 1 Center pad is connected to PCB ground plane for electrical grounding and thermal relief Pin configuration for HVQFN56 002aaf833 Refer to Section 13 Package outline for package and pin dimensions All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 5 of 32 NXP Semiconductors PTN3460 Table 2 eDP to LVDS bridge IC 7 2 Pin description Pin description Symbol Pin Type Description DisplayPort interface signals DPO P 4 self biasing Differential signal from DP source DPO P makes a differential pair with DPO N differential input The input to this pin must be AC coupled externally DPO N 5 self biasing Differential signal from DP source DPO_N makes a differential pair with DPO P differential input The input to this pin must be AC coupled externally DP1 P 7 self biasing Differential signal from DP source DP1 P makes a differential pair with DP1_N differential input The input to this pin must be AC couple
6. 3 0 3 3 3 6 V Vpp ive Supply voltage 1 8 V 1 7 1 8 1 9 V Vi input voltage 3 3 V CMOS inputs 0 3 3 3 6 V open drain I O with 0 5 5 5 V respect to ground e g DDC_SCL DDC SDA MS SDA MS SCL Tamb ambient temperature operating in free air 0 70 C PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 19 of 32 NXP Semiconductors PTN3460 eDP to LVDS bridge IC 12 Characteristics 12 1 Device characteristics Table 16 Device characteristics Over operating free air temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Unit tstartup start up time device start up time from power on and 90 ms RST_N HIGH supply voltage within operating range to specified operating characteristics lw rst reset pulse width device is supplied with valid supply voltage 10 us la rst reset delay timel device is supplied with valid supply voltage 90 ms ta pwrsave act delay time from time between PD_N going HIGH and HPD 90 ms power save to active raised HIGH by PTN3460 RST_N is HIGH Device is supplied with valid supply voltage 1 Time for device to be ready after rising edge of RST_N 12 2 Power consumption Table 17 Power consumption At operating free air temperature of 25 C and under nominal supply val
7. DPCD registers e g to facilitate Link training check error conditions etc and 2C over AUX transactions are used to perform any required access to DDC bus e g EDID reads Given that the HPDRX pin is internally connected to GND through an integrated pull down resistor gt 100 kQ the DP source will see HPDRX pin as LOW indicating that the DisplayPort receiver is not ready when the device is not powered This helps avoid raising false events to the source After power up PTN3460 continues to drive HPDRX pin LOW until completion of internal initialization After this PTN3460 generates HPD signal to notify DP source and take corrective action s DP Link PTN3460 is capable of operating either in DP 2 lane or 1 lane mode The default is 2 lane mode of operation in alignment with PTN3460 DCPD register 00002h MAX_LANE_COUNT 2 There are two ways to enable 1 lane operation in an application Connect both DP lanes of PTN3460 to the DP source This enables the DP source to decide use only required number of lanes based on display resolution Connect only 1 lane DPO P DPO N to DP source and modify the DPCD register 00002h MAX LANE COUNT to 1 through NXP I C configuration utility to modify the internal configuration table Please consult NXP for more details regarding the Flash over AUX and DOS utilities DPCD registers DPCD registers are described in VESA DisplayPort v1 1a 1 2 specifications in detail and PTN3
8. Human Body Model HBR High Bit Rate 2 7 Gbit s of DisplayPort specification HPD Hot Plug Detect signal of DisplayPort or LVDS interface VO Input Output I2C bus Inter Integrated Circuit bus IC Integrated Circuit LVDS Low Voltage Differential Signaling NVM Non Volatile Memory PCB Printed Circuit Board POR Power On Reset PWM Pulse Width Modulation or Modulator RBR Reduced Bit Rate 1 62 Gbit s of DisplayPort specification RGB Red Green Blue ROM Read Only Memory Rx Receive SSC Spread Spectrum Clock TCON Timing CONtroller Tx Transmit UI Unit Interval VESA Video Electronics Standards Association All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 28 of 32 NXP Semiconductors PTN3460 17 References eDP to LVDS bridge IC 1 2 3 4 5 6 7 8 9 10 11 UM10492 PTN3460 eDP to LVDS bridge IC application board user manual 2011 AN11088 PTN3460 system design and PCB layout guidelines 2011 AN11128 PTN3460 programming guide 2011 AN11133 PTN3460 FoA Flash over AUX utility user s guide 2011 AN11134 PTN3460 DPCD utility user s guide 2011 VESA DisplayPort standard version 1 revision 1a January 11 2008 VESA DisplayPort standard version 1 revision 2 January 5 2010 VESA embedded DisplayPort standard versio
9. Leaded or leadless SMDs which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered Packages with solder balls and some leadless packages which have solder lands underneath the body cannot be wave soldered Also leaded SMDs with leads having a pitch smaller than 0 6 mm cannot be wave soldered due to an increased probability of bridging The reflow soldering process involves applying solder paste to a board followed by component placement and exposure to a temperature profile Leaded packages packages with solder balls and leadless packages are all reflow solderable Key characteristics in both wave and reflow soldering are Board specifications including the board finish solder masks and vias Package footprints including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead free soldering versus SnPb soldering Wave soldering Key characteristics in wave soldering are Process issues such as application of adhesive and flux clinching of leads board transport the solder wave parameters and the time during which components are exposed to the wave e Solder bath specifications including temperature and impurities Reflow soldering Key characteristics in reflow soldering are Lead free versus SnPb soldering note that a lead free reflow process usually leads to higher minimum peak temperatures see Fig
10. conversion and transmits processed stream in LVDS format Refer to Figure 2 Block diagram of PTN3460 The PTN3460 consists of DisplayPort receiver LVDS transmitter System control and operation The following sections describe individual sub systems and their capabilities in more detail DisplayPort receiver PTN3460 implements a DisplayPort receiver consisting of 2 lane Main Link and AUX channel With its advanced signal processing capability it can handle Fast Link training or Full Link training scheme PTN3460 implements a high performance Auto Receive Equalizer and Clock Data Recovery CDR algorithm with which it identifies and selects an optimal operational setting for given channel environment Given that the device is targeted primarily for embedded Display connectivity both Display Authentication and Copy Protection Method 3a Alternate Scrambler Seed Reset and Method 3b Enhanced Framing are supported as per eDP 1 2 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 8 of 32 NXP Semiconductors PTN3460 8 1 2 PTN3460 eDP to LVDS bridge IC The PTN3460 DPCD registers can be accessed by DP source through AUX channel It supports both Native AUX transactions and C over AUX transactions Native AUX transactions are used to access PTN3460 DisplayPort Configuration Data
11. 14 All rights reserved Product data sheet Rev 4 12 March 2014 21 of 32 NXP Semiconductors PTN3460 12 4 DisplayPort AUX characteristics Table 19 DisplayPort AUX characteristics eDP to LVDS bridge IC Symbol Parameter Conditions Min Typ Max Unit Ul unit interval 11 0 4 0 5 0 6 us liit cc cycle to cycle jitter time transmitting device 2 0 04 UI receiving device Il 0 05 UI VAUX_DIFFp p AUX differential peak to peak voltage transmitting device I4 10 39 1 38 V receiving device 14 0 32 1 36 V Raux reRM po AUX CH termination DC resistance informative i 100 2 Q Vaux_pc_cm AUX DC common mode voltage B1 o 2 0 V Vaux TURN cM AUX turnaround common mode voltage e 0 3 V lAUX SHORT AUX short circuit current limit Ul 90 mA Caux AUX AC coupling capacitor 8 75 200 nF 1 Results in the bit rate of 1 Mbit s including the overhead of Manchester II coding 2 Maximum allowable UI variation within a single transaction at connector pins of a transmitting device Equal to 24 ns maximum The transmitting device is a source device for a request transaction and a sink device for a reply transaction 3 Maximum allowable UI variation within a single transaction at connector pins of a receiving device Equal to 30 ns maximum The transmitting device is a source device for a request transaction and a sink device for a reply transaction
12. 3460 in turn reads from the panel EDID ROM and passes back to the source To support seamless functioning of panels without EDID ROM the PTN3460 can be programmed to emulate EDID ROM and delivers internally stored EDID information to the source Given All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 16 of 32 PTN3460 eDP to LVDS bridge IC NXP Semiconductors that EDID is specific to panels PTN3460 enables system integrator to program EDID information into embedded memory through DP AUX and I C bus interfaces The supported EDID ROM emulation size is 896 bytes seven EDID data structures each of 128 bytes 9 Application design in information Figure 5 illustrates PTN3460 usage in a system context The eDP inputs are connected to DP source port on CPU GPU and the LVDS outputs are connected to LVDS panel TCON All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Rev 4 12 March 2014 17 of 32 PTN3460 Product data sheet Jeeus Lep 12npoJd VLO Uo946 N C v ed sjeuirejosip Jea 0 1oefqns s jueuunoop siu ui pepi oid uoneuuojul y ZE JO 8L O09vEN Ld pamasa sjuDu Ily P LOZ AN SIoonpuoorues dXN
13. 390 ps tr fall time R 100 Q from 80 to 20 96 390 ps tsk skew time intra pair skew between differential 50 ps pairs inter pair skew between 2 adjacent 200 ps LVDS channels m modulation index for center spreading minimum modulation depth 0 maximum modulation depth 2 5 fmod modulation frequency center spreading 30 100 kHz 12 6 Control inputs and outputs Table 21 Control input and output characteristics Symbol Parameter Conditions Min Typ Max Unit Signal output pins PVCCEN BKLTEN HPDRX PWMO Vou HIGH level output voltage lou 2 mA 2 4 V VoL LOW level output voltage lo 2 mA 0 4 V Control input pins RST N PD N TESTMODE DEV CFG CFG 4 1 Vin HIGH level input voltage 0 7Vpp 3v3 _ V Vit LOW level input voltage 0 3Vpp avs V Control input pin EPS N Vin HIGH level input voltage 0 7Vpp 3v3 _ V Vit LOW level input voltage 2 0 2Vpp ava V DDC SDA DDC SCL MS SDA MS SCLI Vin HIGH level input voltage 0 7Vpp avs 5 25 V ViL LOW level input voltage 0 3Vpp avs V lo LOW level output current static output VoL 0 4 V 3 0 mA 1 ForDDC SCL DDC SDA MS SCL MS SDA characteristics please refer to UM10204 I C bus specification and user manual Ref 11 PTN3460 All information provided in this document is subject to legal disclaimers Product data sheet Rev 4 12 March 2014 23 of 32 NXP Semiconductors N V 2014
14. 460 supports DPCD version 1 2 PTN3460 configuration registers can be accessed through DP AUX channel from the GPU CPU if required They are defined under vendor specific region starting at base address 0x00510h So any configuration register can be accessed at DPCD address obtained by adding the register offset and base address PTN3460 supports down spreading on DP link and this is reflected in DPCD register MAX DOWNSPREAD at address 0003h Further the DP source could control down spreading and inform PTN3460 via DOWNSPREAD CTRL register at DPCD register 00107h The key aspect is that the system designer must take care that the Input video payload fits well within both DP link bandwidth and LVDS bandwidth for a given pixel frequency SSC depths when clock spreading is enabled Also another aspect for the system designer is to ensure LVDS panel TCONs are capable of handling SSC modulated LVDS signaling All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 9 of 32 NXP Semiconductors PTN3460 eDP to LVDS bridge IC 8 2 LVDS transmitter The LVDS interface can operate either in Single or Dual LVDS Bus mode at pixel clock frequencies over the range of 25 MHz to 112 MHz and color depths of 18 bpp or 24 bpp Each LVDS bus consists of 3 4 differential data pairs and one clock pair PTN3460 can packetize RGB vide
15. 8 1p 2 0 1 uF DP_LOp LL co i _ 2 s CFG4 AUXP C19 up 0 1 uF DP AUXP zc ay OT HF EE IR AUXN C20 12 0 1uF DP AUXN spen ud MU i TESTMODE 4 R5 2 MS SDA 10 KQ a 002aag619 Fig 5 Application diagram 91 eBpuq SAAM oi dde O9VENLd SJOJONPUODIWIIS dXN NXP Semiconductors PTN3460 eDP to LVDS bridge IC 10 Limiting values Table 14 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Vpp supply voltage 11 0 3 44 6 V VI input voltage 3 3 V CMOS inputs 1 0 3 Vpp4 0 5 IV Tstg storage temperature 65 150 C VEsp electrostatic discharge HBM 2 8000 V voltage CDM B 1000 V 1 All voltage values except differential voltages are with respect to network ground terminal 2 Human Body Model ANSI EOS ESD S5 1 1994 standard for ESD sensitivity testing Human Body Model Component level Electrostatic Discharge Association Rome NY USA 8 Charged Device Model ANSI EOS ESD S5 3 1 1999 standard for ESD sensitivity testing Charged Device Model Component level Electrostatic Discharge Association Rome NY USA 11 Recommended operating conditions Table 15 Operating conditions Over operating free air temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Unit Vpp ava supply voltage 3 3 V
16. All rights reserved NXP Semiconductors PTN 3460 eDP to LVDS bridge IC 13 Package outline HVQFNS6 plastic thermal enhanced very thin quad flat package no leads 56 terminals body 7 x 7 x 0 85 mm SOT949 2 D T B A 4 A A i A3 terminal 1 E f index area detail X Y C CIA B A iyice muU y CE En e2 7 ne E A terminal 1 EC index area X 0 5 mm lil lai if Dimensions scale Unt AM A A3 b D D E E e e e L v w y y max 1 00 0 05 0 30 7 1 4 85 7 1 4 05 0 5 mm nom 0 85 0 02 0 2 0 21 7 0 4 70 7 0 390 04 52 52 04 0 1 0 05 0 05 0 1 min 0 80 0 00 0 18 69 455 69 3 75 0 3 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included sot949 2_po Outline References European ond Issue date version IEC JEDEC JEITA projection SOT949 2 MO 220 tI Q 11 09 16 Fig 7 Package outline SOT949 2 HVQFN56 PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 24 of 32 NXP Semiconductors PTN3460 eDP to LVDS bridge IC 14 Packing information Figure 8 is an example of the label that would be placed on the pr
17. IGH Panel power up power down sequence example PTN3460 When working with eDP capable DP sources PTN3460 supports the following for specific sequence refer to Figure 4 After power on startup HPDRX is asserted HIGH DP source will start AUX communication for initialization perform Link Training and starts the video data stream Once presence of video data is detected PTN3460 will assert PVCCEN to HIGH synchronize to video stream output LVDS data and assert rise the Sink status lock as indicated in DPCD register 0x00205h PTN3460 will wait for Backlight enabling delay T3 to avoid visual artifacts and program the BKLTEN HIGH While transitioning out of Active state by receiving DPCD 0x600 to set PTN3460 in D3 mode PTN3460 will disable BKLTEN prior to cutting off Video streaming to avoid visible artifacts following specific panel specifications PTN3460 will assert PVCCEN to LOW after T5 delay as long as either if the video stream is stopped or video synchronization is lost This is to avoid driving the LVDS panel with illegal stream for long periods of time It is good practice for sources to keep video data or at least DP idle stream active during T4 T5 When PTN3460 is in Low power state DisplayPort D3 power state the LVDS differential I Os are weakly pulled down to 0 V In this state PVCCEN and BKLTEN are pulled LOW e When PD N is LOW which sets PTN3460 in Deep power saving state the BKLTEN pin is set to
18. LOW LVDS differential I Os are pulled LOW via the weak pull downs All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 15 of 32 NXP Semiconductors PTN3460 8 3 4 8 3 5 8 3 6 8 3 7 8 3 8 8 3 9 PTN3460 eDP to LVDS bridge IC Termination resistors The device provides integrated and calibrated 50 Q termination resistors on both DisplayPort Main Link lanes and AUX channel Reference clock input PTN3460 does not require an external clock It relies fully on the clock derived internally from incoming DP stream or on chip clock generator Power supply PTN3460 can be flexibly supplied with either 3 3 V supply only or dual supplies 3 3 V 1 8 V When supplied with 3 3 V supply only the integrated regulator is used to generate 1 8 V for internal circuit operation In this case the EPS_N pin must be pulled HIGH or left open For optimal power consumption dual supply option 3 3 V and 1 8 V is recommended Power management In tune with the system application needs PTN3460 implements aggressive techniques to support system power management and conservation The device can exist in one of the three different states as described below Active state when the device is fully operational Low power state when DP source issues AUX SET POWER command on DPCD register 00600h In this state AU
19. N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 2 of 32 NXP Semiconductors PTN3460 2 5 General eDP to LVDS bridge IC B Power supply with on chip regulator 3 3 V 10 integrated regulator switched on 3 3 V 1095 1 8 V 5 96 integrated regulator switched off B ESD 8kV HBM 1 kV CDM Operating temperature range 0 C to 70 C B HVQFN56 package 7 mm x 7 mm 0 4 mm pitch exposed center pad for thermal relief and electrical ground 3 Applications E AIO platforms W Notebook platforms B Netbooks net tops 4 System context diagram 5 Figure 1 illustrates the PTN3460 usage CPU GPU CHIP SET notebook or AIO platform PTN3460 DP to LVDS gt LVDS PANEL BRIDGE MOTHERBOARD 002aaf831 Fig 1 PTN3460 context diagram Ordering information Table 1 Ordering information no leads 56 terminals body 7 x 7 x 0 85 mml 0 4 mm pitch Type number Topside mark Package Name Description Version PTN3460BS Fxl 2 PTN3460BSS HVQFN56 plastic thermal enhanced very thin quad flat package SOT949 2 1 2 3 PTN3460BS Fx is firmware specific where the x indicates the firmware version Notes on firmware and marking a Firmware versions are not necessarily backwards compatible b Box reel labels will indicate the firmware version via the orderable part number for example labeling w
20. PTN3460 eDP to LVDS bridge IC Rev 4 12 March 2014 Product data sheet 1 General description PTN3460 is an embedded DisplayPort to LVDS bridge device that enables connectivity between an embedded DisplayPort eDP source and LVDS display panel It processes the incoming DisplayPort DP stream performs DP to LVDS protocol conversion and transmits processed stream in LVDS format PTN3460 has two high speed ports Receive port facing DP Source for example CPU GPU chip set Transmit port facing the LVDS receiver for example LVDS display panel controller The PTN3460 can receive DP stream at link rate 1 62 Gbit s or 2 7 Gbit s and it can support 1 lane or 2 lane DP operation It interacts with DP source via DP Auxiliary AUX channel transactions for DP link training and setup It supports single bus or dual bus LVDS signaling with color depths of 18 bits per pixel or 24 bits per pixel and pixel clock frequency up to 112 MHz The LVDS data packing can be done either in VESA or JEIDA format Also the DP AUX interface transports 2C over AUX commands and support EDID DDC communication with LVDS panel To support panels without EDID ROM the PTN3460 can emulate EDID ROM behavior avoiding specific changes in system video BIOS PTN3460 provides high flexibility to optimally fit under different platform environments It supports three configuration options multi level configuration pins DP AUX interface and I2C bus interface
21. TN3460 implements eDPv1 2 specific DPCD registers that concern panel power backlight and PWM controls and the DP source can issue AUX commands to initiate panel power up down sequence as required Also PTN3460 supports LVDS panel control pins backlight enable panel power enable and PWM that can be set via AUX commands PVCCEN pin the signal output is set based on SET POWER DPCD register 00600h and SET POWER CAPABLE bit of EDP GENERAL CAPABILITY REGISTER 1 DPCD register 00701h and detection and handling of video data stream by PTN3460 BKLTEN pin the signal output is set based on BACKLIGHT PIN ENABLE CAPABLE bit of EDP GENERAL CAPABILITY REGISTER 1 DPCD register 00701h and BACKLIGHT ENABLE bit of EDP DISPLAY CONTROL REGISTER DPCD register 00720h PWMO pin the PWM signal generated by PTN3460 based on controls set in DPCD registers In addition PTN3460 can pass through PWM signal from eDP source as well Please refer to Ref 2 for more information All the panel control enable and signal outputs from PTN3460 are aligned with panel power on sequence timing including LVDS video output generation It is important to note that the Panel power must be delivered by the system platform and it should be gated by PVCCEN signal All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 14 of 32 NXP Sem
22. X and HPD circuits are operational but the main DP Link and LVDS Bus are put to high impedance condition The device will transition back to Active state when the DP source sets the corresponding DPCD register bits to DisplayPort DO Normal Operation mode The 2C bus interface will not be operational in this state Deep power saving state In this state PTN3460 is put to ultra low power condition This is effected when PD N is LOW To get back to Active state PD N must be made HIGH The external interfaces like 12C AUX DP LVDS configuration pins will not be operational Register interface control and programmability PTN3460 has a register interface that can be accessed by CPU GPU or System Controller to choose settings suitably for the System application needs The registers can be read written either via DP AUX or I C bus interface It is left to system integrator choice to use an interface to configure PTN3460 PTN3460 provides greater level of configurability of certain parameters e g LVDS output swing spreading depth etc via registers beyond what is available through pins The register settings override the pin values All registers must be configured during power on initialization after HPDRX is HIGH The registers and bit definitions are described in C bus utility and programming guide for firmware and EDID update Ref 3 EDID handling The DP source issues EDID reads using 2C over AUX transactions and PTN
23. a from the preliminary specification Product short data sheet Production This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 19 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevai
24. achines are initialized and the registers take default values In addition PTN3460 has a dedicated control pin RST_N This serves the same purpose as power on reset but without power cycling of the device platform PTN3460 starts up in a default condition after power on or after RST_N is toggled from LOW to HIGH The configuration pins are sampled at power on or external reset or when returning from Deep Sleep PTN3460 goes into Deep power saving when PD N is LOW This will trigger a power down sequence To leave Deep power saving state the system needs to drive PD N back to HIGH If PD N pin is open the device will not enter Deep power saving state Once the device is in Deep power saving condition the HPDRX pin will go LOW automatically and this can be used by the system to remove the 3 3 V supply if required Remark The device will not respect the Panel power down sequence if PD N is asserted LOW while video is being streamed to the display So the system is not supposed to toggle PD N and RST N pins asynchronously while the LVDS output is streaming video to the display panel but instead follow the panel powering sequence as described in Section 8 3 3 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 13 of 32 NXP Semiconductors PTN3460 eDP to LVDS bridge IC 8 3 2 LVDS panel control PTN3460 P
25. d externally DP1 N 8 self biasing Differential signal from DP source DP1 N makes a differential pair with DP1 P differential input The input to this pin must be AC coupled externally AUX P 2 self biasing Differential signal towards DP source AUX P makes a differential pair with differential I O AUX_N The pin must be AC coupled externally AUX_N 1 self biasing Differential signal towards DP source AUX_N makes a differential pair with differential I O AUX_P The pin must be AC coupled externally HPDRX 11 single ended Hot Plug Detect signal to DP source 3 3 V CMOS output LVDS interface signals LVSAE_P 41 LVDS output Even bus Channel A differential signal to LVDS receiver I VSAE P makes a differential pair with LVSAE_N LVSAE_N 42 LVDS output Even bus Channel A differential signal to LVDS receiver LVSAE_N makes a differential pair with LVSAE_P LVSBE_P 39 LVDS output Even bus Channel B differential signal to LVDS receiver LVSBE_P makes a differential pair with LVSBE_N LVSBE_N 40 LVDS output Even bus Channel B differential signal to LVDS receiver LVSBE_N makes a differential pair with LVSBE_P LVSCE_P 36 LVDS output Even bus Channel C differential signal to LVDS receiver LVSCE_P makes a differential pair with LVSCE_N LVSCE_N 37 LVDS output Even bus Channel C differential signal to LVDS receiver LVSCE_N makes a differential pair with LVSCE P LVSCKE P 34 LVDS clock Eve
26. e options via 1 C bus or AUX interface Please refer to Section 8 3 8 for more details PTN3460 All information provided in this document is subject to legal disclaimers Rev 4 12 March 2014 NXP Semiconductors N V 2014 All rights reserved 12 of 32 Product data sheet NXP Semiconductors PTN3460 eDP to LVDS bridge IC 8 3 System control and operation 8 3 1 PTN3460 With its combination of embedded microcontroller non volatile memory DPCD AUX and I2C bus interfaces PTN3460 delivers significant value for customer applications by providing higher degree of control and programmability By default all user controllable registers can be accessed through DPCD AUX interface This interface is always enabled This AUX interface delivers seamless access of PTN3460 registers to system platform GPU firmware driver Nevertheless use of I2C bus interface for configuring PTN3460 is left to the choice of system integrator DEV CFG pin 12 sets up I C bus configuration mode Pull down resistor to GND PTN3460 operates as I C bus slave low address 0x40h Open PTN3460 operates as I C bus slave high address OxCOh e Pull up resistor to Vpp ava PTN3460 operates as I C bus master capable of reading from external EEPROM Reset power down and power on initialization The device has a built in reset circuitry that generates internal reset signal after power on All the internal registers and state m
27. formation provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 7 of 32 NXP Semiconductors PTN3460 eDP to LVDS bridge IC Table 2 Pin description continued Symbol Pin Type Description MS_SDA 24 open drain 12C 12C bus data signal connection to I2C bus master or slave Pulled up by external data input output resistor MS SCL 25 open drain 12C 2C bus clock signal connection to I C bus master or slave Pulled up by clock input output external resistor n c 55 not connected reserved EPS_N 56 input Can be left open or pulled HIGH for 3 3 V supply only option relying on internal regulator for 1 8 V generation Should be pulled down to GND for dual supply 3 3 V 1 8 V option Supply ground and decoupling Vpp 3v3 13 14 power 3 3 V supply input 38 50 Vpp 1v8 6 45 power 1 8 V supply input Vpp 1v8 19 power 1 8 V regulator supply output n c 15 16 power Not connected GND 3 power Ground GNDREG 17 18 power Ground for regulator GND center power The center pad must be connected to motherboard GND plane for both pad electrical ground and thermal relief 8 Functional description PTN3460 8 1 PTN3460 is an Embedded DisplayPort to LVDS bridge IC that processes the incoming DisplayPort DP stream performs DP to LVDS protocol
28. gate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof PTN3460 All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Cus
29. iconductors PTN3460 eDP to LVDS bridge IC 8 3 3 Panel power sequencing Figure 4 illustrates an example of panel power up power down sequence for PTN3460 Depending on the source behavior and PTN3460 firmware version the powering sequence timing could have some slight differences Fig 4 LCDVCC Pd NN P d LVDS interface videofrom source WEEE c SINK STATUS eDP AUX channel AUX channel operational eDP Main Link display backlight VDD 3V3 T12 gt 500 ms PVCCEN a black video T2 lt 50 ms from PTN3460 x ia T5 lt 50 ms HPDRX video or IDLE stream from DP source ee TT Link Training de valid video data disabled enabled T3 200 ms T4 200 ms to 1000 ms 002aaf839 T2 Time interval between panel power enable signal PVCCEN going HIGH and video data clock driven on LVDS interface T3 Time interval between valid video data clock on LVDS interface and backlight enable signal BKLTEN going HIGH T4 Time interval between backlight enable signal BKLTEN made LOW and stopping of video data clock on LVDS interface T5 Time interval between stopping of video data clock on LVDS interface and panel power enable signal PVCCEN made LOW T12 Time interval for which PVCCEN is held LOW before it can be made H
30. ill indicate PTN3460BS F1 for firmware version 1 A sample label is illustrated in Figure 8 Topside marking is limited to PTN3460BS and will not indicate the firmware version Maximum package height is 1 mm PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 3 of 32 O9vEN Ld Jays Lep 12npoJd VLO Uo946 N C v ed sjeuirejosip Jea 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y pamasa sjuDu II v P LOZ AN SIoronpuoorues dXN c Jor supply PTN3460 RX PHY LVS A D E P ANALOG RX PHY DIGITAL ISOCHRONOUS LINK LVS A DJE_N SUBSYSTEM LVSCKE_P 6 LVDS LVSCKE_N DPO_P DIFF CDR cz DIGITAL PHY DPO_N d RCV s2P oz SUBSYSTEM SUBSYSTEM LVS A DJO P H whe LVS A D O_N ajo Ww LVSCKO P T LVSCKO N o z z cpu DP1 P DIFF CDR Es m DPCD PVCCEN E BPN ROV bal ojz REGISTERS VOLATILE BKLTEN a MEMORY FED PWMO SYSTEM EMULATION CONTROLLER 12c BUS DDC DDC_SCL conor_ irena l eoe sen INTERFACE AUX P CONTROL AUX N HPDRX 002aaf832 EPSN PDN RST_N CFG1 CFG3 DEV CFG MS SDA M TESTMODE CFG2 CFG4 MS_SCL Fig 2 Block diagram of PTN3460 9 uieJDeip yoo g SIOJONPUODIWISS dXN 91 eBpuq SAAM oi dde O9VENLd NXP Semiconductors PTN3460 7 Pinning information
31. input Chip reset pin active LOW internally pulled up The pin is meant to reset the device and all its internal states logic all internal registers are taken to default value after RST_N is applied and made HIGH If RST_N is LOW the device stays in reset condition and for the device to be able to operate RST_N must be HIGH DEV_CFG 12 CMOS I O I C bus address mode selection pin TESTMODE CMOS input If TESTMODE is left open or pulled HIGH CFG 4 1 operate as JTAG pins If TESTMODE is pulled LOW these pins serve as configuration pins CFG1 21 input Behavior defined by TESTMODE pin If TESTMODE is left open or pulled HIGH this pin functions as JTAG TEST CLOCK input If TESTMODE is pulled LOW this pin acts as configuration input CFG2 22 input Behavior defined by TESTMODE pin If TESTMODE is left open or pulled HIGH this pin functions as JTAG MODE SELECT input If TESTMODE is pulled LOW this pin acts as configuration input CFG3 23 input Behavior defined by TESTMODE pin If TESTMODE is left open or pulled HIGH this pin functions as JTAG TEST DATA INPUT If TESTMODE is pulled LOW this pin acts as configuration input CFG4 27 1 0 Behavior defined by TESTMODE pin value If TESTMODE is left open or pulled HIGH this pin functions as JTAG TEST DATA OUTPUT If TESTMODE is pulled LOW this pin acts as configuration input PTN3460 All in
32. istor value in the range of 1 kQ to 10 kQ PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 10 of 32 NXP Semiconductors PTN3460 eDP to LVDS bridge IC The VESA and JEIDA data format definitions are described in Table 7 to Table Table 13 Table 7 LVDS single bus 18 bpp VESA or JEIDA data packing Channel Bit position LVDS odd differential channel A LVDS odd differential channel B LVDS odd differential channel C Table 8 LVDS single bus 24 bpp VESA data packing Channel Bit position LVDS odd differential channel A LVDS odd differential channel B LVDS odd differential channel C LVDS odd differential channel D Table 9 LVDS dual bus 18 bpp Channel LVDS odd differential channel A LVDS odd differential channel B LVDS odd differential channel C LVDS even differential channel A LVDS even differential channel B LVDS even differential channel C Table 10 LVDS dual bus 24 bpp VESA data packing Channel Bit position LVDS odd differential channel A LVDS odd differential channel B LVDS odd differential channel C LVDS odd differential channel D don t care LVDS even differential channel A LVDS even differe
33. l Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 19 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggre
34. l and operation 13 Reset power down and power on initialization 13 LVDS panel control 005 14 Panel power sequencing 15 Termination resistors 04 16 Reference clock input 16 Power supply 200e eee eee 16 Power management 00 16 Register interface control and programmability 16 EDID handling 020s eee 16 Application design in information 17 Limiting values lees 19 Recommended operating conditions 19 Characteristics 200i uc einen ieee wens 20 Device characteristics 20 Power consumption 06 20 DisplayPort receiver characteristics 21 DisplayPort AUX characteristics 22 LVDS interface characteristics 23 Control inputs and outputs 23 Package outline 24 Packing information 25 Soldering of SMD packages 25 Introduction to soldering 25 15 2 Wave and reflow soldering 26 15 3 Wave soldering 2 eee aee 26 15 4 Reflow soldering 20 00 26 16 Abbreviations lsleeess 28 17 References lslleesesees 29 18 Revision history lesse 29 19 Legal information sese 30 19 1 Data sheet statuS
35. lified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b whenever customer uses the product for automotive applications beyond 20 Contact information eDP to LVDS bridge IC NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications Translations A non English translated version of a document is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 19 4 Trademarks Notice All referenced brands product names service name
36. makes a differential pair with LVSCO N LVSCO N 49 LVDS output Odd bus Channel C differential signal to LVDS receiver LI VSCO N makes a differential pair with LVSCO P LVSCKO P 46 LVDS clock Odd bus clock differential signal to LVDS receiver LIVSCKO P makes a output differential pair with LI VSCKO N LVSCKO N 47 LVDS clock Odd bus clock differential signal to LVDS receiver I VSCKO N makes a output differential pair with LI VSCKO P LVSDO P 43 LVDS output Odd bus Channel D differential signal to LVDS receiver LVSDO_P makes a differential pair with LVSDO N LVSDO N 44 LVDS output Odd bus Channel D differential signal to LVDS receiver LVSDO_N makes a differential pair with LVSDO P DDC SDA 30 open drain DDC data signal connection to display panel Pulled up by external termination DDC data I O resistor 5 V tolerant DDC SCL 29 open drain DDC clock signal connection to display panel Pulled up by external termination DDC clock I O resistor 5 V tolerant Panel and backlight interface signals PVCCEN 33 CMOS output Panel power Vcc enable output PWMO 28 CMOS output PWM output signal to display panel BKLTEN 26 CMOS output Backlight enable output Control interface sign als PD_N 10 CMOS input Chip power down input active LOW If PD_N is LOW then the device is in Deep power down completely even if supply rail is ON for the device to be able to operate the PD_N pin must be HIGH RST_N CMOS
37. n 1 2 May 5 2010 VESA embedded DisplayPort standard version 1 1 October 23 2009 ANSI TIA EIA 644 A 2001 Electrical characteristics of Low Voltage Differential Signaling LVDS Interface Circuits approved January 30 2001 UM10204 I C bus specification and user manual NXP Semiconductors 18 Revision history Table 25 Revision history Document ID Release date Data sheet status Change notice Supersedes PTN3460 v 4 20140312 Product data sheet PTN3460 v 3 Modifications Section 8 3 3 Panel power sequencing third paragraph fourth bullet item changed from the BKLTEN and PVCCEN pins are set to LOW to the BKLTEN pin is set to LOW PTN3460 v 3 20140213 Product data sheet PTN3460 v 2 PTN3460 v 2 20130320 Product data sheet PTN3460 v 1 PTN3460 v 1 20120109 Product data sheet PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 29 of 32 NXP Semiconductors PTN3460 19 Legal information eDP to LVDS bridge IC 19 1 Data sheet status Document status I2 Product status Definition Objective short data sheet Development This document contains data from the objective specification for product development Preliminary short data sheet Qualification This document contains dat
38. n bus clock differential signal to LVDS receiver IVSCKE P makes a output differential pair with LVSCKE_N LVSCKE N 35 LVDS clock Even bus clock differential signal to LVDS receiver LVSCKE_N makes a output differential pair with LVSCKE_P LVSDE_P 31 LVDS output Even bus Channel D differential signal to LVDS receiver LVSDE_P makes a differential pair with LVSDE_N LVSDE_N 32 LVDS output Even bus Channel D differential signal to LVDS receiver LVSDE_N makes a differential pair with LVSDE P LVSAO P 53 LVDS output Odd bus Channel A differential signal to LVDS receiver LIVSAO P makes a differential pair with LVSAO N LVSAO N 54 LVDS output Odd bus Channel A differential signal to LVDS receiver LVSAO_N makes a differential pair with LVSAO P LVSBO P 51 LVDS output Odd bus Channel B differential signal to LVDS receiver LIVSBO P makes a differential pair with LVSBO N LVSBO N 52 LVDS output Odd bus Channel B differential signal to LVDS receiver LVSBO_N makes a differential pair with LVSBO P PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 6 of 32 NXP Semiconductors PTN3460 eDP to LVDS bridge IC Table 2 Pin description continued Symbol Pin Type Description LVSCO P 48 LVDS output Odd bus Channel C differential signal to LVDS receiver LVSCO_P
39. ntial channel B LVDS even differential channel C DE LVDS even differential channel D don t care PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 11 of 32 NXP Semiconductors PTN3460 Table 11 eDP to LVDS bridge IC LVDS single bus 24 bpp JEIDA data packing Channel Bit position LVDS odd differential channel A LVDS odd differential channel B LVDS odd differential channel C LVDS odd differential channel D don t care Table 12 LVDS dual bus 18 bpp JEIDA data packing Channel LVDS odd differential channel A LVDS odd differential channel B LVDS odd differential channel C LVDS even differential channel A LVDS even differential channel B LVDS even differential channel C Table 13 LVDS dual bus 24 bpp JEIDA data packing Channel Bit position LVDS odd differential channel A LVDS odd differential channel B LVDS odd differential channel C LVDS odd differential channel D LVDS even differential channel A LVDS even differential channel B LVDS even differential channel C don t care DE LVDS even differential channel D don t care PTN3460 delivers great flexibility by supporting more programmabl
40. o data HSYNC VSYNC DE either in VESA or JEIDA format To enable system EMI reduction the device can be programmed for center spreading of LVDS channel clock outputs The LVDS interface can be flexibly configured using multi level configuration pins CFG1 CFG2 CFG3 CFG4 or via register interface The configuration pins and the corresponding definitions are described in Table 3 through Table 6 Nevertheless as the configuration pins are designed for general purpose their definitions can be modified and they can be used for any other purposes However this can be achieved through firmware upgrade only Table 3 CFG1 configuration options Configuration input setting Number of LVDS links LOW single LVDS bus HIGH dual LVDS bus Table 4 CFG2 configuration options 3 level configuration input setting Data format Number of bits per pixel bpp LOW VESA 24 bpp open JEIDA 24 bpp HIGH JEIDA or VESA 18 bpp Table 5 CFG3 configuration options 3 level configuration input setting LVDS clock frequency spread depth control LOW 0 96 open 1 96 HIGH 0 5 96 1 LVDS center spreading modulation frequency is kept at 32 9 kHz Table 6 CFG4 configuration options 3 level configuration input setting LVDS output swing typical value pull down resistor to GND 250 mV open 300 mV pull up resistor to Vpp ava 400 mV 1 Pull up down res
41. oduct shipment box and the tape reel 002aag652 Fig 8 Packing label example 15 Soldering of SMD packages 15 1 PTN3460 This text provides a very brief insight into a complex technology A more in depth account of soldering ICs can be found in Application Note AN10365 Surface mount reflow soldering description Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards PCBs to form electrical circuits The soldered joint provides both the mechanical and the electrical connection There is no single soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and Surface Mount Devices SMDs are mixed on one printed wiring board however it is not suitable for fine pitch SMDs Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 25 of 32 NXP Semiconductors PTN3460 15 2 15 3 15 4 PTN3460 eDP to LVDS bridge IC Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder The wave soldering process is suitable for the following Through hole components
42. r Seed Reset ASSR and Alternate Framing Supports Fast Link training and Full Link training Supports DisplayPort symbol error rate measurements 2 3 LVDS transmitter features Compatible with ANSI TIA EIA 644 A 2001 standard Supports RGB data packing as per JEIDA and VESA data formats Supports pixel clock frequency from 25 MHz to 112 MHz Supports single LVDS bus operation up to 112 mega pixels per second Supports dual LVDS bus operation up to 224 mega pixels per second Supports color depth options 18 bpp 24 bpp Programmable center spreading of pixel clock frequency to minimize EMI Supports 1920 x 1200 at 60 Hz resolution in dual LVDS bus mode Programmable LVDS signal swing to pre compensate for channel attenuation or allow for power saving Supports PCB routing flexibility by programming for LVDS bus swapping Channel swapping Differential signal pair swapping Supports Data Enable polarity programming DDC control for EDID ROM access I C bus interface up to 400 kbit s 2 4 Control and system features PTN3460 Device programmability Multi level configuration pins enabling wider choice I C bus slave interface supporting Standard mode 100 kbit s and Fast mode 400 kbit s Power management Low power state DP AUX command based Low power mode SET POWER Deep power saving state via a dedicated pin All information provided in this document is subject to legal disclaimers NXP Semiconductors
43. s and trademarks are the property of their respective owners For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 31 of 32 NXP Semiconductors PTN3460 21 Contents eDP to LVDS bridge IC 2 2 1 2 2 2 3 2 4 8 1 8 1 1 8 1 2 8 2 8 3 8 3 1 8 3 2 8 3 3 8 3 4 8 3 5 8 3 6 8 3 7 8 3 8 8 3 9 10 11 12 12 1 12 2 12 3 12 4 12 5 12 6 13 14 15 15 1 General description Lieu 1 Features and benefits 1 Device features llle 1 DisplayPort receiver features 2 LVDS transmitter features 2 Control and system features 2 General 231 op ene t RR Ed MEA 3 Applications leeren 3 System context diagram 3 Ordering information esses 3 Block diagram Le 4 Pinning information lees 5 PIANINO e uve reed eR ERE dere ees 5 Pin description 000000 6 Functional description 8 DisplayPort receiver 00000 8 DP Link ee 9 DPCD registers 0c eee eee eee 9 LVDS transmitter 0 10 System contro
44. se given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 30 of 32 NXP Semiconductors PTN3460 Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qua
45. ted on the packing must be respected at all times Studies have shown that small packages reach higher temperatures during reflow soldering see Figure 9 maximum peak temperature MSL limit damage level temperature minimum peak temperature minimum soldering temperature peak temperature mmm time 001aac844 MSL Moisture Sensitivity Level Fig 9 Temperature profiles for large and small components For further information on temperature profiles refer to Application Note AN10365 Surface mount reflow soldering description NXP Semiconductors N V 2014 All rights reserved 27 of 32 PTN3460 All information provided in this document is subject to legal disclaimers Rev 4 12 March 2014 Product data sheet NXP Semiconductors PTN3460 16 Abbreviations eDP to LVDS bridge IC PTN3460 Table 24 Abbreviations Acronym Description AIO All In One AUX Auxiliary channel BIOS Basic Input Output System bpp bits per pixel CDM Charged Device Model CDR Clock Data Recovery CPU Central Processing Unit DDC Data Display Channel DP DisplayPort DPCD DisplayPort Configuration Data EDID Extended Display Identification Data eDP embedded DisplayPort EMI ElectroMagnetic Interference ESD ElectroStatic Discharge GPU Graphics Processor Unit HBM
46. terval high bit rate 0l j 370 ps 2 7 Gbit s per lane reduced bit rate i 617 ps 1 62 Gbit s per lane AfpowN sPREAD link clock down spreading a0 s 0 5 96 Crx AC coupling capacitor 75 200 nF VRX_DIFFp p differential input peak to peak at receiver package pins voltage high bit rate 1 120 mV 2 7 Gbit s per lane reduced bit rate 8 40 mV 1 62 Gbit s per lane VRx DC CM RX DC common mode voltage Io s 2 0 V IRX SHORT RX short circuit current limit DI 50 mA nx TRACKING Bw jitter tracking bandwidth 6 20 MHz Geg max maximum equalization gain at 1 35 GHz 15 dB 1 Range is nominal 350 ppm DisplayPort channel RX does not require local crystal for channel clock generation 2 Up to 0 5 down spreading is supported Modulation frequency range of 30 kHz to 33 kHz is supported 3 Informative refer to Figure 6 for definition of differential voltage 4 Common mode voltage is equal to Vpias nx voltage b Total drive current of the input bias circuit when it is shorted to its ground 6 Minimum CDR tracking bandwidth at the receiver when the input is repetition of D10 2 symbols without scrambling VD Vom Vp pre emphasis 20Log Vpirr pne VoiFF VDIFF_PRE VDIFF Fig 6 Definition of pre emphasis and differential voltage 002aaf363 PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 20
47. tomers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above tho
48. ue unless otherwise noted Symbol Parameter Conditions Single supply mode Dual supply mode Unit EPS N HIGH EPS N LOW or open Min Typ Max Min Typ Max 430 290 mW pe Pcons power Active mode consumption 1440 x 900 at 60 Hz 24 bits per pixel dual LVDS bus Active mode 1600 x 900 at 60 Hz 24 bits per pixel dual LVDS bus Active mode 1920 x 1200 at 60 Hz 24 bits per pixel dual LVDS bus D3 mode Power saving mode 27 15 mw when PTN3460 is set to Power saving mode via SET_POWER AUX command by eDP source AUX and HPDRX circuitry are only kept active gi 1 448 305 mW E 1 570 380 mW Deep power saving Shutdown mode 5 2 mW when PD N is LOW and the device is supplied with valid supply voltage 1 For Active mode power consumption LVDS output swing of 300 mV is considered PTN3460 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 20 of 32 NXP Semiconductors PTN3460 12 3 DisplayPort receiver characteristics Table 18 DisplayPort receiver main channel characteristics Over operating free air temperature range unless otherwise noted eDP to LVDS bridge IC Symbol Parameter Conditions Min Typ Max Unit UI unit in
49. ure 9 than a SnPb process thus reducing the process window Solder paste printing issues including smearing release and adjusting the process window for a mix of large and small components on one board Reflow temperature profile this profile includes preheat reflow in which the board is heated to the peak temperature and cooling down It is imperative that the peak temperature is high enough for the solder to make reliable solder joints a solder paste characteristic In addition the peak temperature must be low enough that the packages and or boards are not damaged The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 22 and 23 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 4 12 March 2014 26 of 32 NXP Semiconductors PTN3460 Table 22 SnPb eutectic process from J STD 020D eDP to LVDS bridge IC Package thickness mm Package reflow temperature C Volume mm lt 350 2 350 lt 2 5 235 220 22 5 220 220 Table 23 Lead free process from J STD 020D Package thickness mm Package reflow temperature C Volume mm lt 350 350 to 2000 gt 2000 1 6 260 260 260 1 6 to 2 5 260 250 245 gt 2 5 250 245 245 Moisture sensitivity precautions as indica

Datasheet - Mouser Electronics

Contents

Download Pdf Manuals

Related Search

Related Contents