logiREF-VIDEO-ISP-EVK
Contents
1. ccccccseeecceceeeeceeseeeeceeesaeeeceesaeeeeess 7 1 3 2 Develop Standalone and Linux Software no HW Changes cccsececeeceeeeeteeeseeetaeeees 8 1 3 3 Full ISP Customization HW and SW Changes nennnennnsnnnsnnnsrrnnrrrsrrrsrrrerrrerrrerrrerrreene 8 1 4 XILINX DEVELOPMENT SOFTWARE teisiticcse ste ceeaseeancticnusn cate rsaorecn acu ecetassnacedne ne ocetauwuneadnssedcateansuoenenas 8 1 5 ISP DEMO tele 8 2 LOGICBRIGKS IP CORES EEN 9 2 1 ABOUT LOGICBRICKS IP UBA 9 2 2 EVALUATION LOGICBRICKS P ere 10 2 3 LOGICBRICKS IP CORES USED IN THIS DEN 11 2 3 1 logilSP Image Signal Processing ISP Pipeline cccecceececeeeeseeeeeeeeceeeeseeeeeeeeseeeeaes 11 2 3 2 logiCVC ML Compact Multilayer Video Controller 12 2 3 3 logiWIN Versatile Video Input cicicniiccantenusncrscovsaat Sect daandaetianctideatdstndactionctioaatixendantinncttenixeniactire 13 2 3 4 logiCLK Programmable Clock Generator 13 2 4 LOGICBRICKS IP CORES FOR GRAPHICAL USER INTERFACE GUI IMPLEMENTATIONG 14 2 5 COMPLEMENTARY LOGICBRICKS REFERENCE DESIGN FACE TRACKING ssseessoesennnrereennren 15 3 GET AND INSTALL THE REFERENCE DESIGN cc ccccessecsecsecesceseeeeeeeecuscuseeeeeseeenseunsenes 16 3 1 REGISTRATION bpOoCEesg rttr ntete AoAo APE EEEE EEEE RERE PE DEDE EEEEE EEEE nEn A Ennen 16 3 2 INSTALLATION PROCESS aig tees cst dernie E AESA 18 3 2 1 Filesystem permissions of the installed directory Windows Z A 19 3 3 DIREC2. e Main control frame displays the video resolution and video color depth bits per pixel Those three values are determined by the PYTHON 1300 Camera Module and can not be changed e Video ON and OFF buttons turn video input streaming on and off e Checkbox Xylon AWB turns on off Xylon Auto White Balance AWB algorithm in which case the user can not manually program the Color Correction Matrix CCM values e Checkbox Xylon AE turns on off Xylon Auto Exposure AE control The AE algorithm uses image statistic data and calculates the image brightness The calculated image brightness is used by the processor controlled algorithm that calculates sensor gain and exposure values e Target brightness slider The checkbox AE muxt be turned to allow this slider to sets up the AE brightness target value e Check box Sensor AE turns on the PYTHON 1300 Camera Module s built in Auto Exposure Control AEC 8 2 Block Controls Each ISP pipeline block can be independently reset or bypassed User controllable options are briefly described in the following text For more information about the logilSP customization options please refere to the logilSP Users Manual distributed with the IP core 8 2 1 DPC Defective Pixel Correction Block The DPC block menu displays the number of defective pixel candidates and the number of the detected defective pixels Those values are updated every second Demo users can setup the
3. To learn more about the available software support for graphics logicBRICKS IP cores please visit http www logicbricks com logicBRICKS Reference logicBRICKS Design OS IP Core Support aspx logiBITBLT Bit Block Transfer 2D Graphics Accelerator This 2D graphics accelerator soeeds up the most common GUI operations and off loads the processor The logiBITBLT transfers graphics objects from one to another part of system s on screen or off screen video memory and performs different Operations during transfers such as ROP2 raster operations bitmap scaling stretching and flipping Porter amp Duff compositing rules or transparency More info http Awww logicbricks com Products logiBIT BLT aspx Datasheet http www logicbricks com Documentation Datasheets IP logiBITBLT hds paf Copyright Xylon d o o 2014 All Rights Reserved Page 14 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Xulon Designed by XYLON User s Manual December 15 2014 Version v1 00 a logi3D Scalable 3D Graphic Accelerator The oo Scalable 3D Graphics Accelerator IP core is a 3D Graphics Processing Unit GPU IP core developed for embedded systems based on the Xilinx Zyng 7000 All Programmable SoC The IP is designed to support the ZX OpenGL ES 1 1 API specifications a royalty free cross platform API for full function 2D and 3D graphics on embedded systems including consoles phones appliances and vehicles Product
4. etc Add your own or third party IP cores to various combinations of logicBRICKS IP cores 5 2 Memory Layout Reference design s memory layout is shown on the bellow Figure 29 Linux OS 768 MB l logilWIN 928 MB logiCVC layer 0 960 MB A ecv avera Figure 29 logiREF VIDEO ISP EVK Memory Layout Copyright Xylon d o o 2014 All Rights Reserved Page 28 of 38 D logiREF VIDEO ISP EVK mmm g ISP Reference Design Sulon Designed by XYLON User s Manual December 15 2014 Version v1 00 a MB pixels HxV pixels logic VC 768 1024 2048 1920x1080 logiWIN 768 1024 2048 Po es a Table 2 logicBRICKS IP Cores Memory Addressing Top video layer layer 0 is used for camera image refresh while bottom video layer layer 1 is used for GUI logiCVC video Type Layer data Layer memory Double buffer address layer width address offset WA YCbCr 0x3a000000 2048 lines 422 0x3c000000 2048 lines Table 3 logiCVC ML video layer settings 5 2 1 PL clocking Figure 30 explains generation of the required PL clocks 148 5 MHz 100 MHz FCLK_CLKO 100 MHz 150 MHz 120 MHz Figure 30 PL clocks generation using logiCLK The logiCLK IP core is sourced by 100 MHz clock generated in the Zynq 7000 AP SoC Processing System and supplied to the FCLK_CLKO PS output The CLK2_ DRP output clock frequency can be dynamically adjusted during device s operation It is used to generate sou
5. Space Noise Reduction amp Chroma Correction Interpolation Statistics Matrix Correction Conversion Edge Enhancement Resampler YCrCb 422 AXI4 STREAM AXI4 STREAM AXI4 LITE Figure 28 logilSP configuration for reference design The camera supplies the image in the raw Bayer format which is at first converted into the parallel RGB format and further into the AXI4 Stream format as required by the logilSP IP core The logilISP IP core outputs the processed YCbCr 422 formated video through the AX14 Stream interface The video output is converted into a standard parallel interface with sync signals and supplied to the logiWIN frame grabber IP The resolution of the camera image is 1280 x 1024 pixels The logiWIN frame grabber stores the video in video frame buffers implemented in an external DDR3 memory The logiWIN is AXI4 bus protocol compliant and can be easily connected to Zyna 7000 AP SoC memory controller The logiWIN works synchronously with the logiCVC ML Compact Multilayer Video Controller to enable implementation of the triple buffering video storage method that assures a flicker free video output The memory subsystem is an essential part of any video and graphics based system It must ensure enough storage space for video buffers GUI elements and application code as well as a fast interface to assure enough memory bandwidth for a smooth and uninterrupted SoC operation The MicroZed board includes two 16 bit DDR3 memory devices t
6. are FSBL application Standalone Bare Metal SW drivers and logilSP example code and documentation Building logiISP standalone application Runing standalone applications 7 2 Software Instructions Linux Software Xylon provides Linux Framebuffer driver Linux userspace ISP driver and logilSP example Described chapters are e Xylon Linux userspace drivers and libs building e Xylon Linux framebuffer driver e Using the Linux binaries logilSP Copyright Xylon d o o 2014 All Rights Reserved Page 34 of 38 i logiREF VIDEO ISP EVK mm 9 ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 8 LOGIISP DEMO APPLICATION The logilSP demo is the QT application that runs on Linux OS and can be fully controlled by the mouse The demo control box occupies the left part of the application window Figure 36 The video stream in the right part of the application window can be turned on and off by buttons Video ON and Video OFF Image Signal Processing Pipeline demo by Xylon um Rz XILINX ALL PROGRAMMABLE Figure 36 logilSP Demo The Control Box The Control box is divided in 3 parts Main Controls Block Controls and Bypass and Reset All Copyright Xylon d o o 2014 All Rights Reserved Page 35 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual E December 15 2014 Version v1 00 a 8 1 Main Controls
7. chapter 2 5 GET AND INSTALL THE REFERENCE DESIGN Setup the demo hardware paragraph 6 1 Set Up the MicroZed EVK kit for Use with the Precompiled Linux Demo From the SD Card Use the provided Zynq 7000 AP SoC as it is binaries Follow instructions for working with logicBRICKS standalone bare metal or Linux drivers please get the full instructions in the start htm file from your installation root directory Develop software applications prior to the availability of the actual target system Full ISP Customization HW and SW Changes Download and install the logiREF VIDEO ISP EVK reference design chapter 2 5 GET AND INSTALL THE REFERENCE DESIGN Setup the demo hardware paragraph 6 1 Set Up the MicroZed EVK kit for Use with the Precompiled Linux Demo From the SD Card Obtain logicBRICKS evaluation licenses from Xylon chapter 4 GETTING LOGICBRICKS EVALUATION LICENSES Use the provided Zyng 7000 AP SoC to add or remove more logicBRICKS IP cores and or third party IP cores or to change logicBRICKS IP settings through the GUI Implement new Zyng 7000 AP SoC design Develop software by following instructions listed in the start bim file from your installation root directory 1 4 Xilinx Development Software The logiREF VIDEO ISP EVK reference design and Xylon logicBRICKS IP cores are fully compatible with Vivado Design Suite 2014 2 Future design releases shall be synchronized with the newest Xilinx development tools 1 5 ISP Demo Previe
8. s speed grade More info http Avww logicbricks com Products logiCLK aspx Datasheet http www logicbricks com Documentation Datasheets IP logiCLK _hds pdf Copyright Xylon d o o 2014 All Rights Reserved Page 13 of 38 ni logiREF VIDEO ISP EVK mmm g ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 2 4 logicBRICKS IP Cores for Graphical User Interface GUI Implementations Xylon s logicBRICKS library of IP cores optimized for Xilinx All Programmable devices includes several graphics logicBRICKS IP cores for full range implementation of 2D and 3D Graphics Processing Units GPU on Xilinx Zynq 7000 All Programmable SoC and FPGAs Xylon s graphics logicBRICKS IP cores can be quickly combined with the video processing IP cores when it is necessary to support complex GUI interfaces Graphics logicBRICKS IP cores are well supported by Xylon provided software drivers for the most popular operating systems Linux Android QNX and Microsoft Windows Embedded Compact A number of Xilinx partners who provide BSPs Board Support Package for different operating systems support Xylon logicBRICKS IP cores for graphics Figure 7 Screenshots from Some Demos Provided with the Reference Designs logiREF ZGPU ZED logiREF ZGPU ZC702 and logiREF ZGPU ZC706 To get Xylon free GUI reference designs please visit htto www logicbricks com logicBRICKS Reference logicBRICKS Design aspx
9. 014 Version v1 00 a The Figure 5 shows imported logicBRICKS IP cores into Vivado Design Suite while the Figure 6 shows a typical logicBRICKS IP core s configuration GUI E e iF Re customize IP Image Signal Processing Pipeline 1 1 d a Documentation CC IP Location Show disabled ports IP License Type Source General Input Output DPC CFA STATS CCM GAMMA RGB2YCC ENHANCE MANR Enable Color Correction Matrix Coefficient Matrix Range 8 0 8 0 K11 1 0 K12 0 0 K13 0 0 K21 0 0 K22 1 0 K23 0 0 K31 0 0 K32 0 0 K33 1 0 Offsets Red Offset 0 255 255 Green Offset 0 255 255 Blue Offset 0 255 255 Output Clamping and Clipping Clamping Value 0 0 255 Clipping Value 255 0 255 J Readable Block Specific Registers Figure 6 Example of logicBRICKS IP Configuration GUI Click on the Documentation icon in the GUI opens the User s Manual of the logicBRICKS IP core 2 2 Evaluation logicBRICKS IP Cores Xylon offers free evaluation logicBRICKS IP cores which enable full hardware evaluation Imported into the Xilinx ISE Platform Studio XPS and or Vivado IP Integrator IPI P parameterization through the tool GUI interface Bitstream generation lf you need to simulate logicBRICKS IP cores please contact Xylon The logicBRICKS evaluation IP cores are run time limited and cease to function after some time Proper operation can be restored by relo
10. 2 of 38 D logiREF VIDEO ISP EVK mmm g ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a Figure 34 The MicroZed Board Plugged In the Figure 35 The PYTHON 1300 Camera Module Carrier Card Plugged In the Carrier Card 6 2 Running the Precompiled Demo from the SD Card Image To quickly start the precompiled ISP demo make sure that you have the SD card with the precompiled image plugged in the board s slot and all jumpers setup as described in the previous paragraph Connect USB mouse to the J1 connector on the MicroZed board It is used for interaction with logilSP demo application Power up the board After some time cca 30s logilSP demo Qt application will automatically start Instructions how to use demo can be found in chapter 8 Copyright Xylon d o o 2014 All Rights Reserved Page 33 of 38 logiREF VIDEO ISP EVK mmm 3 ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 7 SOFTWARE DOCUMENTATION Please use the start htm1 file which is located in your logiREF VIDEO ISP EVK installation directory or open directly software readme htm1 file to find relevant documentation for using logiREF VIDEO ISP EVK software deliverables This file contains links to software documents and instructions related to e Standalone Bare Metal software e Linux software 7 1 Software Instructions Standalone Software Described chapters
11. 24 Step 3 Licensing logicBRICKS Evaluation IP Cores Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS gS Se CSC Obtain Evaluation License Change Password Sao Xylon logicBRICKS da Graphics for Xilinx Zynq 7000 AAT lt Click to get reference designs for Xilinx ZC702 Evaluation Board S 4 Request Eval IP Core IP Core Activation Create Case Subscribe to Newsletter Downloads License key will be created and send to your e mail address Figure 25 Step 3 Confirmation Message Step 4 You will get an e mail with the license key file and full instructions for setting up the license key and downloading the logicBRICKS IP core Please follow the provided instructions From Xylon License Key Generator Sent 6 9 2012 17 47 To Cc Subject Xylon Core License Delivery 1D 03512090617423596 Attachments 03512090617423596_ip_xap_349logicvcml_eval_flexim lic 568 B Tam THIS IS AN AUTOMATICALLY GENERATED EMAIL Please do not reply to this message Designed by XYLON All requests for support should be directed You can download the evaluation IP core deliv jrables here o ere You will need your login email and password for access to Xylonjweb download area This email contains the license s for the core s you requested It enables you tg use the core s at the level authorized by the License Type indicated in the ta
12. Figure 31 PL clocks generation using Clock Wizard 5 3 Restoring Full SoC Design from Xylon Deliverables Xylon provides all necessary design files and TCL scripts to enable full Vivado Design Suite 2014 2 project restore Full guidelines can be found in the vivado create project html1 file The hp433ab xpr file from your installation directory is the Vivado Design Suite project file that opens the project Open this file with the Vivado and explore the design Figure 32 In order to re implement or change the provided reference design please go to Xylon s web site www logicbricks com and acquire evaluation licenses for the logicBRICKS IP cores see chapter 4 GETTING LOGICBRICKS EVALUATION LICENSES Copyright Xylon d o o 2014 All Rights Reserved Page 30 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Xulon Designed by XYLON User s Manual December 15 2014 Version v1 00 a L keet i i wE E 1 Fees Seng Heel Figure 32 Vivado Block Design Diagram logiREF VIDEO ISP EVK Project To access logicBRICKS IP cores user s manuals double click on the specific IP core s to open the GUI and click on the Documentation icon to open the document logicBRICKS User s Manuals contain all necessary information about the IP cores features architecture registers modes of operation etc Copyright Xylon d o o 2014 All Rights Reserved Page 31 of 38 th logiREF VIDEO IS
13. LKO PL Clocking signals VITA Receiver Clock wizard FCLK_CLK1 from Avnet MIXED 3RD PARTY Figure 27 logiREF VIDEO ISP EVK Reference SoC Block Diagram The VITA Receiver IP core from Avnet Electronics Marketing receives the video data from the ON Semiconductor PYTHON 1300 camera module LVDS data and provides parallel RGB video data and video sync signals at its outputs The logilSP Image Signal Processing Pipeline IP core accepts the VITA Receiver sourced parallel RGB video converted into the streaming AXl4 Stream video input by an auxiliary Xilinx s Parallel to Copyright Xylon d o o 2014 All Rights Reserved Page 26 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Alen Designed by XYLON User s Manual VW December 15 2014 Version v1 00 a AxX1 4 Stream converter IP core The logilSP pipeline outputs the quality enhanced AXI4 Stream formatted streaming video which is converted to the parallel RGB format prior to entering the logiWIN Versatile Video Input frame grabbing IP core Demo users can evaluate different logilSP IP core s hardware configurations and re programm the setup IP configuration through the provided Xylon GUI demo application In this referent design the logilSP IP core is configured to include the following image processing modules shown on the below Figure 28 logilSP Image Signal Processing Pipeline 1080p60 Defective Pixel Color Filter Array Image Color Correction Gamma Color
14. P EVK mmm ISP Reference Design Designed by XYLON User s Manual Sulon December 15 2014 Version v1 00 a 6 QUICK START 6 1 Set Up the MicroZed EVK kit for Use with the Precompiled Linux Demo From the SD Card Xylon provides the demo binaries in the software ready for download linux_ sd directory of the delivery In order to quickly run the precompiled Xylon demo please copy the contents of the linux sd directory to the root directory on the FAT32 formatted SD card and use it with the hardware kit Note there should be no linux sad directory on the SD card but only the contents of that directory Set up your MicroZed Embedded Vision Kit as follows Plug the programmed SD card into the micro SD card connector J6 on the MicroZed board Select the MicroZed configuration mode by setting up JP1 JP3 jumpers as shown on Figure 33 The presented setup selects the SD card as the boot device Plug the MicroZed board into the Carrier Card board as shown on Figure 34 Attach the On Semiconductor PYTHON 1300 camera module to the MicroZed Carrier Card as shown on Figure 35 Connect the Full HD 1920x1080 PC monitor and the Carrier Card HDMI OUT CONS by the micro HDMI to HDMI video cable Connect the USB mouse to the MicroZed USB connector J1 Connect the 5VDC power supply to the Carrier Card to connector CON8 Figure 33 The MicroZed Board Jumpers Settings Copyright Xylon d o o 2014 All Rights Reserved Page 3
15. PU ZED_120919 ang Designed by XYLON Ei By clicking Next you are accepting the following XYLON EVALUATION SEAT LICENSE AGREEMENT XESLA IMPORTANT UNLESS SUPERSEDED BY A SIGNED LICENSE AGREEMENT BETWEEN YOU AND XYLON THIS XYLON EVALUATION SEAT LICENSE AGREEMENT XESLA IS A LEGAL AGREEMENT BETWEEN YOU AND XYLON doo PROVIDING YOU WITH THE LICENSE TO USE THE LICENSED MATERIALS UNDER THE TERMS AND CONDITIONS OF THIS AGREEMENT CAREFULLY READ THIS LICENSE AGREEMENT AGREEMENT BY CLICKING THE ACCEPT OR AGREE BUTTON OR OTHERWISE ACCESSING DOWNLOADING INSTALLING OR USING THE LICENSED MATERIALS YOU AGREE ON BEHALF OF LICENSEE TO BE BOUND BY THIS AGREEMENT LICENSEE OR YOU MEANS THE CORPORATION OR OTHER LEGAL ENTITY TO WHICH XYLON doo A CROATIAN CORPORATION WITH AN OFFICE AT FALLEROVO SETALISTE 22 10000 ZAGREB REPUBLIC OF CROATIA XYLON HAS ISSUED THE LICENSE DESCRIBED HEREIN IF YOU DO NOT AGREE TO ALL OF THE TERMS AND CONDITIONS OF THIS AGREEMENT DO NOT CLICK THE ACCEPT OR AGREE BUTTON AND DO NOT ACCESS DOWNLOAD INSTALL OR USE THE LICENSED MATERIALS AS USED HEREIN THE EFFECTIVE DATE MEANS THE DATE ON WHICH LICENSEE CLICKS THE ACCEPT OR AGREE BUTTON IDENTIFIED ABOVE PURCHASES OR OTHERWISE ACCESSES DOWNLOADS INSTALLS OR USES THE LICENSED MATERIALS WHICHEVER OCCURS FIRST 1 Definitions Licensed Materials means the Xylon design files also r
16. SP EVK Reference Design Copyright Xylon d o o 2014 All Rights Reserved Page 22 of 38 m logiREF VIDEO ISP EVK mmm ISP Reference Design Sulon Designed by XYLON User s Manual December 15 2014 Version v1 00 a 4 GETTING LOGICBRICKS EVALUATION LICENSES Please note that the logiREF VIDEO ISP EVK reference design installation provides you with everything needed to run the provided demo applications or to use change the provided software source code However if you wish to make any changes on the hardware design files such as to remove add or reconfigure some of the provided IP cores you have to obtain evaluation IP licenses from Xylon The following pages describe the procedure for getting and licensing evaluation logicBRICKS IP cores that takes several minutes to complete If you experience any troubles during this process please contact Xylon Technical Support Service support logicbricks com You must be logged in to the Xylon website using your logicBRICKS user name and password to get an access to evaluation logicBRICKS IP cores Unregistered users will be re directed to the User Login page Paragraph 3 1 Registration Process explains this simple registration procedure Step 1 Logged in users get the My logicBRICKS tab in the main www logicbricks com navigation menu Click on it and you will be directed to your main web page for communication with Xylon logicBRICKS Figure 20 Please select the Request E
17. TORY STRUCTURE E 21 GETTING LOGICBRICKS EVALUATION LICENSES cccccceececcecceceeceecescueceseeseeeeeeeeeuseeees 23 5 LOGIREF VIDEO ISP EVK DESIGN ccccccecceceeceeceececceeeeseeceeeescuseuseuseseseuseuseuseueeeeeseuseuseuees 26 5 1 DESIGN CUSTOMIZATION cccececceceececeeceececeececeececeeceeeeseeeeceeseceeseeaeseeaeseeaeseenecseneeeneseenenaeseees 28 5 2 MEMORY LAYOUT WE 28 AF gd ek 616 lt 1 0 ee a A E ee E A eee 29 5 3 RESTORING FULL SOC DESIGN FROM XYLON DELIVERABLES s seseseenenonnnorrrrrrrrrrrrrrrrrrrrrrrnn 30 6 QUICK SUP EE 32 6 1 SET UP THE MICROZED EVK KIT FOR USE WITH THE PRECOMPILED LINUX DEMO FROM THE SD CARD 32 6 2 RUNNING THE PRECOMPILED DEMO FROM THE SD CApplMAGE 33 7 SOFTWARE DOCUMENTATION cccccccceceececcecceceeceecescuseuseuseeseseuseuseuseeeeseeseuseuseuseeseseuseuseuees 34 7 1 SOFTWARE INSTRUCTIONS STANDALONE SOFTWARE cccccccsceeee eee e ee eeeeeeeesseaaaaeeeeeeeeeeees 34 7 2 SOFTWARE INSTRUCTIONS LINUX SOF TW TT 34 8 LOGISP DEMO APPLICATION paces seccccceseaverdescsecercdenssecseuvcecetsensevesdsseccecdersovaddsseceecdeaseeaseesecceste 35 8 1 MAINC ONTROL earr EEEE E EAE EAEE EE E 36 8 2 Z belei e eie ug ie 36 8 2 1 DPC Defective Pixel Correction Block 36 8 2 2 CFA Color Filter Array Interpolation Block 36 oe ane Moy Ade En E le de 0 6 E 36 Copyright Xylon d o o 2014 All Rights Reserved Page 3 of 38 rh logiREF VIDEO ISP EVK mmm ISP Ref
18. Xylon technical support if you have active IP core or HW platform development license Create Case Subscribe to Newsletter Subscribe or unsubscribe to Xylon s newsletters Figure 20 Step 1 My logicBRICKS Navigation Page Step 2 Select the evaluation logicBRICKS IP core and click on Obtain evaluation license key link Figure 21 If you are entitled to get the evaluation logicBRICKS IP core you will be immediately asked Figure 24 your Ethernet MAC ID number or Sun Host ID as described in the Step 3 If the evaluation logicBRICKS IP cores list looks differently from the one shown on Figure 21 for example as the list presented by the Figure 22 please fill in and submit the request form Figure 23 and allow us some time to process your request Scroll down to get to the request form For instructions how to find your Ethernet MAC or host ID please visit http www logicbricks com Documentation Article aspx articlelID KBA 01186 MOJXKD Copyright Xylon d o o 2014 All Rights Reserved Page 23 of 38 logiREF VIDEO ISP EVK ISP Reference Design User s Manual mm Designed by XYLON December 15 2014 Sulon Version v1 00 a Home About us Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS Evaluation License View Data Change Password Xylon logicBRICKS d Graphics for Xilinx Zynq 7000 WH J Click to get referen
19. ading the bitstream Besides this run time limitation there are no other functional differences between the evaluation and fully licensed logicBRICKS IP cores Evaluation logicBRICKS IP cores are distributed as parts of the Xylon reference designs http Awww logicbricks com logicBRICKS Reference logicBRICKS Design aspx Specific IP cores can be downloaded from Xylon s web shop http www logicbricks com Products IP Cores aspx Copyright Xylon d o o 2014 All Rights Reserved Page 10 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 2 3 logicBRICKS IP Cores Used in This Design 2 3 1 logilSP Image Signal Processing ISP Pipeline The logilSP Image Signal Processing Pipeline IP core is a full high definition ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx Zynq 7000 All Programmable SoC and 7 Series FPGA devices Supports Xilinx Zyng 7000 AP SoC and 7 Series FPGA Complete and configurable ISP pipeline includes Defective Pixel Correction Color Filter Array Interpolation Image Statistics AWB amp AE Support Color Correction Matrix Gamma Corrections Image Enhancement Motion Adaptive Noise Reduction YCbCr to RGB Color Space Converter RGB to YCbCr Color Space Converter Chroma Resampler Digitally processes and enhances the quality
20. be now 7 r H D Si ac facial for Xilinx Zyng 7000 ean res Figure 8 Screenshot from the Xylon Face Tracking Demo Copyright Xylon d o o 2014 All Rights Reserved Page 15 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 3 GET AND INSTALL THE REFERENCE DESIGN Xylon offers several logicBRICKS reference designs for different hardware platforms Short descriptions of all Xylon logicBRICKS reference designs can be found at htto www logicbricks com logicBRICKS Reference logicBRICKS Design aspx A quick access to specific reference design is also possible through the main downloads navigation page http www logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Reference Desiqns Navigation Page aspx Only registered logicBRICKS users can download logicBRICKS reference designs Unregistered users will be re directed to the User Login page The download link is automatically sent by an e mail which means that the registration process requires access to the e mail account Xylon reference logicBRICKS designs can be downloaded as cross platform Java JAR self extracting installers For quick registration and other general instructions please visit http www logicbricks com logicBRICKS logicBRICKS Quick Info aspx 3 1 Registration Process Registration is very quick and simple If you experience any troubles durin
21. ble at the bottom of this page A full license allows you to use the core in Full Access mode yal IP download link NOTE A full license means that purchased or evaluation IP core can be fully implemented into the Xilinx FPGA The IP core licenses are attached to this e mail 03512090617423596_ip_xap_349logicvcml_eval_flexim lic NOTE You can alternatively download the license archive by clicking here You must access this downloads evaluation license by September 13 2012 After this date the license archive will be removed from the website Figure 26 Step 4 E mail with logicBRICKS License and Download Instructions Copyright Xylon d o o 2014 All Rights Reserved Page 25 of 38 i logiREF VIDEO ISP EVK mmm 9 ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 5 LOGIREF VIDEO ISP EVK DESIGN Figure 27 shows the simplified block diagram of the logiREF VIDEO ISP EVK reference design Design clocking structures are not shown in detail Please read the chapter 5 2 1 PL Clocking and explore the design files to understand the clocking structure GigE Flash QSPI UART SPI DISPLAY CAN 12C Q PETT GPIO Xilinx Zynq Z 7020 Programmable Logic Z 7020 Processing System e AX 4 Lite ADV7511 logiCVC ML logilSP AXI4 Stream to logiWIN Video ayj4 ISP Pipeline parallel Frame Grabber Parallel to AX 4 Stream Processing system 7 logiCLK FCLK_C
22. can be licensed from Xylon ot image Signal Processing Pipeline demo by Xylon A ALL PROGRAMMABLE Figure 1 Screenshot from the Xylon Image Sensor Processing Pipeline logilSP Demo Figure 2 and Figure 3 illustrate video quality enhancements achievable by the logilSP ISP pipeline IP core Figure 3 shows the logilSP video output after the processing of the low quality video input image shown on Figure 2 This users manual describes Xylon s logiREF VIDEO ISP EVK ISP pipeline reference design for the MicroZed Embedded Vision Development Kit from Avnet Electronics Marketing and the ON Semiconductors PYTHON 1300 1 3 MP video camera This free and pre verified logicBRICKS reference design includes evaluation logicBRICKS IP cores and hardware design files prepared for Xilinx Vivado Design Suite It also includes the complete Linux OS image software drivers demo applications and documentation Copyright Xylon d o o 2014 All Rights Reserved Page 5 of 38 D logiREF VIDEO ISP EVK mm g ISP Reference Design Designed by XYLON User s Manual E December 15 2014 Version v1 00 a The offered evaluation hardware design is customizable logicBRICKS IP cores can be setup through the Vivado IP Integrator IPI and design users can evaluate different logilSP features make changes on the logicBRICKS graphics sub system and add third party IP cores required by the target application Figure 2 Example logilSP Video Input Figur
23. ce designs for Xilinx ZC702 Evaluation Board ay Request Eval IP Core IP Core Activation Create Case Click to get the IP license key Subscribe to Newsletter Name Status Downloads logiCVC ML EVAL 1M Not Activated Obtain evaluation license key logiWIN EVAL 1M Not Activated Obtain evaluation license key logiBITBLT EVAL 1M Not Activated Obtain evaluation license key Figure 21 Step 2 Selecting logicBRICKS IP Core for Licensing Home About us Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS Evaluation License View Data Change Password Xylon logicBRICKS Request Eval IP Core Graphics for Xilinx zynq 7000 IP Core Activation Create Case Subscribe to Newsletter Name Status Downloads logiCVC ML EVAL 1M Activated Already activated IP licenses logiWVIN EVAL 1M logiBITBLT EVAL 1M Activated Activated Figure 22 Step 2 A List of Already Activated logicBRICKS IP Licenses logiJART EVAL 1M Not Activated Obtain evaluation license key Your company can get one evaluation license per product per year If your company already used evaluation license in last year you cannot obtain evaluation license automatically In that case please fill form with request for additional evaluation license Subject logic CM IP Core Evaluation License IP Core logiCVC ML EVAL 1M l Message Text Ps
24. e 3 Example logilSP Video Output 1 1 Hardware Platform The logiREF VIDEO ISP EVK Image Signal Processing ISP Reference Design works with the the MicroZed Embedded Vision Kit from Avnet Electronics Marketing A full evaluation requires the following hardware components MicroZed Embedded Vision Development Kit Part Number AES MBCC EMBV DEV KIT or the equivalent combination built of o MicroZed 7020 SOM Part Number AES Z7MB 7Z020 SOM G o MicroZed Embedded Vision Carrier Card Kit Part Number AES MBCC EMBV G and ON Semiconductor PYTHON 1300 COLOR Camera Part Number AES CAM ON P1300C G Avnet Electronics Marketing part number for more details visit www microzed org Figure 4 Avnet MicroZed Embedded Vision Kit Copyright Xylon d o o 2014 All Rights Reserved Page 6 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual XK ulon December 15 2014 Version v1 00 a 1 2 Design Deliverables 1 2 1 1 3 Hardware Design Files Configuration bitstream file for the programmable logic MicroZed Embedded Vision Kit reference design prepared for Vivado Design Suite Xylon evaluation logicBRICKS IP cores logilSP Image Signal Processing ISP Pipeline logiWIN Versatile Video Input logic VC ML Compact Multilayer Video Controller logiCLK Programmable Clock Generator Avnet IP cores FMC Imageon Vita Receiver Software standalone bare metal driver w
25. eferred to as a core and documentation that is made available to you _ suhiect to the terms of this XESTA z i nen am Figure 14 Installation Process Step er Wl Xylon logiREF ZGPU ZED_120919 fi Designed by XYLON i E Select the installation path DAProg ram Files ixylon ZGPU ZED_120919 tt Previous _ a gt nex _ au_ Figure 16 Installation Process Step 3 8 Xylon logiREF ZGPU ZED_120919 1 uc Sl 5 Designed by XYLON v Installation has completed successfully Figure 18 Installation Process Step 5 Copyright Xylon d o o 2014 All Rights Reserved User s Manual Sulon Version v1 00 a r a Xylon logiREF ZGPU ZED_120919 ang Designed by XYLON E By clicking Next you are accepting the following XYLON SOFTWARE EVALUATION LICENSE AGREEMENT XSWELA IMPORTANT READ BEFORE COPYING INSTALLING OR USING Do not use or load this software and any associated materials collectively the Software until you have carefully read the following terms and conditions By loading or using the Software you agree to the terms of this Agreement If you do not wish to so agree do not install or use the Software LICENSED MATERIALS logi3D LNX software drivers for logi3D for Linux LICENSED PERIOD unlimited LICENSE This Software is licensed fo
26. erence Design Sulon Designed by XYLON User s Manual December 15 2014 Version v1 00 a 8 2 4 CCM Color Correction Matrix Block Ne NNN RRE RENE NENNEN NENNEN NENNEN 36 8 2 5 GAMMA Gamma Correction Block 37 8 2 6 Enhance Image Enhancement Block 37 8 3 BYPASS ALL AND RESET ALL BUTTONS 37 Bisel Bypass ALC BURNOM E 37 SS THESE ALCEO NEE 37 9 REVISION HISTORY EEN 38 Copyright Xylon d o o 2014 All Rights Reserved Page 4 of 38 D logiREF VIDEO ISP EVK mmm g ISP Reference Design Designed by XYLON User s Manual E December 15 2014 Version v1 00 a 1 INTRODUCTION Xylon s logilSP Image Signal Processing ISP Pipeline IP core is a full high definition ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx Zynq 7000 All Programmable SoC and 7 Series FPGA devices The logilSP IP core accepts diversely formatted video inputs generated by different sensors and removes defective pixels de mosaics Bayer encoded video makes image color and gamma corrections filters the noise from the video collects video analytics data for various control algorithms and manipulates video data formats and color domains IP core deliverables include the software driver documentation and technical support The IP core can be used with processor based control algorithms for Auto White Balancing AWB and Auto Exposure AE that
27. figuration uses a separated Gamma LUT for each color 8 2 6 Enhance Image Enhancement Block The Enhance block allows for noise reduction parameter noise threshold and enhance parameters enhance strength and halo suppression setup 8 3 Bypass ALL and Reset ALL buttons 8 3 1 Bypass ALL Button Demo users can bypass all ISP pipeline blocks and then gradually turn them one by one back to evaluate effects on the processed video stream 8 3 2 Reset ALL Button Resets all logilSP blocks to the initial state turns off the Xylon AWB AE algorithms and sets the default AE target value Copyright Xylon d o o 2014 All Rights Reserved Page 37 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 9 REVISION HISTORY Version Dee LC Author Approved by Note December 15 2014 G Galic G Galic Initial a H WE Copyright Xylon doo 2014 All Rights Reserved Page 38 of 38
28. following defective pixel calculation parameters pixel age spatial variance threshold and temporal variance threshold 8 2 2 CFA Color Filter Array Interpolation Block Enables setup of the Bayer filter phase configuration which is specified by the beginning pixel in the top left corner of the Bayer sampling grid Green Red or Blue Pixel 8 2 3 STATS Image Statistic Block The Image Statistic Block cannot be turned off or bypassed This block is here for a future development displaying histograms etc Xylon Auto White Balance AWB and Auto Exposure AE control algorithms use the statistics data collected by this ISP block 8 2 4 CCM Color Correction Matrix Block Demo users can setup the following CCM block parameters the color correction matrix color offsets and clip and clamp values Copyright Xylon d o o 2014 All Rights Reserved Page 36 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a It is not possible to change the CCM matrix values while the AWB algorithm is turned on checked in the Main Controls Xylon AWB does not affect the color offsets clip and clamp values 8 2 5 GAMMA Gamma Correction Block The GAMMA block enables user to set gamma value y for each color The Gamma look up tables LUT values are calculated by the software application and written in the logilSP IP core s LUTs The demonstrated logilSP con
29. g the registration process please contact Xylon Technical Support Service support logicbricks com Copyright Xylon d o o 2014 All Rights Reserved Page 16 of 38 i logiREF VIDEO ISP EVK mmm g ISP Reference Design Designed by XYLON User s Manual Sulon December 15 2014 Version v1 00 a Mos wn K Designed by RYLOM Home Aboutes Products Markets Solutions logicBRICKS Downloads Docemestation Hews amp Events English Home Login About us Products Markets lutions logicBRICKS Downloads D Register get and evaluate logicBRICKS IP cores in just a few clicks News amp tve Gr 9 g gi J d e ANDA For registration and other general instructions please CLICK HERE G Log am ac tand othe servii e mas adcress ve EI infor rin Figure 9 Registration Process Step 1 English mem Register About us LP Xylon logicBRICKS AA ZG Products Graphics tor Xilinx Zynq 7000 e Markets Click to get reference designs for Xilinx ZC 202 Evaluation Board an asterisk 7 OCH and e X eer 00 Solutions logicBRICKS e roquared fieids Downloads Satutabon Documentat ion State Province t Prodects Markets Sotutons jogicBRICKS Downloads Documentation News amp Evests Sg Register Abou E n Jom ie as B Xyton logicBRICKS di f Products Graphics for Xilinx Zynq 7000 S Markets Click to get reference Gesigns for Xilinx 20702 Evaluatio
30. is based on a published Khronos specification and is expected to pass the Khronos Conformance Testing Process Current conformance status can be found at www khronos org conformance 2 5 Complementary logicBRICKS Reference Design Face Tracking The face detection and tracking is a computer technology that uses video images captured by the video camera to determine and track distinctive facial features The technology significantly improves human machine interaction and opens a very wide range of applications such as adriver drowsiness detection in automotive safety systems that prevent accidents speaker detection in video conferencing systems capable to automatically zoom to the current speaker hands free interfacing helping disabled people to improve their daily lives character animations in virtual reality entertainment and gaming health robotics audio processing and others To learn more about this technology and to evaluate Xylon s solution designed for Xilinx All Programmable please check Xylon s free downloadable logiREF FACE TRACK EVK Face Detection and Tracking reference design for the MicroZed Embedded Vision Development Kit from Avnet Electronics Marketing and the ON Semiconductor s PYTHON 1300 1 3 MP video camera htto www logicbricks com logicBRICKS Reference logicBRICKS Design Face Detection for Zyna AP SoC aspx Face Detection and Tracking demo by Xylon logiFDT IP Core Main Features Wi t u 7 ERS g
31. ith the logilSP driver example and Linux user space driver standalone bare metal and Linux user space libraries OSlib Linux Framebuffer driver for the logiGVC ML IP core display controller IP core Binaries Linux binaries containing precompiled SD Card image for the fastest demo startup o logilSPDemoQt logilSP demo application with the GUI designed by the Linux Qt o uboot dtb dts root file system o ulmage kernel with framebuffer driver for logiCVC ML o qt image compressed precompiled Qt application framework Standalone binaries zynq_fsbl logiiSP_demo FPGA bitstream Usage Modes The logiREF VIDEO ISP EVK reference design can be used in different ways which are listed in this paragraph and thoroughly explained through this document 1 3 1 Quick Evaluation with no HW and or SW Changes Download and install the logiREF VIDEO ISP EVK reference design chapter 2 5 GET AND INSTALL THE REFERENCE DESIGN Setup the demo hardware and use the provided SD card image to run precompiled demo applications paragraph 6 1 Set Up the MicroZed EVK kit for Use with the Precompiled Linux Demo From the SD Card Copyright Xylon d o o 2014 All Rights Reserved Page 7 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual Sulon December 15 2014 Version v1 00 a 1 3 2 Develop Standalone and Linux Software no HW Changes Download and install the logiREF VIDEO ISP EVK reference design
32. ixel alpha blending Embedded image color enhancements brightness contrast hue saturation ARM AMBA AXI4 and AXI4 Lite bus compliant Available for Xilinx Vivado IP Integrator and ISE XPS implementation tools More info http Awww logicbricks com Products logiWIN aspx Datasheet htto www logicbricks com Documentation Datasheets IP logiIWIN_ hds pdf 2 3 4 logiCLK Programmable Clock Generator The logiCLK is a programmable clock generator IP core featuring twelve independent and fully configurable clock outputs While six clock outputs can be fixed by generic parameters prior to the implementation the other six clock outputs can be either fixed by generics or dynamically reconfigured in a SE working device Supports Xilinx Zyng 7000 All Programmable SoC 7 series and Spartan 6 FPGAs Provides 12 independent clock outputs that can be configured by generic parameters 6 outputs can be dynamically configured through the DRP interface 6 outputs can be configured by generics only Input clock frequency range Spartan 6 19 540 MHz 7 series 19 1066 MHz Output clocks frequency range Spartan 6 3 125 400 MHz 7 series 6 25 741 MHz Configurable ARM AMBA AXI4 Lite and CoreConnect PLBv46 compliant registers interface Software support for Linux and Microsoft Windows Embedded Compact operating systems Available for Xilinx Vivado IP Integrator and ISE Platform Studio Depending on the used device
33. logiREF VIDEO ISP EVK Xylon logicBRICKS Image Signal Processing ISP Reference Design for Xilinx Zynq 7000 AP SoC based MicroZed Embedded Vison Development Kit User s Manual Version 1 00 a logiREF VIDEO ISP EVK_v1_00_a docx logiREF VIDEO ISP EVK mmm 3 ISP Reference Design Alen Designed by XYLON User s Manual VW December 15 2014 Version v1 00 a Ty pats Designed by XYLON All rights reserved This manual may not be reproduced or utilized without the prior written permission issued by Xylon Copyright Xylon doo logicBRICKS is a registered Xylon trademark All other trademarks and registered trademarks are the property of their respective owners This publication has been carefully checked for accuracy However Xylon does not assume any responsibility for the contents or use of any product described herein Xylon reserves the right to make any changes to product without further notice Our customers should ensure to take appropriate action so that their use of our products does not infringe upon any patents Copyright Xylon d o o 2014 All Rights Reserved Page 2 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Sulon Designed by XYLON User s Manual December 15 2014 Version v1 00 a 1 INTRODUCTION NN 5 1 1 HARDWARE DA Ne 6 1 2 BRSzeCHNer WEE 7 n WE Eve Desn E 7 Neu OT a 7 e tegt 7 1 3 USAGE leet 7 1 3 1 Quick Evaluation with no HW and or SW Changes
34. n Board Solutions logicBRICKS Your account has been created Check your mai for dotats staut acthrating your account Downloads Documentation News amp Events Ce Figure 11 Registration Process Step 3 Copyright Xylon d o o 2014 All Rights Reserved Step 1 If you are the registered logicBRICKS user please type in your Username and Password Unregistered users should click on the Register button which will open the registration form Step 2 Unregistered users should fill in the registration form from the Fig 10 Please take care on required form s fields Your Username is an actual e mail account used for communication with Xylon logicBRICKS Xylon accepts only valid company e mail accounts Step 3 As soon as your registration form gets accepted by Xylon you get a confirmation message Please check your e mail to find a link that activates your logicBRICKS account If you do not get the confirmation message in several minutes please check your Spam Filter or Junk Mail Folder If you have not received the confirmation message please contact Xylon support Page 17 of 38 th logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual Sulon December 15 2014 Version v1 00 a ang dE Home Abee an Products Markets Solutions togicBICKS Downloads Documentation News amp Events Activate Account apn mn Home k for ir e y Ti About
35. of an input video stream and collects video Statistics data for use in video control algorithms i e Auto White Balance AWB and Auto Exposure AE Supports up to 1080p60 1920x1080 60fps and up to 7680x7680 at lower refresh rates Supports video input formats Raw Bayer RGB and YCbCr color depth 8 10 12 bit Video input and output are ARM AMBA AX1 4 Stream protocol compliant Optional registers are AMBA AX14 Lite protocol compliant Parametrical VHDL design that allows tuning of slice consumption and features set Prepackaged for Xilinx Vivado Design Suite and fully controllable through the IP Integrator GUI interface Evaluation IP core available online and the bit accurate C model for evaluations available on request P deliverables include the software driver documentation and technical support Available fee based license extension for the AWB amp AE libraries which are verified with the logilSP IP core More info http Awww logicbricks com Products logiISP aspx Datasheet hitp www logicbricks com Documentation Datasheets IP logilSP_hds pdf Copyright Xylon d o o 2014 All Rights Reserved Page 11 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual Sulon December 15 2014 Version v1 00 a 2 3 2 logiCVC ML Compact Multilayer Video Controller The logiCVC ML IP core is an advanced display graphics controller for LCD and CRI displays which enables an easy video and graphics integ
36. otalling 1GB of random access memory The memory is connected to the hard memory controller in the Zyng 7000 AP SoC Processor Subsystem PS The logiCVC ML Compact Multilayer Video Controller IP core drives a common PC monitor through the ADV7511 High Definition Multimedia Interface HDMI transmitter available on the MicroZed Embedded Vision Carrier Card Kit The logiCVC ML automatically handles the full HD graphics background layer and the live video overlay The demo GUI has been implemented by the Qt cross platform application framework Copyright Xylon d o o 2014 All Rights Reserved Page 27 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual E December 15 2014 Version v1 00 a 5 1 Design Customization The provided reference design can be customized in different ways Please note that any changes in the provided reference design require evaluation IP licenses for logicBRICKS IP cores The licensing process is described in the chapter 4 GETTING LOGICBRICKS EVALUATION LICENSES Possible design changes include Change logicBRICKS IP settings i e logilSP pipeline configuration in order to fit the application requirements and reduce programmable logic utilization number of graphics layers controlled by the logiCVC ML display controller IP core etc Add or remove logicBRICKS IP cores i e add graphics accelerators to speed up the GUI interface and offload the processing system
37. r use only in conjunction with Xylon FPGA IP cores products Use of the Software in conjunction with non Xylon FPGA IP cores or component products is not licensed hereunder Subject to the terms of this Agreement Xylon grants to You a nonexclusive nontransferable license under Xylon s copyrights to use modify and copy Software internally for evaluation purposes You may not reverse compile disassemble or otherwise reverse engineer the Software You may not copy modify rent sell distribute or transfer any part of the Software except as provided in this Agreement and you agree to prevent unauthorized copying of the Software Except as expressly stated in this Agreement no license or right is granted to You directly or by implication inducement estoppel or otherwise Xylon shall have the right to inspect or have an independent auditor inspect Your relevant records to verify Your compliance with the terms and conditions of this Agreement with a prior written notice of ten 10 days CONFIDENTIALITY You shall not disclose the terms or existence of this Agreement or use Xylon s name in any publications advertisements or other announcements without Xylon s prior written consent OWNERSHIP OF SOFTWARE AND COPYRIGHTS Title to all copies of the Software remains with Xylon ei Figure 15 Installation Process Step gt H Xylon logiREF ZGPU ZED_120919 el SI Designed by XYLON Pack installation progres
38. ration into embedded systems with Xilinx Zynq 7000 All Programmable SoC and FPGAs This IP core is the cornerstone of all 2D and 3D GPUs Though its main function is to provide flexible display control it also includes hardware acceleration functions three types of aloha blending panning buffering of multiple frames etc Supports all Xilinx FPGA families Supports LCD and CRT displays easily tailored for special display types 64x1 to 2048x2048 display resolutions Available SW drivers for Linux Android QNX and Microsoft Windows Embedded Compact OS Support for higher display resolutions available on request Supports up to 5 layers the last one configurable as a background layer Configurable layers size position and offset Alpha blending and Color keyed transparency Pixel layer or Color Lookup Table CLUT alpha blending mode can be independently set for each layer Packed pixel layer memory organization RGB 8 bpp 8 bpp using CLUT 16bpp Hi color RGB 565 and True color 24bpp YCbCr 16bpp 4 2 2 and 24bpp 4 4 4 Configurable CoreConnect PLBv4 6 Xylon XMB or ARM AMBA AXI4 memory interface data width 32 64 or 128 Programmable layer memory base address and stride Simple programming due to small number of control registers Support for multiple output formats Parallel display data bus RGB 12x2 bit 15 bit 16 bit 18 bit or 24 bit YCbCr 4 4 4 or 4 2 2 output format Digital Video ITU 656 PAL and NTSC LVDS ou
39. rce clock for logiC VC ML video controller and for the video output It s frequency is by default set to 148 5 MHz due to full HD display resolution 1920x1080 and refresh rate 60 Hz 1080p Copyright Xylon d o o 2014 All Rights Reserved Page 29 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a CLKO CLK1 and CLK2 outputs frequencies can be changed only prior to the design implementation and are fixed during device s operation The CLKO output clock is used as a source clock for AX14 Lite interfaces in the programmable logic such as register interfaces and interconnects Its frequency is set to 100 MHz The CLK1 output clock is used as a source clock for logiCVC ML s AXI4 memory interface and interconnect Its frequency is set to 150 MHz The CLK2 output clock is used as a source clock for logilSP video path which comprises Parallel to AxX1 4 Stream converter logilSP AXIl4 Stream to parallel converter and logiWIN Its frequency is set to 120 MHz Besides above mentioned clocks few more are needed by the Vita receiver IP core provided by Avnet 27 MHz and 108 MHz To generate those clocks the Clock wizard is used as shown by Figure 31 Ratio between those clocks is 1 4 The Clock wizard is sourced by 200 MHz clock generated in the Processing System PS and supplied to the FOLK_CLK1 PS output 108 MHz FCLK_CLK1 200 MHz 27 MHz
40. rchase from Alliance Partner Name Multilayer Video Controller Interfaces AXI4 Description The logiCVC ML Compact Multilayer Video Controller is a graphics video display controller optimized for Xilinx Zynq 7000 All Programmable AP SoC and FPGA devices logiCVC ML rir provides all the necessary control signals to interface directly with LCD and other flat panel displays A wide veriaty of LCD doisplay types is supported Its compact size low slice coi configuration by VHDL code parameterization Its functions indude refreshing the display image by reading the video memory and converting the read data into a data stream accap for the display Multilayer support provides alpha blending transparency hardware cursors and fast scrolling by using low CPU processing power By means of an external video digi composite video devices and CRT displays Additionally Digital Visual Interface DVI compliant displays can be controlled by using the appropriate devices http www xilinx com products intellectual property logiCVC ML htm Figure 5 logicBRICKS IP Cores in the Vivado IP Catalog logilSP IP Core is provided in the Vivado compatible version only Please visit our web site or contact Xylon to learn more about the tools compatibility of the specific logicBRICKS IP core Copyright Xylon d o o 2014 All Rights Reserved Page 9 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual December 15 2
41. rence Designs Linux Installation aspx Copyright Xylon d o o 2014 All Rights Reserved Page 18 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a lf you agree with the conditions from the evaluation licenses click NEXT and select the installation path for your logicBRICKS reference design Figure 16 The installation process takes several minutes It generates the directory structure described in the paragraph 3 3 Directory Structure 3 2 1 Filesystem permissions of the installed directory Windows 7 The reference design installed in the default path C Program Files xylon will inherit read only filesystem permissions from the parent directory This will block you in opening the hardware project file in Xilinx Vivado tools Therefore it is necessary to change the filesystem permissions for the current user to Full control preferably To change the user permissions for C Program Files xylon directory and all of it s subdirectories right click on the C Program Files xylon directory and select Properties Under Security tab select Edit Select Users group in the list and check Full control checkbox in the Allow column Copyright Xylon d o o 2014 All Rights Reserved Page 19 of 38 logiREF VIDEO ISP EVK ISP Reference Design mm Designed by XYLON December 15 2014 Wl Xylon logiREF ZG
42. s D Users Overall installation progress Figure 17 Installation Process Step A Page 20 of 38 logiREF VIDEO ISP EVK mmm 3 ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 3 3 Directory Structure Figure 19 gives a top level view of the directories and files included with the logiREF VIDEO ISP EVK reference design for the MicroZed Embedded Vision development kit Table 1 explains the purpose of directories kend INSTALLATION ROOT DOC VIVADO HARDWARE SOFTWARE Start html a roject L Eval licenses pdf pre kg DRIVERS Linux logilSP SW files data makeBin Gell logiCLK SW Files as scrivi makeBinSA standalone S et logiCVC SW Files e ready_for_download nE al logiWIN SW Files D w T al logilSP_lu SW Files SDK_workspace E hdl bg SW_SERVICES ui Xyl_oslib Create_project html al Gel Fmc_imageon_sw kg LOGICBRICKS P R Readme html Fmc_imageon_vita_receiver SW files Xyl_oslib_lu Fmc_iic_s w lib logiCVC ML IP XACT core Ge O logilSP IP XACT core cal logWIN IP XACT core oo logiCLK IP XACT core L Gama AVNET_EMBV_CORES Figure 19 Installed Reference Design The Directory Structure Copyright Xylon d o o 2014 All Rights Reserved Page 21 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference De
43. sign Sulon Designed by XYLON User s Manual December 15 2014 Version v1 00 a Directory Installation Root This directory contains the start him page the jump start navigation page through the reference design Vivado This directory contains the complete Vivado project and files necessary for regenerating project from TCL scripts Data hp433ab Sres Scripts fpga create project html Instructions for building Vivado project from scratch Hardware RN Drivers Standalone bare metal and linux userspace drivers for logicBRICKS IP cores with documentation and examples and Avnet s standalone driver for Vita Receiver logucbracks Ke Evaluation logicBRICKS IP XACT cores zip archives logicbricks src Evaluation logicBRICKS IP XACT extracted IP cores IP cores User s Manuals are stored In doc subdirectories Logicbricks if logicBRICKS IPs interface definitions for Vivado avnet_embv_cores Avnet provided IP cores Sw_services xyl_oslib Xylon OS abstraction library for Linux applications and Avnet IIC libraries Software readme html Navigation page through the software files and instructions for building binaries Linux kernel Linux kernel and device tree configuration files Linux libraries a makeBinSA ready_for_download SDK_workspace Xilinx SDK workspace folder for building of bare metal logilSP application and linux userspace logilSP driver Table 1 Explanation of Directories in logiREF VIDEO I
44. tput format 3 or 4 data pairs plus clock Camera link output format 4 data pairs plus clock DVI output format Supports synchronization to external parallel input Versatile and programmable sync signals timing Double triple buffering enables flicker free reproduction Display power on sequencing control signals Parametrical VHDL design that allows tuning of slice consumption and features set Available for Xilinx Vivado IP Integrator and ISE XPS implementation tools More info http Avww logicbricks com Products logiC VC ML aspx Datasheet http www logicbricks com Documentation Datasheets IP logiC VC ML_hds pdf Copyright Xylon d o o 2014 All Rights Reserved Page 12 of 38 rh logiREF VIDEO ISP EVK mmm ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 2 3 3 logiWIN Versatile Video Input The logiWIN IP core enables easy implementation of video frame grabbers Input video can be decoded real time scaled de interlaced cropped anti aliased positioned on the screen Supports Xilinx Zyng 7000 AP SoC and FPGAs Maximum input and output resolutions 2048x2048 Supports different input interface standards ITU656 and 1TU1120 PAL and NTSC RGB YUV 4 2 2 Built in YCrCb to RGB YUV to RGB and RGB to YCrCb converters Real time scale up to 64x and scale down to 16x lossless scaling down to 2x or 4x in the cascade scaling mode Supports video de interlacing cropping positioning p
45. us Xylon logicBRICKS IFN f Ind FPGA Produc ts i Graphics tor Xilinx Zynq 7000 gt Markets SS Click io gat reference Gesigns for fra 20702 Evatuction Board io gt Step 4 Click on the logicBRICKS web account activation link in the received e mail and you will get the confirmation status message Please login to proceed Step 5 As soon as you select an appropriate logicBRICKS reference design and installer for your operating system from the Downloads Navigation Page link bellow you will get an e mail with the download link for the selected reference design installation http www logicbricks com logicBRICKS Ref erence logicBRICKS Design Xylon Reference Designs Navigation Page aspx Figure 13 Registration Process Step 5 3 2 Installation Process Installation process is quick and easy Each logicBRICKS reference design can be downloaded as a cross platform Java JAR self extracting installer Please make sure that you have a copy of the JRE Java Runtime Environment version 6 or higher on your system to run Java applications and applets Double click on the installer s icon to run the self installing executable to unpack and install the reference design on your PC At the beginning you will be requested to accept two evaluation licenses Figure 14 and Figure 15 For installation in Linux OS please follow instructions http Awww logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Refe
46. val IP Core tab in the left menu Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News Events MylogicBRICKS My logicBRICKS i Gi hi id SoS My logicBRICKS video for xine er Zynq 7000 ee EPP and FPGAs View Data D IP Cores and Design Services for Xilinx All Programmable e emm 7 o Change Password Gemen yideo nnen K Request Eval IP Core Processing Analytics L IP Core Activation SS eee oy Sa Create Case d Situational Awareness Subscribe to Newsletter lt Your FPGA Partner in Smarter Vision Downloads Welcome to logicBRICKS Registered Users Section Within this section you can z Quickly get instructions on how to download install or purchase A Quick Info KI logicBRICKS products We View Data View and update your user data logicBRICKS profile logicBRICKS IP Cores Change Password Change your logicBRICKS password cover it alll Knowledge Base Access and search the knowledge base Request an evaluation version of logicBRICKS IP core and check if it Request Eval IP Core fits to your needs prior to purchase Both pay for and evaluation IP www logicbricks com cores have the same licensing procedure Activate your purchased IP core s license key The key is valid for a IP Core Activation single PC or Sun workstation 1 development seat and indentified by unique MAC MS Windows or Linux or Sun HostiD Solaris Create a case for
47. w Please check Xylon s Video Gallery web pages htip www logicbricks com logicBRICKS IP Library Video Galleries logicBRICKS Demos xXilinx ISP Processing aspx to preview the Image Signal Processing ISP demo provided with the logiREF VIDEO ISP EVK installation for your MicroZed EVK development kit Copyright Xylon d o o 2014 All Rights Reserved Page 8 of 38 ni logiREF VIDEO ISP EVK mmm 3 ISP Reference Design Designed by XYLON User s Manual December 15 2014 Version v1 00 a 2 LOGICBRICKS IP CORES 2 1 About logicBRICKS IP Library Xylon s logicBRICKS IP core library provides IP cores optimized for Xilinx FPGAs and Zynq 7000 All Programmable SoC logicBRICKS IP cores shorten development time and enable fast design of complex embedded systems based on Xilinx All Programmable devices The key features of the logicBRICKS IP cores are Compatibility with the Xilinx Vivado and ISE Design Suites logicBRICKS can be used in same ways as Xilinx IP cores and require no skills beyond general tools Knowledge IP core feature sets and programmable logic utilization can be setup through Xilinx tool GUI Each logicBRICKS IP core comes with the extensive documentation reference design examples and can be evaluated on reference hardware platforms Xylon provides evaluation logicBRICKS IP cores to enable risk free evaluation prior to purchase Broad software support from bare metal software drivers to standard soft
48. wW ould like to use your o evaluation core with the SE E development kit E Figure 23 Step 1 Licensing logicBRICKS Evaluation IP Cores Step 3 Evaluation logicBRICKS IP licenses are tied to your Ethernet MAC address or Sun Host ID Figure 24 and can be used on a single working station only Fill in this address and click on the Request License Key button You should get the confirmation message Figure 25 If you do not get the confirmation message please contact Xylon technical support support logicbricks com Copyright Xylon d o o 2014 All Rights Reserved Page 24 of 38 th logiREF VIDEO ISP EVK mmm ISP Reference Design User s Manual E December 15 2014 Version v1 00 a Designed by XYLON Home About us Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS eer Obtain Evaluation License Change Password ana lex D Xylon logicBRICKS SR E ve A Graphics for Xilinx Zynq 7000 A Sig WV Click to get reference designs for Xilinx ZC702 Evaluation Board S WY 4 IP Core Activation Create Case Subscribe to Newsletter Downloads MAC Address You will be able to use evaluation license on one development workstation Please enter your Sun Host ID lt i e workstation MAC address for MS Windows and Linux 00 00 00 00 00 00 platforms or Sun Host for Solaris platforms Figure
49. ware drivers for different operating systems OS Xylon assures skilled technical support E Project Summary X amp Automotive amp Industrial gt AXI Infrastructure BaseIP HL Basic Elements H LC Communication amp Networking Debug amp Verification Digital Signal Processing gt Embedded Processing gt FPGA Features and Design Math Functions Memories amp Storage Elements Standard Bus Interfaces H gt Video amp Image Processing gt e Name e AXI4 Status License VLNV a Alliance Partners Xylon 4 2D Graphics Accelerator Bit Block Transfer AXI4 Production Induded logicbricks com logicbricks logibitblt 0 0 Ze 3 Audio 12S Transmitter Receiver AXI4 Production Induded logicbricks com logicbricks logii2s 0 0 S 3 Bitmap 2 5D Graphics Accelerator AXI4 Production Included logicbricks com logicbricks logibmp 0 0 Kb 3 DC Bus Master Controller AXI4 Production Included logicbricks com logicbricks logii2c 0 0 R jE yer Vid Jana Production induded logicbricks com logicbricks logicvc 0 0 3 Perspective Transformation and Lens Correction Image Processor AXI4 AXI4 Stream Production Induded logicbricks com logicbricks logiview 0 0 3 Scalable 3D Graphics Accelerator AXI4 Production Induded logicbricks com logicbricks logi3d 0 0 ol 3 SD Card Host Controller AXI4 Production Induded logicbricks com logicbricks logisdhc 0 0 6 Details i IP available for pu
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